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1

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

SciTech Connect

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

2011-10-20

2

CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging  

Microsoft Academic Search

A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS

Lodovico Ratti; Massimo Caccia; Luigi Gaioni; Alessia Manazza; Massimo Manghisoni; Valerio Re; Gianluca Traversi; Stefano Zucca

2010-01-01

3

High-Q capacitors implemented in a CMOS process for low-power wireless applications  

Microsoft Academic Search

In a foundry 0.8-?m CMOS process, low-cost capacitors with a measured Q factor of around 50 at 3 GHz and high intrinsic capacitance\\/area (~200 nF\\/cm2) were demonstrated. When extrapolated to 900 MHz, the Q factor is greater than 100. The capacitors use a poly-to-n-well MOS structure which has been commonly dismissed for high-Q applications due to the high n-well sheet

Chih-Ming Hung; Yo-Chuol Ho; I-Chang Wu

1998-01-01

4

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented

Christian Enz; Manfred Punzenberger; Dominique Python

1999-01-01

5

Process Compensated CMOS Temperature Sensor for Microprocessor Application  

E-print Network

Process Compensated CMOS Temperature Sensor for Microprocessor Application Yaesuk Jeong and Farrokh consumption is 478uW. I. INTRODUCTION With microprocessors scaling to higher performance and faster speed in the microprocessor to monitor its thermal distribution. Many CMOS based temperature sensors have been reported

Ayazi, Farrokh

6

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage (LV) and low-power (LP) analog signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V

C. C. Enz; M. Punzenberger; D. Python

1997-01-01

7

Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source  

NASA Astrophysics Data System (ADS)

We present a study of radiation effects on MOSFET transistors irradiated with a 60Co source to a total absorbed dose of 1.5 Mrad. The transistor test structures were manufactured using a commercial 150 nm CMOS process and are composed of transistors of different types (NMOS and PMOS), dimensions and insulation from the bulk material by means of deep n-wells. We have observed a degradation of electrical characteristics of both PMOS and NMOS transistors, namely a large increase of the leakage current of the NMOS transistors after irradiation.

Carna, M.; Havranek, M.; Hejtmanek, M.; Janoska, Z.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2014-06-01

8

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability  

Microsoft Academic Search

This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identifi- cation and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature,

Stefano Stanzione; Daniele Puntin; Giuseppe Iannaccone

2011-01-01

9

A single poly EEPROM cell structure for use in standard CMOS processes  

Microsoft Academic Search

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 ?m\\/150 Å standard CMOS logic process showed

Katsuhiko Ohsaki; Noriaki Asamoto; Shunichi Takagaki

1994-01-01

10

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers  

NASA Astrophysics Data System (ADS)

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35??m 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

Cheng, Chao-Lin; Tsai, Ming-Han; Fang, Weileun

2015-02-01

11

Analog CMOS Design for Optical Coherence Tomography Signal Detection and Processing  

Microsoft Academic Search

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The

Wei Xu; David L. Mathine; Jennifer K. Barton

2008-01-01

12

Novel color processing architecture for digital cameras with CMOS image sensors  

Microsoft Academic Search

This paper presents a color processing architecture for digital color cameras utilizing complementary metal oxide semiconductor (CMOS) image sensors. The proposed architecture gives due consideration to the peculiar aspects of CMOS image sensors and the human visual perception related to the particular application of digital color photography. A main difference between the proposed method arid the conventional systems is the

Chaminda Weerasinghe; Wanqing Li; Igor Kharitonenko; Magnus Nilsson; Sue Twelves

2005-01-01

13

Pressure Sensor Monolithically Integrating MEMS and CMOS-LSI with CMOS Compatible ``Back-end-of-line MEMS processes''  

Microsoft Academic Search

Back-end-of-line (BEOL) MEMS processes for a compact, high-precision pressure sensor was developed. A CMOS-LSI-integrated capacitive pressure-sensor was fabricated with a chip size of 0.72 mm2 using developed BEOL MEMS processes. Multi-sensor chip (with a size of 1.7 by 1.9 mm2) which consists of pressure sensor, temperature sensor and high-precision measurement circuits was also fabricated, and precise atmospheric pressure measurement (~

Tsukasa Fujimori; Hideaki Takano; Yuko Hanaoka; Yasushi Goto

2010-01-01

14

Development of a radiation-hard CMOS process  

NASA Technical Reports Server (NTRS)

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Power, W. L.

1983-01-01

15

Process technology for the modular integration of CMOS and polysilicon microstructures  

Microsoft Academic Search

Modular fabrication of polysilicon surface-micromachined structures after completion of a conventional CMOS electronic process is described. Key process steps include tungsten metallization with contact diffusion barriers, LPCVD oxide and nitride passivation of the CMOS, rapid thermal processing for stress-relief annealing of the structural polysilicon film, implementation of a sacrificial spin-on-glass planarization, and the final microstructure release in hydrofluoric acid. Modularity

James M. Bustillo; Gary K. Fedder; Clark T.-C. Nguyen; Roger T. Howe

1994-01-01

16

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

17

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process  

NASA Astrophysics Data System (ADS)

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

2013-04-01

18

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process.  

PubMed

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

19

A novel single-poly floating-gate UV sensor using standard CMOS process  

NASA Astrophysics Data System (ADS)

This paper proposes a novel single-poly floating gate (FG) UV sensor in standard CMOS process. The sensor cell is based on PMOS FG and only adopts four transistors including sensitive component and readout amplifier. The architecture is compact and feasible for future high density array chip implementation. A theoretical analysis of sensor sensitivity is described in detail. As the sensor is compatible with standard single poly CMOS process, it has the merits of low cost, more sensitive, and be integrated with signal processing system. A prototype chip is manufactured in a 0.18?m single-poly standard CMOS logic process. The tested results indicate that the sensor is sensitive to the incoming UV irradiation.

Li, Guike; Li, Yunlong; Feng, Peng; Wu, Nanjian

2009-07-01

20

Silicon-on-Nothing (SON)-an innovative process for advanced CMOS  

Microsoft Academic Search

A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally

Malgorzata Jurczak; Thomas Skotnicki; M. Paoli; B. Tormen; J. Martins; Jorge Luis Regolini; Didier Dutartre; Pascal Ribot; D. Lenoble; Roland Pantel; Stephanie Monfray

2000-01-01

21

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS  

Microsoft Academic Search

The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

Martin von Arx; Oliver Paul; Henry Baltes

2000-01-01

22

Sensors and Actuators A 109 (2003) 102113 Low-cost uncooled infrared detectors in CMOS process  

E-print Network

Sensors and Actuators A 109 (2003) 102­113 Low-cost uncooled infrared detectors in CMOS process the implementation and comparison of two low-cost uncooled infrared microbolometer detectors that can be imple type detector is better for low-cost large format infrared detector arrays, since it has a superior

Akin, Tayfun

23

Gamma radiation damage study of 0.18 µm process CMOS image sensors  

NASA Astrophysics Data System (ADS)

A 0.18 ?m process CMOS image sensor has recently been developed by e2v technologies plc. with a 0.5 megapixel imaging area consisting of 6 × 6 ?m 5T pixels. The sensor is able to provide high performance in a diverse range of applications including machine vision and medical imaging, offering good low-light performance at a video rate of up to 60 fps. The CMOS sensor has desirable characteristics which make it appealing for a number of space applications. Following on from previous tests of the radiation hardness of the image sensors to proton radiation, in which the increase in dark-current and appearance of bright and RTS pixels was quantified, the sensors have now been subjected to a dose of gamma radiation. Knowledge of the performance after irradiation is important to judge suitability for space applications and radiation sensitive medical imaging applications. This knowledge will also enable image correction to mitigate the effects and allow for future CMOS devices to be designed to improve upon the findings in this paper. One device was irradiated to destruction after 120 krad(Si) while biased, and four other devices were irradiated between 5 and 20 krad(Si) while biased. This paper explores the resulting radiation damage effects on the CMOS image sensor such as increased dark current, and a central brightening effect, and discusses the implications for use of the sensor in space applications.

Dryer, Ben; Holland, Andrew; Murray, N. J.; Jerram, Paul; Robbins, Mark; Burt, David

2010-07-01

24

Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing  

Microsoft Academic Search

A monolithic tin oxide (SnO2) gas sensor realized by commercial CMOS foundry fabrication (MOSIS) and postfabrication processing techniques is reported. The device is composed of a sensing film that is sputter-deposited on a silicon micromachined hotplate. The fabrication technique requires no masking and utilizes in situ process control and monitoring of film resistivity during film growth. Microhotplate temperature is controlled

John S. Suehle; Richard E. Cavicchi; Michael Gaitan; Steve Semancik

1993-01-01

25

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure  

Microsoft Academic Search

In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists of 3 stacked layers which are 100

K. Kiyoyama; K-W Lee; T. Fukushima; H. Naganuma; H. Kobayashi; T. Tanaka; M. Koyanagi

2010-01-01

26

RF-MEMS switching devices using vertical comb-drive actuation in the CMOS process  

Microsoft Academic Search

Radio frequency micro-electro-mechanical system (RF-MEMS) switching devices using vertical comb-drive actuation toward low-voltage actuation, fast response are presented in this paper. The switching devices, which comprise comb-drive electrodes, are actuated entirely by the electrostatic forces applied not only for the down-state but also for the up-state. The cost-effective MEMS process compatible with the complementary metal oxide semiconductor (CMOS) process is

Y. Naito; K. Nakamura; K. Onishi

2010-01-01

27

A BiCMOS 0.8 ?m process with a toolkit for mixed-mode design  

Microsoft Academic Search

A production 0.8-?m BiCMOS process having optional process modules for mixed-mode IC applications is described. Schottky-clamped NPN, isolated NMOS, vertical PNP, and N-channel JFET transistors are among the devices that can be added to the process at little additional cost. Electrical characteristics of the standard BiCMOS and optional devices are discussed. A toolkit composed of these devices gives designers increased

D. Stolfa; R. Reuss; J. Ford; B. Cosentino; D. Monk; F. Shapiro; D. Lamey; C. Dragon

1993-01-01

28

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing  

PubMed Central

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

29

Efficient smart CMOS camera based on FPGAs oriented to embedded image processing.  

PubMed

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L; Espinosa, Felipe; García, Jorge

2011-01-01

30

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array  

PubMed Central

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 ?m CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

31

Respiration Detection Chip With Integrated Temperature-Insensitive MEMS Sensors and CMOS Signal Processing Circuits.  

PubMed

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 ?m CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change. PMID:24956395

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

32

Performance comparison of pH sensors fabricated in a CMOS process  

Microsoft Academic Search

A comparison of performance in three pH-sensitive CHEMFET devices in a standard 1.6 micron CMOS process using aluminum oxide, silicon nitride, and silicon oxide is described. Experimental results compare sensitivity, resolution, and signal-to-noise ratio for the three devices across their usable lifetime. The best signal to noise ratio (19.3 dB) occurs with a silicon oxide pH sensitive layer and the

Linda A. Lee; Steve R. Marx; Rachel Yotter; Karl S. Booksh; R. Bruce Darling; Denise M. Wilson

2004-01-01

33

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Woo, D. S.

1977-01-01

34

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors  

Microsoft Academic Search

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-?m single-poly n-well CMOS process.

Christian Menolfi; Qiuting Huang

1997-01-01

35

Low-noise silicon avalanche photodiodes fabricated in conventional CMOS technologies  

Microsoft Academic Search

We present a simple design technique that allows the fabrication of UV\\/blue-selective avalanche photodiodes in a conventional CMOS process. The photodiodes are fabricated in a twin tub 0.8 ?m CMOS technology. An efficient guard-ring structure is created using the lateral diffusion of two n-well regions separated by a gap of 0.6 ?m. When operated at a multiplication gain of 20,

Alexis Rochas; Alexandre R. Pauchard; P.-A. Besse; D. Pantic; Z. Prijic; R. S. Popovic

2002-01-01

36

Lithography with infrared illumination alignment for advanced BiCMOS backside processing  

NASA Astrophysics Data System (ADS)

Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP's 0.25/0.13 ?m high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVG®NT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 ?m across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG®40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP's 0.25/0.13 ?m SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

Kulse, P.; Schulz, K.; Behrendt, U.; Wietstruck, M.; Kaynak, M.; Marschmeyer, S.; Tillack, B.

2014-10-01

37

RF-MEMS switching devices using vertical comb-drive actuation in the CMOS process  

NASA Astrophysics Data System (ADS)

Radio frequency micro-electro-mechanical system (RF-MEMS) switching devices using vertical comb-drive actuation toward low-voltage actuation, fast response are presented in this paper. The switching devices, which comprise comb-drive electrodes, are actuated entirely by the electrostatic forces applied not only for the down-state but also for the up-state. The cost-effective MEMS process compatible with the complementary metal oxide semiconductor (CMOS) process is presented in this paper as well. The fabrication process is composed by adapting the CMOS 0.18 µm back end of line (BEOL) process on 200 mm wafers. The MEMS process in the CMOS process enables the realization of passive devices integrated with active devices, which is effective for size and cost reduction. Two metal interconnection layers in the BEOL process are used for the MEMS process. Interconnection aluminum and inter-layer dielectric tetraethoxysilane (TEOS) are used as MEMS structural material and sacrificial material, respectively. The chemical mechanical polishing (CMP) process is implemented to planarize the sacrificial material surface. The structures were fabricated using a simple low-cost two-mask process. The characteristics of switching capacitors, C-V, RF performance, switching speed and continuous drive cycles are measured on the fabricated devices. The capacitance ratio for the down-state/up-state is Cdown/Cup = 5.4. The characteristics of switching speed response/actuation voltage in the down-state and up-state are 4.5 µs/5 V and 8.0 µs/5 V, respectively. The switching speed is stable up to 107 cycles in spite of the fact that the unipolar voltage speed is stable up to 107 cycles.

Naito, Y.; Nakamura, K.; Onishi, K.

2010-04-01

38

High-speed bipolar phototransistors in a 180 nm CMOS process  

NASA Astrophysics Data System (ADS)

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 ?m2 and 100×100 ?m2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p- epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Kostov, P.; Gaberl, W.; Zimmermann, H.

2013-03-01

39

Photo-Spectrometer Realized In A Standard Cmos Ic Process  

DOEpatents

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Simpson, Michael L. (Knoxville, TN); Ericson, M. Nance (Knoxville, TN); Dress, William B. (Knoxville, TN); Jellison, Gerald E. (Oak Ridge, TN); Sitter, Jr., David N. (Tucson, AZ); Wintenberg, Alan L. (Knoxville, TN)

1999-10-12

40

An automated unique tagging system using CMOS process variation  

Microsoft Academic Search

An Automated Unique Tagging System (AUTS) is presented, intended for RFID applications, that generates identification numbers based on random process variations, circumventing the need for non-volatile memories such as EEPROM or Flash. A sense amplifier is used to measure the mismatch in threshold voltage between two identical NMOS devices and generate a 1-bit random output. The AUTS has been fabricated

Brandon L. Dell; Jonathan F. Bolus; Travis N. Blalock

2007-01-01

41

A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration  

PubMed Central

This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-?m 2P4M CMOS process, and a robust resolution of 0.05 °C and dissipation of 25 ?W were achieved at a sample rate of 10 samples/s. An inaccuracy of ?0.35 °C to 1.35 °C was achieved after one-point calibration at temperatures ranging from ?40 °C to 120 °C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

Chen, Chun-Chi; Lin, Yi

2014-01-01

42

A linearity-enhanced time-domain CMOS thermostat with process-variation calibration.  

PubMed

This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-?m 2P4M CMOS process, and a robust resolution of 0.05 °C and dissipation of 25 ?W were achieved at a sample rate of 10 samples/s. An inaccuracy of -0.35 °C to 1.35 °C was achieved after one-point calibration at temperatures ranging from -40 °C to 120 °C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

Chen, Chun-Chi; Lin, Yi

2014-01-01

43

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.

1980-01-01

44

A CMOS Micromachined Capacitive Tactile Sensor With Integrated Readout Circuits and Compensation of Process Variations.  

PubMed

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 ?m CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/?Newton. The overall power dissipation is 132.8 ?W. PMID:25314707

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

45

Multi-channel high-speed CMOS image acquisition and pre-processing system  

NASA Astrophysics Data System (ADS)

A new multi-channel high-speed CMOS image acquisition and pre-processing system is designed to realize the image acquisition, data transmission, time sequential control and simple image processing by high-speed CMOS image sensor. The modular structure design, LVDS and ping-pong cache techniques used during the designed image data acquisition sub-system design ensure the real-time data acquisition and transmission. Furthermore, a new histogram equalization algorithm of adaptive threshold value based on the reassignment of redundant gray level is incorporated in the image preprocessing module of FPGA. The iterative method is used in the course of setting threshold value, and a redundant graylevel is redistributed rationally according to the proportional gray level interval. The over-enhancement of background is restrained and the feasibility of mergence of foreground details is reduced. The experimental certificates show that the system can be used to realize the image acquisition, transmission, memory and pre-processing to 590MPixels/s data size, and make for the design and realization of the subsequent system.

Sun, Chun-feng; Yuan, Feng; Ding, Zhen-liang

2008-10-01

46

Abstract--A fully CMOS-compatible process, based on silicon epitaxial deposition from physical vapour-deposited amorphous  

E-print Network

1 Abstract--A fully CMOS-compatible process, based on silicon epitaxial deposition from physical vapour-deposited amorphous Si (-Si) through aluminium, was recently proposed. This technique has been integration of SPE-Si modules into the silicon-on- glass (SOG) processes. Index Terms--Al-doping, elevated

Technische Universiteit Delft

47

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process  

NASA Astrophysics Data System (ADS)

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

Ma, Xiao-Hua; Hao, Yue; Sun, Bao-Gang; Gao, Hai-Xia; Ren, Hong-Xia; Zhang, Jin-Cheng; Zhang, Jin-Feng; Zhang, Xiao-Ju; Zhang, Wei-Dong

2006-01-01

48

An RF LDMOS with excellent efficiency and ruggedness based on a modified CMOS process  

NASA Astrophysics Data System (ADS)

Two types of RF LDMOS devices, specified for application in the driver stage and output stage of a power amplifier, are designed based on a modified CMOS process. By optimizing the layout and process, the output capacitance per unit of gate width is as low as 225 fF/mm. The driver stage and output stage devices achieve an output power of 44 W with a PAE of 82% and 230 W with a PAE of 72.3%, respectively (P3dB compression) at 1 GHz. Both devices are capable of withstanding extremely severe ruggedness tests without any performance degradation. These tests are 3-5 dB overdrive, 10:1 voltage standing wave ratio mismatch load through all phase angles, and 40% drain overvoltage elevation at a working point of P3dB.

Ting, Yu; Ling, Luo

2013-09-01

49

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

50

Micro ethanol sensors with a heater fabricated using the commercial 0.18 ?m CMOS process.  

PubMed

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

51

CMOS foundry implementation of Schottky diodes for RF detection  

Microsoft Academic Search

Schottky diodes for RF power measurement were designed and fabricated using a commercial n-well CMOS foundry process through the MOSIS service. The Schottky diodes are implemented by modifying the SCMOS technology file of the public-domain graphics layout editor, MAGIC, or by explicitly implementing the appropriate CIF layers. The modifications allow direct contact of first-layer metal to the low-doped substrate. Current-voltage

Veljko MilanoviC; Michael Gaitan; Janet C. Marshall; Mona E. Zaghloul

1996-01-01

52

Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study  

E-print Network

is considered as the objective optimization function with the area overhead as constraint. Extensive Monte Carlo variations has been considered. Index Terms-- Nano-CMOS, Process Variation, Monte Carlo I. INTRODUCTION that early layout-parasitic information, designers rely mostly on experience. If a design is understood well

Mohanty, Saraju P.

53

Abstract--The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to  

E-print Network

Abstract-- The energy efficiency of a CMOS architecture processing dynamic workloads directly efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS densities, and "green" computing initiatives have prioritized energy efficiency as a first class system

Calhoun, Benton H.

54

Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor  

NASA Astrophysics Data System (ADS)

This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

2013-09-01

55

A discrete time quad-band GSM\\/GPRS receiver in a 90nm digital CMOS process  

Microsoft Academic Search

We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing

K. Muhammad; Y. C. Ho; T. Mayhugh; C. M. Hung; T. Jung; I. Elahi; C. Lin; I. Deng; C. Fernando; J. Wallberg; S. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; M. C. Lee; R. B. Staszewski; K. Maggio

2005-01-01

56

Process techniques of charge transfer time reduction for high speed CMOS image sensors  

NASA Astrophysics Data System (ADS)

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 × 64 pixels was designed and implemented in the 0.18 ?m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 ?s is achieved and 31% of image lag was reduced by using the proposed process techniques.

Zhongxiang, Cao; Quanliang, Li; Ye, Han; Qi, Qin; Peng, Feng; Liyuan, Liu; Nanjian, Wu

2014-11-01

57

Optimisation of a Geiger mode avalanche photodiode imaging pixel based on a hybrid bulk SOI CMOS process  

NASA Astrophysics Data System (ADS)

Single photon detection has a wide variety of scientific and industrial applications including optical time domain reflectometry, astronomy, spectroscopy, defect monitoring of Complementary Metal Oxide Semiconductor (CMOS) circuits, fluorescence lifetime measurement and imaging. In imaging applications, the dead time is the time during which the detector is inhibited after a photon has been detected. This is a limiting factor on the dynamic range of the pixel. The rate of photon detection will saturate if the dead time is too large. Time constants generated by Metal Oxide Semiconductor (MOS) transistor bulk and sidewall capacitances adversely affect the dead time of pixels developed in conventional CMOS technology. In this paper, a novel imaging pixel configuration based on a Geiger Mode Avalanche Photodiode (GMAP) and fabricated using a dedicated hybrid bulk Silicon On Insulator (SOI) CMOS process is presented. The GMAP is fabricated in the bulk layer and the CMOS circuitry is implemented in the upper SOI layers. As a result, bulk and sidewall capacitance effects are significantly reduced. As both the diode and the CMOS transistors are on the same wafer there is a reduction in pixel area and an additional reduction in the parasitic capacitance effects. This leads to a significant improvement in pixel performance. Pixels incorporating 5 micron and 10 micron diameter GMAPs have been simulated. The circuits were optimised with a view to maximising the photon count rate. Results show a significant improvement in the dead time with values of 14 nanoseconds and 15 nanoseconds being observed for the 5 micron and 10 micron GMAPs respectively.

Coakley, Niall G.; Moloney, Aoife M.; Schwarzbacher, Andreas T.

2007-10-01

58

Monolithic electronic-photonic integration in state-of-the-art CMOS processes  

E-print Network

As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

Orcutt, Jason S. (Jason Scott)

2012-01-01

59

Current mode integrators and their applications in low-voltage high frequency CMOS signal processing  

E-print Network

Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented.. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve...

Smith, Sterling Lane

1993-01-01

60

UltraSensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process  

Microsoft Academic Search

Capacitive measurement of very small displacement of nano-electro-mechanical systems (NEMS) presents some issues that are discussed in this article. It is shown that performance is fairly improved when integrating on a same die the NEMS and CMOS electronics. As an initial step toward full integration, an in-plane suspended gate MOSFET (SGMOSFET) compatible with a front-end CMOS has been developed. The

Eric Colinet; CÉdric Durand; Laurent Duraffourg; Patrick Audebert; Guillaume Dumas; Fabrice Casset; Eric Ollier; Pascal Ancey; Jean-FranÇois Carpentier; Lionel Buchaillot; Adrian M. Ionescu

2009-01-01

61

Design and implementation of non-linear image processing functions for CMOS image sensor  

NASA Astrophysics Data System (ADS)

Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 64×64 pixels image sensor built in a standard CMOS Technology 0.35 ?m including non-linear image processing. The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 2×2 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 40×40 mu m. The total area of the 64×64 pixels is 12.5mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (10K frames per second), minima/maxima calculations in less then one ms.

Musa, Purnawarman; Sudiro, Sunny A.; Wibowo, Eri P.; Harmanto, Suryadi; Paindavoine, Michel

2012-11-01

62

The First Fully Integrated Quad-Band GSM\\/GPRS Receiver in a 90-nm Digital CMOS Process  

Microsoft Academic Search

We present the receiver in the first single-chip GSM\\/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive

Khurram Muhammad; Yo-Chuol Ho; Terry L. Mayhugh; Chih-Ming Hung; T. Jung; Imtinan Elahi; Charles Lin; Irene Deng; C. Fernando; J. L. Wallberg; S. K. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; Meng-Chang Lee; Roman Staszewski; K. Maggio

2006-01-01

63

Timing design and image processing of CMOS sensor LUPA-4000 based on FPGA  

NASA Astrophysics Data System (ADS)

This article describes a method of the timing sequence design for CMOS image sensor LUPA-4000. A FPGA based imaging system with the function of adjustable integration time, multiple-slope integration, parallel integration an reading, windowing readout has been designed. This design can satisfy the frequency of 66M limit frequency of LUPA-4000 and 20 frames of a second. As the fixed noise of LUPA-4000 is aloud and the image is not clear, an efficient real-time image processing algorithm is also described in this paper. First a black image should be acquired as the fixed noise image. The real-time images can be send out after subtracting the noise image. This method can effectively eliminate the fixed noise o f the image, as the same time, the original image information has been maintained in the maximum degree. The test experiments on FPGA shows this design can drive LUPA-4000 working properly. Also this design takes full advantage of the accessibility features of the device, which provides a wider dynamic range and more flexible application of the device. The image sensor driven by this design improves imaging quality, which can be used for space exploration, especially for small space dynamic target tracking.

Xin, Li

2014-11-01

64

Designing a Ring-VCO for RFID Transponders in 0.18??m CMOS Process  

PubMed Central

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42?GHz operated active RFID transponders compatible with IEEE 802.11?b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18??m process is adopted for designing the circuit with 1.5?V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54?GHz and dissipates 2.47?mW of power. It exhibits a phase noise of ?126.62?dBc/Hz at 25?MHz offset from 2.42?GHz carrier frequency. PMID:24587731

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

65

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process  

NASA Astrophysics Data System (ADS)

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 ?m2 and 100 × 100 ?m2. Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

Kostov, P.; Gaberl, W.; Hofbauer, M.; Zimmermann, H.

2012-08-01

66

Design of CMOS-APS smart imagers with mixed signal processing and analysis of their transfer characteristics  

NASA Astrophysics Data System (ADS)

CMOS imagers based on Active Pixel Sensors (APS) are very important among others because of their possible technical innovations leading to ultra-low power image acquisition or efficient on-chip image preprocessing. Implementation of the image processing tasks (focal plane preprocessing and subsequent image processing) can be done effectively only with the consideration of known transfer characteristics of the imager itself. Geometrical Point Spread Function (PSF) depends on the certain geometric shape of active area in the particular design of CMOS APS. In this paper, the concept of Modulation Transfer Function (MTF) analysis is generalized to be applicable to the sampled structures of CMOS APS. Recalling theoretical results, we have analytically derived the detector MTF in the closed form for some special active area shapes. The paper also deals with the method based on pseudorandom image pattern with uniform power spectral density (PSD). This method allows to evaluate (in contrast to other methods) spatially invariant MTF including sampling MTF. It is generally known that a signal acquired by image sensor contains different types of noises. The superposition of these noises produces noise with a Gaussian distribution. The denoising method based on Bayesian estimator for implementation into the smart imager is presented.

Fliegel, Karel; Švihlík, Jan; ?e?ábek, Martin

2006-08-01

67

Compact low noise operational amplifier for a 1.2 micron digital CMOS technology  

Microsoft Academic Search

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 micron digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1\\/f noise and good lateral beta. The fabricated op amp has an area of only 0.211 mm(exp 2) with E(sub

W. Timothy Holman; J. Alvin Connelly

1995-01-01

68

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing  

NASA Astrophysics Data System (ADS)

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

2014-06-01

69

A RF receiver frontend for SC-UWB in a 0.18-?m CMOS process  

NASA Astrophysics Data System (ADS)

A radio frequency (RF) receiver frontend for single-carrier ultra-wideband (SC-UWB) is presented. The front end employs direct-conversion architecture, and consists of a differential low noise amplifier (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The proposed LNA employs source inductively degenerated topology. First, the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S11 is given. Then, a noise figure optimization strategy under gain and power constraints is proposed, with consideration of the integrated gate inductor, the bond-wire inductance, and its variation. The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band, and has two gain modes to obtain a higher receiver dynamic range. The mixer uses a double balanced Gilbert structure. The front end is fabricated in a TSMC 0.18-?m RF CMOS process and occupies an area of 1.43 mm2. In high and low gain modes, the measured maximum conversion gain are 42 dB and 22 dB, input 1 dB compression points are -40 dBm and -20 dBm, and S11 is better than -18 dB and -14.5 dB. The 3 dB IF bandwidth is more than 500 MHz. The double sideband noise figure is 4.7 dB in high gain mode. The total power consumption is 65 mW from a 1.8 V supply.

Rui, Guo; Haiying, Zhang

2012-12-01

70

Packaged X-band Phased-Arrays and High Data-Rate Switching Matrices in Advanced CMOS Processes  

E-print Network

s transimpedance amplifier,” IEEE J. Solid-State Circuits,for CMOS amplifiers,” IEEE J. Solid-State Circuits, vol. 41,amplifier and ESD protection circuit in 0.18-µm CMOS technology,” IEEE J. Solid-State

Shin, Donghyup

71

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process  

NASA Astrophysics Data System (ADS)

This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm2, and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G-1with a standard deviation of 2.5 mV G-1. The measured output noise floor is 354 µG Hz-1/2, corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C-1 below 85 °C.

Tseng, Sheng-Hsiang; S-C Lu, Michael; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

2012-05-01

72

A 60GHz double-balanced homodyne down-converter in 65-nm CMOS process  

Microsoft Academic Search

A fully differential 60 GHz down-converter in 65-nm CMOS technology is presented. The circuit, including the buffers, draws 5 mA from a 1.2 V supply. The measured power conversion gain is 4 dB with an IF 3 dB bandwidth of 1.3 GHz. Measured IIP2 and IIP3 are 16.6 and -6 dBm respectively. The mixer will be part of a 60

Pooyan Sakian; Reza Mahmoudi; Paul van Zeijl; Maarten Lont; Arthur van Roermund

2009-01-01

73

SCR device for ESD protection in sub-micron triple well silicided CMOS processes  

Microsoft Academic Search

A high-holding-low-trigger-voltage-silicon-controlled-rectifier (HHLVTSCR) is fabricated in a sub-micron triple well CMOS technology in complementary nand p-types. The HHLVTSCRs occupy less area than typical electrostatic discharge (ESD) protection devices and the corresponding I-V characteristics are adjustable to different protection requirements. The characteristics of these devices are tuned by the appropriate choice of the internal dimensions and device interconnections. Both n- and

J. A. Salcedo; J. J. Liou; Joseph C. Bernier

2004-01-01

74

Figure 1: Schematic of a combined adaptive body bias and adaptive supply voltage adaptation scheme Process and Reliability Sensors for Nanoscale CMOS  

E-print Network

timing/power analysis) and postsilicon measurements to predict the performance drift due to process Process and Reliability Sensors for Nanoscale CMOS John P. Keane*, Chris H. Kim, Qunzeng Liu**, and Sachin, Hillsboro, OR 97124, USA ** now with LinkedIn Corp., Mountain View, CA 94043, USA Abstract A key component

Sapatnekar, Sachin

75

The 1.2 micron CMOS technology  

NASA Technical Reports Server (NTRS)

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.

1985-01-01

76

An Unassisted Low-Voltage-Trigger ESD Protection Structure in a 0.18-µm CMOS Process without Extra Process Cost  

NASA Astrophysics Data System (ADS)

In order to quickly discharge the electrostatic discharge (ESD) energy, an unassisted low-voltage-trigger ESD protection structure is proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structure. Moreover there is no need to add any extra mask or do any process modification for the new structure. The proposed structure has been verified in foundry's 0.18-µm CMOS process.

Li, Bing; Shan, Yi

77

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

78

A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at  

E-print Network

is the worst thing to happen that cast doubt on all outputs from the server. Since high end serv- ers use many this goal, a new 130nm partially depleted SOI CMOS process is selected. Minimizing the risk of using the new

Koppelman, David M.

79

Design and analysis of a UWB low-noise amplifier in the 0.18 ?m CMOS process  

NASA Astrophysics Data System (ADS)

An ultra-wideband (3.1-10.6 GHz) low-noise amplifier using the 0.18 ?m CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev filers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm2.

Yi, Yang; Zhuo, Gao; Liqiong, Yang; Lingyi, Huang; Weiwu, Hu

2009-01-01

80

Effects of drain-wall in mitigating N-hit single event transient via 45 nm CMOS process  

NASA Astrophysics Data System (ADS)

A three-dimensional (3D) technology computer-aided design (TCAD) simulation in a novel layout technique for N-hit single event transient (SET) mitigation based on drain-wall layout technique is proposed. Numerical simulations of both single-device and mixed-mode show that the proposed layout technique designed with 45 nm CMOS process can efficiently reduce not only charge collection but also SET pulse widths (WSET). What is more, simulations show that impacts caused by part of ion-incidents can be shielded with this novel layout technique. When compared with conventional layout technique and guard drain layout technique, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in effective area.

Y Xu, X.; Xiong, Y.; Tang, M. H.; Xiao, Y. G.; Yan, S. A.; Zhang, W. L.; Zhao, W.; Guo, H. X.; Li, Z.

2015-01-01

81

An advanced 0.8 ?m complementary BiCMOS technology for ultra-high speed circuit performance  

Microsoft Academic Search

An 0.8-?m fully complementary BiCMOS (CBiCMOS) process has been developed which offers superior drive capability and low-voltage performance compared to standard BiCMOS technologies. The CBiCMOS process was developed by the successful integration of a high-performance, poly emitter vertical PNP (Ft=17 GHz, emitter coupled logic gate delay=65 ps) and CMOS transistors (CMOS gate delay=68 ps). A CBiCMOS push-pull ring oscillator has

W. R. Burger; C. Lage; B. Landau; M. DeLong; J. Small

1990-01-01

82

A 1.2 V, 0.1 ?m gate length CMOS technology: design and process issues  

Microsoft Academic Search

CMOS technology is being scaled to sub-0.1 ?m gate length and to power supply (Vdd) of 1.2 V for applications of high density at lower active power than achievable with a 1.5 V-1.8 V CMOS. Many challenges are observed at this technology node including choice of gate dielectric for applications with sub-2.5 nm physical SiO2 gate dielectric (or electrical equivalent),

M. Rodder; S. Hattangady; N. Yu; W. Shiau; P. Nicollian; T. Laaksonen; C. P. Chao; M. Mehrotra; C. Lee; S. Murtaza; S. Aur

1998-01-01

83

A 5.8 GHz MMIC Down-Conversion Mixer for DSRC Receiver using SiGe BiCMOS Process  

Microsoft Academic Search

DSRC (dedicated short range communication) provides high speed radio link between road side equipment and on-board equipment within the narrow communication area. In this paper, a 5.8 GHz MMIC down-conversion mixer for DSRC receiver is designed and fabricated using SiGe BiCMOS process technology. RF\\/LO matching circuits, active-based RF\\/LO input balun circuits, and active-based IF output balun circuit are all integrated

Sang-Heung Lee; Ja-Yol Lee; Sang-Hoon Kim; Hyun-Cheol Bae; Seung-Yun Lee; Jin-Yeong Kang; Bo Woo Kim

2005-01-01

84

The Impact of Gate-Oxide Breakdown on Common-Source Amplifiers With Diode-Connected Active Load in Low-Voltage CMOS Processes  

Microsoft Academic Search

The influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the nonstacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as

Jung-Sheng Chen; Ming-Dou Ker

2007-01-01

85

SPICE macromodel and CMOS emulator for memristors.  

PubMed

In this paper, a new SPICE macromodel and CMOS emulator for memristors are proposed and verified to fit to the memristor's model equation very well in the entire range of memristor's resistance from the RESET state to the SET state. Compared with the memristor's model equation, average percentage errors in the new SPICE macromodel and in the 4-bit CMOS emulator are less than 0.5% and 0.9%, respectively. In addition, the CMOS emulator for memristors which can be implemented by a CMOS circuit will be very useful to design and verify various peripheral circuits for memristor applications particularly when the memristor fabrication process is not ready. PMID:22629985

Jung, Chul-Moon; Jo, Kwan-Hee; Min, Kyeong-Sik

2012-02-01

86

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process  

NASA Technical Reports Server (NTRS)

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

2006-01-01

87

Postfabrication Independent Inductance and Quality Factor Adjustments of On-Chip Inductors by Above-CMOS Processing for Rapid Prototyping of Radio Frequency System on Chips  

NASA Astrophysics Data System (ADS)

The flexible adjustment of on-chip inductor characteristics after a regular complementary metal-oxide-semiconductor (CMOS) fabrication was realized by the “above-CMOSprocessing technology for radio frequency (RF) system-on-a-chip (SoC) rapid prototyping. It is shown that the above-CMOS metal pattern formation in a chip-by-chip manner can both increase and decrease the inductance (L) values of on-chip inductors. It is realized by applying various planar patterns of a metal layer deposited on the passivation layer of the chip. To increase the modification range of the characteristics and to establish an independent L and quality factor (Q) adjustment scheme, we have newly developed a pre-design method and a Q-compensation method. By combining these methods, the effective L and Q values of the on-chip inductors can be independently and arbitrarily modified. The adjustment of the input impedance matching frequency of a low-noise amplifier (LNA) using this scheme has also been demonstrated.

Sasaki, Yuki; Kotani, Koji

2012-04-01

88

Thermoelectric infrared sensors by CMOS technology  

Microsoft Academic Search

The authors report two integrated thermoelectric infrared sensors on thin silicon oxide\\/nitride microstructures realized by industrial CMOS IC technology, followed by one compatible single maskless anisotropic etching step. No additional material is needed to enhance infrared absorption since the passivation layer, as provided by the CMOS process, is sufficient for certain spectral bands. The responsivities are between 12 and 28

Rene Lenggenhager; Henry Baltes; Jon Peer; Martin Forster

1992-01-01

89

A CMOS surface micromachined pressure sensor  

Microsoft Academic Search

A capacitive pressure sensor has been implemented by the industrial standard 0.8?m CMOS (Complementary metal oxide semiconductor) process. The device layout follows the entire set of CMOS IC (Integrated circuit) design rules. The sensing capacitor of the capacitive pressure sensor is composed of the upper metal (metal 2) and the polysilicon layer. The lower metal layer (metal 1) serves as

1999-01-01

90

RF MEMS components using CMOS technology  

Microsoft Academic Search

Recently microelectromechanical systems (MEMS) devices have become an important technology that is used in many applications. We describe post-processing steps of CMOS technology to implement a MEMS structure suitable for RF systems. We describe CMOS-based monolithic MEMS structures suitable for realizing passive RF components operating at frequencies of up to 60 GHz. Examples of RF MEMS components - inductors, switches

Mehmet Ozgur; Mona E. Zaghloul

2001-01-01

91

On-Chip Spatial Image Processing with CMOS Active Pixel Sensors  

E-print Network

connections instead of off-chip wires, which are the only transfer medium between two separated chips by circuit density of processing elements are not sufficient to achieve optimal design with power, speed

Hornsey, Richard

92

Unified P4 (Power-Performance-Process-Parasitic) Fast Optimization of a Nano-CMOS VCO  

E-print Network

analysis, we pro- pose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which offers up to 6.25x time savings over a tradi- tional Monte Carlo (TMC) method. A performance optimization In this paper, we present the design of a P4 (Power-Performance- Process-Parasitic) aware voltage controlled

Mohanty, Saraju P.

93

Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects  

Microsoft Academic Search

The International Technology Roadmap for Semiconductors (ITRS) foresees the production of sub 10 nm gate length devices before 2016. To achieve this, both front- and back-end processing have to face major technological challenges and innovations. Lithography, device isolation, gate stack, shallow junctions, device engineering, high- and low-k dielectrics and interconnect schemes are hot research issues necessitating a global collaboration and

Cor Claeys

2004-01-01

94

Traveling wave electrode design for ultra compact carrier-injection HBT-based electroabsorption modulator in a 130nm BiCMOS process  

NASA Astrophysics Data System (ADS)

Silicon photonic system, integrating photonic and electronic signal processing circuits in low-cost silicon CMOS processes, is a rapidly evolving area of research. The silicon electroabsorption modulator (EAM) is a key photonic device for emerging high capacity telecommunication networks to meet ever growing computing demands. To replace traditional large footprint Mach-Zehnder Interferometer (MZI) type modulators several small footprint modulators are being researched. Carrier-injection modulators can provide large free carrier density change, high modulation efficiency, and compact footprint. The large optical bandwidth and ultra-fast transit times of 130nm HBT devices make the carrierinjection HBT-based EAM (HBT-EAM) a good candidate for ultra-high-speed optical networks. This paper presents the design and 3D full-wave simulation results of a traveling wave electrode (TWE) structure to increase the modulation speed of a carrier-injection HBT-EAM device. A monolithic TWE design for an 180um ultra compact carrier-injection-based HBT-EAM implemented in a commercial 130nm SiGe BiCMOS process is discussed. The modulator is electrically modeled at the desired bias voltage and included in a 3D full-wave simulation using CST software. The simulation shows the TWE has a S11 lower than -15.31dB and a S21 better than -0.96dB covering a bandwidth from DC-60GHz. The electrical wave phase velocity is designed close to the optical wave phase velocity for optimal modulation speed. The 3D TWE design conforms to the design rules of the BiCMOS process. Simulation results show an overall increase in modulator data rate from 10Gbps to 60Gbps using the TWE structure.

Fu, Enjin; Joyner Koomson, Valencia; Wu, Pengfei; Huang, Z. Rena

2014-03-01

95

Mechanical and optical characterization of thermal microactuators fabricated in a CMOS process  

Microsoft Academic Search

Microelectromechanical actuators with large vertical deflections are desirable for microactuation and sensing applications, such as tactile stimulators for telerobotics, micropositioners, and microflaps for airflow control. Thermally actuated cantilever beams provide large deflections at low voltages and low power. Cantilever beams using silicon micromachining have been fabricated in a complementary metal-oxide-semiconductor process. The beams were tested using a microscope-based laser interferometer

Britton C. Read; Victor M. Bright; John H. Comtois

1995-01-01

96

Ge technology beyond Si CMOS  

NASA Astrophysics Data System (ADS)

To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at <= 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to <= 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-?/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

Chin, Albert

2012-12-01

97

Very low drift and high sensitivity of nanocrystal-TiO2 sensing membrane on pH-ISFET fabricated by CMOS compatible process  

NASA Astrophysics Data System (ADS)

High sensitivity and very low drift rate pH sensors are successfully prepared by using nanocrystal-TiO2 as sensing membrane of ion sensitive field effect transistor (ISFET) device fabricated via CMOS process. This paper describes the physical properties and sensing characteristics of the TiO2 membrane prepared by annealing Ti and TiN thin films that deposited on SiO2/p-Si substrates through reactive DC magnetron sputtering system. The X-ray diffraction, scanning electron microscopy and Auger electron spectroscopy were used to investigate the structural and morphological features of deposited films after they had been subjected to annealing at various temperatures. The experimental results are interpreted in terms of the effects of amorphous-to-crystalline phase transition and subsequent oxidation of the annealed films. The electrolyte-insulator-semiconductor (EIS) device incorporating Tisbnd Osbnd N membrane that had been obtained by annealing of TiN thin film at 850 °C exhibited a higher sensitivity (57 mV/pH), a higher linearity (1), a lower hysteresis voltage (1 mV in the pH cycle of 7 ? 4 ? 7 ? 10 ? 7), and a smaller drift rate (0.246 mV/h) than did those devices prepared at the other annealing temperatures. Furthermore, this pH-sensing device fabrication process is fully compatible with CMOS fabrication process technology.

Bunjongpru, W.; Sungthong, A.; Porntheeraphat, S.; Rayanasukha, Y.; Pankiew, A.; Jeamsaksiri, W.; Srisuwan, A.; Chaisriratanakul, W.; Chaowicharat, E.; Klunngien, N.; Hruanun, C.; Poyai, A.; Nukeaw, J.

2013-02-01

98

An ultra-low-power area-efficient non-volatile memory in a 0.18 ?m single-poly CMOS process for passive RFID tags  

NASA Astrophysics Data System (ADS)

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 ?m single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 ?m single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 ?m2 and 0.12 mm2, respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 ?W/0.69 ?W at a read/write rate of (268 kb/s)/(3.0 kb/s).

Xiaoyun, Jia; Peng, Feng; Shengguang, Zhang; Nanjian, Wu; Baiqin, Zhao; Su, Liu

2013-08-01

99

Review of radiation damage studies on DNW CMOS MAPS  

NASA Astrophysics Data System (ADS)

Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7·1013 cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

2013-12-01

100

Graphene/Si CMOS Hybrid Hall Integrated Circuits  

PubMed Central

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

101

Silicon CMOS based Vertical Multimode Interference Optical Taps  

Microsoft Academic Search

A compact, low loss, optical tap technology is critical for the incorporation of optical interconnects into mainstream CMOS processes. A recently introduced multimode interference effect based device has the potential for very high speed performance in a compact geometry and in a CMOS compatible process. For this work, 2-D and 3-D device simulations confirm a low excess optical loss on

Vincent Stenger; Fred R. Beyette Jr

102

Wanlass's CMOS circuit  

Microsoft Academic Search

The invention of complementary-MOS (CMOS) logic circuitry by Frank Wanlass in 1963 is recounted. The difficulties encountered by Wanlass in an attempt to make stable silicon MOSFETs and how they led him to the CMOS circuit are described. The first demonstration circuit, a two-transistor inverter, consumed just a few nanowatts of standby power and exhibited propagation delay times on the

M. J. Riezenman

1991-01-01

103

Ion traps fabricated in a CMOS foundry  

NASA Astrophysics Data System (ADS)

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

2014-07-01

104

Ion traps fabricated in a CMOS foundry  

E-print Network

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

2014-06-13

105

CMOS Avalanche Photodiode Embedded in a Phase-Shift Laser Rangefinder  

Microsoft Academic Search

This paper presents the design and the characterization of a CMOS avalanche photodiode (APD) working as an optoelectronic mixer. The P+N photodiode has been implemented in a commercial 0.35-mum CMOS technology after optimization with SILVACO. The surface of the active region is 3.78 middot10-3 cm2. An efficient guard-ring structure has been created using the lateral diffusion of two n-well regions

Emmanuel R. Moutaye; Hélène Tap-Beteille

2008-01-01

106

Fundamental performance differences of CMOS and CCD imagers: part V  

NASA Astrophysics Data System (ADS)

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

107

Thermoelectric power sensor for microwave applications by commercial CMOS fabrication  

Microsoft Academic Search

This work describes an implementation of a thermoelectric microwave power sensor fabricated through commercial CMOS process with additional maskless etching. The sensor combines micromachined coplanar waveguide and contact pads, a microwave termination which dissipates heat proportionally to input microwave power, and many aluminum-polysilicon thermocouples. The device was designed and fabricated in standard CMOS technology, including the appropriate superimposed dielectric openings

V. Milanovic; M. Gaitan; E. D. Bowen; N. H. Tea; M. E. Zaghloul

1997-01-01

108

Fundamental performance differences between CMOS and CCD imagers: part III  

NASA Astrophysics Data System (ADS)

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

109

Fundamental performance differences between CMOS and CCD imagers: Part 1  

NASA Astrophysics Data System (ADS)

In depth characterization of CMOS arrays is unveiling many characteristics not observed in CCD imagers. This paper is the first of a series of papers that will discuss unique CMOS characteristics related to fundamental performance differences between CMOS and CCD imagers with emphasis on scientific arrays. The first topic will show that CMOS read noise is ultimately limited by a phenomenon referred to as random telegraph signal (RTS) noise. RTS theory and experimental data discuss its creation, time and frequency domain characteristics, wide variance from pixel to pixel and magnitude on the sensor's overall read noise floor. Specific operating parameters that control and lower RTS noise are identified. It is shown how correlated double sampling (CDS) signal processing responds to RTS noise and demonstrate that sub electron CMOS read noise performance is possible. The paper also discusses CMOS sensitivity (V/e-) nonlinearity, an effect not familiar to CCD users. The problem plays havoc on conventional photon transfer analysis that leads to serious measurement errors. New photon transfer relations are developed to deal with the problem. Nonlinearity for custom CMOS pixels is shown to be beneficial for lowering read noise and extending dynamic range. The paper closes with a section on the high performance CMOS array used to generated data products presented.

Janesick, James; Andrews, James T.; Elliott, Tom

2006-06-01

110

CMOS sensor for face tracking and recognition  

NASA Astrophysics Data System (ADS)

This paper describes the main principles of a vision sensor dedicated to the detecting and tracking faces in video sequences. For this purpose, a current mode CMOS active sensor has been designed using an array of pixels that are amplified by using current mirrors of column amplifier. This circuit is simulated using Mentor Graphics software with parameters of a 0.6 ?m CMOS process. The circuit design is added with a sequential control unit which purpose is to realise capture of subwindows at any location and any size in the whole image.

Ginhac, Dominique; Prasetyo, Eri; Paindavoine, Michel

2005-03-01

111

Improving CMOS-compatible Germanium photodetectors.  

PubMed

We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 ?m Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data. PMID:23187489

Li, Guoliang; Luo, Ying; Zheng, Xuezhe; Masini, Gianlorenzo; Mekis, Attila; Sahni, Subal; Thacker, Hiren; Yao, Jin; Shubin, Ivan; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

2012-11-19

112

All-CMOS night vision viewer with integrated microdisplay  

NASA Astrophysics Data System (ADS)

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

113

Abstract--The total ionization dose effects and the single event effects in a 0.25 m Silicon-On-Sapphire CMOS process are  

E-print Network

Abstract-- The total ionization dose effects and the single event effects in a 0.25 µµµµm Silicon-On-Sapphire, silicon-on-sapphire I. INTRODUCTION ilicon-on-Sapphire (SOS) CMOS technology has been used in applications for radiation tolerant electronics since 1970. With the insulating sapphire substrate, this technology

Ye, Jingbo

114

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications  

PubMed Central

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

115

Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications  

Microsoft Academic Search

An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip

Mohamed Mobarak; Marvin Onabajo; Jose Silva-Martinez; Edgar Sanchez-Sinencio

2010-01-01

116

Packaged CMOS-MEMS free-free beam oscillator  

NASA Astrophysics Data System (ADS)

In this paper a self-oscillator based on a polysilicon free-free beam resonator monolithically integrated and packaged in a 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology is presented. The oscillator is capable of providing a 350 mVPP sinusoidal signal at 25.6 MHz, with a bias polarization voltage of 7 V. The microelectromechanical systems (MEMS) resonator is packaged using only the back-end-of-line metal layers of the CMOS technology, providing a complete low-cost CMOS-MEMS processing for on-chip frequency references.

Marigó, E.; Verd, J.; López, J. L.; Uranga, A.; Barniol, N.

2013-11-01

117

Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process  

SciTech Connect

The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and overlay on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described.

Allen, R.A.; Cresswell, M.W.; Linholm, L.W.; Owen, J.C. III; Ellenwood, C.H. [National Inst. of Standards and Technology, Gaithersburg, MD (United States); Hill, T.A.; Benecke, J.D.; Volk, S.R.; Stewart, H.D. [Sandia National Labs., Albuquerque, NM (United States)

1994-02-01

118

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

119

Implantable CMOS Biomedical Devices  

PubMed Central

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented. PMID:22291554

Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

2009-01-01

120

A low-power CMOS compatible integrated gas sensor using maskless tin oxide sputtering  

Microsoft Academic Search

This paper describes a CMOS compatible integrated gas sensor. The device was designed so that the front-end fabrication is fully compatible with the standard CMOS process. The non-CMOS compatible fabrication steps were carried out as post-processing steps. This included the silicon anisotropic etch to create the thermally isolated micro-hotplate (MHP) and the deposition of gas-sensitive thin films using maskless r.f.

Lie-yi Sheng; Zhenan Tang; Jian Wu; Philip C. H. Chan; Johnny K. O. Sin

1998-01-01

121

N-well resistance modelling in Q-factor of doughnut-shaped PN varactors  

NASA Astrophysics Data System (ADS)

In this paper the N-well resistance in doughnut-shaped PN varactors, with the cathode connected to an N+ buried layer, has been modelled. The proposed expression for the N-well resistance, numerically validated, is based on the device geometry and overlapping of adjacent basic cells, and adequately reproduces its applied reverse bias voltage dependency. Once the varactor extrinsic parasitic components are extracted considering proximity effects, from anode-to-cathode measured RF admittances, and frequencies ranging from 0.5 GHz to 10 GHz, the impact of the N-well resistance on the experimental varactor quality factor is determined for reverse biases up to 5 V.

Marrero-Martín, M.; González, B.; García, J.; Hernández, A.

2015-01-01

122

CMOS MEMS capacitive absolute pressure sensor  

NASA Astrophysics Data System (ADS)

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

2013-05-01

123

Micromachined microwave transmission lines in CMOS technology  

Microsoft Academic Search

Coplanar waveguides were designed and fabricated through a commercial CMOS process with post-processing micromachining. The transmission-line layouts were designed with commercial computer-aided design (CAD) tools. Integrated circuits (ICs) were fabricated through the MOSIS service, and subsequently suspended by top-side etching. The absence of the lossy silicon substrate after etching results in significantly improved insertion-loss characteristics, dispersion characteristics, and phase velocity.

V. Milanovic; M. Gaitan; E. D. Bowen; M. E. Zaghloul

1997-01-01

124

A monolithic CMOS step-down DC-DC converter  

Microsoft Academic Search

A monolithic CMOS switch-mode step-down power converter, with on-chip PWM technique, has been designed and implemented. Also, a micropower bandgap reference generator is developed for the dc-dc converter. This power converter occupied a chip area of 880times1040 mum2 is fabricated in a 2P4M 0.35-mum CMOS process. The simulation results show that the converter is well regulated over an output range

Yeong-Tsair Lin; Wen-Yaw Chung; Dong-Shiu Wu; Hung-Chan Wang; Hung-Yih Lin; Jiann-Jong Chen

2005-01-01

125

Integration of a photodiode array and centroid processing on a single CMOS chip for a real-time shack-Hartmann wavefront sensor  

Microsoft Academic Search

A real-time VLSI optical centroid processor has been developed as part of a larger Shack-Hartmann wavefront sensor system for applications in adaptive optics. The implementation of the optical centroid detection system was demonstrated successfully using a hardware emulation system. Subsequently, the design has been implemented as a CMOS single-chip solution. This has advantages in terms of speed, power consumption, system

Boon Hean Pui; Barrie Hayes-Gill; Matthew Clark; Mike G. Somekh; Chung Wah See; Steve Morgan; Alan Ng

2004-01-01

126

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process  

Microsoft Academic Search

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design

Chun-Hsien Lien; Chi-Hsueh Wang; Chin-Shen Lin; Pei-Si Wu; Kun-You Lin; Huei Wang

2009-01-01

127

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

128

CMOS Gates Demonstration  

NSDL National Science Digital Library

This website, hosted by the University of Hamburg, provides an in depth description of the basic operation of CMOS circuits including inverters, NAND gates, and NOR gates. Circuit simulations are shown and power dissipation is discussed. Some of these include: inverters, NAND and NOR gates, transmission gates, D-latch with T-gates, power consumption, complex gates and SRAM cells. Overall, the site is perfect for undergraduate computer science majors to learn more about the exciting topic of semiconductors.

129

Integration of Solar Cells on Top of CMOS Chips Part I: aSi Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process

Jiwu Lu; Alexey Y. Kovalgin; Karine H. M. van der Werf; Ruud E. I. Schropp; Jurriaan Schmitz

2011-01-01

130

An image identification system of seal with fingerprint based on CMOS image sensor  

Microsoft Academic Search

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analog signal conditioning circuits, A\\/D converter and digital processing functions. Furthermore, CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image

Xu-cheng Xue; Shu-yan Zhang; Yong-fei Guo

2006-01-01

131

Advanced CMOS Radiation Effects Testing Analysis  

NASA Technical Reports Server (NTRS)

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

2014-01-01

132

Advanced CMOS Radiation Effects Testing and Analysis  

NASA Technical Reports Server (NTRS)

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

2014-01-01

133

High-speed CMOS circuit technique  

Microsoft Academic Search

Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

JIREN YUAN; CHRISTER SVENSSON

1989-01-01

134

Modeling and simulation of TDI CMOS image sensors  

NASA Astrophysics Data System (ADS)

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

2013-09-01

135

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Castro, Xitzel Sanchez; Winter, Marc

2014-01-01

136

Low-power 2-D fully integrated CMOS fluxgate magnetometer  

Microsoft Academic Search

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works

Predrag M. Drljaca; Pavel Kejik; Franck Vincent; Dominique Piguet; Radivoje S. Popovic

2005-01-01

137

Design and Fabrication of Vertically-Integrated CMOS Image Sensors  

PubMed Central

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-01-01

138

Test structures to measure the Seebeck coefficient of CMOS IC polysilicon  

Microsoft Academic Search

We report on two thermal characterization structures to measure the Seebeck coefficient ? of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 ?m CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for

M. Von Arx; O. Paul; Henry Baltes

1997-01-01

139

A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps  

E-print Network

]. Tgta1 I 44.000 Before the DLL circuit was mapped on to a 0.8 pm CMOS process, a detailed analysis on the stabili- ty characteristics of the DLL loop was carried out to determine the component valuesA CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps Element Phase detector

Ayers, Joseph

140

A CMOS humidity sensor for passive RFID sensing applications.  

PubMed

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

141

An array-based CMOS biochip for electrical detection of DNA with multilayer self-assembly gold nanoparticles  

Microsoft Academic Search

This paper presents an array-based CMOS biochip for DNA detection using self-assembly multilayer gold nanoparticles (AuNPs). The biochip is fabricated by a TSMC 0.35?m standard CMOS process and post-CMOS micromachining processes. Before taking DNA detection measurements, self-assembly monolayer of AuNPs is established on SiO2 surface between two microelectrodes. The gap distance between the two microelectrodes in this study is less

Yi-Ting Cheng; Ching-Chin Pun; Chien-Ying Tsai; Ping-Hei Chen

2005-01-01

142

High voltage AlGaN/GaN metal–oxide–semiconductor high-electron mobility transistors with regrown In0.14Ga0.86N contact using a CMOS compatible gold-free process  

NASA Astrophysics Data System (ADS)

We report the fabrication and characterization of high voltage AlGaN/GaN metal–oxide–semiconductor high-electron mobility transistors (MOSHEMTs) with selectively regrown In0.14Ga0.86N contact using a CMOS compatible gold-free process. Device with the regrown InGaN contact with a gate-to-drain spacing LGD of 5 µm achieves an off-state breakdown voltage VBR of 800 V and on-state resistance Ron of 2 m?·cm2. The VBR achieved in this work is higher than those of gold-free GaN MOSHEMTs with gate-to-drain spacing LGD below 10 µm.

Liu, Xinke; Amin Bhuiyan, Maruf; S/O Somasuntharam, Pannirselvam; Beng Soh, Chew; Liu, Zhihong; Zhi Chi, Dong; Liu, Wei; Lu, Youming; Yu, Wenjie; Seow Tan, Leng; Yeo, Yee-Chia

2014-12-01

143

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

144

CMOS-Based Biosensor Arrays  

E-print Network

CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

2011-01-01

145

Hybrid postprocessing etching for CMOS-compatible MEMS  

Microsoft Academic Search

A major limitation in the fabrication of microstructures as a postCMOS (complimentary metal oxide semiconductor) process has been overcome by the development of a hybrid processing technique, which combines both an isotropic and anisotropic etch step. Using this hybrid technique, microelectromechanical structures with sizes ranging from 0.05 to ~1 mm in width and up to 6 mm in length were

Nim H. Tea; V. Milanovic; Christian A. Zincke; John S. Suehle; Michael Gaitan; Mona E. Zaghloul; Jon Geist

1997-01-01

146

CMOS APS digital camera based on enhanced parallel port  

NASA Astrophysics Data System (ADS)

CMOS APS become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor analogue circuitry, and digital processing functions. This paper discusses a CMOS digital camera based on EPP interface. A CMOS APS (OV7110) with VGA resolution (640 x 480) was selected as the image sensor, it can generate digital output of typically an 8 or 16 bit data bus in YUV or RGB mode, all the image controllling, e.g. frame rate, white balance, gamma control and exposure control all can be adjusted through 12C bus. The 12C bus control unit, FIFO and EPP interface, etc. are all integrated within a CPLD. The overall structure, working scheme and performance analyses of the camera were discussed in detail. Several images taken by the camera are provided and a detailed discussion of its quality, processing of image data, etc. is also given.

Liu, Zhi; Yang, Jingyi; Wang, Yefan; Hao, Zhihang

2002-09-01

147

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

NASA Astrophysics Data System (ADS)

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

Zhang, Weiquan

2000-12-01

148

VLSI scaling methods and low power CMOS buffer circuit  

NASA Astrophysics Data System (ADS)

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Sharma, Vijay Kumar; Pattanaik, Manisha

2013-09-01

149

CMOS passive pixel image design techniques  

E-print Network

CMOS technology provides an attractive alternative to the currently dominant CCD technology for implementing low-power, low-cost imagers with high levels of integration. Two pixel configurations are possible in CMOS ...

Fujimori, Iliana L. (Iliana Lucia)

2002-01-01

150

Novel neuromorphic CMOS device array for biochemical charge sensing.  

PubMed

Novel neuromorphic CMOS device is proposed as a biochemical charge sensor. The basic architecture of an extended floating-gate field-effect transistor (FET) is modified to be suited for large-array applications. The FET has a floating-gate that is umbrella-shaped (UGFET), maximizing its charge sensing area in a much reduced transistor area. Compared to previous chemoreceptive FET-based charge sensors, the UGFET shows improved scalability and sensitivity. 3-D device simulations validate the UGFET model. The design is fabricated in a standard CMOS process and characterized. Experimental results on biochemical charge sensing are presented employing the transconductance and subthreshold measurement schemes. PMID:19163158

Pandey, Santosh; Daryanani, Michelle; Chen, Baozhen; Tao, Chengwu

2008-01-01

151

CMOS Circuit Speed and Buffer Optimization  

Microsoft Academic Search

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown

Nils Hedenstierna; Kjell O. Jeppson

1987-01-01

152

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics  

PubMed Central

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

153

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

154

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

155

A low power CMOS adaptive line equalizer for fast Ethernet  

Microsoft Academic Search

An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 ?m CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm2).

Kwisung Yoo; Hoon Lee; Gunhee Han

2002-01-01

156

Low cost CMOS multi-electrode arrays Alex Lyakhov1  

E-print Network

significantly better corrosion immunity under stress. However, several tested electrodes have performed very of the recording probes and the amplifying circuitry can also enhance noise immunity in CMOS MEAs. Finally, entire electric stress. To facilitate stimulation in low cost MEAs, we investigate simple post-processing steps

Ginosar, Ran

157

Photocurrent estimation from multiple nondestructive samples in CMOS image sensor  

Microsoft Academic Search

CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic

Xinqiao Liu; Abbas El Gamal

2001-01-01

158

SI-based unreleased hybrid MEMS-CMOS resonators in 32nm technology  

E-print Network

This work presents the first unreleased Silicon resonators fabricated at the transistor level of a standard CMOS process, and realized without any release steps or packaging. These unreleased bulk acoustic resonators are ...

Marathe, Radhika A.

159

A 0.06 mm2 1.0 V 2.5 mW 10 bit 250 MS/s current-steering D/A converter in 65 nm GP CMOS process  

NASA Astrophysics Data System (ADS)

A 10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard VT core devices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity (INL) yield with both end-point line and best-fit line. A formula is derived for the relationship of INL and output impedance. The relation of dynamic range and output impedance is also discussed. The double centroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to overcome the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.

Yawei, Guo; Li, Li; Peng, Ou; Zhida, Hui; Xu, Cheng; Xiaoyang, Zeng

2014-06-01

160

SQI-CMOS based single crystal silicon micro-heaters for gas sensors  

Microsoft Academic Search

Here we report on novel high temperature gas sensors that have been fabricated using an SOI (silicon-on-insulator) -CMOS process and deep RIE back-etching. These sensors offer ultra-low power consumption, low unit cost, and excellent thermal stability. The highly-doped single crystal silicon (SCS) layer of a standard SOI-CMOS process, which is traditionally used to form the source and drain regions of

T. Iwaki; J. A. Covington; J. W. Gardner; F. Udrea; C. S. Blackman; I. P. Parkin

2006-01-01

161

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.  

PubMed

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200?mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Kazior, Thomas E

2014-03-28

162

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio  

Microsoft Academic Search

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

2007-01-01

163

Low Power CMOS Digital Design  

Microsoft Academic Search

: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which

Anantha P. Chandrakasan; Samuel Sheng; Robert W. Brodersen

1995-01-01

164

Nanophotonic integration in state-of-the-art CMOS foundries.  

PubMed

We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming. PMID:21369052

Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popovi?, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Kärtner, Franz X; Smith, Henry I; Stojanovi?, Vladimir; Ram, Rajeev J

2011-01-31

165

Research-grade CMOS image sensors for demanding space applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2004-06-01

166

Research-grade CMOS image sensors for remote sensing applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

2004-11-01

167

Micro FET pressure sensor manufactured using CMOS-MEMS technique  

Microsoft Academic Search

The fabrication of a micro field effect transistor (FET) pressure sensor using the commercial 0.35?m complementary metal oxide semiconductor (CMOS) process and a post-process has been investigated. The pressure sensor is composed of 16 sensing cells in parallel, and each sensing cell includes a suspended membrane and an NMOS. The suspended membrane is the movable gate of the NMOS. The

Ching-Liang Dai; Pin-Hsu Kao; Yao-Wei Tai; Chyan-Chyi Wu

2008-01-01

168

Single core fully integrated CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

A new fully integrated 2D micro-fluxgate magnetometer is presented. This magnetometer is integrated in a standard CMOS process and uses a ferromagnetic core integrated on the chip by a photolithographic post-process compatible with the integrated circuit technology. The cross-shaped ferromagnetic core is placed diagonally above four excitation coils, two for each measurement axis. A novel electronic signal extraction technique is

Predrag M. Drlja?a; Pavel Kejik; Franck Vincent; Dominique Piguet; François Gueissaz; Radivoje S. Popovi?

2004-01-01

169

0.5 micron CMOS for high performance at 3.3 V  

Microsoft Academic Search

In addition to higher packing density, the scaling of CMOS technology to the half-micron regime must provide improved circuit performance at a reduced supply voltage without increased process complexity. These goals have been met with a 0.5- mu m CMOS technology with 12-nm gate oxide thickness that gives at least a 20% speed improvement at a 3.3-V supply voltage compared

R. A. Chapman; C. C. Wei; D. A. Bell; S. Aur; G. A. Brown; R. A. Haken

1988-01-01

170

High performance and low power transistors integrated in 65nm bulk CMOS technology  

Microsoft Academic Search

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 %

Z. Luo; A. Steegen; M. Eller; R. Mann; C. Baiocco; P. Nguyen; L. Kim; M. Hoinkis; V. Ku; V. Klee; F. Jamin; P. Wrschka; P. Shafer; W. Lin; S. Fang; A. Ajmera; W. Tan; R. Mo; J. Lian; D. Vietzke; C. Coppock; A. Vayshenker; T. Hook; V. Chan; K. Kim; A. Cowley; S. Kim; E. Kaltalioglu; B. Zhang; S. Marokkey; Y. Lin; K. Lee; H. Zhu; M. Weybright; R. Rengarajan; J. Ku; T. Schiml; J. Sudijono; I. Yang; C. Wann

2004-01-01

171

Nano\\/CMOS architectures using a field-programmable nanowire interconnect  

Microsoft Academic Search

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano\\/CMOS circuit architectures that generalizes the CMOL (CMOS\\/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components

Gregory S Snider; R Stanley Williams

2007-01-01

172

A Sub W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application  

Microsoft Academic Search

An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 ?m CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT)

Man Kay Law; Amine Bermak; Howard C. Luong

2010-01-01

173

A 1.9GHz Single-Chip CMOS PHS Cellphone  

Microsoft Academic Search

A single-chip CMOS PHS cellphone, fabricated in a 0.18mum CMOS process, implements all handset functions including radio, voice, audio, CPU, and digital interfaces. The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity, and 15mus synthesizer settling time. It draws 81 mA from a 1.8V supply while occupying 35mm2 of chip area

S. Mehta; W. W. Si; H. Samavati; M. Terrovitis; M. Mack; K. Onodera; S. Jen; S. Luschas; J. Hwang; S. Mendis; D. Su; B. Wooley

2006-01-01

174

Advances in CMOS solid-state photomultipliers for scintillation detector applications  

Microsoft Academic Search

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes

James F. Christian; Christopher J. Stapels; Erik B. Johnson; Mickel McClish; Purushotthom Dokhale; Kanai S. Shah; Sharmistha Mukhopadhyay; Eric Chapman; Frank L. Augustine

2010-01-01

175

Digital-Centric RF CMOS Technologies  

NASA Astrophysics Data System (ADS)

Analog-centric RFCMOS technology has played an important role in motivating the change of technology from conventional discrete device technology or bipolar IC technology to CMOS technology. However it introduces many problems such as poor performance, susceptibility to PVT fluctuation, and cost increase with technology scaling. The most important advantage of CMOS technology compared with legacy RF technology is that CMOS can use more high performance digital circuits for very low cost. In fact, analog-centric RF-CMOS technology has failed the FM/AM tuner business and the digital-centric CMOS technology is becoming attractive for many users. It has many advantages; such as high performance, no external calibration points, high yield, and low cost. From the above facts, digital-centric CMOS technology which utilizes the advantages of digital technology must be the right path for future RF technology. Further investment in this technology is necessary for the advancement of RF technology.

Matsuzawa, Akira

176

Evolving Variability-Tolerant CMOS Designs  

Microsoft Academic Search

As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher\\u000a failure rates in conventional CMOS designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerent\\u000a CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully\\u000a evolve unconventional designs for logic

James Alfred Walker; James A. Hilder; Andy M. Tyrrell

2008-01-01

177

A Low-Cost CMOS Programmable Temperature Switch  

PubMed Central

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 ?m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 ?A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

Li, Yunlong; Wu, Nanjian

2008-01-01

178

A back-illuminated megapixel CMOS image sensor  

NASA Technical Reports Server (NTRS)

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

179

Development of a silicon gate CMOS technology with small structures  

NASA Astrophysics Data System (ADS)

The development of HCMOS technology for 3 to 4 microns structures in order to improve packing density and performance for very large scale integration CMOS circuits, operating at 1,5V, is outlined. Design rule definition, photolithography/contact and projection, layout techniques, and process development (high value polysilicon resistors) are discussed. The technology developed was successfully demonstrated on an advanced 4 MHz (1,5V) watch circuit.

Milosevic, I.; Tilenschi, L.; Luft, R.; Cornwell, D.

1982-09-01

180

A low-phase-noise K-band CMOS VCO  

Microsoft Academic Search

A novel circuit topology for low-phase-noise voltage controlled oscillators (VCOs) is presented in this letter. By employing a PMOS cross-coupled pair with a capacitive feedback, superior circuit performance can be achieved especially at higher frequencies. Based on the proposed architecture, a prototype VCO implemented in a 0.18-mum CMOS process is demonstrated for K-band applications. From the measurement results, the VCO

Hsieh-Hung Hsieh; Liang-Hung Lu

2006-01-01

181

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator  

Microsoft Academic Search

This paper reports a full CMOS process using a combination of a TiN\\/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO2 but having relatively low gate leakage are reported. Transistors with gate lengths

A. Chatterjee; R. A. Chapman; K. Joyner; M. Otobe; S. Hattangady; M. Bevan; G. A. Brown; H. Yang; Q. He; D. Rogers; S. J. Fang; R. Kraft; A. L. P. Rotondaro; M. Terry; K. Brennan; S.-W. Aur; J. C. Hu; H.-L. Tsai; P. Jones; G. Wilk; M. Aoki; M. Rodder; I.-C. Chen

1998-01-01

182

Phase Noise and Jitter in CMOS Ring Oscillators  

Microsoft Academic Search

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1\\/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise,

Asad A. Abidi

2006-01-01

183

A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13µ CMOS process  

Microsoft Academic Search

A high performance, fully differential line driver for use in gigabit and fast Ethernet over unshielded twisted pair CAT-5 copper cables is presented. By using a negative feedback based technique and an on-chip calibration engine to compensate for process variations, the 100-ohm output impedance is synthesized. To date, this is the single industrial realization of a gigabit\\/fast Ethernet line driver

Dan Stiurca

2005-01-01

184

Improved Space Object Orbit Determination Using CMOS Detectors  

NASA Astrophysics Data System (ADS)

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

185

Demonstration of a free-space optical interconnect in a CMOS chip  

NASA Astrophysics Data System (ADS)

We have developed a hybrid optoelectronic circuit to demonstrate a free-space optical interconnect in a CMOS chip. Discrete GaAs-based optical devices are hybridly integrated with a 0.8 micrometers CMOS chip fabricated by a MOSIS foundry. The CMOS chip consists of two separate digital modules, an ALU and a ROM, communicating via a pair of optical interconnects. Each interconnect consists of a CMOS laser driver that converts full CMOS logic-level data into a suitable laser drive current, a laser-photodetector pair, and a CMOS transimpedance amplifier that converts a photocurrent from the photodetector into logic-level data. An on-chip clock is used to time the serialization and deserialization of 4-bit words of data across each interconnect at a data rate of 40 Mb/s. In order to account for limitations of the hybrid design as well as process variations, pads are provided for off-chip clock signals to override the built-in clock and therefore operate the interconnect at a transmission rate different from the design value. Each laser-photodetector pair is fabricated from a single laser structure epitaxially grown on semi-insulating GaAs substrate. Similar to a laser-photomonitor arrangement, a dry etch is used to divide the laser structure into a separate laser and photodiode. This device is then hybridly integrated with the CMOS chip to implement the proof-of-principle free-space optical interconnect. Experimental results for the optical elements and simulation results for the CMOS design are presented to demonstrate the operation of the chip.

Mena, Pablo V.; Lammert, Robert M.; Kang, Steve M.; Coleman, James J.

1995-04-01

186

CMOS foveal image sensor chip  

NASA Technical Reports Server (NTRS)

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

187

Diffuse reflectance measurements using lensless CMOS imaging chip  

NASA Astrophysics Data System (ADS)

To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 ?m thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

2014-10-01

188

Cryogenic CMOS circuits for single charge digital readout.  

SciTech Connect

The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

2010-03-01

189

Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors  

Microsoft Academic Search

A scheme for low-voltage CMOS op-amp operation with rail-to-rail input and output signal swing and constant gm is presented. Single-ended and fully differential versions are discussed. The scheme is based on the use of multiple-input floating-gate transistors and allows direct implementation of linear weighted addition of continuous-time signals. Simulations are presented that verify the scheme operating with a 1.2-V single

J. Ramirez-Angulo; R. G. Carvajal; J. Tombs; A. Torralba

2001-01-01

190

A CMOS 18 THz? 248 Mb\\/s transimpedance amplifier and 155 Mb\\/s LED-driver for low cost optical fiber links  

Microsoft Academic Search

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 ?m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is

Mark Ingels; Geert Van der Plas; Jan Crols; Michel Steyaert

1994-01-01

191

Integration of RF-MEMS, passives and CMOS-IC on silicon substrate by low temperature wafer to wafer bonding technique  

Microsoft Academic Search

In this paper, a novel platform technology for system level integration of RF-MEMS, RF passives and CMOS-IC on silicon substrate is reported. The RF passives and RF MEMS devices are fabricated on a low resistivity silicon wafer using Cu damascene process. After bonding the wafer to a CMOS wafer with recesses using benzocyclobutene (BCB) as intermediate layer and subsequently removal

Q. X. Zhang; H. Y. Li; M. Tang; A. B. Yu; E. B. Liao; Rong Yang; G. Q. Lo; N. Balasubramanian; D. L. Kwong

2008-01-01

192

A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking  

NASA Astrophysics Data System (ADS)

With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 ?m CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

Degerli, Y.; Guilloux, F.; Orsini, F.

2014-05-01

193

High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology  

Microsoft Academic Search

The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate

Min Park; Seonghearn Lee; Hyun Kyu Yu; Jin Gun Koo; Kee Soo Nam

1997-01-01

194

Introducing 65 nm CMOS technology in low-noise read-out of semiconductor detectors  

Microsoft Academic Search

The large scale of integration provided by CMOS processes with minimum feature size in the 100nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, processes with 130nm minimum channel length are widely available for Application Specific Integrated Circuits (ASICs)

M. Manghisoni; L. Gaioni; L. Ratti; V. Re; G. Traversi

2010-01-01

195

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity epitaxial layers leads to the better radiation hardness and allows the implementation of accelerated readout circuits. The TowerJazz $0.18 \\mu m$ CMOS process being one of the most relevant examples recently became of interest for several future detector projects. The most imminent of these project is an upgrade of the Inner Tracking System (ITS) of the ALICE detector at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems.

Serhiy Senyukov; Jerome Baudot; Auguste Besson; Giles Claus; Loic Cousin; Wojciech Dulinski; Mathieu Goffe; Boris Hippolyte; Robert Maria; Levente Molnar; Xitzel Sanchez Castro; Marc Winter

2014-02-10

196

Integration hybride de transistors a un electron sur un noeud technologique CMOS  

NASA Astrophysics Data System (ADS)

This study deals with the hybrid integration of single electron transistors (SET) on a CMOS technology nod. SET devices possess a high potential, especially regarding energy efficiency, but aren't fit to completely replace CMOS components in electrical circuits. However, this problem can be solved through hybrid combination of SETs and MOS, leading to very low operating power circuits, and high integration density. This thesis investigates the use of the nanodamascene process, developed by C. Dubuc, for back-end-of-line (BEOL) SET fabrication, meaning creation of SETs in the oxide encapsulating CMOS devices. The assets the nanodamascene process presents are quite interesting: fabrication of SETs with a large operation margin, high repeatability, and potential for BEOL fabrication. This last point, in particular, makes this process promising. Indeed, it opens the path to the fabrication of numerous layers of SETs, stacked one upon the other, and forming 3D circuits, created on top of 2D CMOS layer. Thus a high gain to existing CMOS wafers could be generated. Devices created through the use of the nanodamascene process, adapted for BEOL SET fabrication, are presented. Limits and improvement perspectives of the technique's transfer are discussed. Electrical characterizations of the devices are also presented. They have demonstrated the created devices functionality, thus validating the successful adaption of the nanodamascene process. They have also allowed for the identification of numerous traps located at the heart of fabricated devices. Fabricated SET devices potential for hybrid SET-CMOS circuits was studied through simulations. Possible architectures showing good potential for early hybrid circuits' realization were identified. Keywords: MOSFET, single electron transistor (SET), nanotechnology, microfabrication, nanodamascene, electrical characterization.

Jouvet, Nicolas

197

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

198

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

199

A 64 single photon avalanche diode array in 0.18 µm CMOS standard technology with versatile quenching circuit for quick prototyping  

NASA Astrophysics Data System (ADS)

Several works have demonstrated the successfully integration of Single-photon avalanche photodiodes (SPADs) operating in Geiger mode in a standard CMOS circuit for the last 10 years. These devices offer an exceptional temporal resolution as well as a very good optical sensitivity. Nevertheless, it is difficult to predict the expected performances of such a device. Indeed, for a similar structure of SPAD, some parameter values can differ by two orders of magnitude from a technology to another. We proposed here a procedure to identify in just one or two runs the optimal structure of SPAD available for a given technology. A circuit with an array of 64 SPAD has been realized in the Tower-Jazz 0.18 ?m CMOS image sensor process. It encompasses an array of 8 different structures of SPAD reproduced in 8 diameters in the range from 5 ?m up to 40 ?m. According to the SPAD structures, efficient shallow trench insulator and/or P-Well guard ring are used for preventing edge breakdown. Low dark count rate of about 100 Hz are expected thanks to the use of buried n-well layer and a high resistivity substrate. Each photodiode is embedded in a pixel which includes a versatile quenching circuitry and an analog output of its cathode voltage. The quenching system is configurable in four operation modes; the SPAD is disabled, the quenching is completely passive, the reset of the photodiode is active and the quenching is fully active. The architecture of the array makes possible the characterization of every single photodiode individually. The parameters to be measured for a SPAD are the breakdown avalanche voltage, the dark count rate, the dead time, the timing jitter, the photon detection probability and the after-pulsing rate.

Uhring, Wilfried; Le Normand, Jean-Pierre; Zint, Virginie; Dumas, Norbert; Dadouche, Foudil; Malasse, Imane; Scholz, Jeremy

2012-04-01

200

A scalable neural chip with synaptic electronics using CMOS integrated memristors  

NASA Astrophysics Data System (ADS)

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

2013-09-01

201

A scalable neural chip with synaptic electronics using CMOS integrated memristors.  

PubMed

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. PMID:23999447

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

202

60-GHz array antenna with standard CMOS technology on Schott Borofloat  

NASA Astrophysics Data System (ADS)

This design is presented of a 2 × 2 planar array, with a half-wave dipole antenna to be its element, on a new substrate material, Schott Borofloat, with CMOS technology in the 60 GHz band. In the proposed structure, all the designs are based on the CMOS technology and similar performance could be achieved with the same size in contrast to the design on low-temperature co-fired ceramic (LTCC). This could lead to the improving of the compatibility with the CMOS IC process, the design cost and the design precision which is restricted in the LTCC process. The simulated -10 dB bandwidth of the array is from 58 to 64 GHz. A peak gain of 9.4 dBi is achieved. Good agreement on return loss is achieved between simulations and measurements.

Jun, Luo; Yan, Wang; Ruifeng, Yue

2013-11-01

203

CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results  

NASA Astrophysics Data System (ADS)

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 ? cm, which is at least one order of magnitude greater than the typical value (1-10 ? cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

2013-12-01

204

High-level numerical simulations of noise in CCD and CMOS photosensors: review and tutorial  

E-print Network

In many applications, such as development and testing of image processing algorithms, it is often necessary to simulate images containing realistic noise from solid-state photosensors. A high-level model of CCD and CMOS photosensors based on a literature review is formulated in this paper. The model includes photo-response non-uniformity, photon shot noise, dark current Fixed Pattern Noise, dark current shot noise, offset Fixed Pattern Noise, source follower noise, sense node reset noise, and quantisation noise. The model also includes voltage-to-voltage, voltage-to-electrons, and analogue-to-digital converter non-linearities. The formulated model can be used to create synthetic images for testing and validation of image processing algorithms in the presence of realistic images noise. An example of the simulated CMOS photosensor and a comparison with a custom-made CMOS hardware sensor is presented. Procedures for characterisation from both light and dark noises are described. Experimental results that confirm...

Konnik, Mikhail

2014-01-01

205

Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors  

E-print Network

mm Si-CMOS fabrication infrastructure. Implementation of Si-CMOS compatible technologies began in 2011 and remains heavily researched [8-13]. In particular, realization of low, uniform contact resistance, and uniform enhancement mode threshold... window lithography, a SiNx plasma etch, an AlGaN recess etch, contact metal sputtering, metal patterning, metal etch, and ohmic alloying anneal. Process development began with the SiNx plasma etch. An Applied Materials Centura Super E system was used...

Johnson, Derek Wade

2014-07-31

206

A Wideband CMOS Current-Mode Operational Amplifier and Its Use for BandPass Filter Realization  

Microsoft Academic Search

In this paper, a CMOS current-mode operational amplifier (COA) based on a novel, class A input stage and a folded-cascode output stage is presented. The amplifier provides a 95 dB DC gain and a gain-bandwidth product exceeding 200 MHz. The COA is operated under plusmn1.5 V voltage supplies and designed with 0.35-mum CMOS process. Additionally, COA-based band-pass filter is realized.

M. Altun; H. Kuntman

2006-01-01

207

Low-Power, High-Gain V-Band CMOS Low Noise Amplifier for Microwave Radiometer Applications  

Microsoft Academic Search

A low power and high gain V-band CMOS low-noise amplifier (LNA) is proposed in this letter with a three-stage cas- code topology. Using the gate-inductive gain-peaking technique to boost the gain, the proposed LNA achieves a good figure of merit (FOM) with less power consumption. This proposed LNA is fabri- cated in a 0.13 RF CMOS process, which achieves a

Chun-Chieh Huang; Hsin-Chih Kuo; Tzuen-Hsi Huang; Huey-Ru Chuang

2011-01-01

208

A multi-mode LDO-based Li-ion battery charger in 0.35?m CMOS technology  

Microsoft Academic Search

The paper designs a CMOS Li-ion battery charger that uses multi-mode low dropout (LDO) voltage regulator associated with current sense circuit to supply trickle current, large constant current and constant voltage. The whole circuits have been approved by HSPICE with TSMC 0.35?m 2P4M CMOS process. The simulation results provide the trickle current of 150mA, the maximum charging current of 312mA

Chia-Chun Tsai; Chin-Yen Lin; Yuh-Shyan Hwang; Wen-Ta Lee; Trong-Yen Lee

2004-01-01

209

Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits  

Microsoft Academic Search

The logic behavior and performance of an ECL OR\\/NOR gate under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage. Performance degradation faults such as delay, current and voltage transfer characteristics (VTC) or noise margin

D. Al-Khalili; M. O. Esonu; C. Rozon

1993-01-01

210

A complementary MOS process  

NASA Technical Reports Server (NTRS)

The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.

Jhabvala, M. D.

1977-01-01

211

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

212

Integrating Security Solutions to Support nanoCMOS Electronics Research .  

E-print Network

??The UK Engineering and Physical Sciences Research Council (EPSRC) funded Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is developing a research infrastructure for collaborative… (more)

SINNOTT, RICHARD

2008-01-01

213

CMOS compatible silicon-based Mach-Zehnder optical modulators with improved extinction ratio  

NASA Astrophysics Data System (ADS)

Improved Extinction Ratio of 25 dB was demonstrated in silicon based optical modulators on CMOS platform in China. The measurement results agree with the simulation, followed by a discussion about the effects of both propagation loss in Mach-Zehnder arms and power ratio at beam splitters and combiners. The analyses indicate that many considerations have to be taken into design and development of the compatible fabrication of these integrated silicon photonics, especially for the improved extinction ratio of optical modulators. In this summary, we propose the integrated optical modulators in SOI by use of the compatible CMOS processes under the modern CMOS foundry in Chinese homeland. And the measured results were shown, the fast response modulator with the data transmission rate of 10 Gbps.

Li, Zhiyong; Zhou, Liang; Hu, Yingtao; Xiao, Xi; Yu, Yude; Yu, Jinzhong

2012-02-01

214

New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications  

NASA Astrophysics Data System (ADS)

Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.

Zhou, Wei; Hart, Darcy

2013-09-01

215

Wideband Matched CMOS LNA Design Using R-L-C Loading Network  

NASA Astrophysics Data System (ADS)

This paper proposes a new methodology for designing and analyzing wideband matched CMOS LNA with R-L-C loading network, where validity of this new approach is supported by the agreement between the simulated input impedance of the LNA and its calculated counterpart. To demonstrate its feasibility, two wideband matched LNA’s are designed using TSMC 0.18-?m RF-CMOS process. One is for 3-8 GHz application and the second one targets at 8-25 GHz frequency range. The measured results of both circuits will then be presented.

Wu, Hui-I.; Horng, Qi-Yuan; Hu, Robert; Jou, Christina F.

2010-09-01

216

A novel 3D stacking method for Opto-electronic dies on CMOS ICs.  

PubMed

A high speed, high density and potentially low cost solution for realizing a compact transceiver module is presented in this paper. It is based on directly bonding an Opto-electronic die on top of CMOS IC chip and creating a photoresist ramp to bridge the big step (around 220 ?m) from Opto-electronic pads to CMOS IC pads. The required electrical connection between them is realized lithographically with a process than can be scaled to full wafer production. A 12-channel transmitter based on the technique was fabricated and test shows good performance up to 12.5 Gb/s/ch. PMID:23262878

Duan, Pinxiang; Raz, Oded; Smalbrugge, Barry E; Duis, Jeroen; Dorren, Harm J S

2012-12-10

217

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

218

Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor  

NASA Astrophysics Data System (ADS)

A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35??m CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35?dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 ?-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10?k?, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

2014-09-01

219

CMOS image sensors: electronic camera-on-a-chip  

Microsoft Academic Search

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed

Eric R. Fossum

1997-01-01

220

LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY  

E-print Network

LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock, and Gabriel A. Rincon School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta supply voltages in CMOS integrated circuits. As the channel lengths of CMOS technology decrease

Rincon-Mora, Gabriel A.

221

CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems  

E-print Network

CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems Rajiv Damodaran Prabha, and radiation, photovoltaic (PV) systems are appealing options. Still, chip-sized CMOS PV cells produce only well in substrate cell are better. Index Terms--Ambient light energy, harvester, CMOS photovoltaic (PV

Rincon-Mora, Gabriel A.

222

Electrostatic Modeling of CMOS sensor array 1 Computing Security  

E-print Network

Electrostatic Modeling of CMOS sensor array 1 1 Computing Security Distributed System to establish 2-way authentication. #12;Electrostatic Modeling of CMOS sensor array 2 4 Port Protection (2 to Hades. #12;Electrostatic Modeling of CMOS sensor array 3 7 Kerberos Tickets Used for authentication

Cukic, Bojan

223

Floating-body effects in partially depleted SOI CMOS circuits  

Microsoft Academic Search

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on

Pong-Fei Lu; Ching-Te Chuang; Jin Ji; Lawrence F. Wagner; Chang-Ming Hsieh; J. B. Kuang; L. L.-C. Hsu; S.-F. S. Chu; C. J. Anderson

1997-01-01

224

Towards evolving industry-feasible intrinsic variability tolerant CMOS designs  

Microsoft Academic Search

As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. This paper introduces a design tool capable of evolving CMOS topologies using a modified form of Cartesian genetic programming and a multi-objective strategy. The effect of intrinsic variability within the design is then analysed

James Alfred Walker; James A. Hilder; Andy M. Tyrrell

2009-01-01

225

Resistor Extends Life Of Battery In Clocked CMOS Circuit  

NASA Technical Reports Server (NTRS)

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Wells, George H., Jr.

1991-01-01

226

Page 1 of 20 Catalyst preparation for CMOS-compatible silicon  

E-print Network

-11 . Gold has been the historic catalyst1 for silicon nanowire synthesis as it allows excellent yieldsPage 1 of 20 Catalyst preparation for CMOS-compatible silicon nanowire synthesis Vincent T. Renard (complementary metal oxide semiconductor) fabrication processes. Nanowire synthesis with those metals which

Paris-Sud XI, Université de

227

The impact of RTN on performance fluctuation in CMOS logic circuits  

Microsoft Academic Search

In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of

Kyosuke Ito; Takashi Matsumoto; Shinichi Nishizawa; Hiroki Sunagawa; Kazutoshi Kobayashi; Hidetoshi Onodera

2011-01-01

228

9-11 April 2008 Integrated RF MEMS/CMOS Devices  

E-print Network

the dc tuning voltage exceeds the pull-in voltage, and the top plate snaps down on the bottom plate, smaller size and zero dc power consumption using electrostatic actuation mechanism. The CMOS-MEMS post. Three maskless post-processing steps are required to construct the tunable capacitors. They also include

Paris-Sud XI, Université de

229

A resistorless CMOS bandgap reference with low temperature coefficient and high PSRR  

Microsoft Academic Search

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to

Zekun Zhou; Luping Feng; Yingqian Ma; Yue Shi; Xin Ming; Bo Zhang

2012-01-01

230

Test structures for characterization and comparative analysis of CMOS image sensors  

Microsoft Academic Search

A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized

David X. d. Yang; Hao Min; Boyd A. Fowler; Abbas El Gamal; Mark Beiley; Kit Cham

1996-01-01

231

An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems  

Microsoft Academic Search

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process.

J. Christiansen

1995-01-01

232

Capacitive RF MEMS Switches Fabricated in Standard 0.35- CMOS Technology  

Microsoft Academic Search

The objective of this paper is to investigate the integration of capacitive type RF microelectromechanical systems (MEMS) switches in a standard CMOS technology. A maskless monolithic integration process dedicated to electrostatically actuated capacitive type RF MEMS switches is developed and optimized. The fabricated switches consist of composite metal-dielectric warped membranes. The warped-plate structure is used to increase the capacitance ratio

Siamak Fouladi; Raafat R. Mansour

2010-01-01

233

A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler  

Microsoft Academic Search

This paper presents the design and realization of a downconversion mixer fabricated in a standard 130 nm commercial CMOS process and aimed at applications in the 60 GHz ISM band. A balanced mixer configuration was implemented using a layout efficient 90deg hybrid coupler which serves as a diplexer to inject the LO signal while also providing two outputs with 3

R. E. Amaya; Cornelius J. Verver

2009-01-01

234

Optically Addressed CMOS Spatial Light Modulators.  

NASA Astrophysics Data System (ADS)

The thesis focuses on optically addressed spatial light modulators that consist of a complementary-metal -on-silicon (CMOS) backplane and a ferroelectric liquid crystal modulator. The CMOS chip contains combinations of photodetectors, analog/digital electronics, and liquid crystal modulators. In this manner, information is optically written to and from the spatial light modulator. This technology allows custom spatial light modulators to be easily designed and fabricated that can perform specialized functions in optoelectronic computing architectures. Three different optically addressed CMOS spatial light modulators are presented: a thresholding spatial light modulator, a pulse frequency modulated spatial light modulator, and a zero-crossing edge detection spatial light modulator. Experimental results are present for each device along with a discussion of fabrication and system issues.

Jared, David Allen

235

Design and fabrication of a CMOS-compatible MHP gas sensor  

SciTech Connect

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ?19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao; Tang, Zhenan [College of Electronic Science and Technology, Dalian University of Technology, Dalian 116024 (China)] [College of Electronic Science and Technology, Dalian University of Technology, Dalian 116024 (China)

2014-03-15

236

Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.  

PubMed

We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects. PMID:23903103

Shainline, Jeffrey M; Orcutt, Jason S; Wade, Mark T; Nammari, Kareem; Moss, Benjamin; Georgas, Michael; Sun, Chen; Ram, Rajeev J; Stojanovi?, Vladimir; Popovi?, Miloš A

2013-08-01

237

IBM: Scaling CMOS to the Limit  

NSDL National Science Digital Library

This is the latest issue of the IBM Journal of Research and Development. "This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached." Specifically, research teams report on topics such as silicon-on-insulator technology, new CMOS materials and device structures, dynamic random-access memory, and many others. The papers provide views of how far scaling could progress in the future and what constrains further advancement. Several back issues of the journal are also available, and each focuses on a different area of research.

2002-01-01

238

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

239

Double junction photodiode for X-ray CMOS sensor IC  

NASA Astrophysics Data System (ADS)

A CMOS compatible P+/Nwell/Psub double junction photodiode pixel was proposed, which can efficiently detect fluorescence from CsI(Tl) scintillation in an X-ray sensor. Photoelectric and spectral responses of P+/Nwell, Nwell/Psub and P+/Nwell/Psub photodiodes were analyzed and modeled. Simulation results show P+/Nwell/Psub photodiode has larger photocurrent than P+/Nwell photodiode and Nwell/Psub photodiode, and its spectral response is more in accordance with CsI(Tl) fluorescence spectrum. Improved P+/Nwell/Psub photodiode detecting CsI(Tl) fluorescence was designed in CSMC 0.5 ?m CMOS process, CTIA (capacitive transimpedance amplifier) architecture was used to readout photocurrent signal. CMOS X-ray sensor IC prototype contains 8 × 8 pixel array and pixel pitch is 100 × 100 ?m2. Testing results show the dark current of the improved P+/Nwell/Psub photodiode (6.5 pA) is less than that of P+/Nwell and P+/Nwell/Psub photodiodes (13 pA and 11 pA respectively). The sensitivity of P+/Nwell/Psub photodiode is about 20 pA/lux under white LED. The spectrum response of P+/Nwell/Psub photodiode ranges from 400 nm to 800 nm with a peak at 532 nm, which is in accordance with the fluorescence spectrum of CsI(Tl) in an indirect X-ray sensor. Preliminary testing results show the sensitivity of X-ray sensor IC under Cu target X-ray is about 0.21 V·m2/W or 5097e-/pixel @ 8.05 keV considering the pixel size, integration time and average energy of X-ray photons.

Chaoqun, Xu; Ying, Sun; Yan, Han; Dazhong, Zhu

2014-07-01

240

CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr  

E-print Network

#12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

Choi, Woo-Young

241

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems  

PubMed Central

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 ?) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 ?W).

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

242

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking  

PubMed Central

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-01-01

243

An image identification system of seal with fingerprint based on CMOS image sensor  

NASA Astrophysics Data System (ADS)

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analog signal conditioning circuits, A/D converter and digital processing functions. Furthermore, CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image sensor is used to identify the seal images that include fingerprint, and then determine whether the seal is fake or not. The system consists of a color CMOS image sensor (OV2610), a buffer memory, a CPLD, a MCU (P89C61X2), a USB2.0 interface chip (ISP1581) and a personal computer. The CPLD implement the logic and timing of the system. The MCU and the USB2.0 interface chip deal with the communications between the images acquisition system and PC. Thus PC can send some parameters and commands to the images acquisition system and also read image data from it. The identification of the images of seal is processed by the PC. The structure and scheme of the system are discussed in detail in this paper. Several test images of seal taken by the system are also provided in the paper.

Xue, Xu-cheng; Zhang, Shu-yan; Guo, Yong-fei

2006-01-01

244

Decoupling capacitor calculations for CMOS circuits  

Microsoft Academic Search

CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply within specification, provide signal integrity and reduce EMC\\/EMI radiated noise. Capacitor values and quantities are calculated using time and frequency domain techniques

L. D. Smith

1994-01-01

245

Minimizing power consumption in digital CMOS circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

1995-01-01

246

Low energy CMOS for space applications  

NASA Technical Reports Server (NTRS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

247

Radiation Tolerance of 65nm CMOS Transistors  

E-print Network

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

Krohn, M; Cumalat, J P; Wagner, S R; Christian, D C; Deptuch, G; Fahim, F; Hoff, J; Shenai, A

2015-01-01

248

Radiation Tolerance of 65nm CMOS Transistors  

E-print Network

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

M. Krohn; B. Bentele; J. P. Cumalat; S. R. Wagner; D. C. Christian; G. Deptuch; F. Fahim; J. Hoff; A. Shenai

2015-01-23

249

Battery-Powered Digital CMOS Massoud Pedram  

E-print Network

Energy Applications 100 mWh~2 Wh Electric watches, calculators, implanted medical devices Batteries, camcorders, lap-top computers SLI Batteries (starting, lighting and ignition) 100~600 Wh Cars, trucks, buses1 Page 1 USC Low Power CAD Massoud Pedram Battery-Powered Digital CMOS Design Massoud Pedram

Pedram, Massoud

250

Silicon on sapphire CMOS for optoelectronic microsystems  

Microsoft Academic Search

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that

A. G. Andreou; Z. K. Kalayjian; A. Apsel; P. O. Pouliquen; R. A. Athale; G. Simonis; R. Reedy

2001-01-01

251

Micromachined coplanar waveguides in CMOS technology  

Microsoft Academic Search

Coplanar waveguides were fabricated in standard complimentary metal-oxide semiconductor (CMOS) with postprocessing micromachining. ICs were designed with commercial CAD tools, fabricated through the MOSIS service, and subsequently suspended by maskless top-side etching. Absence of the lossy silicon substrate after etching results in significantly improved insertion loss characteristics, dispersion characteristics, and phase velocity. Measurements were performed at frequencies from 1 to

Veljko MilanoviC; Michael Gaitan; Edwin D. Bowen; Mona E. Zaghloul

1996-01-01

252

Failure analysis of a half-micron CMOS IC technology  

SciTech Connect

We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S. [and others

1996-08-01

253

Design and Fabrication of High-Efficiency CMOS/CCD Imagers  

NASA Technical Reports Server (NTRS)

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata

2007-01-01

254

High-Q CMOS-integrated photonic crystal microcavity devices  

PubMed Central

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10?s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31?A/W), 3?GHz bandwidth, and 30?nA dark current at a reverse bias of 30?V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

2014-01-01

255

CMOS-TDI detector technology for reconnaissance application  

NASA Astrophysics Data System (ADS)

The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

2014-10-01

256

High-Q CMOS-integrated photonic crystal microcavity devices.  

PubMed

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

2014-01-01

257

A CMOS variable gain LNA for UWB receivers  

NASA Astrophysics Data System (ADS)

A CMOS variable gain low noise amplifier (LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13-?m RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1,1) less than -9 dB and S(2,2) less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.

Feihua, Chen; Lingyun, Li; Xinzhong, Duo; Tong, Tian; Xiaowei, Sun

2011-02-01

258

A CMOS integrated circuit for pulse-shaped discrimination  

NASA Astrophysics Data System (ADS)

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the zero crossing of the shaped signal. The circuit is designed to interface with two photomultiplier tubes -- one for pulse processing and one for coincidence detection. Two Outputs from the IC, a start and stop, can be used with a high speed timing system for pulse characterization with minimal external control. The circuit was fabricated in Orbit 1.2 micrometer CMOS and operates from a 5-V supply. Specifics of the design including overall topology, charge sensitive preamplifier and CFD characteristics, shaping method and time constant selections, system timing, and implementation are discussed. Circuit performance is presented including dynamic range, timing walk, system dead time, and power consumption.

Frank, S. S.; Ericson, M. N.; Simpson, M. L.; Todd, R. A.; Hutchinson, D. P.

259

A CMOS smart temperature and humidity sensor with combined readout.  

PubMed

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

260

A CMOS Smart Temperature and Humidity Sensor with Combined Readout  

PubMed Central

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

261

CMOS low data rate imaging method based on compressed sensing  

NASA Astrophysics Data System (ADS)

Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

Xiao, Long-long; Liu, Kun; Han, Da-peng

2012-07-01

262

High-performance VGA-resolution digital color CMOS imager  

NASA Astrophysics Data System (ADS)

This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

1999-04-01

263

X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application  

NASA Astrophysics Data System (ADS)

This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 ?m 1 Poly 4 Metal CMOS process. The pixel size is 100 ?m×100 ?m and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

2013-12-01

264

A Transformer Noise-Canceling Ultra-Wideband CMOS Low-Noise Amplifier  

NASA Astrophysics Data System (ADS)

Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originating from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) applications is implemented in a 90nm digital CMOS process. It occupies 0.12mm2 and achieves |S11| < -10dB, NF < 4.4dB, and |S21| > 9.3dB across 3.1-10.6GHz with a power consumption of 2.5mW from a 1.0V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.

Kihara, Takao; Matsuoka, Toshimasa; Taniguchi, Kenji

265

77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...  

Federal Register 2010, 2011, 2012, 2013, 2014

...337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Institution...after importation of certain CMOS image sensors and products containing same by reason...after importation of certain CMOS image sensors and products containing same that...

2012-06-06

266

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Docket No. 2895] Certain CMOS Image Sensors and Products Containing Same; Notice...complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895...after importation of certain CMOS image sensors and products containing same. The...

2012-05-07

267

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors  

PubMed Central

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

268

Thirty megarad CMOS gate array for spacecraft applications  

SciTech Connect

The recent development, testing, qualification and integration for spacecraft applications of a general purpose, 30 Megarad-hard, CMOS logic gate array having 3000 transistors is reported. Fabricated on the National Semiconductor, Inc. class S radation-hard line, the gate array operates at >3 MHz (10V) after 10/sup 7/ rad(Si) total dose from a Co/sup 60/ source. The threshold voltage change is 0.2 volts (0.5 volts) for the n-channel (p-channel) devices under 10V bias conditions. The rad-hard process of the CDI gate array family is mask compatible with the conventional process for cost effective semicustom design. The rad-hard array is presently operating in-orbit on the AMPTE satellite and is planned for instruments to be flown on the CRRES and UARS satellites.

Voss, H.D.; Hardage, C.; Jones, F.C.; Roffelsen, L.

1984-12-01

269

Analysis and optimization of BiCMOS digital circuit structures  

Microsoft Academic Search

Circuit analyses and performance optimization are presented of three basic BiCMOS digital circuit structures: BiCMOS buffer, NMOS\\/CML (coupled-mode logic), and ECL (emitter-coupled logic)\\/CMOS interface circuits. The analytical modeling of the transient behavior offers insight into the critical circuit and device parameters that affect the performance of these circuits. Techniques to improve the speed of each structure and the tradeoff factors

S. H. K. Embabi; A. Bellaouar; M. I. Elmasry

1991-01-01

270

Biomimetic sampling architectures for CMOS image sensors  

NASA Astrophysics Data System (ADS)

We demonstrate a non-orthogonal architecture for a CMOS active pixel image sensor, called here pyramid architecture, for improved two-dimensional spatial sampling. In the pyramid architecture 2D sampling using concentric rings replaces the 1D row sampling in the classical imager architecture, and diagonal output busses replace the conventional vertical column busses. Moreover, we propose a scanning scheme in which, instead of rolling over to the first ring (or row) at the end of image capture, the scan returns from the outer ring towards the first inner ring at the centre of the sensor. This leads to two scenes of differing integration times that, after being fused, results in a foveated increase in intra-scene dynamic range. Results from a sensor fabricated in 0.18?m CMOS technology are presented and discussed. We will also present a multi-resolution architecture which is based on the pixel structures as building block to control the acquired image resolution.

Saffih, Faycal; Hornsey, Richard

2004-06-01

271

OPASYN: a compiler for CMOS operational amplifiers  

Microsoft Academic Search

A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and

Han Young Koh; Carlo H. Séquin; Paul R. Gray

1990-01-01

272

Thermoelectric AC power sensor by CMOS technology  

Microsoft Academic Search

The authors report the development of a thermoelectric AC power sensor (thermoconverter) realized by industrial CMOS IC technology in combination with postprocessing micromachining. The sensor is based on a polysilicon heating resistor and a polysilicon\\/aluminum thermopile integrated on an oxide microbridge. The thermopile sensitivity is 9.9 mV\\/mW and the burn-out power of the sensor is 50 mW. The time constant

Dominik Jaeggi; Henry Baltes; David Moser

1992-01-01

273

Monolithic high-speed CMOS-photoreceiver  

Microsoft Academic Search

Results of optoelectronic integrated CMOS receivers for applications in optical data transmission and in optical interconnects are presented. The rise and fall times of the integrated p-i-n photodiodes (PDs) are 0.19 and 0.24 ns, respectively, corresponding to -3 dB bandwidths in excess of 1.4 GHz. These PDs combine this high speed with a high quantum efficiency. Rise and fall times

H. Zimmermann; T. Heide; A. Ghazi

1999-01-01

274

CMOS Camera Array With Onboard Memory  

NASA Technical Reports Server (NTRS)

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Gat, Nahum

2009-01-01

275

Single-chip CMOS optical microspectrometer  

Microsoft Academic Search

Numerous applications, e.g., systems for chemical analysis by optical absorption and emission line characterization, will benefit from the availability of low-cost single-chip spectrometers. A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry–Perot etalons (each one with different resonance cavity length), photodetectors and circuits for read-out, multiplexing and driving a serial bus interface has been fabricated. The result

J. H. Correia; G. de Graaf; S. H. Kong; M. Bartek; R. F. Wolffenbuttel

2000-01-01

276

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

NASA Astrophysics Data System (ADS)

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-11-01

277

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

PubMed Central

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

2013-01-01

278

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.  

PubMed

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-01-01

279

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

280

Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets  

NASA Astrophysics Data System (ADS)

A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

2014-01-01

281

A new visible watermarking technique applied to CMOS image sensor  

NASA Astrophysics Data System (ADS)

This paper presents a new visible watermarking solution for CMOS image sensor which can enhance secure features of captured images. Visible watermarks are embedded in the Bayer format image data and can be transferred by the subsequent interpolation process. A piecewise function is setup based on the gray scale resolution characteristics of human eyes. Watermark stretch factor can be adaptively chosen according to the gray value of the current pixel. The advantage of this algorithm is that the watermark has the same visibility in different image brightness region. A number of color images have been used to test the method. In order to check the robustness of watermarked images, we conducted adding noise and filtering experiments, results show that the visibility of watermark is also good after the experiments. The approach allows a digital watermark to be embedded in an image immediately upon its capture, before leaving the imaging chip.

Yu, Pingping; Shang, Yan; Li, Chunming

2013-10-01

282

Measurements on HV-CMOS Active Sensors After Irradiation to HL-LHC fluences  

E-print Network

During the long shutdown (LS) 3 beginning 2022 the LHC will be upgraded for higher luminosities pushing the limits especially for the inner tracking detectors of the LHC experiments. In order to cope with the increased particle rate and radiation levels the ATLAS Inner Detector will be completely replaced by a purely silicon based one. Novel sensors based on HV-CMOS processes prove to be good candidates in terms of spatial resolution and radiation hardness. In this paper measurements conducted on prototypes built in the AMS H18 HV-CMOS process and irradiated to fluences of up to $2\\cdot10^{16}\\,\\text{n}_\\text{eq}\\text{cm}^{-2}$ are presented.

B. Ristic; for the ATLAS CMOS pixel collaboration

2015-01-13

283

Unified Challenges inUnified Challenges in NanoNano--Unified Challenges inUnified Challenges in NanoNano CMOS HighCMOS High--Level SynthesisLevel Synthesis  

E-print Network

Aff t ti liincreasing. Affect energy consumption, cooling costs, packaging costs. 12/4/2008 Unified. 1967 2007 VLSI technology is the fastest growing technology in human history. 12/4/2008 4 1967 2007 together in the same die. · Smaller Process Technology: Use of smaller nanoscale CMOS technology, 32nm node

Mohanty, Saraju P.

284

A 1.5-V, 1.5GHz CMOS low noise amplifier  

Microsoft Academic Search

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-?m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis

Derek K. Shaeffer; Thomas H. Lee

1997-01-01

285

GaN-Based Power LEDs With CMOS ESD Protection Circuits  

Microsoft Academic Search

A power light-emitting diode (LED) module has been successfully designed and demonstrated by combining GaN-based power LEDs with CMOS electrostatic discharge (ESD) protection circuits through a flip-chip process. It was found that we could enhance the power LED output intensity by 20% by using the flip-chip technology. Lifetimes of flip-chip power LEDs were also found to be better. It was

J. J. Horng; Y. K. Su; S. J. Chang; W. S. Chen; S. C. Shei

2007-01-01

286

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry  

Microsoft Academic Search

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and

Cristian Marcu; Debopriyo Chowdhury; Chintan Thakkar; Jung-Dong Park; Ling-Kai Kong; Maryam Tabesh; Yanjie Wang; Bagher Afshar; Abhinav Gupta; Amin Arbabian; Simone Gambini; Reza Zamani; Elad Alon; Ali M. Niknejad

2009-01-01

287

High-performance 0.25-um CMOS technology for fast SRAMs  

Microsoft Academic Search

A high performance 0.25 micrometers CMOS process has been developed for fast static RAMs. This technology features retrograde wells, shallow trench isolation scalable to a 0.45 micrometers active pitch, surface channel 0.25 micrometers NMOS and PMOS transistors with a 55 angstroms nitrided gate oxide providing drive currents of 630 and 300 (mu) A\\/micrometers respectively at off-leakages of 10 pA\\/micrometers ,

James D. Hayden; T. F. McNelly; A. H. Perera; J. R. Pfiester; C. K. Subramanian; Matthew A. Thompson

1996-01-01

288

Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs  

Microsoft Academic Search

A new on-chip RC-based transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed, which can detect fast electrical transients during the system-level ESD test. A novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18- mum CMOS process with 3.3-V devices. The

Ming-Dou Ker; Cheng-Cheng Yen

2009-01-01

289

0.13-?m CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays  

Microsoft Academic Search

Two 4-bit active phase shifters integrated with all digital control circuitry in 0.13-mum RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter

Kwang-Jin Koh; Gabriel M. Rebeiz

2007-01-01

290

K- and Q-bands CMOS frequency sources with X-band quadrature VCO  

Microsoft Academic Search

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-?m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To

Sangsoo Ko; Jeong-Geun Kim; Taeksang Song; Euisik Yoon; Songcheol Hong

2005-01-01

291

A CMOS\\/LCOS image transceiver chip for smart goggle applications  

Microsoft Academic Search

The design of a novel, CMOS-liquid-crystal-based image transceiver device (ITD) is described. The device combines both functions of imaging and display by means of a dual-function array formed in a single-processed chip. The image transceiver system design allows the integration of the see-through, aiming, imaging, and display of a superposed image into a single, compact, head-mounted goggle. The timing, sequencing,

Uzi Efron; I. David; Vladimir Sinelnikov; B. Apter

2004-01-01

292

A CMOS mixed-signal 100 Mb\\/s receive architecture for fast Ethernet  

Microsoft Academic Search

A 125 Mbaud quad transceiver for 10\\/100 fast Ethernet has been designed in a 5 V 0.35 ?m digital CMOS process. Power consumption for the device is 3 W. Detailed testing show excellent receiver results with error free performance up to 160 m under worst-case baseline wander and crosstalk conditions. The analog receiver uses digital adaptation circuitry to optimize an

Ayal Shoval; Omid Shoaei; K. O. Lee; R. H. Leonowich

1999-01-01

293

A dual-speed 125 Mbaud\\/10 Mbaud CMOS transmitter for Fast Ethernet  

Microsoft Academic Search

A 10 Mbaud waveshaping and current-mode line driver for 10Base-T and a 125 Mbaud current-mode line driver for 100Base-TX\\/FX dual-speed transmitter for a Fast Ethernet transceiver chip are presented. Their power consumption from a single 5 V supply are 200 mW and 125 mW respectively. Transmitter die area for both is 0.764 mm2 in a 0.35 ?m digital CMOS process

Omid Shoaei; Ayal Shoval; Robert H. Leonowich

1999-01-01

294

A 300MHz 64-b quad-issue CMOS RISC microprocessor  

Microsoft Academic Search

This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm×18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 ?m, CMOS process. The upper metal layers (metal-3 and metal-4), primarily

B. J. Benschneider; A. J. Black; W. J. Bowhill; S. M. Britton; D. E. Dever; D. R. Donchin; R. J. Dupcak; R. M. Fromm; M. K. Gowan; P. E. Gronowski; M. Kantrowitz; M. E. Lamere; S. Mehta; J. E. Meyer; R. O. Mueller; A. Olesin; R. P. Preston; D. A. Priore; S. Santhanam; M. J. Smith; G. M. Wolrich

1995-01-01

295

An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications  

Microsoft Academic Search

The proposed transmitter chip is fabricated in a standard 0.25 ?m single-poly-five-metal CMOS process with low resistance substrate. It consists of a quadrature modulator, a quadrature VCO, and a power amplifier. This transmitter IC consumes only 45 mA from a 2.5 V power supply voltage. With highly linear quadrature modulator and low phase-error quadrature VCO structure, the measured LO leakage,

Hong-sing Kao; Chung-yu Wu

2002-01-01

296

A Low-Power Ultra-Wideband CMOS True RMS Power Detector  

Microsoft Academic Search

This paper introduces a low-power ultra-wideband true root-mean-square power detector with a 0.13-mum CMOS process operating from 125 MHz to 8.5 GHz. The detector utilizes the MOS transistor's square-law characteristic in the strong inversion region to obtain the power information of the input RF signal, and its exponential characteristic in the weak inversion region to realize the linear-in-decibel output. Measured

Yijun Zhou; Michael Yan-Wah Chia

2008-01-01

297

Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits  

Microsoft Academic Search

This paper explores an unexpected link between system-level security considerations and deep-submicron CMOS circuits. Many deep-submicron effects including increased leakage power, process variability, noise-level, power- density and integration density are thought of to be liabilities for integrated design. However, we show how they may instead be an asset for certain types of secure circuits. These circuits are useful for secure

Patrick Schaumont; David D. Hwang

2008-01-01

298

A 2.87?ppm\\/°C 65?nm CMOS bandgap reference with nonlinearity compensation  

Microsoft Academic Search

Based on the review and analysis of two recently reported low temperature coefficient (TC) bandgap voltage references (BGRs), a new temperature compensation technique is presented. With the double-end piecewise nonlinearity correction method, the logarithm cancellation technique and the mixed-mode output topology, a BGR with high-temperature stability is realised based on 65?nm CMOS low-leakage process. The post-simulation results using Spectre show

Tong Xingyuan; Zhu Zhangming; Yang Yintang

2011-01-01

299

A resonant switch for LNA protection in watt-level CMOS transceivers  

Microsoft Academic Search

An integrated resonant switch designed to protect low-noise amplifier (LNA) circuits in CMOS transceivers is reported. The design implements the receive-path portion of a transmit\\/receive switch protecting 3-V-process transistors from 5 W (22-V peak) transmit signals while simultaneously helping to achieve a good LNA noise figure on receive and low power loss on transmit. Since the approach is to combine

William B. Kuhn; Mohammad M. Mojarradi; Alina Moussessian

2005-01-01

300

Industrial CMOS technology for the integration of optical metrology systems (photo-ASICs)  

Microsoft Academic Search

With 'photo-ASKS' comprlsmg hght-sensitive structures, hght-emmmg devices and analog and chgtal clrcults, complete optlcal metrology systems can be Integrated on a smgle chip We report the reahzatlon of key components of such photo-ASICs usmg an mdustrual IC CMOS process We achieve photodlodes with an external quantum efficiency of 50-80% m the visible spectrum and posItIon-sensltlve devices (PSDs) with a spatial

J. Kramer; P Seltz; H. Baltes

1992-01-01

301

Key sub 1nm EOT CMOS enabler by comprehensive PMOS design  

Microsoft Academic Search

A high performance CMOS HK\\/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA\\/?m with VDD = 1 V are 1.25 mA\\/?m and 0.56 mA\\/?m for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region.

J. Tseng; L.-A. Ragnarsson; T. Schram; A. Akheyar; Y. Okuno; Z. L. Li; M. Aoulaiche; E. Rohr; T. Witters; C. Adelmann; A. Delabie; V. Paraschiv; C. Kerner; K. Xiong; M. Mueller; T. Hoffmann; P. Absil; S. Biesemans

2010-01-01

302

Low standby power CMOS with HfO2 gate oxide for 100-nm generation  

Microsoft Academic Search

We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO2 gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S\\/D anneal of ?1000°C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.

S. Pidin; Y. Morisaki; Y. Sugita; T. Aoyama; K. Irino; T. Nakamura; T. Sugii

2002-01-01

303

Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials  

Microsoft Academic Search

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 mum 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of

Mohsen Mollazadeh; Kartikeya Murari; Gert Cauwenberghs; Nitish Thakor

2009-01-01

304

A micropower class AB CMOS log-domain filter for DECT applications  

Microsoft Academic Search

This paper presents a micropower 2nd-order low-pass filter using the log-domain principle and integrated in a 0.35 µm CMOS process. It has been designed as an anti-aliasing filter for a DECT transceiver with a 45 kHz nominal cut-off frequency. The circuit uses transistors biased in weak inversion without requiring separate wells. It operates at 1.5V supply voltage and its current

D. Python; C. C. Enz

2000-01-01

305

80 nm poly-Si gate CMOS with HfO2 gate dielectric  

Microsoft Academic Search

We report here for the first time the formation of an amorphous oxide layer between the polysilicon gate and hafnium oxide (HfO2 ) gate dielectric due to a lateral oxidation mechanism at the gate edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv of 25 Å with

C. Hobbs; H. Tseng; K. Reid; B. Taylor; L. Dip; L. Hebert; R. Garcia; R. Hegde; J. Grant; D. Gilmer; A. Franke; V. Dhandapani; M. Azrak; L. Prabhu; R. Rai; S. Bagchi; J. Conner; S. Backer; F. Dumbuya; B. Nguyen; P. Tobin

2001-01-01

306

CMOS chip for biomedical telemetry with hf power supply  

Microsoft Academic Search

This paper aims at describing a miniaturized CMOS implant- circuit for human medical telemetry. The chip includes a silicon antenna working on the principle of inductive coil coupling through the skin, an rf rectifier for power supply, an hf filter and logic circuitry for chip control. A CMOS compatible temperature sensor is included in the same chip. The obtained measurements

Sonia Delmas; Marcin Kaluza; Fabrice Caignet; Etienne Sicard

1996-01-01

307

Performance computation for precharacterized CMOS gates with RC loads  

Microsoft Academic Search

For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This

Florentin Dartu; Noel Menezes; Lawrence T. Pileggi

1996-01-01

308

Contactless fluorescence imaging with a CMOS image sensor  

Microsoft Academic Search

In this work, we utilize a CMOS active pixel sensor in a fluorescence imaging setup. The ability to sense small light intensity changes on top of a large baseline with spatial resolution at the subcellular scale is required in fluorescence imaging. The CMOS imager presented in (1) is perfect for this application with the ability to resolve fine features coupled

Andreas G. Andreou; Zhaonian Zhang; Recep Ozgun; Edward T. Choi; Zaven K. Kalayjian; Miriam A. Marwick; Jennifer Blain Christen; Leslie Tung

2011-01-01

309

A CMOS fault extractor for inductive fault analysis  

Microsoft Academic Search

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list

F. Joel Ferguson; John Paul Shen

1988-01-01

310

GaAs MQW modulators integrated with silicon CMOS  

Microsoft Academic Search

We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32×32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor

K. W. Goossen; J. A. Walker; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. D. Bacon; D. Dahringer; L. M. F. Chirovsky; A. L. Lentine; D. A. B. Miller

1995-01-01

311

RF power potential of 45 nm CMOS technology  

E-print Network

This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

Putnam, Christopher

312

Quiescent power supply current measurement for CMOS IC defect detection  

Microsoft Academic Search

Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer

CHARLES F. HAWKINS; JERRY M. SODEN; RONALD R. FRITZEMEIER; LUTHER K. HORNING

1989-01-01

313

Autonomous mobile mini-robot with embedded CMOS vision system  

Microsoft Academic Search

This paper presents a prototype of a mobile minirobot with an embedded vision system. The robot control is implemented in a low cost microcontroller and the vision system is based in a proprietary CMOS imaging array. The proposed vision sensor has enough flexibility to be incorporated directly to most microcontroller-based systems without any additional electronics. The CMOS camera sensor has

J. Palacin; A. Sanuy; X. Clua; G. Chapinal; S. Bota; M. Moreno; A. Herms

2002-01-01

314

High-performance monolithic CMOS detectors for space applications  

Microsoft Academic Search

During the last 10 years, research about CMOS image sensors (also called APS - Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on

Olivier Saint-Pe; Michel Tulet; Robert Davancens; Franck Larnaudie; Bruno Vignon; Pierre Magnan; Jean A. Farre; Franck Corbiere; Philippe Martin-Gonthier

2001-01-01

315

Simultaneous switching ground noise calculation for packaged CMOS devices  

Microsoft Academic Search

Here, it is assumed that the internal switching current is small compared to the output driver switching current. In the past, it was assumed that simultaneous switching noise created by CMOS outputs was directly proportional to the number of outputs switching simultaneously. Recent studies indicate that CMOS circuits exhibit sublinear behavior (due to the negative feedback influence) of power\\/ground noise

R. Senthinathan; J. L. Prince

1991-01-01

316

A 1-V CMOS log-domain integrator  

Microsoft Academic Search

A novel circuit implementation of a CMOS log-domain integrator is presented. Unlike most other implementations, it does not require placing of MOSFETs in separated wells, and therefore allows very compact filters, which are fully compatible with modern standard CMOS technologies. Besides the saving of chip area, this also helps to reduce parasitic capacitances. The most important advantage of this circuit

Dominique Python; Manfred Punzenberger; Christian C. Enz

1999-01-01

317

Electrostatically driven micro resonator with a CMOS capacitive read out  

Microsoft Academic Search

An electrostatically driven micro resonator is fabricated from single-crystal silicon, using micromachining techniques. The displacement amplitude is measured through differential capacitance measurement, implemented on a CMOS interface circuit, which also provides the excitation clocks for the resonator. The unique feature of this micromechanical system is the integration method applied for attaching the resonator to the CMOS chip. The integration is

Yinon Satuby; Uri Ben-Yehuda; Claudio G. Jakobson; Jacob Shneider; D. Lavie; Y. Nemirovsky; S. Kaldor; M. Hershkovitz; E. Netzer

1995-01-01

318

High responsivity CMOS imager pixel implemented in SOI technology  

NASA Technical Reports Server (NTRS)

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

319

CMOS temperature sensor utilizing interface-trap charge pumping  

E-print Network

Silicon Temperature Sensors Three devices used in CMOS technology for temperature sensing are lateral bipo- lar transistors, vertical bipolar transistors, and CMOS transistors operating in weak inversion [9]. These sensors usually rely on proportional... . . . . . . . . . . . . . . . . . . . . 27 V TESTING AND CHARACTERIZATION . . . . . . . . . . . . . 32 A. ITCP Current Source Characterization . . . . . . . . . . . 33 1. Temperature Sensitivity . . . . . . . . . . . . . . . . . 39 B. Leakage Device Characterization...

Berber, Feyza

2006-10-30

320

Cost-Effective 28-nm LSTP CMOS using gate-first metal gate\\/high-k technology  

Microsoft Academic Search

Metal gate\\/high-k CMOS technology for 28-nm node low power and low standby power application is demonstrated. A gate-first single metal\\/high-k gate stack has been employed together with leading-edge isolation, ultra-shallow junction, and stress engineering technologies. High density and high performance device is provided with least process cost increase.

T. Tomimatsu; Y. Goto; H. Kato; M. Amma; M. Igarashi; Y. Kusakabe; M. Takeuchi; S. Ohbayashi; S. Sakashita; T. Kawahara; M. Mizutani; M. Inoue; M. Sawada; Y. Kawasaki; S. Yamanari; Y. Miyagawa; Y. Takeshima; Y. Yamamoto; S. Endo; T. Hayashi; Y. Nishida; K. Horita; T. Yamashita; H. Oda; K. Tsukamoto; Y. Inoue; H. Fujimoto; Y. Sato; K. Yamashita; R. Mitsuhashi; S. Matsuyama; Y. Moriyama; K. Nakanishi; T. Noda; Y. Sahara; N. Koike; J. Hirase; T. Yamada; H. Ogawa; M. Ogura

2009-01-01

321

1832 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011 CMOS Technology Scaling Considerations for  

E-print Network

higher volumes for optoelectronic components than long-haul communication, they are more cost- munication into standard nanoscale CMOS process technologies can enable low cost for emerging high volume longer distances. For long-haul communication the superior signal integrity of optical links

Chan Carusone, Tony

322

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1, FEBRUARY 1988 159 A High-Speed CMOS Comparator  

E-print Network

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1, FEBRUARY 1988 159 A High-Speed CMOS a standard 3- pm process. A dynamic latch preceded by an offset-cancelled amplifier is used to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium

Lee, Hae-Seung "Harry"

323

Fundamental performance differences between CMOS and CCD imagers, part IV  

NASA Astrophysics Data System (ADS)

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8?m 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 ?m and 10k × 10k × 10 um imager formats.

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

324

CMOS-MEMS resonator as a signal generator for fully-adiabatic logic circuits  

NASA Astrophysics Data System (ADS)

Fully-adiabatic (thermodynamically reversible) logic is one of the few promising approaches to low-power logic design. To maximize the system power-performance of an adiabatic circuit requires an ultra low-loss on-chip clock source, which can generate an output signal with a quasi-trapezoidal (flat-topped) voltage waveform. In this paper, we propose to use high-Q MEMS resonators to generate the custom waveform. The big challenge in the MEMS resonator design is that a non-sinusoidal (quasi-trapezoidal) waveform needs to be generated even though the resonator oscillates sinusoidally. Our solution is to customize the shape of the sensing comb fingers of the resonator, with the result that the sensing capacitance varies quasi-trapezoidally. The effective quality factor and the area-efficiency of the microstructure have been optimized so as to minimize the whole system"s power dissipation and cost at a given frequency. A resonator design with a 100 kHz resonant frequency based on a standard TSMC 0.35?m CMOS process has been fabricated. The resonator has an area of 300 ?m by 160 ?m with a thickness of 30 ?m. Three-dimensional field simulation shows that the resonator generates a quasi-trapezoidal waveform when it operates at its resonance. An on-chip buffer is also designed for monitoring the waveform generated by the MEMS resonator. The post-CMOS fabrication process is compatible with standard CMOS processes. Thus the custom clock generator can be integrated with logic circuits on the same CMOS chip. The size of the MEMS resonator can be further reduced by design optimization and advances in micro/nano-fabrication technology.

He, Maojiao; Frank, Michael P.; Xie, Huikai

2005-02-01

325

Post-CMOS Parylene Packaging for On-chip Biosensor Arrays  

E-print Network

Post-CMOS Parylene Packaging for On-chip Biosensor Arrays Lin Li Department of Electrical as an open challenge. This paper presents a robust and reliable packaging scheme for on-CMOS biosensors CMOS die. Photos of a packaged CMOS biosensor array chip and electrochemical measurements in potassium

Mason, Andrew

326

Packaging commercial CMOS chips for lab on a chip integration.  

PubMed

Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

2014-05-21

327

Ultra low power CMOS technology  

NASA Technical Reports Server (NTRS)

This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

Burr, J.; Peterson, A.

1991-01-01

328

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.  

PubMed

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications. PMID:20040430

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

329

Terahertz Imaging Detectors in CMOS Technology  

Microsoft Academic Search

Square-law power detection circuits with on-chip antennas and amplifiers are presented for the detection of 0.65-THz radiation\\u000a in a low-cost 0.25-?m CMOS technology. The circuit architecture combines metal-insulator-metal (MIM) coupling capacitors with NMOS transistors\\u000a to facilitate self-mixing in a resistive mixer. A low-frequency (quasi-static) and a high-frequency (non-quasi-static) analysis\\u000a of the broad-band circuit is presented. Current and voltage readout techniques

Erik Öjefors; Alvydas Lisauskas; Diana Glaab; Hartmut G. Roskos; Ullrich R. Pfeiffer

2009-01-01

330

Vertical Isolation for Photodiodes in CMOS Imagers  

NASA Technical Reports Server (NTRS)

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Pain, Bedabrata

2008-01-01

331

CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics  

NASA Astrophysics Data System (ADS)

A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

Sawadsaringkarn, Y.; Kimura, H.; Maezawa, Y.; Nakajima, A.; Kobayashi, T.; Sasagawa, K.; Noda, T.; Tokuda, T.; Ohta, J.

2012-03-01

332

3D integration of planar crossbar memristive devices with CMOS substrate.  

PubMed

Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. PMID:25224779

Lin, Peng; Pi, Shuang; Xia, Qiangfei

2014-10-10

333

3D integration of planar crossbar memristive devices with CMOS substrate  

NASA Astrophysics Data System (ADS)

Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing.

Lin, Peng; Pi, Shuang; Xia, Qiangfei

2014-10-01

334

Noise behavior of a 180-nm CMOS SOI technology for detector front-end electronics  

SciTech Connect

This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully depleted SOI devices as a reference. The comparison in terms of white and 1/f noise components with bulk MOSFETs with the same minimum feature size gives a basis of estimate for the signal-to-noise ratio achievable in detector front-end integrated circuits designed in an SOI technology.

Re, Valerio; /Bergamo U. /INFN, Pavia; Gaioni, Luigi; /Pavia U. /INFN, Pavia; Manghisoni, Massimo; /Bergamo U. /INFN, Pavia; Ratti, Lodovico; /Pavia U. /INFN, Pavia; Speziali, Valeria; /Pavia U. /INFN, Pavia; Traversi, Gianluca; /Bergamo U. /INFN, Pavia; Yarema, Ray; /Fermilab

2008-01-01

335

MNOS stack for reliable, low optical loss, Cu based CMOS plasmonic devices.  

PubMed

We study the electro optical properties of a Metal-Nitride-Oxide-Silicon (MNOS) stack for a use in CMOS compatible plasmonic active devices. We show that the insertion of an ultrathin stoichiometric Si(3)N(4) layer in a MOS stack lead to an increase in the electrical reliability of a copper gate MNOS capacitance from 50 to 95% thanks to a diffusion barrier effect, while preserving the low optical losses brought by the use of copper as the plasmon supporting metal. An experimental investigation is undertaken at a wafer scale using some CMOS standard processes of the LETI foundry. Optical transmission measurments conducted in a MNOS channel waveguide configuration coupled to standard silicon photonics circuitry confirms the very low optical losses (0.39 dB.?m(-1)), in good agreement with predictions using ellipsometric optical constants of Cu. PMID:22714426

Emboras, Alexandros; Najar, Adel; Nambiar, Siddharth; Grosse, Philippe; Augendre, Emmanuel; Leroux, Charles; de Salvo, Barbara; de Lamaestre, Roch Espiau

2012-06-18

336

A low noise CMOS RF front-end for UWB 6-9 GHz applications  

NASA Astrophysics Data System (ADS)

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 ?m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

Feng, Zhou; Ting, Gao; Fei, Lan; Wei, Li; Ning, Li; Junyan, Ren

2010-11-01

337

High-speed camera based on a CMOS active pixel sensor  

NASA Astrophysics Data System (ADS)

Standard CMOS technologies offer great flexibility in the design of image sensors, which is a big advantage especially for high framerate system. For this application we have integrated an active pixel sensor with 256 X 256 pixel using a standard 0.5 micrometers CMOS technologies. With 16 analog outputs and a clockrate of 25-30 MHz per output, a continuous framerate of more than 50000 Hz is achieved. A global synchronous shutter is provided, but it required a more complex pixel circuit of five transistors and a special pixel layout to get a good optical fill factor. The active area of the photodiode is 9 X 9 micrometers . These square diodes are arranged in a chess pattern, while the remaining space is used for the electronic circuit. FIll factor is nearly 50 percent. The sensor is embedded in a high-speed camera system with 16 ADCs, 256Mbyte dynamic RAM, FPGAs for high-speed real time image processing, and a PC for user interface, data archive and network operation. Fixed pattern noise, which is always a problem of CMOS sensor, and the mismatching of the 16 analog channels is removed by a pixelwise gain-offset correction. After this, the chess pattern requires a reconstruction of all the 'missing' pixels, which can be done by a special edge sensitive algorithm. So a high quality 512 X 256 image with low remaining noise can be displayed. Sensor, architecture and processing are also suitable for color imaging.

Bloss, Hans S.; Ernst, Juergen D.; Firla, Heidrun; Schmoelz, Sybille C.; Gick, Stephan K.; Lauxtermann, Stefan C.

2000-02-01

338

Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems  

Microsoft Academic Search

In this paper, we present a vision for the cointegration of deeply scaled complementary metal-oxide-semiconductor (CMOS) and emerging nanoelectronic devices into CMOS-hybrid systems. These hybrid systems will create new functionality, modality and add value to existing CMOS integrated circuits. We describe several new nanoelectronic devices which may enable new dimensions to traditional CMOS circuits and systems that build on CMOS

David S. Ricketts; James A. Bain; Yi Luo; R. D. Blanton; Kenneth Mai; Gary K. Fedder

2010-01-01

339

Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS  

SciTech Connect

Recently, a great deal of interest has developed in manufacturing processes that allow the monolithic integration of MicroElectroMechanical Systems (MEMS) with driving, controlling, and signal processing electronics. This integration promises to improve the performance of micromechanical devices as well as lower the cost of manufacturing, packaging, and instrumenting these devices by combining the micromechanical devices with a electronic devices in the same manufacturing and packaging process. In order to maintain modularity and overcome some of the manufacturing challenges of the CMOS-first approach to integration, we have developed a MEMS-first process. This process places the micromechanical devices in a shallow trench, planarizes the wafer, and seals the micromechanical devices in the trench. Then, a high-temperature anneal is performed after the devices are embedded in the trench prior to microelectronics processing. This anneal stress-relieves the micromechanical polysilicon and ensures that the subsequent thermal processing associated with fabrication of the microelectronic processing does not adversely affect the mechanical properties of the polysilicon structures. These wafers with the completed, planarized micromechanical devices are then used as starting material for conventional CMOS processes. The circuit yield for the process has exceeded 98%. A description of the integration technology, the refinements to the technology, and wafer-scale parametric measurements of device characteristics is presented. Additionally, the performance of integrated sensing devices built using this technology is presented.

Smith, J.H.; Montague, S.; Sniegowski, J.J.; Murray, J.R. [and others

1996-10-01

340

Far ultraviolet sensitivity of silicon CMOS sensors  

NASA Astrophysics Data System (ADS)

We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K × 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

2012-07-01

341

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers  

NASA Technical Reports Server (NTRS)

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

342

Designing and implementing a miniature CMOS imaging system with USB interface  

NASA Astrophysics Data System (ADS)

Although CMOS cameras with USB interface are popular, their sizes are not small enough and working lengths are not that long enough when used as industrial endoscope. Here we present a small-sized image acquisition system for high-definition industrial electronic endoscope based on USB2.0 high-speed controller, which is composed of a 1/6 inch CMOS image sensor with resolution of 1 Megapixels. Signals from the CMOS image sensor are put into computer through the USB interface using the slave FIFO mode for processing, storage and display. LVDS technology is used for image data stream transmission between the sensor and USB controller to realize a long working distance, high signal integrity and low noise system. The maximum pixel clock runs at 48MHz to support for 30 fps for QSXGA mode or15 fps for SXGA mode and the data transmission rate can reach 36 megabytes per second. The imaging system is simple in structure, low-power, low-cost and easy to control. Based on multi-thread technology, the software system which realizes the function of automatic exposure, automatic gain, and AVI video recording is also designed.

Yao, Chenyun; Wang, Liqiang; Yuan, Bo; Xu, Jin

2012-11-01

343

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip  

NASA Astrophysics Data System (ADS)

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

344

Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter  

NASA Astrophysics Data System (ADS)

The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.

Naumowicz, M.; Melosik, M.; Katarzynski, P.; Handkiewicz, A.

2013-09-01

345

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate  

NASA Astrophysics Data System (ADS)

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of circulator shows how crucial this device is to many industries and the need for smaller, cost effective RF components.

Oukacha, Hassan

346

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits  

NASA Technical Reports Server (NTRS)

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Blaes, B. R.; Soli, G. A.; Buehler, M. G.

1991-01-01

347

High-speed multicolour photometry with CMOS cameras  

NASA Astrophysics Data System (ADS)

We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ?14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

2012-11-01

348

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies  

E-print Network

CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

Brooks, Lane Gearle, 1975-

2008-01-01

349

A study of CMOS technologies for image sensor applications  

E-print Network

CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

Wang, Ching-Chun, 1969-

2001-01-01

350

Strain-engineered CMOS-compatible Ge photodetectors  

E-print Network

The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

Cannon, Douglas Dale, 1974-

2004-01-01

351

Fabrication and simulation of CMOS-compatible photodiodes  

E-print Network

CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

DiLello, Nicole Ann

2008-01-01

352

A silicon avalanche photodetector fabricated with standard CMOS technology  

E-print Network

A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain a silicon avalanche photodetector (APD) fabricated with standard complementary metal-well junction, and its current-voltage characteristics, responsivity, avalanche gain, and photodetection

Choi, Woo-Young

353

Formal specification of a high speed CMOS correlator  

NASA Technical Reports Server (NTRS)

The formal specification of a high speed CMOS correlator is presented. The specification gives the high-level behavior of the correlator and provides a clear, unambiguous description of the high-level architecture of the device.

Windley, P. J.

1991-01-01

354

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology  

NASA Technical Reports Server (NTRS)

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

355

High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector  

E-print Network

and compared with the simulation results. Frequency limitations were encountered during the testing process due to unexpected increase in the value of the N-well resistors. All other problems faced during the testing, as well as the results obtained so far...

Venkatasubramanian, Radhika

2007-04-25

356

CMOS image sensors optimised for GEO observation  

NASA Astrophysics Data System (ADS)

CMOS Image Sensors (CIS) arrays have well proven their capabilities to address the growing need of space imaging from the GEO orbit within the visible and near infrared spectral bands. The main interesting features of CIS detectors for such applications are smearing-free capability, small pixel pitches even with large charge handling capacity, fine tuning of QE and MTF, low power dissipation, exposure control and good radiation behaviour. This paper will present new results obtained by our team in the field of development of such 2D arrays, including large format detectors (up to 12 million pixels), front and back side illuminations, 3T and 4T pixels, microlenses and different types of epitaxial layers/thicknesses. Radiometric and geometric characterisation results obtained for various devices will be presented.

Bréart de Boisanger, Michel; Larnaudie, Franck; Saint-Pé, Olivier

2013-10-01

357

CMOS digital pixel sensors: technology and applications  

NASA Astrophysics Data System (ADS)

CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

Skorka, Orit; Joseph, Dileepan

2014-04-01

358

Log polar image sensor in CMOS technology  

NASA Astrophysics Data System (ADS)

We report on the design, design issues, fabrication and performance of a log-polar CMOS image sensor. The sensor is developed for the use in a videophone system for deaf and hearing impaired people, who are not capable of communicating through a 'normal' telephone. The system allows 15 detailed images per second to be transmitted over existing telephone lines. This framerate is sufficient for conversations by means of sign language or lip reading. The pixel array of the sensor consists of 76 concentric circles with (up to) 128 pixels per circle, in total 8013 pixels. The interior pixels have a pitch of 14 micrometers, up to 250 micrometers at the border. The 8013-pixels image is mapped (log-polar transformation) in a X-Y addressable 76 by 128 array.

Scheffer, Danny; Dierickx, Bart; Pardo, Fernando; Vlummens, Jan; Meynants, Guy; Hermans, Lou

1996-08-01

359

Latchup in CMOS devices from heavy ions  

NASA Technical Reports Server (NTRS)

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.; Nichols, D. K.

1983-01-01

360

CMOS imager for pointing and tracking applications  

NASA Technical Reports Server (NTRS)

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

361

Nano-CMOS Technology for Next Fifteen Years  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will govern the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options

H. Iwai; H. Wong

2006-01-01

362

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

2012-06-07

363

CMOS\\/LCOS-based image transceiver device: II  

Microsoft Academic Search

A CMOS-liquid crystal-based image transceiver device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaging and display in a single array configuration. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel

Uzi Efron; Isak Davidov; Vladimir Sinelnikov; Asher A. Friesem

2001-01-01

364

CMOS-liquid-crystal-based image transceiver device  

Microsoft Academic Search

A CMOS-Liquid Crystal-Based Image Transceiver Device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaginary and display in a single array structure. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel

Uzi Efron; Isak Davidov; Vladimir Sinelnikov; Ilya Levin

2001-01-01

365

CMOS Monolithic Metal–Oxide Gas Sensor Microsystems  

Microsoft Academic Search

This paper presents two mixed-signal monolithic gas sensor microsystems fabricated in standard 0.8-$muhbox m$CMOS technology combined with post-CMOS micromachining to form the microhotplates. The on-chip microhotplates provide very high temperatures (between 200$^circ$C and 400$^circ$C), which are necessary for the normal operation of metal–oxide sensing layers. The first microsystem has a single-ended architecture comprising a microhotplate (diameter of 300$muhbox m$) and

Diego Barrettino; Markus Graf; Stefano Taschini; Sadik Hafizovic; Christoph Hagleitner; Andreas Hierlemann

2006-01-01

366

An Energy-Efficient CMOS Line Driver Using Adiabatic Switching  

Microsoft Academic Search

The energy recovery principle used in high-efficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom line- driver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than conventional CMOS. The paper describes the adiabatic charging principle underlying this class

W. C. Athas; J. G. Koller

1993-01-01

367

Electrical properties and detection methods for CMOS IC defects  

Microsoft Academic Search

CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees detection of all types

Jerry M. Soden; Charles F. Hawkins

1989-01-01

368

A CMOS ASIC Design for SiPM Arrays.  

PubMed

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2011-12-01

369

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS  

NASA Technical Reports Server (NTRS)

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Trotter, J. D.

1982-01-01

370

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.  

PubMed

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18? ?m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 ?m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

371

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out  

Microsoft Academic Search

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

2008-01-01

372

Post-CMOS compatible high-throughput fabrication of AlN-based piezoelectric microcantilevers  

NASA Astrophysics Data System (ADS)

A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3–Cl2–Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1?0?0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

Pérez-Campos, A.; Iriarte, G. F.; Hernando-Garcia, J.; Calle, F.

2015-02-01

373

A wide dynamic range CMOS image sensor with 200-1100 nm spectral sensitivity and high robustness to UV right exposure  

NASA Astrophysics Data System (ADS)

A highly UV-light sensitive and sensitivity robust CMOS image sensor with a wide dynamic range (DR) was developed and evaluated. The developed CMOS image sensor includes a lateral overflow integration capacitor in each pixel in order to achieve a high sensitivity and a wide DR simultaneously. As in-pixel photodiodes (PDs), buried pinned PDs were formed on flattened Si surface. The PD has a thin surface p+ layer with a steep dopant concentration profile to form an electric field that drifts photoelectrons to the pinned n layer. This structure improves UV-light sensitivity and its stability. In addition, a buried channel source follower driver was introduced to achieve a low pixel noise. This CMOS image sensor was fabricated by a 0.18-µm 1-polycrystalline silicon 3-metal CMOS process technology with buried pinned PD. The fabricated image sensor has a high sensitivity for 200-1100 nm light wave band, high robustness of sensitivity and dark current toward UV-light exposure and a wide DR of 97 dB. In this paper, the PD structures, the circuit, the operation sequence and the measurement results of this CMOS image sensor are discussed.

Nasuno, Satoshi; Kawada, Shun; Koda, Yasumasa; Nakazawa, Taiki; Hanzawa, Katsuhiko; Kuroda, Rihito; Sugawa, Shigetoshi

2014-01-01

374

Passive radiation detection using optically active CMOS sensors  

NASA Astrophysics Data System (ADS)

Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and ? particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

Dosiek, Luke; Schalk, Patrick D.

2013-05-01

375

Cryogenic CMOS avalanche diodes for nuclear physics research  

NASA Astrophysics Data System (ADS)

Exploration in nuclear physics may require extreme conditions, such as temperatures down to a few Kelvin, high magnetic fields of several Tesla, or the small physical dimensions of a few centimeters. As a standard technique for radiation detection using scintillation materials, it is desirable to develop photodetectors that can operate under these harsh conditions. Though photomultiplier tubes (PMTs) have been used for most applications for readout of scintillation materials, they are bulky, highly susceptible to magnetic fields, and present a large heat load in cryogenic environments. Avalanche photodiodes are a reasonable alternative to PMTs in that they are extremely compact and less susceptible to magnetic fields. Avalanche photodiodes have been developed in a commercial CMOS process for operation at temperatures below 100 Kelvin. Here we present the overall operation of the photodiodes at 5 Kelvin. The diodes show a quantum efficiency of at least 30% at 532 nm at 5 Kelvin. At about 30 Kelvin, the diodes exhibit an internal resistive term, which generates a second breakdown point. The prototype diode shows a proportional response to the intensity of light pulses down to 150 detected photons with a hole to electron ionization ratio, k, of 2.3x10-13 at 5 Kelvin. The properties of the photodiodes and the readout electronics will be discussed for general photon detection below 100 K.

Chen, Xiao Jie; Johnson, Erik B.; Stapels, Christopher J.; Whitney, Chad; Chapman, Eric; Alberghini, Guy; Augustine, Frank; Miskimen, Rory; Christian, James F.

2011-09-01

376

Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays  

PubMed Central

High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-?m, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35?m × 15?m and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2kHz bandwidth is ? 110fA. The maximum charge storage capacity at 2kHz is 1.26 × 106 electrons. PMID:20514150

Ayers, Sunitha; Gillis, Kevin D.; Lindau, Manfred; Minch, Bradley A.

2010-01-01

377

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...within the United States after importation of certain CMOS image sensors and products containing the same based on infringement of...

2012-12-14

378

Cost-effective CMOS-compatible grating couplers with backside metal mirror and 69% coupling efficiency.  

PubMed

A highly efficient grating structure for the coupling between standard optical fibers and single-mode waveguides in the silicon-on-insulator platform realized in a CMOS fabrication process is presented. The cost-effective method introduces a backside metal mirror to the grating coupler without need of an extensive wafer-to-wafer bonding. A coupling efficiency of -1.6 dB (around 69%) near the telecommunication wavelength 1550 nm and a large 1 dB-bandwidth of 48 nm are achieved. PMID:23262857

Zaoui, Wissem Sfar; Rosa, María Félix; Vogel, Wolfgang; Berroth, Manfred; Butschke, Jörg; Letzkus, Florian

2012-12-10

379

Teledyne Imaging Sensors: silicon CMOS imaging technologies for x-ray, UV, visible, and near infrared  

Microsoft Academic Search

Teledyne Imaging Sensors develops and produces high performance silicon-based CMOS image sensors, with associated electronics and packaging for astronomy and civil space. Teledyne's silicon detector sensors use two technologies: monolithic CMOS, and silicon PIN hybrid CMOS. Teledyne's monolithic CMOS sensors are large (up to 59 million pixels), low noise (2.8 e- readout noise demonstrated, 1-2 e- noise in development), low

Yibin Bai; Jagmohan Bajaj; James W. Beletic; Mark C. Farris; Atul Joshi; Stefan Lauxtermann; Anders Petersen; George Williams

2008-01-01

380

Performance and reliability of post-CMOS metal/oxide MEMS for RF application  

NASA Astrophysics Data System (ADS)

This paper describes work carried out to assess the elastic performance of microelectromechanical (MEMS) test structures in a post-CMOS (complementary metal oxide semiconductor) metal oxide process. Electrostatic pull-in measurements are used to extract the residual stress, elastic modulus and stress-gradient for the process. Results are presented for metal structures and for composite metal/oxide structures. The extracted parameters are compared with values obtained from blanket film measurements and from analysis based on bulk material properties. Test structures have also been tested for cycling repeatability. A drift is observed in successive cycles of electrostatic actuation and this drift is attributed to charge trapping in the nitride passivation of the underlying CMOS process. A charge-balance model is used to estimate the trapped charge and the effect of actuation voltage polarity is also discussed. The results indicate that satisfactory elastic performance of mechanical structures is dependent on process conditions but can be achieved. The stability of electrical operating characteristics is dominated by nitride charge trapping effects. This effect can be quantified using a basic model. To minimize problems due to charge trapping dielectric properties must be investigated and operating characteristics modified.

Hill, M.; O'Mahony, C.; Duane, R.; Mathewson, A.

2003-07-01

381

An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC  

NASA Astrophysics Data System (ADS)

Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz mechanical variable capacitor. The precharger, harvester, monitoring, and control microelectronics of the first prototype draw sufficient power to operate and at the same time produce experimentally 1.27, 2.14, and 2.87 nJ per vibration cycle for battery voltages at 2.7, 3.5, and 4.2 V, which with 30-Hz vibrations produce 38.1, 64.2, and 86.1 nW. By incorporating into the system a self-tuning loop that adapts optimally the inductor-based precharger to varying battery voltages, the second prototype harnessed and gained 1.93, 2.43, and 3.89 nJ per vibration cycle at battery voltages 2.7, 3.5, and 4.2 V, generating 57.89, 73.02, and 116.55 nW at 30 Hz. The harvester ultimately charges from 2.7 to 4.2 V a 1-muF capacitor (which emulates a small thin-film Li Ion) in approximately 69 s, harnessing in the same length of time 47.9% more energy than with a non-adapting harvester.

Torres, Erick Omar

382

Integrating silicon photonic interconnects with CMOS: Fabrication to architecture  

NASA Astrophysics Data System (ADS)

While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

Sherwood, Nicholas Ramsey

383

A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS1800 systems  

Microsoft Academic Search

A set of two VCOs is developed in a 0.4 ?m CMOS process, using a fully integrated spiral inductor with symmetrical octagonal shape in the resonance LC-tank. One VCO operates at a 900 MHz center frequency, and the other at 1.8 GHz, both achieving the required phase noise spec and tuning range for the GSM and DCS-1800 system. The phase

Jan Craninckx; Michiel Steyaert; Hiroyuki Miyakawa

1997-01-01

384

Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation  

Microsoft Academic Search

In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source\\/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation

Saibal Mukhopadhyay; Kaushik Roy

2003-01-01

385

A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications  

Microsoft Academic Search

A self-terminated line driver suitable for fast Eth- ernet operates in class AB mode and combines digital signal processing with low-power analog circuits. It dissipates 108mW, 48% less than an existing state-of-the-art design. It occupies 0.22mm 2 in a 65nm standard CMOS technology and operates from a 2.5V supply. I. INTRODUCTION The design of a compact low-power fast Ethernet (FE)

Joseph Aziz; Ark-Chew Wong; Andrew Chen; Derek Tam

2011-01-01

386

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification  

NASA Technical Reports Server (NTRS)

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

387

A 3 5Gb\\/s Multilane Low-Power 0.18- CMOS Pseudorandom Bit Sequence Generator  

Microsoft Academic Search

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb\\/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb\\/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb\\/s due to test setup limitations. The prototype

Kin-Joe Sham; Shubha Bommalingaiahnapallya; Mahmoud Reza Ahmadi; Ramesh Harjani

2008-01-01

388

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI  

Microsoft Academic Search

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n+- and p+-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600°C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at

Toyota Morimoto; Tatsuya Ohguro; Hisayo Sasaki Momose; Toshihiko Iinuma; Iwao Kunishima; Kyoichi Suguro; Ichiro Katakabe; Hiroomi Nakajima; Masakatsu Tsuchiaki; Mizuki Ono; Yasuhiro Katsumata; Hiroshi Iwai

1995-01-01

389

A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras  

Microsoft Academic Search

This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable quantization level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design

Shoji Kawahito; Makoto Yoshida; Masaaki Sasaki; Keijiro Umehara; Daisuke Miyazaki; Yoshiaki Tadokoro; Kenji Murata; Shirou Doushou; Akira Matsuzawa

1997-01-01

390

Pulsed Laser Single-Event Effects in Highly Scaled CMOS Technologies in the Presence of Dense Metal Coverage  

Microsoft Academic Search

single-photon (SPA) and two-photon laser absorption (TPA) techniques are established as reliable, effective methods to study specific single-event (SE) phenomena in advanced CMOS technologies. However, dense metal-fill in these nanoscale processes can prevent the use of top-side SPA in some cases. This paper demonstrates a novel methodology enabling top-side laser SPA single-event effects (SEEs) measurements in the presence of dense

Anupama Balasubramanian; Dale McMorrow; Sarah A. Nation; Bharat L. Bhuva; Robert A. Reed; Lloyd W. Massengill; Thomas D. Loveless; Oluwole A. Amusan; Jeffrey D. Black; Joseph S. Melinger; Mark P. Baze; Veronique Ferlet-Cavrois; Marc Gaillardin; James R. Schwank

2008-01-01

391

Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS  

NASA Astrophysics Data System (ADS)

Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET (GGNMOS) was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse (TLP) measurements and Sentaurus technology computer aided design (TCAD) 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.

Daoxun, Wu; Lingli, Jiang; Hang, Fan; Jian, Fang; Bo, Zhang

2013-02-01

392

Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua  

E-print Network

Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua , Wei Gaoa , Paul J, University of Toronto, Toronto, Ontario, Canada ABSTRACT Damage in CMOS image sensors caused by heavy ions and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors

Hornsey, Richard

393

CMOS Cell Sensors for Point-of-Care Diagnostics  

PubMed Central

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

394

Temporal-noise measurements of a CMOS camera used for image quality measurements  

NASA Astrophysics Data System (ADS)

We have used a CMOS camera as multi-purpose instrument for measuring image quality of high-resolution LCD displays for use in medical diagnosis. The camera uses a Foveon sensor so that the RGB pixels are co-located making for simplified spatial sampling. In this presentation we examine the temporal-noise characteristics of the CMOS camera. We are using one of several LED's in an integrating sphere as the light source to provide the nominally uniform illumination for each experiment. In first experiments we place the camera sensor near to the opening of the integrating sphere without introducing an imaging lens in order to initially eliminate the characteristics of the lens. The capture parameters for the camera control software are set to give us as nearly raw data as possible. We suppress the native processing because our application is much different than the usual image-reproduction function. We capture sequences of images with the same illumination and same capture parameters and write them to TIFF files. The Matlab-based software we've written first pre-processes the images then calculates the pixel-wise mean and standard deviation over the sequence of frames. The calculation is repeated for each of the three (RGB) channels of the CMOS camera. These statistics are displayed as graytone images in three windows with the maxima and minima displayed in the title-bars. The short-term goal of the experiments is to prepare the way to compare the performance of cooled and un-cooled versions of the camera.

Roehrig, Hans; Dallas, William J.; Redford, Gary R.

2008-03-01

395

CMOS-based Biosensor Arrays R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, M. Augustyniak, M. Jenkner,  

E-print Network

of the drug development process is schematically depicted in Fig. 1. Moreover, CMOS-based solutions also. Whereas optical detection principles make use of fluorescence or chemoluminescense light originating from and serial digital data transmission. Measured electrical, electrochemical, and biological data as well

Paris-Sud XI, Université de

396

Target acquisition and tracking system based on a real-time reconfigurable multiwindow CMOS image sensor  

NASA Astrophysics Data System (ADS)

This paper presents a prototype Dynamically Reconfigurable Vision (DRV) system. DRV is based on the intelligent, dynamic allocation of spatial and temporal resources in order to maximize system performance. Minimization of irrelevant data in the video processing chain reduces on- board processing requirements, power consumption, and payload, and increases the amount of relevant information that can be communicated over bandwidth-limited channels. Our DRV system employs a real-time reconfigurable CMOS image sensor which supports multiple variance-resolution, independently-configurable windows per exposure, operates in a snapshot capture mode to minimize smear, and outputs data through multiple video ports to minimize readout time. Multiple, time-correlated windows enable the vision system to better support multiple targeting functions concurrently, and achieve a maximum level of situational awareness. This imager is capable of reconfiguring itself in microseconds upon demand; frame-by-frame configurable parameters include frame rate, integration time, and parameters defining the position, shape, size, and resolution of each window. The system additionally features a small footprint and very low power, resulting from a CMOS implementation and on-chip signal processing using passive circuitry. The advantages of DRV over conventional imaging techniques are discussed, and the overall design and performance of our DRV sensor and camera are presented.

Stack, David J.; Kramer, Christopher A.; McLoughlin, Terence H.; Sielski, Kris W.; Yang, Guang; Wrigley, Christopher J.; Pain, Bedabrata

2000-07-01

397

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays  

NASA Astrophysics Data System (ADS)

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

398

Operation and biasing for single device equivalent to CMOS  

DOEpatents

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

399

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications  

NASA Astrophysics Data System (ADS)

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 ?m long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

400

Electroplated solenoid-type inductors for CMOS rf CO  

NASA Astrophysics Data System (ADS)

A Solenoid-type Inductors have been realized using electroplating technique mainly used for 2 Ghz band CMOS RF VCO applications. The integrated spiral inductor has low Q factor due to substrate loss and skin effects. And it also occupies large area compared to solenoid-type inductor. The direction of flux of the solenoid-type inductor is parallel to the substrate, which can lower substrate loss and other interference with integrated passive components. In this research, Solenoid-type inductors are simulated and modeled as equivalent circuit for CMOS RF VCO based on extracted S- parameters. The electroplated solenoid-type inductors are fabricated on both a standard silicon substrate and glass substrate by thick PR photolithography and copper electroplating. The achieved inductance varies range from 1 nH to 5 nH, and maximum Q factor over 10. The inductors are scheduled to be integrated on CMOS RF VCO with RF MEMS capacitor for future.

Nam, Chul; Choi, Wonseo; Chun, KukJin

2000-10-01

401

Study of CMOS process variation by multiplexing analog characteristics  

E-print Network

Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic ...

Gettings, Karen Mercedes González-Valentín

2007-01-01

402

The impact of deuterated CMOS processing on gate oxide reliability  

Microsoft Academic Search

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. In particular, the influence of deuterium incorporation on the bulk oxide quality is not clear. In this letter, deuterium or hydrogen is introduced during either the gate oxidation, postoxidation anneal, and\\/or the postmetal anneal (PMA). The oxide bulk degradation was

A. J. Hof; E. Hoekstra; A. Y. Kovalgin; R. van Schaijk; W. M. Baks; J. Schmitz

2005-01-01

403

A high performance 0.25 mu m CMOS technology  

Microsoft Academic Search

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. Cw=0.2 pF) delay per stage of 280 ps achieved (Weff\\/Leff=15 mu m\\/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m),

B. Davari; W. H. Chang; M. R. Wordeman; C. S. Oh; Y. Taur; K. E. Petrillo; D. Moy; J. J. Bucchignano; H. Y. Ng; M. G. Rosenfield; F. J. Hohn; M. D. Rodriguez

1988-01-01

404

Statistical circuit design for yield improvement in CMOS circuits  

NASA Technical Reports Server (NTRS)

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

1990-01-01

405

Modifications in CMOS Dynamic Logic Style: A Review Paper  

NASA Astrophysics Data System (ADS)

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

Meher, Preetisudha; Mahapatra, Kamalakanta

2014-11-01

406

Large Format CMOS-based Detectors for Diffraction Studies  

NASA Astrophysics Data System (ADS)

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 ?m × 100 ?m are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 ?m × 100 ?m pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

407

Scalable production of sub-?m functional structures made of non-CMOS compatible materials on glass  

NASA Astrophysics Data System (ADS)

Biophotonic and Life Science applications often require non-CMOS compatible materials to be patterned with sub ?m resolution. Whilst the mass production of sub ?m patterns is well established in the semiconductor industry, semiconductor fabs are limited to using CMOS compatible materials. IMT of Switzerland has implemented a fully automated manufacturing line that allows cost effective mass manufacturing of consumables for biophotonics in substrate materials like D263 glass or fused silica and layer/coating materials like Cr, SiO2, Cr2O5, Nb2O5, Ta2O5 and with some restrictions even gold with sub-?m patterns. The applied processes (lift-off and RIE) offer a high degree of freedom in the design of the consumable.

Arens, Winfried

2014-03-01

408

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties  

PubMed Central

This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 ?m standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

2012-01-01

409

A CMOS pressure sensor with integrated interface for passive RFID applications  

NASA Astrophysics Data System (ADS)

This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18??m CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2?fF?kPa?1. The sensor interface consumes only 1.1?µW of power at 0.5?V voltage supply, which is at least an order of magnitude better than state-of-the-art designs.

Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

2014-12-01

410

sCMOS detector for imaging VNIR spectrometry  

NASA Astrophysics Data System (ADS)

The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

2013-09-01

411

Compact CMOS Camera Demonstrator (C3D) for Ukube-1  

NASA Astrophysics Data System (ADS)

The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

2011-09-01

412

SRAM Design Techniques for Sub-nano CMOS Technology  

Microsoft Academic Search

The scaling of CMOS technology has significant impacts on SRAM cell ? random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be

Jordan Lai

2006-01-01

413

A unified model for integrated resistors in CMOS technologies  

Microsoft Academic Search

In the present work we present a compact model, oriented to the SPICE-like simulation, that pictures the electrical behavior of integrated resistors fabricated in CMOS technologies. The model accounts for the main electrical features of integrated resistors such as the depletion effects, the head resistance contribution, the velocity saturation and the temperature behavior also including possible self-heating phenomena. It has

I. Aureli; D. Ventrice; C. Codegoni; P. Fantini

2007-01-01

414

Testing for bridging faults (shorts) in CMOS circuits  

Microsoft Academic Search

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

John M. Acken

1983-01-01

415

Variable threshold voltage CMOS (VTCMOS) in series connected circuits  

Microsoft Academic Search

Characteristics of variable threshold voltage CMOS (VTCMOS) in series connected circuits are investigated by means of device simulation. It is found that the performance degradation due to the body effect in series connected circuits is suppressed by utilizing VTCMOS. Lowering the threshold voltage (Vth) enhances the drive current and alleviates the degradation due to the series connected configuration. Therefore, larger

T. Inukai; T. Hiramoto; T. Sakurai

2001-01-01

416

Variable threshold CMOS (VTCMOS) in series connected circuits  

Microsoft Academic Search

Characteristics of variable threshold voltage CMOS (VTCMOS) in the series connected circuits are investigated by means of device simulation. It is newly found that the performance degradation due to the body effect in series connected circuit is suppressed by utilizing VTCMOS. Lowering the threshold voltage (Vth) enhances the drive current and alleviates the degradation due to the series connected configuration.

Takashi Inukai; Toshiro Hiramoto; Takayasu Sakurai

2001-01-01

417

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess  

E-print Network

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault of the two methods. We con­ clude that the new simulation method, Wire Memory bridge fault simulation

Larrabee, Tracy

418

Ultrabroadband supercontinuum generation in a CMOS-compatible platform  

E-print Network

Ultrabroadband supercontinuum generation in a CMOS-compatible platform R. Halir,1,5, * Y. Okawachi 162267); published May 10, 2012 We demonstrate supercontinuum generation spanning 1.6 octaves in silicon Optical Society of America OCIS codes: 190.4390, 320.7110, 320.6629, 230.7370. Supercontinuum generation

Lipson, Michal

419

CMOS imager microsystem for multi-bacteria detection  

Microsoft Academic Search

The paper presents the design and implementation of a Complementary Metal-Oxide Semiconductor (CMOS) based imaging microsystem that can monitor multiple bacteria and viruses simultaneously. The sensor microsystem uses bacteriophages or phage organisms as recognition elements to detect deadly bacteria such as Anthrax, Salmonella, and E-Coli. The genetically engineered phages are viruses that recognize specific receptors on the bacteria surface to

Lei Yao; Mohamad Hajj Hassan; Vamsy Chodavarapu; Arghavan Shabani; Beatrice Allain; Mohammed Zourob; Rosemonde Mandeville

2008-01-01

420

CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria  

Microsoft Academic Search

We present the design and implementation of a pro- totype complementary metal-oxide semiconductor (CMOS) con- ductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The de- tection of E. coli is done by employing T4 bacteriophages as re- ceptor organisms. The conductometric system operates by mea- suring the resistance of the test

Lei Yao; Philippe Lamarche; Nancy Tawil; Rifat Khan; Amir M. Aliakbar; Mohamad H. Hassan; Vamsy P. Chodavarapu; Rosemonde Mandeville

2011-01-01

421

Total dose testing of a CMOS charged particle spectrometer  

Microsoft Academic Search

A first-generation CMOS Charged Particle Spectrometer chip was designed at JPL for flight on the STRV-2 spacecraft. These devices will collect electron and proton spectra in low Earth orbit as part of an experiment to demonstrate Active Pixel Sensor (APS) technology in space. This paper presents the results of total dose testing on these chips and, where possible, attempts to

B. R. Hancock; G. A. Soli

1997-01-01

422

CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.  

SciTech Connect

Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

RADEKA, V.

2006-04-03

423

A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR  

E-print Network

A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR Piotr Dudek and Peter J. Hicks functions as an analogue microprocessor (AµP). The AµP executes software programs, in a way akin to a digital microprocessor, while nevertheless operating on analogue sampled data values. This enables

Dudek, Piotr

424

An integrated CMOS micromechanical resonator high-Q oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

Clark T.-C. Nguyen; Roger T. Howe

1999-01-01

425

Total-Ionizing-Dose Effects in Modern CMOS Technologies  

Microsoft Academic Search

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by

H. J. Barnaby

2006-01-01

426

Measurements of Si hybrid CMOS x-ray detector characteristics  

Microsoft Academic Search

The recent development of active pixel sensors as X-Ray focal plane arrays will place them in contention with CCDs on future satellite missions. Penn State University (PSU) is working with Teledyne Imaging Sensors (TIS) to develop X-Ray Hybrid CMOS devices (HCDs), a type of active pixel sensor with fast frame rates, adaptable readout timing and geometry, low power consumption, and

Stephen D. Bongiorno; Abraham D. Falcone; David N. Burrows; Robert Cook

2010-01-01

427

A CMOS Potentiostat for Control of Integrated MEMS Actuators  

E-print Network

. The fabricated chip has been employed for the control of off-chip electroactive polymer films and micro-actuatorsA CMOS Potentiostat for Control of Integrated MEMS Actuators Somashekar Bangalore Prakash, Pamela-- We describe a potentiostat designed for in situ electrochemical control of MEMS actuators

Maryland at College Park, University of

428

Effects Of Dose Rates On Radiation Damage In CMOS Parts  

NASA Technical Reports Server (NTRS)

Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

Goben, Charles A.; Coss, James R.; Price, William E.

1990-01-01

429

Effect of a polywell leometry on a CMOS photodiode array  

Microsoft Academic Search

The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination.

Paul V. Jansz; Steven Hinckley; Graham Wild

2010-01-01

430

Effect of a Polywell geometry on a CMOS Photodiode Array  

Microsoft Academic Search

The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination

Paul V Jansz; Steven Hinckley; Graham Wild

2010-01-01

431

A foveated image sensor in standard CMOS technology  

Microsoft Academic Search

We describe the design and implementation of a CMOS foveated image sensor for use in mobile robotic and machine vision applications. The sensor is biologically motivated and performs a spatial image transformation from Cartesian to log-polar coordinates. As opposed to traditional approaches, the sensor benefits from a high degree of integration, minimal power consumption and ease of manufacture due to

Robert Wodnicki; Gordon W. Roberts; Martin D. Levine

1995-01-01

432

CMOS foveated image sensor: signal scaling and small geometry effects  

Microsoft Academic Search

A new foveated (log-polar) image sensor using standard CMOS technology has been designed and fabricated. The pixel distribution follows the log polar transform having more resolution in the center than in the periphery. For the fovea or central part, a different but also polar distribution has been adopted to fit the inner pixels. The particular problem of foveated image sensors

Fernando Pardo; Bart Dierickx; Danny Scheffer

1997-01-01

433

CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics  

NASA Technical Reports Server (NTRS)

Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

Yeh, Penshu; Maki, Gary

2007-01-01

434

CMOS Active-Pixel Image Sensor With Simple Floating Gates  

NASA Technical Reports Server (NTRS)

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

435

Integrated imaging sensor systems with CMOS active pixel sensor technology  

NASA Technical Reports Server (NTRS)

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

436

Quasi-TEM characteristic impedance of micromachined CMOS coplanar waveguides  

Microsoft Academic Search

Micromachined coplanar waveguides (CPW's) fabricated in CMOS technology consist of glass-encapsulated metal conductor strips, fully suspended by selective etching of the silicon substrate. The minimum amount of etching necessary for proper operation of the micromachined waveguides is determined by using an isolation criterion. In this paper, the quasi-TEM characteristic impedance of a CPW is derived, including the finite conductor thickness

Mehmet Ozgur; V. Milanov; Christian Zincke; Michael Gaitan; Mona E. Zaghloul

2000-01-01

437

Contact CMOS imaging of gaseous oxygen sensor array.  

PubMed

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

438

Contact CMOS imaging of gaseous oxygen sensor array  

PubMed Central

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

439

Fourier analysis of the imaging characteristics of a CMOS active pixel detector for mammography by using a linearization method  

NASA Astrophysics Data System (ADS)

Active pixel design using the complementary metal-oxide-semiconductor (CMOS) process is a compelling solution for use in X-ray imaging detectors because of its excellent electronic noise characteristics. We have investigated the imaging performance of a CMOS active pixel photodiode array coupled to a granular phosphor through a fiber-optic faceplate for mammographic applications. The imaging performance included the modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). Because we observed a nonlinear detector response at low exposures, we used the linearization method for the analysis of the DQE. The linearization method uses the images obtained at detector input, which are converted from those obtained at detector output by using the inverse of the detector response. Compared to the conventional method, the linearization method provided almost the same MTF and a slightly lower normalized NPS. However, the difference between the DQE results obtained by using the two methods was significant. We claim that the conventional DQE analysis of a detector having a nonlinear response characteristic can yield wrong results. Under the standard mammographic imaging condition, we obtained a DQE performance that was competitive with the performances of conventional flat-panel mammography detectors. We believe that the CMOS detector investigated in this study can be successfully used for mammography.

Han, Jong Chul; Yun, Seungman; Youn, Hanbean; Kam, Soohwa; Cho, Seungryong; Achterkirchen, Thorsten G.; Kim, Ho Kyung

2014-09-01

440

Novel CMOS time-delay integration using single-photon counting for high-speed industrial and aerospace applications  

NASA Astrophysics Data System (ADS)

Time-delay integration (TDI) is a popular imaging technique that is used in many applications such as machine vision, dental scanning and satellite earth observation. One of the main advantages of using TDI imagers is the increased effective integration time that is achieved while maintaining high frame-rates. Another use for TDI imagers is with moving objects, such as the earth's surface or industrial machine vision applications, where integration time is limited in order to avoid motion blurs. Such technique may even find its way in mobile and consumer based imaging applications where the reduction in pixel size can limit the performance during low-light and high speed applications. Until recently, TDI was only used with charge-coupled devices (CCDs) mainly due to their charge transfer characteristics. CCDs however, are power consuming and slow when compared to CMOS technology and are no longer favorable for mobile applications. In this work, we report on novel single-photon counting based TDI technique that is implemented in standard CMOS technology allowing for complete camera-on-a-chip solution. The imager was fabricated in a standard CMOS 150 nm 5-metal digital process from LFoundry.

El-Desouki, Munir M.; Al-Azem, Badeea

2014-03-01

441

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB  

NASA Astrophysics Data System (ADS)

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 ?m RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

Guang, Yang; Wang, Yao; Jiangwei, Yin; Renliang, Zheng; Wei, Li; Ning, Li; Junyan, Ren

2009-01-01

442

The application and quantitative testing of 150 million pixel CMOS image sensor  

NASA Astrophysics Data System (ADS)

With the requirements of high time resolution, high spatial and high spectral resolution development in geostationary orbit, photodetector pixel size has gradually become the bottleneck of the space exploration technology. Shanghai Institute of Technical Physics of Chinese Academy of Science has made a new breakthrough in CMOS image sensor area. The scale of its new CMOS image sensor achieves 2.5K×2.5K, and then use 24 detectors to achieve a detector whose scale is 150 million. The detector has been successfully imaging on the ground. In the application process, presents a systematic test and measurement methods to deal with the time noise, dark current, fixed pattern noise, MTF and other parameters of the detector. The test results are below. The MTF of the detector is 0.565 which is measured at 57.21/mm Nyquist frequency. The number of saturated electrons reaches 8.9×104. The total number of transient noise electrons is smaller than 16. The signal to noise ratio is 58.02dB. Through comprehensive analysis and measurement, it shows that the overall performance of the 2.5K×2.5K detector among the same types of products is in the leading position currently.

Gong, Xueyi; Chen, Fansheng; Huang, Sijie; Su, Xiaofeng; Dong, Yucui

2013-12-01

443

Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications  

PubMed Central

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

2014-01-01

444

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.  

PubMed

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 ?m CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure. PMID:23853177

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

445

A high speed, low power consumption LVDS interface for CMOS pixel sensors  

NASA Astrophysics Data System (ADS)

The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-?m CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW.

Shi, Zhan; Tang, Zhenan; Tian, Yong; Pham, Hung; Valin, Isabelle; Jaaskelainen, Kimmo

2015-01-01

446

Ultra-sensitive detection of adipocytokines with CMOS-compatible silicon nanowire arrays  

NASA Astrophysics Data System (ADS)

Perfectly aligned arrays of single-crystalline silicon nanowires were fabricated using top-down CMOS-compatible techniques. We demonstrate that these nanowire devices are able to detect adipocytokines secreted by adipose cells with femtomolar sensitivity, high specificity, wide detection range, and ability for parallel monitoring. The nanowire sensors also provide a novel tool to reveal the poorly understood signaling mechanisms of these newly recognized signaling molecules, as well as their relevance in common diseases such as obesity and diabetes.Perfectly aligned arrays of single-crystalline silicon nanowires were fabricated using top-down CMOS-compatible techniques. We demonstrate that these nanowire devices are able to detect adipocytokines secreted by adipose cells with femtomolar sensitivity, high specificity, wide detection range, and ability for parallel monitoring. The nanowire sensors also provide a novel tool to reveal the poorly understood signaling mechanisms of these newly recognized signaling molecules, as well as their relevance in common diseases such as obesity and diabetes. Electronic supplementary information (ESI) available: Process diagram of nanowire fabrication; specificity of nanowire detection; induced differentiation of 3T3-L1 cells. See DOI: 10.1039/b9nr00092e

Pui, Tze-Sian; Agarwal, Ajay; Ye, Feng; Tou, Zhi-Qiang; Huang, Yinxi; Chen, Peng

2009-09-01

447

Thin film transistors made of nanocrystalline silicon for CMOS on plastic  

NASA Astrophysics Data System (ADS)

Our motivation is to realize CMOS on plastic foil. We report the development of thin film transistors (TFTs) made of nanocrystalline silicon (nc-Si:H). nc-Si:H is compatible with present a-Si:H thin film technology. Because of the structural evolution of nc-Si:H with film thickness, it requires extensive experimentation with device geometry. For comparison we fabricate TFTs in (a) conventional coplanar top-gate, top-source/drain geometry and (b) staggered top-gate, bottom source/drain geometry. A seed layer is introduced in the latter case serves to develop the crystallinity of the intrinsic channel layer. While the coplanar geometry provides the shortest carrier path in the most crystalline channel region, the inverted staggered geometry ensures that the active channel is formed in the last-to-grow nc-Si:H layer, and also avoids exposure of the channel to reactive ion etching (RIE). The highest process temperature is 150°C. Both intrinsic and doped nc-Si:H layers are grown by plasma-enhanced chemical vapor deposition with an excitation frequency of 80MHz. Present p-channel TFTs reach a hole field-effect mobility of ~ 0.2 cm2V-1s-1 in the staggered geometry, and an electron field-effect mobility of ~ 40 cm2V-1s-1 in both geometries. These results suggest that directly deposited nc-Si:H is an attractive candidate material for CMOS capable electronics on plastic substrates.

Cheng, I.-Chun; Wagner, Sigurd

2003-05-01

448

A Wideband Noise-canceling CMOS LNA Using Cross-coupled Feedback and Bulk Effect  

NASA Astrophysics Data System (ADS)

An improved wideband common-gate (CG) and common-source (CS) CMOS LNA with noise cancellation is proposed. The cross-coupled feedback between the CG input transistor and the cascode transistor of CS input stage is used to increase the input transconductance of the LNA. And the bulk effect of CS input transistors is utilized to enhance gm-boosting coefficient. Thus, comparable gain and noise are achieved by reduced bias currents of the LNA while the resulted additional NF degradation is negligible. Fabricated in a 0.13 ?m RF CMOS process, the LNA achieves a flat voltage gain of 18 dB, an NF of 2.7~3.2 dB, and an IIP3 of -4.5~-7.4 dBm over a 3 dB bandwidth of 0.1~4.4 GHz. It consumes only 4.1 mA from a 1 V supply and occupies an area of 520 × 490 um2. In contrast to those of reported wideband LNAs, the proposed LNA has the merit of lower power consumption and lower supply voltage.

Guo, Benqing; Yang, Guoning; An, Shiquan

2014-05-01

449

Using a large area CMOS APS for direct chemiluminescence detection in Western blotting electrophoresis  

NASA Astrophysics Data System (ADS)

Western blotting electrophoretic sequencing is an analytical technique widely used in Functional Proteomics to detect, recognize and quantify specific labelled proteins in biological samples. A commonly used label for western blotting is Enhanced ChemiLuminescence (ECL) reagents based on fluorescent light emission of Luminol at 425nm. Film emulsion is the conventional detection medium, but is characterized by non-linear response and limited dynamic range. Several western blotting digital imaging systems have being developed, mainly based on the use of cooled Charge Coupled Devices (CCDs) and single avalanche diodes that address these issues. Even so these systems present key drawbacks, such as a low frame rate and require operation at low temperature. Direct optical detection using Complementary Metal Oxide Semiconductor (CMOS) Active Pixel Sensors (APS)could represent a suitable digital alternative for this application. In this paper the authors demonstrate the viability of direct chemiluminescent light detection in western blotting electrophoresis using a CMOS APS at room temperature. Furthermore, in recent years, improvements in fabrication techniques have made available reliable processes for very large imagers, which can be now scaled up to wafer size, allowing direct contact imaging of full size western blotting samples. We propose using a novel wafer scale APS (12.8 cm×13.2 cm), with an array architecture using two different pixel geometries that can deliver an inherently low noise and high dynamic range image at the same time representing a dramatic improvement with respect to the current western blotting imaging systems.

Esposito, Michela; Newcombe, Jane; Anaxagoras, Thalis; Allinson, Nigel M.; Wells, Kevin

2012-03-01

450

Continuous-time ?? ADC with implicit variable gain amplifier for CMOS image sensor.  

PubMed

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 ?m CMOS process and the measurement result shows an ADC power consumption lower than 63.5 ?W under 1.4 V power supply and 50 MHz clock frequency. PMID:24772012

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

451

A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors  

PubMed Central

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 ?m CMOS process. The proposed ADC has average power consumption of 128 ?W and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors. PMID:25407903

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-01-01

452

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.  

PubMed

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 ?m CMOS process. The proposed ADC has average power consumption of 128 ?W and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors. PMID:25407903

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-01-01

453

A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS With an Absolute Inaccuracy of 0.1% From 55 C to 125 C  

Microsoft Academic Search

An on-chip frequency reference exploiting the well-defined thermal-diffusivity (TD) of IC-grade silicon has been realized in a standard 0.7 ?m CMOS process. A frequency-locked loop (FLL) locks the frequency of a digitally controlled oscillator (DCO) to the process-insensitive phase shift of an electrothermal filter (ETF). The ETF's phase shift is determined by its geometry and by the thermal diffusivity of

S. Mahdi Kashmiri; Michiel A. P. Pertijs; Kofi A. A. Makinwa

2010-01-01

454

Maximum density of quantum information in a scalable CMOS implementation of the hybrid qubit architecture  

E-print Network

Scalability from single qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si Metal-Oxide-Semiconductor (MOS) quantum dots, compatible with the CMOS industrial technologic standards. We discuss the realization of multi-qubit circuits capable of fault-tolerant computation and quantum error correction, by evaluating the time and space resources needed for their implementation. As a result, the maximum density of quantum information is extracted from a circuit including 8 logical qubits encoded by the [[7,1,3

Davide Rotta; Marco De Michielis; Elena Ferraro; Marco Fanciulli; Enrico Prati

2014-06-05

455

Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications  

PubMed Central

We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

2014-01-01

456

Design of a 3 ?m pixel linear CMOS sensor for earth observation  

NASA Astrophysics Data System (ADS)

A visible wavelength linear photosensor featuring a pixel size of 3 ?m has been designed for fabrication using commercial 0.25 ?m CMOS technology. For the photo-sensing element, the design uses a special "deep N-well" in P-epi diode offered by the foundry for imaging devices. Pixel reset is via an adjacent p-FET, thus allowing high reset voltages for a wide pixel voltage swing. The pixel voltage is buffered using a voltage-follower op-amp and a sampling scheme is used to allow correlated double sampling (CDS) for removal of reset noise. Reset and signal levels are buffered through a 16:1 multiplexer to a switched capacitor amplifier which performs the CDS function. Incorporated in the CDS circuit is a programmable gain of 1-8 for increased signal-to-noise ratio at low signal levels. Data output is via 4 analogue output drivers for off-chip conversion. Each driver supplies a differential output voltage with a ±1 V swing for improved power supply noise rejection. The readout circuitry is designed for 12 bit accuracy at frame rates of up to 6.25 kHz. This gives a peak data rate at each output driver of 10 M samples/s. The device will operate on a 3.3 V supply and will dissipate approximately 950 mW. Simulations indicate an equivalent noise charge at the pixel of 66.3 e - for a full well capacity of 255,000 e -, giving a dynamic range of 71.7 dB.

Morrissey, Q. R.; Waltham, N. R.; Turchetta, R.; French, M. J.; Bagnall, D. M.; Al-Hashimi, B. M.

2003-10-01

457

SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices  

SciTech Connect

The monolithic integration of MicroElectroMechanical Systems (MEMS) with the driving, controlling, and signal processing electronics promises to improve the performance of micromechanical devices as well as lower their manufacturing, packaging, and instrumentation costs. Key to this integration is the proper interleaving, combining, and customizing of the manufacturing processes to produce functional integrated micromechanical devices with electronics. The authors have developed a MEMS-first monolithic integrated process that first seals the micromechanical devices in a planarized trench and then builds the electronics in a conventional CMOS process. To date, most of the research published on this technology has focused on the performance characteristics of the mechanical portion of the devices, with little information on the attributes of the accompanying electronics. This work attempts to reduce this information void by presenting the results of SPICE Level 3 and BSIM3v3.1 model parameters extracted for the CMOS portion of the MEMS-first process. Transistor-level simulations of MOSFET current, capacitance, output resistance, and transconductance versus voltage using the extracted model parameters closely match the measured data. Moreover, in model validation efforts, circuit-level simulation values for the average gate propagation delay in a 101-stage ring oscillator are within 13--18% of the measured data. In general, the BSIM3v3.1 models provide improved accuracy over the SPICE Level 3 models. These results establish the following: (1) the MEMS-first approach produces functional CMOS devices integrated on a single chip with MEMS devices and (2) the devices manufactured in the approach have excellent transistor characteristics. Thus, the MEMS-first approach renders a solid technology foundation for customers designing in the technology.

Staple, B.D.; Watts, H.A.; Dyck, C.; Griego, A.P.; Hewlett, F.W.; Smith, J.H.

1998-08-01

458

CMOS VLSI Active-Pixel Sensor for Tracking  

NASA Technical Reports Server (NTRS)

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

459

High voltage vs. high integration: a comparison between CMOS technologies for SPAD cameras  

NASA Astrophysics Data System (ADS)

In the last years the fabrication of SPAD cameras has become one of the main fields of interest in 3-D imaging and bioapplications. In this paper we present the comparison between two standard CMOS technologies to fabricate SPADs cameras. The two technologies used in the comparison are a high voltage 0.35?m technology from AMS and a high integration 130nm technology from STM. The advantage of using a standard CMOS technology among a dedicated is the possibility of integrating the control/reading electronics into the same die. Neither of the processes is optimized for optical applications, and no post-processing has been applied to improve the features. The technologies have been selected due to the different integration density, and different intrinsic process parameters with similar cost. Comparison has been done by fabricating several structures in both technologies which allow analyzing sensibility, noise, and time response. Experimental results show that the high voltage technology has a lower level of dark counts than the 130nm. Instead, the high integration technology has a shorter quenching time, 1.5ns, which reduces the afterpulsing events to a negligible level. In optical applications it is important to have a high integration of the camera reducing the pitch of the pixel, while noise effects can be corrected in post-processing. For low frequency events, such as high energetic particle tracking, the noise frequency has to be lower, but it is also required a high fill factor. Depending on the specific application this analysis allows to opt for the most suitable technology.

Arbat, A.; Comerma, A.; Trenado, J.; Gascon, D.; Vilà, A.; Garrido, L.; Dieguez, A.

2010-08-01

460

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis  

Microsoft Academic Search

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0\\/1 fault model. Faults

John Paul Shen; F. Joel Ferguson

1988-01-01

461

Heterogeneously Integrated 10Gb\\/s CMOS Optoelectronic Receiver for Long Haul Telecommunication  

Microsoft Academic Search

A fully integrated 10 Gb\\/s 1.3 to 1.55 mum CMOS optoelectronic receiver is demonstrated for the first time. By heterogeneously integrating of a CMOS transimpedance amplifier (TIA) with an InGaAs\\/InP PIN photodiode using a recently developed self-aligned wafer-level integration technology (SAWLIT), operation at 10 Gb\\/s is achieved. The CMOS transimpedance amplifier exhibits a transimpedance gain of 51 dBOmega and a

Hasan Sharifi; Saeed Mohammadi

2007-01-01

462

65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction  

E-print Network

Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

Mayr, C; Krause, A; Schlüßler, J -U; Schüffny, R

2014-01-01

463

324GHz CMOS VCO Using Linear Superimposition Technique  

NASA Technical Reports Server (NTRS)

Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

2007-01-01

464

High Speed Smart CMOS Sensor for Adaptive Optics - Poster Paper  

Microsoft Academic Search

We describe the design and experimental performance of a smart Shack-Hartmann wavefront sensor based on a high speed CMOS imager chip and a Field Programmable Gate Array (FPGA) capable of full frame operation at 500 frames\\/s and operated via simple USB2.0 interface. Two FPGA firmware designs are described. The serial version is most suited to modest speed (100 frames\\/s) high

T. D. Raymond; Daniel R. Neal; A. Whitehead; G. Wirth

2008-01-01

465

A generation of CMOS readout ASICs for CZT detectors  

Microsoft Academic Search

As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. The ASICs, realized in CMOS 0.5 ?m technology, are available in several different versions, single or multi-channel and with unipolar or bipolar shaper, in view of their use in research, spectroscopy, medical, safeguard and industrial applications. Four innovative

G. De Geronimo; P. O'Connor; J. Grosholz

1999-01-01

466

Transient irradiation effect on 4000 series CMOS circuits  

Microsoft Academic Search

Various CMOS devices from the 4000 series were studied as to the effects on circuit performance of exposure to an X-ray burst. The functional characteristics of the equipment were determined before irradiation, then compared with electrical measurements made on the same equipment after exposure. The radiative beam was produced by an X-ray emitter which generates 20 billion rad\\/sec. Total dosage

G. Goeransson; P. Zamuhl; B. Danielsson

1981-01-01

467

High-Voltage CMOS ESD and the Safe Operating Area  

Microsoft Academic Search

Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I t2. For the first time, the

Andrew J. Walker; Helmut Puchner; Sai Prashanth Dhanraj

2009-01-01

468

Total dose testing of a CMOS charged particle spectrometer  

SciTech Connect

A first-generation CMOS Charged Particle Spectrometer chip was designed at JPL for flight on the STRV-2 spacecraft. These devices will collect electron and proton spectra in low Earth orbit as part of an experiment to demonstrate Active Pixel Sensor (APS) technology in space. This paper presents the results of total dose testing on these chips and, where possible, attempts to extend the results to other Active Pixel Sensors.

Hancock, B.R.; Soli, G.A. [California Inst. of Tech., Pasadena, CA (United States). Jet Propulsion Lab.] [California Inst. of Tech., Pasadena, CA (United States). Jet Propulsion Lab.

1997-12-01

469

High performance CMOS integrated circuits for optical receivers  

E-print Network

to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Aydin Karsilayan Committee Members, Jose Silva-Martinez Reza Langari... Prasad Enjeti Head of Department, Costas Georghiades December 2006 Major Subject: Electrical Engineering iii ABSTRACT High Performance CMOS Integrated Circuits for Optical Receivers. (December 2006) MohammadReza SamadiBoroujeni, B...

SamadiBoroujeni, MohammadReza

2009-05-15

470

RF CMOS UWB transmitter and receiver front-end design  

E-print Network

, Cam Nguyen Committee Members, Steven Wright Laszlo Kish Reza Langari Head of Department, Costas Georghiades May 2008 Major Subject: Electrical Engineering iii ABSTRACT Radio Frequency (RF) Complementary Metal-Oxide Semiconductor (CMOS... advice, encouragement and support throughout this research. I would also like to thank my committee members, Dr. Steven Wright, Dr. Laszlo Kish, and Dr. Reza Langari for their valuable time and advice. I am also grateful to my wife, Qingmei Lu...

Miao, Meng

2009-05-15

471

A 200MHz 64-b dual-issue CMOS microprocessor  

Microsoft Academic Search

A 400-MIPS\\/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-?m CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both

D. W. Dobberpuhl; R. T. Witek; R. Allmon; R. Anglin; D. Bertucci; S. Britton; L. Chao; R. A. Conrad; D. E. Dever; B. Gieseke; S. M. N. Hassoun; G. W. Hoeppner; K. Kuchler; M. Ladd; B. M. Leary; L. Madden; E. J. McLellan; D. R. Meyer; J. Montanaro; D. A. Priore; V. Rajagopalan; S. Samudrala; S. Santhanam

1992-01-01

472

Monolithic CMOS detector module for photon counting and picosecond timing  

Microsoft Academic Search

A monolithic optoelectronic module for counting and timing single optical photons has been designed and fabricated in CMOS technology. It integrates a single-photon avalanche diode (SPAD) of 12 ?m-diameter with a complete active-quenching and active-reset circuit. The detector operates in Geiger-mode biased above breakdown level, with overvoltage adjustable up to 20 V. The on-chip electronics detects the rise of the

F. Zappa; S. Tisa; A. Gulinatti; A. Gallivanoni; S. Cova

2004-01-01

473

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits  

Microsoft Academic Search

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers

Laleh Rabieirad; Edgar J. Martinez; Saeed Mohammadi

2009-01-01

474

A BiCMOS integrated charge to amplitude converter  

SciTech Connect

This paper describes a fast two channel gated charge to amplitude converter (QAC) which has been designed with the 1.2 {mu}m BiCMOS technology from AMS (Austria Mikro Systeme). It can integrate fast negative impulse currents up to 100 mA. Associated with an audio 18 bit low cost ADC, it can easily be used to make a 12 to 13 bit QDC. The problems of current to current conversion, pedestal and offset stability are discussed.

Gallin-Martel, L.; Pouxe, J.; Rossetto, O. [Institut des Sciences Nucleaires, Grenoble (France)

1996-12-31

475

A 1-V piecewise curvature-corrected CMOS bandgap reference  

Microsoft Academic Search

A 1-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise corrected current to a conventional first-order current-mode BGR. The corrected current is zero, exponential with temperature and proportional to the squared temperature in the lower, middle and upper temperature range (TR). Simulated results indicate that proposed BGR achieves temperature coefficient (TC) of 1.18ppm\\/°C in the

Jing-hu Li; Yu-nan Fu; Yong-sheng Wang

2008-01-01

476

A comprehensive varactor study for advanced CMOS RFIC design  

Microsoft Academic Search

The key performance index related to RF circuit design for a portfolio of varactor structures, N+\\/Nwell MOS varactor (N+\\/NW MOSVAR). P+\\/Pwell MOSVAR (P+\\/PW MOSVAR) and junction varactor (JVAC) were studied using advanced 0.18?m to 90nm RF-CMOS technologies. The engineering and trade-offs for quality factor (Q-factor), tuning ratio (TR = Cmax \\/ Cmin), capacitance mismatch and flicker noise for different device

C. F. Huang; C. C. Wu; C. H. Chen; C. C. Ho; Y. J. Chan; C. S. Chang; C. P. Chao; G. J. Chern

2005-01-01

477

Radiation effects in a CMOS active pixel sensor  

Microsoft Academic Search

A CMOS active pixel sensor has been evaluated with Co60, 10 MeV proton and heavy-ion irradiation. Permanent displacement damage effects were seen but total ionizing dose-induced dark current and increase in power supply current annealed at 100°C. Large changes in responsivity were seen after proton irradiation, which subsequently annealed. Mechanisms for these responsivity changes are discussed, but a definitive cause

Gordon R. Hopkinson

2000-01-01

478

CMOS bandgap references and temperature sensors and their applications  

Microsoft Academic Search

Two main parts have been presented in this thesis: device characterization and circuit. \\u000aIn integrated bandgap references and temperature sensors, the IC(VBE, characteristics of bipolar transistors are used to generate the basic signals with high accuracy. To investigate the possibilities to fabricate high-precision bandgap references and temperature sensors in low-cost CMOS technology, the electrical characteristics of substrate bipolar pnp transistors

G. Wang

2005-01-01

479

A linear fully balanced CMOS OTA for VHF filtering applications  

Microsoft Academic Search

A linear, fully balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with large dc gain and wide bandwidth is described. The approach uses a two-differential-pair transconductor with a cross-coupled input stage together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated, dc gain enhancement is obtained without bandwidth limitation.

S. Szczepanski; Jacek Jakusz; Rolf Schaumann

1997-01-01

480

CMOS low-noise amplifier design optimization techniques  

Microsoft Academic Search

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques.

Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; Moon-Su Yang; Sang-Gug Lee

2004-01-01

481

DARWIN: CMOS opamp synthesis by means of a genetic algorithm  

Microsoft Academic Search

Abstract—DARWIN is a ,tool that is able ,to synthesize CMOS opamps, on the basis of a genetic algorithm. A ran- domly generated initial set of opamps,evolves to a set in which the topologies as well as the transistor sizes of the,opamps ,are adapted to the ,required performance ,specifications. Several design examples illustrate the behavior of DARWIN. I. INTRODUCTION The analog

Wim Kruiskamp; Domine Leenaerts

1995-01-01

482

Radiation Detectors for HEP Applications Using Standard CMOS Technology  

Microsoft Academic Search

The suitability of standard CMOS technology featuring no epitaxial layer for particle detection has been investigated through extensive experimental characterization. Different pixel layout and read-out schemes have been devised and implemented, as well as different test strategies. In this work test results are reported concerning the response of the detector to IR laser, beta-particles and X-rays stimuli, thus confirming the

D. Passeri; A. Marras; P. Placidi; P. Delfanti; D. Biagetti; L. Servoli; G. M. Bilei; P. Ciampolini

2006-01-01

483

Linear dynamic range enhancement in a CMOS imager  

NASA Technical Reports Server (NTRS)

A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

Pain, Bedabrata (Inventor)

2008-01-01

484

An integrated CMOS detection system for optical short-pulse  

NASA Astrophysics Data System (ADS)

We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of ?-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of M? and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 ?s, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 ?m CMOS technology are presented.

Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

2014-03-01

485

Development of CMOS Imager Block for Capsule Endoscope  

NASA Astrophysics Data System (ADS)

This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

2014-04-01

486

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.  

SciTech Connect

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

2008-08-01

487

25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.  

PubMed

We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 ?m ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 ?m2 footprint. PMID:21997052

Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

2011-10-10

488

116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer  

NASA Astrophysics Data System (ADS)

A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit (ASIC) is fabricated in a 0.5 ?m one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is ?116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5 × 2.5 mm2 and the current is 3.5 mA.

Shanli, Long; Yan, Liu; Kejun, He; Xinggang, Tang; Qian, Chen

2014-09-01

489

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors.  

PubMed

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 ?m standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-01-01

490

Design, characterization and analysis of a 0.35 ?m CMOS SPAD.  

PubMed

Most of the works about single-photon detectors rely on Single Photon Avalanche Diodes (SPADs) designed with dedicated technological processes in order to achieve single-photon sensitivity and excellent timing resolution. Instead, this paper focuses on the implementation of high-performance SPADs detectors manufactured in a standard 0.35-micron opto-CMOS technology provided by AMS. We propose a series of low-noise SPADs designed with a variable pitch from 20 µm down to 5 µm. This opens the further way to the integration of large arrays of optimized SPAD pixels with pitch of a few micrometers in order to provide high-resolution single-photon imagers. We experimentally demonstrate that a 20-micron SPAD appears as the most relevant detector in terms of Signal-to-Noise ratio, enabling emergence of large arrays of SPAD. PMID:25470491

Jradi, Khalil; Pellion, Denis; Ginhac, Dominique

2014-01-01

491

Design, Characterization and Analysis of a 0.35 ?m CMOS SPAD  

PubMed Central

Most of the works about single-photon detectors rely on Single Photon Avalanche Diodes (SPADs) designed with dedicated technological processes in order to achieve single-photon sensitivity and excellent timing resolution. Instead, this paper focuses on the implementation of high-performance SPADs detectors manufactured in a standard 0.35-micron opto-CMOS technology provided by AMS. We propose a series of low-noise SPADs designed with a variable pitch from 20 ?m down to 5 ?m. This opens the further way to the integration of large arrays of optimized SPAD pixels with pitch of a few micrometers in order to provide high-resolution single-photon imagers. We experimentally demonstrate that a 20-micron SPAD appears as the most relevant detector in terms of Signal-to-Noise ratio, enabling emergence of large arrays of SPAD. PMID:25470491

Jradi, Khalil; Pellion, Denis; Ginhac, Dominique

2014-01-01

492

A novel CMOS digital pixel sensor for 1D barcode scanning  

NASA Astrophysics Data System (ADS)

A 1-D CMOS digital pixel image sensor system architecture is presented. Each pixel contains a photodiode, a low-power charge-sensitive amplifier, low noise sample/hold circuit, an 8-bit single-slope ADC, a 12-bit shift register and timing & control logic. The pixel is laid out on a 4?m pitch to enable a cost efficient implementation of high-resolution pixel arrays. Fixed pattern noise (FPN) is reduced by a charge-sensitive feedback amplifier, and the reset noise is cancelled by correlated double sampling read out. A prototype chip containing 512 pixels has been fabricated in the TSMC .25um logic process. A 40?V/e- conversion gain is measured with 100 e- rms read noise.

Yan, Mei; DeGeronimo, Gianluigi; O'Connor, Paul; Carlson, Bradley S.

2004-06-01

493

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors  

PubMed Central

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 ?m standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-01-01

494

1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS Technology  

Microsoft Academic Search

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of