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1

Recent progress in the development of 3D deep n-well CMOS MAPS  

NASA Astrophysics Data System (ADS)

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.

2012-02-01

2

Improving the RF performance of 0.18 ?m CMOS with deep n-well implantation  

Microsoft Academic Search

The radio-frequency (RF) figures of merit of 0.18 ?m complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F t) and maximum oscillation frequency (Fmax). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in

Jiong-Guang Su; Heng-Ming Hsu; Shyh-Chyi Wong; Chun-Yen Chang; Tiao-Yuan Huang; Jack Yuan-Chen Sun

2001-01-01

3

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector  

NASA Astrophysics Data System (ADS)

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 ?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-12-01

4

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing  

NASA Astrophysics Data System (ADS)

We report on further developments of our proposed design approach for a full in-pixel signal processing chain of deep N-well monolithic active pixel sensor, by exploiting the triple well option of a CMOS 130 nm process. Two different geometries of the collecting electrode (namely "Apsel 3 T1M1" and "Apsel 3 T1M2") was implemented to compare their charge collection efficiency. The results of the characterization of the various versions of pixel matrices with a pion beam of 120 GeV/ c at the SPS H6 CERN facility will be presented. The performances of an "Apsel 3 T1" chip irradiated with a dose up to 10 Mrad (Co 60) was also measured. Comparison will be presented among the irradiated and the new chip showing the impact of radiation damages on tracking efficiencies.

Paoloni, E.; Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Calderini, G.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell'Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M. A.; Lusiani, A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Neri, N.; Piendibene, M.; Profeti, A.; Rizzo, G.; Sartori, L.; Walsh, J.; Yurtsev, E.; Manghisoni, M.; Re, V.; Traversi, G.; Bruschi, M.; Di Sipio, R.; Giacobbe, B.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini, N.; Spighi, R.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Citterio, M.; Liberali, V.; Palombo, F.; Andreoli, C.; Gaioni, L.; Pozzati, E.; Ratti, L.; Speziali, V.; Gamba, D.; Giraudo, G.; Mereu, P.; Dalla Betta, G. F.; Soncini, G.; Fontana, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Giacomini, G.; Jugovaz, D.; Lanceri, L.; Rashevskaya, I.; Vitale, L.; Venier, G.

2011-02-01

5

A Simple Test Structure for Directly Extracting Substrate Network Components in Deep n-Well RF-CMOS Modeling  

Microsoft Academic Search

A simple test structure is proposed for accurately extracting the substrate network parameters of a radio-frequency MOSFET with deep n-well implantation from two-port measurements. The test structure with the source, drain, and gate terminals all connected together is used as port one, while the bulk terminal as port two, making the substrate network distinctly accessible in measurements. A methodology is

Jun Liu; Lingling Sun; Liheng Lou; Huang Wang; Charles McCorkell

2009-01-01

6

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

SciTech Connect

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

2011-10-20

7

Carbon Nanotube Integration with a CMOS Process  

PubMed Central

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 ?m CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

8

Micromachined thermal radiation emitter from a commercial CMOS process  

Microsoft Academic Search

Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch

M. Parameswaran; Alexander M. Robinson; David L. Blackburn; Michael Gaitan; Jon Geist

1991-01-01

9

The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process.  

SciTech Connect

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

Ball, D. R. (Vanderbilt University, Nashville, TN); Ahlbin, Jonathan R. (Vanderbilt University, Nashville, TN); Gadlage, Matthew J. (NSWC Crane, Crane, IN); Massengill, Lloyd W. (Vanderbilt University, Nashville, TN); Witulski, A. W. (Vanderbilt University, Nashville, TN); Reed, R. A. (Vanderbilt University, Nashville, TN); Vizkelethy, Gyorgy; Bhuva, Bharat L. (Vanderbilt University, Nashville, TN)

2010-07-01

10

A Standard CMOS Humidity Sensor without Post-Processing  

PubMed Central

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023–10 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

11

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented

Christian Enz; Manfred Punzenberger; Dominique Python

1999-01-01

12

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage (LV) and low-power (LP) analog signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V

C. C. Enz; M. Punzenberger; D. Python

1997-01-01

13

Analog CMOS Implementation of Neural Network for Adaptive Signal Processing  

Microsoft Academic Search

A modular analog CMOS artificial neural network is designed and fabricated for adaptive signal processing. A modified Gilbert multiplier is used as a linear combination of several input signals. Modified back-propagation continuous-time learning rules are used as an adaptive algorithm. The adaptive algorithm adjusts the weights in real time by on-chip learning circuits. Hardware learning circuits are simulated using PSPICE,

Oh Hwa-joon; Fathi M. A. Salam

1994-01-01

14

Bridging Defects Resistance Measurements in a CMOS Process  

Microsoft Academic Search

Measurements on process-related defect nionitwing ,wcijers are presented in order to euuluute the i,csisluiict. ,ualu,e of b ridyzng deJects zn CMOS VLSI circu~ts. 'I'he inethodoloyy u sed is dlustrated and statzstics OIL the 1.esistance values are p resented. As a result, the vast niajoi-zty of the measured brzdges have a 1o.w 7.eszsta.nce. Only a small percentage of the brzdges has

Rosa Rodríguez-montañés; Joan Figueras; Eric Bruls

1992-01-01

15

2D and 3D CMOS MAPS with high performance pixel-level signal processing  

NASA Astrophysics Data System (ADS)

Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

Traversi, Gianluca; Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio

2011-02-01

16

PIN photodiode bandwidth optimization in integrated CMOS process  

NASA Astrophysics Data System (ADS)

Silicon photodiode integrated with CMOS has been in extensive study for the past ten years due to its wide use in applications such as short-distance communication, VCD players, ambient light sensors and many other intelligent systems. In recent years, high speed blue-ray DVD is replacing conventional DVD due to its larger storage capacity and higher speed. In this work, the photodiode optimized for blue ray is fully integrated with standard 0.35um CMOS process and the bandwidth dependency upon thermal process and epitaxial material is investigated. It was found that the additional substrate thermal process can improve bandwidth for blue and red light but reduce bandwidth for infra-red. It is also found that higher level p-type epi doping does not impact bandwidth for blue light but reduces bandwidth for red and infra-red. The various mechanisms of bandwidth were discussed based on the experimental results. It indicated that the bandwidth of photodiodes depends on photo carriers travel time which can be explained by simple model of drift transport and diffusion transport. The design of photodiode should optimize the depletion region and reduce the carrier travel time.

Fang, Fred; Franke, Matthias; Gaebler, Daniel; Sang Sool, Koo

2011-05-01

17

Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors  

NASA Astrophysics Data System (ADS)

In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co ?-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2011-09-01

18

Pressure Sensor Monolithically Integrating MEMS and CMOS-LSI with CMOS Compatible ``Back-end-of-line MEMS processes''  

Microsoft Academic Search

Back-end-of-line (BEOL) MEMS processes for a compact, high-precision pressure sensor was developed. A CMOS-LSI-integrated capacitive pressure-sensor was fabricated with a chip size of 0.72 mm2 using developed BEOL MEMS processes. Multi-sensor chip (with a size of 1.7 by 1.9 mm2) which consists of pressure sensor, temperature sensor and high-precision measurement circuits was also fabricated, and precise atmospheric pressure measurement (~

Tsukasa Fujimori; Hideaki Takano; Yuko Hanaoka; Yasushi Goto

2010-01-01

19

Development of a radiation-hard CMOS process  

NASA Technical Reports Server (NTRS)

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Power, W. L.

1983-01-01

20

Noise performance and ionizing radiation tolerance of CMOS Monolithic Active Pixel Sensors using the 0.18?m CMOS process  

NASA Astrophysics Data System (ADS)

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few ?m), a detection efficiency of gtrsim99.9%, very low material budget (0.05% X0) and good radiation tolerance (gtrsim 1 Mrad, gtrsim 1014 neq/cm2) [1]. This recommends them as an interesting technology for various applications in heavy ion and particle physics. For the vertex detectors of CBM and ALICE, we are aiming at developing large scale sensors with an integration time of 30?s. Reaching this goal is eased by features available in CMOS-processes with 0.18?m feature size. To exploit this option, some sensor designs have been migrated from the previously used 0.35?m processes to this novel process. We report about our first findings with the devices obtained with a focus on noise and the tolerance to ionizing radiation.

Doering, D.; Baudot, J.; Deveaux, M.; Linnik, B.; Goffe, M.; Senyukov, S.; Strohauer, S.; Stroth, J.; Winter, M.

2014-05-01

21

Post assembly process development for Monolithic OptoPill integration on silicon CMOS  

E-print Network

Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that ...

Lei, Yi-Shu Vivian, 1979-

2004-01-01

22

A Calibration-Free Low-Cost Process-Compensated Temperature Sensor in 130 nm CMOS  

Microsoft Academic Search

A calibration-free low-cost CMOS integrated smart temperature sensor is presented that requires significantly less die area than previously published designs through the use of novel circuit technique and the 130 nm CMOS process. Uncalibrated sensor operation is achieved through the extensive use of analog dynamic element matching and chopper stabilization circuitry. A novel process-compensation circuit is presented that uses the

Robert P. Fisk; S. M. Rezaul Hasan

2011-01-01

23

Refined Si-CMOS-MEMS process using AOE, drie and preform bonding  

Microsoft Academic Search

This paper presents a Si-CMOS-MEMS fabrication process that forms released structures out of a 10 µm CMOS metal and oxide stack along with a 50 µm-thick section of the underlying silicon substrate. The process employs back-side silicon grinding that provides silicon mean roughness of 20 nm and maximum peak-to-valley roughness of 264 nm. The thinned MEMS substrate is bonded with

Y.-J. Fang; T. Mukherjee; G. K. Fedder

2011-01-01

24

Technology aspects of a CMOS neuro-sensor: back end process and packaging  

Microsoft Academic Search

A CMOS-compatible process is presented which allows to realize sensor arrays for non-invasive, extracellular, high density, long term recording of neural activity. A high-permittivity biocompatible dielectric is used to capacitively couple nerve cell-induced biological signals to the CMOS circuitry-based electronic world. The transducer consists of a multi layer of TiO2 and ZrO2 and is fabricated in the backend of a

Franz Hofmann; Björn Eversmann; Martin Jenkner; Alexander Frey; Matthias Merz; Tamara Birkenmaier; Peter Fromherz; Matthias Schreiter; Reinhard Gabl; Kurt Plehnert; Michael Steinhauser; Gerald Eckstein; Roland Thewes

2003-01-01

25

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process  

NASA Astrophysics Data System (ADS)

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

2013-04-01

26

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process.  

PubMed

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

27

Integration of solid-state nanopores in a 0.5 ?m cmos foundry process  

PubMed Central

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

28

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications  

NASA Astrophysics Data System (ADS)

The prototype of a three-dimensional (3D) monolithic active pixel sensor (MAPS) has been characterized. The device, featuring a 20 ?m pitch, was designed based on the same approach that was adopted in developing the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS technology. Different kinds of test structures, including single pixels, 3×3 arrays and 8×8 and 16×16 matrices were tested. Functionality of the collecting deep N-well electrode, the analog front-end and the digital readout electronics has been demonstrated. Inter-tier communication was found to work properly in the case of redundant interconnection and could be exploited for the test of the analog pixel section. On the other hand, inter-tier interconnections based on individual bond pads were proven ineffective likely due to wafer misalignment.

Ratti, L.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Re, V.; Traversi, G.

2013-01-01

29

Fabrication of a micro humidity sensor with polypyrrole using the CMOS process  

Microsoft Academic Search

This study investigates the fabrication of a micro humidity sensor integrated with circuitry using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The advantages of the humidity sensor include small volume, high sensitivity, and integrated with circuitry on a chip. The sensor, which is a capacitive type, comprises the improved

Ching-Liang Dai; De-Hao Lu

2010-01-01

30

Overview of CMOS process and design options for image sensor dedicated to space applications  

NASA Astrophysics Data System (ADS)

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35?m generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

31

On process variation tolerant low cost thermal sensor design in 32nm CMOS technology  

Microsoft Academic Search

Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However,

Spandana Remarsu; Sandip Kundu

2009-01-01

32

A Nano-CMOS Process Variation Induced Read Failure Tolerant SRAM Cell  

E-print Network

A Nano-CMOS Process Variation Induced Read Failure Tolerant SRAM Cell Jawar Singh, Jimson Mathew the design of low power embedded SRAMs increasingly impor- tant. Moreover, with increase in device density a larger fraction of the SoC area is devoted to SRAM, because on-chip memory offers high system performance

Mohanty, Saraju P.

33

Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations  

E-print Network

Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations Jawar Singh, Jimson@cs.bris.ac.uk, smohanty@unt.edu Abstract-- Several design metrics have been used in the past to evaluate the SRAM cell. Therefore, we investigate new stability metrics and report the stability analysis for typical a SRAM cell

Mohanty, Saraju P.

34

Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes  

Microsoft Academic Search

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths

Balaji Narasimham; Bharat L. Bhuva; Ronald D. Schrimpf; Lloyd W. Massengill; Matthew J. Gadlage; T. W. Holman; Arthur F. Witulski; William H. Robinson; Jeffrey D. Black; Joseph M. Benedetto; Paul H. Eaton

2008-01-01

35

Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes  

Microsoft Academic Search

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths

Balaji Narasimham; Bharat L. Bhuva; Ronald D. Schrimpf; Lloyd W. Massengill; Matthew J. Gadlage; W. Timothy Holman; Arthur F. Witulski; William H. Robinson; Jeffrey D. Black; Joseph M. Benedetto; Paul H. Eaton

2007-01-01

36

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing  

PubMed Central

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Bravo, Ignacio; Balinas, Javier; Gardel, Alfredo; Lazaro, Jose L.; Espinosa, Felipe; Garcia, Jorge

2011-01-01

37

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array  

PubMed Central

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 ?m CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Lopez-Huerta, Francisco; Herrera-May, Agustin L.; Estrada-Lopez, Johan J.; Zuniga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

38

A 1.2 V companding current-mode integrator for standard digital CMOS processes  

Microsoft Academic Search

A low-voltage current-mode integrator using voltage companding and operating in class AB is presented. The integrator is made only with transistors without any functional capacitors and is therefore suited to the integration in a digital CMOS process. It has been used in a 4th-order Tchebycheff low-pass filter which can be tuned from 20 Hz to 20 kHz and achieves total

Dominique Python; Rafael Fried; Christian C. Enz

1996-01-01

39

High performance CMOS converter design in TSMC 0.18-?m process  

Microsoft Academic Search

This paper demonstrates the low voltage operation of a double balanced Gilbert mixer fabricated in 0.18-?m standard\\/bulk CMOS process. A tuned load was used to ensure the rail-to-rail swing and a source degeneration resistor was used to improve the linearity. As an upconverter, the mixer demonstrates 1.65 dB of conversion gain at an RF frequency of 1.9 GHz with an

Nazmul Islam; Syed K. Islam; Hasina F. Huq

2005-01-01

40

A novel pH sensitive ISFET with on chip temperature sensing using CMOS standard process  

Microsoft Academic Search

A monolithic chip processing method is reported, which includes the ion sensitive field effect transistor (ISFET) of the pH sensor, p–n diode of temperature sensor and readout circuit using 0.5?m double poly double metal (DPDM) standard CMOS product with UMC IC foundry company. We have designed a planar diffused silicon diode on a n-channel pH sensitive ISFET sensor to act

Yuan-Lung Chin; Jung-Chuan Chou; Tai-Ping Sun; Wen-Yaw Chung; Shen-Kan Hsiung

2001-01-01

41

High-speed bipolar phototransistors in a 180 nm CMOS process  

NASA Astrophysics Data System (ADS)

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 ?m2 and 100×100 ?m2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p- epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Kostov, P.; Gaberl, W.; Zimmermann, H.

2013-03-01

42

10GBase-LX4 optical fiber receiver in a 0.18µm digital CMOS process  

Microsoft Academic Search

In this paper, a monolithic CMOS optical receiver designed in a 0.18mum digital process suitable for 10GBase-LX4 optical fiber transmissions is described. The system is based on CMOS actively loaded inverter structures and works with a single 1.8 V supply voltage. The thermal effects are minimized between -20 and 80 degC by using two different compensation techniques. The design presents

Jose Maria Garcia Del Pozo; Maria Teresa Sanz; Santiago Celma; Aránzazu Otín; Juan Pablo Alegre; Justo Sabadell

2008-01-01

43

Modeling and Testing Process Variation in Nanometer CMOS  

Microsoft Academic Search

As device technology progresses toward 45nm and beyond, the fidelity of the process parameter modeling becomes questionable. In this paper we propose the concept of process variation (PV) testing. This is achieved by applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, our architecture

Mehrdad Nourani; Arun Radhakrishnan

2006-01-01

44

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors  

Microsoft Academic Search

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-?m single-poly n-well CMOS process.

Christian Menolfi; Qiuting Huang

1997-01-01

45

An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier  

NASA Astrophysics Data System (ADS)

We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 32×80 element CMOS active pixel array was implemented in a 0.8 ?m CMOS double poly, n-well process with a pixel pitch of 50 ?m. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

Abdalla, M. A.; Fröjdh, C.; Petersson, C. S.

2001-06-01

46

A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration  

PubMed Central

This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-?m 2P4M CMOS process, and a robust resolution of 0.05 °C and dissipation of 25 ?W were achieved at a sample rate of 10 samples/s. An inaccuracy of ?0.35 °C to 1.35 °C was achieved after one-point calibration at temperatures ranging from ?40 °C to 120 °C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

Chen, Chun-Chi; Lin, Yi

2014-01-01

47

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.

1980-01-01

48

Modeling and manufacturing of a micromachined magnetic sensor using the CMOS process without any post-process.  

PubMed

The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 mm complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA. PMID:24732100

Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

2014-01-01

49

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

50

CMOS\\/BiCMOS power amplifier technology trend in Japan  

Microsoft Academic Search

Aiming for 2-5GHz band transceiver system on a chip, the integration of RF section has been developed by using conventional CMOS\\/BiCMOS (SiGeCMOS) process. The attempts to integrate power amplifiers (PA's) have been successful for low transmit power system such as Bluetooth, but these attempts are very limited due to the poor power handling capability of FET's in CMOS and the

Noriharu Suematsu; Shintaro Shinjo

2001-01-01

51

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes  

Microsoft Academic Search

This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0.18 mum CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles

Vincent Goiffon; Cédric Virmontois; Pierre Magnan; Paola Cervantes; Franck Corbière; Magali Estribeau; Philippe Pinel

2010-01-01

52

P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP  

E-print Network

P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP Garima, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual is constructed to show the fea- sibility of the proposed SRAM cell. To the best of the authors' knowledge

Mohanty, Saraju P.

53

Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor  

NASA Astrophysics Data System (ADS)

This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

2013-09-01

54

Avoiding sensor blindness in Geiger mode avalanche photodiode arrays fabricated in a conventional CMOS process  

NASA Astrophysics Data System (ADS)

The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

Vilella, E.; Diéguez, A.

2011-12-01

55

A 33-mpixel 120-fps CMOS image sensor using 0.11-?m CIS process  

NASA Astrophysics Data System (ADS)

We have been researching and developing a CMOS image sensor that has 2.8 ?m x 2.8 ?m pixel, 33-Mpixel resolution (7680 horizontal pixels x 4320 vertical pixels), 120-fps frame rate, and 12-bit analog-to-digital converter for "8K Super Hi-Vision." In order to improve its sensitivity, we used a 0.11-?m nanofabricated process and attempted to increase the conversion gain from an electron charge to a voltage in the pixel. The prototyped image sensor shows a sensitivity of 2.4 V/lx•s, which is 1.6 times higher than that of a conventional image sensor. This image sensor also realized the input-referred random noise as low as 2.1 e-rms.

Yasue, Toshio; Hayashida, Tetsuya; Yonai, Jun; Kitamura, Kazuya; Watabe, Toshihisa; Ootake, Hiroshi; Shimamoto, Hiroshi; Kosugi, Tomohiko; Watanabe, Takashi; Aoyama, Satoshi; Kawahito, Shoji

2014-05-01

56

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.  

PubMed

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-01-01

57

Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing  

PubMed Central

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

He, Diwei; Nguyen, Hoang C.; Hayes-Gill, Barrie R.; Zhu, Yiqun; Crowe, John A.; Gill, Cally; Clough, Geraldine F.; Morgan, Stephen P.

2013-01-01

58

Optimisation of a Geiger mode avalanche photodiode imaging pixel based on a hybrid bulk SOI CMOS process  

NASA Astrophysics Data System (ADS)

Single photon detection has a wide variety of scientific and industrial applications including optical time domain reflectometry, astronomy, spectroscopy, defect monitoring of Complementary Metal Oxide Semiconductor (CMOS) circuits, fluorescence lifetime measurement and imaging. In imaging applications, the dead time is the time during which the detector is inhibited after a photon has been detected. This is a limiting factor on the dynamic range of the pixel. The rate of photon detection will saturate if the dead time is too large. Time constants generated by Metal Oxide Semiconductor (MOS) transistor bulk and sidewall capacitances adversely affect the dead time of pixels developed in conventional CMOS technology. In this paper, a novel imaging pixel configuration based on a Geiger Mode Avalanche Photodiode (GMAP) and fabricated using a dedicated hybrid bulk Silicon On Insulator (SOI) CMOS process is presented. The GMAP is fabricated in the bulk layer and the CMOS circuitry is implemented in the upper SOI layers. As a result, bulk and sidewall capacitance effects are significantly reduced. As both the diode and the CMOS transistors are on the same wafer there is a reduction in pixel area and an additional reduction in the parasitic capacitance effects. This leads to a significant improvement in pixel performance. Pixels incorporating 5 micron and 10 micron diameter GMAPs have been simulated. The circuits were optimised with a view to maximising the photon count rate. Results show a significant improvement in the dead time with values of 14 nanoseconds and 15 nanoseconds being observed for the 5 micron and 10 micron GMAPs respectively.

Coakley, Niall G.; Moloney, Aoife M.; Schwarzbacher, Andreas T.

2007-10-01

59

Monolithic electronic-photonic integration in state-of-the-art CMOS processes  

E-print Network

As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

Orcutt, Jason S. (Jason Scott)

2012-01-01

60

Current mode integrators and their applications in low-voltage high frequency CMOS signal processing  

E-print Network

Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented.. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve...

Smith, Sterling Lane

2012-06-07

61

Zero-space microlenses for CMOS image sensors: optical modeling and lithographic process development  

NASA Astrophysics Data System (ADS)

Microlens arrays are widely used on image sensor products to control incident light propagation onto an appropriate sensor, in order to increase collection efficiency and reduce optical cross-talk. Typically microlenses are formed by defining arrays of photoresist islands using standard lithographic techniques, then melting and cross-linking the resist to form stable microlens arrays. A space between the resist islands is necessary to avoid the lenses merging during melting. The minimum space is constrained by lithographic resolution. Such refractive microlens arrays are a part of Tower Semiconductor"s standard offering for CMOS Image Sensor products. In order to understand the contribution of alternative microlens fabrication processes to optical cross-talk, optical simulation techniques have been developed at Tower Semiconductor and applied to quantify the performance of microlenses in image sensors. Amongst other factors, these simulations quantify the effect of the space between microlenses. Several alternative fabrication techniques have been compared, including a process to remove the lithographic resolution constraint and form microlens arrays with arbitrary spacing between lenses.

Baillie, Douglas A.; Gendler, Jonathan E.

2004-05-01

62

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process  

NASA Astrophysics Data System (ADS)

A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two-dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is -120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is -169 dBc/Hz.

Haijun, Gao; Lingling, Sun; Xiaofei, Kuang; Liheng, Lou

2012-07-01

63

A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology  

Microsoft Academic Search

A focal-plane array (FPA) for room-temperature detection of 0.65-THz radiation has been fully integrated in a low-cost 0.25 mum CMOS process technology. The circuit architecture is based on the principle of distributed resistive self-mixing and facilitates broadband direct detection well beyond the cutoff frequency of the technology. The 3 timesZ 5 pixel array consists of differential on-chip patch antennas, NMOS

Erik Ojefors; Ullrich R. Pfeiffer; Alvydas Lisauskas; Hartmut G. Roskos

2009-01-01

64

A 5.8 GHz Linear Power Amplifier in a Standard 90nm CMOS Process using a 1V Power Supply  

Microsoft Academic Search

A fully integrated 5.8 GHz class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or

Peter Haldi; Debopriyo Chowdhury; Gang Liu; Ali M. Niknejad

2007-01-01

65

CMOS RF Power Amplifier Design for Wireless Communications  

E-print Network

power, while the electronic isolation of the transformersPower Ratio CE Consumer Electronic CMOS Complementary Metal-Oxide-Semiconductor CMOS+ Post-CMOS backend process module DAT Distributive Active Transformer

FANG, Qiang

2012-01-01

66

Designing a ring-VCO for RFID transponders in 0.18 ?m CMOS process.  

PubMed

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 ?m process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. PMID:24587731

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

67

Designing a Ring-VCO for RFID Transponders in 0.18 ?m CMOS Process  

PubMed Central

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42?GHz operated active RFID transponders compatible with IEEE 802.11?b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18??m process is adopted for designing the circuit with 1.5?V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54?GHz and dissipates 2.47?mW of power. It exhibits a phase noise of ?126.62?dBc/Hz at 25?MHz offset from 2.42?GHz carrier frequency. PMID:24587731

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

68

New mechanism of plasma induced damage on CMOS image sensor: Analysis and process optimization  

Microsoft Academic Search

A new plasma induced damage mechanism on CMOS image sensor is analyzed. An increase of the mean pixel dark current is observed after the plasma etch of a cavity on the pixel area. The degradation increases non-linearly when the dielectric layers between the photodiode and the plasma become thinner. This can be explained by a photo generation phenomenon in the

J. P. Carre?re; J. P. Oddou; C. Richard; C. Jenny; M. Gatefait; C. Aumont; A. Tournier; F. Roy

2010-01-01

69

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic  

Microsoft Academic Search

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies,

Kumar Yelamarthi; Chien-In Henry Chen

2009-01-01

70

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing  

NASA Astrophysics Data System (ADS)

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

2014-06-01

71

Numerical Simulation Analysis of CMOS Compatible Process of 50 nm Vertical Single and Double Gate NMOSFET  

NASA Astrophysics Data System (ADS)

Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using oblique rotating ion implantation (ORI) technique addressed by numerical simulation. An electrical characterization of the device demonstrated a suppression of short channel effects (SCE) that was quantitatively given by an analysis of transfer and output characteristics with a reasonable value of threshold voltage (VT), drive and off -leakage current (ION and IOFF), saturation current (IDSat), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). These results show that the vertical transistor is seen to offer considerable advantages down to the 100 nm node and beyond due to the dual or surround channels and the ability to produce a 50 nm channel length with relax lithography.

Saad, I.; Ismail, R.

2010-03-01

72

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)\\/CMOS Hybrid Process  

Microsoft Academic Search

We propose a complementary self-biasing method which enables the single-electron transistor (SET)\\/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron

Ki-Whan Song; Yong Kyu Lee; Jae Sung Sim; Kyung Rok Kim; Jong Duk Lee; Byung-Gook Park; Young Sub You; Joo-On Park; You Seung Jin; Young-Wug Kim

2005-01-01

73

Differential Temperature Sensors Fully Compatible With a 0.35- m CMOS Process  

Microsoft Academic Search

Four differential temperature sensors, two passive and two active, designed and fabricated in a 0.35-m standard CMOS technology, are presented and characterized. Passive sensors are based on integrated thermopiles. Each one consists of eight thermocouples (16 strips) serially connected: poly1-poly2 for the first thermopile and poly1-P+diffusion for the second one. The active sensors are based on differential amplifiers, one with

Eduardo Aldrete-Vidrio; Diego Mateo; Josep Altet

2007-01-01

74

A 63 GHz VCO using a standard 0.25 ?m CMOS process  

Microsoft Academic Search

A 63 GHz VCO using a 0.25 ?m 1P6M CMOS is presented. It achieves an output power of -4 dBm without any output amplifier. This VCO is tunable over a 2.5 GHz range and its phase noise is -85 dBc\\/Hz at 1 MHz offset. The IC covers an area of 0.315 mm2 and consumes 118 mW maximum.

Ren-Chieh Liu; Hong-Yeh Chang; Chi-Hsueh Wang

2004-01-01

75

CMOS PIN fiber receiver and DVD OEIC  

Microsoft Academic Search

Two monolithically integrated PIN CMOS OEICs (optoelectronic integrated circuits) are presented: A high-speed CMOS PIN fiber receiver for optical data transmission and optical interconnects and a CMOS PIN OEIC for optical storage systems. Both OEICs were integrated in a 1.0 ?m twin-well CMOS-process, using PIN-photodiodes as photodetectors. For the high-speed fiber receiver a NRZ data rate of 622 Mbit\\/s is

A. Ghazi; T. Heide; H. Zimmermann; P. Seegebrecht

1999-01-01

76

Charge-coupled CMOS and hybrid detector arrays  

NASA Astrophysics Data System (ADS)

Over a decade has passed since complementary metal oxide semiconductor (CMOS) imaging detectors made their move into the charge-coupled device (CCD) arena. Low cost, low power, on-chip system integration, high-speed operation and tolerance to high-energy radiation sources are unique features that make CMOS detectors popular. However, it remains unclear if CMOS arrays can compete with the CCD in high performance applications (e.g., scientific). This paper compares fundamental performance parameters common to both CMOS and CCD imagers, and lists specific SMOS performance deficiencies that prevent the technology from high end use. In this paper we will present custom CMOS pixel designs and related fabrication processes that solve most deficiencies. We will also discuss "hybrid" imaging arrays that marry the advantages of CCD and CMOS producing sensors with superior performance in comparison to CCD and CMOS bulk monolithic sensors. CCD to CMOS, CMOS to CMOS and CMOS SOI hybrids are reviewed.

Janesick, James R.

2004-01-01

77

CMOS dot matrix microdisplay  

NASA Astrophysics Data System (ADS)

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

78

Design and characterization of the immersion-type capacitive ultrasonic sensors fabricated in a CMOS process  

NASA Astrophysics Data System (ADS)

This work presents the CMOS micromachined capacitive sensors for ultrasound detection in water. The sensing membranes with a 60 µm diameter are released through small etchant holes of 2 µm × 2 µm by a post-CMOS metal etch and sealed with the thinnest possible silicon dioxide (type A) or parylene-D film (type B). Nine membranes form a single detection unit with a capacitance value of 292.5 fF. Convenient routing, which is desired for making a large two-dimensional array, is allowed with the detection circuits being placed directly beneath the sensing membranes. An alternating voltage bias is applied to the sensing electrodes for stabilizing the sensed signals which would otherwise attenuate over time due to trapped charges between electrodes. Resonant frequencies of type-A and type-B sensors in water are 8.8 and 5.8 MHz, with fractional bandwidths of 0.43 and 0.55, respectively. The measured sensitivities are 151.0 and 369.8 mVpp MPa-1 V-1. The equivalent noise pressures, based on the measured thermal noise, are 3.3 and 1.35 Pa Hz-1/2 at a 1 V membrane bias.

Tang, Po-Kai; Wang, Po-Hsun; Li, Meng-Lin; S-C Lu, Michael

2011-02-01

79

Development and production integration of a planarized AlCu interconnect process for submicron CMOS  

NASA Astrophysics Data System (ADS)

A planarized aluminum alloy interconnect has been developed as an alternative to tungsten plugs for a 0.65 (mu) CMOS technology. Contact resistance can increase with either an inadequate RF sputter clean or titanium that is too thin to reduce the native oxide. Diffusion barrier results show that a minimum amount of titanium nitride, whether deposited conventionally or with collimation, is necessary for low junction leakage and good sort yield. Stacked contacts and vias are supported while via resistance and defect density are improved. Electrical bridging due to silicon residues from AlSiCu can be minimized with metal overetching, but not to the extent of AlCu. Sidewall pitting was observed to be due to galvanic corrosion from copper precipitate formation. Overall yield has been improved along with decreased wafer cost compared to conventional tungsten plug technology.

Brown, Kevin C.; Hill, Rodney; Reddy, Krishna; Gadepally, Kamesh

1995-09-01

80

Charged particle detection performances of CMOS pixel sensors produced in a 0.18 um process with a high resistivity epitaxial layer  

E-print Network

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 um thin CMOS Pixel Sensors (CPS) covering either the 3 innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 um CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 um CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 10^13 n_eq/cm^2 was observed to yield a SNR ranging between 11 and 23 for coolant temperatures varying from 15 C to 30 C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation respectively. These satisfactory results allow to validate the TowerJazz 0.18 um CMOS process for the ALICE ITS upgrade.

Serhiy Senyukov; Jerome Baudot; Auguste Besson; Gilles Claus; Loic Cousin; Andrei Dorokhov; Wojciech Dulinski; Mathieu Goffe; Christine Hu-Guo; Marc Winter

2013-01-03

81

Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors  

NASA Astrophysics Data System (ADS)

Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 micrometers pitch in a 1.2 micrometers n-well CMOS process and a 40 micrometers pitch in a 2 micrometers n-well CMOS process. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 (mu) W at a 5 KHz conversion rate.

Panicacci, Roger; Pain, Bedabrata; Zhou, Zhimin; Nakamura, Junichi; Fossum, Eric R.

1996-03-01

82

Single-chip CMOS anemometer  

Microsoft Academic Search

For the first time a packaged single-chip anemometry microsystem is reported. The system includes a thermal CMOS flow sensor with on-chip power management, signal conditioning, and A\\/D conversion. It is fabricated using an industrial IC process followed by post-CMOS micromachining. The system is packaged on a flexible substrate using flip-chip interconnection technology. The measurement of wind speeds is demonstrated in

F. Mayer; A. Haberli; H. Jacobs; G. Ofner; O. Paul; H. Baltes

1997-01-01

83

CMOS array design automation techniques  

NASA Technical Reports Server (NTRS)

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lombardi, T.; Feller, A.

1976-01-01

84

A CCD\\/CMOS image motion sensor  

Microsoft Academic Search

Presents a 1D image motion sensor with a 115-pixel linear image sensor and analog CCD\\/CMOS processors that correlates two image frames that are spatially shifted between -5 and +5 pixels, to estimate object motion over a range of ±1 to ±5000 pixels\\/s. The CCD\\/CMOS smart sensor chip is fabricated with a standard double poly, double metal, 2-?m CMOS\\/CCD process available

Massimo Gottardi; Woodward Yang

1993-01-01

85

BLINC: a 640x480 CMOS active pixel video camera with adaptive digital processing, extended optical dynamic range, and miniature form factor  

NASA Astrophysics Data System (ADS)

A miniaturized camera utilizing advanced extended dynamic range CMOS APS imager technology and employing real-time histogram equalization has been developed for capturing scenes having high intra-scenic dynamic range. The camera adapts to changes in scene brightness and contrast in two frame periods, and acquires fully processed images in less than 100 milliseconds after power is applied. The BLINC camera contains an automatic exposure time control and is capable of capturing over 8 equivalent f-stops of optical dynamic range. This exposure time control along with programmable extended dynamic range and built-in 12-bit analog to digital converter allows the Sarnoff APS75 CMOS VGA image sensor to accommodate up to 15 f-stops of intra- scenic dynamic range. The APS75 sensor was fabricated with standard CMOS-7 design rules in a 0.5 micron SPTM process. Progressive scan digital video is stored and processed in real-time by an application specific integrated circuit image processor to provide optimal image contrast and exposure. The processed video is then transformed to 10-bits with a proprietary adaptive non-linear mapper before being converted to standard RS-170 analog video. Small size, light weight and low energy consumption make this camera well suited for UAV, and automotive applications.

Smith, Scott T.; Zalud, Peter; Kalinowski, John; McCaffrey, Nathaniel J.; Levine, Peter A.; Lin, Min-Long

2001-05-01

86

An ultra low phase noise GSM local oscillator in a 0.09 ?m standard digital CMOS process with no high-Q inductors  

Microsoft Academic Search

A design approach is presented for realizing a fully integrated local oscillator, covering all 4 GSM bands, and fulfilling the stringent phase noise requirement of -162 dBc\\/Hz at a 20-MHz offset from a 915-MHz carrier in a 1.4-V 0.09-?m digital CMOS process. By operating a digitally-controlled oscillator at a 4× frequency followed by ÷ 4 frequency dividers, the requirements of

Chih-Ming Hung; Nathen Barton; Meng-Chang Lee; Dirk Leipold

2004-01-01

87

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-?m CMOS process  

NASA Astrophysics Data System (ADS)

We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-?m complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 ?s with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Zhu, Si-Heng; Si, Li-Ming; Guo, Chao; Shi, Jun-Yu; Zhu, Wei-Ren

2014-07-01

88

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit.  

PubMed

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal processing is accomplished with a current-to-frequency converter circuit that forms the causal portion of the matched filter for dc luminescence in wide-band white noise. Measurements show that luminescence can be detected from as few as 4 x 10(5) cells/ml. PMID:12192685

Simpson, M L; Sayler, G S; Patterson, G; Nivens, D E; Bolton, E K; Rochelle, J M; Arnott, J C; Applegate, B M; Ripp, S; Guillorn, M A

2001-01-25

89

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

90

Hinged polysilicon structures with integrated CMOS TFTs  

Microsoft Academic Search

The surface micromachining process described can produce a variety of microelectromechanical components, including CMOS thin film transistors and three dimensional polysilicon structures with large features and high detail in all three dimensions. Polysilicon structural elements are made with integrated hinges, which allow three dimensional structures to be erected out of the plane of the wafer. CMOS transistors are integrated directly

Kristofer S. J. Pister

1992-01-01

91

Thermoelectric infrared sensors by CMOS technology  

Microsoft Academic Search

The authors report two integrated thermoelectric infrared sensors on thin silicon oxide\\/nitride microstructures realized by industrial CMOS IC technology, followed by one compatible single maskless anisotropic etching step. No additional material is needed to enhance infrared absorption since the passivation layer, as provided by the CMOS process, is sufficient for certain spectral bands. The responsivities are between 12 and 28

Rene Lenggenhager; Henry Baltes; Jon Peer; Martin Forster

1992-01-01

92

Spin-on-glass/phosphosilicate glass etchback planarization process for 1.0 um CMOS technology  

NASA Astrophysics Data System (ADS)

Studies of SOG/oxide planarization etch back processes have shown that micro loading effects play a major role in shifting selectivity of the etch at the SOG/oxide interface thereby causing the wafer to lose its asspun level of pianarization. This paper describes recent work performed to improve an SOG/PSG etchback planarizatiori process used in production on 1. O/m geome tries. The etchback planarization process is run in a Drytek Model 616 etch system using a triode chamber. In the study the effect of CHF3 C2F6 SF6 and CF4 gas chemistries on etch planarization are examined. Results of these experiments and how they compare to the original production etchback planarization process are discussed.

Bogle-Rohwer, Elizabeth; Nulty, James E.; Chu, Wileen; Cohen, Andrew

1991-03-01

93

Low-k materials as interlayer dielectrics in CMOS: The effects of deposition and processing on N-channel MOSFET's characteristics  

NASA Astrophysics Data System (ADS)

We report on comprehensive studies of the effects, on n- channel metal-oxide-silicon field-effect transistors (MOSFETs), of deposition and processing of low-k interlayer dielectrics (ILDs) in complementary MOS (CMOS). We have explored the ILD candidacy of fluorinated silicon oxide (FSO), fluorinated poly(erylene)ethers (FLARE), and divinylsiloxane-benzocyclobutane (BCB). We have observed that FLARE and BCB degradation by plasma exposures manifests itself as changes in the physical properties especially leakage current, which is observed to increase by several orders of magnitude. This degradation is proposed to result from bond scissioning, bond cross-linking and void formation processes which are promoted by ion bombardment, ultra-violet radiation, and plasma charging mechanisms associated with plasma exposures. The latter mechanism is suggested to be the dominant degradation mechanism in FLARE and BCB and is observed to contribute the largest share to MOSFET's damage from via etching of FLARE or BCB, as a second ILD, in a 0.35 and 0.5 ?m channel length full flow CMOS process. The severity of this MOSFET damage is significantly reduced by the inclusion of a thin insulating Si3N4 layer underneath the ILD or annealing at 350°C in forming gas (94% N2 and 6% H2). In CMOS processes utilizing FSO as an ILD we have observed that fluorine interactions, coupled with plasma charging, adversely affects MOSFET's Fowler-Nordheim reliability via fluorine passivation/depassivation of bulk gate oxide and oxide/silicon interface defects. Overall, these results underscore the negative effects of ILD processing on MOSFET's characteristics and call for these effects to be reckoned with in making the choice of a suitable low-k ILD.

Trabzon, Levent

2000-10-01

94

Uniaxial-process-induced strained-Si: extending the CMOS roadmap  

Microsoft Academic Search

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are

S. E. Thompson; Guangyu Sun; Y. S. Choi; T. Nishida; G. Sun

2006-01-01

95

A CNN UNIVERSAL CHIP IN CMOS TECHNOLOGY  

Microsoft Academic Search

This paper describes the design of a programmable Cellular Neural Network (CNN) chip,with added functionalities similar to those of the CNN Universal Machine. The prototype contains1024 cells and has been designed in a 1.0|ìm, n-well CMOS technology. Careful selectionof the topology and design parameters has resulted in a cell density of 31 cells\\/mm2and around7-8 bits accuracy in the weight values.

S. ESPEJO; R. Domínguez-Castro; R. Carmona; A. RODRÍGUEZ-VÁZQUEZ

1996-01-01

96

Traveling wave electrode design for ultra compact carrier-injection HBT-based electroabsorption modulator in a 130nm BiCMOS process  

NASA Astrophysics Data System (ADS)

Silicon photonic system, integrating photonic and electronic signal processing circuits in low-cost silicon CMOS processes, is a rapidly evolving area of research. The silicon electroabsorption modulator (EAM) is a key photonic device for emerging high capacity telecommunication networks to meet ever growing computing demands. To replace traditional large footprint Mach-Zehnder Interferometer (MZI) type modulators several small footprint modulators are being researched. Carrier-injection modulators can provide large free carrier density change, high modulation efficiency, and compact footprint. The large optical bandwidth and ultra-fast transit times of 130nm HBT devices make the carrierinjection HBT-based EAM (HBT-EAM) a good candidate for ultra-high-speed optical networks. This paper presents the design and 3D full-wave simulation results of a traveling wave electrode (TWE) structure to increase the modulation speed of a carrier-injection HBT-EAM device. A monolithic TWE design for an 180um ultra compact carrier-injection-based HBT-EAM implemented in a commercial 130nm SiGe BiCMOS process is discussed. The modulator is electrically modeled at the desired bias voltage and included in a 3D full-wave simulation using CST software. The simulation shows the TWE has a S11 lower than -15.31dB and a S21 better than -0.96dB covering a bandwidth from DC-60GHz. The electrical wave phase velocity is designed close to the optical wave phase velocity for optimal modulation speed. The 3D TWE design conforms to the design rules of the BiCMOS process. Simulation results show an overall increase in modulator data rate from 10Gbps to 60Gbps using the TWE structure.

Fu, Enjin; Joyner Koomson, Valencia; Wu, Pengfei; Huang, Z. Rena

2014-03-01

97

Low-Noise CMOS Circuits for On-Chip Signal Processing in Focal-Plane Arrays  

NASA Astrophysics Data System (ADS)

The performance of focal-plane arrays can be significantly enhanced through the use of on-chip signal processing. Novel, in-pixel, on-focal-plane, analog signal-processing circuits for high-performance imaging are presented in this thesis. The presence of a high background-radiation is a major impediment for infrared focal-plane array design. An in-pixel, background-suppression scheme, using dynamic analog current memory circuit, is described. The scheme also suppresses spatial noise that results from response non-uniformities of photo-detectors, leading to background limited infrared detector readout performance. Two new, low-power, compact, current memory circuits, optimized for operation at ultra-low current levels required in infrared-detection, are presented. The first one is a self-cascading current memory that increases the output impedance, and the second one is a novel, switch feed-through reducing current memory, implemented using error-current feedback. This circuit can operate with a residual absolute -error of less than 0.1%. The storage-time of the memory is long enough to also find applications in neural network circuits. In addition, a voltage-mode, accurate, low-offset, low-power, high-uniformity, random-access sample-and-hold cell, implemented using a CCD with feedback, is also presented for use in background-suppression and neural network applications. A new, low noise, ultra-low level signal readout technique, implemented by individually counting photo-electrons within the detection pixel, is presented. The output of each unit-cell is a digital word corresponding to the intensity of the photon flux, and the readout is noise free. This technique requires the use of unit-cell amplifiers that feature ultra-high-gain, low-power, self-biasing capability and noise in sub-electron levels. Both single-input and differential-input implementations of such amplifiers are investigated. A noise analysis technique is presented for analyzing sampled-data systems having 1/f noise reduction capability. Closed form expressions have been derived and low-noise design criteria have been established, taking into account both the 1/f and white noise, and the effects of under-sampling. The analysis technique will be an important tool for analysis and design of a large variety of focal-plane sampled-data signal processing circuits.

Pain, Bedabrata

98

CMOS Meets Bio  

Microsoft Academic Search

There are burgeoning efforts to use CMOS ICs for biotechnology. This paper reviews one such effort, development of a CMOS\\/Microfluidic hybrid system for magnetic manipulation of biological cells originally reported by the authors in H. Lee et al. (2005, 2006). Programmable magnetic field patterns produced by a CMOS microcoil array IC efficiently manipulate individual cells (tagged by magnetic beads) inside

Yong Liu; Hakho Lee; R. M. Westervelt; D. Ham

2006-01-01

99

Integrated RF MEMS/CMOS Devices  

E-print Network

A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

Mansour, R R; Bakeri-Kassem, M

2008-01-01

100

Review of radiation damage studies on DNW CMOS MAPS  

NASA Astrophysics Data System (ADS)

Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7·1013 cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

2013-12-01

101

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager  

PubMed Central

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 ?m pixel pitch fabricated in a standard 0.5 ? CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 ?A from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 ?W/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

102

CMOS image sensors  

Microsoft Academic Search

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most

A. El Gamal; H. Eltoukhy

2005-01-01

103

Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 um CMOS Process  

PubMed Central

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

2014-01-01

104

Ion traps fabricated in a CMOS foundry  

E-print Network

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

2014-01-01

105

Impurity diffusion behavior of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5-?m Bi-CMOS process  

Microsoft Academic Search

A low-temperature-processed (800-850°C) bipolar transistor design suitable for the high-performance 0.5-?m BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region. and insufficient arsenic diffusion from the poly Si are serious considerations if low-temperature furnace annealing is used. If high-temperature rapid thermal annealing (RTA) is used

Masayuki Norishima; Hiroshi Iwai; Youichiro Niitsu; Kenji Maeguchi

1992-01-01

106

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

Microsoft Academic Search

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force

Weiquan Zhang

2000-01-01

107

Low-Power Strategies for High-Performance CMOS Circuits  

Microsoft Academic Search

Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as

Tobias G. Noll; RWTH Aachen Rogowski-Institu

1994-01-01

108

256 x 256 CMOS active pixel image sensor  

NASA Astrophysics Data System (ADS)

A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source. At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 (mu) V, yielding a dynamic range of 72 dB (12 bits). The read-out sensitivity is approximately 6.75 (mu) V per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mV/s, equivalent to 3.3 nA/cm2. The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW.

Eid, Sayed I.; Dickinson, Alex G.; Inglis, Dave A.; Ackland, Bryan D.; Fossum, Eric R.

1995-04-01

109

LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)  

SciTech Connect

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

2000-01-01

110

Planarization of a CMOS die for an integrated metal MEMS  

NASA Astrophysics Data System (ADS)

This paper describes a planarization procedure to achieve a flat CMOS die surface for the integration of a MEMS metal mirror array. The CMOS die for our device is 4 mm × 4 mm and comes from a commercial foundry. The initial surface topography has 0.9 ?m bumps from the aluminum interconnect patterns that are used for addressing the individual micro mirror array elements. To overcome the tendency for tilt error in the planarization of the small CMOS die, our approach is to sputter a thick layer of silicon nitride (2.2 ?m) at low temperature and to surround the CMOS die with dummy pieces to define the polishing plane. The dummy pieces are first lapped down to the height of the CMOS die, and then all pieces are polished. This process reduces the 0.9 ?m height of the bumps to less than 25 nm.

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2003-01-01

111

Lab-on-CMOS integration of microfluidics and electrochemical sensors.  

PubMed

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J

2013-10-01

112

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors  

PubMed Central

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J.

2013-01-01

113

CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques.  

E-print Network

??We propose and verify the design of low-power, high-performance CMOS Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In low-cost CMOS semiconductor processes, SC… (more)

Song, Yu (1980 - )

2011-01-01

114

Delta Doping High Purity CCDs and CMOS for LSST  

NASA Technical Reports Server (NTRS)

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

115

An advanced, radiation hardened bulk CMOS/LSI technology  

NASA Technical Reports Server (NTRS)

An advanced, second generation, bulk, Si-gate CMOS process is described. This process is capable of producing LSI and VLSI parts that are latch-up free and hardened to total dose levels in excess of 2 x 10 to the 5th rad-Si for applications in space and weapons radiation environments. Two memories designed to use this process are also described. Both circuits are 4096-bit, static CMOS RAMs.

Schroeder, J. E.; Lichtel, R. L.; Gingerich, B. L.

1981-01-01

116

Simulation of SEU transients in CMOS ICs  

Microsoft Academic Search

An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used

N. Kaul; B. L. Bhuva; S. E. Kerns

1991-01-01

117

CMOS Compatible Nanoscale Nonvolatile Resistance Switching  

E-print Network

) inside the a-Si matrix at positive (negative) applied voltages.3-5 Such M/a-Si/M devices, however, need involves standard CMOS processes only, with the exception that the active device area is defined with electron-beam lithography to test the smallest devices. The cross-sectional image of a fabri- cated device

Lu, Wei

118

Statistical power analysis for nanoscale CMOS  

Microsoft Academic Search

With the scaling down of CMOS technology, process variations are becoming significant. Power consumption is a major constraint on IC yield. However, there has been little research on statistical power analysis compared with that on timing analysis. Here, both the static and dynamic power are considered. We characterize a cell library containing mean power. A standard deviation power library is

Yangang Wang; Michael Merrett; Mark Zwolinski

2010-01-01

119

All-CMOS night vision viewer with integrated microdisplay  

NASA Astrophysics Data System (ADS)

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

120

Yield Learning and Process Optimization on 65-nm CMOS Technology Accelerated by the Use of Short Flow Test Die  

Microsoft Academic Search

Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation and gate and premetal dielectric\\/contact loops of a 65-nm process technology in addition to the BEOL. These test chips

Jeffrey R. D. DeBord; Nagarajan Sridhar

2007-01-01

121

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

122

Monolithically integrated high-speed CMOS photonic transceivers  

Microsoft Academic Search

We demonstrate monolithically integrated 4times10 Gb\\/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb\\/s error-free, bidirectional transmission is demonstrated.

T. Pinguet; B. Analui; E. Balmater; D. Guckenberger; M. Harrison; R. Koumans; D. Kucharski; Y. Liang; G. Masini; A. Mekis; S. Mirsaidi; A. Narasimha; M. Peterson; D. Rines; V. Sadagopan; S. Sahni; T. J. Sleboda; D. Song; Y. Wang; B. Welch; J. Witzens; J. Yao; S. Abdalla; S. Gloeckner; P. De Dobbelaere

2008-01-01

123

Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process  

Microsoft Academic Search

This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.18 um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range

R. K. Pokharel; A. Tomar; H. Kanaya; K. Yoshida

2008-01-01

124

An On-Die CMOS Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations  

E-print Network

PMOS is used as a load with a static inverter performing the A/D conversion. This design suffers from PMOS load and the static inverter. It also requires multiple VBIAS generators when expanded to multi requirements are solved in [3] by replacing the PMOS load with a process- voltage (PV) insensitive IREF

Kim, Chris H.

125

Advanced microlens and color filter process technology for the high-efficiency CMOS and CCD image sensors  

NASA Astrophysics Data System (ADS)

New markets are emerging for digital electronic image device, especially in visual communications, PC camera, mobile/cell phone, security system, toys, vehicle image system and computer peripherals for document capture. To enable one-chip image system that image sensor is with a full digital interface, can make image capture devices in our daily lives. Adding a color filter to such image sensor in a pattern of mosaics pixel or wide stripes can make image more real and colorful. We can say 'color filter makes the life more colorful color filter is? Color filter means can filter image light source except the color with specific wavelength and transmittance that is same as color filter itself. Color filter process is coating and patterning green, red and blue (or cyan, magenta and yellow) mosaic resists onto matched pixel in image sensing array pixels. According to the signal caught from each pixel, we can figure out the environment image picture. Widely use of digital electronic camera and multimedia applications today makes the feature of color filter becoming bright. Although it has challenge but it is very worthy to develop the process of color filter. We provide the best service on shorter cycle time, excellent color quality, high and stable yield. The key issues of advanced color process have to be solved and implemented are planarization and micro-lens technology. Lost of key points of color filter process technology have to consider will also be described in this paper.

Fan, Yang-Tung; Peng, Chiou-Shian; Chu, Cheng-Yu

2000-12-01

126

First fully CMOS-integrated 3D Hall probe  

Microsoft Academic Search

We present the first fully CMOS-integrated 3D Hall probe. The microsystem is developed for precise magnetic field measurements in the range from mT up to tens of tesla in the frequency range from DC to 30 kHz and with a spatial resolution of about 150 ?m. The microsystem is realized in a conventional CMOS process without any additional processing step

P. Kejik; E. Schurig; F. Bergsma; R. S. Popovic

2005-01-01

127

CMOS magnetic sensor integrated circuit with sectorial MAGFET  

Microsoft Academic Search

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6?m digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling

Guo Qing; Zhu Dazhong; Yao Yunruo

2006-01-01

128

A CMOS Smart Thermal Sensor for Biomedical Application  

NASA Astrophysics Data System (ADS)

This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18?m CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180° phase difference input to SDM is also a novel design of this work. As a result, in the range of 0°C to 80°C or body temperature (37±5°C), the inaccuracy is less than ±0.1°C or ±0.05°C respectively with one-point calibration after packaging. The average power consumption is 268.4?W with 1.8V supply voltage.

Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

129

Capabilities of a new spatiotemporal CMOS imager for nanosecond low power pulse detection  

NASA Astrophysics Data System (ADS)

High speed cameras use the interesting performances of CMOS imagers which offer advantages in on-chip functionalities, system power reduction, cost and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, we present a new imager called FAMOSI 2 which implements an electronic shutter and analog accumulation capabilities inside the pixel. With this kind of pixel and the new architecture for controlling the integration, FAMOSI 2 can work in repetitive mode for low light power and in single shot mode for higher light power. This repetitive mode utilizes an analog accumulation to improve the sensitivity of the system with a standard N well/P sub photodiode. The prototype has been fabricated in the AMS 0.35 ?m CMOS process. The chip is composed of 64 columns per 64 rows of pixels. The pixels have a size of 20 ?m per 20 ?m and a fill factor of 47 %. Characterizations under static and uniform illumination in single shot mode have been done in order to evaluate the performances of the detector. The main noises levels have been evaluated and the experiments show that a conversion gain of 4.8 ?V/e - is obtained with a dynamic range of 1.2 V. Moreover, the charge transfer characterization in single shot mode has been realized. It permits to know which potential must be apply to the charge spill transistor to obtain the whole dynamic of the output with a maximal transfer gain, what is primordial to optimize the analog accumulation.

Morel, Frédéric; Zint, Chantal-Virginie; Uhring, Wilfried; Le Normand, Jean-Pierre

2006-04-01

130

Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits  

Microsoft Academic Search

This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high performance microelectromechanical systems solenoid inductors and metal-insulator-metal (MIM) capacitors by using a post CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of

Zhengzheng Wu; Lei Gu; Xinxin Li

2009-01-01

131

Micromachined thermally based CMOS microsensors  

Microsoft Academic Search

An integrated circuit (IC) approach to thermal microsensors is presented. The focus is on thermal sensors with on-chip bias and signal conditioning circuits made by industrial complementary metal-oxide-semiconductor (CMOS) IC technology in combination with post-CMOS micromachining or deposition techniques. CMOS materials and physical effects pertinent to thermal sensors are summarized together with basic structures used for microheaters, thermistors, thermocouples, thermal

HENRY BALTES; OLIVER PAUL; OLIVER BRAND

1998-01-01

132

CMOS serial link for fully duplexed data communication  

NASA Astrophysics Data System (ADS)

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

133

Integrated CMOS RF amplifier  

NASA Technical Reports Server (NTRS)

This paper reports an integrated 2.0 micron CMOS RF amplifier designed for amplification in the 420-450 MHz frequency band. Design techniques are shown for the test amplifier configuration. Problems of decreased amplifier bandwidth, gain element instability, and low Q values for the inductors were encountered. Techniques used to overcome these problems are discussed. Layouts of the various elements are described and a summary of the simulation results are included. Test circuits have been submitted to MOSIS for fabrication.

Charity, C.; Whitaker, S.; Purviance, J.; Canaris, M.

1990-01-01

134

Integration of a photodiode array and centroid processing on a single CMOS chip for a real-time shack-Hartmann wavefront sensor  

Microsoft Academic Search

A real-time VLSI optical centroid processor has been developed as part of a larger Shack-Hartmann wavefront sensor system for applications in adaptive optics. The implementation of the optical centroid detection system was demonstrated successfully using a hardware emulation system. Subsequently, the design has been implemented as a CMOS single-chip solution. This has advantages in terms of speed, power consumption, system

Boon Hean Pui; Barrie Hayes-Gill; Matthew Clark; Mike G. Somekh; Chung Wah See; Steve Morgan; Alan Ng

2004-01-01

135

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-?m to 90-nm generation  

Microsoft Academic Search

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 ?m, 0.18 ?m, 0.13 ?m, and 90 nm showed an increase of 8% per generation.

P. Hazucha; T. Karnik; J. Maiz; S. Walstra; B. Bloechel; J. Tschanz; G. Dermer; S. Hareland; P. Armstrong; S. Borkar

2003-01-01

136

BiCMOS OEIC with enhanced sensitivity for DVD systems  

Microsoft Academic Search

A new BiCMOS OEIC with enhanced sensitivity for advanced optical storage systems is presented. The photodiode and the amplifier are monolithically integrated on the same substrate in an industrial 0:8 µm BiCMOS process. The OEIC shows a sensitivity of 43.3mV\\/µW in combination with a -3 dB-bandwidth of 60.2 MHz.

K. Kieschnick; H. Zimmermann; P. Seegebrecht

2001-01-01

137

Precision interface electronics for a CMOS smart temperature sensor  

Microsoft Academic Search

This paper describes the interface electronics of a CMOS smart temperature sensor that is accurate to plusmn0.1degC over the full military temperature range. The sensor is fabricated in a standard CMOS process. Substrate bipolar transistors are used as temperature-sensitive devices. Precision interface electronics are used to make the most of their temperature characteristics. While the sensor is trimmed at one

Michiel A. P. Pertijs; J. H. Huijsing

2005-01-01

138

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

139

IR CMOS: infrared enhanced silicon imaging  

NASA Astrophysics Data System (ADS)

SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

2013-06-01

140

Silicon Avalanche Photodetectors Fabricated With Standard CMOS/BiCMOS Technology  

E-print Network

Silicon Avalanche Photodetectors Fabricated With Standard CMOS/BiCMOS Technology Myung-Jae Lee Photonics for High-Speed Interconnects .....1 1-2. Silicon Photodetectors in Standard CMOS/BiCMOS Technology/BiCMOS Technology for Photodetectors .......................................................7 2-2. Silicon

Choi, Woo-Young

141

An 0.8µm CMOS technology for high performance logic applications  

Microsoft Academic Search

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

Richard A. Chapman; Roger A. Haken; David A. Bell; C. C. Wei; R. H. Havemann; T. E. Tang; T. C. Holloway; R. J. Gale

1987-01-01

142

A CMOS clock and data recovery circuit for intraocular microsystems.  

PubMed

This paper presents the implementation of a clock and data recovery circuit (CDR) for intraocular microsystems. The CDR was designed to minimize chip area and power consumption and to recover the clock and data signals from the incoming data stream. Since the CDR has been designed without any external components it is well suited for being integrated in an intraocular microsystem. Simulation results show that this CDR works with power dissipation of less than 2.4 mW with a single 3.3 V power supply. The simulations are based on a 0.6 micron n-well CMOS single-polysilicon, three-metal technology. PMID:12451805

Prämassing, F; Püttjer, D; Buss, R; Jäger, D

2002-01-01

143

Modeling and simulation of TDI CMOS image sensors  

NASA Astrophysics Data System (ADS)

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

2013-09-01

144

Surface enhanced biodetection on a CMOS biosensor chip  

NASA Astrophysics Data System (ADS)

We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-? and IFN-?). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

2012-03-01

145

Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm  

E-print Network

This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

Wladyslaw Szczesniak

2008-01-07

146

Scaling trends of single-photon avalanche diode arrays in nanometer CMOS technology  

NASA Astrophysics Data System (ADS)

A family of scaleable single photon avalanche diode (SPAD) structures in 130nm and 90nm CMOS is presented. Performance trends such as dark count rate (DCR), jitter and breakdown voltage are studied versus active diameter for devices ranging from 32?m down to 2?m. To address pixel pitch we introduce a shared buried n-well approach allowing compact arrays containing both NMOS-transistor readout circuitry and SPAD devices. A pixel pitch of 5?m has been achieved in 90nm CMOS technology, offering the potential for future megapixel single photon image sensors.

Richardson, Justin A.; Webster, Eric A. G.; Grant, Lindsay A.; Henderson, Robert K.

2011-05-01

147

Regenerative switching CMOS system  

DOEpatents

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Welch, J.D.

1998-06-02

148

Regenerative switching CMOS system  

DOEpatents

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

1998-01-01

149

CMOS sensor for RSI applications  

NASA Astrophysics Data System (ADS)

Three CMOS sensors were developed for remote sensing instrument (RSI) applications. First device is linear CMOS Sensor for Terrain Mapping Camera (TMC). This device has 4000 elements, 7 ?m x 7 ?m of pixel size. Second device is area CMOS Sensor for Hyper Spectral Imager (HySI). The device has 512 x 256 elements and 50 ?m x 50 ?m of pixel size. Third device is multi band sensor for Remote Sensing Instrument (RSI). This device integrates five linear CMOS sensor into a single monolithic chip to form a Multiple System On Chip (MSOC) IC. The multi band sensor consists of one panchromatic (PAN) and four multi - spectral (MS) bands. The PAN is 12000 elements, 10 ?m x 10 ?m with integration time of 297 ?s +/- 5%. Each MS band is 6000 elements, 20 ?m x 20 ?m with integration time of 594 us ?s +/- 5%. Both linear and area CMOS sensor were designed and developed for Chandrayaan-1 project. The Chandrayaan-1 satellite was launched to the moon on October 22, 2008. The moon orbit height is 100 km and 20 km of swath size. The multi band sensor was designed for earth orbit. The earth orbit height is about 720 km and 24 km of swath. The low weight, low power consumption and high radiation tolerance camera requirement only can be done by CMOS Sensor technology. The detail device structure and performance of three CMOS sensors will present.

Wang, Weng Lyang; Lin, Shengmin

2012-11-01

150

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Castro, Xitzel Sanchez; Winter, Marc

2014-01-01

151

Design and Fabrication of Vertically-Integrated CMOS Image Sensors  

PubMed Central

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-01-01

152

Low-power 2-D fully integrated CMOS fluxgate magnetometer  

Microsoft Academic Search

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works

Predrag M. Drljaca; Pavel Kejik; Franck Vincent; Dominique Piguet; Radivoje S. Popovic

2005-01-01

153

Smart-pixel cellular neural networks in analog current-mode CMOS technology  

Microsoft Academic Search

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT's connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing

S. Espejo; A. Rodriguez-Vazquez; R. Dominguez-Castro; J. L. Huertas; E. Sanchez-Sinencio

1994-01-01

154

CMOS tunable bandpass RF filters utilizing coupled on-chip inductors  

Microsoft Academic Search

A novel scheme for tunable integrated CMOS bandpass RF filters using magnetically coupled on-chip inductors is proposed. A filter designed in a 0.6 ?m CMOS process exhibits a blocking dynamic range of over 70 dB, when tuned at a center frequency in the range of 900-1000 MHz and a filter Q of 25

Sotiris Bantas; Yannis Papananos; Yorgos Koutsoyannopoulos

1999-01-01

155

Impact of CMOS technology scaling on the atmospheric neutron soft error rate  

Microsoft Academic Search

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size LG. A different

Peter Hazucha; Christer Svensson

2000-01-01

156

A high speed camera system based on an image sensor in standard CMOS technology  

Microsoft Academic Search

In this contribution a novel camera system developed for high speed imaging will be presented. The core of the system consists of a CMOS image sensor manufactured in a 1 ?m standard CMOS process. The special merit of the image sensor is the capability to acquire more than 1000 frames\\/s using a global electronic shutter in each sensor cell. The

Nenad Stevanovic; Matthias Hillebrand; Bedrich J. Hosticka; Uri Iurgel; Andreas Teuner

1999-01-01

157

A CMOS Humidity Sensor for Passive RFID Sensing Applications  

PubMed Central

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

158

25 nm CMOS design considerations  

Microsoft Academic Search

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues,

Y. Taur; Clement H. Wann; David J. Frank

1998-01-01

159

PMOSFET-Type Photodetector with High Responsivity for CMOS Image Sensor  

Microsoft Academic Search

In this paper, a new photodetector using a PMOSFET-type photodetector with a transfer gate has been designed and fabricated using a 0.35 mum standard CMOS technology. The photodetector is composed of a floating gate that is tied to an n-well and a transfer gate. The transfer gate controls the photocurrent flow by controlling the barrier for holes in the PMOSFET-type

Sang-Ho Seo; Kyung-Do Kim; Jang-Kyoo Shin; Youze Cho; Hong-Bae Park; Pyung Choi

2006-01-01

160

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

NASA Astrophysics Data System (ADS)

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

Zhang, Weiquan

2000-12-01

161

A perspective on CMOS technology trends  

Microsoft Academic Search

Integrated circuit technology continues to evolve at a rapid pace, driven by the requirements of new applications for electronics of higher performance at ever lower cost. The attributes of CMOS technology in a ULSI environment are an ideal match to these requirements; thus CMOS is becoming the ubiquitous integrated circuit technology. The main feature of CMOS is the existence of

W. C. Holton; R. K. Cavin

1986-01-01

162

Color recognition sensor in standard CMOS technology  

NASA Astrophysics Data System (ADS)

Two integrated color detectors are presented as a solution for low cost color sensing applications. The color detection is based on lateral carrier diffusion and wavelength-dependent absorption-depth. The proposed detectors are implemented in a standard 130 nm CMOS technology without process modification or color filters. Three independent output signals are obtained with spectral responsivities optimized to short, middle and long wavelengths. R, G, B or X, Y, Z standard color representation can be realized by a linear transformation of the output signals.

Batistell, Graciele; Zhang, Vincent Chi; Sturm, Johannes

2014-12-01

163

CMOS digital intra-oral sensor for x-ray radiography  

NASA Astrophysics Data System (ADS)

In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

2011-03-01

164

Impact of technology trends on SEU in CMOS SRAMs  

SciTech Connect

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. The authors study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation to the development of a 0.5-{micro}m radiation-hardened CMOS SRAM is presented.

Dodd, P.E.; Sexton, F.W.; Hash, G.L.; Shaneyfelt, M.R.; Draper, B.L.; Farino, A.J.; Flores, R.S. [Sandia National Labs., Albuquerque, NM (United States)] [Sandia National Labs., Albuquerque, NM (United States)

1996-12-01

165

Performance and Limitations of 65 nm CMOS for  

E-print Network

· High-volume, low cost consumer applications ­ Current: WLAN, Bluetooth, Cell-phone PA driver, Wi Vdd impact on reliability ­ Use I/O devices (if available) process complexity (cost) ­ Increase · Devices designed and fabricated in IBM's 65 nm CMOS WG,TOT = NC x NF x WG,F NC = # of cells NF

del Alamo, Jesús A.

166

Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.  

PubMed

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

167

Evaluation of Transistor Densities for Submicronic CMOS Technologies  

Microsoft Academic Search

The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given technology at the cell and circuit level, from the design rules. This

F. Moraes; L. Torres; M. Robert; D. Auvergne

168

Overcoming scaling concerns in a radiation-hardening CMOS technology  

SciTech Connect

Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.

Maimon, J.; Haddad, N.

1999-12-01

169

Impact of technology trends on SEU in CMOS SRAMs  

Microsoft Academic Search

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design

P. E. Dodd; F. W. Sexton; G. L. Hash; M. R. Shaneyfelt; B. L. Draper; A. J. Farino; R. S. Flores

1996-01-01

170

Design of CMOS chopper amplifiers for thermal sensor interfacing  

Microsoft Academic Search

An analytical approach to the design of compact CMOS chopper amplifiers for integrated thermoelectric sensors is presented. The impact of the high resistance and low signal bandwidth of thermopile sources on the design is illustrated. The proposed approach, regarding the precision vs noise tradeoff, is applied to the design of a practical prototype, using a commercial process. Accurate electrical simulations

Michele Dei; Paolo Bruschi; Massimo Piotto

2008-01-01

171

Helicopter rotors pyramid angle measurement based on CMOS technology  

Microsoft Academic Search

Based on computer image processing, give a new method on helicopter rotors pyramid angle by CMOS -Camera. give a overall design of the system, compare image results with different camera's location and analyze the system's qualitative error. design a synchronized system by external synchronized pulse in order to catch the accuracy image and calculate the blade's height differences by filter

Jiang Mai; Cai Cheng-Tao; Zhu Qi-Dan; Shi Zhen

2009-01-01

172

a Quantum Fluctuation Operator for Deep N-Well Mosfet Flicker Noise Modeling  

NASA Astrophysics Data System (ADS)

In this work, a quantum fluctuation operator (QFO) has been formulated to achieve realistic flicker noise simulations which are currently not available on BSIM platforms. The responsibility of the operator is to create a closer representation of flicker noise in deep n-well (DNW) MOSFETs based on probabilistic densities. It is well known that flicker (or 1/f) noise is generated by a combination of number and mobility fluctuations. The application of Heisenberg's Uncertainty Principle (HUP) can determine the transitional probabilities that influence the extent of these fluctuations. These are the elementary issues that are not readily addressed in Berkeley's model. QFO modeling approximates conductivity fluctuation along the n-channel by normalizing the k-space time-dependent energies of electrons in a finite double-well which represents the DNW and the p-type material.

Png, Ethan

2014-04-01

173

A HIGH RESOLUTION, STICTIONLESS, CMOS COMPATIBLE SOI ACCELEROMETER WITH A LOW NOISE, LOW POWER, 0.25M CMOS INTERFACE  

E-print Network

0.25µm CMOS. The interface IC consumes 3mW of power. II. ACCELEROMETER DESIGN The simplified with no perforations results in a smaller footprint for the sensor and an improved mechanical design. The fabricated-release low temperature process comprising of three plasma etching steps. The fabricated devices were

Ayazi, Farrokh

174

RF-CMOS performance trends  

Microsoft Academic Search

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance

Pierre H. Woerlee; Mathijs J. Knitel; Ronald van Langevelde; Dirk B. M. Klaassen; Luuk F. Tiemeijer; Andries J. Scholten; A. T. A. Zegers-van Duijnhoven

2001-01-01

175

Anodic Ta 2O 5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication  

NASA Astrophysics Data System (ADS)

This paper reports a CMOS compatible fabrication procedure that enables electrowetting-on-dielectric (EWOD) technology to be post-processed on foundry CMOS technology. With driving voltages less than 15 V it is believed to be the lowest reported driving voltage for any material system compatible with post-processing on completed integrated circuits wafers. The process architecture uses anodically grown tantalum pentoxide as a pinhole free high dielectric constant insulator with an overlying 16 nm layer of Teflon-AF ®, which provides the hydrophobic surface for droplets manipulation. This stack provides a very robust dielectric, which maintains a sufficiently high capacitance per unit area for effective operation at a reduced voltage (15 V) which is more compatible with standard CMOS technology. The paper demonstrates that the sputtered tantalum layer used for the electrodes and the formation of the insulating dielectric can readily be integrated with both aluminium and copper interconnect used in foundry CMOS.

Li, Y.; Parkes, W.; Haworth, L. I.; Stokes, A. A.; Muir, K. R.; Li, P.; Collin, A. J.; Hutcheon, N. G.; Henderson, R.; Rae, B.; Walton, A. J.

2008-09-01

176

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio  

Microsoft Academic Search

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

2007-01-01

177

Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 ?m  

Microsoft Academic Search

During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 ?m-generation to 0.13 ?m-generation technology

D. Nayak; M.-Y. Hao; R. Hijab

1997-01-01

178

Optical and noise performance of CMOS solid-state photomultipliers  

NASA Astrophysics Data System (ADS)

Solid-state photomultipliers (SSPM) are photodetectors composed of avalanche photodiode pixel arrays operating in Geiger mode (biased above diode breakdown voltage). They are built using CMOS technology and can be used in a variety of applications in high energy and nuclear physics, medical imaging and homeland security related areas. The high gain and low cost associated with the SSPM makes it an attractive alternative to existing photodetectors such as the photomultiplier tube (PMT). The capability of integrating CMOS on-chip readout circuitry on the same substrate as the SSPM also provides a compact and low-power-consumption solution to photodetector applications with stringent area and power requirements. The optical performance of the SSPM, specifically the detection and quantum efficiencies, can depend on the geometry and the doping profile associated with each photodiode pixel. The noise associated with the SSPM not only includes dark noise from each pixel, but also consists of excess noise terms due to after pulsing and inter-pixel cross talk. The magnitude of the excess noise terms can depend on biasing conditions, temperature, as well as pixel and inter-pixel dimensions. We present the optical and noise performance of SSPMs fabricated in a conventional CMOS process, and demonstrate the dependence of the SSPM performance on pixel/inter-pixel geometry, doping profile, temperature, as well as bias conditions. The continuing development of CMOS SSPM technology demonstrated here shows that low cost and high performance solid state photodetectors are viable solutions for many existing and future optical detection applications.

Chen, Xiao Jie; Johnson, Erik B.; Staples, Christopher J.; Chapman, Eric; Alberghini, Guy; Christian, James F.

2010-08-01

179

Design of clock recovery circuits for optical clocking in DSM CMOS  

NASA Astrophysics Data System (ADS)

CMOS technology scaling especially in the sub-100 nm regime has made signaling in long global a challenge, resulting in a need for an improved interconnect technology. Optical signalling is a promising alternative to existing global interconnects and alleviates interconnect bottle-neck. This paper presents a design of a CMOS trans-impedance amplifier (TIA) that is intended for a truly CMOS compatible on-chip optical clock distribution system. This TIA employs replica biasing technique to achieve stability while maximizing its bandwidth and gain. The design was implemented in a 0.35?m CMOS process and is currently under probe testing. The simulation results show that the design achieved a bandwidth of 1GHz and gain of 128dB-?. Extensive Monte-Carlo simulations indicate the superior characteristics of stability under a variety of process and environmental variations.

Thangaraj, Charles; Stephenson, Kevin; Chen, Tom; Lear, Kevin; Raza, Abdul Matheen

2007-05-01

180

High Resolution CMOS Current Comparators  

Microsoft Academic Search

A 2¿m CMOS current comparator prototype is presented with an input current comparison range of 140dB and virtual zero offset(?10pA). The circuit uses capacitive sensing for high resolution and nonlinear feedback to achieve small input voltage variations in the complete input current range. Operation speed for low current is abot two orders of magnitude larger than for conventional circuits. Simplified

R. Dominguez-Castro; A. Rodriguez-Vazquez; F. Medeiro; J. L. Huertas

1992-01-01

181

New package for CMOS sensors  

Microsoft Academic Search

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low

Jean-Luc Diot; Kum Weng Loo; Jean-Pierre Moscicki; Hun Shen Ng; Tong Yan Tee; Jerome Teysseyre; Daniel Yap

2004-01-01

182

Single core fully integrated CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

A new fully integrated 2D micro-fluxgate magnetometer is presented. This magnetometer is integrated in a standard CMOS process and uses a ferromagnetic core integrated on the chip by a photolithographic post-process compatible with the integrated circuit technology. The cross-shaped ferromagnetic core is placed diagonally above four excitation coils, two for each measurement axis. A novel electronic signal extraction technique is

Predrag M. Drlja?a; Pavel Kejik; Franck Vincent; Dominique Piguet; François Gueissaz; Radivoje S. Popovi?

2004-01-01

183

A high performance CMOS LNA for system-on-chip GPS  

Microsoft Academic Search

A 1.6 GHz CMOS single-ended low noise amplifier (LNA) optimized for integration and use in Global Positioning System (GPS) applications is presented. The LNA is implemented in a 0.13 mum standard CMOS process with on-chip inductors. The LNA achieves a noise figure of 1.35 dB, a power gain of 16.7 dB and a 1 dB compression point of -14 dBm

Bo Bokinge; Wenche Einerman; Anders Emericks; Christian Grewing; Ola Pettersson; Detlev Theil; Stefan van Waasen

2006-01-01

184

Fully integrated CMOS GPS receiver for system-on-chip solutions  

Microsoft Academic Search

A CMOS receiver for the Global Positioning System (GPS) is presented. It is designed in a 0.13mum standard CMOS process and is fully integrated for the needs of a system-on-chip (SoC) solution for GPS and assisted GPS (A-GPS). It provides the needed frequency conversion, gain and filtering for GPS signals without any other external components than those required for matching

Christian Grewing; Bo Bokinge; Wenche Einerman; Anders Emericks; Detlev Theil; Stefan van Waasen

2006-01-01

185

An efficient low voltage, high frequency silicon CMOS light emitting device and electro-optical interface  

Microsoft Academic Search

A silicon light emitting device was designed and realized utilizing a standard 2-?m industrial CMOS technology design and processing procedure. The device and its associated driving circuitry were integrated in a CMOS integrated circuit and can interface with a multimode optical fiber. The device delivers 8 nW of optical power (450-850 nm wavelength) per 20-?m diameter of chip area at

L. W. Snyman; M. du Plessis; E. Seevinck; H. Aharoni

1999-01-01

186

Technologies for (sub-) 45nm Analog\\/RF CMOS - Circuit Design Opportunities and Challenges  

Microsoft Academic Search

The new process module and device architecture options emerging for (sub-) 45nm CMOS, lead to both opportunities and challenges for analog\\/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for

S. Decoutere; P. Wambacq; V. Subramanian; J. Borremans; A. Mercha

2006-01-01

187

An acquisition system for CMOS imagers with a genuine 10 Gbit\\/s bandwidth  

Microsoft Academic Search

This paper presents a high data throughput acquisition system for pixel detector readout such as CMOS imagers. This CMOS acquisition board offers a genuine 10 Gbit\\/s bandwidth to the workstation and can provide an on-line and continuous high frame rate imaging capability. On-line processing can be implemented either on the Data Acquisition Board or on the multi-cores workstation depending on

C. Guérin; J. Mahroug; W. Tromeur; J. Houles; P. Calabria; R. Barbier

188

A wide-band CMOS read amplifier for magnetic data storage systems  

Microsoft Academic Search

Circuit techniques for a CMOS amplifier suitable for read waveform signal processing in high-speed disk drives are described. A 30-MHz low-noise preamplifier with a gain of 100 was designed in 3-?m CMOS, capable of being driven by an inductive source, and producing an equivalent input noise voltage spectral density of 2 nV\\/?Hz. This, with other recent developments, makes it possible

Tzu-Wang Pan; Asad A. Abidi

1992-01-01

189

An extremely low power 2 GHz CMOS LC VCO for wireless communication applications  

Microsoft Academic Search

An extremely low power low phase noise CMOS LC voltage controlled oscillator (VCO) has been fully integrated in a commercial 0.18 mum CMOS process. To achieve low power and low phase noise, a complementary NMOS and PMOS cross-coupled differential LC structure is used. The LC tank is composed of octagonal-shaped inductors with 2 mum Al metal and standard NMOS varactors.

Han-il Lee; Tae-young Choi; Saeed Mohammadi; L. P. B. Katehi

2005-01-01

190

High performance and low power transistors integrated in 65nm bulk CMOS technology  

Microsoft Academic Search

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 %

Z. Luo; A. Steegen; M. Eller; R. Mann; C. Baiocco; P. Nguyen; L. Kim; M. Hoinkis; V. Ku; V. Klee; F. Jamin; P. Wrschka; P. Shafer; W. Lin; S. Fang; A. Ajmera; W. Tan; R. Mo; J. Lian; D. Vietzke; C. Coppock; A. Vayshenker; T. Hook; V. Chan; K. Kim; A. Cowley; S. Kim; E. Kaltalioglu; B. Zhang; S. Marokkey; Y. Lin; K. Lee; H. Zhu; M. Weybright; R. Rengarajan; J. Ku; T. Schiml; J. Sudijono; I. Yang; C. Wann

2004-01-01

191

Towards a hybrid CMOS-imager with organic semiconductors as photoactive layer  

Microsoft Academic Search

Hybrid CMOS-imagers with vertically integrated organic semiconductors are proposed to enhance the currently small fill factor of conventional CMOS-pixels. Organic photodetectors (OPDs) are low-cost and easy processable and their performance begins to match the one of silicon based devices. Therefore, they are advantageous compared to other hybrid concepts like costly microlenses or thin-film-on-ASIC. In addition, the spectral tunability of organic

Daniela Baierl; Morten Schmidt; Giuseppe Scarpa; Paolo Lugli; Lucio Pancheri; David Stoppa; Gian-Franco Dalla Betta

2011-01-01

192

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources  

NASA Astrophysics Data System (ADS)

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

193

Dark current study for CMOS fully integrated-PIN-photodiodes  

NASA Astrophysics Data System (ADS)

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices and pulse oximeters for medical applications. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process allows device miniaturization in addition to enhance its properties lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The dark current is studied, analyzed and measured for two different starting materials and for different geometries. A model previously proposed is reviewed and compared with experimental data.

Teva, Jordi; Jessenig, Stefan; Jonak-Auer, Ingrid; Schrank, Franz; Wachmann, Ewald

2011-05-01

194

Smart CMOS image sensor for lightning detection and imaging.  

PubMed

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

195

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass  

PubMed Central

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

196

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.  

PubMed

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

197

Figure 1: Schematic of a combined adaptive body bias and adaptive supply voltage adaptation scheme Process and Reliability Sensors for Nanoscale CMOS  

E-print Network

process variation effects. The first case study, demonstrated in silicon, shows how beat frequencies can along the spatial and temporal axes, are showing a markedly increasing trend. The net resultFigure 1: Schematic of a combined adaptive body bias and adaptive supply voltage adaptation scheme

Sapatnekar, Sachin

198

Variable gain CMOS potentiostat for dissolved oxygen sensor  

Microsoft Academic Search

This paper presents a variable gain potetiostat designed for the electrochemical control of Dissolved Oxygen (DO) sensors. The design is targeted for implementation using MIMOS 0.35 um CMOS process technology at 3.3V. The potentiostat amplifier for dissolved oxygen utilizes three electrodes (working, reference and counter) which work together to form the electrochemical reaction. There are several types of DO sensor

Mei Yee Ng; Yuzman Yusoff

2010-01-01

199

Active devices under CMOS I\\/O pads  

Microsoft Academic Search

Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I\\/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (Vt2, It2) of ESD protection devices under various metal level stack structures, shows

Kuo-Yu Chou; Ming-Jer Chen; Chi-Wen Liu

2002-01-01

200

A CMOS microcoil-associated preamplifier for NMR spectroscopy  

Microsoft Academic Search

For improving sensitivity of nuclear magnetic resonance (NMR) measurements, an in-field preamplifier in a low-cost CMOS process is presented. It is based on a second-generation positive current conveyor (CCII+), with an impedance-matching output stage. The circuit has been designed with optimization of key performances, such as bandwidth, noise, and offset voltage. There have also been precautions taken against potential effect

Tewfik Cherifi; Nacer Abouchi; Guo-Neng Lu; Latifa Bouchet-Fakri; Laurent Quiquerez; B. Sorli; Jean-François Chateaux; M. Pitaval; P. Morin

2005-01-01

201

A low–voltage CMOS transconductor for very high frequencies  

Microsoft Academic Search

This paper presents a pseudo-differential continuous time transconductor for applications in low-voltage systems over the very high frequency range. By using a 0.8 µm CMOS process, the transconductor consumes less than 1.5 mW from a 2.7 V supply. A prototype third-order 60 MHz elliptic lowpass ladder filter with a transmission zero at 200 MHz confirms the feasibility of the proposed

S. Celma; J. Sabadell; C. Aldea; P. A. Martinez

1999-01-01

202

Below 2.0mum CMOS imager technology shrinks  

Microsoft Academic Search

A quick calculation and accurate estimation algorithm with systematic analysis of optical view is crucial in developing sub 2.0mum imager since as the pixel size scales down below 2.0mum, saturation and sensitivity are reduced more than those expected by nominal scaling factor of CMOS process. In this paper, an unconventional treatment by diffraction focal shift theory is proposed for explaining

H. W. Lee; C. H. Wu

2008-01-01

203

CMOS-compatible AlN piezoelectric micromachined ultrasonic transducers  

Microsoft Academic Search

Piezoelectric micromachined ultrasonic transducers for air-coupled ultrasound applications were fabricated using aluminum nitride (AlN) as the active piezoelectric layer. The AlN is deposited via a low-temperature sputtering process that is compatible with deposition on metalized CMOS wafers. An analytical model describing the electromechanical response is presented and compared with experimental measurements. The membrane deflection was measured to be 210 nm

Stefon Shelton; Mei-Lin Chan; David Horsley; Bernhard Boser; Igor Izyumin; Richard Przybyla; Tim Frey; Michael Judy; K. Nunan; F. Sammoura; Ken Yang

2009-01-01

204

252 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 A CMOS Subbandgap Reference Circuit With 1-V Power Supply Voltage  

E-print Network

252 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 A CMOS Subbandgap Reference management circuits [1]. As process technologies go into the deep-submicron eras and the demand for battery) as well as design margin. To keep pace with supply voltage requirements of a state-of-the-art CMOS process

Ayers, Joseph

205

Accelerated life testing effects on CMOS microcircuit characteristics  

NASA Technical Reports Server (NTRS)

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

1977-01-01

206

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT  

NASA Astrophysics Data System (ADS)

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

2013-12-01

207

High-resolution imaging of latch-up sites in CMOS IC  

E-print Network

. . LATCH-UP IN CMOS A. The Problem B. Lumped Circuit Model 1. Assumptions 2. The Model C. Conclusion 5 6 6 7 11 IV TRIGGERING MECHANISMS A. Output/Input Node Overshoot/Undershoot B. Avalanching Well/Substrate Junction . C. Punchthrough 1.... Punchthrough from N-well to External N-type Diffusion 2. Punchthrough from Substrate to Internal P-type Diffusion D. Parasitic Field Devices E. Radiation and Photocurrents . F. Source/Drain Avalanching Junctions G. Conclusion . AVOIDING LATCH-UP 13 14...

Shah, Mayank

2012-06-07

208

Diffuse reflectance measurements using lensless CMOS imaging chip  

NASA Astrophysics Data System (ADS)

To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 ?m thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

2014-10-01

209

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

210

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

PubMed Central

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

2010-01-01

211

Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors  

Microsoft Academic Search

A scheme for low-voltage CMOS op-amp operation with rail-to-rail input and output signal swing and constant gm is presented. Single-ended and fully differential versions are discussed. The scheme is based on the use of multiple-input floating-gate transistors and allows direct implementation of linear weighted addition of continuous-time signals. Simulations are presented that verify the scheme operating with a 1.2-V single

J. Ramirez-Angulo; R. G. Carvajal; J. Tombs; A. Torralba

2001-01-01

212

Integrated Microphone with CMOS Circuits on a Single Chip  

NASA Astrophysics Data System (ADS)

A miniature diaphragm microphone having sensitivity to acoustic signals at the level of conversational speech has successfully been integrated with CMOS circuits on a single chip. The microphone is built on 1.4 ?m thick LPCVD silicon nitride diaphragm (2 x 2 mm^2 in size) with electrodes and ZnO piezoelectric film to transduce mechanical deformation into electrical charge. The CMOS amplifier put next to the microphone on a single chip has a gain of 491, flat in audio frequency range with 3-dB frequency being 18 kHz. The total number of transistors integrated in an amplifier is more than 300. The amplified sensitivity of the integrated microphone with a gain of 491 is 1.5 mV/mu bar when excited by sound waves at 1 kHz with the sensitivity variation from 100 Hz to 20 kHz being approximately 9 dB. The integrated microphone has been fabricated through an interactive joint process between a commercial CMOS foundry and a university lab. It is the first to demonstrate an integration of a microphone with CMOS circuits on a single chip. Theory of the integrated microphone has been developed through combining mechanics, piezoelectricity and circuit theory. Also developed are theoretical optimizations for sensitivity-bandwidth product and signal-to-noise ratio. A new processing technique to align features on the front side of a wafer to those on its backside has been developed for bulk micromachining. A tiny (30 mum-square and 1.6 ?m -thick) diaphragm serves as an alignment pattern. At the same time that the alignment diaphragm is made, much thicker, large-area diaphragms can be partially etched using "mesh" masking patterns in these area. The mesh-masking technique exploits the etch-rate differences between (100) and (111) planes to control the depths reached by etch pits in selected areas. The large, partially etched diaphragms (2 to 3 mm squares roughly 100 ?m thick) are sufficiently robust to survive subsequent IC-processing steps in a silicon-foundry environment. The thin alignment diaphragm can be processed through these steps because of its very small area. The partially etched diaphragms can be reduced to useful thicknesses in a final etch step after the circuits have been fabricated. This technique was successfully employed to fabricate microphones and on-chip CMOS circuits.

Kim, Eun Sok

1990-01-01

213

Study for cross contamination between CMOS image sensor and IC product  

Microsoft Academic Search

In the authors' fab, CIS (CMOS image sensor) and IC products are in mass production. However, CIS products have an extra color filter (CF) process after traditional IC processing, and color filter (CF) processes are composed of multi-color photoresist layers. The color photoresist contains many metal impurities. Based on experimental data, these metal impurities influence the gate oxide quality of

Chih-Hsing Chen; Hung-Jen Tsai; Kwo-Shu Huang; Hsien-Tsong Liu

2001-01-01

214

A CMOS-compatible compact display  

E-print Network

Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

Chen, Andrew R. (Andrew Raymond)

2005-01-01

215

CMOS \\/ CMOL architectures for spiking cortical column  

Microsoft Academic Search

We present a spiking cortical column model based on neural associative memory, and demonstrate architectures for emulating the cortical column model with nanogrid molecular circuitry. We investigate a number of options for cost-effective hardware with digital CMOS and mixed-signal CMOL, a hybrid CMOS\\/nanogrid technology. We also give an example of a dynamic learning algorithm that is a suitable match to

Changjian Gao; Mazad S. Zaveri; Dan W. Hammerstrom

2008-01-01

216

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

217

CMOS imager technology shrinks and image performance  

Microsoft Academic Search

In this paper, we present a performance summary of CMOS imager pixels from 5.2 ?m to 4.2 ?m using 0.18 ?m imager design rules, then to 3.2 ?m using 0.15 ?m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based

H. Rhodes; G. Agranov; C. Hong; U. Boettiger; R. Mauritzson; J. Ladd; I. Karasev; J. McKee; E. Jenkins; W. Quinlin; I. Patrick; J. Li; X. Fan; R. Panicacci; S. Smith; C. Mouli; J. Bruce

2004-01-01

218

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

NASA Astrophysics Data System (ADS)

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Davidson, Bradley Darren

219

Deposition of titanium dioxide nanoparticles on the membrane of a CMOS-MEMS resonator  

NASA Astrophysics Data System (ADS)

A CMOS-MEMS resonator is optimized as a highly sensitive gas sensor. The principle of detection is based on change in resonant frequency of the resonator due to adsorption/absorption of trace gases onto the active material on the resonator membrane. The resonator was successfully fabricated using 0.35 ?m CMOS technology and post-CMOS micromachining process. The post-CMOS process is used to etch the silicon substrate and silicon oxide to release the suspended structures of the devices. Preliminary trials of nanocrystalline Titania paste (TiO2) was screen-printed on three aluminum plates of sizes 2mm × 2 mm. One of the samples was analysed as prepared while the other two samples were sintered at 300°C and 550°C, respectively. Physical observation indicated a change of the color for heated samples as compared to the unheated one. EDX results indicates a carbon (C) peak with average weight % of 18.816 in the as prepared sample and absence of the peaks for the samples sintered at 300°C and 550°C. EDX results also show that the TiO2 used consists of a uniform distribution of spherical shaped nanoparticles with a diameter of about 13.49 to 48.42 nm. Finally, the Titania paste was successfully deposit on the membrane of the CMOS-MEMS resonator for use as the gas sensitive membrane of the sensor.

Ahmed, A. Y.; Dennis, J. O.; Khir, M. H. Md; Saad, M. N. Mohamad

2014-10-01

220

A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking  

NASA Astrophysics Data System (ADS)

With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 ?m CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

Degerli, Y.; Guilloux, F.; Orsini, F.

2014-05-01

221

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity epitaxial layers leads to the better radiation hardness and allows the implementation of accelerated readout circuits. The TowerJazz $0.18 \\mu m$ CMOS process being one of the most relevant examples recently became of interest for several future detector projects. The most imminent of these project is an upgrade of the Inner Tracking System (ITS) of the ALICE detector at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems.

Serhiy Senyukov; Jerome Baudot; Auguste Besson; Giles Claus; Loic Cousin; Wojciech Dulinski; Mathieu Goffe; Boris Hippolyte; Robert Maria; Levente Molnar; Xitzel Sanchez Castro; Marc Winter

2014-02-10

222

High-performance integrated inductor and effective crosstalk isolation using post-CMOS selective grown porous silicon (SGPS) technique for RFIC applications  

NASA Astrophysics Data System (ADS)

In this paper, a post-CMOS selective grown porous silicon (SGPS) technique is proposed to achieve high-performance integrated inductor and effective isolation. The inductors and isolation structures are fabricated in standard CMOS process and then this post-CMOS SGPS technique is carried out to greatly improve the performances of inductors and crosstalk isolation. For a 4.5 nH inductor fabricated in standard CMOS process, an over 100% increase (from 4.8 to 9.7) in peak Q-factor and an about 200% increase (from 4 GHz to 12 GHz) in resonance frequency are obtained. Furthermore, a thick SGPS trench for crosstalk isolation has been formed and about 20 dB improvement in substrate isolation is achieved. These results demonstrate that the post-CMOS SGPS technique is very promising for RFIC applications.

Li, Chen; Liao, Huailin; Yang, Li; Huang, Ru

2007-06-01

223

A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application  

SciTech Connect

A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

Eaton, W.P. [New Mexico, Albuquerque, NM (United States); Smith, J.H. [Sandia National Labs., Albuquerque, NM (United States)

1994-12-31

224

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology  

Microsoft Academic Search

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas\\/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon

Chih-Cheng Lu; Kuan-Hsun Liao; F. Udrea; J. A. Covington; J. W. Gardner

2008-01-01

225

Design of a low-power 3.5GHz broad-band CMOS transimpedance amplifier for optical transceivers  

Microsoft Academic Search

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-?m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz

S. M. Rezaul Hasan

2005-01-01

226

An Ultra Low Voltage, Low Power, Fully Integrated VCO for GPS in 90 nm RF-CMOS  

Microsoft Academic Search

A fully integrated 0.6 V VCO for the GPS L1 band is realized in a 90 nm RF-CMOS process. The purpose of the design is to demonstrate how suitable deep submicron CMOS transistors are for ultra low voltage, low power oscillator design. The VCO operates at 6.3 GHz and a divide-by-four circuit buffer provide the wanted 1575.42 MHz signal. Measured

L. Aspemyr; D. Linten

2006-01-01

227

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

228

Simulation of SEU transients in CMOS ICs  

SciTech Connect

This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

Kaul, N.; Bhuva, B.L.; Kerns, S.E. (Space Electronics Research Group, Vanderbilt Univ., Nashville, TN (US))

1991-12-01

229

HELIOS: photonics electronics functional integration on CMOS  

NASA Astrophysics Data System (ADS)

Silicon photonics have generated an increasing interest in the recent year, mainly for optical telecommunications or for optical interconnects in microelectronic circuits. The rationale of silicon photonics is the reduction of the cost of photonic systems through the integration of photonic components and an IC on a common chip, or in the longer term, the enhancement of IC performance with the introduction of optics inside a high performance chip. In order to build a Opto-Electronic Integrated circuit (OEIC), a large European project HELIOS has been launched two years ago. The objective is to combine a photonic layer with a CMOS circuit by different innovative means, using microelectronics fabrication processes. High performance generic building blocks that can be used for a broad range of applications are developed such as WDM sources by III-V/Si heterogeneous integration, fast Si modulators and Ge or InGaAs detectors, Si passive circuits and specific packaging. Different scenari for integrating photonic with an electronic chip and the recent advances on the building blocks of the Helios project are presented.

Fédéli, Jean-Marc; Fulbert, Laurent; Van Thourhout, Dries; Viktorovitch, Pierre; O'Connor, Ian; Duan, Guang-Hua; Reed, Graham; Della Corte, Francesco; Vivien, Laurent; Lopez Royo, Francisco; Pavesi, Lorenzo; Garrido, Blas; Grard, Emmanuel; Tillack, Bernd; Zimmermann, Lars; Formont, Stéphane; Hakansson, Andreas; Wachmann, Ewald; Zimmermann, Horst; Bakker, Arjen; Porte, Henri

2010-05-01

230

RF CMOS UWB transmitter and receiver front-end design  

E-print Network

The low-cost low-power complementary metal-oxide semiconductor (CMOS) ultra wideband (UWB) transmitter and receiver front-ends based on impulse technology were developed. The CMOS UWB pulse generator with frequency-band tuning capability...

Miao, Meng

2009-05-15

231

Development of fast and high throughput tomography using CMOS image detector at SPring-8  

NASA Astrophysics Data System (ADS)

A fast micro-tomography system and a high throughput micro-tomography system using state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) imaging devices have been developed at SPring-8. Those systems adopt simple projection type tomography using synchrotron radiation X-ray. The fast micro-tomography system achieves a scan time around 2 s with 1000 projections, which is 15 times faster than previously developed system at SPring-8. The CMOS camera for fast tomography has 64 Giga Byte on-board memory, therefore, the obtained images must be transferred to a PC at the appropriate timing. A melting process of snow at room temperature was imaged every 30 s as a demonstration of the system. The high throughput tomography system adopts a scientific CMOS (sCMOS) camera with a low noise and high quantum efficiency. The system achieves a scan time around 5 minutes which is three times faster than before. The images quality of the system has been compared to the existing system with Charge-Coupled Device (CCD) camera. The results have shown the advantage of the new sCMOS camera.

Uesugi, Kentaro; Hoshino, Masato; Takeuchi, Akihisa; Suzuki, Yoshio; Yagi, Naoto

2012-10-01

232

New package for CMOS sensors  

NASA Astrophysics Data System (ADS)

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

2004-02-01

233

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits  

NASA Astrophysics Data System (ADS)

In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60×180nm2 achieves a large change in resistance of 3.52k? (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

Iga, Fumitaka; Kamiyanagi, Masashi; Ikeda, Shoji; Miura, Katsuya; Hayakawa, Jun; Hasegawa, Haruhiro; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

234

LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY  

E-print Network

are incompatible with the CMOS technology trends of the future. Ways to circumvent this conflict are to develop, or develop circuit techniques that are compatible with future standard CMOS technology trends. This paperLOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock

Rincon-Mora, Gabriel A.

235

A nano-metallic-particles-based CMOS image sensor for DNA detection  

NASA Astrophysics Data System (ADS)

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano-metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 ?m CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

He, Jin; Su, Yan-Mei; Ma, Yu-Tao; Chen, Qin; Wang, Ruo-Nan; Ye, Yun; Ma, Yong; Liang, Hai-Lang

2012-07-01

236

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate  

PubMed Central

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 ?m UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is ?42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 ?A, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

237

Implementation of the CMOS MEMS condenser microphone with corrugated metal diaphragm and silicon back-plate.  

PubMed

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 ?m UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is -42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz-10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 ?A, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

238

RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications  

NASA Astrophysics Data System (ADS)

New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS ‘Receiver-on-a-Chip’ is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 ?m RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

Jackson, Suzy A.

2004-06-01

239

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

240

An ultra-low-power CMOS temperature sensor for RFID applications  

NASA Astrophysics Data System (ADS)

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-?m CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 ?A @ 1.8 V for continuous operation and achieves an accuracy of ±0.65 °C from -20 to 120 °C after calibration at one temperature.

Conghui, Xu; Peijun, Gao; Wenyi, Che; Xi, Tan; Na, Yan; Hao, Min

2009-04-01

241

Second Generation Monolithic Full-depletion Radiation Sensor with Integrated CMOS Circuitry  

SciTech Connect

A second-generation monolithic silicon radiation sensor has been built and characterized. This pixel detector has CMOS circuitry fabricated directly in the high-resistivity floatzone substrate. The bulk is fully depleted from bias applied to the backside diode. Within the array, PMOS pixel circuitry forms the first stage amplifiers. Full CMOS circuitry implementing further amplification as well as column and row logic is located in the periphery of the pixel array. This allows a sparse-field readout scheme where only pixels with signals above a certain threshold are readout. We describe the fabrication process, circuit design, system performance, and results of gamma-ray radiation tests.

Segal, J.D.; Kenney, C.J.; /SLAC; Parker, S.I.; /Hawaii U.; Aw, C.H.; /UOB Ventiure Management, Singapore; Snoeys, W.J.; /CERN; Wooley, B.; Plummer, J.D.; /Stanford U., Elect. Eng. Dept.

2011-05-20

242

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker  

NASA Astrophysics Data System (ADS)

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 ?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

2013-08-01

243

Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor  

NASA Astrophysics Data System (ADS)

A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal–oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35??m CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35?dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 ?-based test facilities. In this work, we design a clamped–clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10?k?, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

2014-09-01

244

Investigation of Fast Switched CMOS Inverter using  

E-print Network

Inverter is truly the nucleus of electronics industry. It is the main building block of everyday appliances i.e. microwaves, power tools, battery chargers, air conditioners and computers etc. In this paper, CMOS technology has been chosen to study the transient and dc characteristics of an inverter. Feature size is the main parameter to study the voltage transfer characteristics of inverter, for which length and width of transistors is varied. Further, CMOS inverters can be paralleled for increased power to drive higher current loads. Simulations are run on cadence design tool and the schematic diagrams are drawn in virtuoso schematic editor using 180nm technology file.

Navneet Kaur; Guru Nanak; Dev Engineering; Gurpurneet Kaur; Chahat Jain; Guru Nanak; Dev Engineering

245

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

246

Fabrication and characterization of CMOS-MEMS magnetic microsensors.  

PubMed

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5-200 mT. PMID:24172287

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

247

DVD OEIC and 1 Gbit\\/s fiber receiver in CMOS technology  

Microsoft Academic Search

Two new CMOS OEICs (optoelectronic integrated circuits) with integrated photodiodes for the application in DVD (digital versatile disc) systems and for optical data transmission are presented. Due to the integration of the photodiodes and the analog signal processing circuits on the same chip, smaller dimensions, better immunity against electromagnetic interference (EMI) and faster systems are achievable. Furthermore, a higher reliability

A. Ghazi; T. Heide; H. Zimmermann; P. Seegebrecht

2000-01-01

248

100 nm gate length high performance\\/low power CMOS transistor structure  

Microsoft Academic Search

We report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V. These transistors are incorporated in a 180 nm logic technology generation. Various process enhancements are incorporated to significantly improve transistor current drive capability relative to the results published by Yang et al. (1998). Unique transistor features responsible for achieving high performance are described.

T. Ghani; S. Ahmed; P. Aminzadeh; J. Bielefeld; P. Charvat; C. Chu; M. Harper; P. Jacob; C. Jan; J. Kavalieros; C. Kenyon; R. Nagisetty; P. Packan; J. Sebastian; M. Taylor; J. Tsai; S. Tyagi; S. Yang; M. Bohr

1999-01-01

249

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms  

Microsoft Academic Search

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and

Paulo F. Butzen; Leomar S. da Rosa Jr.; Erasmo J. D. Chiappetta Filho; Dionatan S. Moura; André Inácio Reis; Renato P. Ribas

2008-01-01

250

Design of Wide Tuning-Range CMOS VCOs Using Switched Coupled-Inductors  

Microsoft Academic Search

Two designs of voltage-controlled oscillators (VCOs) with mutually coupled and switched inductors are presented in this paper to demonstrate that the tuning range of an LC VCO can be improved with only a small increase in phase noise and die area in a standard digital CMOS process. Particular attention is given to the layout of the inductors to maintain Q

Murat Demirkan; Stephen P. Bruss; Richard R. Spencer

2008-01-01

251

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS  

Microsoft Academic Search

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM) and how it controls calibration and compensation for

Roman Staszewski; Robert Bogdan Staszewski; Tom Jung; Thomas Murphy; Imran Bashir; Oren Eliezer; Khurram Muhammad; Mitch Entezari

2010-01-01

252

Abstract--As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more  

E-print Network

theoretical performance. Index Terms-- Analog to digital converter, delta-sigma modulation, interleaved data mismatches and nonlinearity is appropriate. II. 1BDELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS It is known of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes

Baker, R. Jacob

253

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM  

E-print Network

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM Garima Thakral1 memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM in the read SNM. The process variation analysis of the optimal SRAM carried out considering twelve device

Mohanty, Saraju P.

254

Radiation response of two Harris semiconductor radiation hardened 1k CMOS RAMs  

SciTech Connect

This paper describes the testing of two types 1K CMOS static RAMs in various transient and steady state ionizing radiation environments. Type HM 6551R (256x4 bits) and type HM 6508R (1024x1 bit) RAMs were evaluated. The RAMs are radiation hardened versions of Harris' commercial RAMs. A brief description of the radiation hardened process is presented.

Abare, W.E.; Huffman, D.D.; Moffett, G.E.

1982-12-01

255

High and Low Light CMOS Imager Employing Wide Dynamic Range Expansion and Low Noise Readout  

Microsoft Academic Search

A high and low light imager (HALLI) developed in a CMOS process is presented. The HALLI utilizes a single column parallel partitioned pixel amplifier with variable topology for the detection of both high and low light levels in the same frame. For high light level detection, a wide dynamic range algorithm is utilized in which multiple resets via real-time feedback

Yonathan Dattner; Orly Yadid-Pecht

2012-01-01

256

A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems  

E-print Network

to implement real-time brain-like processing learning systems with about 108 neurons and 1012 synapses on one1 A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems Teresa Serrano, a discipline that implements physical artifacts based on neuroscience knowledge, has related neural learning

Barranco, Bernabe Linares

257

Improvement for bond pads discolor (sic) of CMOS image sensor products  

Microsoft Academic Search

The CMOS image sensor is covered with a color filter. Bond pads discoloration was found after the color filter process. SEM analysis showed metal loss of the bond pads, and residues in the discolored area. EDS results showed the residues contained mostly C and O elements, indicating photoresist residues. These defects caused package reliability problems based on a bondability test.

Chih-Hsing Chen; Hong-Wen Huang; Chih-Chen Kuo; Hung-Jen Tsai

2001-01-01

258

III V CMOS:III-V CMOS: A sub-10 nm Electronics Technology?gy  

E-print Network

Microsystems Technology Laboratories, MIT AVS 57th International Symposium & Exhibition October 17-22, 2010 microprocessors Intel microprocessors 3 #12;Recent trend in CMOS scaling · Si CMOS has entered era of "power nm)- InAs core (tInAs = 5 nm) - InGaAs cladding - n Hall = 13,200 cm2/V-secn,Hall 13,200 cm /V sec

del Alamo, Jesús A.

259

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch  

NASA Astrophysics Data System (ADS)

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 ?m pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 ?m pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

260

Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.  

PubMed

We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects. PMID:23903103

Shainline, Jeffrey M; Orcutt, Jason S; Wade, Mark T; Nammari, Kareem; Moss, Benjamin; Georgas, Michael; Sun, Chen; Ram, Rajeev J; Stojanovi?, Vladimir; Popovi?, Miloš A

2013-08-01

261

Fabrication of a CMOS compatible nanopore detector for DNA  

NASA Astrophysics Data System (ADS)

Nanopore based DNA sequencers require integration of miniaturized electrodes and amplifier electronics in close proximity to the nanopores in a CMOS platform. This will facilitate portability, enable faster analysis, and improve sensing performance. Here we report for the first time the fabrication of a DNA nanopore detector compatible with a standard CMOS process. Our nanopore devices are made using an N+ polysilicon/gate oxide/N+ polysilicon stack on an oxidized silicon substrate identical to the AMI 0.5? process. The nanopores are created in the gate oxide membrane (36 nm) while doped polysilicon layers (250 and 370 nm) act as electrodes to apply bias across pores. Five lithography masks are used to pattern the oxide membrane and the electrodes. The nanopores are defined by etching the membrane using electron beam lithography patterned holes in a resist mask. Using this method we have directly fabricated pores with diameters as small as 11 nm, without applying conventional pore shrinkage techniques. This is enhanced by cold development of the e-beam exposed resist resulting in sub-10 nm pores. DNA experiments are currently underway utilizing our nanopores.

Uddin, Ashfaque; Milaninia, Kaveh; Elibol, Oguz; Daniels, Jonathan; Su, Xing; Varma, Madoo; Stein, Derek; Theogarajan, Luke

2010-03-01

262

Electronic-photonic integrated circuits on the CMOS platform  

NASA Astrophysics Data System (ADS)

The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

2006-02-01

263

A fully integrated CMOS chopper amplifier  

Microsoft Academic Search

A CMOS chopper amplifier that achieves reduced input offset voltage and fast overload recovery time while maintaining bandwidths comparable to conventional operational amplifiers and requiring no external components is presented. The chopper amplifier consists of two folded cascode operational transconductance amplifiers (OTA) connected in a switched feed-forward configuration, and a third OTA that is used to realize a large capacitive

Doug Garrity; Jenkuan Young; Don Thelen

1991-01-01

264

ALU design using reconfigurable CMOS logic  

Microsoft Academic Search

In designing ALUs, many techniques have been followed. The functional units of an ALU have been realized using conventional transistors and pass transistor gates. In this paper, we present the design of a 4 bit ALU using multi-input floating gate (MIFG) CMOS reconfigurable logic. It has been designed in a 1.5 ?m technology for 3 V operation. The ALU can

A. Srivastava; C. Srinivasan

2002-01-01

265

Switch level optimization for CMOS circuits  

E-print Network

In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

Chugh, Pankaj Pravinkumar

2012-06-07

266

A study on CMOS negative resistance circuits  

Microsoft Academic Search

An in-depth study of CMOS transconductor designed negative resistance circuits is presented. Important large signal and small signal characteristics including noise, stability and bandwidth are investigated. A strategy of designing large bandwidth active resistors is proposed with supporting analysis. Key stability issues that have not previously been reported are discussed. Finally, applications which include the design of a low phase

Vishal Patel; R. Raut

2008-01-01

267

Predictive Oscillation Based Test of CMOS circuits  

Microsoft Academic Search

Two different CMOS circuits has been used to check the predictive oscillation based test (POBT) approach, combined with supply current monitoring technique. These circuits are a two stage op amp and a biquad filter composed by two transconductance amplifiers (OTA). The combination of both techniques has given excellent results in predicting the main performance parameters of the circuits as DC

K. Suenaga; E. Isern; R. Picos; S. Bota; M. Roca; E. Garcia-Moreno

2006-01-01

268

Micropower CMOS temperature sensor with digital output  

Microsoft Academic Search

A CMOS smart temperature sensor with digital output is presented. It consumes only 7 ?W. To achieve this extremely low-power consumption, the system is equipped with a facility that switches off the supply power after each sample. The circuit uses substrate bipolars as a temperature sensor. Conversion to the digital domain is done by a sigma-delta converter which makes the

Anton Bakker; J. H. Huijsing

1996-01-01

269

An integrated CMOS microsystem for NMR applications  

Microsoft Academic Search

A monolithic CMOS microsystem for nuclear magnetic resonance applications has been designed and tested. It includes two planar microcoils and a complete readout electronics with a single 3.3 V supply. It measures static fields around 1 T with a field resolution better than 1 ppm\\/?Hz. The probe can also be used for NMR spectroscopy with a spectral resolution of 15

J. Frounchi; G. Boero; B. Furrer; P.-A. Besse; R. S. Popovic

2001-01-01

270

CMOS preamplifiers for detectors large and small  

SciTech Connect

We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

O`Connor, P. [Brookhaven National Lab., Upton, NY (United States)

1997-12-31

271

Low energy CMOS for space applications  

NASA Technical Reports Server (NTRS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

272

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies  

Microsoft Academic Search

An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS \\

M. Horstmann; A. Wei; T. Kammler; J. Hontschel; H. Bierstedt; T. Feudel; K. Frohberg; M. Gerhardt; A. Hellmich; K. Hempel; J. Hohage; P. Javorka; J. Klais; G. Koerner; M. Lenski; A. Neu; R. Otterbach; C. Reichel; M. Trentsch; B. Trui; H. Salz; M. Schaller; H.-J. Engelmann; O. Herzog; H. Ruelke; P. Hubler; R. Stephan; D. Greenlaw; M. Raab; N. Kepler; H. Chen; D. Chidambarrao; D. Fried; J. Holt; W. Lee; H. Nii; S. Panda; T. Sato; A. Waite; S. Liming; K. Rim; D. Schepis; M. Khare; S. F. Huang; J. Pellerin; L. T. Su

2005-01-01

273

Evaluation of a CMOS image detector for low-cost and power medical x-ray imaging applications  

NASA Astrophysics Data System (ADS)

Recent developments in CMOS image detectors are changing the way digital imaging is performed for many applications. The replacement of charge coupled devices (CCDs), with CMOS detectors is a desirable paradigm shift that will depend on the ability to match the high performance characteristics of CCDs. Digital X-ray imaging applications (chest X-ray, mammography) would benefit greatly from this shift because CMOS detectors have the following inherent characteristics: (1) Low operating power (5 - 10 times lower than CCD/processing electronics). (2) Standard CMOS manufacturing process (CCD requires special manufacturing). (3) On-chip integration of analog/digital processing functions (difficult with CCD). (4) Low Cost (5 - 10 times lower cost than CCD). The achievement of both low cost and low power is highly desirable for portable applications as well as situations where large, expensive X-ray imaging machines are not feasible (small hospitals and clinics, emergency medical vehicles, remote sites). Achieving this goal using commercially available components would allow rapid development of such digital X-ray systems as compared with the development difficulties incurred through specialized direct detectors and systems. The focus of this paper is to evaluate a CMOS image detector for medical X-ray applications and to demonstrate the results obtained from a prototype CMOS digital X-ray camera. Results from the images collected from this optically-coupled camera are presented for a particular lens, X-ray conversion screen, and demagnification factor. Further, an overview of the overall power consumption and cost of a multi-sensor CMOS mosaic compared to its CCD counterpart are also reported.

Smith, Scott T.; Bednarek, Daniel R.; Wobschall, Darold C.; Jeong, Myoungki; Kim, Hyunkeun; Rudin, Stephen

1999-05-01

274

Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies  

NASA Astrophysics Data System (ADS)

A new transient macromodel for the cells used in DCFL GaAs and CMOS digital design is introduced in this paper. The numerical solution determines accurate propagation delay times. The macromodel is based on the differential equation for the output voltage in terms of currents and capacitances. An straightforward treatment of the differential equation for an inverter in DCFL GaAs and CMOS has been obtained. It could be resolved numerically by a 4th order Runge Kutta method. Good agreement is obtained between the HSPICE simulation and the computation of the propagation delays for DCFL GaAs and CMOS basic gates: INV, NOR, OR and NAND. There is no error between HSPICE and our computation of propagation delay time for the high to low (tphl) and low to high (tplh) transitions. The propagation delay times for two types of transition were measured and compared with HSPICE. The results demonstrate that our approach matches with HSPICE with no error. The numerical method was programmed in C language. In addition, computation time analysis is provided and numerical solution is several orders of magnitude faster than HSPICE. Work is in progress to obtain the macromodel of a standard cell library for digital application both for a 0.6 microns E/D GaAs process (H-GaAsIV) from Vitesse Semiconductor and for a 0.18 microns logic/mixed-signal CMOS process (1P6M) from TSMC Corp.

Garcia, Jose C.; Montiel-Nelson, Juan A.; Sosa, Javier; Navarro, Hector; Sarmiento, Roberto

2003-04-01

275

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems  

PubMed Central

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 ?) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 ?W).

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

276

Failure analysis of a half-micron CMOS IC technology  

SciTech Connect

We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S. [and others

1996-08-01

277

A CMOS Smart Temperature and Humidity Sensor with Combined Readout  

PubMed Central

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

278

Post-irradiation effects in CMOS integrated circuits  

SciTech Connect

The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80/sup 0/C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105/sup 0/C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80/sup 0/C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal.

Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

1988-12-01

279

CMOS-compatible active thermopiles for noise-added theory  

NASA Astrophysics Data System (ADS)

Recently a novel signal processing theory related with noise has grown and proven. Certain complex systems can improve performance with added optimal noise that classical theory cannot explain. Their behavior may be represented by a simplified scheme that combines both a deterministic and stochastic source. To that end, we are using noise in remote temperature sensing system to enhance their function without altering the system. A new investigation of noise added scheme has been realized by an embedded heater for CMOS compatible thermoelectric infrared sensor. The design and fabrication of thermopile sensors are realized by using 1.2?m CMOS IC technology combined with a subsequent anisotropic front-side etching. We firstly develop an active thermopile with a heater embedded which is easily and naturally driven by a noise generation circuit. The stochastic resonance theory can be realized as a reduction in threshold of temperature detection. We have shown the possibility of improving the performance of remote temperature sensing system in the presence of noise. The strategy depends on the application. Stochastic resonance can reduce threshold detection resolution and greatly improve the temperature detection limit with a low cost scheme without using higher resolution ADC.

Shen, Chih-Hsiung; Hou, Kuan-Chou

2004-05-01

280

High-performance VGA-resolution digital color CMOS imager  

NASA Astrophysics Data System (ADS)

This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

1999-04-01

281

Development of a radiation hardened npn bipolar transistor for a 64K CMOS fusible-link PROM  

SciTech Connect

A 1.2 [mu]m CMOS production process was adapted to produce a 64K CMOS fusible-link Programmable Read-Only Memory (PROM) for space applications. The circuit requirement of less than 50 nS access time combined with the need for 9 volt single pulse programming of the fusible links and radiation tolerance to levels over 300 Krad(Si) made close collaboration between design engineering, reliability engineering, and device engineering essential for a successful project. A vertical NPN bipolar transistor was integrated into a standard CMOS process to be used for programming and reading the fuses. The device characteristics were carefully matched to the product speed and programmability requirements. The NPN device was optimized for radiation performances. Successful development required extensive use of process and device modeling, test structure design and measurement, and experimental design methods.

Fuller, R.; Newman, W. (Harris Semiconductor, Melbourne, FL (United States))

1994-12-01

282

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors  

NASA Astrophysics Data System (ADS)

This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 ?m CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

2013-08-01

283

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays  

PubMed Central

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 ?m two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/?Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

284

A radiation hardened SONOS/CMOS EEPROM family  

SciTech Connect

There has long been a need for fast read nonvolatile, rad hard memories for military and space applications. Recent advances in EEPROM technology now allow this need to be met for many applications. Harris/Sandia have developed a 16k and a 256k rad hard EEPROM. The EEPROMs utilize a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory transistor integrated into a 2 {mu}m, rad hard two level metal CMOS process. Both the 16k and the 256k parts have been designed to interface with the Intel 8085 or 80C51 and National 32000 series microprocessors and feature page and block clear modes. Both parts are functionally identical, and are produced by the same fabrication process. They are also pin for pin compatible with each other, except for the extra address and ground pins on the 256k. This paper describes the characteristics of this EEPROM family. 1 ref.

Klein, V.F.; Wood, G.M.; Buller, J.F. (Harris Corp., Melbourne, FL (USA). Semiconductor Sector); Murray, J.R.; Rodriquez, J.L. (Sandia National Labs., Albuquerque, NM (USA))

1990-01-01

285

Critical charge concepts for CMOS SRAMs  

SciTech Connect

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge can be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must taken into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.

Dodd, P.E.; Sexton, F.W. [Sandia National Labs., Albuquerque, NM (United States)] [Sandia National Labs., Albuquerque, NM (United States)

1995-12-01

286

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors  

PubMed Central

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

287

Battery-powered digital CMOS design  

Microsoft Academic Search

In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and

Massoud Pedram; Qing Wu

1999-01-01

288

RF-CMOS oscillators with switched tuning  

Microsoft Academic Search

Fully integrated CMOS oscillators are of great interest for use in single-chip wireless transceivers. In most oscillator circuits reported to date that operate in the 0.9 to 2 GHz frequency range, an integrated spiral inductor sets the frequency. It is generally believed that an LC oscillator, even when it uses a low-Q inductor, displays a lower phase noise than a

A. Kral; F. Behbahani; A. A. Abidi

1998-01-01

289

Analog Circuit Design in Nanoscale CMOS Technologies  

Microsoft Academic Search

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic

Lanny L. Lewyn; Trond Ytterdal; Carsten Wulff; Kenneth Martin

2009-01-01

290

Critical charge concepts for CMOS SRAMs  

Microsoft Academic Search

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations

P. E. Dodd; F. W. Sexton

1995-01-01

291

Layout optimization of static CMOS functional cells  

Microsoft Academic Search

A general theory for designing minimum-area layouts of static series-parallel CMOS functional cells (also called complex gates) in a standard cell layout style is presented. T. Uehara and W.M. vanCleemput. (1981) originally formulated this as the graph optimization problem of finding the minimum number of dual trails that cover a multigraph model of M of a cell. The present theory

Robert L. Maziasz; John P. Hayes

1990-01-01

292

A CMOS interface IC for CCD imagers  

Microsoft Academic Search

A 2- mu m CMOS IC interfaces directly to the output of a CCD, level shifts the signal, amplifies it by a 4-bit programmable gain of up to 20 dB, and corrects the offset per pixel with a 3-bit word. A non-reset video output is obtained with an internal time-interleaved architecture. The total harmonic distortion (THD) of -50 dB is

K. Y. Kim; A. A. Abidi

1993-01-01

293

Noise modeling for RF CMOS circuit simulation  

Microsoft Academic Search

The RF noise in 0.18-?m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with

Andries J. Scholten; Luuk F. Tiemeijer; Ronald van Langevelde; Ramon J. Havens; A. T. A. Zegers-van Duijnhoven; Vincent C. Venezia

2003-01-01

294

Low noise CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

We present a new two-axis fluxgate magnetometer fully integrated in CMOS technology. The magnetometer exhibits excellent sensitivity of 2700 V\\/T and the magnetic equivalent noise spectral density of 6nT\\/?Hz at 1 Hz. The total power consumption is as low as 35 m W from the single 5 V power supply. The low noise characteristic is obtained using the combination of

Predrag M. Drljaca; P. Kejik; F. Vincent; R. S. Popovic

2003-01-01

295

OPASYN: a compiler for CMOS operational amplifiers  

Microsoft Academic Search

A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and

Han Young Koh; Carlo H. Séquin; Paul R. Gray

1990-01-01

296

Thermoelectric AC power sensor by CMOS technology  

Microsoft Academic Search

The authors report the development of a thermoelectric AC power sensor (thermoconverter) realized by industrial CMOS IC technology in combination with postprocessing micromachining. The sensor is based on a polysilicon heating resistor and a polysilicon\\/aluminum thermopile integrated on an oxide microbridge. The thermopile sensitivity is 9.9 mV\\/mW and the burn-out power of the sensor is 50 mW. The time constant

Dominik Jaeggi; Henry Baltes; David Moser

1992-01-01

297

A 0.4 micron fully complementary BiCMOS technology for advanced logic and microprocessor applications  

Microsoft Academic Search

A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5 ?m logic and microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n+\\/p+) gate CMOS process flow. Using a pedestal implant in the emitter window, the n-p-n performance has been enhanced

S. W. Sun; P. G. Y. Tsui; B. M. Somero; J. Klein; F. Pintchovski; J. R. Yeargain; B. Pappert

1991-01-01

298

CMOS Characterization, Modeling, and Circuit Design in the Presence of Random Local Variation.  

E-print Network

??Random local variation in CMOS transistors complicates characterization procedures, modeling efforts, simulation tools, and circuit design methodologies in highly scaled CMOS devices. Mismatch is not… (more)

Millemon, Benjamin A., Sr.

2012-01-01

299

Self-Oscillating Harmonic OptoElectronic Mixer Based on a CMOS-Compatible Avalanche Photodetector for Fiber-Fed 60GHz Self-Heterodyne Systems  

Microsoft Academic Search

A self-oscillating harmonic opto-electronic mixer based on a CMOS-compatible avalanche photodetector for fiber-fed 60-GHz self-heterodyne systems is demonstrated. The mixer is composed of an avalanche photodetector fabricated with 0.18-mum standard CMOS process and an electrical feedback loop for self oscillation. It simultaneously performs photodetection and frequency up-conversion of photodetected signals into the second harmonic self-oscillation frequency band. The avalanche photodetector

Myung-Jae Lee; Hyo-Soon Kang; Kwang-Hyun Lee; Woo-Young Choi

2008-01-01

300

A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability  

Microsoft Academic Search

This work demonstrates a self-referenced CMOS LCO, or CMOS harmonic oscillator (CHO), that exhibits 90ppm total frequency error over process, bias and temperature, thus making it suitable for replacing XOs in many applications. Additionally, the clock generator can be configured to produce a number of different output frequencies, has 1\\/4 of the frequency error of the oscillator in [3] and

Michael S. McCorquodale; Scott M. Pernia; Justin D. O'Day; Gordy Carichner; Eric Marsman; Nam Nguyen; Sundus Kubba; Si Nguyen; Jon Kuhn; Richard B. Brown

2008-01-01

301

Hafnium oxide and hafnium aluminum oxide for CMOS applications  

NASA Astrophysics Data System (ADS)

The continued scaling of the CMOS gate dielectric to its fundamental limit governed by the large gate leakage current requires the introduction of high-k material for sub-100-nm technology nodes. This dissertation research deals with the physical and electrical properties of a promising high-k candidate, hafnium oxide, as a gate dielectric for CMOS applications. Hafnium oxide made by the Jet-Vapor-Deposition process shows very promising properties in terms of surface roughness, dielectric constant, and energy bandgap, but there are also severe challenges, such as low crystallization temperature, high charge trapping probability, and low channel mobility, which have been studied in detail in this thesis. We have found that the crystallization of HfO2 could result in a significant increase of the leakage current. This problem has been solved by adding Al in the HfO2 film. The impacts of Al inclusion in HfO 2 film on crystallization temperature, bandgap energy, and dielectric constant have been investigated. Considering the trade-off among the crystallization temperature, bandgap energy, and dielectric constant, we have concluded that the optimum concentration is about 30% Al for conventional self-aligned CMOS gate processing technology. The charge trapping properties of ultra-thin HfO2 in metal-oxide-silicon capacitors during constant voltage stress have also been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode have been studied in detail, and reported in this dissertation. Accurate measurements and degradation mechanisms of the channel mobility for MOSFETs with HfO2 as the gate dielectric have been systemetically studied. The error in mobility extraction caused by a high density of interface traps for a MOSFET with high-k gate dielectric has been analyzed, and a new method to correct this error has been proposed. Other sources of error in mobility extraction, including gate leakage current, channel resistance, and contact resistance for a MOSFET with ultra-thin high-k dielectric have also been investigated and reported in this thesis. Based on the accurately measured channel mobility, we have analyzed the degradation mechanisms of channel mobility for a MOSFET with HfO2 as the gate dielectric. The mobility degradation due to Coulomb scatting arising from interface trapped charges, and that due to remote soft optical phonon scattering are discussed.

Zhu, Wenjuan

302

Enabling Solutions for 28 nm CMOS Advanced Junction Formation  

NASA Astrophysics Data System (ADS)

Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K/metal gate or stress induced carrier mobility enhancement. Ultra-Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra-Shallow Junction formations in terms of figure of merits of Rs/Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, C2B10H12) molecular implant and Phosphorus along with co-implantation and PTC II (VSEA Process Temperature Control) technology, sub-32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state-of-the-art 28 nm device manufacturing.

Li, C. I.; Kuo, P.; Lai, H. H.; Ma, K.; Liu, R.; Wu, H. H.; Chan, M.; Yang, C. L.; Wu, J. Y.; Guo, B. N.; Colombeau, B.; Thirumal, T.; Arevalo, E.; Toh, T.; Shim, K. H.; Sun, H. L.; Wu, T.; Lu, S.

2011-01-01

303

RF power potential of 45 nm CMOS technology  

E-print Network

This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

Putnam, Christopher

304

Biological inspired CMOS foveated sensor: For neural network training  

Microsoft Academic Search

In this work we describe the design and testing of a custom CMOS-based motion detection system that derives its functionality from biology. The system will beone component of a CMOS visual sensor system that will identify and foveate on objects. The system is inspired by different animals that perform similar functions and have similar retinal structures. For example, we mimic

Yongwoo Jeong; Albert H. Titus

2011-01-01

305

Failures of CMOS Circuits Irradiated At Low Rates  

NASA Technical Reports Server (NTRS)

Report describes experiments on irradiation of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated inverter circuits by 60Co and 137Cs radioactive sources. Purpose of experiments to supplement previous observations that minimum radiation doses at which failure occurred in more-complicated CMOS parts were lower at lower dose rates.

Goben, Charles A.; Price, William E.

1990-01-01

306

Fluctuation limits & scaling opportunities for CMOS SRAM cells  

Microsoft Academic Search

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write operation to be more fluctuation limited. Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations

Azeez Bhavnagarwala; Stephen Kosonocky; Carl Radens; Kevin Stawiasz; Randy Mann; Qiuyi Ye; Ken Chin

2005-01-01

307

Supply and threshold voltage scaling for low power CMOS  

Microsoft Academic Search

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In

Ricardo Gonzalez; Benjamin M. Gordon; Mark A. Horowitz

1997-01-01

308

A 1-V CMOS log-domain integrator  

Microsoft Academic Search

A novel circuit implementation of a CMOS log-domain integrator is presented. Unlike most other implementations, it does not require placing of MOSFETs in separated wells, and therefore allows very compact filters, which are fully compatible with modern standard CMOS technologies. Besides the saving of chip area, this also helps to reduce parasitic capacitances. The most important advantage of this circuit

Dominique Python; Manfred Punzenberger; Christian C. Enz

1999-01-01

309

Variable Input Delay CMOS Logic for Low Power Design  

Microsoft Academic Search

Modern digital circuits consist of logic gates imple- mented in the complementary metal oxide semiconduc- tor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to out- put delay irrespective of which

Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell

2005-01-01

310

CCD\\/CMOS hybrid FPA for low light level imaging  

Microsoft Academic Search

We present a CCD \\/ CMOS hybrid focal plane array (FPA) for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low pixel cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of

Xinqiao Liu; Boyd A. Fowler; Steve K. Onishi; Paul Vu; David D. Wen; Hung Do; Stuart Horn

2005-01-01

311

The temperature characteristics of bipolar transistors fabricated in CMOS technology  

Microsoft Academic Search

This paper presents the results of an experimental investigation of the temperature characteristics of bipolar transistors fabricated in CMOS technology. These results have to be known and understood to enable the design of high-performance temperature sensors and bandgap references in CMOS integrated circuits. The non-idealities of proportional to the absolute temperature voltage (VPTAT) have been studied, and the results show

Guijie Wang; Gerard C. M Meijer

2000-01-01

312

Counter based CMOS temperature sensor for low frequency applications  

Microsoft Academic Search

A simple temperature sensor in Bi-CMOS technology is proposed for applications with low frequency temperature variations in addition to a complete analysis of each block in the system. Most CMOS temperature sensors are based on the temperature characteristics of parasitic bipolar transistors. Two important factors need to be met in the design of the sensor: the first is the accuracy

Omar Fathy; Ahmed Abdallah; Amr Wassal; Yehea Ismail

2010-01-01

313

A new compact model for junctions in advanced CMOS technologies  

Microsoft Academic Search

We present a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model contains Shockley-Read-Hall generation\\/recombination, trap-assisted tunneling, band-to-band-tunneling, and avalanche breakdown. It has been validated for a wide range of bias and temperature, for NMOS and PMOS junctions, and for different CMOS generations

A. J. Scholten; G. D. J. Smit; M. Durand; R. van Langevelde; C. J. J. Dachs; D. B. M. Klaassen

2005-01-01

314

Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,  

E-print Network

Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,§ Stanley P. Burgos, 243-0014, Japan ABSTRACT: We report on the optical properties of plasmonic hole arrays as they apply to requirements for plasmonic color filters designed for state-of-the-art Si CMOS image sensors. The hole arrays

Atwater, Harry

315

RF CMOS is more than CMOS: Modeling of RF passive components  

Microsoft Academic Search

This paper details recent progress in modeling some RF CMOS passive components: inductors, transformers, and resistors. Many different topologies have been proposed for networks to model spiral inductors; these are analyzed and shown to trend toward reviving the one-segment (pi- or T-topology) approach. The need to account for the distributed nature of metal windings and coupling through a lossy substrate

Zhiping Yu; Colin C. McAndrew

2009-01-01

316

CMOS transconductance multipliers: a tutorial  

Microsoft Academic Search

Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been

Gunhee Han; E. Sanchez-Sinencio

1998-01-01

317

Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope.  

PubMed

A novel tunable all-digital, ultrawideband pulse generator (PG) has been implemented in a standard 0.18-¿ m complementary metal-oxide semiconductor (CMOS) process for implantable medical applications. The chip shows that an ultra-low dynamic energy consumption of 27 pJ per pulse without static current flow at a 200-MHz pulse repetition frequency (PRF) with a 1.8-V power supply and low area of 90 × 50 ¿m(2). The PG generates tunable pulsewidth, amplitude, and transmit (Tx) power by using simple circuitry, through precise timing control of the H-bridge output stage. The all-digital architecture allows easy integration into a standard CMOS process, thus making it the most suitable candidate for in-vivo biotelemetry applications. PMID:23853319

Chul Kim; Nooshabadi, S

2010-04-01

318

Imaging performance comparison between CMOS and sCMOS detectors in a vibration test on large areas using digital holographic interferometry  

NASA Astrophysics Data System (ADS)

A comparison of the interferometric imaging performance of two different cameras during a vibration study is presented. One of the cameras has a high speed CMOS sensor and the second one uses a high resolution (scientific) sCMOS sensor. This comparison is based on the interferometric response as a merit parameter of these sensors which is not a conventional procedure. Even when the current standard for image quality is on the signal to noise ratio calculations, an interferometric test to evaluate the fringe pattern visibility is equivalent to the contrast to noise ratio value. An out of plane digital holographic interferometer is used to test each camera once at the time with the same experimental conditions. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The sample is deformed by means of a controlled vibration induced by a tip ended linear step motor. Results from each camera are presented as the retrieved optical phase during the vibration. Finally, some conclusions based on the post processed images are presented suggesting a smoother optical phase obtained with the sCMOS camera.

Flores-Morenoa, J. M.; Torre I., Manuel H. De la; Aguayo, Daniel D.; Fernando Mendoza, S.

2014-05-01

319

A 54-mW 8-Gbit/s VCSEL driver in a 65-nm CMOS technology  

NASA Astrophysics Data System (ADS)

We report a VCSEL driver ASIC designed and fabricated in a commercial 65-nm CMOS process. At 8 Gbps, the eye diagram passes the eye mask test and the bit-error-rate is less than 10-12 at the 95% confidence level. The total power consumption (including VCSEL) is about 54 mW, less than 1/4 of our previous VCSEL driver ASIC in a silicon-on-sapphire CMOS technology. The VCSEL driver has been tested in a neutron beam with the maximum energy of 800 MeV and the cross section has been estimated to be less than 3.14 × 10-11 cm2.

Liang, F.; Lu, W.; Chen, J.; Deng, B.; Gong, D.; Guo, D.; Jin, G.; Li, X.; Liang, H.; Liu, C.; Liu, G.; Wang, Z.; Xiang, A.; Xu, T.; Ye, J.; Liu, T.

2014-01-01

320

Optical characterization of CMOS compatible micro optics fabricated by mask-based and mask-less hybrid lithography  

NASA Astrophysics Data System (ADS)

We report a CMOS compatible fabrication and optical characterization of the micrometer scale optical coupler, a 45° mirror-based optical coupler for inter-layer optical coupling. A newly proposed mask-based and mask-less hybrid lithography process enables accurate surface profile of the micrometer sized 45° mirror by using a CMOS compatible buffer coat material. Surface profile inspected by an optical interferometry agrees well with SEM based inspection results. Experimental and theoretical results for routing and coupling of laser beam in 90° will be discussed.

Wang, Sunglin; Summitt, Chris; Johnson, Lee; Zaverton, Melissa; Milster, Tom; Takashima, Yuzuru

2014-09-01

321

Design of high speed camera based on CMOS technology  

NASA Astrophysics Data System (ADS)

The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

2007-12-01

322

Radiation Hardening of CMOS Microelectronics  

SciTech Connect

A unique methodology, silicon transfer to arbitrary substrates, has been developed under this program and is being investigated as a technique for significantly increasing the radiation insensitivity of limited quantities of conventional silicon microelectronic circuits. In this approach, removal of the that part of the silicon substrate not required for circuit operation is carried out, following completion of the circuit fabrication process. This post-processing technique is therefore applicable to state-of-the-art ICs, effectively bypassing the 3-generation technology/performance gap presently separating today's electronics from available radiation-hard electronics. Also, of prime concern are the cost savings that result by eliminating the requirement for costly redesign of commercial circuits for Rad-hard applications. Successful deployment of this technology will result in a major impact on the radiation hard electronics community in circuit functionality, design and software availability and fabrication costs.

McCarthy, A.; Sigmon, T.W.

2000-02-20

323

Ultra low power CMOS technology  

NASA Technical Reports Server (NTRS)

This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

Burr, J.; Peterson, A.

1991-01-01

324

U-shaped slow-wave transmission lines in 0.18?m CMOS  

Microsoft Academic Search

An area-efficient U-shaped slow-wave coplanar waveguide (U-SCPW) in a standard 0.18 ?m CMOS process is presented. Compared to a conventional straight line CPW (S-CPW), it provides a more compact layout because of its approximate 1:1 aspect ratio. Measured results show that it has a quality factor and phase velocity comparable to its straight-line counterpart with measured Q ~ 30 at

Heng-Chia Hsu; Kaushik Dasgupta; Nathan M. Neihart; Sudip Shekhar; Jeffrey S. Walling; David J. Allstot

2010-01-01

325

A low-voltage CMOS DC-DC converter for a portable battery-operated system  

Microsoft Academic Search

Motivated by emerging battery-operated applications that demand compact, lightweight, and highly efficient DC-DC power converters, a buck circuit is presented in which all active devices are integrated on a single chip using a standard 1.2 ? CMOS process. The circuit delivers 750 mW at 1.5 V from a 6 V battery. To effectively eliminate switching loss at high operating frequencies,

Anthony J. Stratakos; Seth R. Sanders; Robert W. Brodersen

1994-01-01

326

A 1.8GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler  

Microsoft Academic Search

The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-?m CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of

Jan Craninckx; Michel S. J. Steyaert

1995-01-01

327

CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices  

Microsoft Academic Search

Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating\\/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in

Ilku Nam; Bonkee Kim; Kwyro Lee

2005-01-01

328

A CMOS multi-bit sigma-delta modulator for video applications  

Microsoft Academic Search

This paper describes the design of a sigma-delta modulator with 5-bit quantizer for analog to digital conversion in video applications. A single poly, 0.35 µm CMOS process is used. Most of the quantization noise of a sigma-delta modulator is shifted to higher frequencies by noise shaping. The resulting output spectrum corresponds well with the noise sensitivity of the human eye

J. Vink; J. van Rens

1998-01-01

329

A 6-ns 1Mb CMOS SRAM with latched sense amplifier  

Microsoft Academic Search

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 ?m×7.2 ?m and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-?m triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new

Teruo Seki; Eisaki Itoh; Chiaki Furukawa; Isamu Maeno; Tadashi Ozawa; Hiroyuki Sano; Noriyuki Suzuki

1993-01-01

330

A micropower class AB CMOS log-domain filter for DECT applications  

Microsoft Academic Search

This paper presents a micropower 2nd-order low-pass filter using the log-domain principle and integrated in a 0.35 µm CMOS process. It has been designed as an anti-aliasing filter for a DECT transceiver with a 45 kHz nominal cut-off frequency. The circuit uses transistors biased in weak inversion without requiring separate wells. It operates at 1.5V supply voltage and its current

D. Python; C. C. Enz

2000-01-01

331

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip  

NASA Technical Reports Server (NTRS)

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

332

Radiation-hard design principles utilized in CMOS 8085 microprocessor family  

Microsoft Academic Search

A microprocessor family has been designed in radiation-hardened bulk, silicon-gate CMOS and the three main family members are logic emulations of Intel NMOS devices: SA3000, a general-purpose 8-bit central processing unit (CPU) (Intel 8085A); SA3001, a 256 x 8-bit static RAM with two 8-bit I\\/O ports, one 6-bit I\\/O port and a timer (Intel 8155\\/56); SA3002, a 2K x 8-bit

W. S. Kim; T. M. Mnich; W. T. Corbett; R. K. Treece; A. E. Giddings; J. L. Jorgensen

1983-01-01

333

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry  

Microsoft Academic Search

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and

Cristian Marcu; Debopriyo Chowdhury; Chintan Thakkar; Jung-Dong Park; Ling-Kai Kong; Maryam Tabesh; Yanjie Wang; Bagher Afshar; Abhinav Gupta; Amin Arbabian; Simone Gambini; Reza Zamani; Elad Alon; Ali M. Niknejad

2009-01-01

334

Shared transistor architecture with diagonally connected pixels for CMOS image sensors  

Microsoft Academic Search

We have developed a pixel unit for CMOS image sensors (CISs) that has a shared transistor architecture with diagonally connected pixels. This pixel unit is composed of four photodiodes and seven transistors. It has a pixel size of 2.5-mum square. The transistors were designed using 0.18-micron aluminum process technology. Shared diffusion for reading signal electrons occurs between the corners of

Yoshiharu Kudoh; Fumihiko Koga; Takashi Abe; Haruyuki Taniguchi; Maki Sato; Hiroaki Ishiwata; Susumu Ooki; Ryoji Suzuki; Hiroyuki Mori

2007-01-01

335

A 0.18?m CMOS 10-6 lux bioluminescence detection system-on-chip  

Microsoft Academic Search

A chip comprising a 8x16 pseudo-differential pixel array, 128-channel 13b ADC and column-level DSP is fabricated in a 0.18?m CMOS process. Detection of 10-6lux at 30s integration time is achieved via on-chip background subtraction, correlated multiple sampling and averaged 128 13b digitizations\\/readout. The IC is 25mm2 and contains 492k transistors.

H. Eltoukhy; K. Salama; A. El Gamal; M. Ronaghi; R. Davis

2004-01-01

336

GaN-Based Power LEDs With CMOS ESD Protection Circuits  

Microsoft Academic Search

A power light-emitting diode (LED) module has been successfully designed and demonstrated by combining GaN-based power LEDs with CMOS electrostatic discharge (ESD) protection circuits through a flip-chip process. It was found that we could enhance the power LED output intensity by 20% by using the flip-chip technology. Lifetimes of flip-chip power LEDs were also found to be better. It was

J. J. Horng; Y. K. Su; S. J. Chang; W. S. Chen; S. C. Shei

2007-01-01

337

Sub-quarter micron Si-gate CMOS with ZrO2 gate dielectric  

Microsoft Academic Search

MOSFETs with a zirconium dioxide (ZrO2) gate dielectric and poly-silicon gate were fabricated using a low temperature CMOS process. Well-behaved transistor characteristics were obtained for devices with sizes of 14 ?m×1.4 ?m or smaller. Devices 14 ?m×14 ?m or larger were found to be nonfunctional due to the formation of Zr-silicide at the polySi-gate\\/Zr02 interface. In this paper, we present

C. Hobbs; L. Dip; K. Reid; D. Gilmer; R. Hegde; T. Ma; B. Taylor; B. Cheng; S. Samavedam; H. Tseng; D. Weddington; F. Huang; D. Farber; M. Schippers; M. Rendon; L. Prabhu; R. Rai; S. Bagchi; J. Conner; S. Backer; F. Dumbuya; J. Locke; D. Workman; P. Tobin

2001-01-01

338

Current status of CMOS low voltage and low power wireless IC designs  

Microsoft Academic Search

This paper surveys recent research on CMOS low voltage and low power IC designs for wireless applications. Advancements and\\u000a challenges in using nanometer IC processes are addressed, and the impacts of device scaling on wireless systems are discussed.\\u000a Recent advances in device technologies and system architectures are presented. State-of-the-art low power wireless systems,\\u000a both from academia and from industry, are

Tommy K. Tsang; Mourad N. El-Gamal; Krzysztof Iniewski; Kenneth A. Townsend; James W. Haslett; Yanjie Wang

2007-01-01

339

Industrial CMOS technology for the integration of optical metrology systems (photo-ASICs)  

Microsoft Academic Search

With 'photo-ASKS' comprlsmg hght-sensitive structures, hght-emmmg devices and analog and chgtal clrcults, complete optlcal metrology systems can be Integrated on a smgle chip We report the reahzatlon of key components of such photo-ASICs usmg an mdustrual IC CMOS process We achieve photodlodes with an external quantum efficiency of 50-80% m the visible spectrum and posItIon-sensltlve devices (PSDs) with a spatial

J. Kramer; P Seltz; H. Baltes

1992-01-01

340

A 1.5-V, 1.5GHz CMOS low noise amplifier  

Microsoft Academic Search

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-?m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis

Derek K. Shaeffer; Thomas H. Lee

1997-01-01

341

Thermally tunable SOI CMOS photonics circuits  

NASA Astrophysics Data System (ADS)

Ring waveguide resonating structures with high quality factors are the key components in the silicon photonics portfolio boosting up its functionality and circuit performance. Due to a number of manufacturing reasons their peak wavelengths are often prone to deviate from designed values. In order to keep the ring resonator operating as specified, its peak wavelength then needs to be corrected in a reliable and power efficient way. We demonstrate the performance of the thermally tunable mux/demux filter ring structures fabricated in the commercial 130 nm SOI CMOS line.

Shubin, Ivan; Zheng, Xuezhe; Thacker, Hiren; Yao, Jin; Costa, Joannes; Luo, Ying; Li, Guoliang; Krishnamoorthy, Ashok V.; Cunningham, John E.; Pinguet, Thierry; Mekis, Attila

2010-02-01

342

Monolithic CMOS imaging x-ray spectrometers  

NASA Astrophysics Data System (ADS)

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15?m, high resistivity custom (~30k?-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16?m pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40?V/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9?m epitaxial silicon and have a 1k by 1k format. They incorporate similar 16?m pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

343

Nanoscale Materials and Structures for CMOS Devices  

NSDL National Science Digital Library

This presentation was given at the Arizona Nanotechnology Conference in March of 2008 by Dr. Stefan Zollner, Freescale Semiconductor, USA. The focus is on problems with planar CMOS and their solutions. These solutions consist of: SOI or FINFET to reduce source and drain leakage, high mobility channel materials to increase drive current, new silicide materials to reduce source and drain contact resistance, metal oxides with high dielectric constants to reduce gate leakage and metal gate electrodes to reduce gate depletion. Overall, the presentation is filled with images and diagrams allowing it to flow easily. This is an excellent resource for anyone looking to learn more about nanotechnology and its applications.

Zollner, Stefan

2008-10-27

344

The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays  

PubMed Central

Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

2014-01-01

345

Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I\\/Sub DDQ\\/ Testing  

Microsoft Academic Search

A rapid failure analysis method for high-density CMOS static RAMs (SRAMs) that uses realistic defect modeling and the results of functional and IDDQ testing is presented. The key to the method is the development of a defect-to-signature vocabulary through inductive fault analysis. Results indicate that the method can efficiently debug the multimegabit-memory manufacturing process

Samir Naik; Frank Agricola; Wojciech Maly

1993-01-01

346

3D Hall probe integrated in 0.35 ?m CMOS technology for magnetic field pulses measurements  

Microsoft Academic Search

This paper presents a 3 dimensional magnetometer based on Hall effect sensors integrated without any post processing in a standard low cost 0.35 mum CMOS technology. The system is dedicated to magnetic pulses measurements under a strong static field. Two vertical Hall devices (VHD) are sensitive to the components of the magnetic field oriented in the plane of the chip,

Joris Pascal; Luc Hébrard; Vincent Frick; Jean-Philippe Blondé

2008-01-01

347

Selection and modeling of integrated RF varactors on a 0.35-?m BiCMOS technology  

Microsoft Academic Search

Integrated varactors are becoming a common feature for many RF designs and in particular RF voltage controlled oscillators (VCOs). Optimization of the quality of both the inductor and the varactor from the VCO core is essential. This work details the characterization and optimization of a number of varactor types available on a typical submicron BiCMOS process. Engineering of the bottom

Sean C. Kelly; James A. Power; M. O'Neill

2004-01-01

348

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS Rajani Kuchipudi and Hamid Mahmoodi  

E-print Network

faster, leading to faster chips without having to shrink the size of transistors [1,2]. Thus, device in CMOS technology. Traditionally, silicon straining is applied in a similar ad-hoc manner to the whole in a predictive 45nm process technology, the proposed straining solution enhances circuit performance by 15

Mahmoodi, Hamid

349

A CMOS 500MHz continuous-time fourth order 0.05degree equiripple linear phase filter with automatic tuning  

E-print Network

at such high frequencies, has also been designed. The inaccuracies of the filter are compensated by using a simple automatic tuning system. The design is fabricated in 0.35 µ TSMC CMOS process technology. The design was simulated in Cadence using... Implementation......................................................... 17 III DESIGN OF SUITABLE OTA......................................................................... 19 A. Design Considerations for High Frequency Applications...

Pandey, Pankaj

2004-09-30

350

Power conserving CMOS reference voltage source  

SciTech Connect

This patent describes a power-conserving CMOS reference voltage generation circuit comprising first (101) and second (101') parallel reference voltage sources, coupled to a common ENABLE input, and having a common reference voltage output node (101''), each source including a first, p-channel (102,102') and a second, n-channel (103,103') CMOS transistor series-connected between Vcc and ground. The first and second transistors have respective gates connected at a common gate node (G, G') and respective drains connected to a common drain node (D, D'), characterized in that: the second reference voltage source (101') is of relatively large capacity compared to the first source (101), means (173,107'), responsive to a rising signal edge at the ENABLE input, are provided for temporarily enabling the second source (101'). This shortens the time required to drive the reference voltage at the output node (101'') to a desired level, i.e. enhancing the slew rate of the node, and means (190-194) are provided for interconnecting the common gate nodes (G,G') the common drain nodes (D,D'), and the common output reference voltage output node (101'') in response to a high signal on the ENABLE input and for isolating the nodes from one another in response to a low signal on the ENABLE input, thereby conserving power.

Lee, R.D.

1986-12-09

351

3D integration of planar crossbar memristive devices with CMOS substrate  

NASA Astrophysics Data System (ADS)

Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing.

Lin, Peng; Pi, Shuang; Xia, Qiangfei

2014-10-01

352

3D integration of planar crossbar memristive devices with CMOS substrate.  

PubMed

Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. PMID:25224779

Lin, Peng; Pi, Shuang; Xia, Qiangfei

2014-10-10

353

Integrated NiSi waveguide heaters for CMOS-compatible silicon thermo-optic devices.  

PubMed

We report the performance of NiSi-based heaters integrated with submicrometer silicon waveguides. The heaters were fabricated using a standard complementary metal-oxide-semiconductor (CMOS) silicidation process on a thin silicon slab laterally connected with a silicon rib waveguide. The intrinsic properties of such NiSi waveguide heaters were characterized by using them as thermo-optic phase shifters in a Mach-Zehnder interferometer. The power consumption P(pi) for obtaining a pi phase shift was measured to be as low as 20 mW, using CMOS-compatible drive voltages. The time constant of the thermo-optic response was less than 2.8 mus. Simulations suggest that a further reduction in the power consumption P(pi) is feasible. PMID:20364201

Van Campenhout, Joris; Green, William M J; Assefa, Solomon; Vlasov, Yurii A

2010-04-01

354

Fixed-gain CMOS differential amplifiers with no external feedback for a wide temperature range  

NASA Astrophysics Data System (ADS)

We present original CMOS amplifiers designed for the DC to 10 MHz frequency range and operating in the 70-380 K temperature range. Aimed applications concern readout circuitry to be associated with THz bolometric pixels (either high- Tc superconducting or uncooled semiconducting), which require accuracy, low noise and low power consumption. Two designs are described that both exhibit high fixed-gain (40 dB) in a feedback-free architecture, which is based on a new low-transconductance composite transistor for an accurate control of this gain. Both amplifiers have been realized in a regular 0.35 ?m CMOS process and tested in the 4.2-380 K temperature range, exhibiting good agreement between designed and measured characteristics.

Michal, Vratislav; Klisnick, Geoffroy; Sou, Gérard; Redon, Michel; Kreisler, Alain J.; Dégardin, Annick F.

2009-11-01

355

A CMOS fifth-derivative Gaussian pulse generator for UWB applications  

NASA Astrophysics Data System (ADS)

A CMOS fifth-derivative Gaussian pulse generator is presented for ultra-wideband (UWB) applications. The design exhibits low power consumption, low circuit complexity, and a precise pulse shape to inherently comply with the FCC spectrum mask for indoor UWB applications without the need for a filter. The pulse generator is implemented with a 1.8-V, 0.18-?m CMOS process. The small core chip size of the pulse generator is only 217 × 121 ?m2 because of its all digital circuit design. The measured fifth-derivative Gaussian pulse has a peak-to-peak amplitude of 158 mV and a pulse width of 800 ps. The average power dissipation is 0.6 mW with a pulse repetition frequency of 50 MHz.

Jin, He; Jiang, Luo; Hao, Wang; Sheng, Chang; Qijun, Huang; Yueping, Zhang

2014-09-01

356

CMOS 155-Mb/s optical wireless transmitter for indoor networks  

NASA Astrophysics Data System (ADS)

12 A 155 Mb/s CMOS LED driver for low-cost optical wireless links is presented. The driver is realized in a 0.7 micrometers commodity mixed-signal CMOS process from Alcatel Microelectronics. The driver employs switching transistors which drive a current mirror to generate modulation current. The circuit also contains a controllable quiescent current source. The transmitter driver incorporates two novel features: adjustable current peaking and adjustable charge extraction. These functions are implemented with the use of original timing generators. Simulations indicate that the design achieves output rise times and fall times of less than 2 ns. Other design parameters were selected to suit the requirements of the InP resonant cavity LED that was developed for this application.

Holburn, David M.; Mears, Robert J.; Samsudin, Rina J.; Joyner, Valencia M.; Lalithambika, Vinod A.

2001-02-01

357

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain  

PubMed Central

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4?GHz CMOS power amplifier with a 0.18??m RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32?dBm. The designed chip size is 1.4 × 0.6?mm2. PMID:25045755

2014-01-01

358

X-Ray Detector with CMOS Sensor Camera Application of Calcium Denisty Measurement  

Microsoft Academic Search

This paper presented a design of an x-ray-detector using CMOS image sensor. The main components consist of CMOS sensor, taper fiber optic, and image intensifier screen. CMOS sensor offers various advantages including miniature-sized, low power consumption and cost effective. CMOS-based digital camera becomes hence very demanding due to its potential application in multimedia and information technology. To apply the CMOS

Y. Pititheerapab; T. Chanmalueang; T. Rerksngaem; C. Kitipol; C. Pintavirooj

2006-01-01

359

CMOS-compatible fabrication, micromachining, and bonding strategies for silicon photonics  

NASA Astrophysics Data System (ADS)

The adoption of optical technologies by high-volume consumer markets is severely limited by the cost and complexity of manufacturing complete optical transceiver systems. This is in large part because "boutique" semiconductor fabrication processes are required for III-V lasers, modulators, and photodetectors; furthermore, precision bonding and painstaking assembly are needed to integrate or assemble such dissimilar devices and materials together. On the other hand, 200mm and 300mm silicon process technology has been bringing ever-increasing computing power to the masses by relentless cost reduction for several decades. Intel's silicon photonics program aims to marry this CMOS infrastructure and recent developments in MEMS manufacturing with the burgeoning field of microphotonics to make low cost, high-speed optical links ubiquitous. In this paper, we will provide an overview of several aspects of silicon photonics technology development in a CMOS fabrication line. First, we will describe fabrication strategies from the MEMS industry for micromachining silicon to create passive optical devices such as mirrors, waveguides, and facets, as well as alignment features. Second, we will discuss some of the challenges of fabricating hybrid III-V lasers on silicon, including such aspects as hybrid integration of InP-based materials with silicon using various bonding methods, etching of InP films, and contact formation using CMOS-compatible metals.

Heck, John; Jones, Richard; Paniccia, Mario J.

2011-02-01

360

Leakage Control of Digital Circuits Using McCMOS Technique  

NASA Astrophysics Data System (ADS)

In Nano Scale CMOS design, non-minimum length transistors offer the possibility of achieving excellent leakage control without the disadvantages of other known leakage control techniques. Preliminary analysis indicate that one can expect leakage reduction by a factor of at least 100 (and possibly orders of magnitude higher) with only modest, increase in circuit area and switched capacitance. This paper briefly reviews related leakage control techniques, describes the Multiple Channel CMOS (McCMOS) technique, by using 45 nm MOS and presents simulation results that are indicative of the performance of the technique. This technique will be very much useful for designing low leakage high performance ALU units.

Kayal, Dibyendu; Dandapat, Anup; Sarkar, C. K.

2010-10-01

361

A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies  

NASA Astrophysics Data System (ADS)

Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

Schmitz, A.; Tielert, R.

2005-05-01

362

Spin blockade in a triple silicon quantum dot in CMOS technology  

NASA Astrophysics Data System (ADS)

We study the spin blockade (SB) phenomenon by quantum transport in a triple quantum dot made of two single electron transistors (SET) on a CMOS platform separated by an implanted multiple donor quantum dot [1]. Spin blockade condition [2] has been used in the past to realize single spin localization and manipulation in GaAs quantum dots [3]. Here, we reproduce the same physics in a CMOS preindustrial silicon quantum device. Single electron quantum dots are connected via an implanted quantum dot and exhibit SB in one current direction. We break the spin blockade by applying a magnetic field of few tesla. Our experimental results are explained by a theoretical microscopic scheme supported by simulations in which only some of the possible processes through the triple quantum dot are spin blocked, according to the asymmetry of the coupling capacitances with the control gates and the central dot. Depending on the spin state, the SB may be both lifted and induced. Spin control in CMOS quantum dots is a necessary condition to realize large fabrication of spin qubits in some solid state silicon quantum device architectures.[0pt] [1] Pierre et al., Appl. Phys. Lett., 95, 24, 242107 (2009); [2] Liu et al., Phys. Rev. B 77, 073310 (2008); [3] Koppens et al., Nature 442, 766-771 (2006)

Prati, E.; Petretto, G.; Belli, M.; Mazzeo, G.; Cocco, S.; de Michielis, M.; Fanciulli, M.; Guagliardo, F.; Vinet, M.; Wacquez, R.

2012-02-01

363

Designing and implementing a miniature CMOS imaging system with USB interface  

NASA Astrophysics Data System (ADS)

Although CMOS cameras with USB interface are popular, their sizes are not small enough and working lengths are not that long enough when used as industrial endoscope. Here we present a small-sized image acquisition system for high-definition industrial electronic endoscope based on USB2.0 high-speed controller, which is composed of a 1/6 inch CMOS image sensor with resolution of 1 Megapixels. Signals from the CMOS image sensor are put into computer through the USB interface using the slave FIFO mode for processing, storage and display. LVDS technology is used for image data stream transmission between the sensor and USB controller to realize a long working distance, high signal integrity and low noise system. The maximum pixel clock runs at 48MHz to support for 30 fps for QSXGA mode or15 fps for SXGA mode and the data transmission rate can reach 36 megabytes per second. The imaging system is simple in structure, low-power, low-cost and easy to control. Based on multi-thread technology, the software system which realizes the function of automatic exposure, automatic gain, and AVI video recording is also designed.

Yao, Chenyun; Wang, Liqiang; Yuan, Bo; Xu, Jin

2012-11-01

364

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip  

NASA Astrophysics Data System (ADS)

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

365

CMOS digital pixel sensors: technology and applications  

NASA Astrophysics Data System (ADS)

CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

Skorka, Orit; Joseph, Dileepan

2014-04-01

366

Latchup in CMOS devices from heavy ions  

NASA Technical Reports Server (NTRS)

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.; Nichols, D. K.

1983-01-01

367

On-chip polarizer on image sensor using advanced CMOS technology  

NASA Astrophysics Data System (ADS)

The structures in advanced complementary metal-oxide-semiconductor (CMOS) integrated circuit technology are in the range of deep-submicron. It allows designing and integrating nano-photonic structures for the visible to near infrared region on a chip. In this work, we designed and fabricated an image sensor with on-pixel metal wire grid polarizers by using a 65-nm standard CMOS technology. It is known that the extinction ratio of a metal wire grid polarizer is increased with decrease in the grid pitch. With the metal wire layers of the 65-nm technology, the grid pitch sufficiently smaller than the wavelengths of visible light can be realized. The extinction ratio of approximately 20 dB has been successfully achieved at a wavelength of 750 nm. In the CMOS technologies, it is usual to include multiple metal layers. This feature is also useful to increase the extinction ratio of polarizers. We designed dual layer polarizers. Each layer partially reflects incident light. Thus, the layers form a cavity and its transmission spectrum depends on the layer position. The extinction ratio of 19.2 dB at 780 nm was achieved with the grid pitch greater than the single layer polarizer. The high extinction ratio is obtained only red to near infrared region because the fine metal layers of deepsubmicron standard CMOS process is usually composed of Cu. Thus, it should be applied for measurement or observation where wide spectrum is not required such as optical rotation measurement of optically active materials or electro-optic imaging of RF/THz wave.

Sasagawa, Kiyotaka; Wakama, Norimitsu; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2014-03-01

368

A 512×512 CMOS Monolithic Active Pixel Sensor with integrated ADCs for space science  

NASA Astrophysics Data System (ADS)

In the last few years, CMOS sensors have become widely used for consumer applications, but little has been done for scientific instruments. In this paper we present the design and experimental characterisation of a Monolithic Active Pixel Sensor (MAPS) intended for a space science application. The sensor incorporates a 525×525 array of pixels on a 25 ?m pitch. Each pixel contains a detector together with three transistors that are used for pixel reset, pixel selection and charge-to-voltage conversion. The detector consists of four n-well/p-substrate diodes combining optimum charge collection and low noise performance. The array readout is column-parallel with adjustable gain column amplifiers and a 10-bit single slope ADC. Data conversion takes place simultaneously for all the 525 pixels in one row. The ADC slope can be adjusted in order to give the best dynamic range for a given brightness of a scene. The digitised data are output on a 10-bit bus at 3 MHz. An on-chip state machine generates all of the control signals needed for the readout. All of the bias currents and voltages are generated on chip by a DAC that is programmable through an I 2C compatible interface. The sensor was designed and fabricated on a standard 0.5 ?m CMOS technology. The overall die size is 16.7 mm×19.9 mm including the associated readout electronics and bond pads. Preliminary test results show that the full-scale design works well, meeting the Star Tracker requirements with less than 1-bit noise, good linearity and good optical performance.

Prydderch, M. L.; Waltham, N. J.; Turchetta, R.; French, M. J.; Holt, R.; Marshall, A.; Burt, D.; Bell, R.; Pool, P.; Eyles, C.; Mapson-Menard, H.

2003-10-01

369

Fabrication and simulation of CMOS-compatible photodiodes  

E-print Network

CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

DiLello, Nicole Ann

2008-01-01

370

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies  

E-print Network

CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

Brooks, Lane Gearle, 1975-

2008-01-01

371

Failures Of CMOS Devices At Low Radiation-Dose Rates  

NASA Technical Reports Server (NTRS)

Method for obtaining approximate failure-versus-dose-rate curves derived from experiments on failures of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated circuits irradiated by Co60 and Cs137 radioactive sources.

Goben, Charles A.; Price, William E.

1990-01-01

372

Strain-engineered CMOS-compatible Ge photodetectors  

E-print Network

The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

Cannon, Douglas Dale, 1974-

2004-01-01

373

A study of CMOS technologies for image sensor applications  

E-print Network

CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

Wang, Ching-Chun, 1969-

2001-01-01

374

III-V CMOS: What have we learned from HEMTs?  

E-print Network

The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic performance has recently come into question. An end to Moore's Law threatens to bring to a halt the microelectronics revolution: ...

del Alamo, Jesus A.

375

CMOS front-end amplifier for broadband DTV tuner  

E-print Network

In this work, the design of a CMOS broadband low noise amplifier with inherent high performance single-to-differential conversion is presented. These characteristics are driven by the double quadrature single conversion digital television tuner...

Zhang, Guang

2005-08-29

376

A wide-dynamic-range time-based CMOS imager  

E-print Network

This thesis describes a novel dual-threshold time-based current sensing algorithm suitable for use in wide-dynamic-range CMOS imagers. A prototype 150 x 256 pixel imager employing this algorithm experimentally achieves ...

O'Halloran, Micah G. (Micah Galletta), 1978-

2008-01-01

377

Scintillator and CMOS APS Imager for Radiography Conditions  

Microsoft Academic Search

We evaluated X-ray image performance for several scintillators and a CMOS APS imager by both diagnostic radiography and mammography conditions. Commercially available scintillators such as Lanex screen, needle structured CsI (Tl), and fiber optic structured CsI (Tl) were coupled with a CMOS APS imager. The X-ray machines used in this study were fixed tube voltage of 80 kVp and variable

Kwang Hyun Kim; Young Soo Kim

2008-01-01

378

CMOS Image Sensors: Electronic Camera On A Chip  

NASA Technical Reports Server (NTRS)

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Fossum, E. R.

1995-01-01

379

Deep submicron CMOS based on silicon germanium technology  

Microsoft Academic Search

The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 ?m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si\\/SiO2 interface scattering by the

A. G. O'Neill; D. A. Antoniadis

1996-01-01

380

A study of phase noise in CMOS oscillators  

Microsoft Academic Search

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative

Behzad Razavi

1996-01-01

381

A novel CMOS SRAM feedback element for SEU environments  

SciTech Connect

A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells.

Verghese, S.; Wortman, J.J.; Kerns, S.E.

1987-12-01

382

Burn-In Stress Test of Analog CMOS ICs  

Microsoft Academic Search

With the successful development of EVoSTA (Extreme-Voltage Stress Test for Analog CMOS ICs), this paper investigated whether the extreme-temperature burn-in stress test is properly applied for enhancing the gate-oxide reliability of mixed-signal\\/analog CMOS ICs. Burn-in is an effective screening method used in predicting, achieving, and enhancing field reliability of ICs. Today, almost all IC manufacturers perform 100% burn-in for various

Chin-long Wey; Meng-yao Liu

2004-01-01

383

A New High-Filling-Factor CMOS-Compatible Thermopile  

Microsoft Academic Search

To reach a high fill factor, a new CMOS-compatible thermopile was designed and fabricated. The floating membrane of the thermopile that we designed was formed by a T-shape anisotropic etching window with a minimum etching area. The design and fabrication of thermopile sensors are realized by using 1.2-mum CMOS IC technology combined with a subsequent anisotropic front-side etching. The proposed

Shu-Jung Chen; Chih-Hsiung Shen

2007-01-01

384

Sensing temperature in CMOS circuits for Thermal Testing  

Microsoft Academic Search

Abstract Temperature,is a ,physical ,magnitude ,that can ,be used,as an ,observable ,quantity ,for ,IC testing purposes. The authors ,discuss ,in this ,paper ,the suitability of two ,temperature ,measuring ,strategies applicable to standard ,CMOS integrated circuits: a laser interferometer ,and ,a differential ,fully CMOS built-in temperature,sensor. Keywords: Thermal testing, temperature sensors, analysis failure, built-in self test 1. Introduction:Thermal testing Thermal,testing comprises

Josep Altet; Antonio Rubio; M. Amine Salhi; J. L. Gálvez; Stefan Dilhaire; Ashish Syal; André Ivanov

2004-01-01

385

CMOS Amperometric Instrumentation and Packaging for Biosensor Array Applications  

Microsoft Academic Search

An integrated CMOS amperometric instrument with on-chip electrodes and packaging for biosensor arrays is pre- sented. The mixed-signal integrated circuit supports a variety of electrochemical measurement techniques including linear sweep, constant potential, cyclic and pulse voltammetry. Implemented in CMOS, the chip dissipates 22.5 mW for a 200 kHz clock. The highly programmable chip provides a wide range of user-controlled stimulus

Lin Li; Xiaowen Liu; Waqar A. Qureshi; Andrew J. Mason

2011-01-01

386

A low voltage CMOS low drop-out voltage regulator  

Microsoft Academic Search

A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer

Salma Ali Bakr; Tanvir Ahmad Abbasi; Mohammas Suhaib Abbasi; Mohamed Samir Aldessouky; Mohammad Usaid Abbasi

2009-01-01

387

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

2012-06-07

388

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits  

SciTech Connect

This paper describes a methodology for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-{mu}m n-well CMOS 4k-bit test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 {mu}m was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 Mev cm{sup 2}/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV cm{sup 2}/mg was determined.

Blaes, B.R.; Soli, G.A.; Buehler, M.G. (Jet Propulsion Lab., Pasadena, CA (United States))

1991-12-01

389

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits  

NASA Technical Reports Server (NTRS)

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Blaes, B. R.; Soli, G. A.; Buehler, M. G.

1991-01-01

390

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor  

PubMed Central

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18??m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18??m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

391

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.  

PubMed

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18? ?m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 ?m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

392

Label-free immunodetection with CMOS-compatible semiconducting nanowires  

NASA Astrophysics Data System (ADS)

Semiconducting nanowires have the potential to function as highly sensitive and selective sensors for the label-free detection of low concentrations of pathogenic microorganisms. Successful solution-phase nanowire sensing has been demonstrated for ions, small molecules, proteins, DNA and viruses; however, `bottom-up' nanowires (or similarly configured carbon nanotubes) used for these demonstrations require hybrid fabrication schemes, which result in severe integration issues that have hindered widespread application. Alternative `top-down' fabrication methods of nanowire-like devices produce disappointing performance because of process-induced material and device degradation. Here we report an approach that uses complementary metal oxide semiconductor (CMOS) field effect transistor compatible technology and hence demonstrate the specific label-free detection of below 100 femtomolar concentrations of antibodies as well as real-time monitoring of the cellular immune response. This approach eliminates the need for hybrid methods and enables system-scale integration of these sensors with signal processing and information systems. Additionally, the ability to monitor antibody binding and sense the cellular immune response in real time with readily available technology should facilitate widespread diagnostic applications.

Stern, Eric; Klemic, James F.; Routenberg, David A.; Wyrembak, Pauline N.; Turner-Evans, Daniel B.; Hamilton, Andrew D.; Lavan, David A.; Fahmy, Tarek M.; Reed, Mark A.

2007-02-01

393

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology  

Microsoft Academic Search

In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inductively degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P-1dBin) and

MinSuk Koo; Hakchul Jung; Ickhyun Song; Hee-Sauk Jhon; Hyungcheol Shin

2008-01-01

394

Broadband Root-Mean-Square Detector in CMOS for On-Chip Measurements of Millimeter-Wave Voltages  

Microsoft Academic Search

A root-mean-square Schottky diode detector for estimating millimeter-wave (80–110 GHz) signal voltage using dc or low-frequency measurements for debugging and self-testing is demonstrated. The detector is realized in a 45-nm CMOS process without any process modifications. The detector gain at 30-$ \\\\hbox{mV}_{\\\\rm rms}$ input voltage is 11 $\\\\hbox{V}^{-1}$ . The insertion loss is less than 0.2 dB, and the flatness

Chuan Lee; Wooyeol Choi; Ruonan Han; Hisashi Shichijo; Kenneth K. O

2012-01-01

395

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS  

NASA Technical Reports Server (NTRS)

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Trotter, J. D.

1982-01-01

396

Analysis of USJ formation with combined RTA/laser annealing conditions for 28 nm high-k/metal gate CMOS technology using advanced TCAD for process and device simulation  

NASA Astrophysics Data System (ADS)

TCAD process and device simulations are used to gain physical understanding for the integration of laser-annealed junctions into a 28 nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (lsa) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJs). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.

Bazizi, E. M.; Zaka, A.; Benistant, F.

2013-05-01

397

Manufacture and Characterization of High Q-Factor Inductors Based on CMOS-MEMS Techniques  

PubMed Central

A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively. PMID:22163726

Yang, Ming-Zhi; Dai, Ching-Liang; Hong, Jin-Yu

2011-01-01

398

Passive radiation detection using optically active CMOS sensors  

NASA Astrophysics Data System (ADS)

Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and ? particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

Dosiek, Luke; Schalk, Patrick D.

2013-05-01

399

Etch challenges for DSA implementation in CMOS via patterning  

NASA Astrophysics Data System (ADS)

This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

Pimenta Barros, P.; Barnola, S.; Gharbi, A.; Argoud, M.; Servin, I.; Tiron, R.; Chevalier, X.; Navarro, C.; Nicolet, C.; Lapeyre, C.; Monget, C.; Martinez, E.

2014-03-01

400

Integrating silicon photonic interconnects with CMOS: Fabrication to architecture  

NASA Astrophysics Data System (ADS)

While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

Sherwood, Nicholas Ramsey

401

Modeling the current behavior of the digital BiCMOS gate  

E-print Network

This thesis describes a piece-wise approximation of transient current response of the digital BiCMOS gate. Based on the detailed transient analysis of the conventional digital BiCMOS gate, a new circuit model for digital BiCMOS gate is derived which...

Tang, Zhilong

2012-06-07

402

N3ASICs: Designing nanofabrics with fine-grained CMOS integration  

Microsoft Academic Search

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules in order to build a reliable nanowire- CMOS fabric called N 3 ASIC with no new manufacturing constraints added. Active devices are formed on a dense uniform semiconductor nanowire array and standard area distributed pins\\/vias; metal interconnects route the signals in 3D. CMOS

Pavan Panchapakeshan; Pritish Narayanan; Csaba Andras Moritz

2011-01-01

403

Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess  

E-print Network

Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess YNGVAR BERG I. Innhold GJ ennomgang av CMOS prosess, tverrsnitt av nMOS- og pMOS transistor og tverrsnitt av CMOS inverter. Enkel forklaring p°a begreper som akkumulasjon, deplesjon og inver- sjon. Enkel fysikalsk forklaring p°a transistor

Sahay, Sundeep

404

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors  

PubMed Central

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed. PMID:22389592

Lu, Guo-Neng; Tournier, Arnaud; Roy, Francois; Deschamps, Benoit

2009-01-01

405

Silicon MCM substrates for integration of III-V photonic devices and CMOS IC`s  

SciTech Connect

The progress made in advanced packaging development at Sandia National Laboratories for integration of III-V photonic devices and CMOS IC`s on Silicon MCM substrates for planar aid stacked applications will be reported. Studies to characterize precision alignment techniques using solder attach materials compatible with both silicon IC`s and III-V devices will be discussed. Examples of the use of back-side alignment and IR through-wafer inspection will be shown along with the extra processing steps that are used. Under bump metallurgy considerations are also addressed.

Seigal, P.; Carson, R.; Flores, R.; Rose, B.

1993-07-01

406

Shared transistor architecture with diagonally connected pixels for CMOS image sensors  

NASA Astrophysics Data System (ADS)

We have developed a pixel unit for CMOS image sensors (CISs) that has a shared transistor architecture with diagonally connected pixels. This pixel unit is composed of four photodiodes and seven transistors. It has a pixel size of 2.5-?m square. The transistors were designed using 0.18-micron aluminum process technology. Shared diffusion for reading signal electrons occurs between the corners of two photodiodes. The advantages of this layout include a long amplifier gate length and a large photodiode area.

Kudoh, Yoshiharu; Koga, Fumihiko; Abe, Takashi; Taniguchi, Haruyuki; Sato, Maki; Ishiwata, Hiroaki; Ooki, Susumu; Suzuki, Ryoji; Mori, Hiroyuki

2007-02-01

407

A hybrid CMOS-microfluidic contact imaging microsystem  

NASA Astrophysics Data System (ADS)

A hybrid CMOS/Microfluidic microsystem is presented. The microsystem integrates a soft polymer microfluidic network with a 64x128 pixel imager fabricated in low-cost standard 0.35 micron CMOS technology. The multiple microfluidic channels facilitate in-situ photochemical reactions of analytes and their detection directly on the surface of the CMOS photosensor array. The promixity between the analyte and the photosensor enhances the microsystem sensitivity, thus requiring only microliter volumes of the sample. Circuit techniques such as pixel binning and a two transistor reset path technique are employed to improve the imager sensitivity. The integrated microsystem is validated in on-chip chemiluminescence detection of luminol for the two microfluidic network prototypes designed.

Singh, Ritu Raj; Leng, Lian; Guenther, Axel; Genov, Roman

2009-08-01

408

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications  

NASA Astrophysics Data System (ADS)

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

409

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications.  

PubMed

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 ?m long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association. PMID:25288224

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-31

410

Operation and biasing for single device equivalent to CMOS  

DOEpatents

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

411

A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application  

Microsoft Academic Search

A low-power digital signal processor (DSP) is the key component for battery-driven mobile phone equipment since a vast amount of data needs to be processed for multimedia use. Reduced supply voltage is a direct approach to power reduction. This 1 V DSPLSI with 26 MOPS and 1.1 mW\\/MOPS performance adopts a multi-threshold-voltage CMOS (MTCMOS) technique. A small embedded power-management processor

S. Mutoh; S. Shigematsu; Y. Matsuya; H. Fukuda; J. Yamada

1996-01-01

412

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification  

NASA Technical Reports Server (NTRS)

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

413

Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices  

SciTech Connect

The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data.

Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

1984-12-01

414

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies  

Microsoft Academic Search

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps

Balaji Narasimham; Bharat L. Bhuva; Ronald D. Schrimpf; Lloyd W. Massengill; Matthew J. Gadlage; Oluwole A. Amusan; William Timothy Holman; Arthur F. Witulski; William H. Robinson; Jeffrey D. Black; Joseph M. Benedetto; Paul H. Eaton

2007-01-01

415

A 5.8 GHz fully integrated low power low phase noise CMOS LC VCO for WLAN applications  

Microsoft Academic Search

A fully integrated low power and low phase noise 5.8 GHz VCO is designed and fabricated in standard 0.24 ?m single-poly, 5-metal digital CMOS process. The VCO-core draws 2 mA of current from a 2.5 V supply. Measured phase noise at 1 MHz offset from the center frequency is -112 dBc\\/Hz. It has a tuning range of 810 MHz with

J. Bhattachaijee; D. Mukheijee; Edward Gebara; Sebastien Nuttinck; Joy Laskar

2002-01-01

416

A new approach for CMOS-compatible fabrication of cantilever\\/tip systems for probe-storage applications  

Microsoft Academic Search

In this work an original approach for the fabrication of the mechanical part of the Millipede, a MEMS-based scanning-probe data storage system, is reported. It allows the integration of both mechanical and electronic parts on the same wafer, by using CMOS-compatible processes. The proposed approach is based on the selective etching of p-type silicon, used as a sacrificial layer, with

G. M. Lazzerini; S. Surdo; G. Barillaro

2009-01-01

417

Electromagnetically compatible CMOS auto-balanced current sensor for highly integrated power control System-On-Chip  

Microsoft Academic Search

This paper describes the design and prototyping of an auto-balanced contactless current sensor in standard Complementary Metal–Oxide–Semiconductor (CMOS) technology, without any additional post-processing cost. The architecture includes two high-sensitivity Hall plates with differential amplification electronics. A high common mode rejection is insured by the integrated auto-balancing system based on the use of integrated coils. When a common current is applied

V. Frick; P. Poure; L. Hébrard; F. Anstotz; F. Braun

2007-01-01

418

Materials issues in the integration of magnetic structures on CMOS-MEMS  

NASA Astrophysics Data System (ADS)

A MEMS-based data storage is being developed at CMU for low power, high access speed and low cost. Multi magnetic heads and their actuators are proposed to be fabricated on top of CMOS and to be released with proper masking. We describe the development of a magnetic head process integrated with a CMOS-MEMS process for actuator fabrication. Process integration depends on an understanding of the structure-process-properties relationship of many different processes. Several materials problems were encountered and solved in the course of the process development. The experiment work and rationale for particular choices is discussed. Low stress (<25 MPa), magnetically soft films of permalloy (Ni 80Fe20) were deposited for a MEMS-based data storage application without significant plasma-induced substrate heating. Optimization of film properties was performed using a designed experiment, response surface methodology. The relationship between the results of the factorial experiment is explained based on Murayama's stripe domain theory. The properties of AMR sensors fabricated on structures released by the CMOS post process are characterized. The AMR sensor on the released MEMS structure functions properly and the MR head shows 0.4% MR change. According to our analysis of the required MR properties and its specification, the characteristics of TMR sensor, high intensity signal and low power consumption, well satisfy the requirement of MEMS-based data storage system. A TMR sensor has been built on our yoke type head. We have investigated the planarized surface with AFM for higher accuracy. The polishing mechanisms for oxide and permalloy are studied based on the materials corrosion theory using Pourbaix diagram. In addition, the uniformity of wafer and a cleaning process as a post CMP process were also studied. For simple fabrication processes, a photoresist layer was used as a side wall insulation which reduces process steps such as oxide or nitride deposition, lift-off and/or other additional etching processes. The sensor shows good tunneling I-V characteristics without shunting but it doesn't respond to the magnetic field. It is believed that the over oxidation would oxides the bottom electrode, permalloy, that ruins spin-preserved tunneling.

Min, Seungook

419

Delay modeling and glitch estimation for CMOS circuits  

E-print Network

DELAY MODELING AND GLITCH ESTIMATION FOR CMOS CIRCUITS A Thesis by YAN-CHYUAN SHIAU Submitted to the Graduate College of Texas A8rM University in partial fulfillment of the requirement for the degree of MASTER OF SCIENCE August 1988 Major... Subject: Electrical Engineering DELAY MODELING AND GLITCH ESTIMATION FOR CMOS CIRCUITS A Thesis by YAN-CHYUAN SHIAU Approved as to style and content by: An-Chang Deng (Chairman of Committee) Karan Watson (Member) I / l j j Stephen M. Morg...

Shiau, Yan-Chyuan

2012-06-07

420

A high performance 0.25 mu m CMOS technology  

Microsoft Academic Search

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. Cw=0.2 pF) delay per stage of 280 ps achieved (Weff\\/Leff=15 mu m\\/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m),

B. Davari; W. H. Chang; M. R. Wordeman; C. S. Oh; Y. Taur; K. E. Petrillo; D. Moy; J. J. Bucchignano; H. Y. Ng; M. G. Rosenfield; F. J. Hohn; M. D. Rodriguez

1988-01-01

421

Organic Field-Effect Transistors for CMOS Devices  

Microsoft Academic Search

\\u000a Organic field-effect transistors (OFETs) are the key elements of future low cost electronics such as radio frequency identification\\u000a tags. In order to take full advantage of organic electronics, low power consumption is mandatory, requiring the use of a complementary\\u000a metal oxide semiconductor (CMOS) like technique. To realize CMOS-devices p-type and n-type organic field-effect transistors\\u000a on one substrate have to be

Christian Melzer; Heinz von Seggern

2010-01-01

422

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays  

NASA Astrophysics Data System (ADS)

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2013-07-01

423

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays  

NASA Astrophysics Data System (ADS)

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

424

Carbon nanotube applications for CMOS back-end processing  

E-print Network

Carbon nanotubes are a recently discovered material with excellent mechanical, thermal, and electronic properties. In particular, they are potential ballistic transporters and are theorized to have thermal conductivities ...

Wu, Tan Mau, 1979-

2005-01-01

425

Improved color filter process for CCD and CMOS imagers  

Microsoft Academic Search

Several different methods exist for converting monochromatic solid-state imagers into color. One of the first techniques was to rotate a color filter wheel in front of the sensor for each exposure. More recently, high-definition cameras align three different sensors and separate the color signals using dichroic filters mounted on a prism. Yet another method, known as “on-chip” color filters, applies

H. Miller

1996-01-01

426

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.  

PubMed

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 ?m 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

427

Scalable production of sub-?m functional structures made of non-CMOS compatible materials on glass  

NASA Astrophysics Data System (ADS)

Biophotonic and Life Science applications often require non-CMOS compatible materials to be patterned with sub ?m resolution. Whilst the mass production of sub ?m patterns is well established in the semiconductor industry, semiconductor fabs are limited to using CMOS compatible materials. IMT of Switzerland has implemented a fully automated manufacturing line that allows cost effective mass manufacturing of consumables for biophotonics in substrate materials like D263 glass or fused silica and layer/coating materials like Cr, SiO2, Cr2O5, Nb2O5, Ta2O5 and with some restrictions even gold with sub-?m patterns. The applied processes (lift-off and RIE) offer a high degree of freedom in the design of the consumable.

Arens, Winfried

2014-03-01

428

sCMOS detector for imaging VNIR spectrometry  

NASA Astrophysics Data System (ADS)

The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

2013-09-01

429

Advanced SOI CMOS transistor technology for high performance microprocessors  

NASA Astrophysics Data System (ADS)

An overview of state of the art Silicon on Insulator CMOS transistors used for 65nm and 45nm volume manufacturing of microprocessors will be given. AMD's unique technology and transistor progression model as well as the key challenges to increase the power efficiency of microprocessor products will be described. For advanced SOI transistors stress engineering has become a standard feature since the 90nm technology node due to gate oxide scaling limitations [1]. Especially techniques which induce local strain such as compressive and tensile stressed over-layer films, embedded-SiGe, and stress memorization, are keys to enhance transistor and product performance. With optimization, the different stressors are highly compatible and additive to each other, improving PMOS and NMOS saturation drive currents by ca. 50% and 30%, respectively [2]. In addition to reducing the lateral and vertical device dimensions advanced (Laser or Flash) annealing has been applied [3]. These anneal processes yield an improved dopant activation for active and gate regions resulting in lower source-drain resistance and gate depletion without any additional diffusion. To achieve a ``high performance per watt'', technology and design optimization is required. Technology elements like SOI, stressors, multiple gate oxides needed hand-in-hand development with multiple core designs and power efficient microprocessor architectures. These techniques have been applied and optimized for 65nm and 45nm manufacturing. Future technology options, like strained silicon directly bonded on SOI, Si:C embedded SD and High K gate oxide will be discussed. [1] M. Horstmann, et al., IEDM 2005, p. 243 [2] A. Wei et al., VLSI 2007 [3] Th.Feudel et al., RTP Conference, Kyoto, 2006

Wiatr, Maciej

2008-03-01

430

Compact CMOS Camera Demonstrator (C3D) for Ukube-1  

NASA Astrophysics Data System (ADS)

The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

2011-09-01

431

A built-in SRAM for radiation hard CMOS pixel sensors dedicated to high energy physics experiments  

NASA Astrophysics Data System (ADS)

CMOS pixel sensors (CPS) are attractive candidates for charged particle tracking in high energy physics experiments. However, CPS chips fabricated with standard CMOS processes, especially the built-in SRAM IP cores, are not radiation hard enough for this application. This paper presents a radiation hard SRAM for improving the CPS radiation tolerance. The SRAM cell is hardened by increasing the static noise margin (SNM) and adding P+ guard rings in layout. The peripheral circuitry is designed by building a radiation-hardened logic library. The SRAM internal timing control is hardened by a self-adaptive timing design. Finally, the SRAM design was implemented and tested in the Austriamicrosystems (AMS) 0.35 ?m standard CMOS process. The prototype chips are adapted to work with frequencies up to 80 MHz, power supply voltages from 2.9 V to 3.3 V and temperatures from 0 °C to 60 °C. The single event latchup (SEL) tolerance is improved from 5.2 MeV cm2/mg to above 56 MeV cm2/mg. The total ionizing dose (TID) tolerance is enhanced by the P+ guard rings and the self-adaptive timing design. The single event upset (SEU) effects are also alleviated due to the high SNM SRAM cell and the P+ guard rings. In the near future, the presented SRAM will be integrated in the CPS chips for the STAR experiments.

Wei, Xiaomin; Gao, Deyuan; Doziere, Guy; Hu, Yann

2013-02-01

432

Gathering effect on dark current for CMOS fully integrated-, PIN-photodiodes  

NASA Astrophysics Data System (ADS)

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices, and pulse oximeters. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process flow opens the window to device miniaturization enhancing its properties and lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity float zone substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The photodiodes in the array are isolated by a guard ring consisting of a n+-p+ diffusions. However, the introduction of the guard ring design, necessary for photodiode-to-photodiode isolation, leads to an increase of the photodiodes dark current. In this article, the new parasitic term on the dark current is identified, formulated, modelled and experimental proven and has finally been used for an accurate design of the guard ring.

Teva, Jordi; Jonak-Auer, Ingrid; Schrank, Franz; Kraft, Jochen; Siegert, Joerg; Wachmann, Ewald

2010-02-01

433

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties  

PubMed Central

This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 ?m standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

2012-01-01

434

A CMOS pressure sensor with integrated interface for passive RFID applications  

NASA Astrophysics Data System (ADS)

This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18??m CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2?fF?kPa?1. The sensor interface consumes only 1.1?µW of power at 0.5?V voltage supply, which is at least an order of magnitude better than state-of-the-art designs.

Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

2014-12-01

435

High-density multilayer connection technology for MEMS and CMOS applications  

NASA Astrophysics Data System (ADS)

A multi-layer technology for electrical high-density connections between the two opposing sides of a wafer has been developed. Openings in a double-side polished wafer were created by applying a deep reactive ion etching technique. Hole structures with a diameter of 20 ?m were formed through a 350-?m thick wafer. A multi-layer system of up to eight layers consisting of alternating conducting layers (N-type doped poly-silicon) and isolating layers (silicon-oxide) were grown until the vias were filled. Subsequently, all layers on the wafer surface were then removed in a CMP process. In this way, a multi-connection structure embedded in the silicon wafer can be fabricated. The applied low-pressure chemical vapor deposition techniques guarantee a sufficient homogenous coating outside and inside of the entire structure to a minimum layer thickness of one ?m. The connection quality has been examined combining impedance spectroscopy and Focused Ion Beam technology. Depending on the geometry and the doping profile of the poly-silicon layers, a connection resistance of less than 80 Ohms can be achieved with sufficient DC isolation. In this way, a multi-connection of up to four isolated signal lines per opening was manufactured. This corresponds to a local connection density higher than 30.000/cm2. The achievable connection density and the full CMOS compatibility of the applied processes make this multi-layer connection technology particularly well suited for combined MEMS and CMOS applications

Bai, Seoung Jai; Fasching, Rainer J.; Prinz, Fritz B.

2003-04-01

436

CMOS Transistor Mismatch Model valid from Weak to Strong Inversion  

E-print Network

CMOS Transistor Mismatch Model valid from Weak to Strong Inversion Teresa Serrano and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able of transistor mismatch is crucial for precision analog design. Using very reduced transistor geometries produces

Barranco, Bernabe Linares

437

An Analog CMOS Backward Error-propagation LSI  

Microsoft Academic Search

The design of a novel cascadable CMOS analog IC architecture that implements the Backward Error Propagation algorithm is describcd. Forward and backward propagation signals coexist simultaneously in this unclockcd system, and internal analog weights are stored as charges on capacitors. This IC will speed up convergence of this algorithm many orders of magnitude over conventional software implementations, allowing a variety

B. Furman; A. A. Abidi

1988-01-01

438

An integrated CMOS micromechanical resonator high-Q oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

Clark T.-C. Nguyen; Roger T. Howe

1999-01-01

439

Gate engineering for deep-submicron CMOS transistors  

Microsoft Academic Search

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the

Bin Yu; Dong-Hyuk Ju; Wen-Chin Lee; Nick Kepler; Tsu-Jae King; Chenming Hu

1998-01-01

440

Development of RF CMOS receiver front-ends for ultrawideband  

E-print Network

measurement result of 7.2dB gain, 4.2-6dB noise figure, and less than -10dB return loss through 0-11GHz. A new distributed amplifier implementing cascade common source gain cells is presented in 0.18-?m CMOS. The new amplifier demonstrates a high gain of 16dB...

Guan, Xin

2009-05-15

441

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess  

E-print Network

circuit. The bridge fault transforms the two gates for which the bridged wires are outputs into a singleBridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault

Larrabee, Tracy

442

Leakage sources and possible solutions in nanometer CMOS technologies  

Microsoft Academic Search

Until recent years, dynamic power dissipation contributed the most to the chip's total power dissipation in CMOS digital circuits thus much attention was given to reduce this dynamic power. But as technology advances into the sub-100 nm regime, leakage power dissipation, which is a static power, increases at a much faster rate than dynamic power and it is expected to

Walid M. Elgharbawy; Magdy A. Bayoumi

2005-01-01

443

Determination of SEU parameters of NMOS and CMOS SRAMs  

Microsoft Academic Search

Procedures for determining the SEU parameters for advanced memory devices are demonstrated for CMOS and resistor-loaded NMOS SRAMs. The dimensions of the sensitive volume are either obtained from charge collection measurements on test structures or estimated from similar measurements on the SRAMs themselves. Values of the critical charge determined from simple proton measurements agree with the values obtained for three

P. J. McNulty; W. J. R. J. Beavais; D. R. Roth

1991-01-01

444

Relationship between IBICC imaging and SEU in CMOS ICs  

SciTech Connect

Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

Sexton, F.W.; Horn, K.M.; Doyle, B.L. [Sandia National Labs., Albuquerque, NM (United States); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. [Melbourne Univ., Parkville, VIC (Australia)

1993-03-01

445

Radiation and postirradiation functional upsets in CMOS SRAM  

SciTech Connect

The CMOS SRAM radiation and postirradiation functional upsets are investigated as a function of total dose, dose rate, annealing time and functional tests. Local and conventional X-ray as well as LINAC and Sr-90 irradiation procedures were performed. A model explaining the experimental results is discussed.

Chumakov, A.I.; Yanenko, A.V. [Specialized Electronic Systems, Moscow (Russian Federation)] [Specialized Electronic Systems, Moscow (Russian Federation)

1996-12-01

446

Relationship between IBICC imaging and SEU in CMOS ICs  

SciTech Connect

Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

Sexton, F.W.; Horn, K.M.; Doyle, B.L. (Sandia National Labs., Albuquerque, NM (United States)); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. (Melbourne Univ., Parkville, VIC (Australia))

1993-01-01

447

Measuring Power and Energy of CMOS Circuits: A Comparative Analysis  

E-print Network

DD(t), it is possible to calculate the charge, energy and power consumed by an IC. The main problem lays on the properMeasuring Power and Energy of CMOS Circuits: A Comparative Analysis J. Rius, A. Peidro, S. Manich presents and compares a set of experimental results on the measurement of power and energy consumed using

Boemo, Eduardo

448

CMOS Monolithic Voltage Converter ________________________________________________________________ Maxim Integrated Products 1  

E-print Network

or Doubles Input Supply Voltage Selectable Oscillator Frequency: 10kHz/80kHz 88% Typ Conversion Efficiency for both battery-powered and board- level voltage conversion applications. The MAX660 can also doubleMAX660 CMOS Monolithic Voltage Converter

Berns, Hans-Gerd

449

Upper-Bound Estimates Of SEU in CMOS  

NASA Technical Reports Server (NTRS)

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Edmonds, Larry D.

1990-01-01

450

A Fully Differential CMOS Potentiostat Meisam Honarvar Nazari  

E-print Network

of poor selectivity [1]. In FSCV a cyclic potential is applied between recording electrodes. It offers beneficial when supply voltage shrinks due to CMOS technology scaling. + - VOUT WE1WE2RE I1I2 I/V ION-SELECTIVE down to pico-ampere range. The fully differential architecture with differential recording electrodes

Genov, Roman

451

Intensity Histogram CMOS Image Sensor for Adaptive Optics  

E-print Network

Intensity Histogram CMOS Image Sensor for Adaptive Optics Yu M. Chi, Gary Carhart , Mikhail A imaging mode and 4.6mW in high-speed histogram mode. Applications include real-time adaptive optics control for laser communications. I. INTRODUCTION Adaptive optical systems are highly useful

Cauwenberghs, Gert

452

Single Event Upset Behavior of CMOS Static RAM Cells  

NASA Technical Reports Server (NTRS)

An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

1993-01-01

453

CMOS image sensors as an efficient platform for glucose monitoring.  

PubMed

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-01

454

Defect classes: An overdue paradigm for CMOS IC testing  

Microsoft Academic Search

The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS IC's that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test

C. F. Hawkins; J. M. Soden; A. W. Righter; F. J. Ferguson

1994-01-01

455

The Evolution of Digital Imaging: From CCD to CMOS  

E-print Network

The Evolution of Digital Imaging: From CCD to CMOS A Micron White Paper Digital imaging began with the invention of the charge- coupled device (CCD) in 1969. Since then, the technologies used to convert light honors, for developing the charge-coupled device (CCD) while they were both researchers

La Rosa, Andres H.

456

Record RF performance of standard 90 nm CMOS technology  

Microsoft Academic Search

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency fmax (280 GHz), varactor tuning range and varactor and inductor quality factor.

L. F. Tiemeijer; R. J. Havens; R. de Kort; A. J. Scholten; R. van Langevelde; D. B. M. Klaassen; G. T. Sasse; Y. Bouttement; C. Petot; S. Bardy; D. Gloria; P. Scheer; S. Boret; B. Van Haaren; C. Clement; J.-F. Larchanche; I.-S. Lim; A. Duvallet; A. Zlotnicka

2004-01-01

457

Accurate thermal noise model for deep-submicron CMOS  

Microsoft Academic Search

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 ?m down to 0.17 ?m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters

A. J. Scholten; H. J. Tromp; L. F. Tiemeijer; R. Van Langevelde; R. J. Havens; P. W. H. De Vreede; R. F. M. Roes; P. H. Woerlee; A. H. Montreen; D. B. M. Klaassen

1999-01-01

458

BiCMOS differential temperature sensor: Characterization and BIST applications  

Microsoft Academic Search

Measurements of thermal gradients inside the silicon die can be used for BIST applications. Two temperature sensors sensible to changes of the surface thermal gradient have been implemented in a 1.2 µm BiCMOS technology. Results show that the power dissipated by a circuit can be monitored by placing differential temperature sensors. A detailed analysis of the noise coupled to the

Josep Altet; X. Aragones; Jose Luis GonzAlez; Diego Mateo; Antonio Rubio

1998-01-01

459

Dynamic internal testing of CMOS circuits using hot luminescence  

Microsoft Academic Search

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the

J. A. Kash; J. C. Tsang

1997-01-01

460

A CMOS Linear power supply for a Wireless Biomedical Sensor  

Microsoft Academic Search

This paper describes a CMOS Linear Voltage Regulator (LVR) of an implanted physiological signal system (biosensor) that is used to monitor blood pressure. This system is part of a Wireless Biomedical Sensor (WBS). The LVR topology is based on a classical structure of a Low Dropout Regulator (LDO). The energy is received from a RF link, thus operating as a

Paulo Crepaldi; Tales Pimenta; Robson Moreno; Edgar Rodriguez

2010-01-01

461

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

462

CMOS-year 2010 and beyond; from technological side  

Microsoft Academic Search

CMOS LSIs, having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems

Hiroshi Iwai; Komukai Toshiba-cho

1998-01-01

463

Research-grade CMOS image sensors for remote sensing applications  

Microsoft Academic Search

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been

Olivier Saint-Pe; Michel Tulet; Robert Davancens; Franck Larnaudie; Pierre Magnan; Philippe Martin-Gonthier; Franck Corbiere; Pierre Belliot; Magali Estribeau

2004-01-01

464

SMALL-SIGNAL MODELING OF RF CMOS A DISSERTATION  

E-print Network

SMALL-SIGNAL MODELING OF RF CMOS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL, where it is becoming a serious contender for radio frequency (RF) appli- cations in the GHz range are critical requirements for circuit designs, the RF behavior and physics are not well understood

Dutton, Robert W.

465

Table of Contents Deep Submicron CMOS Photonics 5-1  

E-print Network

Characteristics of Selectively Grown Ge-on-Si Photodiodes 5-18 Excitonic Surface Plasmon Resonance Biosensor 5-threshold Vertical Cavity Surface-emitting Lasers Recess Integrated within Silicon CMOS Integrated Circuits 5-14 Magnetic Oxides for Optical Isolators and Magnetoelectronic Devices 5-15 Development of Terahertz Quantum

Reif, Rafael

466

Analog CMOS Velocity Sensors C. M. Higgins and C. Koch  

E-print Network

. Keywords: Analog VLSI, CMOS, velocity sensors, motion sensors, optical ow 1. INTRODUCTION Motion is a key. Continuous-time optical sensor arrays have clear advantages over discrete-time sampled arrays for motion pro a long history,1 10 but only recently have such sensors begun to simultane- ously accomplish the aims

467

IBM Systems and Technology Electronics IBM CMOS 7HV for  

E-print Network

companies can significantly improve these metrics today by using IBM technology in smart solar- panel to improve effi- ciency, cost per kilowatt and reliability of solar modules IBM CMOS 7HV is the industry, cost per kilowatt and reliability of solar modules. While this research is critical, photovoltaics

468

Total-Ionizing-Dose Effects in Modern CMOS Technologies  

Microsoft Academic Search

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by

H. J. Barnaby

2006-01-01

469

Power Supply Generation in CMOS Passive UHF RFID Tags  

Microsoft Academic Search

The paper discusses the design of a power generation circuit suitable to provide the supply voltage for a passive UHF RFID tag. The proposed differential rectifier exhibits a low activation threshold and is compatible with digital CMOS technologies. The chip supply voltage is obtained through a Dickson-based voltage multiplier and an ultra low-power voltage regulator

Alessio Facen; A. Boni

2006-01-01

470

Method of recording CMOS IC parameters after a destabilizing pulse  

SciTech Connect

The techniques presented for recording the parameters of a CMOS IC make it possible to determine the pulse transient response function of an integrated circuit and to observe the behavior of the IC during a destabilizing pulse and just after it for 10{sup -5}-10{sup -4} sec.

Chertov, A.V.

1995-09-01

471

Roadmap for CMOS image sensors: Moore meets Planck and Sommerfeld  

E-print Network

lithographic feature size has decreased by thirty percent every three years.2, 3 CMOS technology scaling can be used to shrink transistor size and increase photosensitive area in the pixel (fill-factor). Different and diffraction-limited blurring (Sommerfeld).6 First, consider photon noise. As pixel size shrinks, the mean

Wandell, Brian A.

472

A very high frequency CMOS Variable Gain Amplifier  

E-print Network

A fully differential CMOS Variable Gain Amplifier (VGA) consisting of an analog multiplier, current gain stages, and resistor loads is designed for very high frequency applications. The gain can be programmed from 0dB to 40dB with -3dB bandwidth...

Tan, Siang Tong

2012-06-07

473

Test Considerations for Gate Oxide Shorts in CMOS ICs  

Microsoft Academic Search

Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-?? range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC.

Jerry M. Soden; Charles Hawkins

1986-01-01

474

Ultrabroadband supercontinuum generation in a CMOS-compatible platform  

E-print Network

Ultrabroadband supercontinuum generation in a CMOS-compatible platform R. Halir,1,5, * Y. Okawachi 162267); published May 10, 2012 We demonstrate supercontinuum generation spanning 1.6 octaves in silicon Optical Society of America OCIS codes: 190.4390, 320.7110, 320.6629, 230.7370. Supercontinuum generation

Lipson, Michal

475

Polysilicon sensors for CMOS-MEMS electrothermal probes  

Microsoft Academic Search

We describe multiple embedded polysilicon resistive sensors in CMOS-MEMS electrothermal probes as a step toward creating probe arrays for passing current on ICs to reconfigure resistance change (RC) vias. When not in contact, a low-resistivity unsilicided polysilicon (LP) resistor detects probe displacement indirectly through the temperature coefficient of resistance (TCR) effect. When in contact with a load force, the difference

J. Liu; M. Noman; J. A. Bain; T. E. Schlesinger; G. K. Fedder

2009-01-01

476

Hybrid CMOS SiPIN detectors as astronomical imagers  

NASA Astrophysics Data System (ADS)

Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge Transfer (IPCT), is introduced. This effect has an extremely significant impact on x-ray astronomy. For persistence, a new theory and accompanying simulations are presented to explain latent images in the HyViSI. In consideration of these artifacts and the overall measured performance, we argue that HyViSI sensors are ready for application in certain regimes of astronomy, such as telescope guiding, measurements of fast planetary transits, and x-ray imaging, but not for others, such as deep field imaging and large focal plane astronomical surveys.

Simms, Lance Michael

477

Integrated CMOS-selenium x-ray detector for digital mammography  

NASA Astrophysics Data System (ADS)

This paper describes a novel area detector for direct conversion and readout of the x-ray energy that eliminates multiple conversions and coupling stages which degrade performance. The pixel array and readout electronics are fabricated on the same piece of silicon. The detector consists of a uniform layer (approximately 300 micrometers) of amorphous selenium alloy vapor-deposited on an electronic readout array fabricated using conventional complementary metal oxide semiconductor (CMOS). The CMOS array features 66 micrometer pixels in a 1024 X 832 array providing a 5.5 X 6.75 cm image area. Each pixel has active circuitry including signal amplification, pixel selection and reset, while peripheral circuitry on one end of the array provides shift registers, sample and hold and multiplexing. The CMOS readout array was fabricated at a standard facility on a 10-cm diameter silicon wafer using 2 micrometer CMOS process. Fifteen separate image sensors were assembled for evaluation in a 3 X 5 format to provide a 20 X 27 cm composite field of view. Missing data between sensors is recovered by acquiring three sub-exposures, between which the array is translated diagonally approximately 2 mm. Total exposure time for an average breast is less than one second. Conversion efficiency was found to be approximately 120 electrons per absorbed x-ray (19 keV average). Electronic readout noise was measured to be 2.4 ADU corresponding to approximately 500 electrons. Detective quantum efficiency was found to be 0.65 at low spatial frequency (0.25 lp/mm) and at 0.2 at high spatial frequency (8 lp/mm) for x-ray fluence ranging from 5 - 35 mR. Images of an ACR phantom show visualization of all of the fibers, specks and masses when displayed with a linear lookup table on a high-resolution monitor. These studies demonstrated that there is a slight but measurable image retention evident as 'ghost' images. The two most effective means to reduce this effect are flushing the sensors with infrared light or x-rays between exposures and reversing the applied voltage on the selenium layer. A number of improvements designed to increase sensitivity and reduce noise also have been identified and are being implemented. Sample images were acquired from four volunteer human subjects at exposure factors identical to their film-screen mammograms. The results suggest that the detector performance is suitable for further clinical investigation.

Andre, Michael P.; Spivey, Brett A.; Martin, Peter J.; Morsell, Arthur L.; Atlas, Eugene; Pellegrino, Tony

1998-07-01

478

Modelling of coplanar waveguide transmission lines in multiple metal layer processes  

NASA Astrophysics Data System (ADS)

Accurate characterisation of transmission lines is essential in enabling the design of Monolithic Microwave Integrated Circuits (MMICs) or Radio Frequency Integrated Circuits (RFICs). One RFIC technology currently being pursued is Silicon on Sapphire Complementary Metal Oxide Semiconductor (CMOS) technology. CMOS processes typically involve stacked metal layer structures and the correct method of modelling coplanar waveguides in CMOS is unclear. This paper reports on preliminary studies into electromagnetic design, with an emphasis on correctly predicting losses associated with these structures.

Heading, E.; Hansen, H. J.; Parker, M. E.

2007-01-01

479

Contact CMOS imaging of gaseous oxygen sensor array  

PubMed Central

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

480

Fourier analysis of the imaging characteristics of a CMOS active pixel detector for mammography by using a linearization method  

NASA Astrophysics Data System (ADS)

Active pixel design using the complementary metal-oxide-semiconductor (CMOS) process is a compelling solution for use in X-ray imaging detectors because of its excellent electronic noise characteristics. We have investigated the imaging performance of a CMOS active pixel photodiode array coupled to a granular phosphor through a fiber-optic faceplate for mammographic applications. The imaging performance included the modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). Because we observed a nonlinear detector response at low exposures, we used the linearization method for the analysis of the DQE. The linearization method uses the images obtained at detector input, which are converted from those obtained at detector output by using the inverse of the detector response. Compared to the conventional method, the linearization method provided almost the same MTF and a slightly lower normalized NPS. However, the difference between the DQE results obtained by using the two methods was significant. We claim that the conventional DQE analysis of a detector having a nonlinear response characteristic can yield wrong results. Under the standard mammographic imaging condition, we obtained a DQE performance that was competitive with the performances of conventional flat-panel mammography detectors. We believe that the CMOS detector investigated in this study can be successfully used for mammography.

Han, Jong Chul; Yun, Seungman; Youn, Hanbean; Kam, Soohwa; Cho, Seungryong; Achterkirchen, Thorsten G.; Kim, Ho Kyung

2014-09-01

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