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1

Silicon-gate n-well CMOS process by full ion-implantation technology  

NASA Astrophysics Data System (ADS)

A silicon-gate n-well CMOS process technology which makes use of full ion implantation for digital circuits operating at TTL compatible supply voltage is presented. The process employs an n well for p-MOSFETs in a p substrate and an n(+) polysilicon gate in both n- and p-MOSFETs, with six photomasks, eight photolithography steps and five ion-implantation steps to realize gate lengths as short as 2 microns in n- and p-MOSFETs. Average impurity concentrations determined from MOSFET substrate bias effects and junction depth have been found to be in good agreement with those expected from impurity profiles calculated by simple diffusion theories, indicating that CMOS circuits can be designed for any supply voltage by adjusting threshold voltages.

Ohzone, T.; Shimura, H.; Tsuji, K.; Hirao, T.

1980-09-01

2

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers  

NASA Astrophysics Data System (ADS)

A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

Ratti, L.; Gaioni, L.; Manghisoni, M.; Re, V.; Traversi, G.

2010-12-01

3

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0  

NASA Astrophysics Data System (ADS)

Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5_3D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

Traversi, G.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Re, V.

2011-01-01

4

A high isolation CMFB downconversion micromixer using 0.18-?m deep n-well CMOS technology  

Microsoft Academic Search

CMOS deep n-well technology can eliminate body effects of NMOS transistors and improve LO-IF and LO-RF isolation in a Gilbert micromixer. A 37 dB LO-IF and 38 dB LO-RF isolation downconversion micromixer with 19 dB conversion gain, IP1dB=-19.5 dBm and IIP3=-12.5 dBm when RF=2.4 GHz and LO=2.25 GHz is demonstrated in this paper by using 0.18 ?m deep n-well CMOS

C. C. Meng; S. K. Xu; T. H. Wu; M. H. Chao; G. W. Huang

2003-01-01

5

Process integration for submicron CMOS  

NASA Astrophysics Data System (ADS)

Four aspects of submicron CMOS process integration are examined. They are: (1) device and systems goals, (2) unit processes, (3) process interactions, and (4) process modeling and characterization. It is believed that sub-half-micron CMOS technologies offer the potential for realizing electronic systems with a complexity approaching that of the human brain.

Krusius, J. Peter

6

A high density CMOS process  

Microsoft Academic Search

A 3? CMOS process yielding circuit densities comparable to 1.5? design rules will be reported. The procedure was used to construct an 8b microcomputer for telecom use: clock frequency was 20MHz at 9V; 50k transistors were placed in an area of 31mm2.

R. Luscher; J. De Zaldivar

1985-01-01

7

Microimage processing system based on CMOS sensor  

Microsoft Academic Search

A CMOS IS (image sensor) has been widely applied in the multimedia field due to its unique features. One application of the CMOS IS is the microimage processing field is presented. An electronic eyepiece, mainly incorporating optical lens and a CMOS IS, is developed to digitize an optical image, process the digital signals and transmit them to a processor (i.e.

Xiangdong Xu; Feng Li; Chao Zeng; Xianbing Zheng

2002-01-01

8

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

NASA Astrophysics Data System (ADS)

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm2 with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K.

2011-10-01

9

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

SciTech Connect

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

2011-10-20

10

A process for the combined fabrication of ion sensors and CMOS circuits  

Microsoft Academic Search

A novel process for the fabrication of ion-selective field-effect transistors (ISFETs) together with CMOS circuits on the same chip is reported. The process is based on a standard 2-?m, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFETs are fabricated with floating polysilicon gates, which are exposed to

L. Bousse; J. Shott; J. D. Meindl

1988-01-01

11

The effect of deep trench isolation, trench isolation and sub-collector doping on the electrostatic discharge (ESD) robustness of radio frequency (RF) ESD STI-bound P+\\/N-well diodes in BiCMOS silicon germanium technology  

Microsoft Academic Search

This paper demonstrates the independent and combined effect of deep trench (DT) isolation, trench isolation (TI), and sub-collector on shallow trench isolation (STI) -bound p+\\/n-well ESD diode structures in a 120 and 200 GHz fT BiCMOS Silicon Germanium technology.

Steven H. Voldman

2003-01-01

12

Embedded OTP fuse in CMOS logic process  

Microsoft Academic Search

This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100?s per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm 2 in 0.25?m CMOS process and has 10-year data retention at 85C.

Ching-Yuan Lin; Chung-Hung Lin; Chien-Hung Ho; Wei-Wu Liao; Shu-Yueh Lee; Ming-Chou Ho; Shin-Chen Wang; Shih-Chan Huang; Yuan-Tai Lin; Charles Ching-Hsiang Hsu

2005-01-01

13

High-Q capacitors implemented in a CMOS process for low-power wireless applications  

Microsoft Academic Search

In a foundry 0.8-?m CMOS process, low-cost capacitors with a measured Q factor of around 50 at 3 GHz and high intrinsic capacitance\\/area (~200 nF\\/cm2) were demonstrated. When extrapolated to 900 MHz, the Q factor is greater than 100. The capacitors use a poly-to-n-well MOS structure which has been commonly dismissed for high-Q applications due to the high n-well sheet

Chih-Ming Hung; Yo-Chuol Ho; I-Chang Wu

1998-01-01

14

Substrate bonding techniques for CMOS processed wafers  

NASA Astrophysics Data System (ADS)

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

van der Groen, S.; Rosmeulen, M.; Baert, K.; Jansen, P.; Deferm, L.

1997-09-01

15

The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process.  

SciTech Connect

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

Ball, D. R. (Vanderbilt University, Nashville, TN); Ahlbin, Jonathan R. (Vanderbilt University, Nashville, TN); Gadlage, Matthew J. (NSWC Crane, Crane, IN); Massengill, Lloyd W. (Vanderbilt University, Nashville, TN); Witulski, A. W. (Vanderbilt University, Nashville, TN); Reed, R. A. (Vanderbilt University, Nashville, TN); Vizkelethy, Gyorgy; Bhuva, Bharat L. (Vanderbilt University, Nashville, TN)

2010-07-01

16

A standard CMOS humidity sensor without post-processing.  

PubMed

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-06-08

17

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented

Christian Enz; Manfred Punzenberger; Dominique Python

1999-01-01

18

Schottky barrier diodes for millimeter wave detection in a foundry CMOS process  

Microsoft Academic Search

CoSi2-Si Schottky barrier diodes on an n-well and on a p-well\\/substrate are fabricated without a guard ring in a 130-nm foundry CMOS process. The nand p-type diodes with an area of 160.320.32 ?m2 achieve cutoff frequencies of ?1.5 and ?1.2 THz at 0-V bias, respectively. These are the highest cutoff frequencies for Schottky diodes fabricated in foundry silicon processes. The

Swaminathan Sankaran; Kenneth K. O

2005-01-01

19

Process Optimization of Radiation-Hardened CMOS Integrated Circuits  

Microsoft Academic Search

The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108

G. F. Derbenwick; B. L. Gregory

1975-01-01

20

Efficient premature edge breakdown prevention in SiAPD fabrication using the standard CMOS process  

NASA Astrophysics Data System (ADS)

The effects of premature edge breakdown (PEB) and available PEB prevention (PEBP) techniques in silicon avalanche photodiode fabrication using the standard complementary metal-oxide-semiconductor (CMOS) process are scrutinized in this paper. Impact of device simulation and its induced impacts on fabrication are addressed based on our design, simulation and fabrication experiences. Three most common PEBP techniques are implemented followed by a systematic study aimed at miniaturization, while optimizing the overall performance. The p-well-, p-sub- and n-well-based PEBP techniques are evaluated and compared based on simulation and fabrication results using the standard CMOS process. The results demonstrate that the n-well guard ring offers the most efficient PEBP technique. This technique offers a high-gain (800), low-noise dark current rate (DCR = 40 Hz), high detection efficiency (70%) avalanche photodiode with a higher functionality probability.

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-04-01

21

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage (LV) and low-power (LP) analog signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V

C. C. Enz; M. Punzenberger; D. Python

1997-01-01

22

A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process  

Microsoft Academic Search

This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra

Xu Ji; Zhihong Li; Jianzhong Xi; Juan Li; Yangyuan Wang

2008-01-01

23

Micromachined thermal radiation emitter from a commercial CMOS process  

NASA Astrophysics Data System (ADS)

Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch in an aqueous ethylemediamine-pyrocatechol mixture is performed to realize the micromechanical structures. The resulting structures are suspended plates consisting of polysilicon resistors encapsulated in the field and CVD (chemical-vapor-deposited) oxides available in the CMOS process. The plates are suspended by aluminum heater leads that are also encapsulated in the field and CVD oxides. Studies of the suitability of these structures for DTSS have been initiated, and early favorable results are reported.

Parameswaran, M.; Robinson, Alexander M.; Blackburn, David L.; Gaitan, Michael; Geist, Jon

1991-02-01

24

Review of RF CMOS Performance and Future Process Innovations  

Microsoft Academic Search

This report contains a review of CMOS process technology in terms of radio-frequency(RF) performance around and beyond 1GHz. First, the use of integrated technology forwireless communications is justified and state-of-the-art commercial chipsets are presented.After CMOS is presented as a potential RF candidate, the major elements of the technologyare evaluated in an RF context and current performance is listed. Elements include

Troels Emil Kolding

1998-01-01

25

Micro-image processing system based on CMOS sensor  

NASA Astrophysics Data System (ADS)

A CMOS IS (image sensor) has been widely applied in the multimedia field due to its unique features. One application of the CMOS IS is the microimage processing field is presented. An electronic eyepiece, mainly incorporating optical lens and a CMOS IS, is developed to digitize an optical image, process the digital signals and transmit them to a processor (i.e. computer). The digitized images are displayed in real time and stored off-line for post-mission analysis. An algorithm to process the image is adopted to extract features after the preprocessing operation. In this paper we will describe the system, introduce the structure of eyepiece and discuss the preprocessing technique. Finally some results of feature extraction are given. The system has been applied in the microimage processing field and the availability has been verified.

Xu, Xiangdong; Li, Feng; Zeng, Chao; Zheng, Xianbing

2002-09-01

26

A novel NMOS transistor for high performance ESD protection devices in 0.18 ?m CMOS technology utilizing salicide process  

Microsoft Academic Search

The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 ?m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 . Fully

Chang-Su Kim; Hong-Bae Park; Bung-Gwan Kim; Dae-Gwan Kang; Myoung-Goo Lee; Si-Woo Lee; Chan-Hee Jeon; Wan-Gu Kim; Young-Jae Yoo; Han-Sub Yoon

2000-01-01

27

Fabrication of the planar angular rotator using the CMOS process  

NASA Astrophysics Data System (ADS)

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 ?m single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

28

One time programming (OTP) with Zener diodes in CMOS processes  

Microsoft Academic Search

This article describes a lateral Zener diode in standard CMOS processes, without extra masks or technology steps, for one time programming (OTP) applications. The diode is adapted for programming (=zapping) requirements. The optimization of the device for low zapping currents and high yield is shown. The zapping process is evaluated in detail and follows an optimized layout and zapping conditions.

J. Teichmann; K. Burger; W. Hasche; J. Herrfurth; G. Taschner

2003-01-01

29

A CCD\\/CMOS process for integrated image acquisition and early vision signal processing  

Microsoft Academic Search

The development of technology which integrates a four phase, buried-channel CCD in an existing 1.75 micron CMOS process is described. The four phase clock is employed in the integrated early vision system to minimize process complexity. Signal corruption is minimized and lateral fringing fields are enhanced by burying the channel. The CMOS process for CCD enhancement is described, which highlights

Craig L. Keast; Charles G. Sodini

1990-01-01

30

Industrial microsystems on top of CMOS design and process  

NASA Astrophysics Data System (ADS)

We propose a design and technology methodology and CAD tools for a microsystems fabrication based on the 1.0 micrometers CMOS from ATMEL-ES2. In order to profit from vendor cell libraries, design kits have to be enhanced to deal with the new conception environment. Main contributions are, sensor dependent technology file, device modeling and automatic generation for different ranges, and adaptation of semi- custom tools (simulation environment and P and R) for complete microsystems design. A library of dedicated sensor cells is being designed using Cadence DFWII and the foundry design kit. These sensors are fabricated with the standard CMOS process plus some post-processing steps. Three levels of post-processing are considered: 1) pH-ISFET sensors fabricated using standard CMOS, 2) gas flow and radiation sensors based on thermopiles using simple post-processing. The post-processing is compatible with the foundry CMOS process. Our technology has been developed up tot he point of maximum simplification that results in the use of only one additional mask for back-side etching. Passivation layer together with oxide windows are used for front-side etching with excellent results.

Carrabina, Jordi; Saiz, Joaquin; Marin, David; Marin, Xavier; Merlos, Angel; Bausells, Juan

1996-09-01

31

Quantification of Shallow-junction Dopant Loss during CMOS Process  

SciTech Connect

We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively.

Buh, G.H.; Park, T.; Jee, Y.; Hong, S.J.; Ryoo, C.; Yoo, J.; Lee, J.W.; Yon, G.H.; Jun, C.S.; Shin, Y.G.; Chung, U.-In; Moon, J.T. [Semiconductor R and D Center, Samsung Electronics Co., Ltd., Yongin-City, Gyeonggi-Do, 449-711 (Korea, Republic of)

2005-09-09

32

A triple metal interconnection process for CMOS technology  

Microsoft Academic Search

A triple interconnection process suitable for a CMOS 1.2-?m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used

P. Cagnoni; F. Gualandris; L. Masini

1989-01-01

33

Bridging Defects Resistance Measurements in a CMOS Process  

Microsoft Academic Search

Measurements on process-related defect nionitwing ,wcijers are presented in order to euuluute the i,csisluiict. ,ualu,e of b ridyzng deJects zn CMOS VLSI circu~ts. 'I'he inethodoloyy u sed is dlustrated and statzstics OIL the 1.esistance values are p resented. As a result, the vast niajoi-zty of the measured brzdges have a 1o.w 7.eszsta.nce. Only a small percentage of the brzdges has

Rosa Rodrguez-montas; Joan Figueras; Eric Bruls

1992-01-01

34

Optimal fabrication process for mems pressure sensor by 8inch CMOS  

Microsoft Academic Search

We have developed the MEMS piezo pressure sensor by utilizing CMOS process modules and tool-sets to challenge faster time to market and faster time to volume with high yield. The MEMS device has the commonality of process, tools, material, and design system and qualification method with 0.35um CMOS device. The CMOS integration approach also showed the high quality as small

Tadashi Kai; Katsuyuki Inoue; Y. Adachi

2010-01-01

35

Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic  

Microsoft Academic Search

A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated

Kumar Yelamarthi; Chien-In Henry Chen

2008-01-01

36

A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process  

NASA Astrophysics Data System (ADS)

This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra process required. A partially split cantilever configuration is developed for the lateral force detection. The piezoresistors are self-aligned to the split cantilever, and therefore the width of the beam is only limited by lithography. Consequently, this kind of cantilever potentially has a high resolution. The preliminary experimental results show expected performances of the fabricated piezoresistors and electronic circuits.

Ji, Xu; Li, Zhihong; Xi, Jianzhong; Li, Juan; Wang, Yangyuan

2008-11-01

37

Self-Calibrated Humidity Sensor in CMOS without Post-Processing  

PubMed Central

A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

38

Self-calibrated humidity sensor in CMOS without post-processing.  

PubMed

A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-12-27

39

Cosmic ray neutron multiple-upset measurements in a 0.6-?m CMOS process  

Microsoft Academic Search

A major cause of soft error rate in CMOS circuits operating at ground level and airplane flight altitudes are secondary neutrons generated in the atmosphere by primary cosmic rays. We developed a new technique for characterization of a CMOS process with respect to single upsets (SEUs) and multiple upsets (MUs). This technique has been demonstrated for a process with gate

P. Hazucha; C. Svensson

2000-01-01

40

Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization  

Microsoft Academic Search

The complexity in timing optimization of high- performance microprocessors has been increasing with the number of channel-connected transistors in various paths of dynamic CMOS circuits and the rising magnitude of process variations in nanometer CMOS process. In this paper, a process variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load Balance of Multiple Paths (LBMP) is

Kumar Yelamarthi; Chien-in Henry Chen

2008-01-01

41

Interferometric metrology of wafer nanotopography for advanced CMOS process integration  

NASA Astrophysics Data System (ADS)

According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

2001-12-01

42

3Transistor antifuse OTP ROM array using standard CMOS process  

Microsoft Academic Search

A 3-transistor cell CMOS OTP ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the

Jinbong Kim; Kwyro Lee

2003-01-01

43

A novel CMOS monolithic active pixel sensor with analog signal processing and 100% fill factor  

Microsoft Academic Search

We have designed and fabricated a CMOS monolithic active pixel sensor (MAPS) in a novel 0.18 micrometer image-sensor technology (INMAPS) which has a 100% fill factor for charged particle detection and full CMOS electronics in the pixel. The first test sensor using this technology was received from manufacture in July 2007. The key component of the INMAPS process is the

J. P. Crooks; J. A. Ballin; P. D. Dauncey; A.-M. Magnan; Y. Mikami; O. Miller; M. Noy; V. Rajovic; M. Stanitzki; K. D. Stefanov; R. Turchetta; M. Tyndel; E. G. Villani; N. K. Watson; J. A. Wilson

2007-01-01

44

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications  

Microsoft Academic Search

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT \\/ 270 GHz FMAX SiGe HBT on a 1.8V\\/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in

Arjun Kar-Roy; Edward J. Preisler; George Talor; Zhixin Yan; Roger Booth; Jie Zheng; Samir Chaudhry; David Howard; Marco Racanelli

2011-01-01

45

CMOS photonics  

Microsoft Academic Search

Light will be connecting CMOS chips sooner than you think. While every major semiconductor company is exploring silicon photonics in their research labs, Luxtera has implemented a practical version of the technology in a high-volume production CMOS process. The base process is Freescale's 0.13 ?m SOI CMOS, used to manufacture many of their high-performance PowerPC processors. In addition to the

C. Gunn

2005-01-01

46

Material choice for optimum stress memorization in SOI CMOS processes  

Microsoft Academic Search

Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals

A. Gehring; A. Mowry; A. Wei; M. Wiatr; R. Boschke; P. Javorka; B. Mulfinger; C. Scott; M. Lenski; G. Koerner; K. Huy; R. Otterbach; J. Klais; H. Geisler; T. Mantei; D. Greenlaw; M. Horstmann

2007-01-01

47

Process Development for CMOS-MEMS Sensors With Robust Electrically Isolated Bulk Silicon Microstructures  

Microsoft Academic Search

This paper presents a deep reactive-ion etching (DRIE)-based post-CMOS micromachining process that provides robust electrically isolated single-crystal silicon (SCS) microstructures for integrated inertial sensors. Several process issues arise from previously reported three-axis CMOS microelectromechanical system (MEMS) accelerometers, including sidewall contaminations of SCS microstructures in plasma etch and a severe silicon undercut caused by overheating of suspended microstructures. Solutions to these

Hongwei Qu; Huikai Xie

2007-01-01

48

Development of CMOS Process Compatible Force Sensor and its Application to Probe Card  

Microsoft Academic Search

This thesis aims to apply a standard CMOS process to develop a Wheatstone-bridge- based piezoresistive force sensor. This CMOS-compatible piezoresistive force sensor with small area and easy fabrication consists of a thin-film receiver made by passivation, silicon oxide and a piezoresistive layer made by the polycrystalline silicon respectively. Additionally, utilize the RLS etching process offered by CIC to conduct its

Jung-Tang Huang; Ming-Chieh Chiu; Kuo-Yu Lee; Chan-Shoue Wu; Hou-Jun Hsu; Pen-Shan Chao

2007-01-01

49

Building-in ESD\\/EOS reliability for sub-halfmicron CMOS processes  

Microsoft Academic Search

MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD\\/EOS reliability through nMOSFET drain design for a 0.35 ?m CMOS process that compromises neither the

Carlos H. Diaz; Thomas E. Kopley; Paul J. Marcoux

1996-01-01

50

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications  

NASA Astrophysics Data System (ADS)

The prototype of a three-dimensional (3D) monolithic active pixel sensor (MAPS) has been characterized. The device, featuring a 20?m pitch, was designed based on the same approach that was adopted in developing the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS technology. Different kinds of test structures, including single pixels, 33 arrays and 88 and 1616 matrices were tested. Functionality of the collecting deep N-well electrode, the analog front-end and the digital readout electronics has been demonstrated. Inter-tier communication was found to work properly in the case of redundant interconnection and could be exploited for the test of the analog pixel section. On the other hand, inter-tier interconnections based on individual bond pads were proven ineffective likely due to wafer misalignment.

Ratti, L.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Re, V.; Traversi, G.

2013-01-01

51

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors  

Microsoft Academic Search

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 ?m CMOS triple-metal-layer technology on a 61 mm2 die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double

Nobuhiro Ide; Hiroto Fukuhisa; Yoshihisa Kondo; Takeshi Yoshida; Masato Nagamatsu; Junji Mori; Itaru Yamazaki; Kiyoji Ueno

1993-01-01

52

A SPDT switch in a standard 45 nm CMOS process for 94 GHz Applications  

Microsoft Academic Search

A fully integrated single-pole double-throw (SPDT) transmit\\/receive switch (T\\/R switch) is implemented on a standard 45nm CMOS process. This circuit is dedicated to fully integrated CMOS RF front end modules operating at 94 GHz. The traveling-wave topology was used to minimize the insertion loss at millimeter wave frequencies. The switch exhibits a measured insertion loss of 5.3 dB, an isolation

T. Quemerais; L. Moquillon; J. Fournier; P. Benech

2010-01-01

53

Technology aspects of a CMOS neuro-sensor: back end process and packaging  

Microsoft Academic Search

A CMOS-compatible process is presented which allows to realize sensor arrays for non-invasive, extracellular, high density, long term recording of neural activity. A high-permittivity biocompatible dielectric is used to capacitively couple nerve cell-induced biological signals to the CMOS circuitry-based electronic world. The transducer consists of a multi layer of TiO2 and ZrO2 and is fabricated in the backend of a

Franz Hofmann; Bjrn Eversmann; Martin Jenkner; Alexander Frey; Matthias Merz; Tamara Birkenmaier; Peter Fromherz; Matthias Schreiter; Reinhard Gabl; Kurt Plehnert; Michael Steinhauser; Gerald Eckstein; Roland Thewes

2003-01-01

54

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

55

A CMOS\\/buried-n-channel CCD compatible process for analog signal processing applications  

Microsoft Academic Search

The integration of charge-coupled device structures and support circuitry into prototype equipment for communications systems was studied. The support circuitry involved clock drivers and timing\\/logic circuitry along with CCD signal processing circuitry. A complementary metal oxide semiconductor (CMOS)-CCD compatible approach that minimizes power dissipation, leads to a reduction in complexity of interface circuitry, and offers high reliability was used. The

R. Dawson; J. Preisig; J. Carnes; J. Pridgen

1977-01-01

56

256 x 256 CMOS active pixel image sensor  

Microsoft Academic Search

A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and

El-Sayed I. Eid; Alex G. Dickinson; Dave A. Inglis; Brian D. Ackland; Eric R. Fossum

1995-01-01

57

Reliability challenges of advanced CMOS process and product development: design and application aware qualification  

Microsoft Academic Search

As advanced technology process rapidly migrates, more than Moore approach, with pursuing cutting-edge performance, power and area scaling, revolutionary introduction of new material, process and structure will tax traditional reliability target (spec) being continuously adopted for advanced CMOS process qualification to handle reliability concerns with finer granurality. Although ICs for all applications are currently coming from the same technology node

Jongwoo Park

2012-01-01

58

Silicide-related yield enhancement in a deep submicrometer CMOS process  

Microsoft Academic Search

Electrical bitmapping and physical failure analysis were used to detect a small silicide break within a memory circuit which led to severe yield loss on our 0.20 ?m CMOS process. A parallel, two-phase approach was used to optimize the titanium silicide formation process and the silicon surface preparation prior to titanium silicide. Several process and mask tooling modifications were implemented

S. Qian; R. Solis; M. Haley; G. Pesnell; T. Mitchell; R. Butler; D. Ziger; J. Klatt; M. Delgado; M. P. Karnett; J. Davis

2001-01-01

59

Process and temperature performance of a CMOS beta-multiplier voltage reference  

Microsoft Academic Search

The beta multiplier voltage reference (BMVR) is discussed as a direct replacement for the bandgap voltage reference in a CMOS process especially when substrate current is a concern. Performance of the BMVR with regard to temperature and process variations is covered. Experimental results from a 2-micron MOSIS test chip indicate that the BMVR can be tuned to within 10 mV

Song Liu; R. Jacob Baker

1998-01-01

60

Design Methodology For Optimizing Gate Driven Esd Protection Circuits In Submicron Cmos Processes  

Microsoft Academic Search

This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS) protection scheme has been presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDNMOS is effective even for small analog\\/mixed-signal designs. SPICE simulation is used to optimize the design. High ESD

Julian Zhiliang Chen; A. Amerasekera; Charvaka Duvvury

1997-01-01

61

Application of RTA to a 0.8-um BiCMOS process  

NASA Astrophysics Data System (ADS)

RTA has been established as a key process element in a sub-micron BiCMOS flow. The major advantage of RTA is that a temperature pulse > 1000 degree(s)C can be used to break-up the interfacial oxide in the polysilicon emitter contact to provide enhanced current gain with low-emitter resistance but with little impact on the CMOS. The RTA emitter anneal also serves to simultaneously flow BPSG to planarize the wafer prior to metallization. Contact reflow is also advantageous for a tapered structure to improve metal step-coverage.

Reuss, Robert H.

1994-02-01

62

Design And Testing Of SEU\\/ SEL Immune Memory And Logic Circuits In A Commercial Cmos Process  

Microsoft Academic Search

Test results for logic\\/circuit hardened memory circuits verify upset and latch-up immunity of greater than 120 MeV - cm2\\/mg using a commercial, non-radiation hardened CMOS process. An SEU immune logic family is also described.

Don Wiseman; John Canaris; Sterling Whitaker; Jack Venbrux; Kelly Cameron; Kari Arave; Larry Arave; M. Norley Liu; Kathy Liu

1993-01-01

63

Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process  

Microsoft Academic Search

AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35mum CMOS process

Dong-shong Liang; Cheng-chi Tai; Kwang-jow Gan; Cher-shiung Tsai; Yaw-hwang Chen

2006-01-01

64

New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only)  

Microsoft Academic Search

Over the last 15 years, CMOS scaling simplified the task of the microprocessor architect. With each new process technology, frequency increased by -50%, and transistor density increase by 100 percent. Also, the improvements in manufacturing technology (larger wafers and higher yields) allowed for increasing die sizes without increasing cost. Projections of die sizes of 1 square inch or higher were

Fred J. Pollack

1999-01-01

65

Overview of CMOS process and design options for image sensor dedicated to space applications  

Microsoft Academic Search

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been

P. Martin-Gonthier; P. Magnan; F. Corbiere

2005-01-01

66

A signal-processing CMOS image sensor using a simple analog operation  

Microsoft Academic Search

A high-density CMOS image sensor has a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel and real-time operation are achieved by using a four-transistor pixel scheme and column-parallel on-chip analog operation

Y. Muramatsu; S. Kurosawa; M. Furumiya; H. Ohkubo; Y. Nakashiba

2001-01-01

67

A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process  

Microsoft Academic Search

A novel programmable element has been developed and evaluated for state of the art CMOS processes. This element is based on agglomeration of the Ti-silicide layer on top of poly fuses. Various aspects of this programmable device including characterization and optimization of physical and electrical aspects of the element, programming yield, and reliability have been studied. Development of a novel

Mohsen Alavi; Mark Bohr; Jeff Hicks; Martin Denham; Allen Cassens; Dave Douglas; Min-Chun Tsai

1997-01-01

68

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS  

Microsoft Academic Search

The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

Martin von Arx; Oliver Paul; Henry Baltes

2000-01-01

69

Overview of CMOS process and design options for image sensor dedicated to space applications  

NASA Astrophysics Data System (ADS)

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35?m generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

70

Smart optical and image sensors fabricated with industrial CMOS/CCD semiconductor processes  

NASA Astrophysics Data System (ADS)

Photosensitive elements with well-chosen geometry, combined with suitable analog and digital circuitry on the same CMOS/CCD chip, lead to 'smart image sensors' with interesting capabilities and properties. All our smart sensors were fabricated with commercially available multi-process wafer services of CMOS process, one of them with a buried-channel CCD option. Measurement of the optoelectronic properties of standard CMOS/CCD processes (wavelength-dependent quantum efficiency, lateral homogeneity of quantum efficiency/photo- conductivity, CCD charge transport efficiency, etc.) show excellent performance. The smartness that lies in the geometry is illustrated with a single-chip motion detector, a 3-D depth video camera, a single-chip planar distance sensor, and a sine/cosine (Fourier) transform sensor for fast optical phase measurements. The concept of problem-adapted geometry is also shown with a dynamic frame-transfer CCD whose pixel size and shape can be changed electrically in real-time through charge-binning. Based on the wavelength-dependent absorption of silicon, all-solid-state color pixels are demonstrated by properly arranging the available pn-junctions in the third (bulk) dimension. Moderate color measurement performance is achieved using an unmodified CMOS/CCD process, with a CIE general color-rendering index of Ra equals 69.5.

Seitz, Peter; Leipold, Dirk; Kramer, Joerg; Raynor, Jeffrey M.

1993-07-01

71

Monolithic integration of capacitive sensors using a double-side CMOS MEMS post process  

NASA Astrophysics Data System (ADS)

This study presents a novel double-side CMOS (complementary metal-oxide-semiconductor) post-process to monolithically integrate various capacitance-type CMOS MEMS sensors on a single chip. The CMOS post-process consists of three steps: (1) front-side bulk silicon etching, (2) backside bulk silicon etching and (3) sacrificial surface metal layers etching. Using a TSMC 2P4M CMOS process and the present double-side post-process this study has successfully integrated several types of capacitive transducers and their sensing circuits on a single chip. Monolithic integration of pressure sensors of different sensing ranges and sensitivities, three-axes accelerometers, and a pressure sensor and accelerometer are demonstrated. The measurement results of the pressure sensors show sensitivities ranging from 0.14 mV kPa-1 to 7.87 mV kPa-1. The three-axes accelerometers have a sensitivity of 3.9 mV G-1 in the in-plane direction and 0.9 mV G-1 in the out-of-plane direction; and the accelerated measurement ranges from 0.3 G to 6 G.

Sun, Chih-Ming; Wang, Chuanwei; Tsai, Ming-Han; Hsieh, Hsieh-Shen; Fang, Weileun

2009-01-01

72

CMOS camera with on-chip signal processing for optical correlators  

NASA Astrophysics Data System (ADS)

The design and simulation results of a 64 X 64 pixels smart CMOS photodiode sensor array are presented. The chip is capable of capturing an image as well as performing real time on-chip signal processing on 3 X 3 kernel array of the image. The size of the optical system is significantly reduced by integrating the signal processing circuits on chip. It is particularly suitable for applications such as optical correlators or image processing system. The chip is designed using 0.8 micrometers standard CMOS process technology. It is incorporated with processing circuitry to implement low-pass and high-pass image filters as well as the processing algorithm required by a 1/f binary phase optical correlation system.

Kwok, Terence C.; Wilkinson, Tim D.; Crossland, William A.

2001-12-01

73

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process  

Microsoft Academic Search

A new gateless anti-fuse cell with 45 nm CMOS fully compatible process has been developed for advanced programmable logic applications. This gateless anti-fuse cell processed by pure logic process and decoupled with logic gate oxide has a highly stable and five orders of on\\/off current window. It also exhibits superior program performance by only 5 V operation with no more

Yi-Hung Tsai; Hsin-Ming Chen; Hsin-Yi Chiu; Hung-Sheng Shih; Han-Chao Lai; Ya-Chin King; Chrong Jung Lin

2007-01-01

74

Gamma radiation damage study of 0.18 m process CMOS image sensors  

NASA Astrophysics Data System (ADS)

A 0.18 ?m process CMOS image sensor has recently been developed by e2v technologies plc. with a 0.5 megapixel imaging area consisting of 6 6 ?m 5T pixels. The sensor is able to provide high performance in a diverse range of applications including machine vision and medical imaging, offering good low-light performance at a video rate of up to 60 fps. The CMOS sensor has desirable characteristics which make it appealing for a number of space applications. Following on from previous tests of the radiation hardness of the image sensors to proton radiation, in which the increase in dark-current and appearance of bright and RTS pixels was quantified, the sensors have now been subjected to a dose of gamma radiation. Knowledge of the performance after irradiation is important to judge suitability for space applications and radiation sensitive medical imaging applications. This knowledge will also enable image correction to mitigate the effects and allow for future CMOS devices to be designed to improve upon the findings in this paper. One device was irradiated to destruction after 120 krad(Si) while biased, and four other devices were irradiated between 5 and 20 krad(Si) while biased. This paper explores the resulting radiation damage effects on the CMOS image sensor such as increased dark current, and a central brightening effect, and discusses the implications for use of the sensor in space applications.

Dryer, Ben; Holland, Andrew; Murray, N. J.; Jerram, Paul; Robbins, Mark; Burt, David

2010-07-01

75

Integration of a long pulse laser thermal process for ultra shallow junction formation of CMOS devices  

Microsoft Academic Search

We present results on ultra-shallow junction formation for the sub 65 nm CMOS node by means of a long pulse laser thermal process (LP-LTP). This method achieve to form abrupt and ultra-shallow junctions with low resistivities, but the different irradiated structures like transistor gates need to be preserved. To assess the integration of the laser process in the fabrication of

J. Venturini; M. Hernandez; K. Huet; C. Laviron; H. Akhouayri; T. Sarnet; J. Boulmer

2004-01-01

76

Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing  

Microsoft Academic Search

A monolithic tin oxide (SnO2) gas sensor realized by commercial CMOS foundry fabrication (MOSIS) and postfabrication processing techniques is reported. The device is composed of a sensing film that is sputter-deposited on a silicon micromachined hotplate. The fabrication technique requires no masking and utilizes in situ process control and monitoring of film resistivity during film growth. Microhotplate temperature is controlled

John S. Suehle; Richard E. Cavicchi; Michael Gaitan; Steve Semancik

1993-01-01

77

A discrete-time Bluetooth receiver in a 0.13?m digital CMOS process  

Microsoft Academic Search

A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13?m digital CMOS process.

K. Muhammad; D. Leipold; B. Staszewski; Y.-C. Ho; C. M. Hung; K. Maggio; C. Fernando; T. Jung; J. Wallberg; J.-S. Koh; S. John; I. Deng; O. Moreira; R. Staszewski; R. Katz; O. Friedman

2004-01-01

78

Thermal budget limits of quarter-micrometer foundry CMOS for post-processing MEMS devices  

Microsoft Academic Search

Thermal budget limits for low stand-by power ( LSP), 0.25 ?m foundry CMOS devices have been investigated, in order to assess the impact of post-processing microelectromechanical devices devices. Resistance increases for vias (metal-to-metal contacts) rather than transistor-performance shifts limits the post-processing thermal budget. An empirical relation is found to predict the via resistance increase for various annealing conditions, based on

Hideki Takeuchi; Amy Wung; Xin Sun; Roger T. Howe; Tsu-Jae King

2005-01-01

79

A study of gateless OTP cell using a 45 nm CMOS compatible process  

Microsoft Academic Search

This work proposes a new gateless one-time programmable (OTP) cell. This gateless OTP cell has a parasitic oxidenitrideoxide (ONO) structure as the storage node and is successfully demonstrated in a 45nm CMOS logic process. This gateless OTP cell, formed in a pure logic process and decoupled from gate oxide, is highly stable with a five orders of on\\/off current window.

Yi-Hung Tsai; Kai-Chun Lin; Hsin-Yi Chiu; Hung-Sheng Shih; Ya-Chin King; Chrong Jung Lin

2009-01-01

80

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes  

Microsoft Academic Search

This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog\\/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of

Julian Zhiliang Chen; E. Ajith Amerasekera; Charvaka Duvvury

1998-01-01

81

Efficient smart CMOS camera based on FPGAs oriented to embedded image processing.  

PubMed

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Bravo, Ignacio; Balias, Javier; Gardel, Alfredo; Lzaro, Jos L; Espinosa, Felipe; Garca, Jorge

2011-02-24

82

A CMOS SPDT switch  

Microsoft Academic Search

In this work, a novel architecture with stacked-type CMOS device is presented. The reformed CMOS switch was implemented by the TSMC 0.18 um 1P6M standard CMOS process. In order to improve power handling capability and strengthen the isolation, the proposed circuit is inserted with an excess transistor adjacent to the receiver side. The insertion loss of the designed CMOS T\\/R

Jheng-Da Wu; Janne-Wha Wu; Chih-Ho Tu; Ching-Wen Tang; Chien-You Lai; Bing-Jiun Lai; Wei-Ju Lai; Liang-Yeh Chi; Ying-Zong Juang

2008-01-01

83

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications  

NASA Astrophysics Data System (ADS)

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-10-01

84

Design of 1-THz field effect transistor detectors in 180-nm standard CMOS process  

NASA Astrophysics Data System (ADS)

This paper presents a design of 1-THz imaging detectors implemented in 180-nm standard CMOS process. Device simulator is adopted to simulate the performances of the detectors and the results are well consistent with the theoretical predictions. An on-chip patch antenna is designed aided by HFSS. The simulated peak directivity and gain of antenna are 6.9dBi and 4.4dBi, respectively. The -10dB impedance bandwidth of the antenna is 28 GHz, which corresponds to 2.8% relative bandwidth. To improve power transfer efficiency, we extract the input impedance of the MOSFET and design a matching network inserted between the MOSFET and antenna. Imaging pixels have been arranged in a 3 x 5 array in 180-nm standard CMOS process.

Liu, Zhao-yang; Liu, Li-yuan; Wu, Nan-jian

2013-08-01

85

On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations  

Microsoft Academic Search

This paper describes an on-die leakage current sensor in 1.2V, 90nm CMOS technology for accurately measuring process variation. Results based on measured leakage data show (i) higher signal-to-noise ratio and (ii) reduced sensitivity to supply and P\\/N skew variations compared to prior designs, while the proposed sensor only requires a single bias generator even for multi-bit resolution sensing. A 6-channel

C. H. Kim; K. Roy; S. Hsu; R. K. Krishnamurthy; S. Borkar

2004-01-01

86

A 10 ?m thick poly-SiGe gyroscope processed above 0.35 ?m CMOS  

Microsoft Academic Search

This paper describes a monolithically integrated omegaz-gyroscope fabricated in a surface-micromaching technology. As functional structure, a 10 mum thick Silicon-Germanium layer is processed above a standard high voltage 0.35 mum CMOS-ASIC. Drive and Sense of the in plane double wing gyroscope is fully capacitively. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope

A. Scheurle; T. Fuchs; K. Kehr; C. Leinenbach; S. Kronmuller; A. Arias; J. Ceballos; M. A. Lagos; J. M. Muoz; A. Ragel; J. Ramos; S. Van Aerde; J. Spengler; A. Mehta; A. Verbist; B. Du Bois; A. Witvrouw

2007-01-01

87

Application of quantum well-like thermocouple to thermoelectric energy harvester by BiCMOS process  

Microsoft Academic Search

This work aims at improving the energy harvester performance by using low-dimensional thermoelectric materials. A micro-thermoelectric generator (?TEG) with quantum well-like thermocouples is developed by state-of-the-art CMOS (Complementary metal-oxide semiconductor) process. A relaxation-time model is applied to analyze the characteristic length of silicon germanium quantum well, and a thermal model is also applied to calculate the thermocouple size for optimal

S. M. Yang; M. Cong; T. Lee

2011-01-01

88

A low supply voltage high PSRR voltage reference in CMOS process  

Microsoft Academic Search

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm2, a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes

Khong-Meng Tham; Krishnaswamy Nagaraj

1995-01-01

89

A high d33 CMOS compatible process for aluminum nitride on titanium  

Microsoft Academic Search

We present a CMOS compatible fabrication process which utilizes aluminum nitride with titanium electrodes for high-speed piezoelectric actuation. Aluminum nitride film morphology was improved by maintaining vacuum between film depositions and by the inclusion of an aluminum nitride interlayer. A rocking curve full-width at half-maximum of less than 3 degrees was achieved. Unimorph actuators were fabricated from silicon cantilevers and

J. C. Doll; B. C. Petzold; B. Ninan; R. Mullapudi; B. L. Pruitt

2009-01-01

90

Thermally robust dual-work function ALD-MNx MOSFETs using conventional CMOS process flow  

Microsoft Academic Search

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si\\/metal nitrides (MNx) SiON (or high-k)\\/Si stack with atomic layer deposition (ALD)-TaNx for the NFET and ALD-WNx for the PFET. Much enhanced drive current (Id) and transconductance (Gm) values, and reduced off current (Ioff) characteristics were attained with ALD-MNx gated

D.-G. Park; Z. J. Luo; N. Edleman; W. Zhu; P. Nguyen; K. Wong; C. Cabral; P. Jamison; B. H. Lee; A. Chou; M. Chudzik; J. Bruley; O. Gluschenkov; P. Ronsheim; A. Chakravarti; R. Mitchell; V. Ku; H. Kim; E. Duch; P. Kozlowski; C. D'Emic; V. Narayanan; A. Steegen; R. Wise; R. Jammy; R. Rengarajan; H. Ng; A. Sekiguchi; C. H. Wann

2004-01-01

91

Fabrication of CMOS circuits using non-etchback SOG processing for dielectric planarization  

Microsoft Academic Search

Planarization of interlevel dielectrics by nonetchback spin-on glass (SOG) techniques requires the use of a dense, inorganic SOG with good dielectric characteristics. The authors have evaluated two recently developed phosphosilicate-type SOG materials, Accuglass P-114 and P-114A, for use in nonetchback processing. Both materials were successfully applied to the fabrication of 1.2-?m CMOS ASIC circuits. Extensive reliability tests, including thermal stressing

H. W. M. Chung; S. K. Gupta; T. A. Baldwin

1989-01-01

92

High-Voltage Hall-Effect Sensor Interface in a Standard Digital CMOS Process  

Microsoft Academic Search

A high-voltage Hall-effect sensor interface realized in a 5V 0.6 mum CMOS process using 40V high-voltage devices is presented. The design includes a high-voltage operational transconductance amplifier, which achieves a common-mode input range that is within a VTP of the upper rail with the use of a bulk-driven input stage. Also discussed is a reverse voltage protection architecture that uses

Riley Beck; Michael Riggs; D. Corner; Donald Comer

2006-01-01

93

Integration of hydrogen silsesquioxane into an advanced BiCMOS process  

NASA Astrophysics Data System (ADS)

Performance of advanced integrated circuit (IC) technology is becoming dominated by interconnect RC propagation delays making the introduction of lower capacitance insulators very attractive. The use of low dielectric constant (low-k) materials will be a key challenge for future interconnect technologies. In the case of BiCMOS technology for RF applications, an additional consideration is to minimize parasitic capacitance of passive components such as inductors, buses, and bond pads. The use of hydrogen silsesquioxane (HSQ) with a dielectric constant of about 3.0 allowed the construction of high quality spiral inductors in a 0.5 micrometer BiCMOS technology. In addition to its low-k properties, the HSQ spin-on dielectric was used for planarization of three polycrystalline silicon layers and four levels of metal interconnects. The HSQ layer was applied in a single coat application in a non-etchback process that achieved excellent planarity with good crack resistance. The stability of blanket HSQ films was shown using FTIR spectra, film stress, and capacitance data. Immunity of devices to hot carrier lifetime degradation was demonstrated. Low resistance and high yield for long metal via chains were obtained by careful integration of the via etch, resist strip and metal deposition processes. Thus we demonstrated the integration of HSQ planarization into an advanced BiCMOS process to take advantage of its excellent planarity and its low dielectric constant.

Olewine, Michael; Wall, Ralph; Colovos, Gus J.

1998-09-01

94

Analog CMOS design for optical coherence tomography signal detection and processing.  

PubMed

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented. PMID:18269983

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

95

High-speed bipolar phototransistors in a 180 nm CMOS process  

NASA Astrophysics Data System (ADS)

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 4040 ?m2 and 100100 ?m2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p- epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Kostov, P.; Gaberl, W.; Zimmermann, H.

2013-03-01

96

A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop  

NASA Astrophysics Data System (ADS)

A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 ?m CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within 0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.

Qianqian, Lei; Min, Lin; Yin, Shi

2013-03-01

97

High-speed bipolar phototransistors in a 180 nm CMOS process  

PubMed Central

Several high-speed pnp phototransistors built in a standard 180nm CMOS process are presented. The phototransistors were implemented in sizes of 4040?m2 and 100100?m2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p? epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850nm. Bandwidths up to 92MHz and dynamic responsivities up to 2.95A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Kostov, P.; Gaberl, W.; Zimmermann, H.

2013-01-01

98

A 464 pixel CMOS image sensor for 3D measurement applications  

Microsoft Academic Search

A 464 pixel CMOS image sensor which can capture three-dimensional images has been integrated in a 0.5?m n-well standard CMOS processes. It is based on time-of-flight method and employs an active laser pulse illumination at 900nm optical wavelength. System bandwidth is limited by the refreshing time of the active laser source. The sensor employs the so-called \\

O. M. Schrey; O. Elkhalili; P. Mengel; M. Petermann; W. Brockherde; B. J. Hosticka

2003-01-01

99

A CMOS Area Image Sensor With Pixel Level A\\/D Conversion  

Microsoft Academic Search

A CMOS 64 64 pixel area image sensor chip using Sigma-Delta modulation at each pixel for A\\/D conversion is described. The image data output is digital. The chip was fabricated using a 1.2 mt wo layer metal single layer poly n-well CMOS process. Each pixel block consists of a phototransistor and 22 MOS transistors. Test results demonstrate a dynamic

Boyd Fowler; Abbas El Gamal; David X. D. Yang

1995-01-01

100

Evaluation and verification of improved edgebead removal process in CMOS production  

NASA Astrophysics Data System (ADS)

This paper describes an engineering approach that was taken to improve an existing edgebead removal process which used acetone exclusively. Production problems were encountered after exposure and develop of positive photoresist: after the UV bake step. These problems were manifested by popping photoresist. The approach taken here was to evaluate acetone by itself as an edgebead remover and compare it with a commercially available EBR. Specifically, a combination of ethyl lactate and 2-pentanone. The improved edgebead removal process is presented as a function of photoresist popping after the UV bake step for our CMOS process.

Christensen, Lorna D.; Marchione, M.; Luce, K.

1995-06-01

101

An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier  

NASA Astrophysics Data System (ADS)

We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 3280 element CMOS active pixel array was implemented in a 0.8?m CMOS double poly, n-well process with a pixel pitch of 50?m. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

Abdalla, M. A.; Frjdh, C.; Petersson, C. S.

2001-06-01

102

A merged MEMS-CMOS process using silicon wafer bonding  

Microsoft Academic Search

A process for fabricating integrated silicon micromachined sensors is demonstrated. The process uses silicon wafer bonding to create a substrate that can be inserted into an existing IC fabrication line without perturbation of the line. After circuits are completed, micromachining steps are performed to release the silicon membranes and form the sensors. A variety of test structures including MOSFETs, piezoresistive

Lalitha Parameswaran; Charles Hsu; Martin A. Schmidt

1995-01-01

103

Photo-Spectrometer Realized In A Standard Cmos Ic Process  

DOEpatents

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Simpson, Michael L. (Knoxville, TN); Ericson, M. Nance (Knoxville, TN); Dress, William B. (Knoxville, TN); Jellison, Gerald E. (Oak Ridge, TN); Sitter, Jr., David N. (Tucson, AZ); Wintenberg, Alan L. (Knoxville, TN)

1999-10-12

104

A high performance, low complexity 14V Complementary BiCMOS process built on bulk silicon  

Microsoft Academic Search

This paper details a new 14V Complementary BiCMOS (CBiCMOS) addition to the TowerJazz SBC35 family of BiCMOS technologies. The SBC35 family previously supported BVceo values up to 6V. The bipolar architecture is nearly identical with that used in the lower voltage technologies, leveraging 10 years of manufacturing history. The complementary bipolar transistors are paired with 5V CMOS currently available in

Todd Thibeault; Edward Preisler; Jie Zheng; Lynn Lao; Paul Hurwitz; Marco Racanelli

2010-01-01

105

Process issues in the development of a ferroelectric capacitor/CMOS test chip  

NASA Astrophysics Data System (ADS)

Processing details are discussed in the development of a procedure to fabricate lead-zirconate-titanate (PZT) ferroelectric capacitors on a CMOS test chip for purposes of electrical and radiation characterization studies. During the course of this work, several problems were encountered in the deposition and photoengraving of the platinum electrodes that form the conducting plates of the capacitor. Both dry and wet etching techniques were employed in an effort to define the top platinum electrodes. Solutions are discussed for those problems solved during this initial development phase.

Rod, Bernard J.

1991-12-01

106

Reliability of Surface MEMS Structures Fabricated Using Standard CMOS Back-End-Of-Line Processes  

NASA Astrophysics Data System (ADS)

Reliability of surface MEMS fabricated with standard CMOS back-end-of-line (BEOL) processes was investigated by several film analyses and by monitoring change in MEMS properties after standard pressure cooker test (PCT). A significant change in MEMS characteristics was observed after PCT for samples with SiN passivation layer thinner than 100nm, while for passivation layer thicker than 150nm, no change was observed. A large shift in film stress after PCT and results from TDS (Thermal Desorption Spectroscopy) and XRR (X-ray reflectometry) suggested that this is due to water release from SiO2 film used in the structure.

Hanaoka, Yuko; Fujimori, Tsukasa; Fujisaki, Koji; Fukuda, Hiroshi

107

Designing manufacturable MEMS in CMOS-compatible processes: methodology and case studies  

NASA Astrophysics Data System (ADS)

Designing manufacturable MEMS devices requires a strong link between design and process engineers. Establishing systematic design principles through a common CAD framework facilitates this. A methodology for MEMS Design for Manufacturing (DFM) is presented that focuses on solid process and design qualification through systematic parametric modeling and testing, from initial development of specifications to volume manufacturing. This strategy has been applied to two MEMS fabrication processes, including CMOS-compatible SOI micromachining and metal-nitride surface micromachining. Case studies of designed, simulated, fabricated and characterized test structures demonstrate the methodology and benefits of the outlined DFM approach - including extraction of material properties and process capabilities enabling a prediction of fabricated device performance distribution. The overall result is a MEMS product design framework that incorporates a top-down design methodology with parametric re-usable libraries of MEMS, IC and relevant system components capable of allowing to design within a specific process (via a process design kit) to enable virtual manufacturing.

Schropfer, Gerold; McNie, Mark; da Silva, Mark; Davies, Rhodri; Rickard, Alexandra; Musalem, Francois-Xavier

2004-08-01

108

Towards on-chip integration of brain imaging photodetecors using standard CMOS process.  

PubMed

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration. PMID:24110276

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-07-01

109

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology  

NASA Astrophysics Data System (ADS)

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.

Ajayan, K. R.; Bhat, Navakanta

2012-10-01

110

Cell-based fully integrated CMOS frequency synthesizers  

Microsoft Academic Search

A family of standard cells for phase-locked loop (PLL) applications is presented. The applications are processed using a 1.5 ?m, n-well, double-polysilicon, double-layer metal CMOS process. Applications include frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components since the loop filter

Dejan Mijuskovic; Martin Bayer; Thecla Chomicz; N. Garg; F. James; P. McEntarfer; J. Porter

1994-01-01

111

A new design for a 12801024 digital CMOS image sensor with enhanced sensitivity, dynamic range and FPN  

Microsoft Academic Search

This paper reports a 1.3 M-pixel CMOS image sensor with 5 ?m5 ?m pixel size fabricated with a standard 0.35 ?m CMOS logic process. Three techniques have been applied to improve the chip performance: an N-well photodiode to increase the quantum efficiency for light of long wavelengths; two-stage integration to enhance the performance under high illumination conditions; and capacitor-coupled readout

Jih-Shin Ho; Ming-Cheng Chiang; Han-Min Cheng; Tzu-Ping Lin; Ming-Jer Kao

1999-01-01

112

A robust color signal processing with wide dynamic range WRGB CMOS image sensor  

NASA Astrophysics Data System (ADS)

We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor. The image sensor was fabricated through a 0.18 ?m CMOS technology and has a 45 degrees oblique pixel array, the 4.2 ?m effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY) signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate color processing with a large margin to the sensitivity fluctuation and noise has been achieved.

Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

2011-01-01

113

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process.  

PubMed

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-09-25

114

An RF LDMOS with excellent efficiency and ruggedness based on a modified CMOS process  

NASA Astrophysics Data System (ADS)

Two types of RF LDMOS devices, specified for application in the driver stage and output stage of a power amplifier, are designed based on a modified CMOS process. By optimizing the layout and process, the output capacitance per unit of gate width is as low as 225 fF/mm. The driver stage and output stage devices achieve an output power of 44 W with a PAE of 82% and 230 W with a PAE of 72.3%, respectively (P3dB compression) at 1 GHz. Both devices are capable of withstanding extremely severe ruggedness tests without any performance degradation. These tests are 3-5 dB overdrive, 10:1 voltage standing wave ratio mismatch load through all phase angles, and 40% drain overvoltage elevation at a working point of P3dB.

Ting, Yu; Ling, Luo

2013-09-01

115

Development of a novel thermal switch through CMOS MEMS fabrication process  

NASA Astrophysics Data System (ADS)

This paper focuses on implementing two novel CMOS-MEMS type switches: buckling type and thermal type, by using commercially available TSMC 0.35 ?m two-poly four-metal (2P4M) CMOS process. There are two novel designs in these two type switches: first, the soft contact structure with post-processing fabrication; second, using residual stress to achieve large structural deformation in buckling type and thermal type switches. To create the soft contact structure, residual gradient stress effect has been utilized to make bending-down curvatures. According to the experiments, the layer Metal1 has the largest negative residual gradient stress effect that can achieve the largest negative deflection in z-axis. Because the structure will bend down after post-processing release, larger lateral contact area are set up to gain the lower contact miss ability. In the post-processing fabrication, 0.3?m thickness gold will be deposited on the contact tips. Due to the essence of gold, comparing with aluminum, has no oxidation issue, gold also has the advantage of higher conductivity to reduce the electrical power loss. In the buckling type design, the switch uses residual stress to achieve lateral buckling effect to solve long distance problem. In the thermal type design, this paper design a folded-flexure with the electro-thermal excitation to turn the switch on or off. In the prototype, the device size is 500 ?m x 400 ?m and the gap between two contact pads is 9 ?m in off-state. on the experimental results, the switch can work stably at 3 volts, and the displacement of the thermal type switch can achieve 2.7?m, which is sufficient for the mechanism of switching-on or switching-off.

Lai, You-Liang; Chou, Lei-Chun; Juang, Ying-Zong; Tsai, Hann-Huei; Huang, Sheng-Chieh; Chiou, Jin-Chern

2011-02-01

116

Using Ion Implantation to Streamline High Volt Processing in Standard CMOS  

NASA Astrophysics Data System (ADS)

In a standard 0.5 ?m single well technology, a deep N-well is constructed using a 150 keV P implant at a dose of 1e13 at/cm2 and driven to a final depth of 4 ?m. To make this N-well suitable for automotive battery applications it is constructed with 2 ?m P-tub enclosure. Use of a high energy (780 keV P+++) implant streamlined the requisite long diffusion cycle such that it could be processed in a standard diffusion drive. While this resulted in longer implant times, it reduced the overall cycle time for a low volume, high voltage custom devices.

Naughton, John J.; Towner, Janet M.

2008-11-01

117

Microprocessor reliability performance as a function of die location for a 0.25 ?, five layer metal CMOS logic process  

Microsoft Academic Search

In this paper, we present the results of multiple correlations between reliability (infant mortality and other reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 ?m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield

Walter Carl Riordan; Russell Miller; John M. Sherman; Jeffrey Hicks

1999-01-01

118

An intelligent power module for IGBT gate driver implemented in 0.8 ?m high voltage CMOS process  

Microsoft Academic Search

In this paper, we design and implement a monolithic IGBT gate driver for intelligent power modules (IPMs) in a high voltage (50 V) 0.8 ?m CMOS process. The efficient and various protection functions are included in the IGBT gate driver. The gate driver is designed for medium power applications, such as home appliances. It includes low voltage logic, 5 V

E. D. Kim; N. K. Kim; S. C. Kim; W. Bahng; G. H. Song; S. B. Han

2001-01-01

119

Intelligent CMOS sensors  

Microsoft Academic Search

CMOS including micromechanics using polysilicon structures as functional layers is a promising technology for production of Intelligent CMOS Sensors. Its cost and performance advantages allow to address volume markets like monolithic integrated sensors for automotive application. Using modern silicon processes and their potential for large scale integration, new functions like on-chip calibration and diagnosis are possible. Furthermore, it offers direct

Christofer Hierold

2000-01-01

120

Scaling Behavior of Carbon Nanotube-based Biosensors Integrated on CMOS Signal-processing Circuits  

NASA Astrophysics Data System (ADS)

We built uniform arrays of carbon nanotube (CNT)-based biosensors via linker-free directed assembly strategy, where surface molecular patterns were utilized to direct the assembly of CNTs onto specific regions of the devices. The sensor arrays were utilized to detect ammonia and Hg^+ ions with high sensitivity and selectivity, and the scaling behavior of sensor sensitivity was studied by parallel detection of multiple sensors. We found that the scaling behavior of the sensor sensitivity can be explained by the combination of two effects: adsorption of analyte molecules onto CNT surface and the transconductance change of the CNT junctions. Furthermore, 64 CNT-based sensors were integrated with CMOS circuits into a single-die system-on-a-chip for the detection of glutamate, a neurotransmitter, by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors.

Lee, Byung Yang; Sung, Moon Gyu; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cho, Eunju; Hong, Seunghun; Seo, Sung Min; Cheon, Jun-Ho; Lee, Hyunjoong; Kim, Suhwan; Park, Young June; Chung, In-Young

2010-03-01

121

Feasibility of a novel modular approach for planarization of a submicron triple-level metal CMOS process  

Microsoft Academic Search

The feasibility of a triple-level-metal submicron CMOS process using proven and manufacturable modules is demonstrated. While resist etchback and a silicate SOG (spin-on glass) sandwich are used for planarization at the polysilicon and first metal, respectively, neither of these process modules is feasible for the second-metal planarization due to the severe aspect ratios at this stage of the process. With

N. Parekh; A. Butler; W. Doedel; W. Heesters; L. Forester

1990-01-01

122

Monolithic process for co-integration of GaAs MESFET and silicon CMOS devices and circuits  

NASA Astrophysics Data System (ADS)

A monolithic process to cointegrate Si CMOS and GaAs MESFET devices and circuits on a silicon chip through epitaxial growth of a GaAs layer on a prefabricated Si wafer is described. By embedding the GaAs layer in Si recesses in selected regions of a Si wafer, the cointegration has been realized in a coplanar structure appropriate for IC processing. On a monolithically integrated wafer, a 2-micron gate length Si CMOS ring oscillator showed a minimum delay of 570 ps/gate, and a 1-micron gate GaAs MESFET BFL ring oscillator had a minimum delay of 68 ps/gate. These results indicate that the individual device speed is not degraded by monolithic integration. Some changes in threshold voltage, however, were observed for Si CMOS devices after the GaAs device fabrication. A composite ring oscillator consisting of a string of Si CMOS inverters and a string of GaAs MESFET inverters connected in a ring has been successfully fabricated.

Shichijo, Hisashi; Taddiken, Albert H.; Kao, Yung-Chung; Matyi, Richard

1990-03-01

123

One-M bit CMOS Dynamic RAM.  

National Technical Information Service (NTIS)

Described herein is a 1-M words x 1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology. More than 2.2 millions of element devices are integrated on a 62.5-sq. mm. silicon chip employing an n-channel memory cell of triple-layer polysil...

S. Saito S. Fujii Y. Matsumoto

1985-01-01

124

Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing.  

PubMed

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

125

Performance of buried channel n-type MOSFETs in 0.18-?m CMOS image sensor process  

NASA Astrophysics Data System (ADS)

Buried channel (BC) MOSFETs are known to have better noise performance than surface channel (SC) MOSFETs when used as source followers in modern Charge Coupled Devices (CCD). CMOS image sensors find increasing range of applications and compete with CCDs in high performance imaging, however BC transistors are rarely used in CMOS. As a part of the development of charge storage using BC CCDs in CMOS, we designed and manufactured deep depletion BC n-type MOSFETs in 0.18 ?m CMOS image sensor process. The transistors are designed in a way similar to the source followers in a typical BC CCD. In this paper we report the results from their characterization and compare with enhancement mode and "zero-threshold" SC devices. In addition to the detailed current-voltage and noise measurements, semiconductor device simulation results are presented to illustrate and understand the different conditions affecting the channel conduction and the noise performance of the BC transistors at low operating voltages. We show that the biasing of the BC transistors has to be carefully adjusted for optimal operation, and that their noise performance at the right operating conditions can be superior to SC devices, despite their lower gain as in-pixel source followers.

Stefanov, Konstantin D.; Zhang, Zhige; Damerell, Chris; Burt, David; Kar-Roy, Arjun

2013-09-01

126

Ultra-Compact High-Linearity High-Power Fully Integrated DC20GHz 0.18- CMOS T\\/R Switch  

Microsoft Academic Search

A fully integrated ultra-broadband transmit\\/receive (T\\/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T\\/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an

Yalin Jin; Cam Nguyen

2007-01-01

127

A single-pass, in-situ planarization process utilizing TEOS for double-poly, double-metal CMOS technologies  

Microsoft Academic Search

A planarization technique utilizing in situ etching of TEOS-based CVD oxide is presented. The process includes TEOS\\/O2-based PECVD oxide, TEOS\\/O3-based LPCVD oxide, Ar+ sputter etching, and CF4-based reactive ion etching, all in a single pumpdown. This planarization process has been successfully used to fabricate advanced double-poly double-metal circuits on 0.8-?m CMOS technologies. E-test structures indicate low via resistance (0.15 ?\\/via)

S. Mehta; G. Sharma

1989-01-01

128

A novel SnO 2\\/Al discrete gate ISFET pH sensor with CMOS standard process  

Microsoft Academic Search

In this paper, we present a method allowing industrial production of integrated ion sensitive field effect transistor (ISFET) sensor. An ASIC CMOS standard process is used to integrate the sensor and signal processing circuit; then the sensor is plated with the sensing membrane (SnO2) by sputtering. The structure of the ISFET is novel SnO2\\/Al discrete gate. The discrete gate ISFET

Yuan-Lung Chin; Jung-Chuan Chou; Tai-Ping Sun; Hung-Kwei Liao; Wen-Yaw Chung; Shen-Kan Hsiung

2001-01-01

129

A buried-channel charge-coupled device with non-overlapping gate structure for a CMOS\\/BCCD process  

Microsoft Academic Search

A buried-channel CCD is presented, suitable for integration in a high-energy ion-implanted CMOS process. The BCCD channel is high-energy ion-implanted and the gate structure is non-overlapping. The required submicron spacings between adjacent gates are created by a sequence of processing steps. No demands are imposed on the lithography used. SEM photographs show a well-defined gate structure with straight spacings exhibiting

L. Warmerdam; H. Wallinga

1992-01-01

130

FDTD-based optical simulations methodology for CMOS image sensors pixels architecture and process optimization  

Microsoft Academic Search

This paper presents a new FDTD-based optical simulation model dedicated to describe the optical performances of CMOS image sensors taking into account diffraction effects. Following market trend and industrialization constraints, CMOS image sensors must be easily embedded into even smaller packages, which are now equipped with auto-focus and short-term coming zoom system. Due to miniaturization, the ray-tracing models used to

Flavien Hirigoyen; Axel Crocherie; Jrme M. Vaillant; Yvon Cazaux

2008-01-01

131

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process  

Microsoft Academic Search

A new 45 nm multiple time programming (MTP) cell with self-aligned nitride storage node has been proposed for logic NVM applications. The CMOS fully logic compatible cell has been successfully demonstrated in 45 nm CMOS technology with an ultra small cell size of 0.14 mum2. This cell adapting source side injection programming scheme has a wide on\\/off window and superior

Chia-En Huang; Hsin-Ming Chen; Han-Chao Lai; Ying-Je Chen; Ya-Chin King; Chrong Jung Lin

2007-01-01

132

Design and implementation of non-linear image processing functions for CMOS image sensor  

NASA Astrophysics Data System (ADS)

Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 6464 pixels image sensor built in a standard CMOS Technology 0.35 ?m including non-linear image processing. The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 22 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 4040 mu m. The total area of the 6464 pixels is 12.5mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (10K frames per second), minima/maxima calculations in less then one ms.

Musa, Purnawarman; Sudiro, Sunny A.; Wibowo, Eri P.; Harmanto, Suryadi; Paindavoine, Michel

2012-11-01

133

Process, fabrication, and characteristics of a 0.8 ?m CMOS triple-level-metal gate array  

Microsoft Academic Search

A 0.8-?m CMOS (complementary metal-oxide-semiconductor) triple-level-metal ASIC (application-specific integrated circuit) technology has been developed. Features of this process include heavy twin-well architecture, improved LOCOS (local oxidation of silicon) isolation, scaled gate oxide thickness, and enhanced channel implants. The advanced triple-level-metal module includes a high-temperature contact barrier, dry-dry tapered contacts and vias, and planarized plasma TEOS interlevel dielectric. Inverter gate delays

P. Manos; B. Smith; K. Y. Chang; J. Klein; F. Pintchovski; E. Travis; M. Woo; S. Lai; R. Dillard

1989-01-01

134

Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process  

Microsoft Academic Search

Power gain (fMAX) of 350 GHz and cut-off frequency (fT) of 280 GHz is demonstrated for 36 nm Lpoly devices in a 45 nm bulk CMOS process. A record fT of 350 GHz (intrinsic fT 425 GHz), without any loss of fMAX is seen in 28 nm Lpoly devices. Combination of advanced lithography and liner stress effect can be leveraged

Hongmei Li; B. Jagannathan; Jing Wang; Tai-Chi Su; S. Sweeney; J. J. Pekarik; Yun Shi; D. Greenberg; Zhenrong Jin; R. Groves; L. Wagner; S. Csutak

2007-01-01

135

Phase edge lithography for sub 0.1 ?m electrical channel length in a 200 mm full CMOS process  

Microsoft Academic Search

In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 ?m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore

P. Agnello; T. Newman; E. Crabbe; S. Subbanna; E. Ganin; L. Liebmann; J. Comfort; D. Sunderland

1995-01-01

136

A millimeter-wave wideband SPDT switch with traveling-wave concept using 0.13-?m CMOS process  

Microsoft Academic Search

A wideband SPDT switch in standard bulk 0.13-?m CMOS process is demonstrated in this paper. In order to extend the operation frequency, the traveling-wave circuit topology is utilized. Due to the different requirements in transmit and receive paths, the switch is designed to be asymmetric. In the receive path, the switch achieves a measured insertion loss less than 2.7 dB,

Mei-Chao Yeh; Zuo-Min Tsai; Kim-You Lin; Chia-Yi Su; Chih-Ping Chao

2005-01-01

137

A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology  

Microsoft Academic Search

A focal-plane array (FPA) for room-temperature detection of 0.65-THz radiation has been fully integrated in a low-cost 0.25 mum CMOS process technology. The circuit architecture is based on the principle of distributed resistive self-mixing and facilitates broadband direct detection well beyond the cutoff frequency of the technology. The 3 timesZ 5 pixel array consists of differential on-chip patch antennas, NMOS

Erik Ojefors; Ullrich R. Pfeiffer; Alvydas Lisauskas; Hartmut G. Roskos

2009-01-01

138

Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study  

Microsoft Academic Search

This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as constraint. Extensive Monte Carlo simulations have been carried out on

Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos

2009-01-01

139

A monolithic IGBT gate driver implemented in a conventional 0.8 ?m BiCMOS process  

Microsoft Academic Search

This paper discusses the design and implementation of a monolithic gate driver for an insulated gate bipolar transistor (IGBT). The objective is to implement a high voltage (25 V) monolithic gate driver with an efficient protection circuit in a conventional low-voltage (5 V) high-density (0.8 ?m) BiCMOS process. Extended drain MOSFETs are used to implement the high-voltage capability in this

Mehrdad Ramezani; C. A. T. Salama

1998-01-01

140

Scaling trends in SET pulse widths in Sub-100 nm bulk CMOS processes.  

SciTech Connect

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Narasimham, Balaji; Ahlbin, Jonathan R.; Schrimpf, Ronald D.; Gadlage, Matthew J.; Massengill, Lloyd W.; Vizkelethy, Gyorgy; Reed, Robert A.; Bhuva, Bharat L.

2010-07-01

141

The Making of the CMOS Microchip  

NSDL National Science Digital Library

The animation of the making of the CMOS Microchip.Objective: Determine the process steps needed to complete a CMOS device.This simulation is from Module 002 of the Process & Equipment I Cluster of the MATEC Module Library (MML).

2010-05-05

142

Low loss, high contrast planar optical waveguides based on low-cost CMOS compatible LPCVD processing  

NASA Astrophysics Data System (ADS)

A new class of integrated optical waveguide structures ("TriPleX") is presented, based on low cost CMOS-compatible LPCVD processing of alternating Si3N4 and SiO2 layers. The technology allows for medium and high index-contrast waveguides that exhibit low channel attenuation. In addition, TriPleX waveguides are suitable for operation at wavelengths from visible (< 500 nm) through the infra-red range (2 ?m and beyond). The geometry is basically formed by a rectangular cross-section of silicon nitride (Si3N4) filled with and encapsulated by silicon dioxide (SiO2). The birefringence and minimal bend radius of the waveguide are completely controlled by the geometry of the waveguide layer structures. Experiments on typical geometries show excellent characteristics for telecom wavelengths at ~1300 nm-1600 nm (channel attenuation <= 0.06 dB/cm, Insertion Loss (IL) <= 0.15 dB, Polarization Dependent Loss (PDL) <= 0.1 dB, Group Birefringence (Bg) << 110-4, bend radius <= 50-100 ?m).

Hoving, Willem; Heideman, Rene; Geuzebroek, Douwe; Leinse, Arne; Klein, Edwin; Dekker, Ronald

2008-05-01

143

A CMOS image sensor with programmable pixel-level analog processing.  

PubMed

A prototype of a 34 x 34 pixel image sensor, implementing real-time analog image processing, is presented. Edge detection, motion detection, image amplification, and dynamic-range boosting are executed at pixel level by means of a highly interconnected pixel architecture based on the absolute value of the difference among neighbor pixels. The analog operations are performed over a kernel of 3 x 3 pixels. The square pixel, consisting of 30 transistors, has a pitch of 35 microm with a fill-factor of 20%. The chip was fabricated in a 0.35 microm CMOS technology, and its power consumption is 6 mW with 3.3 V power supply. The device was fully characterized and achieves a dynamic range of 50 dB with a light power density of 150 nW/mm2 and a frame rate of 30 frame/s. The measured fixed pattern noise corresponds to 1.1% of the saturation level. The sensor's dynamic range can be extended up to 96 dB using the double-sampling technique. PMID:16342506

Massari, Nicola; Gottardi, Massimo; Gonzo, Lorenzo; Stoppa, David; Simoni, Andrea

2005-11-01

144

CMOS active pixel sensor with on-chip successive approximation analog-to-digital converter  

Microsoft Academic Search

The first CMOS active pixel sensor (APS) with on-chip column-parallel successive-approximation analog-to-digital converter (ADC) is reported. A 6464 element CMOS APS implemented in a 1.2-?m n-well single-poly, double-metal process with 24-?m pixel pitch is integrated with a 641 array of column parallel successive approximation 8-b ADCs. Good image quality was observed. The capacitively-coupled ADCs dissipate approximately 1 ?W-s\\/ksample and occupy

Zhimin Zhou; Bedabrata Pain; Eric R. Fossum

1997-01-01

145

A buried-channel charge-coupled device with non-overlapping gate structure for a CMOS/BCCD process  

NASA Astrophysics Data System (ADS)

A buried-channel CCD is presented, suitable for integration in a high-energy ion-implanted CMOS process. The BCCD channel is high-energy ion-implanted and the gate structure is non-overlapping. The required submicron spacings between adjacent gates are created by a sequence of processing steps. No demands are imposed on the lithography used. SEM photographs show a well-defined gate structure with straight spacings exhibiting minor width variation. The parasitic potential well, associated with the presence of spacing between the gates, has little influence on charge transport performance. Delay lines have been operated with transfer inefficiency of 10-5 and less.

Warmerdam, L.; Wallinga, H.

1992-05-01

146

A RF receiver frontend for SC-UWB in a 0.18-?m CMOS process  

NASA Astrophysics Data System (ADS)

A radio frequency (RF) receiver frontend for single-carrier ultra-wideband (SC-UWB) is presented. The front end employs direct-conversion architecture, and consists of a differential low noise amplifier (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The proposed LNA employs source inductively degenerated topology. First, the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S11 is given. Then, a noise figure optimization strategy under gain and power constraints is proposed, with consideration of the integrated gate inductor, the bond-wire inductance, and its variation. The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band, and has two gain modes to obtain a higher receiver dynamic range. The mixer uses a double balanced Gilbert structure. The front end is fabricated in a TSMC 0.18-?m RF CMOS process and occupies an area of 1.43 mm2. In high and low gain modes, the measured maximum conversion gain are 42 dB and 22 dB, input 1 dB compression points are -40 dBm and -20 dBm, and S11 is better than -18 dB and -14.5 dB. The 3 dB IF bandwidth is more than 500 MHz. The double sideband noise figure is 4.7 dB in high gain mode. The total power consumption is 65 mW from a 1.8 V supply.

Rui, Guo; Haiying, Zhang

2012-12-01

147

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic  

Microsoft Academic Search

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies,

Kumar Yelamarthi; Chien-In Henry Chen

2009-01-01

148

A CMOS vision chip with SIMD processing element array for 1 ms image processing  

Microsoft Academic Search

Conventional image processing systems use a video signal as a transmission signal between an image sensor and image processor. The video rate, however, is not fast enough for some applications such as visual feedback for robot control, automobiles, gesture recognition for human interfaces, high speed visual inspection, microscope image processing, and so on. For such applications, the video signal, which

M. Ishikawa; K. Ogawa; T. Komuro; I. Ishii

1999-01-01

149

CMOS and BiCMOS VCO Status and trends  

Microsoft Academic Search

This paper gives a brief overview of voltage controlled oscillator(VCO) based on Si CMOS and SiGeBiCMOS process technologies. The status of designing techniques for high performance VCO is summarized because of its importance for high-speed communication systems and radar sensors. Then, the development tendency of VCO is introduced.

Xiang Li; Guang-Yin Feng; Jing-ye Cai; Zhen-Hai Shao; Lianfu Liu; Xueyong Zhu

2011-01-01

150

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 m CMOS MEMS process  

NASA Astrophysics Data System (ADS)

This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 m multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 m and the minimum structural spacing is 2.3 m. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 m. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 0.9 mm2, and the total power consumption is only 0.7 mW. Within the sensing range of 6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G-1with a standard deviation of 2.5 mV G-1. The measured output noise floor is 354 G Hz-1/2, corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV C-1 below 85 C.

Tseng, Sheng-Hsiang; S-C Lu, Michael; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

2012-05-01

151

Integrated CMOS amplifier for ENG signal recording  

Microsoft Academic Search

The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-?m CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain

A. Uranga; X. Navarro; N. Barniol

2004-01-01

152

A CCD\\/CMOS-based imager with integrated focal plane signal processing  

Microsoft Academic Search

Using a CCD\\/CMOS technology, a fully parallel 44 focal plane processor, which performs image acquisition, smoothing, and segmentation, has been fabricated and characterized. In this chip, image brightness is converted into signal charge using charge-coupled-device (CCD) imaging techniques. The Gaussian smoothing operation is approximated by the repeated application of a simple nearest-neighbor binomial convolution mask, realizing the first known use

Craig L. Keast; Charles G. Sodini

1993-01-01

153

Low-Power CMOS Interface for Recording and Processing Very Low Amplitude Signals  

Microsoft Academic Search

In this paper, we describe a low-power low-voltage CMOS very low signal acquisition analog front-end of sensor electronic interfaces. These interfaces are mainly dedicated to biomedical implantable devices. In this work, we focus on the implantable bladder controller. Since the nerve signal has very low amplitude and low frequency, it is, at first fed to a low-voltage chopper amplifier to

A. Harb; Y. Hu; M. Sawan; A. Abdelkerim; M. M. Elhilali

2004-01-01

154

GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes  

Microsoft Academic Search

In this paper, design aspects, operation, protection capability and applications of SCRs in deep sub-micron CMOS are addressed. A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR. Experimental verification, including endurance testing, demonstrates that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um

Christian C. Russ; Markus P. J. Mergens; Koen G. Verhaege; John Armer; Phillip C. Jozwiak; Girija Kolluri; Leslie R. Avery

2001-01-01

155

Polarization- and wavelength-sensitive sub-wavelength structures fabricated in the metal layers of deep submicron CMOS processes  

NASA Astrophysics Data System (ADS)

Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm. We describe the design and simulation of these metal structures using the finite-difference timedomain (FDTD) method. The spectral response of the test structures was measured for different polarizations, where the gratings showed typical features of wire grid polarizers. Using a 180 nm CMOS image sensor process, an image sensor with 6 ?m pixel size was designed and fabricated with different polarization selective structures allowing for polarization imaging. A polarization camera using this image sensor is demonstrated, visualizing stress birefringence as an application example. Finally, first results on the fabrication of hole arrays with a period of 320 nm are presented, showing color filters with enhanced transmission.

Junger, Stephan; Tschekalinskij, Wladimir; Verwaal, Nanko; Weber, Norbert

2010-04-01

156

CMOS active pixel image sensor  

Microsoft Academic Search

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 ?m double-poly, double-metal foundry CMOS process and is realized as a 128128 array of 40 ?m40 ?m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications

S. Mendis; S. E. Kemeny; E. R. Fossum

1994-01-01

157

High-voltage Devices And Circuits Fabricated Using Foundry Cmos For Use With Electrostatic Mem Actuators  

Microsoft Academic Search

SUMMARY High-voltage n- and p-type MOS transistors were fabricated using the 2.0 pm analog CMOS process available through the MOSIS foundry service. By using the n-well and the pbase layers as lightly doped drains, breakdown voltages were 120 V and -27 V for the NMOS and PMOS structures, respectively. The corresponding Early voltages were -1000 V for the NMOS and

N. I. Maluf; R. J. Reay; G. T. A. Kovacs

1995-01-01

158

0.5 Micron Gate CMOS Technology Using E-Beam\\/Optical Mix Lithography  

Microsoft Academic Search

A high performance CMOS process using mix e-beam\\/optical lithography has been developed for VLSI applications. The 0.5 m channel devices are fabricated with shallow N+ and P+ source\\/drain junctions. Self-aligned silicide on gate and diffusions reduces the sheet resistance to 5 ohm\\/sq.. The shallow retrograde N-well formed by multiple high energy phosphorous implants without a drive-in a allows the use

L. K. Wang; Y. Taur; D. Moy; R. H. Dennard; K. Chiong; F. Hohn; P. J. Coane; A. Edenfeld; S. Carbaugh; D. Kenney; S. Schnur

1986-01-01

159

Incorporating standard CMOS design Process methodologies into the QCA logic design process  

Microsoft Academic Search

As the size and complexity of quantum-dot cellular automata (QCA) digital circuits increase, the amount of time needed to create a QCA layout and then simulate the quasi-adiabatic switching of that layout significantly increases. To help reduce this development time, the same design process methodology that has been applied in developing complementary metal-oxide semiconductor circuits over the past twenty years

Steven C. Henderson; Eric W. Johnson; Jason R. Janulis; P. Douglas Tougaw

2004-01-01

160

A CMOS floating point multiplier  

NASA Astrophysics Data System (ADS)

This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

Uya, M.; Kaneko, K.; Yasui, J.

1984-10-01

161

Low-Power, Highspeed 1M bit CMOS DRAM.  

National Technical Information Service (NTIS)

The paper describes a 1M words X 1 bit CMOS DRAM fabricated with an advanced n-well CMOS technology. More than 2.2 million element devices are integrated on a 62.5 sq mm silicon chip employing an n-channel memory cell of triple-layer polysilicon structure...

S. Fujii S. Saito Y. Matsumoto

1985-01-01

162

CMOS dot matrix microdisplay  

NASA Astrophysics Data System (ADS)

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Venter, Petrus J.; Bogalecki, Alfons W.; Du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-02-01

163

Self-assembly patterning using block copolymer for advanced CMOS technology: optimisation of plasma etching process  

NASA Astrophysics Data System (ADS)

The best strategy to transfer nanopatterns formed from the self assembly of PS/PMMA bloc copolymers into a silicon substrate is investigated. We show that a hard mask patterning strategy combined with a plasma cure treatment of the PS mask are necessary to reproduce the PS mask pattern into the silicon with a good critical dimension control. In addition, typical silicon etching plasma condition must be revisited to allow the etching of sub-20 nm holes. These results indicate that block copolymer can be readily used as etching masks for advanced CMOS technology.

Chevolleau, T.; Cunge, G.; Delalande, M.; Chevalier, X.; Tiron, R.; David, S.; Darnon, M.; Navarro, C.

2012-03-01

164

Rapid development, in a manufacturing environment, of a 1 ?m triple-level metal CMOS process through the use of cross-functional teams  

Microsoft Academic Search

The development, in a manufacturing environment, of a 1 ?m triple-level-metal, 5 V CMOS process in under 25 weeks is discussed. The manufacturing process engineering group developed cross-functional process integration teams that synthesized device engineering from R&D, manufacturing process engineering, production, yield engineering, product engineering, and reliability engineering. By developing the process completely within the manufacturing group and allocating key

Matthew Comard; Jesus Cuellar

1992-01-01

165

Towards a high performance vertex detector based on 3D integration of deep N-well MAPS  

NASA Astrophysics Data System (ADS)

The development of deep N-Well (DNW) CMOS active pixel sensors was driven by the ambitious goal of designing a monolithic device with similar functionalities as in hybrid pixel readout chips, such as pixel-level sparsification and time stamping. The implementation of the DNW MAPS concept in a 3D vertical integration process naturally leads the designer towards putting more intelligence in the chip and in the pixels themselves, achieving novel device structures based on the interconnection of two or more layers fabricated in the same technology. These devices are read out with a data-push scheme that makes it possible to use pixel data for the generation of a flexible level 1 track trigger, based on associative memories, with short latency and high efficiency. This paper gives an update of the present status of DNW MAPS design in both 2D and 3D versions, and presents a discussion of the architectures that are being devised for the Layer 0 of the SuperB Silicon Vertex Tracker.

Re, V.

2010-06-01

166

Monolithic Active Pixel Sensors (MAPS) in a quadruple well technology for nearly 100% fill factor and full CMOS pixels  

Microsoft Academic Search

In this paper we present a novel, quadruple well process developed in a modern 0.18mu CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated

J. A. Ballin; J. P. Crooks; P. D. Dauncey; A.-M. Magnan; Yoshiari Mikami; O. D. Miller; Matthew Noy; Vladimir Rajovic; Marcel Stanitzki; K. D. Stefanov; Renato Turchetta; Mike Tyndel; E. G. Villani; N. K. Watson; J. A. Wilson

2008-01-01

167

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures.  

PubMed

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n(+)/p-sub, n-well/p-sub and p(+)/n-well/p-sub. All structures were fabricated in a 0.5 mum 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated-the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 x and 1.6 x over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 x and 1.2 x improvement over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) while the p(+)/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity. PMID:20454596

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2009-07-01

168

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 ?m CMOS Process  

PubMed Central

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

169

Fully Optimized Cu based process with dedicated cavity etch for 1.75?m and 1.45?m pixel pitch CMOS Image Sensors  

Microsoft Academic Search

An innovative process development for sub-2?m CMOS imager sensors is described, leading to tremendous improvements on main pixel parameters like conversion gain, saturation charge, sensitivity, dark current and noise, A full 3MP demonstrator with 1.75? pixel pitch and 1.45?m pixel pitch have been successfully designed, fabricated and characterized

M. Cohen; F. Roy; D. Herault; Y. Cazaux; A. Gandolfi; J. P. Reynard; C. Cowache; E. Bruno; T. Girault; J. Vaillant; F. Barbier; Y. Sanchez; N. Hotellier; O. LeBorgne; C. Augier; A. Inard; T. Jagueneau; C. Zinck; J. Michailos; E. Mazaleyrat

2006-01-01

170

Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD\\/EOS performance of a 0.25 \\/spl mu\\/m CMOS process  

Microsoft Academic Search

In this paper we show for the first time, how junction depths and salicide thicknesses in a 0.25 ?m CMOS process affect the current gain ? of a self-biased lateral NPN transistor, and examine the relationship between ? and the ESD performance. Furthermore, we present a direct method for extracting the self-biased LNPN ? and hence characterize the transistor behavior.

A. Amerasekera; V. McNeil; M. Rodder

1996-01-01

171

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 ?m CMOS process  

Microsoft Academic Search

ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 ?m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications

C. Richier; P. Salome; G. Mabboux; I. Zaza; A. Juge; P. Mortini

2000-01-01

172

Use of screening and response surface experimental designs for development of a 0.5-?m CMOS self-aligned titanium silicide process  

Microsoft Academic Search

A manufacturable self-aligned titanium silicide process for 0.5-?m CMOS technologies has been developed. Factorial and fractional-factorial screening experiments, as well as physical models, were used to identify important process factors. Central-composite and D-optimal response surface designs were used to optimize the process; short-loop process and device experiments and 0.5-?m technology static random access memory (SRAM) circuit flows were used. By

Robert E. Jones; Thomas C. Mele

1991-01-01

173

Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C  

NASA Astrophysics Data System (ADS)

Due to economical reasons junction isolated CMOS should be extensively exploited for temperature resistant electronics. A limitation at high temperatures is given by parasitic effects in the substrate, namely leakage currents, latch-up, and snap-back. Snap-back is caused by the parasitic bipolar action of single MOS transistor structures. We have investigated the temperature dependence of the snap-back phenomenon up to 250 degree(s)C using silicided LDD-MOS transistors with gate lengths of 0.8 micrometers and 1.0 micrometers as test devices. Measurements were performed dynamically with short pulses of rectangular shape. The snap-back breakdown voltage of 0.8 micrometers NMOS transistors decreases from 14.3 V at room temperature to 10.6 V at 250 degree(s)C and the triggering voltage for second breakdown from approximately 9.4 V at RT to 6.2 V at 250 degree(s)C. For PMOS transistors no snap-back was observed up to 20 V pulse height. The results show that snap-back is not a problem for this CMOS process up to the specified power supply voltage of 5 V. To consider shrinking effects were performed 2-dim FEM simulations. At high temperatures, the breakdown voltage is reduced with increasing temperature and decreasing gate length. This correlates to a value of the current gain of the parasitic bipolar transistor (beta) > 1 at the breakdown point. The commonly applied measures for designing processes with shorter gate lengths, like e.g. higher tub doping, are also sufficient to avoid snap-back under bias conditions even at temperatures up to 250 degree(s)C.

Uffmann, Dirk; Ibrom, Christina; Ackermann, Joerg; Stemmer, Jens; Aderhold, Jochen

1996-09-01

174

How a CMOS Device Works  

NSDL National Science Digital Library

This website includes an animation of a CMOS device and how it works. Objective: Identify the required electrical variables that allow a CMOS device to operate. This simulation is from Module 001 of the Process & Equipment I Cluster of the MATEC Module Library (MML). To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

2012-11-02

175

Strained Si CMOS (SS CMOS) technology: opportunities and challenges  

Microsoft Academic Search

Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern days CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics\\/design issues as well as in materials\\/process

K. Rim; R. Anderson; D. Boyd; F. Cardone; K. Chan; H. Chen; S. Christansen; J. Chu; K. Jenkins; T. Kanarsky; S. Koester; B. H. Lee; K. Lee; V. Mazzeo; A. Mocuta; D. Mocuta; P. M. Mooney; P. Oldiges; J. Ott; P. Ronsheim; R. Roy; A. Steegen; M. Yang; H. Zhu; M. Ieong; H.-S. P. Wong

2003-01-01

176

Recent Developments of CMOS Image Sensors  

NASA Astrophysics Data System (ADS)

Recent developments in CMOS image sensors are reviewed. High-speed, wide-dynamic-range, and range or 3D cameras are typical examples of recent success of CMOS image sensors. The fastest CMOS image with 100 M pixels reaches 2000 frames/s. Many techniques for achieving wide dynamic range have been proposed. CMOS image sensors employing wide dynamic range pixels with logarithmic response are applied for imaging of arc-welding process. CMOS sensors for real-time range imaging based on light stripe scanning, TOF (time of flight), and stereoscopic measurement methods are developed. The image quality of CMOS image sensor is being improved by the process technology and signal processing techniques.

Kawahito, Shoji

177

A highly manufacturable 0.25 ?m multiple-Vt dual gate oxide CMOS process for logic\\/embedded IC foundry technology  

Microsoft Academic Search

Summary form only given. A multiple-Vt high performance, high density and highly manufacturable 0.25 ?m CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts\\/vias, and fully stacked contact\\/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for

M. H. Chang; J. K. Ting; J. S. Shy; L. Chen; C. W. Liu; J. Y. Wu; K. H. Pan; C. S. Hou; C. C. Tu; Y. H. Chen; S. L. Sue; S. M. Jang; S. C. Yang; C. S. Tsai; C. H. Chen; H. J. Tao; C. C. Tsai; H. C. Hsieh; Y. Y. Wang; R. Y. Chang; K. B. Cheng; T. Y. Chu; T. N. Yen; P. S. Wang; J. W. Weng; J. H. Hsu; Y. S. Ho; C. H. Ho; Y. C. Huang; R. Y. Shiue; B. K. Liew; C. H. Yu; S. C. Sun; J. Y. C. Sun

1998-01-01

178

Enhanced fT and fMAX SiGe BiCMOS Process and Wideband Power Efficient Medium Power Amplifier  

Microsoft Academic Search

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA) has been designed and fabricated using 0.8 m SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator- metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching

Hyun-Cheol Bae; Seung-Hyeub Oh

2008-01-01

179

Low-noise CMOS signal processing IC for interpolating cathode strip chambers  

SciTech Connect

A CMOS circuit for obtaining precision amplitude and timing information from the cathodes of a proportional chamber with interpolating cathode strips has been developed. The chip performs charge amplification, shaping, analog storage and multiplexing, and generates a prompt timing pulse which can be used for trigger purposes. Novel features of the IC include: preamplifier optimized for large (40--250pF) detector capacitance, digitally programmable gain and bandwidth of the fourth-order shaper, and an array of on-chip capacitors and switches for injecting charge for calibration. Noise is less than 1,500 r.m.s. electrons with an input capacitance of 100 pF using bipolar 550 nsec shaping. Linearity is better than 0.8% over a dynamic range of 1,500:1. The constant fraction discriminator has a time walk of {+-}2.5 nsec over the range 10--500 fC. Power dissipation is 50 mW per channel.

O`Connor, P. [Brookhaven National Lab., Upton, NY (United States)

1995-08-01

180

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process  

Microsoft Academic Search

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on\\/off window and superior program efficiency. The SAN

Chia-En Huang; Ying-Je Chen; Han-Chao Lai; Ya-Chin King; Chrong Jung Lin

2009-01-01

181

Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process  

NASA Astrophysics Data System (ADS)

This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 ?m CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 161 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 k?. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.

Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.

2011-05-01

182

Test Structures for the Local Oxidized Self-Aligned Polysilicon Gate CMOS Process, NORDICMOS.  

National Technical Information Service (NTIS)

The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the p...

H. Pohjonen H. Ronkainen M. L. Silen

1984-01-01

183

Total ionizing dose radiation hardness of the ATLAS MDT-ASD and the HP-Agilent 0.5 m CMOS process  

Microsoft Academic Search

A total ionizing dose (TID) test of the MDT-ASD, the ATLAS MDT front-end chip (12)(13) has been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5 m CMOS process (AMOS14TB). The accumulated TID at the end of the test was 300 krad, delivered by 160 MeV protons at a

C. Posch; E. Hazen

2002-01-01

184

A 4Gbps 0.57pJ\\/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS  

Microsoft Academic Search

This paper describes an all-digital on-die true random number generator implemented in 45 nm CMOS technology, with random bit throughput of 4 Gbps and total energy consumption of 0.57 pJ\\/bit. A 2-step tuning mechanism enables robust operation in the presence of up to 20% fabrication-time process variation as well as immunity to run-time voltage and temperature fluctuation. The 100% use

Suresh Srinivasan; Sanu Mathew; Vasantha Erraguntla; Ram Krishnamurthy

2009-01-01

185

A monolithic IGBT gate driver for intelligent power modules implemented in 0.8 ?m high voltage (50 V) CMOS process  

Microsoft Academic Search

This paper discusses the design and implementation of a monolithic IGBT gate driver for intelligent power modules (IPMs). The objective of this work is to design and implement a monolithic IGBT gate driver IC with efficient protection functions in a high-voltage (50V) 0.8-?m CMOS process. The gate driver is designed for medium power applications, such as home appliances. It includes

J. M Park; E. D Kim; S. C Kim; N. K Kim; W Bahng; G. H Song; S. B Han

2001-01-01

186

Mask design, fabrication and characterization of in - house n-well MOSFET using spin -on dopant technique for undergraduates program  

Microsoft Academic Search

This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source\\/drain doping and aluminum for

M. binti Morsin; A. M. bin Zulkipli; M. S. Sulong; T. binti Ab Rahman

2009-01-01

187

SPICE macromodel and CMOS emulator for memristors.  

PubMed

In this paper, a new SPICE macromodel and CMOS emulator for memristors are proposed and verified to fit to the memristor's model equation very well in the entire range of memristor's resistance from the RESET state to the SET state. Compared with the memristor's model equation, average percentage errors in the new SPICE macromodel and in the 4-bit CMOS emulator are less than 0.5% and 0.9%, respectively. In addition, the CMOS emulator for memristors which can be implemented by a CMOS circuit will be very useful to design and verify various peripheral circuits for memristor applications particularly when the memristor fabrication process is not ready. PMID:22629985

Jung, Chul-Moon; Jo, Kwan-Hee; Min, Kyeong-Sik

2012-02-01

188

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit.  

PubMed

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal processing is accomplished with a current-to-frequency converter circuit that forms the causal portion of the matched filter for dc luminescence in wide-band white noise. Measurements show that luminescence can be detected from as few as 4 x 10(5) cells/ml. PMID:12192685

Simpson, M L; Sayler, G S; Patterson, G; Nivens, D E; Bolton, E K; Rochelle, J M; Arnott, J C; Applegate, B M; Ripp, S; Guillorn, M A

2001-01-25

189

CMOS Image Sensors for High Speed Applications.  

PubMed

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4?5 ?m) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps). PMID:22389609

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-13

190

CMOS Image Sensors for High Speed Applications  

PubMed Central

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4?5 ?m) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

El-Desouki, Munir; Deen, M. Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

191

Postfabrication Independent Inductance and Quality Factor Adjustments of On-Chip Inductors by Above-CMOS Processing for Rapid Prototyping of Radio Frequency System on Chips  

NASA Astrophysics Data System (ADS)

The flexible adjustment of on-chip inductor characteristics after a regular complementary metal--oxide--semiconductor (CMOS) fabrication was realized by the ``above-CMOS'' processing technology for radio frequency (RF) system-on-a-chip (SoC) rapid prototyping. It is shown that the above-CMOS metal pattern formation in a chip-by-chip manner can both increase and decrease the inductance (L) values of on-chip inductors. It is realized by applying various planar patterns of a metal layer deposited on the passivation layer of the chip. To increase the modification range of the characteristics and to establish an independent L and quality factor (Q) adjustment scheme, we have newly developed a pre-design method and a Q-compensation method. By combining these methods, the effective L and Q values of the on-chip inductors can be independently and arbitrarily modified. The adjustment of the input impedance matching frequency of a low-noise amplifier (LNA) using this scheme has also been demonstrated.

Sasaki, Yuki; Kotani, Koji

2012-04-01

192

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

193

A Compact SPDT Switch in 0.18um CMOS Process With High Linearity and Low Insertion Loss  

Microsoft Academic Search

A compact CMOS SPDT switch fabricated in 0.18 mum BiCMOS technology has been successfully demonstrated at X-Ku-band. The fully integrated chip exhibits a low insertion loss of 1.9 dB and an isolation of 22.5 dB at 17 GHz. By reverse biasing the source\\/drain (S\\/D) diode junctions, the switch achieves a PldB of 21 dBm and TOI greater than 30 dB

Mary Teshiba; Glenn Sakamoto; Terry Cisco

2007-01-01

194

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations  

Microsoft Academic Search

The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic

Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; S. Okazaki; Katsuji Satomi; Hironori Akamatsu; Hirofumi Shinohara

2008-01-01

195

Inductorless oscillator design for personal communications devices-a 1.2 ?m CMOS process case study  

Microsoft Academic Search

Three different 1.2 ?m CMOS ring oscillator type VCO architectures have been presented. The VCO's are intended for the use as building blocks of digital radio frequency synthesizer. It is demonstrated that linear control and improved phase-noise performance can be obtained by employing circuit design techniques and time domain based circuit optimization. The measurements results indicate that the maximum oscillating

Tadeusz Kwasniewski; Maamoun Abou-Seido; A. Bouchet; Fabien GauSSOrgues; Jacques Zimmerman

1995-01-01

196

A hybrid CMOS-imager with a solution-processable polymer as photoactive layer.  

PubMed

The solution-processability of organic photodetectors allows a straightforward combination with other materials, including inorganic ones, without increasing cost and process complexity significantly compared with conventional crystalline semiconductors. Although the optoelectronic performance of these organic devices does not outmatch their inorganic counterparts, there are certain applications exploiting the benefit of the solution-processability. Here we demonstrate that the small pixel fill factor of present complementary metal oxide semiconductor-imagers, decreasing the light sensitivity, can be increased up to 100% by replacing silicon photodiodes with an organic photoactive layer deposited with a simple low-cost spray-coating process. By performing a full optoelectronic characterization on this first solution-processable hybrid complementary metal oxide semiconductor-imager, including the first reported observation of different noise types in organic photodiodes, we demonstrate the suitability of this novel device for imaging. Furthermore, by integrating monolithically different organic materials to the chip, we show the cost-effective portability of the hybrid concept to different wavelength regions. PMID:23132025

Baierl, Daniela; Pancheri, Lucio; Schmidt, Morten; Stoppa, David; Dalla Betta, Gian-Franco; Scarpa, Giuseppe; Lugli, Paolo

2012-01-01

197

Precision bandgap circuit using high temperature coefficient diffusion resistor in a CMOS process  

US Patent & Trademark Office Database

Disclosed are bandgap circuits that use a resistive divider circuit to modulate the gate voltage of a reference source transistor. The reference voltage transistor is modulated at the base by a voltage that varies inversely with temperature. In this fashion, high sheet resistance poly resistors and diffusion resistors can be used that have very low process variation and minimize the use of die space.

2007-10-02

198

Radiation Tolerant Circuits Designed in 2 Commercial 0.25(micro) CMOS Processes.  

National Technical Information Service (NTIS)

Characterization of simple devices as well as complex circuits, in two commercial 0.25 micron processes, demonstrates a high level (up to 58 Mrad) radiation tolerance of these technologies. They are also very likely to be immune to single event gate damag...

A. Mekkaoui J. Hoff D. C. Christian W. Wester R. Yarema

2001-01-01

199

Radiation tolerant circuits designed in 2 commercial 0.25{micro} CMOS processes  

SciTech Connect

Characterization of simple devices as well as complex circuits, in two commercial 0.25{micro} processes, demonstrates a high level (up to 58 Mrad) radiation tolerance of these technologies. They are also very likely to be immune to single event gate damage according to the results from 200 MeV-protons irradiation.

Mekkaoui, A. [and others

2001-03-08

200

Circuit hot carrier reliability simulation in advanced CMOS process technology development  

Microsoft Academic Search

To establish the relation between circuit AC hot carrier (HC) degradation and DC testable parameters in early development stage of a deep submicron technology becomes the critical part of the process integration. DC Hot Carrier parameters, e.g. Idsat and Idlin, were found to be correlated to AC Ring Oscillator frequency degradation. The impact of crosstalk induced voltage overshoot to invertor

Peng Fang; P. C. Li; J. T. Yue

1994-01-01

201

Uniaxial-process-induced strained-Si: extending the CMOS roadmap  

Microsoft Academic Search

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are

S. E. Thompson; Guangyu Sun; Y. S. Choi; T. Nishida; G. Sun

2006-01-01

202

IGBT gate driver IC with full-bridge output stage using a modified standard CMOS process  

Microsoft Academic Search

This paper discusses the benefits of a full-bridge output stage on integrated IGBT gate drive circuits. This full-bridge topology allows obtaining positive and negative gate voltages using a single floating power supply. Short circuit protections have also been integrated, implementing an original soft shutdown process after an IGBT short circuit fault. The monolithic integration is based on an innovative high-voltage

A. Prez-toms; X. Jord; Philippe Godignon; J. L. Glvez; M Vellveh??; J. Milln

2004-01-01

203

A CNN UNIVERSAL CHIP IN CMOS TECHNOLOGY  

Microsoft Academic Search

This paper describes the design of a programmable Cellular Neural Network (CNN) chip,with added functionalities similar to those of the CNN Universal Machine. The prototype contains1024 cells and has been designed in a 1.0|m, n-well CMOS technology. Careful selectionof the topology and design parameters has resulted in a cell density of 31 cells\\/mm2and around7-8 bits accuracy in the weight values.

S. ESPEJO; R. Domnguez-Castro; R. Carmona; A. RODRGUEZ-VZQUEZ

1996-01-01

204

High-voltage-tolerant I\\/O buffers with low-voltage CMOS process  

Microsoft Academic Search

This paper presents high-voltage-tolerant I\\/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-?m process with 40- gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I\\/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2

Gajendra P. Singh; Raoul B. Salem

1999-01-01

205

Localization-based super-resolution microscopy with an sCMOS camera part III: camera embedded data processing significantly reduces the challenges of massive data handling.  

PubMed

We present a camera embedded data processing method for localization microscopy (LM) with faster detectors such as scientific complementary metal-oxide semiconductor (sCMOS) cameras. Based on the natural sparsity of single molecule images, this method utilizes the field programmable gate array chip inside a camera to identify and export only the regions containing active molecules instead of raw data. Through numerical simulation and experimental analysis, we found that this method can greatly reduce data volume (<10%) with negligible loss of useful information (<0.2%) at molecular densities <0.2 molecules/?m(2), thus significantly reducing the challenges of data transfer, storage, and analysis in LM. PMID:23722738

Ma, Hongqiang; Kawai, Hiroyuki; Toda, Eiji; Zeng, Shaoqun; Huang, Zhen-Li

2013-06-01

206

A 128128 CMOS active pixel image sensor for highly integrated imaging systems  

Microsoft Academic Search

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 ?m p-well CMOS process, and consists of a 128128 array of 40 ?m40 ?m pixels. The CMOS image

Sunetra K. Mendis; Sabrina E. Kemeny; Eric R. Fossum

1993-01-01

207

Performance of 70 nm strained-silicon CMOS devices  

Microsoft Academic Search

An 86% electron mobility improvement and over 20% Idn-sat enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage

J. R. Hwang; J. H. Ho; S. M. Ting; T. P. Chen; Y. S. Hsieh; C. C. Huang; Y. Y. Chiang; H. K. Lee; Ariel Liu; T. M. Shen; G. Braithwaite; M. Currie; N. Gerrish; R. Hammond; A. Lochtefeld; F. Singaporewala; M. Bulsara; Q. Xiang; M. R. Lin; W. T. Shiau; Y. T. Loh; J. K. Chen; S. C. Chien; F. Wen

2003-01-01

208

An ultra-low-power area-efficient non-volatile memory in a 0.18 ?m single-poly CMOS process for passive RFID tags  

NASA Astrophysics Data System (ADS)

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 ?m single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional FowlerNordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 ?m single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 ?m2 and 0.12 mm2, respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 ?W/0.69 ?W at a read/write rate of (268 kb/s)/(3.0 kb/s).

Xiaoyun, Jia; Peng, Feng; Shengguang, Zhang; Nanjian, Wu; Baiqin, Zhao; Su, Liu

2013-08-01

209

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels  

PubMed Central

In this paper we present a novel, quadruple well process developed in a modern 0.18 ?m CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 ?m pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-01-01

210

SiGe BiCMOS manufacturing platform for mmWave applications  

NASA Astrophysics Data System (ADS)

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18?m and 0.13?m node CMOS processes along with high density 5.6fF/?m2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

211

Back-thinned CMOS sensor optimization  

NASA Astrophysics Data System (ADS)

Back-thinning of a CCD image sensor is a very well established process for achieving high quantum efficiency and the majority of high-specification space and science applications have used such back-thinned devices for many years. CMOS sensors offer advantages over CCDs for a number of these applications and, in principle, it should be possible to back-thin CMOS devices and obtain the same performance as the CCD. This has now been demonstrated by e2v and results from two recent programmes to back-thin CMOS sensors show excellent quantum efficiency values.

Jerram, Paul; Burt, David; Guyatt, Neil; Hibon, Vincent; Vaillant, Joel; Henrion, Yann

2010-02-01

212

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.  

PubMed

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132124 high sensitivity imager array with a 20.1 ?m pixel pitch fabricated in a standard 0.5 ? CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 ?A from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 ?W/cm(2). Implementing 44 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-03-24

213

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager  

PubMed Central

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132124 high sensitivity imager array with a 20.1 ?m pixel pitch fabricated in a standard 0.5 ? CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 ?A from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 ?W/cm2. Implementing 44 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

214

A highly linear filter and VGA chain with novel DC-offset correction in 90nm digital CMOS process  

Microsoft Academic Search

This paper presents a complete base-band chain for current and emerging WLAN in 1.4V 90nm CMOS. The chain consists of a 6th order elliptic Gm-C 1\\/10\\/100MHz filter and five VGA stages. The design is DC-offset free and uses optimized Gm stages for linearity and low voltage operation. IIP3 is 2dBm @ 13.5dB minimum gain, while dissipating 13.5mW.

M. Elmala; B. Carlton; R. Bishop; K. Soumyanath

2005-01-01

215

5-GHz optical front-end for active pixel applications in standard 0.35 m CMOS  

NASA Astrophysics Data System (ADS)

A monolithically integrated, high speed optical front-end for optical sensing application in standard 0.35-m CMOS technology is reported. The proposed receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p- junctions as the active region, the integrated photodiode operates up to several gigahertz with no process modification. With multi-inductive-series peaking technique, the improved regulated cascade (RGC) transimpedance amplifier achieves an experimentally measured -3 dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dB(omega), which is the fastest reported TIA in CMOS 0.35-m technology. The 5 GHz broadband mixer produces a conversion gain of 13 dB which greatly minimizes the noise contribution from the IF amplification stage. The optical front-end of the active pixel demonstrates a -3 dB bandwidth of 4.9 GHz while consuming a current of 40 mA from 3.3 V power supply. This work presents the highest bandwidth for fully integrated CMOS optical receivers reported to date.

Li, Mengxiong; Hayes-Gill, Barrie; Clark, Matt; Pitter, Mark; Somekh, Mike; Harrison, Ian

2007-03-01

216

Characterization of a fully resonant, 1-MHz, 25-watt, DC/DC converter fabricated in a rad-hard BiCMOS/high-voltage process  

SciTech Connect

This paper presents the characterization of a DC/DC converter prototype when its power integrated circuit (PIC) chip is exposed to total dose, dose rate, neutron, and heavy ion environments. This fully resonant, 1-MHZ, 25-Watt, DC/DC converter is composed of a brassboard, populated with input/output filters, isolation transformers, output rectifier, capacitors, resistors, and PIC chip, integrating the primary-side control circuitry, secondary-side control circuitry, power switch, gate-drive circuitry, and voltage references. The brassboard is built using commercial off-the-shelf components; and the PIC chip is fabricated using AT and T`s rad-hard, bipolar complementary metal-oxide semiconductor (BiCMOS)/high-voltage process. The intent of this paper is to demonstrate that the PIC chip is fabricated with a radiation-hardened process and to demonstrate that various analog, digital, and power functions can be effectively integrated.

Titus, J.L.; Gehlhausen, M.A. [Naval Surface Warfare Center, Crane, IN (United States); Desko, J.C. Jr. [AT and T Bell Labs., Allentown, PA (United States); Nguyen, T.T.; Roberts, D.J. [AT and T Bell Labs., Whippany, NJ (United States); Shibib, M.A.; Hollenbach, K.E. [AT and T Bell Labs., Reading, PA (United States)

1995-12-01

217

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-?m CMOS technology  

Microsoft Academic Search

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-?m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to

Hon-Sum Philip Wong; Richard T. Chang; E. Crabbe; P. D. Agnello

1998-01-01

218

Gigahertz low noise CMOS transimpedance amplifier  

Microsoft Academic Search

A new class of low noise CMOS common gate transimpedance amplifier is described. What is novel about the design is the total isolation of the photodiode capacitance from determining the -3 dB bandwidth. HSPICE simulations of this amplifier were conducted using the Tritech 0.6 ?m CMOS process. Simulated performance gives 2 GHz bandwidth, 1.13 k? transimpedance gain and very low

S. M. Park; C. Toumazou

1997-01-01

219

CMOS image sensors for sensor networks  

Microsoft Academic Search

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 ?m CMOS process. The imagers embed\\u000a an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision\\u000a on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low\\u000a power operation. This

Eugenio Culurciello; Andreas G. Andreou

2006-01-01

220

Back-thinned CMOS Sensor Optimisation  

Microsoft Academic Search

Back-thinning of a CCD image sensor is a very well established process for achieving high quantum efficiency and the majority of high-specification space and science applications have used such back-thinned devices for many years. CMOS sensors offer advantages over CCDs for a number of these applications and, in principle, it should be possible to back-thin CMOS devices and obtain the

Paul Jerram; David Burt; Neil Guyatt; Vincent Hibon; Joel Vaillant; Yann Henrion

221

CMOS image sensors  

Microsoft Academic Search

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most

A. El Gamal; H. Eltoukhy

2005-01-01

222

An integrated, CMOS, constant-fraction timing discriminator for multichannel detector systems  

SciTech Connect

An integrated, CMOS, constant-fraction timing discriminator (CFD) designed to accommodate the special requirements of large, multichannel `el detector systems is described. This CFD features on-chip, zero-crossing shaping and an automatic walk setting to limit the number of user adjustments. The circuit is realized in the Orbit 1.2 micron, N-well, CMOS process and operates with a 5 V power supply. The time walk in a 100:1 dynamic range ({minus}15 mV to {minus}1.5 V) is less than {+-}250 ps for a 10 ns rise time/10 ns fall time signal, yet the power dissipation is about 2 mW/channel. The discriminator has a 170 micron pitch, is 800 microns long, and is structured for arraying multiple channels on a single die. In this work, the fully integrated, CMOS CFD that was designed for the lead-glass calorimeter of the WA-98 experiment is described. This circuit also has applications for some detector subsystems in the Relativistic Heavy Ion Collider (RHIC) detector, PHENIX.

Simpson, M.L.; Britton, C.L.; Wintenberg, A.L.; Young, G.R. [Oak Ridge National Lab., TN (United States)

1995-08-01

223

Integrated CMOS amplifier for ENG signal recording.  

PubMed

The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier. PMID:15605867

Uranga, A; Navarro, X; Barniol, N

2004-12-01

224

Modeling and Estimation of FPN Components in CMOS Image Sensors  

Microsoft Academic Search

Fixed pattern noise #FPN# for a CCD sensor is modeled as a sample of a spatial white noise process. This model is,however, not adequate for characterizing FPN in CMOS sensors, since the readout circuitry of CMOS sensors andCCDs are very di#erent. The paper presents a model for CMOS FPN as the sum of two components: a columnand a pixel component.

Abbas El Gamal; Boyd Fowler; Hao Min; Xinqiao Liu

1998-01-01

225

Checkered white-RGB color LOFIC CMOS image sensor  

Microsoft Academic Search

We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1\\/3.3-inch optical format, 1280H x 480V pixels, 4.2-?m effective pixel pitch along with 45 direction was designed and fabricated through 0.18-?m 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image

Shun Kawada; Shin Sakai; Yoshiaki Tashiro; Shigetoshi Sugawa

2010-01-01

226

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

Microsoft Academic Search

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS\\/NEMS hybrid systems, and NEMS based micro-processors\\/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches\\/devices to

Bradley Darren Davidson

2010-01-01

227

Universal high voltage multiplexer for CMOS OTP memory applications  

Microsoft Academic Search

A CMOS-compatible high voltage multiplexer (HV MUX) for zero-additional-mask CMOS one time programmable (OTP) memory array mask is presented. The HV MUX uses standard CMOS with low input voltage and produce high output voltage beyond the VDD allowed by the process for programming the OTP memory array. By limiting the instantaneous voltage between any two nodes, the HV MUX can

Kwok Ping Ng; M. C. Lee; Wan Tim Chan; Randy Barsatan; Mansun Chan

2008-01-01

228

Trends in CMOS image sensor technology and design  

Microsoft Academic Search

Three trends that promise to increase CMOS image sensor system performance are presented: (i) modifications of deep submicron CMOS processes to improve their imaging characteristics, (ii) developments that take advantage of these modified deep submicron processes, and (iii) high frame rate sensors and applications to still and video imaging, specifically to extending sensor dynamic range. Recent research on Digital Pixel

Abbas El Gamal

2002-01-01

229

A CMOS Tunable Transimpedance Amplifier  

Microsoft Academic Search

A tunable transimpedance amplifier (TIA) is presented in this letter. By incorporating a mechanism for gain and bandwidth tuning, the TIA can be adjusted to achieve optimum circuit performance with a lowest bit-error-rate (BER) for high-speed applications. The proposed circuit is implemented in a 0.18-mum CMOS process. Consuming a dc power of 34mW from a 2.0-V supply voltage, the fabricated

Huei-Yan Hwang; Jun-Chau Chien; Tai-Yuan Chen; Liang-Hung Lu

2006-01-01

230

A full Cu damascene metallization process for sub-0.18 \\/spl mu\\/m RF CMOS SoC high Q inductor and MIM capacitor application at 2.4 GHz and 5.3 GHz  

Microsoft Academic Search

A full Cu damascene metallization process was successfully developed for simultaneous formation of sub-0.18 \\\\?m RF CMOS passive components including circular spiral inductor and MIM capacitor. High quality factor inductor with Q=18 at 1.2 nH was achieved by applying highly uniform Cu CMP process on polishing microns of Cu. Less than 2% Rs uniformity and 70 nm dishing on 95%

C. C. Lin; H. M. Hsu; Y. H. Chen; T. Shih; S. M. Jang; C. H. Yu; M. S. Liang

2001-01-01

231

NOTE: Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies  

NASA Astrophysics Data System (ADS)

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process.

Yu, Xiaomei; Tang, Yaquan; Zhang, Haitao

2008-03-01

232

Analog CMOS/SOS in radiative environments  

NASA Astrophysics Data System (ADS)

A radiation tolerant Silicon On Sapphire (SOS) process used to produce Complementary Metal Oxide Semiconductor Application Specific Integrated Circuits (CMOS ASIC's) is described. Use of such analog/digital CMOS/bulk ASIC's in pacemakers and hearing aids is discussed. Recent development on the SOS process now makes it possible to make radiation hard analog designs as well. The SOS4 process and its analog opportunities are discussed. The SOS4 technology in general is presented and its advantages and drawbacks are discussed. Radiation effects on CMOS/SOS devices are presented in order to understand their impact on analog design. Performance results from a high speed comparator and a charge amplifier show different useful aspects of the SOS4 process.

Paulsson, Magnus

1991-03-01

233

An 88 CMOS microelectrode array for electrochemical dopamine detection  

Microsoft Academic Search

This work presents the design and characterization of an integrated CMOS (complementary metal oxide semiconductor) electrochemical sensor array for dopamine (DA) detection. The chip is intended to provide as a platform for high- throughput measurement of neurotransmitter release during exocytosis. Interdigitated gold microelectrodes with a 5-Pm gap are fabricated on CMOS chips by a post-CMOS lithographic process. A buffer with

Po-Hung Yang; Michael S.-C. Lu

2011-01-01

234

A 12 mW wide dynamic range CMOS front end for a portable GPS receiver  

Microsoft Academic Search

At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35?m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications

A. R. Shahani; D. K. Shaeffer; T. H. Lee

1997-01-01

235

Intelligent Vehicle Road Recognition based on the CMOS camera  

Microsoft Academic Search

Since the problems of intelligent auxiliary driving and co-navigating have received more and more attention recent years, a road recognition system is developed for the intelligent vehicle with CMOS camera as its road sensor, which provides solutions for the road recognition and automatic drive functions of the intelligent vehicle. The installation and sampling process of the CMOS camera is explained.

Chu Liu; Jie Chen; Yifan Xu; Feng Luo

2008-01-01

236

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

Microsoft Academic Search

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture

Joseph C. Doll; Bryan C. Petzold; Biju Ninan; Ravi Mullapudi; Beth L. Pruitt

2010-01-01

237

Low-Power Strategies for High-Performance CMOS Circuits  

Microsoft Academic Search

Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as

Tobias G. Noll; RWTH Aachen Rogowski-Institu

1994-01-01

238

ESD Phenomena and Protection Issues in CMOS Output Buffers  

Microsoft Academic Search

In VLSI devices with 1 m CMOS technologies the use of silicided diffusions has been found to have a negative impact on the ESD protection levels of both inputs and outputs. In this paper the ESD phenomena for CMOS output buffers is presented to show that it can be improved for advanced processes. The primary findings here show that the

C. Duvvury; R. N. Rountree; Y. Fong; R. A. McPhee

1987-01-01

239

ESD protection for submicron CMOS circuits-issues and solutions  

Microsoft Academic Search

Key issues pertinent to design with advanced CMOS ESD (electrostatic discharge)-protection circuits are discussed. Input protection elements and their limitations with respect to output and power supply applications are examined. The lateral silicon-controlled rectifier has proved to be an effective primary protection element for a wide range of CMOS processes when it is combined with an optimized secondary protection network.

Robert N. Rountree

1988-01-01

240

Implantable CMOS Biomedical Devices  

PubMed Central

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

2009-01-01

241

LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)  

Microsoft Academic Search

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition

DAVID R. MYERS; JEFFREY R. JESSING; OLGA B. SPAHN; MARTY R. SHANEYFELT

2000-01-01

242

Pulsed bipolar CMOS imager  

Microsoft Academic Search

This paper will describe an acti ve pixel CMOS-compatible im- ager aimed at high resolution still cameras. We will discuss pixel operation, column sense circuits, serial output, and show results from existing imagers. In this abstract, we show results from a prototype 640x480 imager with 5.9x5.9 ?m2 pixels built in 0.8 ?m double-poly CMOS with one additional base implant.

Tobi Delbruck; Nicholas Mascarenhas; Min-Hwa Chi; Albert Bergemont; Carver Mead

243

Resonant mechanical magnetic sensor in standard CMOS  

Microsoft Academic Search

A novel micromechanical magnetic sensor has been built and tested. The field is detected by measuring the vibration amplitude of a mechanical Lorentz force oscillator. This device is made from a standard 2-?m CMOS fabrication process with a post-processing etch step to undercut and release the sensor. When operated at the resonant frequency of the mechanical system, a sensitivity of

Beverley Eyre; Kristofer S. J. Pister; William Kaiser

1998-01-01

244

A fully differential CMOS transconductance-transimpedance wideband amplifier  

Microsoft Academic Search

A high-speed wideband amplifier using a transconductance-transimpedance circuit technique is presented. The proposed circuit configuration results in more reliable performances than are typically obtained from designs using conventional pole-zero, cancellation or peaking technique. With a 0.8 ?m, double poly, double metal, n-well CMOS technology and single 5-V power supply, the prelayout simulation of this amplifier shows a -3 dB frequency

Chorng-Kuang Wang; Po-Chiun Huang; Chen-Yi Huang

1995-01-01

245

SEMICONDUCTOR INTEGRATED CIRCUITS: Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-?m low power CMOS process  

NASA Astrophysics Data System (ADS)

Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q2 random walk NMOS current source layout routing method, a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-?m CMOS process. The total consumption is only 10 mW from a single 1.2-V power supply, and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively. When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate, the SFDR is measured to be 70 dB. The die area is about 0.2 mm2.

Bulu, Xu; Bowen, Shao; Xia, Lin; Wei, Yi; Yun, Liu

2010-09-01

246

Graphene for CMOS and Beyond CMOS Applications  

Microsoft Academic Search

Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated

Sanjay K. Banerjee; Leonard Franklin Register; Emanuel Tutuc; Dipanjan Basu; Seyoung Kim; Dharmendar Reddy; Allan H. MacDonald

2010-01-01

247

Fundamental performance differences between CMOS and CCD imagers: part III  

NASA Astrophysics Data System (ADS)

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

248

Lab-on-CMOS integration of microfluidics and electrochemical sensors.  

PubMed

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J

2013-08-27

249

CMOS sensor for face tracking and recognition  

NASA Astrophysics Data System (ADS)

This paper describes the main principles of a vision sensor dedicated to the detecting and tracking faces in video sequences. For this purpose, a current mode CMOS active sensor has been designed using an array of pixels that are amplified by using current mirrors of column amplifier. This circuit is simulated using Mentor Graphics software with parameters of a 0.6 m CMOS process. The circuit design is added with a sequential control unit which purpose is to realise capture of subwindows at any location and any size in the whole image.

Ginhac, Dominique; Prasetyo, Eri; Paindavoine, Michel

2005-03-01

250

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers  

NASA Astrophysics Data System (ADS)

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 m 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

2011-10-01

251

CMOS imaging for automotive applications  

Microsoft Academic Search

This contribution is devoted to CMOS imaging for automotive applications. It is shown that unlike CCD-based imaging, imaging based on CMOS-sensing meets adequately requirements posed by automotive vision applications. In addition, besides classical vision, CMOS imaging enables new applications like, e.g., occupancy sensing, rangefinding, and 3-D vision.

B. J. Hosticka; W. Brockherde; A. Bussmann; T. Heimann; R. Jeremias; A. Kemna; C. Nitta; O. Schrey

2003-01-01

252

Numerical analysis of heavy ion particle-induced CMOS latch-up  

NASA Astrophysics Data System (ADS)

Assuming a two-dimensional spreading of a sheet of a charge in a plane, a two-dimensional transient numerical simulator is used to analyze heavy ion particle-induced CMOS latch-up. The charge funneling effect during the carrier collection process is found to lower the parasitic bipolar emitter-base potential barrier, which is the main factor initiating latch-up. Latch-up susceptibility is examined as a parameter of the heavy ion particle incident condition, with track lengths taken as 8 microns. The incident conditions demonstrating long path length in the N-well/P-sub junction depletion layer were shown to be the most sensitive to latch-up, and the use of an n+ guard band was found to be more effective for latch-up immunity. The study has LSI space applications.

Aoki, T.; Kasai, R.; Tomizawa, M.

1986-05-01

253

On The Use Of N-well Resistors For Uniform Triggering Of Esd Protection Elements  

Microsoft Academic Search

N-well resistors are sometimes used to add series resistance to a grounded-gate NMOST protection device in order to ensure simultaneous triggering of multiple fingers. It turns out that such protections may fail far below their nominal ESD threshold depending on the particular layout. It is shown that n-well snapback plays a major role in the failure mechanism. Maximum ESD performance

Guido Notermans; Philips Semiconductors

1997-01-01

254

Monolithic piezoresistive CMOS magnetic field sensors  

Microsoft Academic Search

Two original electromechanical magnetic sensors have been developed using a fully industrial fabrication process that relies on bulk wet etching of CMOS dies. The first device uses the Lorentz force to actuate a U-shaped cantilever beam, while piezoresistive polysilicon gauges convert the beam bending into an electrical signal. A 2?T sensor resolution is demonstrated, making this device suitable for earth

Vincent Beroulle; Yves Bertrand; Laurent Latorre; Pascal Nouet

2003-01-01

255

A SubMicron BiCMOS Technology for Telecommunications  

Microsoft Academic Search

A high performance, 0.8 m, analog-digital technology is presented. Telecommunication circuit and system diversity has been accommodated by incorporating modular device options into a triple-level-metal BiCMOS process.

R. Hadaway; P. Kempf; P. Schvan; M. Rowlandson; V. Ho; J. Kolk; B. Tait; D. Sutherland; G. Jolly; I. Emesh

1991-01-01

256

On-wafer measurements and characterization of poly-si resistors for evaluation of selected CMOS manufacturing processes  

NASA Astrophysics Data System (ADS)

In this study, measurements of resistance of polysilicon resistors with different widths have been done over the whole surface of the SOI wafers. The obtained results have been used to determine changes in their width, which is equivalent with shortening of the channel length in the photoli-thography process. By studying the elements distributed across the wafers it was possible to assess the homogeneity of the MOS transistor gate manufacturing process. the abstract two lines below author names and addresses.

G?uszko, Grzegorz; Tomaszewski, Daniel; Malesi?ska, Jolanta; Kucharski, Krzysztof

2013-07-01

257

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications  

PubMed Central

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array.

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

258

A CMOS humidity sensor with on-chip calibration  

Microsoft Academic Search

This paper describes a capacitive humidity sensor with on-chip calibration circuit fabricated by a standard CMOS process to achieve a cost-effective solution for accurate and reliable humidity measurement. The humidity sensing property on-chip is obtained by a post-processing step after the standard CMOS fabrication and whereby a commercial polyimide is deposited on the packaged chip. The sensing principle of the

Y. Y. Qiu; C. Azeredo-Leme; L. R. Alccer; J. E. Franca

2001-01-01

259

CMOS magnetic sensor integrated circuit with sectorial MAGFET  

Microsoft Academic Search

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6?m digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling

Guo Qing; Zhu Dazhong; Yao Yunruo

2006-01-01

260

A 0.18 ?m foundry RF CMOS technology with 70 GHz Ft for single chip system solutions  

Microsoft Academic Search

This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using optimized CMOS topology and deep n-well isolation, we obtain a Ft of 60 GHz and Fmax of 55 GHz at 10 mA, a Ft of 70 GHz and Fmax of 58 GHz at maximum-transconductance bias, and minimum

Heng-Ming Hsu; Jui-Yu Chang; Jiong-Guang Su; Chao-Chieh Tsai; Shyh-Chyi Wong; C. W. Chen; K. R. Peng; S. P. Ma; C. N. Chen; T. H. Yeh; C. H. Lin; Y. C. Sun; C. Y. Chang

2001-01-01

261

Automotive CMOS Image Sensors  

Microsoft Academic Search

After penetrating the consumer and industrial world for over a decade, digital imaging is slowly but inevitably gaining marketshare in the automotive world. Cameras will become a key sensor in increasing car safety, driving assistance and driving comfort. The image sensors for automotive will be dominated by CMOS sensors as the requirements are different from the consumer market or the

S. Maddalena; A. Darmon; R. Diels

262

Implantable CMOS Biomedical Devices.  

PubMed

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented. PMID:22291554

Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

2009-11-17

263

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

264

Reconfigurable subthreshold CMOS perceptron  

Microsoft Academic Search

We present an idea for a new real-time reconfigurable perceptron, also called, a threshold element. The circuit example contain three inverters with shorted outputs. SPICE simulations for a 0.6 ?m CMOS implementation operating in the subthreshold region. are shown. The threshold voltages of the active devices, seen from driving nodes, may be dynamically changed by adjusting their substrate potentials. This

Snorre Aunet; Bengt Oelmann; Suliman Abdalla; Yngvar Berg

2004-01-01

265

Integrated CMOS-MEMS with on-chip readout electronics for high-frequency applications  

Microsoft Academic Search

A bridge-shaped first-lateral-mode 60-MHz mechanical resonator, which is monolithically integrated with capacitive CMOS readout electronics, is presented. The resonator is fabricated directly on a commercial CMOS technology using the top metal level as a structural layer. A maskless single-step wet-etching process for mechanical structure release after the standard CMOS integration process is the only postfabrication requirement. Electrical characterization of the

J. Verd; A. Uranga; J. Teva; J. L. Lopez; F. Torres; J. Esteve; G. Abadal; F. Perez-Murano; N. Barniol

2006-01-01

266

Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits  

Microsoft Academic Search

This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high performance microelectromechanical systems solenoid inductors and metal-insulator-metal (MIM) capacitors by using a post CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of

Zhengzheng Wu; Lei Gu; Xinxin Li

2009-01-01

267

A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process  

NASA Astrophysics Data System (ADS)

An electrostatic discharge (ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed. The leakage current is reduced to 4.6 nA at 25 C. Under the ESD event, it injects a 38.7 mA trigger current into the P-substrate to trigger SCR, and SCR can be turned on the discharge of the ESD energy. The capacitor area used is only 4.2 ?m2. The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency, compared with the previous circuits.

Zhaonian, Yang; Hongxia, Liu; Shulong, Wang

2013-04-01

268

OLED-on-CMOS integration for optoelectronic sensor applications  

NASA Astrophysics Data System (ADS)

Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Toerker, Michael; Grillberger, Christiane; Amelung, Jrg

2007-03-01

269

A study of residual stress effects on CMOS-MEMS microphone technology  

Microsoft Academic Search

In this study, a process modeling methodology applied in finite element (FE) analysis has been developed to investigate the evolution of residual stress during and after the CMOS-MEMS process. The MEMS (micro-electromechanical systems) capacitive microphone structure which contains a large membrane for sound sensing is selected to be studied, and it is fabricated using a standard foundry CMOS process. From

Ming-Chih Yew; Chin-Wen Huang; Wei-Jr Lin; Chin-Hung Wang; Pin Chang

2009-01-01

270

CMOS MEMS capacitive absolute pressure sensor  

NASA Astrophysics Data System (ADS)

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 m CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

2013-05-01

271

A Floating-Gate-Based Programmable CMOS Reference  

Microsoft Academic Search

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-mum CMOS process, and

Venkatesh Srinivasan; Guillermo Serrano; Christopher M. Twigg; Paul Hasler

2008-01-01

272

CMOS High Power SPDT Switch using Multigate Structure  

Microsoft Academic Search

A novel CMOS high power RF switch using the multi-gate structure in a 0.18-mum triple-well CMOS process is designed, implemented, and characterized. The receive switch incorporates the multi-gate structure in order to provide high power handling capability to the transmit switch side. In addition, the RF switch with the multi-gate structure reduces insertion loss more than the one with the

Minsik Ahn; Chang-ho Lee; Joy Laskar

2007-01-01

273

OLED-on-CMOS integration for optoelectronic sensor applications  

Microsoft Academic Search

Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors

Uwe Vogel; Daniel Kreye; Sven Reckziegel; Michael Toerker; Christiane Grillberger; Jrg Amelung

2007-01-01

274

A fully-integrated CMOS-MEMS audio microphone  

Microsoft Academic Search

We report on the construction of a microphone and associated electronics fabricated entirely within a standard CMOS (complementary metal oxide semiconductor) die. An A-weighted noise level of 46 dB SPL was achieved with a total diaphragm area of 0.61 mm2. Because the microphone uses the same processing sequence as CMOS-MEMS (microelectromechanical systems) microspeakers it is now possible to create acoustic

K. J. Gabriel

2003-01-01

275

W-band pulsed radar receiver in low cost CMOS  

Microsoft Academic Search

A CMOS heterodyne receiver integrating a phase-locked loop that includes a bulk of transmitter functions for W-band pulsed radar is realized using low leakage transistors of a low cost 65-nm bulk CMOS process with 5 thin and 1 thick metal layers used to manufacture cell phone RFIC's. The peak conversion gain of receiver is 7 dB and the minimum NF

Ning Zhang; K. O. Kenneth

2010-01-01

276

Wideband VGAs Using a CMOS Transconductor in Triode region  

Microsoft Academic Search

Wideband variable gain amplifiers (VGAs) fabricated using 0.18 mum CMOS process are presented. A scheme with a CMOS triode transconductor is proposed to achieve linear-in-dB characteristics of VGAs for ultra wideband (UWB) systems. The implemented transmitter (TX) VGA shows a highly linear gain range of 28.4 dB (7 dB to -21.4 dB) and a bandwidth of 1200 MHz, while drawing

Hui Dong Lee; Kyung Ai Lee; Songcheol Hong

2006-01-01

277

A 0.13m CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation  

NASA Astrophysics Data System (ADS)

A 2.4GHz 0.13m CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40C and +90C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13m CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

278

A Low Loss High Isolation DC60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process  

Microsoft Academic Search

In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using

Hong-Yeh Chang; Ching-Yan Chan

2010-01-01

279

Opticalthermal simulation applied to the study of the pattern effects induced by the sub-melt laser anneal process in advanced CMOS technologies  

Microsoft Academic Search

We present a study of the temperature non-homogeneities induced by millisecond laser annealing in advanced CMOS technologies\\u000a at die level. Because of the design, the device layout at the wafer surface introduces during this anneal significant spatial\\u000a variations of optical absorption and heat transfer that can induce temperature non-uniformities over the die, often called\\u000a pattern effects. These temperature variations are

A. Colin; P. Morin; F. Cacho; H. Bono; R. Beneyton; D. Mathiot; E. Fogarassy

2011-01-01

280

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-?m to 90-nm generation  

Microsoft Academic Search

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 ?m, 0.18 ?m, 0.13 ?m, and 90 nm showed an increase of 8% per generation.

P. Hazucha; T. Karnik; J. Maiz; S. Walstra; B. Bloechel; J. Tschanz; G. Dermer; S. Hareland; P. Armstrong; S. Borkar

2003-01-01

281

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

282

Electronics and photonics convergence on Si CMOS platform  

NASA Astrophysics Data System (ADS)

The present paper describes Si microphotonics and its current status of electronics and photonics convergence on Si platform based on monolithic integration using CMOS (Complementary Metal Oxide Semiconductor) technologies. The Si CMOS platform is advantageous over III-V semiconductor based platform because of a short time-lag between basic research and commercialization in terms of the standardized materials and processes. To implement photonic devices on the Si CMOS platform, it is important to reduce materials diversity in current photonics devices. Low loss SiNx waveguides with sharp bends, high performance strained Ge photodetectors for C+L band, and demultiplexer/multiplexer for WDM (wavelength division multiplexing) have been successfully implemented on the Si CMOS platform. The current targets are cost-effective OADMs (optical add-drop multiplexers) for optical communication and optical clocking for Si LSIs beyond Cu-low k technologies.

Wada, Kazumi

2004-07-01

283

A safety monitoring system for taxi based on CMOS imager  

NASA Astrophysics Data System (ADS)

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Liu, Zhi

2005-01-01

284

An ultra-low dark current CMOS image sensor cell using n+ ring reset  

Microsoft Academic Search

We present in this letter for the first time a new CMOS image sensor cell using n+-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing

Hsiu-Yu Cheng; Ya-Chin King

2002-01-01

285

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations  

Microsoft Academic Search

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-?m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate\\/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more

Hsiu-Yu Cheng; Ya-Chin King

2003-01-01

286

Integration of Solar Cells on Top of CMOS Chips Part I: aSi Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process

Jiwu Lu; Alexey Y. Kovalgin; Karine H. M. van der Werf; Ruud E. I. Schropp; Jurriaan Schmitz

2011-01-01

287

System-on-package ultra-wideband transmitter using CMOS impulse generator  

Microsoft Academic Search

In this paper, a low-cost CMOS ultra-wideband (UWB) impulse transmitter module with a compact form factor is proposed for impulse-radio communications. The module consists of a CMOS impulse generator, a compact bandpass filter (BPF), and a printed planar UWB antenna. The impulse generator is designed using a Samsung 0.35-?m CMOS process for low-cost and low-power fabrication. The measurement shows the

Junwoo Lee; Young-Jin Park; Myunghoi Kim; Changwook Yoon; Joungho Kim; Kwan-Ho Kim

2006-01-01

288

Development and characterization of CMOS-based monolithic X-ray imager sensor  

Microsoft Academic Search

We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

2007-01-01

289

Design and implementation of a novel CMOS MEMS condenser microphone with corrugated diaphragm  

Microsoft Academic Search

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin films stacking of 0.35?m UMC CMOS 3.3\\/5.0V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, silicon substrate is employed to

Chien-Hsin Huang; Ming-Han Tsai; Chien-Hsing Lee; Tsung-Min Hsieh; Jhyy-Cheng Liou; Li-Che Chen; Ming-Chuen Yip; Weileun Fang

2011-01-01

290

Development of a RF Bipolar Transistor in a Standard 0.35m CMOS Technology  

Microsoft Academic Search

A RF Bipolar Transistor integrated to a standard 0.35m CMOS process is presented. This BiCMOS technology features a single-poly NPN transistor with simulated performance of f? = 16GHz and BVCEO = 6.4V. With implanted base and no trench isolation, this device offers full compatibility with standard CMOS technology at the cost of three additional mask layers, while demonstrates good performance

I-Shan Michael Sun; Wai Tung Ng; Philip K. T. Mok; Hidenori Mochizuki; Katsumi Shinomura; Hisaya Imai; Akira Ishikawa; Nobuo Saito; Kiyoshi Miyashita; Satoru Tamura; Kaoru Takasuka

291

CCD and CMOS sensors  

NASA Astrophysics Data System (ADS)

The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

Waltham, Nick

292

Scaled CMOS MEMS for real-time infrared scene generation  

NASA Astrophysics Data System (ADS)

CMOS/MEMS is used as a technique to create infrared emitters. A commercial CMOS process is used that, with a post-processing silicon etch, creates thermally isolated, electronically addressable polysilicon resistors suitable for infrared scene generation. Previous efforts have focused on 2.0 micron CMOS processes which require large suspended structures in order to accommodate the design rules. This work has successfully used a 1.2 micron commercial process with a post-processing silicon etch to scale down the emitter structure to 40 X 40 microns. This allows higher density arrays, and together with using the high value poly resistor available in the 1.2 micrometer process, allows lower current operation, significantly relaxing the design constraints previously encountered. A 128 X 128 design was fabricated in this process and is characterized using a microradiometer. A silicon-on-insulator thermal pixel array design with a further reduction in emitter dimensions is also presented.

Offord, Bruce W.; Marlin, H. Ronald; Bates, Richard L.; Perkins, Gordon C.; Hutchens, Chris; Huang, Derek

2000-07-01

293

IR CMOS: infrared enhanced silicon imaging  

NASA Astrophysics Data System (ADS)

SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

2013-06-01

294

Radiation-hardened N (+) gate CMOS/SOS  

NASA Astrophysics Data System (ADS)

Process development work for a hardened N+ polysilicon-gate CMOS/SOS process has demonstrated that it is possible to make functional 4K CMOS/SOS static RAMs that are hard to 5 x 10 to the 5th power rads without the implementation of special hardened circuit design techniques. Present circuit probe yields are low, limited by the lack of a hardened low-temperature contoured field oxide. Independent research has shown that a hardened reflow process is possible for such field oxides. Development of this reflow process is nearly complete and should result in significant improvement in yields when fully integrated into the rad-hard N+ process.

Hughes, G. W.; Brucker, G. J.; Smeltzer, R. K.

1981-05-01

295

Deep-submicron tungsten gate CMOS technology  

Microsoft Academic Search

A tungsten-gate CMOS technology has been developed using a low-impurity selective epi-channel and thin gate oxide. The use of this technology leads to a reduction in threshold-voltage sensitivity to process fluctuations such as epi-channel concentration and gate-oxide thickness. The short-channel effect for deep submicron gate MOSFETs can be suppressed by a 50 approximately 10-nm-thick epi-layer with an abrupt impurity profile.

N. Kasai; N. Endo; A. Ishitani

1988-01-01

296

High-speed CMOS circuit technique  

Microsoft Academic Search

Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

JIREN YUAN; CHRISTER SVENSSON

1989-01-01

297

Performance of CMOS differential circuits  

Microsoft Academic Search

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND\\/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are

Pius Ng; Poras T. Balsara; Don Steiss

1996-01-01

298

Review of CMOS image sensors  

Microsoft Academic Search

The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still

M. Bigas; Enric Cabruja; Josep Forest; Joaquim Salvi

2006-01-01

299

Towards CMOS-compatible, solution-processed quantum dot nanocrystal optical sources, modulators, detectors, and optical signal processing elements across the extended communications band 1200-1700 nm  

Microsoft Academic Search

We review devices, fabricated using room-temperature solution spin-casting compatible with silicon post-processing, which produce, detect, modulate, and process optical signals in the spectral range from 1200-1700 nm. We first summarize the synthesis of PbS (lead sulphide) quantum dot nanocrystals 2-10 nm in diameter by solution chemistry. We then discusses the realization to date of solution-processed, silicon-compatible thin-film devices fabricated using

Edward H. Sargent

2004-01-01

300

Surface enhanced biodetection on a CMOS biosensor chip  

NASA Astrophysics Data System (ADS)

We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-? and IFN-?). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

Belloni, Federico; Sandeau, Laure; Conti, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Herv

2012-02-01

301

Modeling and simulation of TDI CMOS image sensors  

NASA Astrophysics Data System (ADS)

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

2013-09-01

302

A packaged low-noise high-speed regulated cascode transimpedance amplifier using a 0.6m N-well CMOS technology  

Microsoft Academic Search

Regulated cascode (RGC) techniques are applied to achieve better isolation of the large input parasitic capacitance in a front-end preamplifier for optical receiver applications, since the RGC circuit behaves like a common-gate transistor with large transconductance comparable to GaAs MESFET. The input resistance of the RGC circuit becomes smaller by the amount of the voltage-gain of the local feedback stage

Sung Min Park; C. Toumazou

2000-01-01

303

Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window  

Microsoft Academic Search

A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes, interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm and 65 nm) targeting the same low-power applications is presented. The impact of technology scaling on the ESD design window will be discussed.

G. Boselli; J. Rodriguez; C. Duvvury; J. Smith

2005-01-01

304

Design and fabrication of vertically-integrated CMOS image sensors.  

PubMed

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-04-27

305

Laser Operation of Nitride Laser Diodes with GaN Well Layer in 340 nm Band  

NASA Astrophysics Data System (ADS)

We have reported the laser operation of a short-wavelength ultraviolet laser diode with multiple quantum wells composed of GaN well layers. The GaN well-width is estimated to be around 1--1.5 nm. We have simulated whole laser-diode structure, and calculated wave-function overlap integrals. It is provided the integral becomes the maximum value in the well-width of 1.5 nm. The laser operation has been achieved in 340-nm-band under the pulsed current mode at room temperature. The wavelength is far from the wavelength corresponding to band gap of GaN, and the shortest lasing wavelength ever reported for a semiconductor laser composed of binary compound well layer. Moreover, the device has been realized on an Al0.2Ga0.8N underlying layer with 0.1 lower AlN mole fraction margin than that of a previous reported 342 nm laser-diode with an Al0.3Ga0.7N underlying layer. These results provide a chance to the next stage for a shorter-wavelength ultraviolet laser diode.

Kuwabara, Masakazu; Yamashita, Yoji; Torii, Kousuke; Yoshida, Harumasa

2013-08-01

306

A 250-ps time-resolution CMOS multihit time-to-digital converter for nuclear physics experiments  

SciTech Connect

This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-{micro}m CMOS process with an area of about 77 mm{sup 2}. Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps.

Bigongiari, F.; Roncella, R.; Saletti, R.; Terreni, P. [Univ. of Pisa (Italy)

1999-04-01

307

A 128 128 CMOS bio-sensor array for extracellular recording of neural activity  

Microsoft Academic Search

A CMOS sensor array for monitoring neural signals of living cells with 128 128 pixels in a 1 mm2 area is described. A standard 0.5 ?m, 5 V CMOS process extended by top electrodes covered by a relatively thin bio-compatible dielectric is used. Detection circuitry is based on a sensor-MOSFET mismatch-compensating current-mode technique.

Bjrn Eversmann; Martin Jenkner; Christian Paulus; Franz Hofmann; Ralf Brederlow; Birgit Holzapfl; Peter Fromherz; Markus Brenner; Matthias Schreiter; Reinhard Gabl; Kurt Plehnert; Michael Steinhauser; Gerald Eckstein; Doris Schmitt-Landsiedel; Roland Thewes

2003-01-01

308

An embedded analog spatial filter design of the current-mode CMOS image sensor  

Microsoft Academic Search

This investigation presents an embedded analog spatial filter, EASF, in a current-mode CMOS image sensor. The EASF successfully identifies the output value of the pixel in B\\/W so as to benefit specific real world applications. Over the last few years, image quality has been improved by better progress in CMOS process technology; however, low cost issue regarding the integration of

Pei-Yung Hsiao; Yu-Chun Hsu; Wen-Ta Lee; Chia-Chun Tsai; Chia-Hao Lee

2004-01-01

309

CMOS scaling for high performance and low power-the next ten years  

Microsoft Academic Search

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios

BIJAN DAVARI; ROBERT H. DENNARD; GHAVAM G. SHAHIDI

1995-01-01

310

A high speed camera system based on an image sensor in standard CMOS technology  

Microsoft Academic Search

In this contribution a novel camera system developed for high speed imaging will be presented. The core of the system consists of a CMOS image sensor manufactured in a 1 ?m standard CMOS process. The special merit of the image sensor is the capability to acquire more than 1000 frames\\/s using a global electronic shutter in each sensor cell. The

Nenad Stevanovic; Matthias Hillebrand; Bedrich J. Hosticka; Uri Iurgel; Andreas Teuner

1999-01-01

311

Piezoresistive cantilevers in a commercial CMOS technology for intermolecular force detection  

Microsoft Academic Search

We report the development of piezoresistive cantilevers for intermolecular force detection in biochemical sensing, by using a commercial CMOS technology. The detection of the small forces involved in molecular recognition requires cantilevers with a small spring constant and high force sensitivity. We have fabricated polycrystalline silicon cantilevers by using the two polysilicon layers of a commercial CMOS process with minimum

Guillermo Villanueva; Francesc Prez-Murano; Martin Zimmermann; Jan Lichtenberg; Joan Bausells

2006-01-01

312

Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.  

PubMed

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array. PMID:23443701

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

2011-12-01

313

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

314

A 340-nm-band ultraviolet laser diode composed of GaN well layers.  

PubMed

We have demonstrated the laser operation of a short-wavelength ultraviolet laser diode with multiple-quantum-wells composed of GaN well layers. The laser action has been achieved in 340-nm-band far from the wavelength corresponding to GaN band gap under the pulsed current mode at room temperature. The device has been realized on the Al(0.2)Ga(0.8)N underlying layer. The AlN mole fraction of the underlying layer is 0.1 lower than that of the underlying layer which was used for the previously reported 342 nm laser diode. These results provide a chance to the next step for a shorter-wavelength ultraviolet laser diode. PMID:23481771

Yamashita, Yoji; Kuwabara, Masakazu; Torii, Kousuke; Yoshida, Harumasa

2013-02-11

315

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration  

NASA Astrophysics Data System (ADS)

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 m high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

316

High-speed CMOS optical communication using silicon light emitters  

NASA Astrophysics Data System (ADS)

The idea of moving CMOS into the mainstream optical domain remains an attractive one. In this paper we discuss our recent advances towards a complete silicon optical communication solution. We prove that transmission of baseband data at multiples of megabits per second rates are possible using improved silicon light sources in a completely native standard CMOS process with no post processing. The CMOS die is aligned to a fiber end and the light sources are directly modulated. An optical signal is generated and transmitted to a silicon Avalanche Photodiode (APD) module, received and recovered. Signal detectability is proven through eye diagram measurements. The results show an improvement of more than tenfold over our previous results, also demonstrating the fastest optical communication from standard CMOS light sources. This paper presents an all silicon optical data link capable of 2 Mb/s at a bit error rate of 10-10, or alternatively 1 Mb/s at a bit error rate of 10-14. As the devices are not operating at their intrinsic switching speed limit, we believe that even higher transmission rates are possible with complete integration of all components in CMOS.

Goosen, Marius E.; Venter, Petrus J.; Du Plessis, Monuko; Nell, Ilse J.; Bogalecki, Alfons W.; Rademeyer, Pieter

2011-02-01

317

Millimeter-wave CMOS design  

Microsoft Academic Search

AbstractThis paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak of 135 GHz has been achieved with optimal device layout. The inductive quality factor is proposed as a more representative metric for transmission lines,

C. H. Doan; S. Emami; A. M. Niknejad; R. W. Brodersen

2005-01-01

318

Future of Nano CMOS Technology  

Microsoft Academic Search

CMOS technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will governed the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options for manufacturing

Hiroshi Iwai

2007-01-01

319

IR CMOS: ultrafast laser-enhanced silicon detection  

NASA Astrophysics Data System (ADS)

SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

2011-05-01

320

Reconfigurable RF CMOS Circuit for Cognitive Radio  

NASA Astrophysics Data System (ADS)

Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology can be used for RF CMOS circuit implementation. The realistic RF CMOS circuit implementation toward cognitive and/or SDR is discussed.

Masu, Kazuya; Okada, Kenichi

321

Cmos-Compatible High Voltage Integrated Circuits.  

NASA Astrophysics Data System (ADS)

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 ?m CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS -bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT. The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.

Parpia, Zahir

322

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

NASA Astrophysics Data System (ADS)

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

Zhang, Weiquan

2000-12-01

323

Ultra low power analog standard cell for low frequency CMOS filters design  

Microsoft Academic Search

A novel approach to very low frequency filters design in CMOS technology has been described in the paper. This approach is based on the application of a new universal analog cell, which can be configured as second order filter, gyrator etc. The circuit is designed in 0.35 mum n-well technology and consumes only 3 nW of power for nominal biasing

Tomasz Kulej; Armii Krajowej

2008-01-01

324

An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier  

Microsoft Academic Search

We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in

M. A. Abdalla; C. Frjdh; C. S. Petersson

2001-01-01

325

VLSI scaling methods and low power CMOS buffer circuit  

NASA Astrophysics Data System (ADS)

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Sharma, Vijay Kumar; Pattanaik, Manisha

2013-09-01

326

CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria.  

PubMed

We present the design and implementation of a prototype complementary metal-oxide semiconductor (CMOS) conductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The detection of E. coli is done by employing T4 bacteriophages as receptor organisms. The conductometric system operates by measuring the resistance of the test sample between the electrodes of a two-electrode electrochemical system (reference electrode and working electrode). The CMOS IC is fabricated in a TSMC 0.35-?m process and uses a current-to-frequency (I to F) conversion circuit to convert the test sample resistance into a digital output modulated in frequency. Pulsewidth control (one-shot circuit) is implemented on-chip to control the pulsewidth of the output digital signal. The novelty in the current work lies in the ability of the CMOS sensor system to monitor very low initial concentrations of bacteria (410(2) to 410(4) colony forming unit (CFU)/mL). The CMOS system is also used to record the interaction between E. coli and its specific receptor T4 bacteriophage. The prototype CMOS IC consumes an average power of 1.85 mW with a 3.3-V dc power supply. PMID:23851473

Lei Yao; Lamarche, P; Tawil, N; Khan, R; Aliakbar, A M; Hassan, M H; Chodavarapu, V P; Mandeville, R

2011-06-01

327

CMOS digital intra-oral sensor for x-ray radiography  

NASA Astrophysics Data System (ADS)

In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

2011-03-01

328

Fault detection in CMOS manufacturing using MBPCA  

NASA Astrophysics Data System (ADS)

This paper describes the application of model-based principal component analysis (MBPCA) to the identification and isolation of faults in CMOS manufacture. Some of the CMOS fabrication processing steps are well understood, with first principles mathematical models available which can describe the physical and chemical phenomena that takes place. The fabrication of the device using a known industrial process is therefore first modeled 'ideally', using ATHENA and MATLAB. Detailed furnace models are used to investigate the effect of errors in furnace control on the device fabrication and the subsequent effect on the device electrical properties. This models the distribution of device properties resulting from processing a stack of wafers in a furnace, and allows faults and production errors to be simulated for analysis. The analysis is performed using MBPCA. which has been shown to improve fault-detection resolution for batch processes. The diagnosis method is demonstrated on an industrial NMOS transistor fabrication process with faults introduced in places where they might realistically occur.

Lachman-Shalem, Sivan; Haimovitch, Nir; Shauly, Eitan N.; Lewin, Daniel R.

2000-08-01

329

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.  

PubMed

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices. PMID:19722537

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

330

A high-speed low-noise transimpedance amplifier in a 0.25 ?m CMOS technology  

Microsoft Academic Search

We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for

Giovanni Anelli; Kurt Borer; Luca Casagrande; Matthieu Despeisse; Pierre Jarron; Nicolas Pelloux; Shahyar Saramad

2003-01-01

331

A resistorless CMOS current reference with temperature compensation  

NASA Astrophysics Data System (ADS)

A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 ?m CMOS process. The output current is 1.5 ?A, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98 ppm/C, and the line regulation is 0.45%/V. The occupied chip area is 0.065 mm2.

Wei, Yan; Xin, Tian; Wenhong, Li; Ran, Liu

2011-03-01

332

Novel neuromorphic CMOS device array for biochemical charge sensing.  

PubMed

Novel neuromorphic CMOS device is proposed as a biochemical charge sensor. The basic architecture of an extended floating-gate field-effect transistor (FET) is modified to be suited for large-array applications. The FET has a floating-gate that is umbrella-shaped (UGFET), maximizing its charge sensing area in a much reduced transistor area. Compared to previous chemoreceptive FET-based charge sensors, the UGFET shows improved scalability and sensitivity. 3-D device simulations validate the UGFET model. The design is fabricated in a standard CMOS process and characterized. Experimental results on biochemical charge sensing are presented employing the transconductance and subthreshold measurement schemes. PMID:19163158

Pandey, Santosh; Daryanani, Michelle; Chen, Baozhen; Tao, Chengwu

2008-01-01

333

Nanomechanical switch for integration with CMOS logic.  

SciTech Connect

We designed, fabricated and measured the performance of nanoelectromechanical (NEMS) switches. Initial data are reported with one of the switch designs having a measured switching time of 400 ns and an operating voltage of 5 V. The switches operated laterally with unmeasurable leakage current in the 'off' state. Surface micromachining techniques were used to fabricate the switches. All processing was CMOS compatible. A single metal layer, defined by a single mask step, was used as the mechanical switch layer. The details of the modeling, fabrication and testing of the NEMS switches are reported.

Nordquist, Christopher Daniel; Wolfley, Steven L.; Baker, Michael Sean; Czaplewski, David A.; Wendt, Joel Robert; Kraus, Garth Merlin; de Boer, Maarten Pieter; Patrizi, Gary A.

2008-11-01

334

Low-light hyperspectral imager for characterization of biological samples based on an sCMOS image sensor  

NASA Astrophysics Data System (ADS)

The new "scientific CMOS" (sCMOS) sensor technology has been tested for use in hyperspectral imaging. The sCMOS offers extremely low readout noise combined with high resolution and high speed, making it attractive for hyperspectral imaging applications. A commercial HySpex hyperspectral camera has been modified to be used in low light conditions integrating an sCMOS sensor array. Initial tests of fluorescence imaging in challenging light settings have been performed. The imaged objects are layered phantoms labelled with controlled location and concentration of fluorophore. The camera has been compared to a state of the art spectral imager based on CCD technology. The image quality of the sCMOS-based camera suffers from artifacts due to a high density of pixels with excessive noise, attributed to the high operating temperature of the array. Image processing results illustrate some of the benefits and challenges of the new sCMOS technology.

Hernandez-Palacios, J.; Randeberg, L. L.; Haug, I. J.; Baarstad, I.; Lke, T.; Skauli, T.

2011-02-01

335

Materials and structures for future nano CMOS  

Microsoft Academic Search

Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels, and even beautiful transistor operation of several nm gate length CMOS devices were reported in conferences. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. It is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into

Hiroshi Iwai

2011-01-01

336

CMOS Circuit Speed and Buffer Optimization  

Microsoft Academic Search

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown

Nils Hedenstierna; Kjell O. Jeppson

1987-01-01

337

SiGe BiCMOS manufacturing platform for mmWave applications  

Microsoft Academic Search

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT\\/fMAX SiGe NPN with deep trench isolation into 0.18mum and 0.13mum node CMOS processes along with high density 5.6fF\\/mum2 stacked MIM capacitors,

Arjun Kar-Roy; David Howard; Edward Preisler; Marco Racanelli; Samir Chaudhry; Volker Blaschke

2010-01-01

338

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

339

Photocurrent estimation for a self-reset CMOS image sensor  

Microsoft Academic Search

CMOS image sensors are capable of very high frame rate non- destructive readout. This capability and the potential of integrating memory and signal processing with the sensor on the same chip enable the implementation of many still and video imaging applications. An important example is dynamic range extension, where several images are captured during a normal exposure time - shorter

Xinqiao Liu; Abbas El Gamal

2002-01-01

340

Photocurrent estimation from multiple nondestructive samples in CMOS image sensor  

Microsoft Academic Search

CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic

Xinqiao Liu; Abbas El Gamal

2001-01-01

341

Overcoming scaling concerns in a radiation-hardening CMOS technology  

SciTech Connect

Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.

Maimon, J.; Haddad, N.

1999-12-01

342

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K.

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

343

Low-Power SRAMs in Nanoscale CMOS Technologies  

Microsoft Academic Search

As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today's SRAM design from perspectives of both process technology optimization and design innovation.

Kevin Zhang; Fatih Hamzaoglu; Yih Wang

2008-01-01

344

CMOS current source for shortened square wave waveforms  

Microsoft Academic Search

In many practical cases sinusoidal signals can be replaced with suitable approximations. Well-known alternative is the three level shortened square wave. By introducing more equally spaced levels, higher harmonics can be further reduced. This multilevel signal is easy to generate digitally and enables simple digital processing involving only additions and shifting. An efficient CMOS technology based current source can be

A. Kasemaa; P. Annus

2008-01-01

345

Total dose hardness of three commercial CMOS microelectronics foundries  

Microsoft Academic Search

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 ?m and 0.8 ?m processes, an Orbit 1.2 ?m process, and an AMI 1.6 ?m process. We

J. V. Osborn; R. C. Lacoe; D. C. Mayer; G. Yabiku

1998-01-01

346

MonoColor CMOS sensor  

NASA Astrophysics Data System (ADS)

A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since the majority of pixels are monochrome, MonoColor sensor maintains 98% barcode decode performance compared with a pure monochrome CMOS sensor. With the help of monochrome and color pixel fusion technique, the resulting color pictures have similar color quality in terms of Color Semantic Error (CSE) compared with a Bayer pattern (RGB) CMOS color camera. Since monochrome pixels are more sensitive than color pixels, a MonoColor sensor produces in general about 2X brighter color picture and higher luminance pixel resolution.

Wang, Ynjiun P.

2009-02-01

347

Damage effect on CMOS detector irradiated by single-pulse laser  

NASA Astrophysics Data System (ADS)

Imaging systems are widespread observation tools used to fulfill various functions such as recognition, detection and identification. These devices such as CMOS and CCD can be damaged by laser. It is very important to study the damage mechanism of CMOS and CCD. Previous studies focused on the interference and damage of CCD. There were only a few researches on the interaction of CMOS and the laser. In this paper, using a 60ns, 1064 nm single-pulse laser to radiate the front illuminated CMOS detector, the typical experiment phenomena were observed and the corresponding energy density thresholds were measured. According to the experiment phenomena, hard damage process of CMOS can be divided into 3 stages. Based on the structure and working principle of CMOS, studying the damage mechanism of 3 stages by theoretical analysis, point damage was caused by the increase in leakage current due to structural defects resulting from thermal effects, half black line damage and black lines cross damage were caused by signal interruption due to that the device circuit fuses were cut. Enhancing the laser energy density, the damaged area expanded. Even if the laser energy density reached 1.95 J/cm2, black lines has covered most of the detector pixels, the detector still not completely lapsed, the undamaged area can imaging due to that pixels of CMOS were separated with each other. Experiments on CMOS by laser pulses at the wavelength of 1064 nm and the pulse duration in 25ps was carried out, then the thresholds with different pulse durations were measured and compared. Experiments on CMOS by fs pulsed laser at the frequency of 1 Hz, 10 Hz and 1000 Hz were carried out, respectively, the results showed that a high-repetition-rate laser was easier to damage CMOS compared to single-shot laser.

Guo, Feng; Zhu, Rongzhen; Wang, Ang; Cheng, Xiang'ai

2013-09-01

348

0.25 ?m CMOS and BiCMOS single-chip direct-conversion Doppler radars for remote sensing of vital signs  

Microsoft Academic Search

Summary form only given. A fully integrated direct conversion Doppler radar that detects heart and respiration movement at a distance of 50 cm is described. The 1.6 GHz transceiver is implemented in both CMOS and BiCMOS technologies, with each chip occupying 14 mm2 using a 0.25 ?m silicon processes. The effects on system sensitivity of phase noise at small offset

Amy D. Droitcour; Olga Boric-Lubecke; Victor M. Lubecke; Jenshan Lin

2002-01-01

349

A 0.18 ?m BiCMOS technology featuring 120\\/100 GHz (fT\\/fmax) HBT and ASIC-compatible CMOS using copper interconnect  

Microsoft Academic Search

A BiCMOS technology is presented that integrates a high performance NPN (fT=120 GHz and fmax=100 GHz), ASIC compatible 0.11 ?m Leff CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved

A. Joseph; D. Coolbaugh; M. Zierak; R. Wuthrich; P. Geiss; Z. He; X. Liu; B. Orner; J. Johnson; G. Freeman; D. Ahlgren; B. Jagannathan; L. Lanzerotti; V. Ramachandran; J. Malinowski; H. Chen; J. Chu; P. Gray; R. Johnson; J. Dunn; S. Subbanna; K. Schonenberg; D. Harame; R. Groves; K. Watson; D. Jadus; M. Meghelli; A. Rylyakov

2001-01-01

350

A CMOS image sensor using floating capacitor load readout operation  

NASA Astrophysics Data System (ADS)

In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has been produced using 0.18 ?m 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5 mmH x 2.5 mmV, the pixel size is 4.5 ?mH x 4.5 ?mV, and the number of pixels is 400H x 300V. This image sensor consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168 ?Vrms. The noise of conventional image sensor is 466 ?Vrms therefore, reduction of 63.8 % of noise was achieved.

Wakashima, S.; Goda, Y.; Li, T. L.; Kuroda, R.; Sugawa, S.

2013-02-01

351

Design and fabrication of a CMOS MEMS logic gate  

NASA Astrophysics Data System (ADS)

This study aims to develop a novel CMOS-MEMS logic gate via commercially available CMOS process (TSMC, 2P4M). Compared to existing CMOS MEMS designs, which uses foundry processes, the proposed design imposes several new challenges including: carrying two voltage levels on a non-warping suspended plate, metal-to- metal contact, and etc. Different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer. And different wet etchants are investigated to remove sacrificial layers without attacking structure layers and features. In a prototype design, the selected structure layer is metal-3 and oxide film; the device is released using AD-10 and titanium etchant; the device is 250 ?m long, 100 ?m wide, and 1.5 ?m gap. The experimental results show that the suspended plate slightly curls down 0.485 ?m. This device can be actuated by 10/0 V with a moving distance 50nm. The resonant frequency is measured at 36 kHz. Due to the damage of the tungsten plugs, the logic function can only be verified by its mechanical movements instead of electrical readouts for now.

Tsai, Chun-Yin; Chen, Tsung-Lin; Liao, Hsin-Hao; Lin, Chen-Fu; Juang, Ying-Zong

2011-02-01

352

A novel multi-actuation CMOS RF MEMS switch  

NASA Astrophysics Data System (ADS)

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

353

Single poly PMOS-based CMOS-compatible low voltage OTP  

NASA Astrophysics Data System (ADS)

A PMOS-based non-volatile memory cell fully compatible with standard CMOS fabrication processes is presented. It consists of a PMOS access transistor in series with a PMOS transistor whose gate is left floating. The cell configuration eliminates the requirement of a control gate, and therefore can be fabricated without using double poly gates. The cell saves area compared to other single poly non-volatile memory cells based on CMOS approaches, which require both NMOS and PMOS transistors. It also avoids the risk of latch-up. The cells were fabricated using a 350nm standard CMOS process. The programming mechanism of the cell is hot electron injection. The programming operation can be performed at programming voltages as low as |Vds|=4.5V. The cell can be used as a low voltage OTP and provides a very cheap alternative to integrate OTPs in CMOS ICs without any modification of the fabrication process.

Vega-Castillo, Paola; Krautschneider, Wolfgang H.

2005-06-01

354

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC  

NASA Astrophysics Data System (ADS)

This paper is intended to discuss the features of a novel kind of monolithic active pixel sensors (MAPS) in deep submicron CMOS technology (130 nm minimum feature size) for use in charged particle trackers and vertex detectors. As compared to conventional MAPS with 3-transistor readout scheme, the design approach proposed here, where a deep N-well (DNW) is used as the collecting electrode, lends itself to pixel-level sparsified processing and is expected to provide the ability to manage the large data flow of information anticipated for future, high luminosity colliders. Lately, the applicability of the DNW-MAPS concept to the design of the vertex detector for future high luminosity colliders, like the International Linear Collider (ILC), has been investigated. This paper will discuss the design and performance of a recently submitted DNW monolithic sensor, the SDR0 (Sparsified Digital Readout) chip, including different test structures, where both analog (charge amplification and threshold discrimination) and digital (sparsification, time stamping) functions have been integrated inside the elementary sensor, as large as 25?m25?m.

Traversi, Gianluca; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Speziali, Valeria

2007-10-01

355

An integrated CMOS time interval measurement system with subnanosecond resolution for the WA-98 calorimeter  

SciTech Connect

The time interval measurement system of the WA-98 calorimeter is presented. This system consists of a constant fraction discriminator (CFD), a variable delay circuit, a time-to-amplitude converter (TAC), and a Wilkinson analog-to-digital converter (ADC) all realized in a 1.2-{micro}m N-well CMOS process. These circuits measured the time interval between a reference logic signal and a photomultiplier tube (PMT) signal that had amplitude variations of 100:1 and 10-ns rise and fall times. The system operated over the interval range from 2 ns to 200 ns with a resolution of {approximately}{+-}300 ps including all walk and jitter components. The variable delay circuit allowed the CFD output to be delayed /by up to 1 {micro}s with a jitter component of {approximately}0.04% of the delay setting. These circuits operated with a 5-V power supply. Although this application was in nuclear physics instrumentation, these circuits could also be useful in other scientific measurements, medical imaging, automatic test equipment, ranging systems, and industrial electronics.

Simpson, M.L.; Britton, C.L.; Wintenberg, A.L.; Young, G.R. [Oak Ridge National Lab., TN (United States)

1997-02-01

356

Finite-difference time domain based electro-optical methodologies to improve CMOS image sensor pixels performances  

Microsoft Academic Search

The current CMOS image sensors market trend leads to achieve good image resolution at small package size and price, thus CMOS image sensors roadmap is driven by pixel size reduction while maintaining good electro-optical performances. As both diffraction and electrical effects become of greater importance, it is mandatory to have a simulation tool able to early help process and design

Flavien Hirigoyen; Axel Crocherie; Pierre Boulenc; Jrme Vaillant; Clment Tavernier; Didier Hrault

2010-01-01

357

A 1\\/4in 2M pixel CMOS image sensor with 1.75 transistor\\/pixel  

Microsoft Academic Search

A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented. This image achieves a 2.25?m pixel pitch with 25% aperture ratio in a 0.25?m IP2M CMOS process.

M. Mori; M. Katsuno; S. Kasuga; T. Murata; T. Yamaguchi

2004-01-01

358

Designing analog and RF circuits in nanoscale CMOS technologies: Scale the supply, reduce the area and use digital gates  

Microsoft Academic Search

We will present our recent research that has centered around three themes aimed at facilitating the design of analog and RF interface circuits in digital nanoscale CMOS processes. Nanometer CMOS is operating with supply voltages of about 1 V or less and for low power operation in future deeply scaled nodes supply voltages as low as 0.5 V are projected.

P. Kinget

2009-01-01

359

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio  

Microsoft Academic Search

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

2007-01-01

360

Steps toward fabricating cryogenic CMOS compatible single electron devices for future qubits.  

SciTech Connect

We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 mum complementary metal oxide semiconductor (CMOS) process intended to operate at 100 mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2 K is presented.

Wendt, Joel Robert; Childs, Kenton David; Ten Eyck, Gregory A.; Tracy, Lisa A.; Eng, Kevin; Stevens, Jeffrey; Nordberg, Eric (University of Wisconsin-Madison); Carroll, Malcolm S.; Lilly, Michael Patrick

2008-08-01

361

A platform for monolithic CMOS-MEMS integration on SOI wafers  

NASA Astrophysics Data System (ADS)

A new platform for micro- and nano-electromechanical systems based on crystalline silicon as the structural layer in CMOS substrates is presented. This platform is fabricated using silicon on insulator (SOI) substrates, which allows the monolithic integration of the mechanical transducer on crystalline silicon while the characteristics of the structural layer are kept independent from the CMOS technology. We report the design characteristics, the fabrication process and an example of application of the CMOS SOI-MEMS platform to obtain a mass sensor based on a crystalline silicon resonating cantilever.

Villarroya, Mara; Figueras, Eduard; Montserrat, Josep; Verd, Jaume; Teva, Jordi; Abadal, Gabriel; Prez Murano, Francesc; Esteve, Jaume; Barniol, Nria

2006-10-01

362

Smart CMOS image sensor arrays  

Microsoft Academic Search

In this paper, we present several smart image sensor arrays intended for various applications. We discuss the realization of image sensors in CMOS technology and show some examples of one-dimensional (1-D) and two-dimensional (2-D) smart image arrays

Michael Schanz; Werner Brockherde; Ralf Hauschild; Bedrich J. Hosticka; Markus Schwarz

1997-01-01

363

MonoColor CMOS sensor  

Microsoft Academic Search

A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since

Ynjiun P. Wang

2009-01-01

364

CMOS voltage to current transducers  

Microsoft Academic Search

This paper explores in detail the possible approaches to. the design of voltage- or current-controllable linear transconductance elements needed for the design of continuous-time CMOS active filters. The focus of the paper is on circuit configurations, techniques of achieving linearity, and temperature compensation using the controlling variable. Circuit techniques for obtaining small transductance values are outlined. Simulation results are presented.

R. Torrance; T. Viswanathan; J. Hanson

1985-01-01

365

Low Power CMOS Digital Design  

Microsoft Academic Search

: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which

Anantha P. Chandrakasan; Samuel Sheng; Robert W. Brodersen

1995-01-01

366

Integration of top-emitting organic light emitting diodes on CMOS substrates  

NASA Astrophysics Data System (ADS)

The integration of top-emitting OLEDs on CMOS substrates is of interest for a variety of applications. Whereas OLEDbased microdisplays have already been commercialized, OLEDs could also be used to realize sensor applications, optocouplers, etc. Red top-emitting OLED structures were deposited on CMOS substrates. The OLED technology includes phosphorescent emitters and doped transport layers. This approach results in high efficiencies and low operating voltage. The CMOS top metal is crucial for this type of devices since this layer is the interface between CMOS and OLED technology. In a first step, OLED process development was carried out on passive substrates without transistor circuit but CMOS compatible interface. Luminance values of 100cd/m2 and 1000cd/m2 are reached at 2.45V and 3.1V, respectively. Current efficiency at these luminance values is 14.2 cd/A and 13.4 cd/A, respectively, with a peak wavelength of 627nm. This OLED stack was then successfully prepared on full-CMOS-substrates. luminance values is 14.2 cd/A and 13.4 cd/A, respectively, with a peak wavelength of 627nm. This OLED stack was then successfully prepared on full-CMOS-substrates.

Toerker, M.; Grillberger, Ch.; Kreye, D.; Vogel, U.; Amelung, J.

2008-05-01

367

Design of clock recovery circuits for optical clocking in DSM CMOS  

NASA Astrophysics Data System (ADS)

CMOS technology scaling especially in the sub-100 nm regime has made signaling in long global a challenge, resulting in a need for an improved interconnect technology. Optical signalling is a promising alternative to existing global interconnects and alleviates interconnect bottle-neck. This paper presents a design of a CMOS trans-impedance amplifier (TIA) that is intended for a truly CMOS compatible on-chip optical clock distribution system. This TIA employs replica biasing technique to achieve stability while maximizing its bandwidth and gain. The design was implemented in a 0.35?m CMOS process and is currently under probe testing. The simulation results show that the design achieved a bandwidth of 1GHz and gain of 128dB-?. Extensive Monte-Carlo simulations indicate the superior characteristics of stability under a variety of process and environmental variations.

Thangaraj, Charles; Stephenson, Kevin; Chen, Tom; Lear, Kevin; Raza, Abdul Matheen

2007-06-01

368

Temperature-dependent yield effects on composite beams used in CMOS MEMS  

NASA Astrophysics Data System (ADS)

This paper presents an experimentally verified analytical model of temperature-dependent yield effects on the curvatures of composite beam structures used in complementary metal-oxide semiconductor microelectromechanical systems (CMOS MEMS). The temperature-dependent effects on composite beam curvatures of a thermal process can be predicted by extracting key parameters from the measured curvatures of a limited number of CMOS MEMS composite-layer combinations. The effects due to thermal history in MEMS packaging, which change the characteristics of beam curvatures due to material yield, are further analyzed. The models are verified with measured results from beam structures fabricated by an application-specific integrated circuit-compatible 0.18 m 1P6M CMOS MEMS process using a white light interferometer. These models can be applied in electronic design automation tools to provide good prediction of temperature-dependent properties related to CMOS MEMS beam curvature, such as sensing capacitance, for monolithic sensor system on chip design.

Y Kuo, F.; Chang, C. S.; Liu, Y. S.; Wen, K. A.; Fan, L. S.

2013-03-01

369

Nanophotonic integration in state-of-the-art CMOS foundries.  

PubMed

We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming. PMID:21369052

Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popovi?, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Krtner, Franz X; Smith, Henry I; Stojanovi?, Vladimir; Ram, Rajeev J

2011-01-31

370

QE reduction due to pixel vignetting in CMOS image sensors  

NASA Astrophysics Data System (ADS)

CMOS image sensor designers take advantage of technology scaling either by reducing pixel size or by adding more transistors to the pixel. In both cases, the distance from the chip surface to the photodiode increases relative to the photodiode planar dimensions. As a result, light must ravel through an increasingly deeper and narrower `tunnel' before it reaches the photodiode. This is especially problematic for light incident at oblique angles; the narrow tunnel walls cast a shadow on the photodiode, which in turn severely reduces its effective QE. We refer to this phenomenon as pixel vignetting. The paper presents experimental results from a 640 X 512 CMOS image sensor fabricated using a 0.35(mu) 4-layer metal CMOs process that shows significant QE reduction of up to 50% for off-axis relative to on-axis pixels. Using simple geometric models of the sensor and the imaging optics, we compare the QE for on and off-axis pixels. We find that our analysis results support the hypothesis that the experimentally observed QE reduction is indeed due to pixel vignetting. We show that pixel vignetting becomes more severe as CMOS technology scales, even for a 2-layer metal APS pixel. Finally, we briefly discuss several potential solutions to the pixel vignetting problem.

Catrysse, Peter B.; Liu, Xinqiao; El Gamal, Abbas

2000-05-01

371

CMOS image sensor with contour enhancement  

NASA Astrophysics Data System (ADS)

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 1616 2D circuit array are implemented using CSMC 0.5?m DPTM CMOS process.

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-05-01

372

Total dose radiation effects on the hardened CMOS\\/bulk and CMOS\\/SOS  

Microsoft Academic Search

Radiation-resistant performance of commercial and rad-hard CMOS\\/bulk and CMOS\\/SOS devices is presented in the total dose environment, when the static power currents of CMOS are increased by a hundred times over the limit value before irradiation, the IDD is determined as the failure criteria of ionizing radiation damage. The ? total dose ionizing radiation failure threshold of commercial CMOS devices

Panxun Chen; Hongzhi Wu; Guanglun Li; Yunhan He; Peijen Li; Yi Mao

1991-01-01

373

Standard CMOS piezoresistive sensor to quantify heart cell contractile forces  

Microsoft Academic Search

A MEMS force transducer system, with a volume less than one cubic millimeter, is being developed to measure forces generated by living, isolated cardiac muscle cells. Cell attachment and measurement of contractile forces have been demonstrated with prototype hinged polysilicon devices. A new transducer system has been fabricated using a standard CMOS process with a post-processing XeF2 etch step. The

Gisela Lin; Kristofer S. J. Pister; Kenneth P. Roos

1996-01-01

374

Low noise current-mode CMOS transimpedance amplifier for giga-bit optical communication  

Microsoft Academic Search

A novel current-mode CMOS transimpedance amplifier is described. The design uses a common-gate regulated cascode configuration providing low input impedance and low input current noise. HSPICE simulations using a 0.6 ?m CMOS process give 3.5 GHz bandwidth, 61 dB transimpedance gain, 4.2 pA\\/?(Hz) equivalent input noise current spectral density, and 135 mW power consumption. Measured results of a previous test

S. M. Park; C. Toumazou

1998-01-01

375

A 200MHz CMOS phase-locked loop with dual phase detectors  

Microsoft Academic Search

,4bstrszct A high-frequency integrated CMOS phase-locked loop (PLL) inckrdlng two phase detectors is presented. Tfse design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase- frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2-pm CMOS p-well process was used to fabricate the circuit.

KURT M. WARE; HAE-SEUNG LEE; CHARLES G. SODINI

1989-01-01

376

Technologies for (sub-) 45nm Analog\\/RF CMOS - Circuit Design Opportunities and Challenges  

Microsoft Academic Search

The new process module and device architecture options emerging for (sub-) 45nm CMOS, lead to both opportunities and challenges for analog\\/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for

S. Decoutere; P. Wambacq; V. Subramanian; J. Borremans; A. Mercha

2006-01-01

377

A CMOS Image Sensor with a Buried-Channel Source Follower  

Microsoft Academic Search

This paper presents a CMOS image sensor with a pinned-photodiode 4T active-pixel design (APS) that uses a buried-channel source follower (BSF) as the in-pixel amplifier. A prototype of the image sensor has been fabricated in a 0.18mum CMOS process. Measurements show that compared to a regular imager with a standard nMOS transistor surface-mode source follower (SSF), the new pixel structure

Xinyang Wang; M. F. Snoeij; P. R. Rao; A. Mierop; A. J. P. Theuwissen

2008-01-01

378

High sensitivity and no-cross-talk pixel technology for embedded CMOS image sensor  

Microsoft Academic Search

A high-photosensitivity and no-cross-talk pixel technology has been developed for an embedded active-pixel CMOS image sensor using a 0.35-?m CMOS logic process. To increase photosensitivity, we developed a deep low-concentration p-well (deep p-well) photodiode. To suppress pixel cross-talk caused by obliquely incident light, a double-metal photoshield was used. The cross-talk caused by electron diffusion in the substrate was suppressed by

M. Furumiya; H. Ohkubo; Y. Muramatsu; S. Kurosawa; Y. Nakashiba

2000-01-01

379

High-sensitivity and no-crosstalk pixel technology for embedded CMOS image sensor  

Microsoft Academic Search

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-?m CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si3N4 film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used

Masayuki Furumiya; Hiroaki Ohkubo; Yasunori Muramatsu; Susumu Kurosawa; Fuyuki Okamoto; Yuki Fujimoto; Yasutaka Nakashiba

2001-01-01

380

Fixed-Pattern Noise Induced by Transmission Gate in Pinned 4T CMOS Image Sensor Pixels  

Microsoft Academic Search

In this paper, we present the characterization and analysis of fixed-pattern noise (FPN) in CMOS image sensor (CIS) pixels fabricated in CMOS 0.18-mum process. The experimental results demonstrate that the dark signal degradation of pinned 4T CIS is mainly due to the dark current generated from the transmission gate (TG) instead of the photodiode (PD). From our investigations of gate

Xinyang Wang; Padmakumar R. Rao; A. J. P. Theuwissen

2006-01-01

381

A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC  

Microsoft Academic Search

A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame

M. R. Snoeij; P. Donegan; A. J. P. Theuwissen; K. A. A. Makinwa; J. H. Huijsing

2007-01-01

382

High performance FDSOI CMOS technology with metal gate and high-k  

Microsoft Academic Search

A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (Tinv) down to 14A with a gate leakage current of 0.2A\\/cm2. This represents a six order of

B. Doris; Y. H. Kim; B. P. Linder; M. Steen; V. Narayanan; D. Boyd; J. Rubino; L. Chang; J. Sleight; A. Topol; E. Sikorski; L. Shi; L. Wong; K. Babich; Y. Zhang; P. Kirsch; J. Newbury; J. F. Walker; R. Carruthers; C. D'Emic; P. Kozlowski; R. Jammy; K. W. Guarini; M. Leong

2005-01-01

383

A 2.7 V 900 MHz CMOS LNA and mixer  

Microsoft Academic Search

The demand for portable wireless communications systems increases the focus on radio frequency (RF) IC implementations. At the same time, fine-line CMOS process technologies offer potential for RF applications. This 2.7 V, 900 MHz, CMOS low-noise amplifier (LNA) and mixer employs a current reuse technique that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to

Andrew N. Karanicolas

1996-01-01

384

A CMOS low-noise amplifier with impedance feedback for ultra-wideband wireless receiver system  

Microsoft Academic Search

In this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, a cascoded amplifier with shunt-peaked load, a RLC-impedance feedback loop and an output buffer for measurement purpose. It is fabricated in TSMC 0.18 um standard RF CMOS process. The LNA gives 11.5 dB maximum

Zhe-Yang Huang; Che-Cheng Huang; Chun-Chieh Chen; Chung-Chih Hung; Christina F. Jou

2008-01-01

385

A 0.25 ?m CMOS OPLL transmitter IC for GSM and DCS  

Microsoft Academic Search

A single chip CMOS GSM\\/DCS dual-band offset-PLL transmitter is presented in this paper. This chip includes a quadrature modulator and an offset-PLL (OPLL) modulation loop. Except for the loop filter and the high-power voltage controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter IC is fabricated in 0.25 ?m CMOS process. The

Peng-Un Su; Chun-Ming Hsu

2004-01-01

386

High-performance CMOS variability in the 65-nm regime and beyond  

Microsoft Academic Search

Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a

Kerry Bernstein; David J. Frank; Anne E. Gattiker; Wilfried Haensch; Brian L. Ji; Sani R. Nassif; Edward J. Nowak; Dale J. Pearson; Norman J. Rohrer

2006-01-01

387

An improved dynamic-biased CMOS operational amplifier for biomedical circuit applications  

Microsoft Academic Search

An improved dynamic-biased CMOS operational amplifier for biomedical circuits is presented in this paper. The proposed ultra-low power operational amplifier comprises a weak-inversion biased differential input stage, a pseudo class-AB output stage and a multi-phase master bias dynamic biasing circuit. Using GLOBALFOUNDRIES 0.18 ?m CMOS process, the proposed amplifier, without dyamic biasing circuit, consumes a static supply current of 5.94

H. L. Tan; G. T. Ong; P. K. Chan

2011-01-01

388

A 1.5 V CMOS VGA based on pseudo-differential structures  

Microsoft Academic Search

A CMOS variable-gain amplifier that works down to VDD=1.5 V is described. The gain characteristic is arranged to be a nearly exponential function of control voltage by a novel circuit topology that utilizes triode-biased transistors in pseudo-differential configurations. This circuit is designed using a 0.35 ?m CMOS process and operates at a 3-dB frequency of 21 MHz with a maximum

Michael M. Green; Sridevi Joshi

2000-01-01

389

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries  

Microsoft Academic Search

Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis

V. Re; M. Manghisoni; L. Ratti; V. Speziali; G. Traversi

2005-01-01

390

Performance of 1-10GHz traveling wave amplifiers in 0.18-?m CMOS  

Microsoft Academic Search

The authors present two four-stage traveling-wave amplifiers (TWA) fabricated in a 0.18-?m CMOS process. A TWA with an internal drain bias network achieved a gain of 5 dB out to 10 GHz, and another TWA without an on-chip bias network achieved a gain of 8 dB out to 10 GHz. These are the highest frequency CMOS TWAs known to the

B. M. Frank; A. P. Freundorfer; Y. M. M. Antar

2002-01-01

391

Marching Pixels: A new Organic Computing Principle for Smart CMOS Camera Chips  

Microsoft Academic Search

We present a new method denoted as Marching Pixels based on organic computing principles for hardwired image pre-processing operations in CMOS camera chips. Marching Pixels are life-like objects which are travelling within a pixel array to solve in a self-organising way tasks like object detection, object centre point detection or the determination of trajectories of moving objects. Our CMOS camera

Dietmar Fey

392

A 150 MIPS\\/W CMOS RISC processor for PDA applications  

Microsoft Academic Search

This CMOS microprocessor has performance of about 45MIPS at 50 MHz with about 300 mW power dissipation at 3.3 V power supply. It implements about 440 k transistors in a 25 mm2 die fabricated by 0.41 ?m double metal CMOS. It is designed as a core processor for PDA applications, that require high speed graphical operation and digital signal processing

M. Nagamatsu; H. Tago; T. Mijamori; M. Kamata; H. Murakami; Y. Ootaguro; H. Goto; T. Utsumi; T. Teruyama; K. Mabuchi; A. Kawasumi; K. Malik

1995-01-01

393

BCD (Bipolar-CMOS-DMOS) technology trends for power management IC  

Microsoft Academic Search

This paper reviews the technology trends of BCD (Bipolar-CMOS-DMOS) technology in terms of voltage capability, switching speed of power transistor, and high integration of logic CMOS for SoC (System-on-Chip) solution requiring high-voltage devices. Recent trends such like modularity of the process, power metal routing, and high-density NVM (Non-Volatile Memory) are also discussed. Power management is becoming highly growing market in

Il-Yong Park; Yong-Keon Choi; Kwang-Young Ko; Sang-Chul Shim; Bon-Keun Jun; Nam-Chil Moon; Nam-Joo Kim; Kwang-Dong Yoo

2011-01-01

394

A novel, low voltage, precision CMOS current reference with no external components  

Microsoft Academic Search

A novel, precision current reference with low temperature and supply sensitivity and without any external component has been designed in a 0.18?m CMOS mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit like a beta multiplier. The simulation results show max-to-min fluctuation of about 1% over a temperature range of -20 C to

Rasoul Dehghani; S. Mojtaba Atarodi

2003-01-01

395

CMOS-compatible zero-mask One Time Programmable (OTP) memory design  

Microsoft Academic Search

A method to design CMOS-compatible diode-based One-Time Programmable (OTP) memory is discussed in this paper. In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. Different memory cells were fabricated in

Wan Tim Chan; K. P. Ng; M. C. Lee; K. C. Kwong; Lin Li; R. Ng; Tsz Yin Man; Mansun Chan

2008-01-01

396

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation  

Microsoft Academic Search

A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation schemes is proposed. The proposed sensor consists of the sensor device, its bias and signal-processing circuit which is fully compatible with a standard CMOS technology. For the high magnetic sensitivity, the MAGFET is implemented with proper geometric parameters. The TDC-based digital circuit is proposed for the low power

Young-Jae Min; Soo-Won Kim

2008-01-01

397

High performance and low power transistors integrated in 65nm bulk CMOS technology  

Microsoft Academic Search

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 %

Z. Luo; A. Steegen; M. Eller; R. Mann; C. Baiocco; P. Nguyen; L. Kim; M. Hoinkis; V. Ku; V. Klee; F. Jamin; P. Wrschka; P. Shafer; W. Lin; S. Fang; A. Ajmera; W. Tan; R. Mo; J. Lian; D. Vietzke; C. Coppock; A. Vayshenker; T. Hook; V. Chan; K. Kim; A. Cowley; S. Kim; E. Kaltalioglu; B. Zhang; S. Marokkey; Y. Lin; K. Lee; H. Zhu; M. Weybright; R. Rengarajan; J. Ku; T. Schiml; J. Sudijono; I. Yang; C. Wann

2004-01-01

398

Robust CMOS Micromachined Inductors With Structure Supports for Gilbert Mixer Matching Circuits  

Microsoft Academic Search

In this brief, three novel structure supports for on-chip CMOS-based micromachined inductors are proposed to improve mechanical stability. The inductors are fabricated using a two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established for performance analysis of the inductors before fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve

Jerry C. Wu; Mona E. Zaghloul

2009-01-01

399

A SiGe HBT BiCMOS technology for mixed signal RF applications  

Microsoft Academic Search

We present results of IBM's Silicon Germanium HBT 0.35 ?m Leff BiCMOS process with 3 level metal on 200 mm wafers. CMOS devices, as well as resistors, capacitors, inductors and other key passive elements are integrated into a high performance SiGe HBT NPN technology without sacrificing key bipolar characteristics (ft, fmax). These results demonstrate the potential of designing analog\\/mixed signal

D. C. Ahlgren; G. Freeman; S. Subbanna; R. Groves; D. Greenberg; J. Malinowski; D. Nguyen-Ngoc; S. J. Jeng; K. Stein; K. Schonenberg; D. Kiesling; B. Martin; S. Wu; D. L. Harame; B. Meyerson

1997-01-01

400

An advanced 0.4 ?m BiCMOS technology for high performance ASIC applications  

Microsoft Academic Search

An advanced 0.4 ?m BiCMOS technology has been developed for high-performance ASIC (application-specific integrated circuit) applications. The technology consists of a core 3.3 V CMOS process featuring 0.4 ?m effective channel lengths into which a high-performance n-p-n device module has been integrated. The ECL (emitter coupled logic) circuits are designed to operate with a conventional supply voltage of 5.2 V

J. Kirchgessner; J. Teplik; V. Ilderem; D. Morgan; R. Parmar; S. R. Wilson; J. Freeman; C. Tracy; S. Cosentino

1991-01-01

401

Using CMOS image sensors to detect photons  

NASA Astrophysics Data System (ADS)

A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS image sensor is deduced. After filtering out the noise of the pixel signals of CMOS image sensor, the number of photons received by every pixel of the CMOS image sensor is obtained. Compared with CCD camera, the CMOS image sensor has some advantages in measuring the properties of cold-atom-cloud,such as quick response, large sensory area, low cost, and so on.

Xu, Chenzhi; Tong, Xiaobo; Zhou, Xiang; Zheng, Xiaodong; Xu, Yunfei

2010-04-01

402

Digital-Centric RF CMOS Technologies  

NASA Astrophysics Data System (ADS)

Analog-centric RFCMOS technology has played an important role in motivating the change of technology from conventional discrete device technology or bipolar IC technology to CMOS technology. However it introduces many problems such as poor performance, susceptibility to PVT fluctuation, and cost increase with technology scaling. The most important advantage of CMOS technology compared with legacy RF technology is that CMOS can use more high performance digital circuits for very low cost. In fact, analog-centric RF-CMOS technology has failed the FM/AM tuner business and the digital-centric CMOS technology is becoming attractive for many users. It has many advantages; such as high performance, no external calibration points, high yield, and low cost. From the above facts, digital-centric CMOS technology which utilizes the advantages of digital technology must be the right path for future RF technology. Further investment in this technology is necessary for the advancement of RF technology.

Matsuzawa, Akira

403

Using CMOS image sensors to detect photons  

Microsoft Academic Search

A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS

Chenzhi Xu; Xiaobo Tong; Xiang Zhou; Xiaodong Zheng; Yunfei Xu

2010-01-01

404

1\\/f noise in advanced CMOS transistors  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology is dominant in the microelectronics industry for a wide range of applications, including analog, digital, RF, and sensor systems. The advantages of silicon CMOS technology compared to bipolar technology as well as transistors in other semiconductors is well-established. CMOS technology scaling has been a main drive for continuous progress in the silicon based semiconductor industry over

Yael Nemirovsky; Dan Corcos; Igor Brouk; Amikam Nemirovsky; Samir Chaudhry

2011-01-01

405

High speed CMOS technology for ASIC application  

Microsoft Academic Search

In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 m, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD3structure is employed for 1.0 m

H. Ooka; S. Murakami; M. Murayama; K. Yoshida; S. Takao; O. Kudoh

1986-01-01

406

A 300mV 494GOPS\\/W reconfigurable dual-supply 4Way SIMD vector processing accelerator in 45nm CMOS  

Microsoft Academic Search

High-throughput parallel SIMD vector computations are the most performance and power-critical operations in multimedia, graphics and signal processing workloads. An array of SIMD vector processing engines delivers high- throughput short bit-width arithmetic operations on large data sets with orders of magnitude higher energy efficiencies vs. general-purpose cores. A reconfigurable 4-way SIMD engine targeted for on-die acceleration of vector processing in

Himanshu Kaul; Mark A. Anders; Sanu K. Mathew; Steven K. Hsu; Amit Agarwal; Ram K. Krishnamurthy; Shekhar Borkar

2009-01-01

407

Topics on CMOS Image Sensors  

Microsoft Academic Search

Abstract Today there exist several applications where a real visible scene needs to be sampled to electrical signals, e.g., video cameras, digital still cameras, and machine vision systems. Since the 1970s charge-coupled device (CCD) sensors have primarily been used for this task, but during the last decade CMOS image sensors have become,more and more popular. The demand,for image sensors has

Leif Lindgren

2005-01-01

408

Novel integrated CMOS sensor circuits  

Microsoft Academic Search

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge

Stuart Kleinfelder; Fred Bieser; Yandong Chen; Robin Gareus; Howard S. Matis; Markus Oldenburg; Fabrice Retiere; H. G. Ritter; Howard H. Wieman; Eugene Yamamoto

2004-01-01

409

High Resolution CMOS Current Comparators  

Microsoft Academic Search

A 2m CMOS current comparator prototype is presented with an input current comparison range of 140dB and virtual zero offset(?10pA). The circuit uses capacitive sensing for high resolution and nonlinear feedback to achieve small input voltage variations in the complete input current range. Operation speed for low current is abot two orders of magnitude larger than for conventional circuits. Simplified

R. Dominguez-Castro; A. Rodriguez-Vazquez; F. Medeiro; J. L. Huertas

1992-01-01

410

CMOS wavelet compression imager architecture  

Microsoft Academic Search

The CMOS imager architecture implements ??-modulated Haar wavelet image compression on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental over-sampling analog-to-digital converters (ADCs). Each ADC performs column-wise distributed focal-plane sampling and concurrent signed weighted average quantization, realizing a one-dimensional spatial Haar wavelet transform. A digital delay and adder loop

Ashkan Olyaei; R. Genov

2005-01-01

411

Scaling fully depleted SOI CMOS  

Microsoft Academic Search

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (Leff) of FD\\/SOI MOSFETs. The

Vishal P. Trivedi; Jerry G. Fossum

2003-01-01

412

5GHz CMOS wireless LANs  

Microsoft Academic Search

This paper first provides an overview of some recently ratified wireless local-area network (WLAN) standards before describing an illustrative 5-GHz WLAN receiver implementation. The receiver, built in a standard 0.25-?m CMOS logic technology, exploits several recent developments, including lateral-flux capacitors, accumulation-mode varactors, injection-locked frequency dividers, and an image-reject low-noise amplifier. The receiver readily complies with the performance requirements of both

T. H. Lee; H. Samavati; H. R. Rategh

2002-01-01

413

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.  

PubMed

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-08-11

414

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass  

PubMed Central

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

415

An advanced triple level metal CMOS technology for ASIC applications  

Microsoft Academic Search

An advanced triple-level metal CMOS technology (TRIM), which uses a twin-well approach to achieve optimal device performance, is described in detail with emphasis on novel process like borophosphosilicate glass wet\\/dry etch, barrier metal, and boron-doped silica glass. Degradation of device reliability due to the triple-level metal (TLM) is also discussed. A 100 K gate array has been successfully manufactured utilizing

J. Schmiesing; K. Y. Chang; F. Pintchovski; J. Klein; K. Baker; C. S. Meyer; S. Lai; D. Hoang; D. Tang

1988-01-01

416

A submicron CMOS triple level metal technology for ASIC applications  

Microsoft Academic Search

A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps

D. Fisher; K. Y. Chang; F. Pintchovski; J. Klein; K.-Y. Fu; S. Lai; R. Dillard

1989-01-01

417

Thin Photo-Patterned Micropolarizer Array for CMOS Image Sensors  

Microsoft Academic Search

We fabricated and characterized a thin photo-patterned micropolarizer array for complementary metal-oxide-semiconductor (CMOS) image sensors. The proposed micropolarizer fabrication technology completely removes the need for complex selective etching. Instead, it uses the well-controlled process of ultraviolet photolithography to define micropolarizer orientation patterns on a spin-coated azo-dye-1 film. The patterned polymer film micropolarizer (10 mum x 10 mum) exhibits submicron thickness

Xiaojin Zhao; Farid Boussaid; Amine Bermak; Vladimir G. Chigrinov

2009-01-01

418

Noise analysis of a fully integrated CMOS image sensor  

Microsoft Academic Search

The read noise characteristics of a 3T photodiode-based CMOS active pixel image sensor IC is described. The sensor is fabricated in Hewlett Packard's standard 0.5 micrometers and 3.3V mixed-signal process. The read noise characteristic of the analog signal path is theoretically estimated by adding together the noise contributions of the pixel, column amplifier and programmable gain amplifier (PGA). The read

Kalwant Singh

1999-01-01

419

An integrated 800600 CMOS imaging system  

Microsoft Academic Search

Using a 0.5 ?m baseline DRAM process, a single chip digital CMOS imaging system with SVGA pixel array, linear bank of 800 parallel 8 b ADCs, 3.2 kB DRAM buffer, digital double sampling (DDS) circuitry and digital control is presented. A 3.3 V high-performance 4T nMOS, 88 ?m2 pixel with on-chip RGB Bayer pattern color filters has measured green sensitivity

Woodward Yang; Oh-Bong Kwon; Ju-Il Lee; Gyu-Tae Hwang; Suk-Joong Lee

1999-01-01

420

Standard CMOS active pixel image sensors for multimedia applications  

Microsoft Academic Search

The task of image acquisition is completely dominated by CCD-based sensors fabricated on specialized process lines. These devices provide an essentially passive means of detecting photons and moving image data across chip. We argue that line widths in standard CMOS have been reduced to the point where it is practical to locate transistors-and hence provide gain-within each detector of an

Alex G. Dickinson; Bryan D. Ackland; El-sayed Eid; David A. Inglis; Eric R. Fossum

1995-01-01

421

Arsenic ion implant energy effects on CMOS gate oxide hardness.  

SciTech Connect

Under conditions that were predicted as 'safe' by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process.

Dondero, Richard; Headley, Thomas Jeffrey; Young, Ralph Watson; Draper, Bruce Leroy; Shaneyfelt, Marty Ray

2005-07-01

422

A fully integrated CMOS DCS1800 frequency synthesizer  

Microsoft Academic Search

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 ?m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was

Jan Craninckx; Michel S. J. Steyaert

1998-01-01

423

Hardening of commercial CMOS PROMs with polysilicon fusible links  

NASA Astrophysics Data System (ADS)

The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

Newman, W. H.; Rauchfuss, J. E.

1985-12-01

424

Scalable PD\\/SOI CMOS with floating bodies  

Microsoft Academic Search

An insightful analysis of the floating-body (FB) effect on off-state current (Ioff) in PD\\/SOI MOSFETs is done based on simulations calibrated to a published scaled SOI CMOS technology (Chau et al., 1997). In contrast to the conclusion drawn by Chau, the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source\\/drain junction region, in conjunction with

Jerry G. Fossum; Mario M. Pelella; Srinath Krishnan

1998-01-01

425

Challenges of IIIV materials in advanced CMOS logic  

Microsoft Academic Search

The superior transport properties of IIIV materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of IIIV materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<10nm, ND=51019 cm?3, ?c= 6?.m2 and Dit = 41012 eV?1

P. D. Kirsch; R. J. W. Hill; J. Huang; W. Y. Loh; T.-W. Kim; M. H. Wong; B. G. Min; C. Huffman; D. Veksler; C. D. Young; K. W. Ang; I. Ali; R. T. P. Lee; T. Ngai; A. Wang; W.-E. Wang; T. H. Cunningham; Y. T. Chen; P. Y. Hung; E. Bersch; B. Sassman; M. Cruz; S. Trammell; R. Droopad; S. Oktybrysky; J. C. Lee; G. Bersuker; C. Hobbs; R. Jammy

2012-01-01

426

Fabrication of a CMOS compatible pressure sensor for harsh environments  

Microsoft Academic Search

The fabrication and characteristics of CMOS compatible absolute pressure sensors for harsh environments are presented in this paper. The sensor which was fabricated using post-processing surface micromachining consists of 100 circular membranes with a total capacity of 14 pF. PECVD SiC was used due to its good mechanical properties, but since SiC has high resistivity, aluminium layers were used for

L S Pakula; H Yang; H T M Pham; P J French; P M Sarro

2004-01-01

427

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control  

Microsoft Academic Search

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield

Mauro Olivieri; Giuseppe Scotti; Alessandro Trifiletti

2005-01-01

428

Novel fully CMOS-compatible vacuum sensor  

Microsoft Academic Search

We present a new CMOS-compatible pressure sensor operating in the range of 100106 Pa. The sensor is fabricated in standard CMOS technology, followed by simple postprocessing consisting of photolithography and a sacrificial metal etch. No anisotropic etching of silicon is required.

Oliver Paul; Henry Baltes

1995-01-01

429

CMOSMEMS Lateral Electrothermal Actuators  

Microsoft Academic Search

In this paper, a type of lateral electrothermal (ET) actuator fabricated with post-CMOS micromachining is presented. The actuator is a beam with a multimorph structure, composed of CMOS dielectric and metal interconnect. Following structural release, the actuators demonstrate self-assembly under the moments arising from residual stress. Actuation is achieved through the imbalanced thermal expansion of internal interconnect members, whose relative

Peter J. Gilgunn; Jingwei Liu; Niladri Sarkar; Gary K. Fedder

2008-01-01

430

An on-chip USB-powered three-phase up\\/down DC\\/DC converter in a standard 3.3 V CMOS process  

Microsoft Academic Search

Some USB powered applications, like PC cameras, require an accurate and low-ripple 5 V supply for sensitive circuits, such as image sensor and video processing. Therefore an on-chip USB powered DC\\/DC converter with a regulated low-ripple 5 V output is needed for this USB application. As the USB supply voltage can range from 4.0 V to 5.5 V, the required

F. Sluijs; H. Neuteboom; M. Breedveld

2000-01-01

431

Process dependent antenna ratio rules for HSQ and FSG back-ends of (embedded flash) 0.18 ?m CMOS technology  

Microsoft Academic Search

The charging damage induced by the inter-metal dielectric deposition in a hydrogen silsequioxane (HSQ) and in a fluorinated-silica glass (FSG) now are compared in a worst case scenario experiment, carried out in a 0.18 ?m embedded flash process. It is shown that different charging damage mechanisms take place in the two flows, calling for different definitions of antenna ratios and

A. Scarpa; M. Diekema; C. van der Schaar; H. Valk; A. Harke; F. G. Kuper

2002-01-01

432

A new CMOS-based digital imaging detector for applications in mammography  

NASA Astrophysics Data System (ADS)

We have developed a CMOS-based x-ray imaging detector in the same form factor of a standard film cassette (18 cm 24 cm) for Small Field-of-view Digital Mammography (SFDM) applications. This SFDM cassette is based on our three-side buttable, 25 mm 50 mm, 48?m active-pixel CMOS sensor modules and utilizes a 150?m columnar CsI(Tl) scintillator. For imaging up to 100 mm 100 mm field-of-view, a number of CMOS sensor modules need to be tiled and electronically synchronized together. By using fiber-optic communication, acquired images from the SFDM cassette can be transferred, processed and displayed on a review station within approximately 5 seconds of exposure, greatly enhancing patient flow. We present the physical performance of this CMOS-based SFDM cassette, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and more subjective criteria, by evaluating images from a phantom study and the clinical studies of our collaborators. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for digital mammography today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. The SFDM cassette can be employed in various mammography applications, including spot imaging, stereotactic biopsy imaging, core biopsy and surgical biopsy specimen radiography. This study demonstrates that all the image quality requirements for demanding mammography applications can be addressed with CMOS technology.

Baysal, Mehmet A.; Toker, Emre

2005-09-01

433

Maintaining the benefits of CMOS scaling when scaling bogs down  

Microsoft Academic Search

A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it

Edward J. Nowak

2002-01-01

434

CMOS image sensors-recent advances and device scaling considerations  

Microsoft Academic Search

This paper reviews the industry trend and the recent advances in CMOS image sensor technology, covering advances in technology, devices, pixel architecture, as well as on-chip circuit integration. Compatibility with standard CMOS technology is an important consideration for CMOS image sensors. We therefore explore the question: will the image sensing performance of CMOS imagers get better or get worse as

Hon-Sum Philip Wong

1997-01-01

435

Design of high speed camera based on CMOS technology  

Microsoft Academic Search

The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and

Sei-Hun Park; Jun-Sick An; Tae-Seok Oh; Il-Hwan Kim

2007-01-01

436

Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process  

Microsoft Academic Search

A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35 mum SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (HBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths\\/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as

Dong-Shong Liang; Cheng-Chi Tai; Kwang-Jow Gan; Yi-Zhi Lin

2008-01-01

437

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.  

PubMed

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power. PMID:23366924

Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

2012-01-01

438

A high precision CMOS weak current readout circuit  

NASA Astrophysics Data System (ADS)

This paper presents a high precision CMOS weak current readout circuit. This circuit is capable of converting a weak current into a frequency signal for amperometric measurements with high precision and further delivering a 10-bit digital output. A fast stabilization-enhanced potentiostat has been proposed in the design, which is used to maintain a constant bias potential for amperometric biochemical sensors. A technique based on source voltage shifting that reduces the leakage current of the MOS transistor to the reverse diode leakage level at room temperature was employed in the circuit. The chip was fabricated in the 0.35 ?m chartered CMOS process, with a single 3.3 V power supply. The interface circuit maintains a dynamic range of more than 100 dB. Currents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.

Qisong, Wu; Haigang, Yang; Tao, Yin; Chong, Zhang

2009-07-01

439

Forced Chaos Generator with CMOS Variable Active Inductor Circuit  

NASA Astrophysics Data System (ADS)

We propose a forced chaos generator with a CMOS variable active inductor circuit. The equivalent inductance of the variable active inductor in the proposed circuit can be controlled by an external voltage. Therefore, the oscillation frequencies of the circuit can be altered by applying an external periodic square waveform. As a result, we can generate chaos from the circuit. We then confirm the folding-and-stretching mechanism of the chaotic motion in the circuit. Complex phenomena, observed in the proposed circuit, are analyzed through the Poincar sections from the SPICE simulations with TSMC 0.35?m CMOS semiconductor process parameters. In addition, we define a return map on the Poincar section to examine the properties of the observed attractors. Moreover, we investigate the bifurcation phenomena when the amplitude and period of the external signal are changed as bifurcation parameters.

Tsubaki, Yusuke; Sekikawa, Munehisa; Horio, Yosihiko

440

A novel noise optimization technique for inductively degenerated CMOS LNA  

NASA Astrophysics Data System (ADS)

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 ?m CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

Zhiqing, Geng; Haiyong, Wang; Nanjian, Wu

2009-10-01

441

Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays  

PubMed Central

We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 ?m 30 ?m. The devices exhibited sensitivity of 6.2 ?C/Rcm2 with corresponding dark current of ?2.7 nA/cm2, and a 80 ?m FWHM planar image response to a 50 ?m slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 ?m spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 ?m), fast readout speeds (8 fps for a 32003200 pixel array), and future design flexibility due to the use of well-developed fabrication processes.

Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

2009-01-01

442

Cryogenic CMOS circuits for single charge digital readout.  

SciTech Connect

The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

2010-03-01

443

Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays.  

PubMed

We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI(2)) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400x400 pixel HgI(2)-coated CMOS readout chips are presented, where the pixel grid is 30 mum x 30 mum. The devices exhibited sensitivity of 6.2 muC/Rcm(2) with corresponding dark current of approximately 2.7 nA/cm(2), and a 80 mum FWHM planar image response to a 50 mum slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 mum spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 mum), fast readout speeds (8 fps for a 3200x3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

Hartsough, Neal E; Iwanczyk, Jan S; Nygard, Einar; Malakhov, Nail; Barber, William C; Gandhi, Thulasidharan

2009-08-01

444

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers.  

PubMed

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d(33f), d(31) and d(33) of up to 2.9, -1.9 and 6.5 pm V(-1), respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

2010-01-01

445

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

NASA Astrophysics Data System (ADS)

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, -1.9 and 6.5 pm V-1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

Doll, Joseph C.; Petzold, Bryan C.; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L.

2010-02-01

446

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS  

Microsoft Academic Search

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

2004-01-01

447

Non-stationary noise responses of some fully differential on-chip readout circuits suitable for CMOS image sensors  

Microsoft Academic Search

CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1\\/f?-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-?m single polysilicon\\/double metal process,

Y. Degerli; F. Lavernhe; P. Magnan; J. Farre

1999-01-01

448

Circuit solutions on ESD protection design for mixed-voltage I\\/O buffers in nanoscale CMOS  

Microsoft Academic Search

Electrostatic discharge (ESD) protection for mixed-voltage I\\/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gate-oxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I\\/O buffers should meet the gate-oxide reliability constraints

Ming-Dou Ker; Chang-Tzu Wang

2009-01-01

449

Development and evaluation of a high resolution CMOS Image Sensor with 17 ?m 17 ?m pixel size for X-ray imaging  

Microsoft Academic Search

In this research, we designed and fabricated a CIS (CMOS Image Sensor) with 17 ?m 17 ?m pixel size and 190 190 pixels using 0.25 ?m standard CMOS process as a testversion sample for developing high resolution X-ray image sensors. Active pixel sensors, area efficient sample and hold circuits, and a switched capacitor amplifier are integrated in a

Jun Hyung Bae; Jongyul Kim; Dong-uk Kang; Gyuseong Cho

2010-01-01

450

Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors  

Microsoft Academic Search

A scheme for low-voltage CMOS op-amp operation with rail-to-rail input and output signal swing and constant gm is presented. Single-ended and fully differential versions are discussed. The scheme is based on the use of multiple-input floating-gate transistors and allows direct implementation of linear weighted addition of continuous-time signals. Simulations are presented that verify the scheme operating with a 1.2-V single

J. Ramirez-Angulo; R. G. Carvajal; J. Tombs; A. Torralba

2001-01-01

451

Introducing 65 nm CMOS technology in low-noise read-out of semiconductor detectors  

NASA Astrophysics Data System (ADS)

The large scale of integration provided by CMOS processes with minimum feature size in the 100 nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, processes with 130 nm minimum channel length are widely available for Application Specific Integrated Circuits (ASICs) design, nonetheless designers are considering more scaled technologies following the trend of commercial silicon foundries. This work provides an extensive analysis of the noise performance which can be attained by detector front-end circuits in a 65 nm CMOS process. The behavior of the 1/f and white noise terms in this technology node is studied as a function of the device polarity, of the gate length and width and of the bias conditions. A comparison with data from previous CMOS generations is also carried out to evaluate the impact of scaling down to the 65 nm node.

Manghisoni, M.; Gaioni, L.; Ratti, L.; Re, V.; Traversi, G.

2010-12-01

452

Multi-target electrochemical biosensing enabled by integrated CMOS electronics  

NASA Astrophysics Data System (ADS)

An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 M choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements.

Rothe, J.; Lewandowska, M. K.; Heer, F.; Frey, O.; Hierlemann, A.

2011-05-01

453

CMOS integrable micromirrors with highly improved drift-stability  

NASA Astrophysics Data System (ADS)

The large-scale integration of analog operable MEMS micro-mirrors onto active CMOS address circuitry requires high quality planar reflective optical surfaces but also a stable deflection vs. voltage characteristic. However, for implementing a CMOS compatible surface micromachining process, certain obstacles like a restricted thermal budget and a limited selection of suitable materials must be overcome. In this paper, amorphous TiAl is presented as a new actuator material for monolithical MEMS integration onto CMOS circuitry at room temperature. Sputter deposited TiAl has an x-ray amorphous structure and a low stress gradient. The missing long range order and the high melting point help to virtually eliminate stress relaxation effects, i.e. TiAl hinges behave almost perfectly elastic. In a first study, 40 ?m wide piston mirrors have been implemented onto substrates with fixed wired address electrode arrays. The actuators had a 300 nm TiAl core sandwiched between two layers of 25 nm Al. The devices reach a maximum deflection of about 500 nm at a dc voltage of about 23V. The drift-stability of the deflection has been tested at "worst case" conditions close to the deflection limit. During 30 min of continuous deflection near 500 nm a mechanical drift below 25nm has been observed. TiAl offers the perspective for actuators capable of a stable analog operation, which is essential to many applications, such as adaptive optics.

Schmidt, Jan U.; Knobbe, Jens; Gehner, Andreas; Lakner, Hubert

2007-03-01

454

CMOS Alcohol Sensor Employing ZnO Nanowire Sensing Films  

NASA Astrophysics Data System (ADS)

This paper reports on the utilization of zinc oxide nanowires (ZnO NWs) on a silicon on insulator (SOI) CMOS micro-hotplate for use as an alcohol sensor. The device was designed in Cadence and fabricated in a 1.0 ?m SOI CMOS process at XFAB (Germany). The basic resistive gas sensor comprises of a metal micro-heater (made of aluminum) embedded in an ultra-thin membrane. Gold plated aluminum electrodes, formed of the top metal, are used for contacting with the sensing material. This design allows high operating temperatures with low power consumption. The membrane was formed by using deep reactive ion etching. ZnO NWs were grown on SOI CMOS substrates by a simple and low-cost hydrothermal method. A few nanometer of ZnO seed layer was first sputtered on the chips, using a metal mask, and then the chips were dipped in a zinc nitrate hexahydrate and hexamethylenetramine solution at 90 C to grow ZnO NWs. The chemical sensitivity of the on-chip NWs were studied in the presence of ethanol (C2H5OH) vapour (with 10% relative humidity) at two different temperatures: 200 and 250 C (the corresponding power consumptions are only 18 and 22 mW). The concentrations of ethanol vapour were varied from 175-1484 ppm (pers per million) and the maximum response was observed 40% (change in resistance in %) at 786 ppm at 250 C. These preliminary measurements showed that the on-chip deposited ZnO NWs could be a promising material for a CMOS based ethanol sensor.

Santra, S.; Ali, S. Z.; Guha, P. K.; Hiralal, P.; Unalan, H. E.; Dalal, S. H.; Covington, J. A.; Milne, W. I.; Gardner, J. W.; Udrea, F.

2009-05-01

455

New integration concept of PIN photodiodes in 0.35?m CMOS technologies  

NASA Astrophysics Data System (ADS)

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 11012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 41013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100100?m2 photodiodes in 20?m thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at ?=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

Jonak-Auer, I.; Teva, J.; Park, J. M.; Jessenig, S.; Rohrbacher, M.; Wachmann, E.

2012-05-01

456

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

NASA Astrophysics Data System (ADS)

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Davidson, Bradley Darren

457

High-performance Optical Receivers Using Conventional Sub-micron CMOS Technology for Optical Communication Applications  

NASA Astrophysics Data System (ADS)

A novel sub-micron total-CMOS common-gate Transimpedance Amplifier (TIA) has been designed for high-speed optical communication applications. This total-CMOS approach has given a tremendous flexibility in optimizing the circuit for high performance. The new design shows superior performance compared to recent common-gate and common-base TIAs. Using conventional 0.8 m CMOS process parameters, simulations showed a transimpedance gain of 69.0 dB over a 3.5 GHz bandwidth, approaching the technology fT of 10 GHz. The mean input referred noise current density was calculated to be 21.2 pA/Hz0.5 at 3.5 GHz, giving an input optical sensitivity of -20.4 dBm for a BER of 10-9. This allows a data transmission easily at 2.5 Gbps for a NRZ synchronous link. The power consumption is only 44 mW when AC coupled to a 50 ? load. In addition, the TIA was designed to tolerate a relatively wide variation in bias conditions while preserving stability. Moreover, simulations using a 0.6 m CMOS process showed even lower noise and wider bandwidth now at 6.0 GHz. The new design approaches similar IC designs in Si-bipolar or GaAs technologies. The design is the first reported TIA, which combines such features and using conventional 0.8 m CMOS transistors with fT = 10 GHz.

Touati, F.; Douss, S.; Elfadil, N.; Nadir, Z.; Suwailam, M. B.; Loulou, M.

458

CMOS photodiodes for narrow linewidth applications  

Microsoft Academic Search

In recent years CMOS image sensors have gained a major market share for general imaging applications. However, when standard CMOS image sensors are employed in applications that require the detection of light with a very small spectral width, like 3D-time-of-flight imaging or other applications with laser light illumination, problems arise, that are negligible in standard imaging applications with broadband illumination.

Frank Hochschulz; Stefan Dreiner; Holger Vogt; Uwe Paschen

2011-01-01

459

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

460

High Linearity Down-Conversion CMOS Mixers  

Microsoft Academic Search

This paper gives a quantitative analysis of the main mechanisms setting fundamental limits to the linearity performances of CMOS direct down-conversion mixers. An advanced low voltage solution is proposed for 3G cell-phones in a 90 nm CMOS technology that achieves: 3nV\\/radicHz average input referred noise in the band from 10 kHz to 1.92 MHz, a flicker noise corner of 300

Danilo Manstretta

2008-01-01

461

Design and defect tolerance beyond CMOS  

Microsoft Academic Search

ABSTRACT It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advance- ment of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement\\/replacement to CMOS must show,significant gains in at least one of the key met- rics (including speed, power and cost) for at least a

Xiaobo Sharon Hu; Alexander Khitun; Konstantin K. Likharev; Michael T. Niemier; Mingqiang Bao; Kang L Wang

2008-01-01

462

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

463

Total-dose and charge-trapping effects in gate oxides for CMOS LSI devices  

NASA Astrophysics Data System (ADS)

The effect of gamma-irradiation on CMOS devices fabricated using 3 Micron CMOS BULK process has been studied as a function of gate oxide processing and subsequent annealing. Threshold shifts, speed degradation, and power supply currents were measured as a function of total dose up to 10 to the 6th rad (Si). Using hot electron injection techniques, trapping densities and capture cross-sections of the traps in each oxide type have been determined at pre- and post-irradiation levels. Power supply leakage and speed performance of the devices were recovered within three to five hours by annealing them at 125 C, +10 V bias.

Singh, R. S.; Korman, C. S.; Kaputa, D. J.; Surowiec, E. P.

1984-12-01

464

Low-noise design criteria for detector readout systems in deep submicron CMOS technology  

NASA Astrophysics Data System (ADS)

This paper presents a study of the noise behavior of deep submicron CMOS transistors, in view of applications to analog front-end systems for high granularity detectors. The white component of the noise voltage spectrum, which is most important for fast signal processing, and the /1/f noise contribution are investigated to find low-noise design criteria concerning the choice of the polarity and of the channel length of the preamplifier input device in low-power operating conditions. This analysis is supported by experimental data from noise measurements on CMOS devices belonging to a 0.35?m process.

Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.

2002-02-01

465

High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology  

Microsoft Academic Search

The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate

Min Park; Seonghearn Lee; Hyun Kyu Yu; Jin Gun Koo; Kee Soo Nam

1997-01-01

466

A Path Oriented In Time optimization flow for mixed-static-dynamic CMOS logic  

Microsoft Academic Search

The complexity of timing optimization has been increasing rapidly in proportion to the shrinking CMOS device size, due to the increased number of channel-connected transistors in a path, and the rising magnitude of process variations. These significant challenges can be addressed through the implementation of designs with an optimal balance between static and dynamic circuits. This paper presents a process

Kumar Yelamarthi; Chien-In Henry Chen

2008-01-01

467

Design, fabrication and modeling of microbeam structures for gas sensor applications in CMOS technology  

Microsoft Academic Search

In this paper we discuss the design, fabrication, and modeling of an electrostatically actuated transducer that is operated in a resonant mode. The transducer is designed for gas sensor applications. The microstructure with high-aspect ratio laminated beam or bridge suspensions, has been fabricated using a 0.6 ?m three metal, double poly CMOS process. The fabricated chip was post processed by

Ioana Voiculescu; Mona E. Zaghloul; R. Andrew Mcgill

2003-01-01

468

A single-in-differential-out CMOS RF front-end for UWB 69GHz applications  

Microsoft Academic Search

An integrated ultra-wideband CMOS RF front-end for UWB 6-9 GHz application is presented in this paper. A single-in-differential-out gain controllable low noise amplifier and a current-reuse bleeding IQ merged quadrature mixer are integrated as the RF front-end. This ESD protected module is implemented in TSMC 0.13?m RF CMOS process and the post-layout simulation results shows that it achieves a high

Feng Zhou; Wei Li; Ting Gao; Fei Lan; Ning Li; Junyan Ren

2010-01-01

469

A 3.73.7 ?m2 square pixel CMOS image sensor for digital still camera application  

Microsoft Academic Search

Systems such as digital still cameras, robots, etc. require low-cost, low-power and high-resolution. This CMOS image sensor has reduced cell size. The sensor is fabricated using 0.6 ?m, triple-poly-silicon, double-metal CMOS process technology. The sensor has 3.73.7 ?m2 pixels. It operates with one 3.3V power supply and has less than 30mW power dissipation

H. Ihara; H. Yamashita; I. Inoue; T. Yamaguchi; N. Nakamura; H. Nozaki

1998-01-01

470

A 128128 pixel CMOS area image sensor with multiplexed pixel level A\\/D conversion  

Microsoft Academic Search

A 128128 pixel CMOS area image sensor with a sigma-delta A\\/D Converter shared within each group of 22 pixels is described. Each pixel comprises a photodiode and 4 MOSFETs and occupies 20.8 ?m19.8 ?m with a fill factor of 30% in a 0.8 ?m three layer metal one layer poly CMOS process. At 3.3 V, the dynamic range is >83

D. X. D. Yang; B. Fowler; A. El Gamal

1996-01-01

471

A SOI-RF-CMOS technology on high resistivity SIMOX substrates for microwave applications to 5 GHz  

Microsoft Academic Search

A silicon-on-insulator (SOI) RF complementary metal-oxide-semiconductor (CMOS) technology for microwave applications up to 5 GHz has been developed. The technology is based on ultra large scale integration (ULSI) CMOS processing using a high resistivity separation through implanted oxygen (SIMOX) substrate of typically 10 k?cm. Dedicated RF n-channel and RF p-channel MOSFET's with an effective channel length of 0.20 and 0.40

Dietmar Eggert; Peter Huebler; Arnd Huerrich; Heinz Kueck; Wolfram Budde; Matthias Vorwerk

1997-01-01

472

A novel p-i-n photodetector fabricated on SIMOX for 1 GHz 2 V CMOS OEICs  

Microsoft Academic Search

We describe a novel p-i-n photodetector fabricated on separation by implanted oxygen (SIMOX) substrate using a fully-depleted CMOS\\/SIMOX process, which is suitable for CMOS optoelectronic integrated circuits (OEICs). The photodetector\\/SIMOX exhibits a low parasitic capacitance of 0.2 pF, a high responsivity of 0.4 A\\/W at 850 nm, and a high photoresponse for 1 GHz operation at a supply voltage of

Takeshi Yoshida; Yusuke Ohtomo; Masakazu Shimaya

1998-01-01

473

A 12mW wide dynamic range CMOS front-end for a portable GPS receiver  

Microsoft Academic Search

This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-?m (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer

Arvin R. Shahani; Derek K. Shaeffer; Thomas H. Lee

1997-01-01

474

Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs  

Microsoft Academic Search

This paper examines the impact of mutual inductance and parasitic capacitance on the phase-error performance for a class of CMOS quadrature voltage-controlled oscillators (QVCOs). Good agreement is found between theory, post-layout simulations, and measurement results. The QVCOs were implemented in a standard 0.35?m CMOS process. All QVCOs display a center frequency of 2 GHz and a tuning range of 15%.

Xiaoyan Wang; Pietro Andreani

2003-01-01

475

A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector  

Microsoft Academic Search

This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buried-channel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-mum CMOS process. The sensor characterization was carried out successfully, and the results show that, compared with a regular imager with the standard nMOS transistor surface-mode SF, the new

Yue Chen; Xinyang Wang; Adri J. Mierop; Albert J. P. Theuwissen

2009-01-01

476

A 1.9 GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications  

Microsoft Academic Search

A number of recent efforts have concentrated on highly-integrated radio receivers using a low-cost silicon process such as CMOS. This prototype monolithic CMOS receiver combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10 b digital baseband waveform. A wide-band intermediate frequency double conversion (WBIFDC) architecture eliminates the need for external narrow-band

Jacques C. Rudell; Jia-Jiunn Ou; Thomas B. Cho; George Chien; F. Brianti; Jeffrey A. Weldon; Paul R. Gray

1997-01-01

477

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device  

Microsoft Academic Search

SUMMARY A new sub-1-V CMOS bandgap voltage reference with- out using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been success- fully verified in a standard 0.25-m CMOS process, where the occupied silicon area is only 177m 106m. The experimental results have shown that, with the minimum supply voltage of

Ming-dou Ker; Jung-sheng Chen; Ching-yun Chu

2004-01-01

478

A scalable neural chip with synaptic electronics using CMOS integrated memristors  

NASA Astrophysics Data System (ADS)

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metaloxidesemiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

2013-09-01

479

Volumetric imaging using single chip integrated CMUT-on-CMOS IVUS array.  

PubMed

An intravascular ultrasound (IVUS) catheter that can provide forward viewing volumetric ultrasound images would be an invaluable clinical tool for guiding interventions. Single chip integration of front-end electronics with capacitive micromachined ultrasonic transducers (CMUTs) is highly desirable to reduce the interconnection complexity and enable miniaturization in IVUS catheters. For this purpose we use the monolithic CMUT-on-CMOS integration where CMUTs are fabricated directly on top of pre-processed CMOS wafers. This minimizes parasitic capacitances associated with connection lines. We have recently implemented a system design including all the required electronics using 0.35-m CMOS process integrated with a 1.4-mm diameter CMUT array. In this study, we present the experimental volumetric imaging results from an ex-vivo chicken heart phantom. The imaging results demonstrate that the single-chip forward looking IVUS (FL-IVUS) system with monolithically integrated electronics has potential to visualize the front view of coronary arteries. PMID:23366605

Tekes, Coskun; Zahorian, Jaime; Gurun, Gokce; Satir, Sarp; Xu, Toby; Hochman, Michael; Degertekin, F Levent

2012-01-01

480

A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring  

SciTech Connect

A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to a substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles. A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-{micro}m conventional CMOS process with a sense capacitor area of 110 {micro}m{sup 2}. Tests carried out under vacuum conditions using a calibrated {sup 241}Am alpha-particle source showed an output voltage swing of {ge}2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles.

Ahmed, A.; Walkey, D.J.; Tarr, N.G. [Carleton Univ., Ottawa, Ontario (Canada). Dept. of Electronics

1997-06-01

481

A scalable neural chip with synaptic electronics using CMOS integrated memristors.  

PubMed

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. PMID:23999447

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-02

482

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator  

Microsoft Academic Search

The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12GeV\\/c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130nm CMOS Technology, square pixels 50?m

M. Villa; M. Bruschi; R. Di Sipio; L. Fabbri; B. Giacobbe; A. Gabrielli; F. Giorgi; G. Pellegrini; C. Sbarra; N. Semprini; R. Spighi; S. Valentinetti; A. Zoccoli; C. Avanzini; G. Batignani; S. Bettarini; F. Bosi; G. Calderini; M. Ceccanti; R. Cenci; A. Cervelli; F. Crescioli; M. DellOrso; F. Forti; P. Giannetti; M. A. Giorgi; A. Lusiani; S. Gregucci; P. Mammini; G. Marchiori; M. Massa; F. Morsani; N. Neri; E. Paoloni; M. Piendibene; A. Profeti; G. Rizzo; L. Sartori; J. Walsh; E. Yurtsev; M. Manghisoni; V. Re; G. Traversi; C. Andreoli; L. Gaioni; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; G. F. Dalla Betta; G. Soncini; G. Fontana; M. Bomben; L. Bosisio; P. Cristaudo; G. Giacomini; D. Jugovaz; L. Lanceri; I. Rashevskaya; L. Vitale; G. Venier

2010-01-01

483

BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry  

Microsoft Academic Search

A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the

Hiep Van Tran; Pak Kuen Fung; David Barry Scott

1989-01-01

484

Development of fast and high throughput tomography using CMOS image detector at SPring-8  

NASA Astrophysics Data System (ADS)

A fast micro-tomography system and a high throughput micro-tomography system using state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) imaging devices have been developed at SPring-8. Those systems adopt simple projection type tomography using synchrotron radiation X-ray. The fast micro-tomography system achieves a scan time around 2 s with 1000 projections, which is 15 times faster than previously developed system at SPring-8. The CMOS camera for fast tomography has 64 Giga Byte on-board memory, therefore, the obtained images must be transferred to a PC at the appropriate timing. A melting process of snow at room temperature was imaged every 30 s as a demonstration of the system. The high throughput tomography system adopts a scientific CMOS (sCMOS) camera with a low noise and high quantum efficiency. The system achieves a scan time around 5 minutes which is three times faster than before. The images quality of the system has been compared to the existing system with Charge-Coupled Device (CCD) camera. The results have shown the advantage of the new sCMOS camera.

Uesugi, Kentaro; Hoshino, Masato; Takeuchi, Akihisa; Suzuki, Yoshio; Yagi, Naoto

2012-10-01

485

CMOS-Memristor Hybrid Nanoelectronics for AES Encryption.  

National Technical Information Service (NTIS)

Complementary metal oxide-semiconductor (CMOS) compatible nanotechnology was investigated under this effort to advance information technology by leveraging the well-proven vast functionality of the existing industry-standard CMOS integrated circuit manufa...

B. Wysocki J. Van Nostrand N. McDonald T. McEwen

2013-01-01

486

New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications  

NASA Astrophysics Data System (ADS)

Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.

Zhou, Wei; Hart, Darcy

2013-09-01

487

CMOS compatible silicon-based Mach-Zehnder optical modulators with improved extinction ratio  

NASA Astrophysics Data System (ADS)

Improved Extinction Ratio of 25 dB was demonstrated in silicon based optical modulators on CMOS platform in China. The measurement results agree with the simulation, followed by a discussion about the effects of both propagation loss in Mach-Zehnder arms and power ratio at beam splitters and combiners. The analyses indicate that many considerations have to be taken into design and development of the compatible fabrication of these integrated silicon photonics, especially for the improved extinction ratio of optical modulators. In this summary, we propose the integrated optical modulators in SOI by use of the compatible CMOS processes under the modern CMOS foundry in Chinese homeland. And the measured results were shown, the fast response modulator with the data transmission rate of 10 Gbps.

Li, Zhiyong; Zhou, Liang; Hu, Yingtao; Xiao, Xi; Yu, Yude; Yu, Jinzhong

2011-11-01

488

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate  

PubMed Central

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 ?m UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is ?42 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 ?A, and low distortion of less than 1% (referred to 100 dB).

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

489

Compatibility of Submicron Silicon CMOS Circuits with Gallium Arsenide-On Heteroepitaxy.  

NASA Astrophysics Data System (ADS)

Advanced packaging and high density interconnections are emerging technologies as silicon MOS device dimensions scale down to minimum physical limits. Multi-chip Modules and Wafer Scale Integration improve packing density, and provide solutions to board area issues beyond the capabilities of even the most densely packed surface mount technologies. Such technologies could confront increasingly complex interconnection constraints, and might provide opportunities for the insertion of high performance optical interconnections into future microelectronic systems. However, successful integration of optics with microelectronic system technologies requires a careful evaluation of the practical issues confronting monolithic co-integration of GaAs optoelectronics with high performance silicon CMOS technologies. This work presents a systematic evaluation of degradation in the performance and characteristics of submicron silicon CMOS devices, induced by heteroepitaxial growth of gallium arsenide. An aggressive yet stable, commercial 0.9 mu m AT&T Twin-Tub V silicon CMOS fabrication process is used to study the compatibility issues.

Nariman, Hormuzdiar E.

1994-01-01

490

RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications  

NASA Astrophysics Data System (ADS)

New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS Receiver-on-a-Chip is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 ?m RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

Jackson, Suzy A.

2004-06-01

491

A nano-metallic-particles-based CMOS image sensor for DNA detection  

NASA Astrophysics Data System (ADS)

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano-metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 ?m CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

He, Jin; Su, Yan-Mei; Ma, Yu-Tao; Chen, Qin; Wang, Ruo-Nan; Ye, Yun; Ma, Yong; Liang, Hai-Lang

2012-07-01

492

A 1\\/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders  

Microsoft Academic Search

A 1\\/2.7 inch 1944times1092pixels CMOS image sensor with multi-gain column amplifier and double noise canceller is fabricated in a 0.18mum 1P3M CMOS process. It operates at 48MHz in a progressive scanning mode at 60fps. A 2T\\/pixel architecture and low optical stack with micro innerlens achieve 14.8ke-\\/1x-s sensitivity, 14ke- saturation, 3.7e- rms noise and 12.2e- dark current at 60degC.

H. Takahashi; T. Noda; T. Matsuda; T. Watanabe; M. Shinohara; T. Endo; S. Takimoto; R. Mishima; S. Nishimura; K. Sakurai; H. Yuzurihara; S. Inoue

2007-01-01

493

Second Generation Monolithic Full-depletion Radiation Sensor with Integrated CMOS Circuitry  

SciTech Connect

A second-generation monolithic silicon radiation sensor has been built and characterized. This pixel detector has CMOS circuitry fabricated directly in the high-resistivity floatzone substrate. The bulk is fully depleted from bias applied to the backside diode. Within the array, PMOS pixel circuitry forms the first stage amplifiers. Full CMOS circuitry implementing further amplification as well as column and row logic is located in the periphery of the pixel array. This allows a sparse-field readout scheme where only pixels with signals above a certain threshold are readout. We describe the fabrication process, circuit design, system performance, and results of gamma-ray radiation tests.

Segal, J.D.; Kenney, C.J.; /SLAC; Parker, S.I.; /Hawaii U.; Aw, C.H.; /UOB Ventiure Management, Singapore; Snoeys, W.J.; /CERN; Wooley, B.; Plummer, J.D.; /Stanford U., Elect. Eng. Dept.

2011-05-20

494

Enhanced total ionizing dose tolerance of bulk CMOS transistors fabricated for ultra-low power applications  

SciTech Connect

The first radiation tests of transistors fabricated in a commercial bulk CMOS process designed for ultra-low power applications in space are presented and analyzed. The predominant failure mode of bulk CMOS, i.e., radiation-induced parasitic leakage currents in n-channel transistors, is greatly suppressed by the use of low threshold voltage devices and by the application of backbias used to optimize their performance. With 2 volts of backbias applied, the transistors tested here show no degradation up to a dose of 200 krad(Si).

Xapsos, M.A.; Summers, G.P.; Jackson, E.M.

1999-12-01

495

A novel 3D stacking method for Opto-electronic dies on CMOS ICs.  

PubMed

A high speed, high density and potentially low cost solution for realizing a compact transceiver module is presented in this paper. It is based on directly bonding an Opto-electronic die on top of