Sample records for n-well cmos process

  1. The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

    NASA Astrophysics Data System (ADS)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

    2013-12-01

    This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 ?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 33 and 88 matrices, are presented.

  2. CMOS BASELINE PROCESS UC BERKELEY MICROFABRICATION LABORATORY

    E-print Network

    Healy, Kevin Edward

    Flow and Device Cross Sections 2.2 Mask Definitions 3 Process Simulationand Material Characterization, double poly and double metal CMOS processes and while these are.running we embarked upon developing a 1

  3. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  4. Micromachined thermal radiation emitter from a commercial CMOS process

    Microsoft Academic Search

    M. Parameswaran; Alexander M. Robinson; David L. Blackburn; Michael Gaitan; Jon Geist

    1991-01-01

    Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch

  5. Efficient premature edge breakdown prevention in SiAPD fabrication using the standard CMOS process

    NASA Astrophysics Data System (ADS)

    Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

    2013-04-01

    The effects of premature edge breakdown (PEB) and available PEB prevention (PEBP) techniques in silicon avalanche photodiode fabrication using the standard complementary metal-oxide-semiconductor (CMOS) process are scrutinized in this paper. Impact of device simulation and its induced impacts on fabrication are addressed based on our design, simulation and fabrication experiences. Three most common PEBP techniques are implemented followed by a systematic study aimed at miniaturization, while optimizing the overall performance. The p-well-, p-sub- and n-well-based PEBP techniques are evaluated and compared based on simulation and fabrication results using the standard CMOS process. The results demonstrate that the n-well guard ring offers the most efficient PEBP technique. This technique offers a high-gain (800), low-noise dark current rate (DCR = 40 Hz), high detection efficiency (70%) avalanche photodiode with a higher functionality probability.

  6. Process Compensated CMOS Temperature Sensor for Microprocessor Application

    E-print Network

    Ayazi, Farrokh

    Process Compensated CMOS Temperature Sensor for Microprocessor Application Yaesuk Jeong and Farrokh consumption is 478uW. I. INTRODUCTION With microprocessors scaling to higher performance and faster speed in the microprocessor to monitor its thermal distribution. Many CMOS based temperature sensors have been reported

  7. Process flow innovations for photonic device integration in CMOS

    NASA Astrophysics Data System (ADS)

    Beals, Mark; Michel, J.; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Kimerling, L. C.; Pomerene, A.; Carothers, D.; Beattie, J.; Kopa, A.; Apsel, A.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.

    2008-02-01

    Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.

  8. Computation-Efficient Image Signal Processing for CMOS Image Sensors

    Microsoft Academic Search

    Ki-Seok Kwon; Eun-Joo Bae; Seokho Lee; Jinook Song; In-Cheol Park

    This paper presents an efficient image signal processing method proposed for CMOS image sensors. In the proposed method, the color correction is moved to the front of the color demosaic to reduce the arithmetic complexity required in the color correction to one third, and a new color correction method is suggested to achieve good images with less data. In spite

  9. Process control for 45 nm CMOS logic gate patterning

    NASA Astrophysics Data System (ADS)

    Le Gratiet, Bertrand; Gouraud, Pascal; Aparicio, Enrique; Babaud, Laurene; Dabertrand, Karen; Touchet, Mathieu; Kremer, Stephanie; Chaton, Catherine; Foussadier, Franck; Sundermann, Frank; Massin, Jean; Chapon, Jean-Damien; Gatefait, Maxime; Minghetti, Blandine; de-Caunes, Jean; Boutin, Daniel

    2008-03-01

    This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

  10. Laminated high-aspect-ratio microstructures in a conventional CMOS process

    Microsoft Academic Search

    G. K. Fedder; S. Santhanam; M. L. Reed; S. C. Eagle; D. F. Guillou; M. S.-C. Lu; L. R. Carley

    1996-01-01

    Electrostatically actuated microstructures with high-aspect-ratio laminated-beam suspensions have been fabricated using a 0.8 ?m three-metal CMOS process followed by a sequence of three maskless dry-etching steps. Laminated structures are etched of the CMOS silicon oxide, silicon nitride, and aluminum layers. The key to the process is the use of the CMOS metallization as an etch-resistant mask to define the microstructures.

  11. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    NASA Astrophysics Data System (ADS)

    Cheng, Chao-Lin; Tsai, Ming-Han; Fang, Weileun

    2015-02-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35??m 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

  12. Development of a radiation-hard CMOS process

    NASA Technical Reports Server (NTRS)

    Power, W. L.

    1983-01-01

    It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

  13. Post assembly process development for Monolithic OptoPill integration on silicon CMOS

    E-print Network

    Lei, Yi-Shu Vivian, 1979-

    2004-01-01

    Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that ...

  14. CMOS active pixel image sensors for highly integrated imaging systems

    Microsoft Academic Search

    Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

    1997-01-01

    A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

  15. RF characterization of deep-submicron DRAM-embedded CMOS process

    Microsoft Academic Search

    Seong-Ho Park; Gwang-Hyun Lim; Yong-Hee Lee

    1999-01-01

    In this paper rf characteristics of a 0.25 ?m DRAM embedded CMOS process, focused on the n-MOSFET and the spiral inductor of the critical devices in rf CMOS circuit design, have been investigated. An extremely high cutoff frequency of 44 GHz, high maximum operating frequency of 29 GHz, and a de-embedded minimum noise figure of 1.0 dB have been obtained

  16. Integration of solid-state nanopores in a 0.5 ?m cmos foundry process

    PubMed Central

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-01-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductors 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  17. Low voltage CMOS transconductors using the series composite transistor

    Microsoft Academic Search

    Young-Gyu Yu; Geun-Ho Lee; Chang-Hun Yun; Seok-Woo Choi; Hong-Kyu Shin

    2000-01-01

    In this paper, low voltage CMOS transconductors using the series composite transistors are presented. The minimum input voltage of the designed circuits is VTn, which is suitable for low supply voltage. The designed circuits have been simulated by HSPICE using 0.25 ?m n-well CMOS process. Simulation results show that THD is less than 1.2% for the differential input signal of

  18. Wide intrascene dynamic range CMOS APS using dual sampling

    Microsoft Academic Search

    Orly Yadid-Pecht; Eric R. Fossum

    1997-01-01

    A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 6464 element prototype sensor with dual output architecture was fabricated using a 1.2 ?m n-well CMOS process with 20.4 ?m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding

  19. Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

    Microsoft Academic Search

    Malgorzata Jurczak; Thomas Skotnicki; M. Paoli; B. Tormen; J. Martins; Jorge Luis Regolini; Didier Dutartre; Pascal Ribot; D. Lenoble; Roland Pantel; Stephanie Monfray

    2000-01-01

    A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally

  20. A 3-D optoelectronic integration methodology utilizing CMOS post-backend process

    NASA Astrophysics Data System (ADS)

    Zhang, Zan; Huang, Beiju; Zhang, Zanyun; Cheng, Chuantong; Mao, Xurui; Chen, Hongda

    2014-10-01

    The integration of optical devices and electronic integrated circuits (IC) is a main issue for optoelectronic convergence. In this work, a CMOS post-backend process flow is proposed to potentially achieve a 3-D monolithic optoelectronic integrated chip. The proposed integrated chip is composed of an IC die as electronic layer and a waveguide device layer as photonic layer above electronic layer. The photonic layer is fabricated by CMOS post-backend process with a temperature blow 450 C, which would do no harm to the performance of the CMOS ICs. We also fabricated Si3N4 mircoring add-drop filters on a bulk Si wafer. The cross-section of the waveguide is 400 nm 1 ?m, and the radius of microring is 30?m. Measured results match well with numerical simulations.

  1. Elevated source\\/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity

    Microsoft Academic Search

    Emmanuel Augendre; Rita Rooyackers; Matty Caymax; E. P. Vandamme; An De Keersgieter; Carles Perell; Marc Van Dievel; Sandrine Pochet; Gonal Badenes

    2000-01-01

    The continuous downscaling of CMOS devices aims at cost reduction and performance improvement. Process development constantly faces new constraints and integrates breakthroughs to overcome them. In deep submicron CMOS generations, scalability is in part limited by conflicting needs for shallow silicided junctions and low junction leakage. Both requirements can be met using elevated source\\/drain (ES\\/D) architecture. Although this solution has

  2. An embedded ultra low power nonvolatile memory in a standard CMOS logic process

    Microsoft Academic Search

    Y.-L. Li; P. Feng; N.-J. Wu

    2008-01-01

    This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area\\/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce

  3. Reliability aspects of a radiation detector fabricated by post-processing a standard CMOS chip

    Microsoft Academic Search

    Cora Salm; Victor M. Blanco Carballo; Joost Melai; Jurriaan Schmitz

    2008-01-01

    This paper describes various reliability concerns of the newly developed INGRID detector. This radiation detector is fabricated by waferscale CMOS post-processing; fresh detectors show excellent performance. Since the microsystems will be used unpackaged they are susceptible to all kinds of environmental con- ditions. The device passed tests of micro-ESD, radiation hardness, dielectric strength; but humidity tests show one weakness of

  4. High-Activation Laser Anneal Process for the 45nm CMOS Technology Platform

    Microsoft Academic Search

    M. Bidaud; H. Bono; C. Chaton; B. Dumont; V. Huard; P. Morin; L. Proencamota; R. Ranica; G. Ribes

    2007-01-01

    This paper presents the integration of a sub-melt laser annealing technique in a 45 nm CMOS technology platform. To enhance the activation of transistors gates and source\\/drain junctions, ms anneal as dynamic surface anneal (DSA) is added to conventional low temperature spike process. The aim of this new integration scheme is to significantly increase the solubility limit of the dopants

  5. Capacitive micro pressure sensors with underneath readout circuit using a standard CMOS process

    Microsoft Academic Search

    2003-01-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35?m complementary metal oxide semiconductor (CMOS) process and post?processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post?processing included anisotropic dry etching and wet etching to remove the

  6. Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO

    Microsoft Academic Search

    Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos

    2009-01-01

    In this paper, we present the design of a P4 (Power-Performance- Process-Parasitic) aware voltage controlled oscillator ( VCO) at nano- CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (cen- ter frequency) of the VCO. For process variation analysis, we pro- pose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which

  7. Gamma radiation damage study of 0.18 m process CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Dryer, Ben; Holland, Andrew; Murray, N. J.; Jerram, Paul; Robbins, Mark; Burt, David

    2010-07-01

    A 0.18 ?m process CMOS image sensor has recently been developed by e2v technologies plc. with a 0.5 megapixel imaging area consisting of 6 6 ?m 5T pixels. The sensor is able to provide high performance in a diverse range of applications including machine vision and medical imaging, offering good low-light performance at a video rate of up to 60 fps. The CMOS sensor has desirable characteristics which make it appealing for a number of space applications. Following on from previous tests of the radiation hardness of the image sensors to proton radiation, in which the increase in dark-current and appearance of bright and RTS pixels was quantified, the sensors have now been subjected to a dose of gamma radiation. Knowledge of the performance after irradiation is important to judge suitability for space applications and radiation sensitive medical imaging applications. This knowledge will also enable image correction to mitigate the effects and allow for future CMOS devices to be designed to improve upon the findings in this paper. One device was irradiated to destruction after 120 krad(Si) while biased, and four other devices were irradiated between 5 and 20 krad(Si) while biased. This paper explores the resulting radiation damage effects on the CMOS image sensor such as increased dark current, and a central brightening effect, and discusses the implications for use of the sensor in space applications.

  8. Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing

    Microsoft Academic Search

    John S. Suehle; Richard E. Cavicchi; Michael Gaitan; Steve Semancik

    1993-01-01

    A monolithic tin oxide (SnO2) gas sensor realized by commercial CMOS foundry fabrication (MOSIS) and postfabrication processing techniques is reported. The device is composed of a sensing film that is sputter-deposited on a silicon micromachined hotplate. The fabrication technique requires no masking and utilizes in situ process control and monitoring of film resistivity during film growth. Microhotplate temperature is controlled

  9. A discrete-time Bluetooth receiver in a 0.13?m digital CMOS process

    Microsoft Academic Search

    K. Muhammad; D. Leipold; B. Staszewski; Y.-C. Ho; C. M. Hung; K. Maggio; C. Fernando; T. Jung; J. Wallberg; J.-S. Koh; S. John; I. Deng; O. Moreira; R. Staszewski; R. Katz; O. Friedman

    2004-01-01

    A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13?m digital CMOS process.

  10. A novel integrated ultraviolet photodetector based on standard CMOS process

    NASA Astrophysics Data System (ADS)

    Wang, Han; Jin, Xiang-Liang; Chen, Chang-Ping; Tian, Man-Fang; Zhu, Ke-Han

    2015-03-01

    A novel integrated ultraviolet (UV) photodetector has been proposed, which realizes a high UV selectivity by combining a conventional UV-selective photodiode with an extra infrared (IR) photodiode. The IR photodiode is designed for compensating the photocurrent response of the UV photodiode in the infrared band and is 15 times smaller than the UV one. The integrated photodetector has been fabricated in a 0.35 ?m standard CMOS technology. Some critical performance indices of this new structure photodetector, such as spectral responsivity, breakdown voltage, quenching waveform, and transient response, are measured and analyzed. Test results show that the complementary UVIR photodetector has a maximum spectral responsivity of 0.27 AW?1 at the wavelength of 400 nm. The device has a high UV selectivity of 3000, which is much higher than that of the single UV photodiode. Project supported by the National Natural Science Foundation of China (Grant No.61274043), the Key Project of the Ministry of Education of China (Grant No.212125), and the State Key Program of the National Natural Science Foundation of China (Grant No.61233010).

  11. 270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

    2011-11-01

    TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

  12. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    PubMed Central

    Lpez-Huerta, Francisco; Herrera-May, Agustn L.; Estrada-Lpez, Johan J.; Zuiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 ?m CMOS standard process and it has 12 pMEA through a 4 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  13. Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

    PubMed

    Lpez-Huerta, Francisco; Herrera-May, Agustn L; Estrada-Lpez, Johan J; Zuiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 ?m CMOS standard process and it has 12 pMEA through a 4 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  14. A 464 pixel CMOS image sensor for 3D measurement applications

    Microsoft Academic Search

    O. M. Schrey; O. Elkhalili; P. Mengel; M. Petermann; W. Brockherde; B. J. Hosticka

    2003-01-01

    A 464 pixel CMOS image sensor which can capture three-dimensional images has been integrated in a 0.5?m n-well standard CMOS processes. It is based on time-of-flight method and employs an active laser pulse illumination at 900nm optical wavelength. System bandwidth is limited by the refreshing time of the active laser source. The sensor employs the so-called \\

  15. Accurate statistical process variation analysis for 0.25-?m CMOS with advanced TCAD methodology

    Microsoft Academic Search

    Hisako Sato; Hisaaki Kunitomo; Katsumi Tsuneno; Kazutaka Mori; Hiroo Masuda

    1998-01-01

    Effects of statistical process variation on the 0.25-?m CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSF's (response surface functions) for threshold voltage (Vth) and saturation drain current

  16. On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations

    Microsoft Academic Search

    C. H. Kim; K. Roy; S. Hsu; R. K. Krishnamurthy; S. Borkar

    2004-01-01

    This paper describes an on-die leakage current sensor in 1.2V, 90nm CMOS technology for accurately measuring process variation. Results based on measured leakage data show (i) higher signal-to-noise ratio and (ii) reduced sensitivity to supply and P\\/N skew variations compared to prior designs, while the proposed sensor only requires a single bias generator even for multi-bit resolution sensing. A 6-channel

  17. High density radiation hardened FeRAMs on a 130 nm CMOS\\/FRAM process

    Microsoft Academic Search

    David A. Kamp; Alan D. DeVilbiss; Gerald R. Haag; Kirk E. Russell; Gary F. Derbenwick

    2005-01-01

    Using hardened-by-design techniques previously demonstrated on a 1-kbit prototype 0.35-micron ferroelectric semiconductor memory, an 8-kbit FeRAM memory segment has been designed for fabrication on a Texas Instruments 130nm commercial CMOS\\/FRAM process. The 8-kbit segment can be arrayed to provide radiation hardened ferroelectric memory densities up to 64 Mbit with reasonable chip sizes and radiation hardness vastly superior to that of

  18. Lithography with infrared illumination alignment for advanced BiCMOS backside processing

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Schulz, K.; Behrendt, U.; Wietstruck, M.; Kaynak, M.; Marschmeyer, S.; Tillack, B.

    2014-10-01

    Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP's 0.25/0.13 ?m high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVGNT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 ?m across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP's 0.25/0.13 ?m SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

  19. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system. PMID:25836869

  20. High-speed bipolar phototransistors in a 180nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Zimmermann, H.

    2013-01-01

    Several high-speed pnp phototransistors built in a standard 180nm CMOS process are presented. The phototransistors were implemented in sizes of 4040?m2 and 100100?m2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p? epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850nm. Bandwidths up to 92MHz and dynamic responsivities up to 2.95A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc. PMID:23847388

  1. High-speed bipolar phototransistors in a 180nm CMOS process.

    PubMed

    Kostov, P; Gaberl, W; Zimmermann, H

    2013-03-01

    Several high-speed pnp phototransistors built in a standard 180nm CMOS process are presented. The phototransistors were implemented in sizes of 4040?m(2) and 100100?m(2). Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p(+) wafer with a p(-) epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850nm. Bandwidths up to 92MHz and dynamic responsivities up to 2.95A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc. PMID:23847388

  2. InGaAs MOSFETs for CMOS: Recent Advances in Process Technology J. A. del Alamo1

    E-print Network

    del Alamo, Jess A.

    InGaAs MOSFETs for CMOS: Recent Advances in Process Technology J. A. del Alamo1 , D. Antoniadis1 as the most attractive non-Si n-channel material for future nano-scale CMOS. InGaAs n-channel MOSFETs promise technology of InGaAs MOSFETs. It also outlines some of the challenges that need to be overcome before

  3. Photo-Spectrometer Realized In A Standard Cmos Ic Process

    DOEpatents

    Simpson, Michael L. (Knoxville, TN); Ericson, M. Nance (Knoxville, TN); Dress, William B. (Knoxville, TN); Jellison, Gerald E. (Oak Ridge, TN); Sitter, Jr., David N. (Tucson, AZ); Wintenberg, Alan L. (Knoxville, TN)

    1999-10-12

    A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

  4. Modular high-performance 2-?m CCD-BiCMOS process technology for application-specific image sensors and image sensor systems on a chip

    NASA Astrophysics Data System (ADS)

    Guidash, R. Michael; Lee, P. P. K.; Andrus, J. M.; Ciccarelli, Antonio S.; Erhardt, H. J.; Fischer, J. R.; Meisenzahl, Eric J.; Philbrick, Robert H.; Kenney, Timothy J.

    1995-04-01

    A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.

  5. A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration

    PubMed Central

    Chen, Chun-Chi; Lin, Yi

    2014-01-01

    This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-?m 2P4M CMOS process, and a robust resolution of 0.05 C and dissipation of 25 ?W were achieved at a sample rate of 10 samples/s. An inaccuracy of ?0.35 C to 1.35 C was achieved after one-point calibration at temperatures ranging from ?40 C to 120 C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

  6. Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study

    E-print Network

    Mohanty, Saraju P.

    Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study Dhruva Ghai of IEEE Abstract-- This paper proposes a novel flow for parasitic and process-variation aware design simulations have been carried out on the parasitic extracted netlist of the VCO to study the effect of process

  7. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1980-01-01

    The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

  8. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  9. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    PubMed

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 ?m CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/?Newton. The overall power dissipation is 132.8 ?W. PMID:25314707

  10. Modeling and Manufacturing of a Micromachined Magnetic Sensor Using the CMOS Process without Any Post-Process

    PubMed Central

    Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

    2014-01-01

    The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA. PMID:24732100

  11. A high performance CMOS readout integrated circuit for IRFPA

    Microsoft Academic Search

    Xiaojuan Xia; Liang Xie; Weifeng Sun

    2008-01-01

    A high performance, 128128 pixel, snapshot Readout Integrated Circuit (ROIC) for IRFPA has been fabricated with 0.5mum Double Poly Double Metal (DPDM) n-well CMOS process. The pixel cell circuit uses an improved direct injection structure with only four transistors to maintain large enough integration capacitror. One pixel cell occupies an area of 5050mum2. Each row's pixel signals are readout to

  12. An On-Die CMOS Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations

    E-print Network

    Kim, Chris H.

    An On-Die CMOS Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations Chris, Hillsboro, OR 97124, USA ram.krishnamurthy@intel.com Abstract This paper describes an on-die leakage current generator even for multi-bit resolution sensing. A 6-channel leakage current monitor testchip fabricated

  13. Abstract--The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to

    E-print Network

    Calhoun, Benton H.

    Abstract-- The energy efficiency of a CMOS architecture processing dynamic workloads directly efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS densities, and "green" computing initiatives have prioritized energy efficiency as a first class system

  14. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    PubMed

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  15. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    PubMed Central

    He, Diwei; Nguyen, Hoang C.; Hayes-Gill, Barrie R.; Zhu, Yiqun; Crowe, John A.; Gill, Cally; Clough, Geraldine F.; Morgan, Stephen P.

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  16. A discrete time quad-band GSM\\/GPRS receiver in a 90nm digital CMOS process

    Microsoft Academic Search

    K. Muhammad; Y. C. Ho; T. Mayhugh; C. M. Hung; T. Jung; I. Elahi; C. Lin; I. Deng; C. Fernando; J. Wallberg; S. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; M. C. Lee; R. B. Staszewski; K. Maggio

    2005-01-01

    We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing

  17. Process techniques of charge transfer time reduction for high speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Zhongxiang, Cao; Quanliang, Li; Ye, Han; Qi, Qin; Peng, Feng; Liyuan, Liu; Nanjian, Wu

    2014-11-01

    This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 64 pixels was designed and implemented in the 0.18 ?m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 ?s is achieved and 31% of image lag was reduced by using the proposed process techniques.

  18. A simulation study on the impact of lithographic process variations on CMOS device performance

    NASA Astrophysics Data System (ADS)

    Fhner, Tim; Kampen, Christian; Kodrasi, Ina; Burenkov, Alexander; Erdmann, Andreas

    2008-03-01

    In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device. Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask nearfield. TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator (UTB FD-SOI) nMOSFET, with a physical gate length of 32 nm. Electrical parameters such as on- and off- current, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed and extracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyed and illustrated. Moreover, we present an adjusted lithography process window defined by the electrical behavior of the device. In addition to a discussion of the obtained results, this paper also focuses on the software design aspects of interfacing a lithography simulation environment with a device simulator. The steps involved in extracting parameters and transferring them from one program to the other are explained, and further automation capabilities are suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/device process optimization procedure.

  19. Monolithic electronic-photonic integration in state-of-the-art CMOS processes

    E-print Network

    Orcutt, Jason S. (Jason Scott)

    2012-01-01

    As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

  20. A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

    NASA Astrophysics Data System (ADS)

    Haijun, Gao; Lingling, Sun; Xiaofei, Kuang; Liheng, Lou

    2012-07-01

    A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two-dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is -120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is -169 dBc/Hz.

  1. The First Fully Integrated Quad-Band GSM\\/GPRS Receiver in a 90-nm Digital CMOS Process

    Microsoft Academic Search

    Khurram Muhammad; Yo-Chuol Ho; Terry L. Mayhugh; Chih-Ming Hung; T. Jung; Imtinan Elahi; Charles Lin; Irene Deng; C. Fernando; J. L. Wallberg; S. K. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; Meng-Chang Lee; Roman Staszewski; K. Maggio

    2006-01-01

    We present the receiver in the first single-chip GSM\\/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive

  2. 7GHz and 25.8GHz LC VCO Using 0.18 m Mixed Signal CMOS Process

    Microsoft Academic Search

    Youngho Jung; Hee Sauk Jhon; Jong Duk Lee; Byung-Gook Park; Hyungcheol Shin

    This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) in 0.18 m mixed signal CMOS process for operating at 7 GHz and 25.8 GHz. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect of image current of resistive Si substrate. Fabricated VCO operated

  3. A prototype 64-electrode stimulator in 65 nm CMOS process towards a high density epi-retinal prosthesis

    Microsoft Academic Search

    N. Tran; E. Skafidas; J. Yang; S. Bai; M. Fu; D. Ng; M. Halpern; I. Mareels

    2011-01-01

    This paper presents a highly flexible 64-electrode stimulator using 65 nm CMOS process fabricated as a stage towards a 1024-electrode epi-retinal prosthesis, which aims to restore partial vision in patients suffering from eye diseases such as retinitis pigmentosa (RP) and age-related macular degradation (AMD). The stimulator drives 64 electrodes with many flexible features, which are necessary before making a complete

  4. New Ti-SALICIDE process using Sb and Ge preamorphization for sub-0.2 ?m CMOS technology

    Microsoft Academic Search

    Qiuxia Xu; Chenning Hu

    1998-01-01

    A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n+ poly-Si lines and n+ diffusion layers using preamorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2-?m CMOS devices and beyond. Preamorphization enhances the phase transformation from C49TixSi x to C54TiSi2 and lowers the transformation temperature by 80C so

  5. Phase edge lithography for sub 0.1 ?m electrical channel length in a 200 mm full CMOS process

    Microsoft Academic Search

    P. Agnello; T. Newman; E. Crabbe; S. Subbanna; E. Ganin; L. Liebmann; J. Comfort; D. Sunderland

    1995-01-01

    In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 ?m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore

  6. Timing design and image processing of CMOS sensor LUPA-4000 based on FPGA

    NASA Astrophysics Data System (ADS)

    Xin, Li

    2014-11-01

    This article describes a method of the timing sequence design for CMOS image sensor LUPA-4000. A FPGA based imaging system with the function of adjustable integration time, multiple-slope integration, parallel integration an reading, windowing readout has been designed. This design can satisfy the frequency of 66M limit frequency of LUPA-4000 and 20 frames of a second. As the fixed noise of LUPA-4000 is aloud and the image is not clear, an efficient real-time image processing algorithm is also described in this paper. First a black image should be acquired as the fixed noise image. The real-time images can be send out after subtracting the noise image. This method can effectively eliminate the fixed noise o f the image, as the same time, the original image information has been maintained in the maximum degree. The test experiments on FPGA shows this design can drive LUPA-4000 working properly. Also this design takes full advantage of the accessibility features of the device, which provides a wider dynamic range and more flexible application of the device. The image sensor driven by this design improves imaging quality, which can be used for space exploration, especially for small space dynamic target tracking.

  7. A CMOS image sensor with programmable pixel-level analog processing.

    PubMed

    Massari, Nicola; Gottardi, Massimo; Gonzo, Lorenzo; Stoppa, David; Simoni, Andrea

    2005-11-01

    A prototype of a 34 x 34 pixel image sensor, implementing real-time analog image processing, is presented. Edge detection, motion detection, image amplification, and dynamic-range boosting are executed at pixel level by means of a highly interconnected pixel architecture based on the absolute value of the difference among neighbor pixels. The analog operations are performed over a kernel of 3 x 3 pixels. The square pixel, consisting of 30 transistors, has a pitch of 35 microm with a fill-factor of 20%. The chip was fabricated in a 0.35 microm CMOS technology, and its power consumption is 6 mW with 3.3 V power supply. The device was fully characterized and achieves a dynamic range of 50 dB with a light power density of 150 nW/mm2 and a frame rate of 30 frame/s. The measured fixed pattern noise corresponds to 1.1% of the saturation level. The sensor's dynamic range can be extended up to 96 dB using the double-sampling technique. PMID:16342506

  8. Designing a ring-VCO for RFID transponders in 0.18 ?m CMOS process.

    PubMed

    Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

    2014-01-01

    In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 ?m process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. PMID:24587731

  9. PNP PIN bipolar phototransistors for high-speed applications built in a 180nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Hofbauer, M.; Zimmermann, H.

    2012-01-01

    This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high ?3dB bandwidth at low collectoremitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40נ40?m2 and 100נ100?m2. Optical DC and AC measurements at 410nm, 675nm and 850nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9MHz and dynamic responsivities up to 2.89A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done. PMID:23482349

  10. Designing a Ring-VCO for RFID Transponders in 0.18??m CMOS Process

    PubMed Central

    Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

    2014-01-01

    In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42?GHz operated active RFID transponders compatible with IEEE 802.11?b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18??m process is adopted for designing the circuit with 1.5?V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.52.54?GHz and dissipates 2.47?mW of power. It exhibits a phase noise of ?126.62?dBc/Hz at 25?MHz offset from 2.42?GHz carrier frequency. PMID:24587731

  11. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    NASA Technical Reports Server (NTRS)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  12. High-speed short-wavelength silicon photodetectors fabricated in 130-nm CMOS process

    NASA Astrophysics Data System (ADS)

    Csutak, Sebastian M.; Schaub, Jeremy D.; Yang, Bo; Campbell, Joe C.

    2003-06-01

    We have integrated several optoelectronic devices into deep-submicron silicon fabrication process. The main results for monolithic integration of silicon planar interdigitated P-I-N photodiodes with transimpedance amplifiers and waveguide grating couplers will be reviewed. The integration process was carried out in an unmodified 130nm CMOS process flow, on SOI substrates. Photodetectors that were fabricated on 200nm-thick SOI exhibited a 3dB electrical bandwidth of 10GHz for -5V bias while the photodetectors fabricated on 2000nm-thick SOI had 8GHz 3dB electrical bandwidth for -28V bias. The external quantum efficiency of the 2000nm-thick photodetectors at 835nm was 14%. The 200nm-thick photodetectors were integrated with waveguide grating couplers. For 835nm, the external quantum efficiency of the photodetector improved from 3% to 12% when a diffraction grating with 265nm period was integrated on top of the photodiode. The 3dB electrical bandwidth of these photodetectors was 4.1GHz (RC limited). The dark current for these devices was 10pA at -3V bias for an area of 2500mm2. The photodetectors fabricated on 2000nm-thick SOI substrates were wire-bonded to SiGe transimpedance amplifiers with 184W transimpedance gain. When the photodiode was used in avalanche operation mode the sensitivity of -7dBm (BER<10-9) was achieved at 10Gb/s. The multiplication gain for the avalanche photodetector was in this case M=4. This is the highest speed reported for an all-silicon optical receiver.

  13. Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

    NASA Astrophysics Data System (ADS)

    Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

    2014-06-01

    A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

  14. Concave-suspended high-Q solenoid inductors with a post-CMOS MEMS process in standard wafers

    Microsoft Academic Search

    Lei Gu; Xinxin Li

    2007-01-01

    We report on concave-suspended high-Q solenoid inductors with a post-CMOS MEMS process in low-resistivity silicon substrate. The 3-mask processes include copper electroplating, photo-resist spray-coating and XeF2 gaseous etching. The peak Q-factor value is measured as 47 at 5.3 GHz with 2.96 nH inductance. A compact and four curving layouts of inductors are fabricated and tested. Both finite element simulation and

  15. On-chip skin color detection using a triple-well CMOS process

    NASA Astrophysics Data System (ADS)

    Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

    2004-03-01

    In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

  16. High-Q Solenoid Inductors With a CMOS-Compatible Concave-Suspending MEMS Process

    Microsoft Academic Search

    Lei Gu; Xinxin Li

    2007-01-01

    This paper presents micromachined solenoid inductors that are fabricated in a standard CMOS silicon substrate (with a resistivity of 1-8 Omega . cm). The solenoid is concavely embedded in a silicon cavity with the silicon wafer surface remaining a plane, and mechanically suspended to form an air gap from the bottom of the silicon cavity. In addition to facilitating flip-chip

  17. Unified P4 (Power-Performance-Process-Parasitic) Fast Optimization of a Nano-CMOS VCO

    E-print Network

    Mohanty, Saraju P.

    , dual oxide VCO physical design. We have achieved 25% power (including leakage) minimization with only 1 and parasitics. The dual- oxide physical design of the VCO is carried out at 90nm. To the best of the authors' knowledge, this is the first research reporting a dual-oxide nano-CMOS VCO design simultaneously optimized

  18. Characterization of charge accumulation and detrapping processes related to latent failure in CMOS integrated circuits

    Microsoft Academic Search

    William D. Greason; Kenneth W. K. Chum

    1994-01-01

    A series of measurements were performed on a variety of custom fabricated CMOS test structures to investigate the latent mode of failure due to ESD. Devices were stressed using the current injection test method and measurement of the quiescent current state was used to detect the failure thresholds. The fault sites were further isolated and the failure mechanisms studied by

  19. Which Photodiode to Use: A Comparison of CMOS-Compatible Structures

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2010-01-01

    While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n+/p-sub, n-well/p-sub and p+/n-well/p-sub. All structures were fabricated in a 0.5 ?m 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricatedthe standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 and 1.6 over the n+/p-sub and p+/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 and 1.2 improvement over the n+/p-sub and p+/n-well/p-sub diodes, respectively) while the p+/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity. PMID:20454596

  20. A 63 GHz VCO using a standard 0.25 ?m CMOS process

    Microsoft Academic Search

    Ren-Chieh Liu; Hong-Yeh Chang; Chi-Hsueh Wang

    2004-01-01

    A 63 GHz VCO using a 0.25 ?m 1P6M CMOS is presented. It achieves an output power of -4 dBm without any output amplifier. This VCO is tunable over a 2.5 GHz range and its phase noise is -85 dBc\\/Hz at 1 MHz offset. The IC covers an area of 0.315 mm2 and consumes 118 mW maximum.

  1. An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology

    Microsoft Academic Search

    Dae-Seok Byeon; Sung-Soo Lee; Young-Ho Lim; Jin-Sung Park; Wook-Kee Han; Pan-Suk Kwak; Dong-Hwan Kim; Dong-Hyuk Chae; Seung-Hyun Moon; Seung-Jae Lee; Hyun-Chul Cho; Jung-Woo Lee; Moo-Sung Kim; Joon-Sung Yang; Young-Woo Park; Duk-Won Bae; Jung-Dal Choi; Sung-Hoi Hur; Kang-Deog Suh

    2005-01-01

    An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 ?m2 and 133 mm2, respectively. Performance improves to 4.4 MB\\/s by using the 2 program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput

  2. CMOS Geiger photodiode array with integrated signal processing for imaging of 2D objects using quantum dots

    NASA Astrophysics Data System (ADS)

    Stapels, Christopher J.; Lawrence, William G.; Gurjar, Rajan S.; Johnson, Erik B.; Christian, James F.

    2008-08-01

    Geiger-mode photodiodes (GPD) act as binary photon detectors that convert analog light intensity into digital pulses. Fabrication of arrays of GPD in a CMOS environment simplifies the integration of signal-processing electronics to enhance the performance and provide a low-cost detector-on-a-chip platform. Such an instrument facilitates imaging applications with extremely low light and confined volumes. High sensitivity reading of small samples enables twodimensional imaging of DNA arrays and for tracking single molecules, and observing their dynamic behavior. In this work, we describe the performance of a prototype imaging detector of GPD pixels, with integrated active quenching for use in imaging of 2D objects using fluorescent labels. We demonstrate the integration of on-chip memory and a parallel readout interface for an array of CMOS GPD pixels as progress toward an all-digital detector on a chip. We also describe advances in pixel-level signal processing and solid-state photomultiplier developments.

  3. An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 ?m CMOS Process

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

    2014-01-01

    This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

  4. TFSOI complementary BiCMOS technology for low power applications

    Microsoft Academic Search

    Wen-Ling Margaret Huang; Kevin M. Klein; M. Grimaldi; Marco Racanelli; Shri Ramaswami; J. Tsao; Juergen Foerstner; Bor-Yuan C. Hwang

    1995-01-01

    A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 ?m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure

  5. Over 10 GHz lateral silicon photodetector fabricated on silicon-on-insulator substrate by CMOS-compatible process

    NASA Astrophysics Data System (ADS)

    Li, Gen; Maekita, Kazuaki; Mitsuno, Hiroya; Maruyama, Takeo; Iiyama, Koichi

    2015-04-01

    We report a design and implementation of lateral silicon photodetectors fabricated on a silicon-on-insulator (SOI) substrate in a complementary CMOS-compatible process. In addition, we disscuss the structure dependences on the frequency and optimum design for a maximum bandwidth. A standard device fabricated with a 210 nm absorbing layer, a finger width of 1.00 m, a finger spacing of 1.63 m, a square detector area of 20 20 m2, and a pad size of 60 60 m2 achieved a bandwidth of 12.6 GHz at a bias voltage of 10 V, with a responsivity of 7.5 mA/W at 850 nm wavelength. A photodetector with the same geometry, which was fabricated with a smaller pad size of 30 30 m2, exhibited a bandwidth of 13.6 GHz.

  6. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 ?m process with a high resistivity epitaxial layer

    NASA Astrophysics Data System (ADS)

    Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 ?m thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 ?m CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz0.18 ?m CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013 neq/cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 C to 30 C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz0.18 ?m CMOS process for the ALICE ITS upgrade.

  7. A highly manufacturable 0.25 ?m multiple-Vt dual gate oxide CMOS process for logic\\/embedded IC foundry technology

    Microsoft Academic Search

    M. H. Chang; J. K. Ting; J. S. Shy; L. Chen; C. W. Liu; J. Y. Wu; K. H. Pan; C. S. Hou; C. C. Tu; Y. H. Chen; S. L. Sue; S. M. Jang; S. C. Yang; C. S. Tsai; C. H. Chen; H. J. Tao; C. C. Tsai; H. C. Hsieh; Y. Y. Wang; R. Y. Chang; K. B. Cheng; T. Y. Chu; T. N. Yen; P. S. Wang; J. W. Weng; J. H. Hsu; Y. S. Ho; C. H. Ho; Y. C. Huang; R. Y. Shiue; B. K. Liew; C. H. Yu; S. C. Sun; J. Y. C. Sun

    1998-01-01

    Summary form only given. A multiple-Vt high performance, high density and highly manufacturable 0.25 ?m CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts\\/vias, and fully stacked contact\\/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for

  8. Novel contamination restrained silicidation processing using load-lock LPCVD-films and lightly doped deep drain (LD3) structure for deep submicron dual gate CMOS

    Microsoft Academic Search

    H. Kotaki; M. Nakano; S. Hayashida; T. Matsuoka; S. Kakimoto; A. Nakano; K. Uda; Y. Sato

    1995-01-01

    A novel low leakage, low resistance and high temperature stability titanium salicide process named Silicidation after ion Implantation through the Contamination-Restrained Oxygen free LPCVD-Nitride layer in a Lightly Doped diffusion layer (LD-SICRON) has been developed. This novel LD-SICRON process has been successfully implemented in deep submicron dual gate CMOS development. Junction leakage current for TiSi2-n+\\/p and -p+\\/n was reduced to

  9. A 20 Gb\\/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

    Microsoft Academic Search

    A. Mineyama; T. Suzuki; H. Ito; S. Amakawa; N. Ishihara; K. Masu

    2009-01-01

    A 9.5 mW 20 Gb\\/s 40times70 mum2 inductorless 1:4 DEMUX in 90 nm CMOS process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail

  10. A prototype 64-electrode stimulator in 65 nm CMOS process towards a high density epi-retinal prosthesis.

    PubMed

    Tran, N; Skafidas, E; Yang, J; Bai, S; Fu, M; Ng, D; Halpern, M; Mareels, I

    2011-01-01

    This paper presents a highly flexible 64-electrode stimulator using 65 nm CMOS process fabricated as a stage towards a 1024-electrode epi-retinal prosthesis, which aims to restore partial vision in patients suffering from eye diseases such as retinitis pigmentosa (RP) and age-related macular degradation (AMD). The stimulator drives 64 electrodes with many flexible features, which are necessary before making a complete 1024-electrode implant chip. Each electrode driver can provide a bi-phasic stimulus current with fully programmable parameters such as amplitude, pulse duration, inter-phase gap, and stimulation rate. The electrode driver operates in an alternately pull-push manner with only one current source working at a time, which helps reduce headroom voltage while controlling charge balance at the active electrode. The stimulator varies both stimulus current amplitude and stimulation rate to represent phosphene brightness. The stimulus current amplitude starts from the tissue depolarization threshold with 64 different levels. The selection of active and return electrodes is arbitrary, any electrodes and any number of them can be selected at any time. The power consumption of the stimulator is 400 ?W excluding the stimulus power. Measurement results verify correct operation. The stimulator is easily scaled up to drive 1024 electrodes. PMID:22255883

  11. Hybrid phase-locked loop with fast locking time and low spur in a 0.18-?m CMOS process

    NASA Astrophysics Data System (ADS)

    Zhu, Si-Heng; Si, Li-Ming; Guo, Chao; Shi, Jun-Yu; Zhu, Wei-Ren

    2014-07-01

    We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-?m complementary metal oxide semiconductor (CMOS) process with a total die area of 1.40.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 ?s with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

  12. SEMICONDUCTOR INTEGRATED CIRCUITS: An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

    NASA Astrophysics Data System (ADS)

    Peijun, Gao; J, Oh N.; Hao, Min

    2009-08-01

    A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 ?m CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

  13. Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

    2006-01-01

    We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

  14. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  15. CMOS RF modeling for GHz communication IC's

    Microsoft Academic Search

    Jia-Jiunn Ou; Xiaodong Jin; Ingrid Ma; Chenming Hu; Paul R. Gray

    1998-01-01

    With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and

  16. Process optimization of developer soluble organic BARC and its characteristics in CMOS devices

    NASA Astrophysics Data System (ADS)

    Lim, Yeon Hwa; Kim, Young Keun; Choi, Jae Sung; Lee, Jeong Gun

    2005-05-01

    As the IC industry is moving toward 90nm node or below, the critical dimension size of implant layers has shrunk to 250nm or smaller. To achieve better CD uniformity, dyed KrF resist and top anti-reflective coating (TARC) are commonly used in advanced photo process of implant layers, while typical organic BARC are not used because it requires dry etch process that damages the substrate and needs additional process steps. In order to overcome those shortcomings, developable BARC is introduced. It is a new type of BARC which is soluble to developer, TMAH solution, in the resist development step. This developer-soluble KrF BARC consists of polyamic acid and its solubility to alkaline could be adjusted by changing bake condition. In this experiment, we evaluated the margin of developable BARC process. Developable BARC reduces the standing wave of photoresist and improves the ID bias and CD uniformity as applied to implant feature printing. However, Developable BARC has a narrow thermal process margin. It is the profile of developable BARC that easily changes according to the coating thickness or thermal process conditions. Even in the same bake conditions, developable BARC profile changes according to the pattern densities. To observe the effects of developable BARC on the device performance, we compare electrical data of devices produced with and without developable BARC. They have the differences in the threshold voltage, leakage current and saturation current. Probably, the residues of the developable BARC after the development bring about the differences.

  17. Development of a RF Bipolar Transistor in a Standard 0.35m CMOS Technology

    E-print Network

    Ng, Wai Tung

    Development of a RF Bipolar Transistor in a Standard 0.35µm CMOS Technology I-Shan Michael Sun-0021, Japan ABSTRACT A RF Bipolar Transistor integrated to a standard 0.35µm CMOS process is presented compared to previously published BiCMOS technologies. Key Words 0.35µm CMOS Technology, RF Silicon Bipolar

  18. A P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) Aware Dual-VT h Nano-CMOS VCO

    E-print Network

    Mohanty, Saraju P.

    and temperature have a drastic effect on the performance (center frequency) of the VCO. A design optimization-controlled oscillator or VCO is an electronic oscillator designed to be controlled in oscillation frequency by a voltage-CMOS VCO. 3. Design of a P4VT-optimal 90nm VCO. The rest of the paper is organized as follows: Related

  19. CMOS Architecture of Synchronous Pulse-Coupled Neural Network and Its Application to Image Processing

    E-print Network

    Wilamowski, Bogdan Maciej

    first, then its application to image processing and the synchronization effect between neighboring-propagation velocity, (iv) pulse-shaping action during its propagation through the neuristor line, and (v) annihilation reactions, with a given external stimulus, by generating a stream of electrical pulse waves. In this case

  20. Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage

    Microsoft Academic Search

    Bo Liu; Hamid Reza Pourshaghaghi; Sebastian Moreno Londono; Jose Pineda de Gyvez

    2011-01-01

    Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. The main drawbacks are performance degradation due to the exponentially reduced driving current, and the effect of increased sensitivity to process variation. To obtain energy savings while reducing performance degradation, we propose the design of a robust sub-threshold library and post-silicon tuning using an adaptive fuzzy

  1. Anomalous NMOSFET hot carrier degradation due to hole injection in a DGO CMOS process

    Microsoft Academic Search

    D. Brisbin; Y. Mirgorodski; P. Chaparala

    2004-01-01

    It has been reported that MOSFET hot carrier (HC) performance is degraded by back-end-of-line (BEOL) processing steps such as interlayer dielectric film deposition, passivation, and H2 annealing. These effects are associated with the incorporation of additional hydrogen at the Si-SiO2 interface states to passivate dangling bonds. This paper focuses on an unusual (anomalous) IDsat HC degradation behavior seen on a

  2. Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels

    PubMed Central

    Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

    2008-01-01

    In this paper we present a novel, quadruple well process developed in a modern 0.18 ?m CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 ?m pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

  3. On the processing aspects of high performance hybrid backside illuminated CMOS imagers

    NASA Astrophysics Data System (ADS)

    De Vos, Joeri; De Munck, Koen; Minoglou, Kiki; Ramachandra Rao, Padmakumar; Akif Erismis, Mehmet; De Moor, Piet; Sabuncuoglu Tezcan, Deniz

    2011-07-01

    In this paper we present a successful integration scheme of a backside (BS) illuminated 1024 1024 pixel, 30 m thin, sensor array that is flip chipped on a read-out IC die with 10 m diameter indium micro bumps, where the pixel pitch is 22.5 m. A novel BS alignment strategy to avoid Pyrex glass as a temporary carrier for wafer thinning is described. Pyrex is namely not compatible in a high-end Si process environment due to its fragile and contaminating nature. Further special attention is given to critical steps leading toward high broadband quantum efficiency of 80-90%. It is also shown that through the introduction of high aspect ratio pixel separating trenches, inter-pixel electrical crosstalk can be avoided.

  4. Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

    Microsoft Academic Search

    Federico A. Altolaguirre; Ming-Dou Ker

    2011-01-01

    The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21 A in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as

  5. Asynchronous dual-mode buck converter design with protection circuits in 0.13m CMOS process for battery applications

    Microsoft Academic Search

    Jefferson A. Hora; Jiun-Chang Zeng; Wan-Rone Liou

    2009-01-01

    An asynchronous architecture dual-mode DC-DC buck converter utilizing an external Schottky diode was evaluated and implemented in SMIC 0.13 ?m 1P6M 3.3\\/2.5 V logic signal CMOS technology. This paper aimed to employ a simple, low cost, and small solution size with on-chip compensation implementation while not compromising high efficiency requirement. Maintaining high efficiency is achieved by adopting a switch-mode pulse-width

  6. Cmos-Compatible High Voltage Integrated Circuits

    Microsoft Academic Search

    Zahir Parpia

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 mum CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50

  7. Ge technology beyond Si CMOS

    NASA Astrophysics Data System (ADS)

    Chin, Albert

    2012-12-01

    To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at <= 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to <= 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-?/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

  8. An ultra-low-power area-efficient non-volatile memory in a 0.18 ?m single-poly CMOS process for passive RFID tags

    NASA Astrophysics Data System (ADS)

    Xiaoyun, Jia; Peng, Feng; Shengguang, Zhang; Nanjian, Wu; Baiqin, Zhao; Su, Liu

    2013-08-01

    This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 ?m single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional FowlerNordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 ?m single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 ?m2 and 0.12 mm2, respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 ?W/0.69 ?W at a read/write rate of (268 kb/s)/(3.0 kb/s).

  9. Review of radiation damage studies on DNW CMOS MAPS

    NASA Astrophysics Data System (ADS)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

    2013-12-01

    Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.71013 cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

  10. pn photodiode in 0.35-?m high-voltage CMOS with 1.2-GHz bandwidth

    NASA Astrophysics Data System (ADS)

    Enne, Reinhard; Steindl, Bernhard; Schneider-Hornstein, Kerstin; Zimmermann, Horst

    2014-11-01

    A pn-junction photodiode with a bandwidth in the GHz range is presented. This photodiode is fabricated in a standard 0.35-?m high-voltage CMOS process with deep n-wells which can isolate negative substrate potentials down to -100 V from the MOS transistors. This photodiode can, therefore, be implemented together with circuits on the same chip. At a reverse bias voltage of -90 V, a bandwidth of 1.2 GHz was measured for 670-nm light. The breakdown voltage of this photodiode is about -180 V.

  11. Fabrication of CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  12. CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-?m CMOS technology

    Microsoft Academic Search

    Hon-Sum Philip Wong; Richard T. Chang; E. Crabbe; P. D. Agnello

    1998-01-01

    This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-?m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to

  13. Post-CMOS integration of germanium microstructures

    Microsoft Academic Search

    A. E. Franke; D. Bilic; D. T. Chang; P. T. Jones; T.-J. King; R. T. Howe; G. C. Johnson

    1999-01-01

    Polycrystalline germanium (poly-Ge) microstructures have been fabricated on standard CMOS wafers. Conventional low pressure chemical vapor deposition (LPCVD) and rapid thermal annealing (RTA) processes were used to achieve low-resistivity (2.3 m?-cm) tensile poly-Ge structural films, with a thermal budget which is compatible with Al (2% Si) metallization. The CMOS circuitry was passivated with low-temperature oxide and amorphous Si; the latter

  14. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 m CMOS Process

    PubMed Central

    Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

    2014-01-01

    The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 m CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 W from 1.8 V supply and 88.05 A average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

  15. CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers

    E-print Network

    Xu, Rui

    2010-10-12

    radar, distance sensor, through wall radar to high speed, short distance communications. The CMOS integrated circuit is an attractive, low cost approach for implementing UWB technology. The improving cut-off frequency of the transistor in CMOS process...

  16. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    E-print Network

    Wade, Mark T.

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS ...

  17. Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation

    E-print Network

    Dokmeci, Mehmet

    Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation-level post processing. The chip was fabricated using the AMI 0.5m CMOS Technology. An electroless zincation process was performed over the Aluminum assembly electrodes (Metal 3 of CMOS technology) to clean

  18. Monolithic multiple axis accelerometer design in standard CMOS

    Microsoft Academic Search

    Brett Warneke; Eric G. Hoffman; Kristofer S. Pister

    1995-01-01

    Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Out postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all

  19. Monolithic multiple axis accelerometer design in standard CMOS

    Microsoft Academic Search

    Brett Warneke; Eric Hoffman; Kristofer S. J. Pister

    1995-01-01

    Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Our postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all

  20. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  1. A CMOS biquad at VHF

    Microsoft Academic Search

    Martin Snelgrove; Ayal Shoval

    1991-01-01

    A differential transconductance-C biquad implemented in the digital subset of a 0.9-?m CMOS process operates at frequencies up to 450 MHz and Q-factors to approximately 100 with SNR (signal-to-noise ratio) in the range of 35-45 dB. By switching in capacitors and adjusting control voltages it can be tuned to below 30 MHz, demonstrating the capability of operating over the entire

  2. Ion traps fabricated in a CMOS foundry

    E-print Network

    Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

    2014-01-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  3. Ion traps fabricated in a CMOS foundry

    NASA Astrophysics Data System (ADS)

    Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

    2014-07-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  4. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  5. Ion traps fabricated in a CMOS foundry

    E-print Network

    K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

    2014-06-13

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  6. Reliability of CMOS/SOS integrated circuits

    NASA Astrophysics Data System (ADS)

    Veloric, H.; Dugan, M. P.; Morris, W.; Denning, R.; Schnable, G.

    1984-06-01

    Reliability data for silicon-gate integrated circuits of various types are summarized. Included are failure rates for devices ranging from plastic-encapsulated commercial products to high-reliability hermetically-sealed integrated circuits for military and aerospace applications. Data are presented on devices fabricated by the original CMOS/SOS silicon-gate process and on devices prepared by advanced processes. These include lower wafer-process temperatures and improved wafer-processing techniques that permit thinner gate dielectrics and smaller feature sizes. Because they have fewer possible failure modes, CMOS/SOS integrated circuits have demonstrated a reliability at least equal to that achieved by bulk-MOS ICs.

  7. Impact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits

    E-print Network

    Mohanty, Saraju P.

    issues in modern nanometer CMOS processes are discussed in this work. Several VCO and PLL designs have been already presented in the literature [6]. High performance CMOS based VCO designs have beenImpact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits Saraju P

  8. Fundamental performance differences of CMOS and CCD imagers: part V

    NASA Astrophysics Data System (ADS)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  9. Fully integrated CMOS and high voltage compatible RF MEMS technology

    Microsoft Academic Search

    Lingpeng Guan; J. K. O. Sin; Haitao Liu; Zhibin Xiong

    2004-01-01

    In this paper, a fully integrated CMOS and high voltage compatible RF MEMS (radio frequency microelectromechanical systems) technology is proposed and demonstrated for the first time. The high performance RF MEMS switch, high voltage MOSFET, and CMOS devices are all obtained using a simple process. The fabricated high voltage device has a breakdown voltage of over 35V. The MEMS capacitive

  10. Low-Power Strategies for High-Performance CMOS Circuits

    Microsoft Academic Search

    Tobias G. Noll; RWTH Aachen Rogowski-Institu

    1994-01-01

    Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as

  11. CMOS compatible wafer scale adhesive bonding for circuit transfer

    Microsoft Academic Search

    S. van der Green; Maartein Rosmeulen; Philippe Jansen; Kris Baert; Ludo Deferm

    1997-01-01

    Reports on a transfer technique for CMOS circuits based on a newly developed bonding technique, namely wafer scale adhesive bonding using epoxies. The circuit transfer sequence consists of three steps: bonding a CMOS processed SIMOX wafer to a Pyrex glass wafer, thinning the SIMOX wafer down to the buried oxide and exposing the contact pads. A test chip was designed

  12. CMOS floating-point vector-arithmetic unit

    NASA Astrophysics Data System (ADS)

    Timmermann, D.; Rix, B.; Hahn, H.; Hosticka, B. J.

    1994-05-01

    This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 micron double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

  13. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  14. A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

    Microsoft Academic Search

    Philippe Roche; Gilles Gasiot; Slawosz Uznanski; Jean-Marc Daveau; Josep Torras-Flaquer; Sylvain Clerc; Reno Harboe-Sorensen

    2010-01-01

    This paper presents new experimental and modeling evidences that advanced commercial CMOS technologies get intrinsically harder against space radiations with technology downscaling. A 65 nm commercial bulk CMOS process can deliver improved radiation-tolerance without sacrificing electrical performance.

  15. A sampled-data CMOS analog adaptive filter

    NASA Astrophysics Data System (ADS)

    Gomez, Gabriel; Siferd, Raymond

    A fully analog sampled-data CMOS adaptive filter realizing the LMS (least mean squared) adaptation on a four-tap FIR (finite impulse response) filter has been fabricated. The system uses clocked CMOS sampled-data storage, four-quadrant CMOS analog multipliers, and CMOS op amp-based arithmetic modules. For achieving higher output sampling rates and for allowing modularity, a parallel architecture has been used, implementing each filter tap separately instead of using a single time-multiplexed processing unit. The prototype chip was fabricated using double-metal double-poly 2-micron CMOS P-well technology, occupying an area of 4.0 sq mm and using +/- 5-V power supplies.

  16. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  17. Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

    PubMed Central

    Huang, Yue; Mason, Andrew J.

    2013-01-01

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

  18. Characterization and comparison of lateral amorphous semiconductors with embedded Frisch grid detectors on 0.18?m CMOS processed substrate for medical imaging applications

    NASA Astrophysics Data System (ADS)

    Hristovski, Christos; Goldan, Amir; Majid, Shaikh Hasibul; Wang, Kai; Shafique, Umar; Karim, Karim

    2011-03-01

    An indirect digital x-ray detector is designed, fabricated, and tested. The detector integrates a high speed, low noise CMOS substrate with two types of amorphous semiconductors on the circuit surface. Using a laterally oriented layout a-Si:H or a-Se can be used to coat the CMOS circuit and provide high speed photoresponse to complement the high speed circuits possible on CMOS technology. The circuit also aims to reduce the effect of slow carriers by integrated a Frisch style grid on the photoconductive layer to screen for the slow carriers. Simulations show a uniform photoresponse for photons absorbed on the top layer and an enhanced response when using a Frisch grid. EQE and noise results are presented. Finally, possible applications and improvements to the area of indirect x-ray imaging that are capable of easily being implemented on the substrate are suggested.

  19. Transistor matching in analog CMOS applications

    Microsoft Academic Search

    Marcel J. M. Pelgrom; Hans P. Tuinhout; Maarten Vertregt

    1998-01-01

    This paper gives an overview of MOSFET mismatch effects that form a performance\\/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease

  20. Quadrature Generation Techniques in CMOS Relaxation Oscillators

    E-print Network

    Krishnapura, Nagendra

    ) A differential VCO running at twice the desired operating frequency followed by a divide-by-2 circuit: Design. These are inspired by similar techniques used to couple LC-VCO's in quadrature. The QRXO's are designed in a UMC 0.4GHz quadrature oscillators are designed and simulated in a UMC 0.18µm CMOS process. The shunt

  1. Neural Networks in CMOS Manufacturing: Some Examples

    Microsoft Academic Search

    Edward A. Rietman

    1998-01-01

    The focus of this paper will be on two neural network models for plasma aided CMOS manufacturing. Both models were developed with strict statistical cross- validation and applied to real world applications. A plasma neural network gate etch controller has shown a 20% improvement in throughput in wafer processing by eliminating a set-up step, and has reduced the variance of

  2. N-well resistance modelling in Q-factor of doughnut-shaped PN varactors

    NASA Astrophysics Data System (ADS)

    Marrero-Martn, M.; Gonzlez, B.; Garca, J.; Hernndez, A.

    2015-01-01

    In this paper the N-well resistance in doughnut-shaped PN varactors, with the cathode connected to an N+ buried layer, has been modelled. The proposed expression for the N-well resistance, numerically validated, is based on the device geometry and overlapping of adjacent basic cells, and adequately reproduces its applied reverse bias voltage dependency. Once the varactor extrinsic parasitic components are extracted considering proximity effects, from anode-to-cathode measured RF admittances, and frequencies ranging from 0.5 GHz to 10 GHz, the impact of the N-well resistance on the experimental varactor quality factor is determined for reverse biases up to 5 V.

  3. Theoretical performance analysis for CMOS based high resolution detectors.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 ?m thick HL-type CsI phosphor, a 50 ?m-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  4. A Wideband Low-Phase-Noise CMOS VCO Axel D. Berny, Ali M. Niknejad and Robert G. Meyer

    E-print Network

    California at Berkeley, University of

    , Berkeley, CA 94720 Abstract A CMOS VCO has been designed and fabricated in a commercial 0.25µm CMOS process sensitivity. Circuit Design An LC VCO topology is chosen mainly for its potential to achieve good phase noiseA Wideband Low-Phase-Noise CMOS VCO Axel D. Berny, Ali M. Niknejad and Robert G. Meyer Berkeley

  5. Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process

    SciTech Connect

    Allen, R.A.; Cresswell, M.W.; Linholm, L.W.; Owen, J.C. III; Ellenwood, C.H. [National Inst. of Standards and Technology, Gaithersburg, MD (United States); Hill, T.A.; Benecke, J.D.; Volk, S.R.; Stewart, H.D. [Sandia National Labs., Albuquerque, NM (United States)

    1994-02-01

    The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and overlay on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described.

  6. Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits

    Microsoft Academic Search

    Zhengzheng Wu; Lei Gu; Xinxin Li

    2009-01-01

    This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high performance microelectromechanical systems solenoid inductors and metal-insulator-metal (MIM) capacitors by using a post CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of

  7. Design on Power-Rail ESD Clamp Circuit for 3.3-V I\\/O Interface by Using Only 1-V\\/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

    Microsoft Academic Search

    Ming-Dou Ker; Wen-Yi Chen; Kuo-Chun Hsu

    2006-01-01

    A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I\\/O) interface is proposed and verified in a 130-nm 1-V\\/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS\\/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I\\/O interface applications. A special ESD

  8. CMOS Bridging Fault Detection

    Microsoft Academic Search

    Thomas M. Storey; Wojciech Maly

    1990-01-01

    The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

  9. A CMOS triode transconductor

    Microsoft Academic Search

    Bram Nauta; Eric Klumperink; Wim Kruiskamp

    1991-01-01

    A novel versatile CMOS voltage to current converter is presented. The conversion transistors operate in the triode region. The linearity is high (total harmonic distortion <0.4% for 6 Vpp input signals on a breadboard). The transconductance can be tuned over a wide range (factor 25 on breadboard, factor 100 expected on chip). The input voltages are not restricted to a

  10. OLED-on-CMOS integration for optoelectronic sensor applications

    NASA Astrophysics Data System (ADS)

    Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Trker, Michael; Grillberger, Christiane; Amelung, Jrg

    2007-02-01

    Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

  11. A 0.13m CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

    NASA Astrophysics Data System (ADS)

    Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

    A 2.4GHz 0.13m CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40C and +90C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13m CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

  12. A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurement

    Microsoft Academic Search

    M. H. Lin; E. R. Hsieh; S. S. Chung; C. H. Tsai; P. W. Liu; Y. H. Lin; G. H. Ma

    2009-01-01

    In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the ID-RTN (drain current random telegraph noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and

  13. Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-?m to 90-nm generation

    Microsoft Academic Search

    P. Hazucha; T. Karnik; J. Maiz; S. Walstra; B. Bloechel; J. Tschanz; G. Dermer; S. Hareland; P. Armstrong; S. Borkar

    2003-01-01

    The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 ?m, 0.18 ?m, 0.13 ?m, and 90 nm showed an increase of 8% per generation.

  14. Hafnium oxide and hafnium aluminum oxide for CMOS applications

    Microsoft Academic Search

    Wenjuan Zhu

    2003-01-01

    The continued scaling of the CMOS gate dielectric to its fundamental limit governed by the large gate leakage current requires the introduction of high-k material for sub-100-nm technology nodes. This dissertation research deals with the physical and electrical properties of a promising high-k candidate, hafnium oxide, as a gate dielectric for CMOS applications. Hafnium oxide made by the Jet-Vapor-Deposition process

  15. Wideband VGAs Using a CMOS Transconductor in Triode region

    Microsoft Academic Search

    Hui Dong Lee; Kyung Ai Lee; Songcheol Hong

    2006-01-01

    Wideband variable gain amplifiers (VGAs) fabricated using 0.18 mum CMOS process are presented. A scheme with a CMOS triode transconductor is proposed to achieve linear-in-dB characteristics of VGAs for ultra wideband (UWB) systems. The implemented transmitter (TX) VGA shows a highly linear gain range of 28.4 dB (7 dB to -21.4 dB) and a bandwidth of 1200 MHz, while drawing

  16. CMOS balanced output transconductor and applications for analog VLSI

    Microsoft Academic Search

    Soliman A. Mahmound; Ahmed M. Soliman

    1999-01-01

    A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing bandpasslowpassallpassnotch biquad mixed mode filter using four BOTAs and two grounded capacitors and in realizing current mode MOS-C

  17. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  18. An ultra-low dark current CMOS image sensor cell using n+ ring reset

    Microsoft Academic Search

    Hsiu-Yu Cheng; Ya-Chin King

    2002-01-01

    We present in this letter for the first time a new CMOS image sensor cell using n+-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing

  19. A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations

    Microsoft Academic Search

    Hsiu-Yu Cheng; Ya-Chin King

    2003-01-01

    An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-?m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate\\/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more

  20. Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier

    Microsoft Academic Search

    Dong Ho Lee; Jeonghu Han; Songcheol Hong

    2007-01-01

    A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the

  1. Development and characterization of CMOS-based monolithic X-ray imager sensor

    Microsoft Academic Search

    Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

    2007-01-01

    We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

  2. A transregional CMOS SRAM with single, logic VDD and dynamic power rails

    Microsoft Academic Search

    A. J. Bhavnagarwala; S. V. Kosonocky; S. P. Kowalczyk; R. V. Joshi; Y. H. Chan; U. Srinivasan; J. K. Wadhwa

    2004-01-01

    New circuit techniques are reported that enable a single VDD SRAM to operate at logic compatible voltages with a cell read current and cell static noise margin (SNM) typically seen with higher\\/dual VDD SRAMs. Implemented in a 65nm CMOS SOI process with no alterations to the CMOS process or to a conventional, single VT SRAM cell, the voltage across power

  3. CMOS micromechanical resonator oscillator

    Microsoft Academic Search

    C. T.-C. Nguyen; R. T. Howe

    1993-01-01

    A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator to achieve stability and phase noise performance comparable to those of quartz crystal oscillators. It is shown that the closed-loop, steady-state oscillation amplitude of this oscillator can be controlled through the DC-bias

  4. Advances in fully CMOS integrated photonic devices

    NASA Astrophysics Data System (ADS)

    Michel, Jurgen; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Giziewicz, W. P.; Beals, M.; Kimerling, L. C.; Kopa, A.; Apsel, A. B.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.; Pomerene, A.; Carothers, D.; Grove, M. J.

    2007-02-01

    The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell University, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable optical filters.

  5. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  6. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  7. A 250-ps time-resolution CMOS multihit time-to-digital converter for nuclear physics experiments

    SciTech Connect

    Bigongiari, F.; Roncella, R.; Saletti, R.; Terreni, P. [Univ. of Pisa (Italy)] [Univ. of Pisa (Italy)

    1999-04-01

    This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-{micro}m CMOS process with an area of about 77 mm{sup 2}. Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps.

  8. CMOS compatible nanoscale nonvolatile resistance switching memory.

    PubMed

    Jo, Sung Hyun; Lu, Wei

    2008-02-01

    We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications. PMID:18217785

  9. Shallow trench isolation for advanced ULSI CMOS technologies

    Microsoft Academic Search

    M. Nandakumar; A. Chatterjee; S. Sridhar; K. Joyner; M. Rodder; I.-C. Chen

    1998-01-01

    This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 ?m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows:

  10. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  11. Active Area Shape Influence on the Dark Current of CMOS Imagers.

    E-print Network

    Active Area Shape Influence on the Dark Current of CMOS Imagers. Igor Shcherback, Alexander Belenky Abstract This work presents an empirical dark current model for CMOS Active Pixel Sensors (APS). The model technology process. This quantitative model determines the pixel dark current dependence on two contributing

  12. Technique to Design MLP's Networks in CMOS Technology with Adjustment of the Back-Propagation Algorithm

    Microsoft Academic Search

    Fabio De Albuquerque Pereira; Js Jesus Fiais Cerqueira

    2002-01-01

    Conception of structures in CMOS technology that de- mand low power and low silicon area consumption have been widely investigated in the implementation of artifi- cial neural networks in VLSI integrated circuits for signal processing purposes (2), (6). Feedforward MLP networks' building blocks require CMOS multipliers for implement- ing the synapses and the activation function circuits. A larger scale of

  13. Impact of CMOS technology scaling on the atmospheric neutron soft error rate

    Microsoft Academic Search

    Peter Hazucha; Christer Svensson

    2000-01-01

    We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size LG. A different

  14. High voltage AlGaN/GaN metaloxidesemiconductor high-electron mobility transistors with regrown In0.14Ga0.86N contact using a CMOS compatible gold-free process

    NASA Astrophysics Data System (ADS)

    Liu, Xinke; Amin Bhuiyan, Maruf; S/O Somasuntharam, Pannirselvam; Beng Soh, Chew; Liu, Zhihong; Zhi Chi, Dong; Liu, Wei; Lu, Youming; Yu, Wenjie; Seow Tan, Leng; Yeo, Yee-Chia

    2014-12-01

    We report the fabrication and characterization of high voltage AlGaN/GaN metaloxidesemiconductor high-electron mobility transistors (MOSHEMTs) with selectively regrown In0.14Ga0.86N contact using a CMOS compatible gold-free process. Device with the regrown InGaN contact with a gate-to-drain spacing LGD of 5 m achieves an off-state breakdown voltage VBR of 800 V and on-state resistance Ron of 2 m?cm2. The VBR achieved in this work is higher than those of gold-free GaN MOSHEMTs with gate-to-drain spacing LGD below 10 m.

  15. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  16. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  17. Regenerative switching CMOS system

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  18. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  19. A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

    SciTech Connect

    Maj, Piotr; Grybos, P.; Szczgiel, R.; Kmon, P.; Drozd, A.; Deptuch, G.

    2013-11-07

    We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 ?m. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e? rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

  20. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    SciTech Connect

    Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

  1. Monolithic multiple axis accelerometer design in standard CMOS

    NASA Astrophysics Data System (ADS)

    Warneke, Brett; Hoffman, Eric G.; Pister, Kristofer S. J.

    1995-09-01

    Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Out postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all spacial coordinates from a widely-accessible source and at a minimal cost. Fabrication of accelerometers for all three axes and associated electronics on a single piece of silicon reduces the cost of 3D acceleration detection while increasing sensor reliability.

  2. Hybrid postprocessing etching for CMOS-compatible MEMS

    Microsoft Academic Search

    Nim H. Tea; V. Milanovic; Christian A. Zincke; John S. Suehle; Michael Gaitan; Mona E. Zaghloul; Jon Geist

    1997-01-01

    A major limitation in the fabrication of microstructures as a postCMOS (complimentary metal oxide semiconductor) process has been overcome by the development of a hybrid processing technique, which combines both an isotropic and anisotropic etch step. Using this hybrid technique, microelectromechanical structures with sizes ranging from 0.05 to ~1 mm in width and up to 6 mm in length were

  3. Compact CMOS linear transconductor and four-quadrant analogue multiplier

    Microsoft Academic Search

    Mladen Panovic; Andreas Demosthenous

    2004-01-01

    This paper describes a low voltage\\/low power MOS linear transconductor which can be configured to realize a square-law function circuit and a four quadrant analogue multiplier. The compact analogue computation cells described are particularly suited to parallel processing systems. The circuits were fabricated using a 0.8 ?m CMOS process and operate from a 2 V power supply.

  4. Cmos-Compatible High Voltage Integrated Circuits.

    NASA Astrophysics Data System (ADS)

    Parpia, Zahir

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 ?m CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS -bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT. The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.

  5. Transistor sizing in CMOS circuits

    Microsoft Academic Search

    Mehmet A. Cirit

    1987-01-01

    The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

  6. CMOS digital intra-oral sensor for x-ray radiography

    NASA Astrophysics Data System (ADS)

    Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

    2011-03-01

    In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

  7. Integration of silicon photonics into electronic processes

    E-print Network

    Orcutt, Jason S.

    Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on ...

  8. Radiation imaging with a new scintillator and a CMOS camera

    NASA Astrophysics Data System (ADS)

    Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

    2014-07-01

    A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 0.4 ?m and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

  9. CMOS passive pixel image design techniques

    E-print Network

    Fujimori, Iliana L. (Iliana Lucia)

    2002-01-01

    CMOS technology provides an attractive alternative to the currently dominant CCD technology for implementing low-power, low-cost imagers with high levels of integration. Two pixel configurations are possible in CMOS ...

  10. Nanomechanical switch for integration with CMOS logic.

    SciTech Connect

    Nordquist, Christopher Daniel; Wolfley, Steven L.; Baker, Michael Sean; Czaplewski, David A.; Wendt, Joel Robert; Kraus, Garth Merlin; de Boer, Maarten Pieter; Patrizi, Gary A.

    2008-11-01

    We designed, fabricated and measured the performance of nanoelectromechanical (NEMS) switches. Initial data are reported with one of the switch designs having a measured switching time of 400 ns and an operating voltage of 5 V. The switches operated laterally with unmeasurable leakage current in the 'off' state. Surface micromachining techniques were used to fabricate the switches. All processing was CMOS compatible. A single metal layer, defined by a single mask step, was used as the mechanical switch layer. The details of the modeling, fabrication and testing of the NEMS switches are reported.

  11. Color recognition sensor in standard CMOS technology

    NASA Astrophysics Data System (ADS)

    Batistell, Graciele; Zhang, Vincent Chi; Sturm, Johannes

    2014-12-01

    Two integrated color detectors are presented as a solution for low cost color sensing applications. The color detection is based on lateral carrier diffusion and wavelength-dependent absorption-depth. The proposed detectors are implemented in a standard 130 nm CMOS technology without process modification or color filters. Three independent output signals are obtained with spectral responsivities optimized to short, middle and long wavelengths. R, G, B or X, Y, Z standard color representation can be realized by a linear transformation of the output signals.

  12. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  13. Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications

    Microsoft Academic Search

    Saurabh Kumar Singh; T. K. Bhattacharyya; Ashudeb Dutta

    2005-01-01

    A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18? CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling

  14. 3D integration of sub-surface photonics with CMOS

    Microsoft Academic Search

    Bahram Jalali; Tejaswi Indukuri; Prakash Koonath

    2006-01-01

    The integration of photonics and electronics on a single silicon substrate requires technologies that can add optical functionalities without significantly sacrificing valuable wafer area. To this end, we have developed an innovative fabrication process, called SIMOX 3-D Sculpting, that enables monolithic optoelectronic integration in a manner that does not compromise the economics of CMOS manufacturing. In this technique, photonic devices

  15. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

  16. Thin Film on CMOS Active Pixel Sensor for Space Applications

    PubMed Central

    Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

    2008-01-01

    A 664 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

  17. A 0.06 mm2 1.0 V 2.5 mW 10 bit 250 MS/s current-steering D/A converter in 65 nm GP CMOS process

    NASA Astrophysics Data System (ADS)

    Yawei, Guo; Li, Li; Peng, Ou; Zhida, Hui; Xu, Cheng; Xiaoyang, Zeng

    2014-06-01

    A 10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard VT core devices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity (INL) yield with both end-point line and best-fit line. A formula is derived for the relationship of INL and output impedance. The relation of dynamic range and output impedance is also discussed. The double centroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to overcome the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.

  18. MonoColor CMOS sensor

    NASA Astrophysics Data System (ADS)

    Wang, Ynjiun P.

    2009-02-01

    A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since the majority of pixels are monochrome, MonoColor sensor maintains 98% barcode decode performance compared with a pure monochrome CMOS sensor. With the help of monochrome and color pixel fusion technique, the resulting color pictures have similar color quality in terms of Color Semantic Error (CSE) compared with a Bayer pattern (RGB) CMOS color camera. Since monochrome pixels are more sensitive than color pixels, a MonoColor sensor produces in general about 2X brighter color picture and higher luminance pixel resolution.

  19. Beyond CMOS: heterogeneous integration of IIIV devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of IIIV electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our IIIV BiCMOS process has been scaled to 200?mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of IIIV devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  20. Development of CMOS-compatible membrane projection lithography

    NASA Astrophysics Data System (ADS)

    Burckel, D. Bruce; Samora, Sally; Wiwi, Mike; Wendt, Joel R.

    2013-09-01

    Recently we have demonstrated membrane projection lithography (MPL) as a fabrication approach capable of creating 3D structures with sub-micron metallic inclusions for use in metamaterial and plasmonic applications using polymer material systems. While polymers provide several advantages in processing, they are soft and subject to stress-induced buckling. Furthermore, in next generation active photonic structures, integration of photonic components with CMOS electronics is desirable. While the MPL process flow is conceptually simple, it requires matrix, membrane and backfill materials with orthogonal processing deposition/removal chemistries. By transitioning the MPL process flow into an entirely inorganic material set based around silicon and standard CMOS-compatible materials, several elements of silicon microelectronics can be integrated into photonic devices at the unit-cell scale. This paper will present detailed fabrication and characterization data of these materials, emphasizing the processing trade space as well as optical characterization of the resulting structures.

  1. Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

    Microsoft Academic Search

    Armin T. Tilke; Chris Stapelmann; Manfred Eller; Karl-Heinz Bach; Roland Hampp; Richard Lindsay; Richard Conti; William Wille; Rakesh Jaiswal; Maria Galiano; Alok Jain

    2007-01-01

    In the present work, a high aspect ratio process (HARP) using a new O3\\/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI

  2. Novel CMOS readout techniques for uncooled pyroelectric IR FPA

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Chin, Yuan-Lung; Chung, Wen-Yaw; Hsiung, Shen-Kan; Chou, Jung-Chuan

    1998-09-01

    Based on the application of the source follower per detector (SFD) input biasing technique, a new redout structure for the IR focal-plane-array (FPA), called the variable gain source follower per detector (VGSFD) is proposed and analyzed. The readout circuit of VGSFD of a unit cell of pyroelectric sensor under investigation, is composed of a source follower per detector circuit, high gain amplifier, and the reset switch. The VGSFD readout chip has been designed in 0.5 micrometers double-poly-double-metal n-well CMOS technology in various formats from 8 by 8 to 128 by 128. The experimental 8 by 8 VGSFD measurement results of the fabricated readout chip at room temperature have successfully verified both the readout function and performance. The high gain, low power, high sensitivity readout performances are achieved in a 50 by 50 micrometers (superscript 2) pixel size.

  3. RF-CMOS performance trends

    Microsoft Academic Search

    Pierre H. Woerlee; Mathijs J. Knitel; Ronald van Langevelde; Dirk B. M. Klaassen; Luuk F. Tiemeijer; Andries J. Scholten; A. T. A. Zegers-van Duijnhoven

    2001-01-01

    The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance

  4. A CMOS Switched Transconductor Mixer

    Microsoft Academic Search

    Eric A. M. Klumperink; Simon M. Louwsma; Gerard J. M. Wienk; Bram Nauta

    2004-01-01

    A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a

  5. Standard CMOS piezoresistive sensor to quantify heart cell contractile forces

    Microsoft Academic Search

    Gisela Lin; Kristofer S. J. Pister; Kenneth P. Roos

    1996-01-01

    A MEMS force transducer system, with a volume less than one cubic millimeter, is being developed to measure forces generated by living, isolated cardiac muscle cells. Cell attachment and measurement of contractile forces have been demonstrated with prototype hinged polysilicon devices. A new transducer system has been fabricated using a standard CMOS process with a post-processing XeF2 etch step. The

  6. Nano\\/CMOS architectures using a field-programmable nanowire interconnect

    Microsoft Academic Search

    Gregory S Snider; R Stanley Williams

    2007-01-01

    A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano\\/CMOS circuit architectures that generalizes the CMOL (CMOS\\/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components

  7. Sub1-V CMOS Image Sensor Using Time-Based Readout Circuit

    Microsoft Academic Search

    Kunhee Cho; Dongmyung Lee; Jeonghwan Lee; Gunhee Han

    2010-01-01

    This paper proposes a sub-1-V CMOS image sensor using a time-based readout (TBR) circuit. The proposed TBR circuit senses the moment of event from the pixel instead of reading the voltage signal. This allows the use of low power-supply voltage in pixel, providing sufficient dynamic range. The prototype chip was fabricated with a 0.13- m standard CMOS logic process, and

  8. Low power CMOS electronic central pattern generator design for a biomimetic underwater robot

    Microsoft Academic Search

    Young-jun Lee; Jihyun Lee; Kyung Ki Kim; Yong-bin Kim; Joseph Ayers

    2007-01-01

    This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electronic neurons based on Hindmarsh-Rose neuron dynamics and first order chemical synapses ls modeled. The controller is based on a standard CMOS process with 2V supply voltage. In order to achieve low power consumption, CMOS

  9. A 4044 Gb\\/s 3 Oversampling CMOS CDR\\/1:16 DEMUX

    Microsoft Academic Search

    Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker

    2007-01-01

    A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb\\/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking\\/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and

  10. CMOS LC Voltage-Controlled Oscillator Design Using Multiwalled Carbon Nanotube Wire Inductor

    Microsoft Academic Search

    A. Srivastava; Y. Xu; Y. Liu; A. K. Sharma; C. Mayberry

    2010-01-01

    A new CMOS LC voltage-controlled oscillator (VCO) circuit design using multiwalled carbon nanotube (MWCNT) wire inductor in LC tank circuit is presented. The VCO is designed in TSMC 0.18 ?m CMOS process. We have applied our recently reported one-dimensional fluid electronic transport model of multiwalled carbon nanotube interconnect in ?-model of the inductor. We have studied the oscillation frequency and

  11. Integration of a high-Q spiral inductor into an existing digital CMOS backend

    Microsoft Academic Search

    John D. Butler; Clay Crouch

    1999-01-01

    A spiral inductor is integrated into an existing CMOS triple layer backend process. To obtain a high quality factor `Q' for the inductor the existing one micron thick metal 3 process was replaced by a three micron thick metal process. The necessary process modifications to integrate this thicker metal process are presented.

  12. A CMOS vision system on-chip with multicore sensory processing architecture for image analysis above 1,000F/s

    NASA Astrophysics Data System (ADS)

    Rodrguez-Vzquez, Angel; Domnguez-Castro, Rafael; Jimnez-Garrido, Francisco; Morillas, Sergio

    2010-01-01

    This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand's frame-per-second rate. The chip employs a distributed processing architecture with a pre-processing stage consisting of an array of programmable sensory-processing cells, and a post-processing stage consisting of a digital microprocessor. The pre-processing stage operates as a retina-like sensor front-end. It performs parallel processing of the images captured by the sensors which are embedded together with the processors. This early processing serves to extract image features relevant to the intended tasks. The front-end incorporates also smart read-out structures which are conceived to transmit only these relevant features, thus precluding full gray-scale frames to be coded and transmitted. The chip is capable to close action-reaction loops based on the analysis of visual flow at rates above 1,000F/s with power budget below 1W peak. Also, the incorporation of processors close to the sensors enables signal-dependent, local adaptation of the sensor gains and hence highdynamic range signal acquisition.

  13. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    NASA Astrophysics Data System (ADS)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Faur, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  14. Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

    NASA Astrophysics Data System (ADS)

    Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

    2013-12-01

    Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

  15. Highly linear voltage-controlled CMOS transconductors

    Microsoft Academic Search

    S. Szczepanski; A. Wyszynski; Rolf Schaumann

    1993-01-01

    A circuit technique for realizing voltage-tunable linear high-frequency CMOS transconductor cells that use two cross-coupled MOS or CMOS transistor pairs operating at saturation is described. The tuning capabilities attained with an adjustable CMOS voltage source are examined. Design trade-offs between linearity and bandwidth are discussed, and a simple operational transconductance amplifier (OTA) example is simulated via SPICE. The simulation results

  16. A 3.4pJ FeRAM-enabled D flip-flop in 0.13m CMOS for nonvolatile processing in digital systems

    E-print Network

    Qazi, Masood

    Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance ...

  17. A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

    PubMed

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  18. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  19. Smart CMOS image sensor for lightning detection and imaging.

    PubMed

    Rolando, Sbastien; Goiffon, Vincent; Magnan, Pierre; Corbire, Franck; Molina, Romain; Tulet, Michel; Brart-de-Boisanger, Michel; Saint-P, Olivier; Guiry, Saprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

  20. A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13 CMOS process

    Microsoft Academic Search

    Dan Stiurca

    2005-01-01

    A high performance, fully differential line driver for use in gigabit and fast Ethernet over unshielded twisted pair CAT-5 copper cables is presented. By using a negative feedback based technique and an on-chip calibration engine to compensate for process variations, the 100-ohm output impedance is synthesized. To date, this is the single industrial realization of a gigabit\\/fast Ethernet line driver

  1. Process dependent antenna ratio rules for HSQ and FSG back-ends of (embedded flash) 0.18 ?m CMOS technology

    Microsoft Academic Search

    A. Scarpa; M. Diekema; C. van der Schaar; H. Valk; A. Harke; F. G. Kuper

    2002-01-01

    The charging damage induced by the inter-metal dielectric deposition in a hydrogen silsequioxane (HSQ) and in a fluorinated-silica glass (FSG) now are compared in a worst case scenario experiment, carried out in a 0.18 ?m embedded flash process. It is shown that different charging damage mechanisms take place in the two flows, calling for different definitions of antenna ratios and

  2. A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual\\/tripe gate oxide process

    Microsoft Academic Search

    Shien-Yang Wu; J. J. Liaw; C. Y. Lin; M. C. Chiang; C. K. Yang; J. Y. Cheng; M. H. Tsai; M. Y. Liu; P. H. Wu; C. H. Chang; L. C. Hu; C. I. Lin; H. F. Chen; S. Y. Chang; S. H. Wang; P. Y. Tong; Y. L. Hsieh; K. H. Pan; C. H. Hsieh; C. H. Chen; C. H. Yao; T. L. Lee; C. W. Chang; H. J. Lin; S. C. Chen; J. H. Shieh; S. M. Jang; K. S. Chen; Y. Ku; Y. C. See; W. J. Lo

    2009-01-01

    For the first time, we present good yielding 64 Mb SRAM test-chip with the smallest cell using dual\\/triple gate oxide process flow in 28 nm node. The low power technology platform continues scaling trend and extends SiON\\/poly technology beyond 32 nm node with gate density of 2.3times higher than that of 45 nm, and integrates high density (0.127 um2) and

  3. An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 ?m CMOS process

    Microsoft Academic Search

    A. Gerosa; A. Novo; A. Neviani

    2001-01-01

    This work explores the feasibility of a cardiac pacemaker front-end, realized using a fully integrated solution. Particularly two different architectures for the sensing chain are compared. The first is based on an SC biquadratic cell and performs the minimum signal processing required, i.e. a band-pass filtering before peak detection. The second is based on a ?? converter, allowing for more

  4. TFSOI CMOS technology for sub-1 V microcontroller circuits

    Microsoft Academic Search

    W. M. Huang; K. Papworth; M. Racanelli; J. P. John; J Foerrstner; H. C. Shin; B. Y. Hwang; T. Wetteroth; S. Hong; S. Wilson; S. Cheng

    1995-01-01

    For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 ?m process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than

  5. Development of a silicon gate CMOS technology with small structures

    NASA Astrophysics Data System (ADS)

    Milosevic, I.; Tilenschi, L.; Luft, R.; Cornwell, D.

    1982-09-01

    The development of HCMOS technology for 3 to 4 microns structures in order to improve packing density and performance for very large scale integration CMOS circuits, operating at 1,5V, is outlined. Design rule definition, photolithography/contact and projection, layout techniques, and process development (high value polysilicon resistors) are discussed. The technology developed was successfully demonstrated on an advanced 4 MHz (1,5V) watch circuit.

  6. Linearization Technique for Source-Degenerated CMOS Differential Transconductors

    Microsoft Academic Search

    Pietro Monsurro; Salvatore Pennisi; Giuseppe Scotti; Alessandro Trifiletti

    2007-01-01

    A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased

  7. A low noise, 2.0 GHz CMOS VCO design

    Microsoft Academic Search

    Kuo-Hsing Cheng; Shu-Chang Kuo; Chia-Ming Tu

    2003-01-01

    In this paper, a new delay cell of the voltage-controlled oscillator (VCO) is proposed. The circuit is designed and fabricated in TSMC 0.25?m Ip5m CMOS process with a 2.5 V supply voltage. It utilizes the skill that decreases the transient time to achieve the wider operating frequencies, lower phase noise and lower power supply noise. The structure of the VCO

  8. CMOS pulse-code-modulation voice codec

    Microsoft Academic Search

    G. Smarandoiu; D. A. Hodges; P. R. Gray; G. F. Landsburg

    1978-01-01

    A standard CMOS technology has been employed in LSI realization of a pulse-code-modulation (PCM) encoder and decoder for per-channel applications in telephony. Innovations in the design of an operational amplifier, a comparator, and precision-ratioed capacitor arrays, all in standard CMOS, are reported.

  9. CMOS pixels for subretinal implantable prothesis

    Microsoft Academic Search

    M. Mazza; P. Renaud; D. C. Bertrand; A. M. Ionescu

    2005-01-01

    This work reports on the design, fabrication, and characterization of CMOS pixels for subretinal implants, which seems to be an effective way to recover visual capabilities in some types of blindness. Two possible approaches are presented for CMOS pixel implementation: 1) an approach based on a light-controlled oscillator (LICOS) using a ring oscillator with an odd number of inverters and

  10. JPL CMOS Active Pixel Sensor Technology

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  11. Non-stationary noise responses of some fully differential on-chip readout circuits suitable for CMOS image sensors

    Microsoft Academic Search

    Y. Degerli; F. Lavernhe; P. Magnan; J. Farre

    1999-01-01

    CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1\\/f?-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-?m single polysilicon\\/double metal process,

  12. All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

    Microsoft Academic Search

    Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

    2004-01-01

    We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

  13. Static power saving TTL-to-CMOS input buffer

    NASA Astrophysics Data System (ADS)

    Yoo, Changsik; Kim, Min-Kyu; Kim, Wonchan

    1995-05-01

    This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 micron CMOS process, and the through current is measured to be only 8.9 mu A and 11.7 mu A for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output up to 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation (left bracket) 1 (right bracket).

  14. Thermally controlled electrochemical CMOS microsystem for protein array biosensors.

    PubMed

    Liu, Xiaowen; Li, Lin; Mason, Andrew J

    2014-02-01

    Because many proteins useful in biosensors exhibit temperature dependent activity, this paper explores the opportunity to integrate thermal control within a protein array biosensor microsystem. A CMOS microhotplate array tailored to protein interfaces was developed for thermoregulation in a liquid sample environment. The microhotplates were shown to provide suitable thermal control for biosensor temperature ranges without the process complexity of most previously reported microhotplates. When combined with a CMOS analog thermal controller, the on-chip array was shown to set and hold temperatures for each protein site within 1() C, and array elements were found to be almost completely thermally isolated from each other at distances beyond 0.4 mm. The compact size and low power of this controller enable it to be combined with the thermal control structures and instantiated for every element in a sensor array to increase biosensor interrogation throughput. PMID:24681917

  15. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 m process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  16. Diffuse reflectance measurements using lensless CMOS imaging chip

    NASA Astrophysics Data System (ADS)

    Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

    2014-10-01

    To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 ?m thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

  17. Development of a 0.75 micron wavelength, all-silicon, CMOS-based optical communication system

    NASA Astrophysics Data System (ADS)

    Snyman, Lukas W.; Ogudo, Kingsley A.; Foty, Daniel

    2011-01-01

    The utilization of Organic Light Emitting Diodes (OLEDs) and Si Avalanche LEDs emitting at 0.45 - 0.75 micron enable the development of high speed all -Silicon CMOS based optical communication systems without the incorporation of materials such as Ge or III-V components. The development of low loss and high curvature optical waveguides in CMOS technology at these wavelengths, however, offers major challenges. Advanced optical simulation software was hence used in order to develop effective CMOS based waveguides, using CMOS materials characteristics, processing parameters, and the spectral characteristics of CMOS Av LEDs. The analyses show that both silicon nitride and Si oxi-nitride offer good viability for developing such waveguides, utilizing 0.2 to 1.5 micron wide CMOS over-layer as well as trench-based technology. Particularly, trench based technology are very attractive, since the optical sources can then be integrated with silicon avalanche based LEDs with trench-based waveguides on the same plane with standard CMOS processing procedures. Effective single mode wave-guiding with calculated loss characteristics of 0.65 dB.cm-1 and modal dispersion characteristics of 0.2 ps.cm-1 and with a bandwidth-length product of higher than 100 GHz-cm are predicted.

  18. Organic thin-film transistors for flexible CMOS integration

    NASA Astrophysics Data System (ADS)

    Perez, Michael Ramon

    In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

  19. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    PubMed Central

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  20. Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays

    PubMed Central

    Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

    2009-01-01

    We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 ?m 30 ?m. The devices exhibited sensitivity of 6.2 ?C/Rcm2 with corresponding dark current of ?2.7 nA/cm2, and a 80 ?m FWHM planar image response to a 50 ?m slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 ?m spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 ?m), fast readout speeds (8 fps for a 32003200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

  1. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 A/m for n-type 149 A/m for p-type), low off-leakage current (28.1 pA/m for n-type and 79.6 pA/m for p-type), and excellent onoff ratio (1 107 for n-type and 2 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10?1310?11 m2/Hz for n-type and 10?1210?10 m2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  2. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  3. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

  4. Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors

    Microsoft Academic Search

    J. Ramirez-Angulo; R. G. Carvajal; J. Tombs; A. Torralba

    2001-01-01

    A scheme for low-voltage CMOS op-amp operation with rail-to-rail input and output signal swing and constant gm is presented. Single-ended and fully differential versions are discussed. The scheme is based on the use of multiple-input floating-gate transistors and allows direct implementation of linear weighted addition of continuous-time signals. Simulations are presented that verify the scheme operating with a 1.2-V single

  5. 100 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 53, NO. 2, FEBRUARY 2006 A Low-Power CMOS Analog Multiplier

    E-print Network

    Chen, Chunhong

    these designs is to use electronic devices to process the input signals, followed by a cancellation A Low-Power CMOS Analog Multiplier Chunhong Chen, Senior Member, IEEE, and Zheng Li Abstract--A multiplier is an important component for many analog applications. This paper presents a low power CMOS

  6. A CMOS 18 THz? 248 Mb\\/s transimpedance amplifier and 155 Mb\\/s LED-driver for low cost optical fiber links

    Microsoft Academic Search

    Mark Ingels; Geert Van der Plas; Jan Crols; Michel Steyaert

    1994-01-01

    The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 ?m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is

  7. A 64 single photon avalanche diode array in 0.18 m CMOS standard technology with versatile quenching circuit for quick prototyping

    NASA Astrophysics Data System (ADS)

    Uhring, Wilfried; Le Normand, Jean-Pierre; Zint, Virginie; Dumas, Norbert; Dadouche, Foudil; Malasse, Imane; Scholz, Jeremy

    2012-04-01

    Several works have demonstrated the successfully integration of Single-photon avalanche photodiodes (SPADs) operating in Geiger mode in a standard CMOS circuit for the last 10 years. These devices offer an exceptional temporal resolution as well as a very good optical sensitivity. Nevertheless, it is difficult to predict the expected performances of such a device. Indeed, for a similar structure of SPAD, some parameter values can differ by two orders of magnitude from a technology to another. We proposed here a procedure to identify in just one or two runs the optimal structure of SPAD available for a given technology. A circuit with an array of 64 SPAD has been realized in the Tower-Jazz 0.18 ?m CMOS image sensor process. It encompasses an array of 8 different structures of SPAD reproduced in 8 diameters in the range from 5 ?m up to 40 ?m. According to the SPAD structures, efficient shallow trench insulator and/or P-Well guard ring are used for preventing edge breakdown. Low dark count rate of about 100 Hz are expected thanks to the use of buried n-well layer and a high resistivity substrate. Each photodiode is embedded in a pixel which includes a versatile quenching circuitry and an analog output of its cathode voltage. The quenching system is configurable in four operation modes; the SPAD is disabled, the quenching is completely passive, the reset of the photodiode is active and the quenching is fully active. The architecture of the array makes possible the characterization of every single photodiode individually. The parameters to be measured for a SPAD are the breakdown avalanche voltage, the dark count rate, the dead time, the timing jitter, the photon detection probability and the after-pulsing rate.

  8. A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Degerli, Y.; Guilloux, F.; Orsini, F.

    2014-05-01

    With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 ?m CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

  9. High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology

    Microsoft Academic Search

    Min Park; Seonghearn Lee; Hyun Kyu Yu; Jin Gun Koo; Kee Soo Nam

    1997-01-01

    The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate

  10. A high frame rate, 16 million pixels, radiation hard CMOS sensor

    NASA Astrophysics Data System (ADS)

    Guerrini, N.; Turchetta, R.; Van Hoften, G.; Henderson, R.; McMullan, G.; Faruqi, A. R.

    2011-03-01

    CMOS sensors provide the possibility of designing detectors for a large variety of applications with all the benefits and flexibility of the widely used CMOS process. In this paper we describe a novel CMOS sensor designed for transmission electron microscopy. The overall design consists of a large 61 63 mm2 silicon area containing 16 million pixels arranged in a 4K 4K array, with radiation hard geometry. All this is combined with a very fast readout, the possibility of region of interest (ROI) readout, pixel binning with consequent frame rate increase and a dynamic range close to 12 bits. The high frame rate has been achieved using 32 parallel analogue outputs each one operating at up to 20 MHz. Binning of pixels can be controlled externally and the flexibility of the design allows several possibilities, such as 2 2 or 4 4 binning. Other binning configurations where the number of rows and the number of columns are not equal, such as 2 1 or 2 4, are also possible. Having control of the CMOS design allowed us to optimise the pixel design, in particular with regard to its radiation hardness, and to make optimum choices in the design of other regions of the final sensor. An early prototype was also designed with a variety of geometries in order to optimise the readout structure and these are presented. The sensor was manufactured in a 0.35 ?m standard CMOS process.

  11. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

  12. CMOS on FZ-high resistivity substrate for monolithic integration of SiGe-RF-circuitry and readout electronics

    Microsoft Academic Search

    Dietmar Beck; Michael Herrmann; Erich Kasper

    1997-01-01

    The choice of a highly resistive substrate for silicon millimeter-wave integrated circuits (SIMMWIC) imposed by the requirement of low RF-substrate losses requires the adaptation of a CMOS process on float zone silicon (FZ). A comparison of n- and p-channel devices realized on high resistivity substrate (p-type, 5000 ?cm) and standard CMOS substrates (CZ, n-type, 4-6 ?cm) is given. Using careful

  13. A quasi-passive CMOS pipeline D/A converter

    NASA Technical Reports Server (NTRS)

    Wang, Fong-Jim; Temes, Gabor C.; Law, Simon

    1989-01-01

    A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.

  14. A CMOS-compatible compact display

    E-print Network

    Chen, Andrew R. (Andrew Raymond)

    2005-01-01

    Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

  15. A scalable neural chip with synaptic electronics using CMOS integrated memristors.

    PubMed

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-09-27

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. PMID:23999447

  16. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    NASA Astrophysics Data System (ADS)

    Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

    2013-09-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  17. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    NASA Astrophysics Data System (ADS)

    Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

    2013-12-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 ? cm, which is at least one order of magnitude greater than the typical value (1-10 ? cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

  18. A complementary MOS process

    NASA Technical Reports Server (NTRS)

    Jhabvala, M. D.

    1977-01-01

    The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.

  19. Neutron spectrum and dose in a CMOS

    NASA Astrophysics Data System (ADS)

    Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

    2012-10-01

    Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

  20. CMOS scaling into the nanometer regime

    Microsoft Academic Search

    Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

    1997-01-01

    Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

  1. Latch-up CMOS/EPI devices

    SciTech Connect

    Chapuis, T. (Centre National d'Etudes Spatiales, 18 Av. Edouard Belin, 31055 Toulouse Cedex (FR)); Erems, H.C. (Z.I. Flourens, 31130 Balma (FR)); Rosier, L.H. (Inst. de Physique Nucleaire, BP 1-91406, Orsay Cedex (FR))

    1990-12-01

    New space projects tend to use more and more VLSI circuits manufactured in CMOS technology. Assessment of latch-up sensitivity is mandatory in the evaluation plan of a component, and in some cases the result could be considered as a GO/NOGO parameter. The authors present data on several CMOS/EPI devices demonstrating the non-efficiency of an epitaxial layer to achieve latch-up immunity for some latest technologies.

  2. CMOS compatible avalanche photodetector and its application in communications

    NASA Astrophysics Data System (ADS)

    Tang, Miangang; Wu, Zhigang; Li, Guohui

    2014-11-01

    CMOS compatible avalanche photodiodes (CMOS APDs) can be fabricated with standard CMOS technology, which make CMOS APDs are considered as a key optoelectronic device for optical communication systems and optical wireless communication systems. The guard-ring (GR) structure in CMOS APDs can alleviate the premature edge breakdown (PEB) effects and greatly improve the device performance. In this paper, the influence of various type GR structure on CMOS APDs performance are discussed, and its important applications in radio-over-fibre (RoF) are reviewed.

  3. A CMOS image sensor with stacked photodiodes for lensless observation system of digital enzyme-linked immunosorbent assay

    NASA Astrophysics Data System (ADS)

    Takehara, Hironari; Miyazawa, Kazuya; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Kim, Soo Hyeon; Iino, Ryota; Noji, Hiroyuki; Ohta, Jun

    2014-01-01

    A CMOS image sensor with stacked photodiodes was fabricated using 0.18 m mixed signal CMOS process technology. Two photodiodes were stacked at the same position of each pixel of the CMOS image sensor. The stacked photodiodes consist of shallow high-concentration N-type layer (N+), P-type well (PW), deep N-type well (DNW), and P-type substrate (P-sub). PW and P-sub were shorted to ground. By monitoring the voltage of N+ and DNW individually, we can observe two monochromatic colors simultaneously without using any color filters. The CMOS image sensor is suitable for fluorescence imaging, especially contact imaging such as a lensless observation system of digital enzyme-linked immunosorbent assay (ELISA). Since the fluorescence increases with time in digital ELISA, it is possible to observe fluorescence accurately by calculating the difference from the initial relation between the pixel values for both photodiodes.

  4. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  5. Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

    NASA Astrophysics Data System (ADS)

    Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 ?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

  6. New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications

    NASA Astrophysics Data System (ADS)

    Zhou, Wei; Hart, Darcy

    2013-09-01

    Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.

  7. Second Generation Monolithic Full-depletion Radiation Sensor with Integrated CMOS Circuitry

    SciTech Connect

    Segal, J.D.; Kenney, C.J.; /SLAC; Parker, S.I.; /Hawaii U.; Aw, C.H.; /UOB Ventiure Management, Singapore; Snoeys, W.J.; /CERN; Wooley, B.; Plummer, J.D.; /Stanford U., Elect. Eng. Dept.

    2011-05-20

    A second-generation monolithic silicon radiation sensor has been built and characterized. This pixel detector has CMOS circuitry fabricated directly in the high-resistivity floatzone substrate. The bulk is fully depleted from bias applied to the backside diode. Within the array, PMOS pixel circuitry forms the first stage amplifiers. Full CMOS circuitry implementing further amplification as well as column and row logic is located in the periphery of the pixel array. This allows a sparse-field readout scheme where only pixels with signals above a certain threshold are readout. We describe the fabrication process, circuit design, system performance, and results of gamma-ray radiation tests.

  8. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  9. Optimal design of phase change random access memory based on 130nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Cai, Daolin; Chen, Houpeng; Wang, Qian; Hong, Xiao; Chen, Yifeng; Xu, Linhai; Li, Xi; Wang, Zhaomin; Zhang, Yiyun; Song, Zhitang

    An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.

  10. Effectiveness of CMOS charge reflection barriers in space radiation environments

    NASA Astrophysics Data System (ADS)

    McNulty, P. J.; Lynch, J. E.; Abdel-Kader, W. G.

    1987-12-01

    Single-event upsets in microelectronic circuits follow the collection of more than some critical amount of charge at certain reverse-biased junctions. Reducing charge collection at the junctions lowers the upset rate without requiring performance tradeoff. Three mechanisms for reducing the fraction of charge collected at a junction can be incorporated in the use of CMOS-type wells. For illustration, the CHMOS-III-D process used in Intel's P51C256 is shown to lower the error rate to be expected in deep space by an order of magnitude from that calculated for an equivalent dynamic RAM of standard design.

  11. Measurements with a CMOS pixel sensor in magnetic fields

    NASA Astrophysics Data System (ADS)

    de Boer, W.; Bartsch, V.; Bol, J.; Dierlamm, A.; Grigoriev, E.; Hauler, F.; Herz, O.; Jungermann, L.; Koppenhfer, M.; Sopczak, A.; Schneider, Th.

    2002-07-01

    CMOS technique, which is the standard process used by most of the semiconductor factories worldwide, allows the production of both cheap and highly integrated sensors. The prototypes MIMOSA -I and MIMOSA-II were designed by the IReS-LEPSI collaboration in order to investigate the potential of this new technique for charged particle tracking (Design and Testing of Monolithic Active Pixel Sensors for Charged Particle Tracking, LEPSI, IN2P3, Strasbourg, France). For this purpose it is necessary to study the effects of magnetic fields as they appear in high-energy physics on these sensors. MIMOSA: Minimum Ionizing particle MOS Active pixel sensor.

  12. Silicon nanowires integrated with CMOS circuits for biosensing application

    NASA Astrophysics Data System (ADS)

    Jayakumar, G.; Asadollahi, A.; Hellstrm, P.-E.; Garidis, K.; stling, M.

    2014-08-01

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  13. A novel CMOS-compatible high-voltage transistor structure

    NASA Astrophysics Data System (ADS)

    Parpia, Zahir; Salama, C. Andre T.; Mena, Jose G.

    1986-12-01

    A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is described. This device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in current density compared to the lateral DMOS. A simple technique by which the switching speeds of the IBT can be improved by almost an order of magnitude without significantly compromising its current carrying capability is also presented.

  14. Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor

    NASA Astrophysics Data System (ADS)

    Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

    2014-09-01

    A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35??m CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35?dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 ?-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10?k?, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0 pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

  15. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  16. CMOS image sensors: electronic camera-on-a-chip

    Microsoft Academic Search

    Eric R. Fossum

    1997-01-01

    CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed

  17. Integration of CMOS, single electron transistors, and quantumdot cellular automata

    Microsoft Academic Search

    Aaron A. Prager; Alexei O. Orlov; Gregory L. Snider

    2009-01-01

    The physical limits associated with CMOS devices require the development of new computational architectures. Quantum-dot cellular automata (QCA) offers a low power, high-speed computational architecture. This paper demonstrates the integration of CMOS, QCA, and SET technologies on a single silicon die. A capacitive voltage divider is used to reduce standard CMOS logic voltage levels to millivolt control voltages for a

  18. Cascode voltage switch logic: A differential CMOS logic family

    Microsoft Academic Search

    L. Heller; W. Griffin; J. Davis; N. Thoma

    1984-01-01

    A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

  19. Technology and device scaling considerations for CMOS imagers

    Microsoft Academic Search

    Hon-Sum Wong

    1996-01-01

    This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from standard CMOS technologies. The

  20. CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems

    E-print Network

    Rincon-Mora, Gabriel A.

    CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems Rajiv Damodaran Prabha, and radiation, photovoltaic (PV) systems are appealing options. Still, chip-sized CMOS PV cells produce only well in substrate cell are better. Index Terms--Ambient light energy, harvester, CMOS photovoltaic (PV

  1. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  2. Single event effects in static and dynamic registers in a 0.25 ?m CMOS technology

    Microsoft Academic Search

    F. Faccio; K. Kloukinas; A. Marchioro; T. Calin; J. Cosculluela; M. Nicolaidis; R. Velazco

    1999-01-01

    We have studied single event effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used guardrings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve

  3. 0.1 ?m CMOS devices using low-impurity-channel transistors (LICT)

    Microsoft Academic Search

    M. Aoki; T. Ishii; T. Yoshimura; Y. Kiyota; S. Iijima; T. Yamanaka; T. Kure; K. Ohyu; T. Nishida; S. Okazaki; K. Seki; K. Shimohigashi

    1990-01-01

    Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 ?m CMOS devices. Attention is given to device fabrication criteria, key process technologies used, and the features achieved using LICTs

  4. RF subsystems implemented in mainstream CMOS - Overcoming special concerns affecting performance and cost

    Microsoft Academic Search

    J. E. Brewer; L. Gao; A. Sugavanam; J.-J. Lin; Y. Su; C. Cao; Y.-P. Ding; A. Verma; X. Yang; Z. Li; H. Wu; M.-H. Hwang; S.-H. Hwang; R. Bashrullah; R. Fox; D. Taubenheim; P. Corday; F. Martin; K. K. O

    2006-01-01

    Research is underway to explore the feasibility of implementing complete RF subsystems in standard mainstream CMOS processes without a need for any off-chip components. Progress to date has verified that RF circuits and on-chip antennas adequate for chip to chip communication can be realized, and it can be stated with some certainty that feasibility has been established. Radio architecture, signaling

  5. Monolithic expandable 6 bit 20 MHz CMOS\\/SOS A\\/D converter

    Microsoft Academic Search

    ANDREW G. F. DINGWALL

    1979-01-01

    Standard process CMOS\\/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A\\/D converter. Two chips may be interconnected in a series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates. Design factors and accuracy requirements are reviewed.

  6. Low-Voltage CMOS Temperature Sensor Design Using Schottky Diode-Based References

    E-print Network

    Baker, R. Jacob

    Low-Voltage CMOS Temperature Sensor Design Using Schottky Diode-Based References Curtis Cahoon-delta temperature sensor using Schottky diode-based current references as a replacement for the traditional PN junction diode-based current references. This sensor was designed using the AMI 0.5um process through

  7. Hybridization of a sigma-delta-based CMOS hybrid detector Kolb, K.E.a

    E-print Network

    Figer, Donald F.

    of aluminum bonding pads, Intermetallic layer, and the indium or Gold/Tin bump bond in between. #12Hybridization of a sigma-delta-based CMOS hybrid detector Kolb, K.E.a ; Stoffel, N.C.c , Douglas, B Technology Center, and Jet Process Corporation developed a hybrid silicon detector with an on-chip sigma

  8. An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems

    Microsoft Academic Search

    J. Christiansen

    1995-01-01

    This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process.

  9. A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits

    Microsoft Academic Search

    Jrg Langeheine; Joachim Becker; Simon Flling; Karlheinz Meier; Johannes Schemmel

    2001-01-01

    This paper describes and discusses an intrinsic approach to hardware evolution of analog electronic circuits using a Field Programmable Transistor Array (FPTA). The FPTA is fabricated in a 0:6 m CMOS process and consists of 16 16 transistor cells. The chip allows to configure the gate geometry as well as the connectivity of each of the 256 transistors. Evolutionary algorithms

  10. A CMOS soft-switched transconductor and its application in gain control and filters

    Microsoft Academic Search

    Clemens H. J. Mensink; Bram Nauta; Hans Wallinga

    1997-01-01

    This paper presents a transconductor suitable for implementation in submicron CMOS technology. The transconductor is nearly insensitive for the second-order effects of the MOS transistors, which become more and more prevalent in today's submicron processes. The transconductor relies on a differential pair with variable degeneration resistance, while the degeneration resistors are soft-switched by means of MOS transistors. The transconductance is

  11. 1GHz CMOS VCO design for wireless application using MEMS technology

    Microsoft Academic Search

    Amal Mohamed; Hamed Elsimary; Mohammed Ismail

    2000-01-01

    In this work, the design of RF VCO circuit, in which the oscillation frequency is controlled by a tunable capacitor based on microelectromechanical system (MEMS) technology is presented. The design of high Q-MEMS tunable capacitor has been accomplished through bulk micro machining with all metal micro structure. A standard CMOS process is used to carry out the fabrication of the

  12. A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING

    E-print Network

    Horiuchi, Timothy K.

    A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING T. Horiuchi 1 to facilitate spike-sorting and data reduction prior to transmission to a data-acquisition system. We have-speed digital signal processing (DSP) boards running spike-sorting software, this is not a scalable solution

  13. New package for CMOS sensors

    NASA Astrophysics Data System (ADS)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  14. Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS

    NASA Astrophysics Data System (ADS)

    Ressejac, Isabelle

    The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length 1000 mum and width 150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only 1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height up to a hundred times higher than its thickness. This natural deflection results from the relaxation of internal stresses inside the thin films which are part of the microactuator. These internal stresses are intrinsics to the host CMOS process. We have developed a model of the microactuator's initial deflection using mechanical properties of thin films and dimensions of the structure. Actuation experiments were performed in order to characterize the deflection of the microactuator with respect to the heating of the bilayers (separately and together). We have developed a thermal actuation analytical model for an n-layers multimorph structure, which takes into account the initial deflection resulting from the relaxation of stresses as well as the deflection due to the temperature increase during the electrothermal activation of the bilayers. (Abstract shortened by UMI.)

  15. Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

    PubMed Central

    Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5200 mT. PMID:24172287

  16. CMOS detectors at Rome "Tor Vergata" University

    NASA Astrophysics Data System (ADS)

    Berrilli, F.; Cantarano, S.; Egidi, A.; Giordano, S.

    The new class of CMOS panoramic detectors represents an innovative tool for the experimental astronomy of the forthcoming years. While current charge-coupled device (CCD) technology can produce nearly ideal detectors for astronomical use, the scientific quality CMOS detectors made today have characteristics similar to those of CCD devices but a simpler electronics and a reduced cost. Moreover, the high frame rate capability and the amplification of each pixel - active pixel - in a CMOS detector, allows the implementation of a specific data management. So, it is possible to design cameras with very high dynamic range suitable for the imaging of solar active regions. In fact, in such regions, the onset of a flare can produce problems of saturation in a CCD-based camera. In this work we present the preliminary result obtained with the Tor Vergata C-Cam APS camera used at the University Solar Station.

  17. Design and fabrication of a CMOS-compatible MHP gas sensor

    SciTech Connect

    Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao; Tang, Zhenan [College of Electronic Science and Technology, Dalian University of Technology, Dalian 116024 (China)] [College of Electronic Science and Technology, Dalian University of Technology, Dalian 116024 (China)

    2014-03-15

    A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ?19 mW and a rapid thermal response of 8 ms for heating up to 300 C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9/C.

  18. Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

    NASA Astrophysics Data System (ADS)

    Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

    2014-03-01

    We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 ?m pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 ?m pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

  19. IBM: Scaling CMOS to the Limit

    NSDL National Science Digital Library

    2002-01-01

    This is the latest issue of the IBM Journal of Research and Development. "This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached." Specifically, research teams report on topics such as silicon-on-insulator technology, new CMOS materials and device structures, dynamic random-access memory, and many others. The papers provide views of how far scaling could progress in the future and what constrains further advancement. Several back issues of the journal are also available, and each focuses on a different area of research.

  20. Optical addressing technique for a CMOS RAM

    NASA Technical Reports Server (NTRS)

    Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

    1988-01-01

    Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

  1. A single-chip 75 GHz\\/0.35 ?m SiGe BiCMOS W-CDMA homodyne transceiver for UMTS mobiles

    Microsoft Academic Search

    Wolfgang Thomann; Volker Thomas; Richard Hagelauer; Robert Weigel

    2004-01-01

    A single-chip, fully-integrated 3G UMTS\\/W-CDMA transceiver has been implemented in a standard 75-GHz\\/0.35 ?m SiGe BiCMOS process for use in FDD mobile terminals. The design comprises two integer-N\\/fractional-N synthesizers with fully integrated CMOS VCOs, on-chip tuning and PLL, a zero-IF receiver and a direct-conversion transmitter. The zero-IF receiver includes a differential-input, bipolar, low-noise amplifier (2nd LNA), a down-converter with CMOS

  2. CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr

    E-print Network

    Choi, Woo-Young

    #12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

  3. Incorporating Effects of Process, Voltage, and Temperature Variation in BTI Model for Circuit

    E-print Network

    Mahmoodi, Hamid

    Temperature Instability (BTI) is a major reliability issue in Nano-scale CMOS circuits. BTI effect results) dependence of BTI effect, and the significant amount of PVT variations in Nano-scale CMOS, we propose. Keywords- Aging effects; Nano-scale CMOS; Process variations; Voltage variations; Temperature variations I

  4. Failure analysis of a half-micron CMOS IC technology

    SciTech Connect

    Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S. [and others

    1996-08-01

    We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

  5. CMOS image sensors for subretinal implant system

    Microsoft Academic Search

    M. Mazza; D. Bertrand; P. Renaud; A. M. Ionescu

    2003-01-01

    Visual capabilities recovery for some kind of illness is possible through subretinal implantable device stimulation. Two possible approaches for retinal pixel are proposed, fabricated in 0.35?m CMOS, tested and compared including electronic response on a human tissue like interface. In these solutions, power consumption has been proved to he dominated by electrode stimulation and, in normal condition, typical consumption is

  6. Radiation Tolerance of 65nm CMOS Transistors

    E-print Network

    Krohn, M; Cumalat, J P; Wagner, S R; Christian, D C; Deptuch, G; Fahim, F; Hoff, J; Shenai, A

    2015-01-01

    We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  7. Radiation Tolerance of 65nm CMOS Transistors

    E-print Network

    M. Krohn; B. Bentele; J. P. Cumalat; S. R. Wagner; D. C. Christian; G. Deptuch; F. Fahim; J. Hoff; A. Shenai

    2015-01-23

    We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  8. Complementary Metal??Oxide??Semiconductor (CMOS) Simulation

    NSDL National Science Digital Library

    This resource is an Interactive Complementary metal??oxide??semiconductor (CMOS) simulation. All the different variables can be modified to represent different aspects of this simulation. Results are presented once the calculations are made. This can be a useful resource for those involved in engineering or physics.

  9. Switch level optimization for CMOS circuits

    E-print Network

    Chugh, Pankaj Pravinkumar

    1997-01-01

    In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

  10. Minimizing power consumption in digital CMOS circuits

    Microsoft Academic Search

    ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

    1995-01-01

    An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

  11. Heavy ion induced snapback in CMOS devices

    Microsoft Academic Search

    R. Koga; W. A. Kolasinski

    1989-01-01

    Single-event-snapback (SES) susceptibilities of selected CMOS devices to heavy ions were measured using N, Ne, Ar, Cu, and Kr ion beams. Like latchup, snapback was observed macroscopically by detecting the abnormally high bias current condition. However, the snapback susceptibility characteristics differed from those of latchup, and consequently it was possible to measure the snapback responses unambiguously. The responses are expressed

  12. Low energy CMOS for space applications

    NASA Astrophysics Data System (ADS)

    Panwar, Ramesh; Alkalaj, Leon

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  13. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

  14. High-Q CMOS-integrated photonic crystal microcavity devices

    PubMed Central

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10?s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,3009,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31?A/W), 3?GHz bandwidth, and 30?nA dark current at a reverse bias of 30?V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  15. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

  16. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

  17. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    PubMed Central

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  18. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 ?m 1 Poly 4 Metal CMOS process. The pixel size is 100 ?m100 ?m and the pixel array format is 2496 pixels, which provide a field-of-view (FOV) of 9.6 mm2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  19. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    PubMed

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-?m two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/?Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz. PMID:21859585

  20. 6.5 mW CMOS low noise amplifier at 1.9 GHz

    Microsoft Academic Search

    Shijun Yang; Ralph Mason; Calvin Plett

    1999-01-01

    A 1.9 GHz low noise amplifier has been designed in a standard CMOS .35 micron process. The amplifier provides a gain of 21 dB with a noise figure only 1.4 dB while drawing 6.5 mW from a 1.5 V supply. Detailed design process and simulation results are presented in this paper

  1. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ...COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products Containing Same...received a complaint entitled Certain CMOS Image Sensors and Products Containing Same...States after importation of certain CMOS image sensors and products containing...

  2. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ...Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same...States after importation of certain CMOS image sensors and products containing same...States after importation of certain CMOS image sensors and products containing...

  3. Correct CMOS IC defect models for quality testing

    NASA Technical Reports Server (NTRS)

    Soden, Jerry M.; Hawkins, Charles F.

    1993-01-01

    Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

  4. Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders from Optical Triangulation to the Automotive Field

    PubMed Central

    Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

    2008-01-01

    With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field.

  5. Heavy ion induced snapback in CMOS devices

    SciTech Connect

    Koga, R.; Kolasinski, W.A. (Space Sciences Lab., The Aerospace Corp., El Segundo, CA (US))

    1989-12-01

    Single event snapback (SES) susceptibilities of selected CMOS devices to heavy ions were measured, first using N, Ne, Ar, Cu and Kr ion beams. Like latchup, snapback was observed macroscopically by detecting the abnormally high bias current condition. However, the snapback susceptibility characteristics differed from those of latchup, and consequently the authors could unambiguously measure the snapback responses. The responses are expressed in terms of the cross-section for varying bias and the stopping power of ions. Test data indicate that CMOS devices with rather long channel lengths (on the order of three microns) are free from SES when operated at about 5 volts. However, present-day theories have predicted that this regenerative breakdown mode of upset may become very important at 5 volts or below for devices with extremely short n-channel lengths.

  6. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  7. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

  8. Analog Circuit Design in Nanoscale CMOS Technologies

    Microsoft Academic Search

    Lanny L. Lewyn; Trond Ytterdal; Carsten Wulff; Kenneth Martin

    2009-01-01

    As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic

  9. Extremely scaled silicon nano-CMOS devices

    Microsoft Academic Search

    Leland Chang; Yang-kyu Choi; Daewon Ha; PUSHKAR RANADE; Shiying Xiong; JEFFREY BOKOR; Tsu-Jae King

    2003-01-01

    Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key

  10. CMOS pixel for subretinal implantable prothesis

    Microsoft Academic Search

    M. Mazza; Philippe Renaud; A. M. Ionescu

    2003-01-01

    Visual capabilities recovery for some kind of illness is possible through subretinal implantable device stimulation. Two possible architectures for retinal pixel are proposed, fabricated in 0.35 ?m CMOS and compared, including evaluation of electronic response on a human-tissue-like interface. In these solutions, power consumption has been proved to be dominated by electrode stimulation and, in normal light condition, typical consumption

  11. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  12. New CMOS tunable transconductor for filtering applications

    Microsoft Academic Search

    G. Palmisano; Salvatore Pennisi

    2001-01-01

    A CMOS high-performance transconductor useful for IC filtering applications is presented. It is based on a feedback source-follower configuration using a resistor to achieve linear voltage-to-current conversion. Tunability is attained through variable-gain current mirrors. A balanced integrator was designed in a 0.8-?m technology and simulations are given which show tunability over a factor of 20 and THD of at most

  13. CMOS on local SOI using SIMOX technology

    Microsoft Academic Search

    S. Matsumoto; T. Ohno; K. Izumi

    1987-01-01

    A new local SOI technique using SIMOX technology has been developed. Using this technique, it is possible to implement SOI regions and bulk regions selectively on the same chip, starting from a conventional SIMOX substrate, and achieve a planar surface of the substrate. The electrical characteristics of CMOS devices composed of n-MOSFETs\\/bulk and p-MOSFETs\\/SIMOX fabricated with this technique are described.

  14. Battery-powered digital CMOS design

    Microsoft Academic Search

    Massoud Pedram; Qing Wu

    1999-01-01

    In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and

  15. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    PubMed Central

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  16. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    NASA Astrophysics Data System (ADS)

    Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  17. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  18. A -68.5dB IM3 Low-Voltage CMOS Transconductor with Wide Tuning Range

    NASA Astrophysics Data System (ADS)

    Lo, Tien-Yu; Hung, Chung-Chih; Lo, Chi-Hsiang

    A CMOS transconductor for multi-mode application is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier, which operates in the weak inversion region, provides a wide transconductance tuning range without degrading the linearity. The transconductor was designed and fabricated in the TSMC 0.18-m CMOS process. The results show the transconductance tuning ratio of 23 and the IM3 performance of -68.5dB.

  19. Design of a CMOS multi-mode GNSS receiver VCO

    NASA Astrophysics Data System (ADS)

    Qiang, Long; Yiqi, Zhuang; Yue, Yin; Zhenrong, Li

    2012-05-01

    A voltage-controlled oscillator (VCO) with dual stages of accumulation mode varactors for a multi-mode global navigation satellite system (GNSS) application, which adopts sigma-delta fractional-N technology in the synthesizer, is presented. The structure is selected to optimize the frequency coverage and tuning linearity, based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells, which cover the global positioning system (GPS) and Beidou (BD) bands. The VCO implemented in the 0.18 ?m CMOS process can cover the GPS L1, BD B1, B2 and B3 bands with sufficient margin, and exhibits low phase noise by using this tuning curve linearization technique. The equalized Kvco characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.

  20. A new visible watermarking technique applied to CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yu, Pingping; Shang, Yan; Li, Chunming

    2013-10-01

    This paper presents a new visible watermarking solution for CMOS image sensor which can enhance secure features of captured images. Visible watermarks are embedded in the Bayer format image data and can be transferred by the subsequent interpolation process. A piecewise function is setup based on the gray scale resolution characteristics of human eyes. Watermark stretch factor can be adaptively chosen according to the gray value of the current pixel. The advantage of this algorithm is that the watermark has the same visibility in different image brightness region. A number of color images have been used to test the method. In order to check the robustness of watermarked images, we conducted adding noise and filtering experiments, results show that the visibility of watermark is also good after the experiments. The approach allows a digital watermark to be embedded in an image immediately upon its capture, before leaving the imaging chip.

  1. Measurements on HV-CMOS Active Sensors After Irradiation to HL-LHC fluences

    E-print Network

    B. Ristic; for the ATLAS CMOS pixel collaboration

    2015-01-13

    During the long shutdown (LS) 3 beginning 2022 the LHC will be upgraded for higher luminosities pushing the limits especially for the inner tracking detectors of the LHC experiments. In order to cope with the increased particle rate and radiation levels the ATLAS Inner Detector will be completely replaced by a purely silicon based one. Novel sensors based on HV-CMOS processes prove to be good candidates in terms of spatial resolution and radiation hardness. In this paper measurements conducted on prototypes built in the AMS H18 HV-CMOS process and irradiated to fluences of up to $2\\cdot10^{16}\\,\\text{n}_\\text{eq}\\text{cm}^{-2}$ are presented.

  2. A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function

    NASA Astrophysics Data System (ADS)

    Tanaka, Hideki; Morie, Takashi; Aihara, Kazuyuki

    In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25m CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.

  3. Imaging performance comparison between CMOS and sCMOS detectors in a vibration test on large areas using digital holographic interferometry

    NASA Astrophysics Data System (ADS)

    Flores-Morenoa, J. M.; Torre I., Manuel H. De la; Aguayo, Daniel D.; Fernando Mendoza, S.

    2014-05-01

    A comparison of the interferometric imaging performance of two different cameras during a vibration study is presented. One of the cameras has a high speed CMOS sensor and the second one uses a high resolution (scientific) sCMOS sensor. This comparison is based on the interferometric response as a merit parameter of these sensors which is not a conventional procedure. Even when the current standard for image quality is on the signal to noise ratio calculations, an interferometric test to evaluate the fringe pattern visibility is equivalent to the contrast to noise ratio value. An out of plane digital holographic interferometer is used to test each camera once at the time with the same experimental conditions. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The sample is deformed by means of a controlled vibration induced by a tip ended linear step motor. Results from each camera are presented as the retrieved optical phase during the vibration. Finally, some conclusions based on the post processed images are presented suggesting a smoother optical phase obtained with the sCMOS camera.

  4. Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

    Microsoft Academic Search

    Ali Mesgarani; Mustafa N. Alam; F. Z. Nelson; Suat U. Ay

    2010-01-01

    This paper presents a technique called supply boosting for designing sub-1V analog\\/mixed-signal circuits. Supply boosting technique (SBT) is suitable for sub-micron CMOS processes containing MOSFET transistors with threshold voltages comparable to the supply voltage. SBT is based on the idea that if current consumption of the circuit block is very low, in the order of nanoamper, supply voltage could be

  5. A 300MHz 64-b quad-issue CMOS RISC microprocessor

    Microsoft Academic Search

    B. J. Benschneider; A. J. Black; W. J. Bowhill; S. M. Britton; D. E. Dever; D. R. Donchin; R. J. Dupcak; R. M. Fromm; M. K. Gowan; P. E. Gronowski; M. Kantrowitz; M. E. Lamere; S. Mehta; J. E. Meyer; R. O. Mueller; A. Olesin; R. P. Preston; D. A. Priore; S. Santhanam; M. J. Smith; G. M. Wolrich

    1995-01-01

    This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 ?m, CMOS process. The upper metal layers (metal-3 and metal-4), primarily

  6. A Fully-Integrated Quad-Band GSM\\/GPRS CMOS Power Amplifier

    Microsoft Academic Search

    Ichiro Aoki; Scott Kee; Rahul Magoon; Roberto Aparicio; Florian Bohn; Jeff Zachan; Geoff Hatcher; Donald McClymont; Ali Hajimiri

    2008-01-01

    Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed- loop power control and operates under supply voltages from 2.9 V to 5.5 V

  7. A high performance active pixel sensor with 0.18um CMOS color imager technology

    Microsoft Academic Search

    Shou-Gwo Wuu; Ho-Ching Chien; Dun-Nian Yaung; Chien-Hsien Tseng; C. S. Wang; Chin-Kung Chang; Yu-Kung Hsaio

    2001-01-01

    A high performance 0.18 um CMOS image sensor technology has been successfully developed and fully characterized. 3T active pixel sensor (APS) with non-silicide source\\/drain process is provided to reduce dark current and increase photoresponse. By optimizing photodiode junction profile with the appropriate thermal cycle, the dark current can be drastically reduced. Small pixel pitch 2.8um~4.0um demonstrates the low dark current

  8. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    NASA Technical Reports Server (NTRS)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  9. A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

    Microsoft Academic Search

    Masaki Kitsunezuka; Shinichi Hori; Tadashi Maeda

    2009-01-01

    This paper describes a reconfigurable analog baseband (ABB) for a software-defined radio (SDR). A wide variety of filter characteristics needed for SDR can be obtained by a reconfigurable filter based on a newly developed duty-cycle controlled discrete-time transconductor. The ABB, implemented in a 90 nm CMOS process, provides second- and fourth-order Butterworth, Chebyshev, and elliptic responses with bandwidths from 400

  10. 0.13-?m CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays

    Microsoft Academic Search

    Kwang-Jin Koh; Gabriel M. Rebeiz

    2007-01-01

    Two 4-bit active phase shifters integrated with all digital control circuitry in 0.13-mum RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter

  11. A 900MHz high efficiency and linearity adaptive CMOS power amplifier

    Microsoft Academic Search

    Jing Wang; Zhangfa Liu

    2011-01-01

    A high efficiency, linear, adaptive radio frequency (RF) power amplifier (PA) is presented. The working frequency is about 900MHz. The circuit employs a self-bias cascode for a higher performance and an adaptive bias to enhance linear and efficiency of the PA as well. This power amplifier is designed with the SMIC 0.18um CMOS RF process. The power supply is 1.8V.

  12. K- and Q-bands CMOS frequency sources with X-band quadrature VCO

    Microsoft Academic Search

    Sangsoo Ko; Jeong-Geun Kim; Taeksang Song; Euisik Yoon; Songcheol Hong

    2005-01-01

    Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-?m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To

  13. A Single-Chip Bluetooth EDR Device in 0.13?m CMOS

    Microsoft Academic Search

    B. Marholev; M. Pan; E. Chien; L. Zhang; R. Roufoogaran; S. Wu; I. Bhatti; T.-H. Lin; M. Kappes; S. Khorram; S. Anand; A. Zolfaghari; J. Castaneda; C. M. Chien; B. Ibrahim; H. Jensen; H. Kim; P. Lettieri; S. Mak; J. Lin; Y. C. Wong; R. Lee; M. Syed; M. Rofougaran; A. Rofougaran

    2007-01-01

    A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, a low-IF receiver and direct-conversion transmitter architecture. It is implemented in a 0.13mum CMOS process and occupies 11.8mm2. Sensitivity for 1, 2 and 3Mb\\/s rates is -88, -90, and -84dBm and transmitter differential EVM is 5.5% rms.

  14. A 40-to-44Gb\\/s 3?? Oversampling CMOS CDR\\/1:16 DEMUX

    Microsoft Academic Search

    N. Nedovic; N. Tzartzanis; H. Tamura; F. Rotella; M. Wiklund; Y. Mizutani; Y. Okaniwa; T. Kuroda; J. Ogawa; W. Walker

    2007-01-01

    A 3times oversampling CDR and 1:16 DEMUX occupies 0.8 times 1.8mm2 in a 90nm CMOS process. The chip operates at 40 to 44Gb\\/s and dissipates 0.91W. Input data is sampled using a 24-phase distributed VCO and a digital CDR recovers 16 bits and a 2.5GHz clock from 48 demultiplexed samples spanning 16UI. Conformance to the ITU G.8251 jitter tolerance mask

  15. 1.2 Gb\\/s SONET\\/SDH demux in CMOS technology

    Microsoft Academic Search

    F. L. Romao; J. N. Soares; R. Silveira; W. A. M. Van Noije

    1995-01-01

    This paper describes the design of a demux to meet the requirements of the SONET STS-24 (synchronous transport signal level 24) at a rate of 1.2 Gb\\/s, using a standard 0.8 ?m DLM CMOS process. True single phase clocked flip-flops sensitive on both clock edges and deep pipeline techniques are used in order to achieve such a clock rate. The

  16. A multi-format Blu-ray player SoC in 90nm CMOS

    Microsoft Academic Search

    Chi-Cheng Ju; Tsu-Ming Liu; Chih-Chieh Yang; Shih-Hung Lin; Kuo-Pin Lan; Chien-Hua Wu; Ting-Hsun Wei; Chi-Chin Lien; Jiun-Yuan Wu; Chih-Hao Hsiao; Te-Wei Chen; Yeh-Lin Chu; Guan-Yi Lin; Yung-Chang Chang; Kung-Sheng Lin; Chih-Ming Wang; Hue-Min Lin; Chia-Yun Cheng; Chun-Chia Chen; Chien-Hung Lin; Yung-Teng Lin; Shang-Ming Lee; Ya-Ching Yang; Yu-Lun Cheng; Chen-Chia Lee; Ming-Shiang Lai; Wen-Hua Wu; Ted Hu; Chao-Wei Tseng; Chen-Yu Hsiao; Wei-Liang Lee; Bo-Jiun Chen; Pao-Cheng Chiu; Shang-Ping Chen; Kun-Hsien Li; Kuan-Hua Chao; Chien-Ming Chen; Chuan-Cheng Hsiao; J. Ju; Wei-Hung Huang; Chi-Hui Wang; Hung-Sung Li; E. Su; J. Chen

    2009-01-01

    A Blue-ray Disc (BD) player, back-end SoC supporting multiple protection, video and display formats is fabricated in a 90 nm 1P7M CMOS process with a core area of 62.95 mm2. This SoC adopts a general copy protection (GCP) unit to integrate various kinds of protection algorithms (e.g. AES, CSS, CPPM\\/CPRM, DES, SHA-1\\/MD5), designs a dedicated memory management unit (MMU) for

  17. Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

    Microsoft Academic Search

    Beln Calvo; Santiago Celma; Maria Teresa Sanz; Juan Pablo Alegre; Francisco Aznar

    2008-01-01

    This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values.

  18. Implementation of New CMOS Differential Stacked Spiral Inductor for VCO Design

    Microsoft Academic Search

    Liang Lin; Wen-Yan Yin; Jun-Fa Mao; Yu-Yang Wang

    2007-01-01

    A new type of silicon-based differential stacked spiral inductor (DSSI) was proposed in this letter, which was successfully implemented in the design of a cross-coupled differential voltage-controlled oscillator (VCO). The samples of DSSI and VCO were fabricated using standard CMOS 0.18 mum process. Based on the two-port S-parameters measured using standard deembedding procedure, the self-resonance frequency (fsr ) and -factor

  19. Ultrafast all-optical temporal differentiators based on CMOS-compatible integrated-waveguide Bragg gratings.

    PubMed

    Rutkowska, K A; Duchesne, D; Strain, M J; Morandotti, R; Sorel, M; Azaa, J

    2011-09-26

    We report the first realization of integrated, all-optical first- and higher-order photonic differentiators operating at terahertz (THz) processing speeds. This is accomplished in a Silicon-on-Insulator (SOI) CMOS-compatible platform using a simple integrated geometry based on (?-)phase-shifted Bragg gratings. Moreover, we achieve on-chip generation of sub-picosecond Hermite-Gaussian pulse waveforms, which are noteworthy for applications in next-generation optical telecommunications. PMID:21996892

  20. GaN-Based Power LEDs With CMOS ESD Protection Circuits

    Microsoft Academic Search

    J. J. Horng; Y. K. Su; S. J. Chang; W. S. Chen; S. C. Shei

    2007-01-01

    A power light-emitting diode (LED) module has been successfully designed and demonstrated by combining GaN-based power LEDs with CMOS electrostatic discharge (ESD) protection circuits through a flip-chip process. It was found that we could enhance the power LED output intensity by 20% by using the flip-chip technology. Lifetimes of flip-chip power LEDs were also found to be better. It was

  1. A low-voltage CMOS DC-DC converter for a portable battery-operated system

    Microsoft Academic Search

    Anthony J. Stratakos; Seth R. Sanders; Robert W. Brodersen

    1994-01-01

    Motivated by emerging battery-operated applications that demand compact, lightweight, and highly efficient DC-DC power converters, a buck circuit is presented in which all active devices are integrated on a single chip using a standard 1.2 ? CMOS process. The circuit delivers 750 mW at 1.5 V from a 6 V battery. To effectively eliminate switching loss at high operating frequencies,

  2. A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS

    Microsoft Academic Search

    Neric Fong; Jean-Olivier Plouchart; N. Zamdmer; Duixian Liu; Lawrence Wagner; Calvin Plett; Gamy Tarr

    2002-01-01

    A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 ?m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (VDD) and 1

  3. A low-power CMOS neural amplifier with amplitude measurements for spike sorting

    Microsoft Academic Search

    Timothy K. Horiuchi; Thomas Swindell; David Sander; Pamela Abshire

    2004-01-01

    Integrated, low-power, low-noise CMOS neural amplifiers have recently grown in importance as large microelectrode arrays have begun to be practical. With an eye to a future where thousands of signals must be transmitted over a limited bandwidth link or be processed in situ, we are developing low- power neural amplifiers with integrated pre-filtering and measurements of the spike signal to

  4. 80 nm poly-Si gate CMOS with HfO2 gate dielectric

    Microsoft Academic Search

    C. Hobbs; H. Tseng; K. Reid; B. Taylor; L. Dip; L. Hebert; R. Garcia; R. Hegde; J. Grant; D. Gilmer; A. Franke; V. Dhandapani; M. Azrak; L. Prabhu; R. Rai; S. Bagchi; J. Conner; S. Backer; F. Dumbuya; B. Nguyen; P. Tobin

    2001-01-01

    We report here for the first time the formation of an amorphous oxide layer between the polysilicon gate and hafnium oxide (HfO2 ) gate dielectric due to a lateral oxidation mechanism at the gate edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv of 25 with

  5. Superior metal step coverage and dielectric quality in a simple two-level metal 1.0 ?m CMOS technology

    Microsoft Academic Search

    C. A. Fieber; E. P. Martin; H. Z. Chew; G. W. Hills; N. Selamoglu; S. A. Lytle

    1989-01-01

    A two-level metal process for a fourth-generation 1.0-?m CMOS technology has been developed which yields superior aluminum step coverages and high-quality dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and

  6. Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors

    E-print Network

    Johnson, Derek Wade

    2014-07-31

    -aligned contact process and the lack of a robust gate dielectric capable of enduring the contact module. The reported research began with the development of a Si-compatible baseline transistor technology in a 200mm Si CMOS environment and an exploration...

  7. A high-speed low-power 0.3 ?m CMOS gate array with variable threshold voltage (VT) scheme

    Microsoft Academic Search

    T. Kuroda; T. Fujita; T. Nagamatu; S. Yoshioka; T. Sei; K. Matsuo; Y. Hamura; T. Mori; M. Murota; M. Kakumu; T. Sakurai

    1996-01-01

    Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3 ?m CMOS technology whose performance is investigated. The gate array is

  8. Symmetrical spiral inductor design and optimization for VCO design in 0.35 mu;m CMOS technology

    Microsoft Academic Search

    Yeung-Bun Choi; Tee-Hui Teo; Huailin Liao

    2003-01-01

    Optimizing the quality factor for VCO (voltage control oscillator) application has the added advantages of reducing power consumption and improving the phase noise performance. This work conducts a comprehensive study on a family of symmetrical spiral inductors in standard digital 0.35 mu;m CMOS process. In addition to quality factor, inductor characteristics of interest include inductor value, peak frequency (frequency at

  9. The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

    PubMed Central

    Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

    2014-01-01

    Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

  10. The intersection of CMOS microsystems and upconversion nanoparticles for luminescence bioimaging and bioassays.

    PubMed

    Wei, Liping; Doughan, Samer; Han, Yi; DaCosta, Matthew V; Krull, Ulrich J; Ho, Derek

    2014-01-01

    Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

  11. CMOS phototransistor device : A total solution for skin whitening assays

    Microsoft Academic Search

    Yen-Pei Lui; Yu-Wei Chang; Ming-Yu Lin; Jiann-Shiun Kao; Yang-Tung Huang; Yuh-Shyong Yang

    2009-01-01

    Three skin whitening assays combining the semiconductor technology was demonstrated for screening the drug candidate and discussing the mechanisms of melanogenesis in medical cosmetics. We proposed a miniaturized photometric system using complementary metal oxide semiconductor (CMOS) phototransistor as a detector with high sensitivity. The CMOS phototransistor was a small, portable optoelectronic device with enlarged depletion region of the outer Nwell\\/Pwell

  12. GaAs MQW modulators integrated with silicon CMOS

    Microsoft Academic Search

    K. W. Goossen; J. A. Walker; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. D. Bacon; D. Dahringer; L. M. F. Chirovsky; A. L. Lentine; D. A. B. Miller

    1995-01-01

    We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 3232 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor

  13. Performance review of integrated CMOS VCO circuits for wireless communications

    Microsoft Academic Search

    M. Rachedine; D. Kaczman; A. Das; M. Shah; J. Mondal; C. Shurboff

    2003-01-01

    This paper reviews monolithically integrated CMOS voltage controlled oscillators (VCO) for wireless communications. The key challenges in VCO development include: design of a high Q tank on a substrate tailored for CMOS, multiband operation using a single VCO, enhanced manufacturability using digital frequency tuning, and optimization of the overall VCO topology for low power operation. Recent developments in each of

  14. RF power potential of 45 nm CMOS technology

    E-print Network

    Putnam, Christopher

    This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

  15. RTDCMOS Pipelined Networks for Reduced Power Consumption

    Microsoft Academic Search

    Juan Nez; Mara J. Avedillo; Jos M. Quintana

    2011-01-01

    The incorporation of resonant tunneling diodes (RTDs) into III\\/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced com- ponent count, and\\/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD- CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work

  16. A CMOS fault extractor for inductive fault analysis

    Microsoft Academic Search

    F. Joel Ferguson; John Paul Shen

    1988-01-01

    The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list

  17. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  18. Quiescent power supply current measurement for CMOS IC defect detection

    Microsoft Academic Search

    CHARLES F. HAWKINS; JERRY M. SODEN; RONALD R. FRITZEMEIER; LUTHER K. HORNING

    1989-01-01

    Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer

  19. A CMOS Imager for DNA Detection Samir Parikh

    E-print Network

    Chow, Paul

    University of Toronto Abstract DNA Microarrays are used to analyse the DNA sequence of an organism at each of the spots on a DNA microarray. This thesis examines the feasibility of using standard CMOS technology for imaging a DNA microarray. It explains the design of a CMOS Imager and the construction

  20. Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,

    E-print Network

    Atwater, Harry

    Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,, Stanley P. Burgos to requirements for plasmonic color filters designed for state-of-the-art Si CMOS image sensors. The hole arrays at the primary colors of red, green, and blue. Hole array plasmonic filters show peak transmission in the 40

  1. Packaging commercial CMOS chips for lab on a chip integration.

    PubMed

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

  2. CMOS transconductance multipliers: a tutorial

    Microsoft Academic Search

    Gunhee Han; E. Sanchez-Sinencio

    1998-01-01

    Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been

  3. A sub-0.3V highly efficient CMOS rectifier for energy harvesting applications

    NASA Astrophysics Data System (ADS)

    Niu, Dan; Huang, Zhangcai; Jiang, Minglu; Inoue, Yasuaki

    This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit, combining with body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18m process. Moreover, the voltage drop of negative voltage converter can be reduced to enhance the output voltage efficiency by adopting the proposed body bias technique. In combination with minimum reverse current and simple bias circuit in the proposed comparator, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96% and the maximum power efficiency of approximately 94%.

  4. A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

    PubMed Central

    Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

    2008-01-01

    A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications.

  5. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    NASA Astrophysics Data System (ADS)

    Sawadsaringkarn, Y.; Kimura, H.; Maezawa, Y.; Nakajima, A.; Kobayashi, T.; Sasagawa, K.; Noda, T.; Tokuda, T.; Ohta, J.

    2012-03-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  6. Noise behavior of a 180-nm CMOS SOI technology for detector front-end electronics

    SciTech Connect

    Re, Valerio; /Bergamo U. /INFN, Pavia; Gaioni, Luigi; /Pavia U. /INFN, Pavia; Manghisoni, Massimo; /Bergamo U. /INFN, Pavia; Ratti, Lodovico; /Pavia U. /INFN, Pavia; Speziali, Valeria; /Pavia U. /INFN, Pavia; Traversi, Gianluca; /Bergamo U. /INFN, Pavia; Yarema, Ray; /Fermilab

    2008-01-01

    This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully depleted SOI devices as a reference. The comparison in terms of white and 1/f noise components with bulk MOSFETs with the same minimum feature size gives a basis of estimate for the signal-to-noise ratio achievable in detector front-end integrated circuits designed in an SOI technology.

  7. 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

    PubMed Central

    2014-01-01

    We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4?GHz CMOS power amplifier with a 0.18??m RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32?dBm. The designed chip size is 1.4 0.6?mm2. PMID:25045755

  8. 3D integration of planar crossbar memristive devices with CMOS substrate.

    PubMed

    Lin, Peng; Pi, Shuang; Xia, Qiangfei

    2014-10-10

    Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moir pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. PMID:25224779

  9. Ultra low power CMOS technology

    NASA Technical Reports Server (NTRS)

    Burr, J.; Peterson, A.

    1991-01-01

    This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

  10. CMOS micromachined probes by die-level fabrication for extracellular neural recording

    NASA Astrophysics Data System (ADS)

    Ho, Meng-Han; Chen, Hsin; Tseng, Fouriers; Yeh, Shih-Rung; S-C Lu, Michael

    2007-02-01

    In this paper, we present the design, fabrication and characterization of CMOS micromachined probes for extracellular neural recording. A convenient fabrication process is proposed for making integrated recording probes at the die level, providing a low-cost solution for academic research as compared to the more expensive wafer-level approach adopted in prior work. The devices are fabricated in a standard 0.35 m CMOS process, followed by post-CMOS micromachining steps to form the probes. The on-chip circuit, used for recording action potential signals of neural activities, provides a stable dc bias when operating in electrolyte. The subthreshold transistor at the circuit input provides a tunable resistance value between 10 M? up to G?. The circuit consumes a total power of 790 W and has an output noise of 19.3 V Hz-1/2 at 100 Hz. The recorded action potential from the stimulated ventral nerve cord of a crayfish is about 0.6 mV with a pulse width of about 1.2 ms.

  11. Integrated pressure-sensing microsystem by CMOS IC technology for barometal applications

    NASA Astrophysics Data System (ADS)

    Zhou, Minxin; Huang, Qing-An

    2001-10-01

    Most currently integrated silicon microsystems available for pressure sensing are based on preprocessing before CMOS IC technology. These microsystems are generally very sensitive to parasitism effect and not available for IC-compatible process. This limits the accuracy of the microsystem and batch-fabrication. Calibration cost is also increased. To overcome these problems, a new generation of pressure microsystems without preprocessing CMOS IC technology has been proposed. This pressure-sensing system consists of a miniature silicon capacitive sensor, fabricated with silicon-silicon bonding technique, and a detection integrated circuit. Only the standard layers of CMOS process are used to build the system and only several photolithography steps are necessary to achieve the micromachined structure in postprocessing, so a high long-term stability could be assured. The entire system converts absolute pressure changes, in the pressure range useful for barometal applications, to frequency changes. A reference capacitor is used in the system and a (delta) C model is applied to cancel out temperature dependence and to compensate non-linearity. The pressure range of the sensor is from 0.5 bar to 1.5bar and the temperature varies between -25 degree(s)C and -60 degree(s)C. A sensitivity of 50Hz/Torr could be achieved.

  12. A simple and low-cost biofilm quantification method using LED and CMOS image sensor.

    PubMed

    Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

    2014-12-01

    A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P < 0.01) and the coefficients of variation (CVs) were approximately threefold lower at the CMOS image-sensor platform. PMID:25455019

  13. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    SciTech Connect

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y. [Institut Pluridisplinaire Hubert Curien IPHC, Univ. of Strasbourg, CNRS/IN2P3, 23 Rue du Loess, 67037 Strasbourg (France)

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  14. CMOS-integrated geometrically tunable optical filters.

    PubMed

    Lerose, Damiana; Hei, Evie Kho Siaw; Ching, Bong Ching; Sterger, Martin; Yaw, Liau Chu; Schulze, Frank Michael; Schmidt, Frank; Schmidt, Andrei; Bach, Konrad

    2013-03-10

    We present a method for producing monolithically integrated complementary metal-oxide-semiconductor (CMOS) optical filters with different and customer-specific responses. The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented. PMID:23478769

  15. Nanoscale Materials and Structures for CMOS Devices

    NSDL National Science Digital Library

    Zollner, Stefan

    This presentation was given at the Arizona Nanotechnology Conference in March of 2008 by Dr. Stefan Zollner, Freescale Semiconductor, USA. The focus is on problems with planar CMOS and their solutions. These solutions consist of: SOI or FINFET to reduce source and drain leakage, high mobility channel materials to increase drive current, new silicide materials to reduce source and drain contact resistance, metal oxides with high dielectric constants to reduce gate leakage and metal gate electrodes to reduce gate depletion. Overall, the presentation is filled with images and diagrams allowing it to flow easily. This is an excellent resource for anyone looking to learn more about nanotechnology and its applications.

  16. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15?m, high resistivity custom (~30k?-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16?m pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40?V/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9?m epitaxial silicon and have a 1k by 1k format. They incorporate similar 16?m pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

  17. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  18. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    SciTech Connect

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  19. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS

    SciTech Connect

    Smith, J.H.; Montague, S.; Sniegowski, J.J.; Murray, J.R. [and others

    1996-10-01

    Recently, a great deal of interest has developed in manufacturing processes that allow the monolithic integration of MicroElectroMechanical Systems (MEMS) with driving, controlling, and signal processing electronics. This integration promises to improve the performance of micromechanical devices as well as lower the cost of manufacturing, packaging, and instrumenting these devices by combining the micromechanical devices with a electronic devices in the same manufacturing and packaging process. In order to maintain modularity and overcome some of the manufacturing challenges of the CMOS-first approach to integration, we have developed a MEMS-first process. This process places the micromechanical devices in a shallow trench, planarizes the wafer, and seals the micromechanical devices in the trench. Then, a high-temperature anneal is performed after the devices are embedded in the trench prior to microelectronics processing. This anneal stress-relieves the micromechanical polysilicon and ensures that the subsequent thermal processing associated with fabrication of the microelectronic processing does not adversely affect the mechanical properties of the polysilicon structures. These wafers with the completed, planarized micromechanical devices are then used as starting material for conventional CMOS processes. The circuit yield for the process has exceeded 98%. A description of the integration technology, the refinements to the technology, and wafer-scale parametric measurements of device characteristics is presented. Additionally, the performance of integrated sensing devices built using this technology is presented.

  20. Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

    NASA Technical Reports Server (NTRS)

    Blaes, B. R.; Soli, G. A.; Buehler, M. G.

    1991-01-01

    A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

  1. Far ultraviolet sensitivity of silicon CMOS sensors

    NASA Astrophysics Data System (ADS)

    Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

    2012-07-01

    We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

  2. High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector

    E-print Network

    Venkatasubramanian, Radhika

    2007-04-25

    and compared with the simulation results. Frequency limitations were encountered during the testing process due to unexpected increase in the value of the N-well resistors. All other problems faced during the testing, as well as the results obtained so far...

  3. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  4. Designing and implementing a miniature CMOS imaging system with USB interface

    NASA Astrophysics Data System (ADS)

    Yao, Chenyun; Wang, Liqiang; Yuan, Bo; Xu, Jin

    2012-11-01

    Although CMOS cameras with USB interface are popular, their sizes are not small enough and working lengths are not that long enough when used as industrial endoscope. Here we present a small-sized image acquisition system for high-definition industrial electronic endoscope based on USB2.0 high-speed controller, which is composed of a 1/6 inch CMOS image sensor with resolution of 1 Megapixels. Signals from the CMOS image sensor are put into computer through the USB interface using the slave FIFO mode for processing, storage and display. LVDS technology is used for image data stream transmission between the sensor and USB controller to realize a long working distance, high signal integrity and low noise system. The maximum pixel clock runs at 48MHz to support for 30 fps for QSXGA mode or15 fps for SXGA mode and the data transmission rate can reach 36 megabytes per second. The imaging system is simple in structure, low-power, low-cost and easy to control. Based on multi-thread technology, the software system which realizes the function of automatic exposure, automatic gain, and AVI video recording is also designed.

  5. Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

    NASA Astrophysics Data System (ADS)

    Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

    2014-12-01

    We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

  6. On-chip polarizer on image sensor using advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Sasagawa, Kiyotaka; Wakama, Norimitsu; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

    2014-03-01

    The structures in advanced complementary metal-oxide-semiconductor (CMOS) integrated circuit technology are in the range of deep-submicron. It allows designing and integrating nano-photonic structures for the visible to near infrared region on a chip. In this work, we designed and fabricated an image sensor with on-pixel metal wire grid polarizers by using a 65-nm standard CMOS technology. It is known that the extinction ratio of a metal wire grid polarizer is increased with decrease in the grid pitch. With the metal wire layers of the 65-nm technology, the grid pitch sufficiently smaller than the wavelengths of visible light can be realized. The extinction ratio of approximately 20 dB has been successfully achieved at a wavelength of 750 nm. In the CMOS technologies, it is usual to include multiple metal layers. This feature is also useful to increase the extinction ratio of polarizers. We designed dual layer polarizers. Each layer partially reflects incident light. Thus, the layers form a cavity and its transmission spectrum depends on the layer position. The extinction ratio of 19.2 dB at 780 nm was achieved with the grid pitch greater than the single layer polarizer. The high extinction ratio is obtained only red to near infrared region because the fine metal layers of deepsubmicron standard CMOS process is usually composed of Cu. Thus, it should be applied for measurement or observation where wide spectrum is not required such as optical rotation measurement of optically active materials or electro-optic imaging of RF/THz wave.

  7. A CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates

    E-print Network

    Islam, Kazi Inamul

    1995-01-01

    of reasons given below. CMOS is the dominant technology in use in VLSI today, but its use in driving large load capacitances is limited. BiCMOS and BiNMOS circuits perform better in this respect because of the higher current capabilities of the bipolar... degradation at lower supply voltages because of a loss in output swing. In this situation, BiNMOS gates combining a bipolar pull-up with a conventional CMOS pull-down provide a remedy. Therefore, as we move towards larger chip size and lower supply voltages...

  8. 252 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 A CMOS Subbandgap Reference Circuit With 1-V Power Supply Voltage

    E-print Network

    Ayers, Joseph

    management circuits [1]. As process technologies go into the deep-submicron eras and the demand for battery) as well as design margin. To keep pace with supply voltage requirements of a state-of-the-art CMOS process) and the operating temperature range is narrow ( 25 C to 125 C). Furthermore, Manuscript received January 21, 2003

  9. 1 chip integrated software calibrated CMOS pressure sensor with MCU, A\\/D convertor, D\\/A convertor, digital communication port, signal conditioning circuit and temperature sensor

    Microsoft Academic Search

    Y. Yoshii; A. Nakajo; H. Abe; K. Nimomiya; H. Miyashita; N. Sakurai; M. Kosuge; S. Hao

    1997-01-01

    This paper reports the newly developed 1 chip integrated CMOS pressure sensor, its highly manufacturable fabrication process using SOI substrate, its output characteristics calibrated and compensated by software on MCU with excellent absolute accuracy over wide temperature range, and the calibration system to perform calibration process

  10. Characterization of the HDP-CVD oxide as interlayer dielectric material for sub-quarter micron CMOS

    Microsoft Academic Search

    Ju Wan Kim; Ju Bum Lee; Jin Gi Hong; Byung Keun Hwang; Sung Tae Kim; Min Soeg Han

    1998-01-01

    The characteristics and process optimization of high density plasma (HDP) CVD oxide as a wordline to bitline interlayer dielectric (ILD) material in sub-quarter micron CMOS DRAM were investigated. To enhance the gap-filling capability, multi-step deposition of HDP CVD oxide was developed. A self-aligned contact (SAC) scheme could be used with HDP CVD oxide ILD with wide process margin and low

  11. Design of CMOS Cell Libraries for Minimal Leakage Currents

    E-print Network

    Design of CMOS Cell Libraries for Minimal Leakage Currents Master's Thesis by Jacob Gregers Hansen Leakage Currents' conducted at Informatics and Mathematical Mod- elling (IMM), Computer Science.3 The problem of leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Possible solutions

  12. Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage

    E-print Network

    Heo, Seongmoo

    2004-07-12

    Digital circuits often have a critical path that runs through a smallsubset of the component subblocks, but where the path changes dynamicallyduring operation. Dynamically resizable static CMOS (DRCMOS) logic isproposed ...

  13. Circuits and algorithms for pipelined ADCs in scaled CMOS technologies

    E-print Network

    Brooks, Lane Gearle, 1975-

    2008-01-01

    CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

  14. Formal specification of a high speed CMOS correlator

    NASA Technical Reports Server (NTRS)

    Windley, P. J.

    1991-01-01

    The formal specification of a high speed CMOS correlator is presented. The specification gives the high-level behavior of the correlator and provides a clear, unambiguous description of the high-level architecture of the device.

  15. A wide-dynamic-range time-based CMOS imager

    E-print Network

    O'Halloran, Micah G. (Micah Galletta), 1978-

    2008-01-01

    This thesis describes a novel dual-threshold time-based current sensing algorithm suitable for use in wide-dynamic-range CMOS imagers. A prototype 150 x 256 pixel imager employing this algorithm experimentally achieves ...

  16. A study of CMOS technologies for image sensor applications

    E-print Network

    Wang, Ching-Chun, 1969-

    2001-01-01

    CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

  17. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  18. High-speed multicolour photometry with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

    2012-11-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ?14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to 10 can be shot at 24 frames per second in the video mode.

  19. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  20. Design of a CMOS compatible, athermal, optical waveguide

    E-print Network

    Fernandez, Luis Enrique, S.B. Massachusetts Institute of Technology

    2007-01-01

    This paper explores a possible design for a CMOS compatible, athermal, optical waveguide. The design explored is a slot waveguide with light guided in the low index material. A design paradigm is proposed which shows the ...

  1. Strain-engineered CMOS-compatible Ge photodetectors

    E-print Network

    Cannon, Douglas Dale, 1974-

    2004-01-01

    The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

  2. Photonic Device Layout Within the Foundry CMOS Design Environment

    E-print Network

    Orcutt, Jason Scott

    A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs ...

  3. A silicon avalanche photodetector fabricated with standard CMOS technology

    E-print Network

    Choi, Woo-Young

    A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain a silicon avalanche photodetector (APD) fabricated with standard complementary metal-well junction, and its current-voltage characteristics, responsivity, avalanche gain, and photodetection

  4. Fabrication and simulation of CMOS-compatible photodiodes

    E-print Network

    DiLello, Nicole Ann

    2008-01-01

    CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

  5. A CMOS Capacitance Sensor for Cell Adhesion Characterization

    E-print Network

    Maryland at College Park, University of

    Abshire Department of Electrical and Computer Engineering University of Maryland College Park, Maryland 20742, USA Mario Urdaneta, Elisabeth Smela Department of Mechanical Engineering University of Maryland College Park, Maryland 20742, USA Abstract-- We describe a CMOS capacitance sensor for measuring

  6. Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

    NASA Technical Reports Server (NTRS)

    Trotter, J. D.

    1982-01-01

    The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

  7. Polysaccharide microarrays with a CMOS based signal detection unit.

    PubMed

    Baader, Johannes; Klapproth, Holger; Bednar, Sonja; Brandstetter, Thomas; Rhe, Jrgen; Lehmann, Mirko; Freund, Ingo

    2011-01-15

    Microarray based test assays have become increasingly important tools in diagnostics for fast multi-parameter detection especially where sample volumes are limited. We present here a simple procedure to create polysaccharide microarrays, which can be used to analyze antibodies using an integrated, complementary metal-oxide-semiconductor (CMOS) based electric signal readout process. To accomplish this chips are used which consist of an array of silicon photodiodes and where different types of polysaccharides from the bacteria Streptococcus pneumoniae are printed on the (silicon dioxide) chip surface. Typical amounts of polysaccharide deposited in the printing process are around 12 attomol/spot. In a subsequent reaction step the polysaccharide microarrays were used for the measurement of IgG antibody concentrations in human blood sera using either chemiluminescence or fluorescence based detection. To understand the device performance the influence of surface density of the immobilized polysaccharide molecules and other parameters on the assay performance are investigated. The dynamic measurement range of the sensor is shown to reach over more than 3 decades of concentration and covers the whole physiologically relevant range for the analysis of antibodies against a large panel of pneumococcal polysaccharides. PMID:20181471

  8. SOI for digital CMOS VLSI: design considerations and advances

    Microsoft Academic Search

    Ching-Te Chuang; PONG-FEI LU; CARL J. ANDERSON

    1998-01-01

    This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted

  9. Study on sub-pixel measurement accuracy of CMOS imager

    Microsoft Academic Search

    Zhi Liu

    2005-01-01

    There are two main image sensors that are now being widely used in image capture system: CCD and CMOS imager. The fill-factor of CMOS imager is lower than that of CCD, so it is of great importance to consider the influence of the fill-factor on sub-pixel measurement accuracy. the main purpose of this paper is to give a discussion of

  10. Deep submicron CMOS based on silicon germanium technology

    Microsoft Academic Search

    A. G. O'Neill; D. A. Antoniadis

    1996-01-01

    The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 ?m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si\\/SiO2 interface scattering by the

  11. An Energy-Efficient CMOS Line Driver Using Adiabatic Switching

    Microsoft Academic Search

    W. C. Athas; J. G. Koller

    1993-01-01

    The energy recovery principle used in high-efficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom line- driver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than conventional CMOS. The paper describes the adiabatic charging principle underlying this class

  12. A statistical MOSFET modeling method for CMOS integrated circuit simulation

    E-print Network

    Chen, Jian

    1992-01-01

    A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

  13. Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects

    Microsoft Academic Search

    Brajesh Kumar Kaushik; Sankar Sarkar

    2008-01-01

    This paper deals in crosstalk analysis of a CMOS-gate-driven capacitively and inductively coupled interconnect. Alpha power-law model of a MOS transistor is used to represent a CMOS driver. This is combined with a transmission-line-based coupled-interconnect model to develop a composite driver-interconnect-load model for analytical purposes. On this basis, a transient analysis of crosstalk noise is carried out. Comparison of the

  14. A compact tunable CMOS transconductor with high linearity

    Microsoft Academic Search

    Meghraj Kachare; Antonio J. Lpez-Martn; Jaime Ramirez-Angulo; Ramon G. Carvajal

    2005-01-01

    A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-?m CMOS technology show a total harmonic

  15. Electrical properties and detection methods for CMOS IC defects

    Microsoft Academic Search

    Jerry M. Soden; Charles F. Hawkins

    1989-01-01

    CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees detection of all types

  16. CMOS Image Sensors: Electronic Camera On A Chip

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  17. Sub60 nm physical gate length SOI CMOS

    Microsoft Academic Search

    I. Y. Yang; K. Chen; P. Smeys; J. Sleight; L. Lin; M. Leong; E. Nowak; S. Fung; E. Maciejewski; P. Varekamp; W. Chu; P. Agnello; S. Crowder; F. Assaderaghi; L. Su

    1999-01-01

    This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of

  18. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  19. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  20. A 7.2 GSa\\/s, 14 Bit or 12 GSa\\/s, 12 Bit Signal Generator on a Chip in a 165 GHz ${\\\\rm f}_{\\\\rm T}$ BiCMOS Process

    Microsoft Academic Search

    Frank Van de Sande; Nico Lugil; Filip Demarsin; Zeger Hendrix; Alvin Andries; Peter Brandt; William Anklam; Jeffery S. Patterson; Brian Miller; Michael Rytting; Mike Whaley; Bob Jewett; Jacky Liu; Jake Wegman; Ken Poulton

    2012-01-01

    We present a complete signal generator with integrated digital-to-analog convertor (DAC) on a chip which can generate complex waveforms at up to 7.2 GSa\\/s with 14 bit resolution or at up to 12 GSa\\/s with 12 bit resolution. The 3 dB bandwidth is 4.4 GHz. The chip includes digital signal processing (DSP) logic for agile generation of wideband modulated RF

  1. Manufacture and Characterization of High Q-Factor Inductors Based on CMOS-MEMS Techniques

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Hong, Jin-Yu

    2011-01-01

    A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively. PMID:22163726

  2. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    PubMed Central

    Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18??m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18??m TSMC CMOS technology. PMID:24782680

  3. PostCMOS compatible sacrificial layers for aluminum nitride microcantilevers

    NASA Astrophysics Data System (ADS)

    Prez-Campos, Ana; Iriarte, Gonzalo Fuentes; Lebedev, Vadim; Calle, Fernando

    2014-10-01

    This report shows different fabrication procedures followed to obtain piezoelectric microcantilevers. The proposed microcantilever is a sandwich structure composed of chromium (Cr) electrodes (from 50 to 300-nm thick) and a reactive sputtered piezoelectric aluminum nitride (AlN) thin film (from 350 nm to 600-nm thick). The microcantilevers top-view dimensions ranged from 50 to 300 ?m in width and from to 250 to 700 ?m in length. Several materials such as nickel silicide and nickel, as well as a photoresist, and finally the silicon substrate surface have been investigated to discern their possibilities and limitations when used as sacrificial layers. These materials have been studied to determine the optimal processing steps and chemistries required for each of them. The easiest and the only successful microcantilevers release was finally obtained using the top silicon substrate surface as a sacrificial layer. The structural and morphological characteristics of the microcantilevers are presented as well as their piezoelectric character. The main difference of this work resides in the Si surface-based microcantilever release technique. This, along with the synthesis of AlN at room temperature by reactive sputtering, establishes a manufacturing procedure for piezoelectric microbeams, which makes possible the integration of such MEMS devices into postCMOS technology.

  4. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 m CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 W power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 W power dissipation. PMID:25806868

  5. CMOS arrays as chemiluminescence detectors on microfluidic devices.

    PubMed

    Rodrigues, Eunice R G O; Lapa, Rui A S

    2010-05-01

    A simple, low-cost process to integrate complementary metal oxide semiconductor array detectors (CMOSAD) for chemiluminescence is presented, evaluated, and applied to the determination of nitrite in ground water samples. CMOS arrays of different brands (obtained from commercial image sensors) were adapted as chemiluminescence detectors on microfluidic devices. The performance of the CMOSADs was evaluated in the visible zone of the spectrum using a tungsten halogen lamp as light source. Intrinsic parameters assessed included signal stability, spectral response, dark current, and signal-to-noise ratio. Thereafter, the CMOSADs were integrated on microfluidic devices and their performances in quantitative analysis were assessed with the chemiluminometric reaction of hydrogen peroxide with luminol, catalyzed with hexacyanoferrate (III). The parameters assessed were sensitivity, linear range, detection limit, reproducibility, correlation coefficient of the calibration curves, and baseline drift during measurements. The CMOSAD with the best performance was selected to assess the applicability of the developed microfluidic devices with the integrated detector. The microfluidic system permitted the determination of nitrite with both good precision and good recovery values in the analysis of ground water samples. Integration was easily achieved and enabled the development of a simple, low-cost, and feasible alternative to conventional detectors. PMID:20177663

  6. CMOS solid state photomultipliers for ultra-low light levels

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

    2011-05-01

    Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

  7. Passive radiation detection using optically active CMOS sensors

    NASA Astrophysics Data System (ADS)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and ? particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  8. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-14

    ...COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations...within the United States after importation of certain CMOS image sensors and products containing the same based on...

  9. A low-power asynchronous ECG acquisition system in CMOS technology.

    PubMed

    Hwang, Sungkil; Trakimas, Michael; Sonkusale, Sameer

    2010-01-01

    An asynchronous electrocardiogram (ECG) acquisition system is presented for wearable ambulatory monitoring. The proposed system consists of a low noise front-end amplifier (AFE) with tunable bandwidth, an asynchronous analog-to-digital converter (ADC), and digital signal processing (DSP). Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. This makes the system attractive for compact wearable ECG monitoring applications. The AFE and ADC were fabricated in a 0.18 microm CMOS technology and consume a total of 79 microW. Measured results demonstrating ECG monitoring are presented. PMID:21096052

  10. Silicon MCM substrates for integration of III-V photonic devices and CMOS IC`s

    SciTech Connect

    Seigal, P.; Carson, R.; Flores, R.; Rose, B.

    1993-07-01

    The progress made in advanced packaging development at Sandia National Laboratories for integration of III-V photonic devices and CMOS IC`s on Silicon MCM substrates for planar aid stacked applications will be reported. Studies to characterize precision alignment techniques using solder attach materials compatible with both silicon IC`s and III-V devices will be discussed. Examples of the use of back-side alignment and IR through-wafer inspection will be shown along with the extra processing steps that are used. Under bump metallurgy considerations are also addressed.

  11. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

    PubMed Central

    Lu, Guo-Neng; Tournier, Arnaud; Roy, Franois; Deschamps, Benot

    2009-01-01

    We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed. PMID:22389592

  12. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

    PubMed

    Lu, Guo-Neng; Tournier, Arnaud; Roy, Franois; Deschamps, Benot

    2009-01-01

    We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed. PMID:22389592

  13. A 1GHz BiCMOS RF front-end IC

    Microsoft Academic Search

    Robert G. Meyer; William D. Mack

    1994-01-01

    An RF front-end IC containing a low-noise amplifier and mixer is described. On-chip temperature and supply-voltage compensation is used to stabilize circuit performance. Realized in a BiCMOS process, the circuit consumes 13.0-mA total current from a 5-V supply. The amplifier gain at 900 MHz is 16 dB, the noise figure is 2.2 dB, and the input third-order intermodulation intercept is

  14. Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Krger, H.; Wermes, N.

    2015-03-01

    We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e?) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 ?m thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

  15. c-mos Variation in Songbirds: Molecular Evolution, Phylogenetic Implications, and Comparisons with Mitochondrial Differentiation

    Microsoft Academic Search

    Irby J. Lovette; Eldredge Bermingham

    Nucleotide sequences from the c-mos proto-oncogene have previously been used to reconstruct the phylogenetic relationships between distantly related vertebrate taxa. To explore c-mos variation at shallower levels of avian divergence, we compared c-mos sequences from representative passerine taxa that span a range of evolutionary differentiation, from basal passerine lineages to closely allied genera. Phylogenetic reconstructions based on these c-mos sequences

  16. Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

    Microsoft Academic Search

    Saibal Mukhopadhyay; Kaushik Roy

    2003-01-01

    In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source\\/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation

  17. High performance 0.25-um CMOS color imager technology with non-silicide source\\/drain pixel

    Microsoft Academic Search

    Shou-Gwo Wuu; Dun-Nian Yaung; Chien-Hsien Tseng; Ho-Ching Chien; Chung S. Wang; Yean-Kuen Hsiao; Chin-Kung Chang; B. J. Chang

    2000-01-01

    A high performance 0.25 um CMOS image sensor technology has been developed to overcome device scaling and process issues. Non-silicide source\\/drain pixel (3 transistors, 3.3 um3.3 um, fill factor: 28%) is provided to reduce dark current and increase photoresponse. By optimizing thermal oxide in STI structure, double ion implanted source\\/drain junction and using H2 annealing, the dark current can be

  18. Design, optimization, and performance analysis of new photodiode structures for CMOS active-pixel-sensor (APS) imager applications

    Microsoft Academic Search

    Chung-Yu Wu; Yu-Chuan Shih; Jeng-Feng Lan; Chih-Cheng Hsieh; Chien-Chang Huang; Jr-Houng Lu

    2004-01-01

    The dark current in the active-pixel-sensor (APS) cell of a CMOS imager is known to be mainly generated in the regions of bird's beak after the local oxidation of silicon process as well as the surface damage caused by the implantation of high doping concentration. Furthermore, shallow and deep pn-junctions can improve the photo-sensitivity for light of short and long

  19. Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

    Microsoft Academic Search

    Toyota Morimoto; Tatsuya Ohguro; Hisayo Sasaki Momose; Toshihiko Iinuma; Iwao Kunishima; Kyoichi Suguro; Ichiro Katakabe; Hiroomi Nakajima; Masakatsu Tsuchiaki; Mizuki Ono; Yasuhiro Katsumata; Hiroshi Iwai

    1995-01-01

    A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n+- and p+-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at

  20. A CMOS readout integrated circuit with wide dynamic range for a CNT bio-sensor array system

    Microsoft Academic Search

    Hyunjoong Lee; Hyongmin Lee; Jong-Kwan Woo; Sunkwon Kim; Young June Park; Suhwan Kim

    2011-01-01

    We present a sensor readout integrated circuit for the CNT bio-sensor array, the heart of which is our low-power current-input continuous-time ?? modulator that is capable of dynamic range extension. Experimental results show that the prototype chip, designed and fabricated in 0.18?m CMOS process, achieves a dynamic range of 87.746dB and has a readout rate of 160kHz, which guarantees 1k

  1. An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers

    Microsoft Academic Search

    A. Bevilacqua; A. M. Niknejad

    2004-01-01

    A UWB 3.1 to 10.6 GHz LNA employing an input three-section band-pass Chebyshev filter is reported. Fabricated in a 0.18 ?m CMOS process, -10 dB over the band, a NF of 4 dB, and an IIP3 of -6.7 dBm while consuming the IC achieves a power gain of 9.3 dB with an input match of 9 mW.

  2. Pulsed Laser Single-Event Effects in Highly Scaled CMOS Technologies in the Presence of Dense Metal Coverage

    Microsoft Academic Search

    Anupama Balasubramanian; Dale McMorrow; Sarah A. Nation; Bharat L. Bhuva; Robert A. Reed; Lloyd W. Massengill; Thomas D. Loveless; Oluwole A. Amusan; Jeffrey D. Black; Joseph S. Melinger; Mark P. Baze; Veronique Ferlet-Cavrois; Marc Gaillardin; James R. Schwank

    2008-01-01

    single-photon (SPA) and two-photon laser absorption (TPA) techniques are established as reliable, effective methods to study specific single-event (SE) phenomena in advanced CMOS technologies. However, dense metal-fill in these nanoscale processes can prevent the use of top-side SPA in some cases. This paper demonstrates a novel methodology enabling top-side laser SPA single-event effects (SEEs) measurements in the presence of dense

  3. A 10Gb\\/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

    Microsoft Academic Search

    Sangjin Byun; Jyung Chan Lee; Jae Hoon Shim; Kwangjoon Kim; Hyun-Kyu Yu

    2006-01-01

    This paper presents a 10-Gb\\/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply

  4. A 38 GHz accumulation MOS differentially tuned VCO design in 0.18-\\/spl mu\\/m CMOS

    Microsoft Academic Search

    J. P. Carr; B. M. Frank

    2006-01-01

    A 38 GHz cross-coupled differential LC-VCO has been designed and fabricated using the TSMC 0.18-mum CMOS process. A differential accumulation-mode MOS (AMOS) varactor structure is used, with a tuning range of 36.7 to 38.9 GHz. The differential varactor structure provides suppression of common-mode noise on the power supply and frequency control lines

  5. Low phase noise 5 GHz VCOs in 0.13 \\/spl mu\\/m SOI and bulk CMOS

    Microsoft Academic Search

    D. I. Sanderson; Jonghae Kim; Xudong Wang; R. E. Trzcinski; J.-O. Plouchart

    2006-01-01

    This paper present 5 GHz LC VCO designs fabricated in 0.13 mum SOI and bulk CMOS process technologies. Technology advantages, considerations, and trade-offs are compared for high performance VCO design. A methodology for designing a low FOM VCO is given. The SOI VCO achieves a phase noise of -131 dBc\\/Hz at a 1 MHz offset and consumes 6 mW. The

  6. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

    Microsoft Academic Search

    Chip-Hong Chang; Jiangmin Gu; Mingyan Zhang

    2004-01-01

    This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel

  7. Etch challenges for DSA implementation in CMOS via patterning

    NASA Astrophysics Data System (ADS)

    Pimenta Barros, P.; Barnola, S.; Gharbi, A.; Argoud, M.; Servin, I.; Tiron, R.; Chevalier, X.; Navarro, C.; Nicolet, C.; Lapeyre, C.; Monget, C.; Martinez, E.

    2014-03-01

    This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

  8. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. XX, NO. Y, MONTH 2013 1 Incorporating Manufacturing Process Variation

    E-print Network

    Mohanty, Saraju P.

    Oscillator (VCO). I. INTRODUCTION AND MOTIVATION The design cycle of analog and mixed-signal circuits). To demonstrate the proposed process-variation aware design flow, a current-starved topology based nano-CMOS VCO Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs Saraju P. Mohanty

  9. The Implementation of Retinal Functions on CMOS ICs and Their Applications

    Microsoft Academic Search

    Chung-Yu Wu

    2007-01-01

    In this talk, three main topics including the CMOS implementation of neuromorphic chips, focal-plane motion sensors, and implantable retinal chips for visual prostheses are addressed. A CMOS design methodology for implementing CMOS neuromorphic chips which imitate the ON brisk transient ganglion cell (GC) set of rabbits' retinas is presented in the first part. Retina is the most important preprocessor in

  10. Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess

    E-print Network

    Sahay, Sundeep

    Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess YNGVAR BERG I. Innhold GJ ennomgang av CMOS prosess, tverrsnitt av nMOS- og pMOS transistor og tverrsnitt av CMOS inverter. Enkel forklaring p°a begreper som akkumulasjon, deplesjon og inver- sjon. Enkel fysikalsk forklaring p°a transistor

  11. Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua

    E-print Network

    Hornsey, Richard

    Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua , Wei Gaoa , Paul J, University of Toronto, Toronto, Ontario, Canada ABSTRACT Damage in CMOS image sensors caused by heavy ions and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors

  12. Architecture and Performance Evaluation of 3D CMOS-NEM FPGA

    E-print Network

    Chen, Deming

    Architecture and Performance Evaluation of 3D CMOS-NEM FPGA Chen Dong*, Chen Chen+, Subhasish Mitra In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and configurable logic blocks (CLBs), NEM-based switch

  13. CMOS Cell Sensors for Point-of-Care Diagnostics

    PubMed Central

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  14. A CMOS readout circuit for microstrip detectors

    NASA Astrophysics Data System (ADS)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  15. Feasibility study of CMOS detectors for mammography

    NASA Astrophysics Data System (ADS)

    Han, Jong Chul; Yun, Seungman; Lim, Chang Hwy; Kim, Tae Woo; Kim, Ho Kyung

    2009-02-01

    We investigated the potential use of CMOS (complementary metal-oxide-semiconductor) imaging detectors with a pixel pitch of 48 ?m for mammography. Fundamental imaging characteristics were evaluated in terms of modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). The magnitudes of various image noise sources, such as optical photons, direct x rays unattenuated and scattered x rays from the scintillator, and additive electronic noise, were measured and analyzed. For the analysis of the measurement results, we applied a model describing the signal and noise transfer based on the cascaded linear-systems approach. The direct x-ray was very harmful to the detector noise performance with white noise characteristics in the spatial frequency domain, and which significantly degraded the spatial-frequency-dependent DQE at higher frequencies. Although the use of a fiber-optic plate (FOP) reduces the detector sensitivity and the MTF performance, it enhances the DQE performance by preventing the direct x-ray photons from the absorption within the photodiode array.

  16. A New CMOS Posicast Pre-shaper for Vibration Reduction of CMOS Op-Amps

    NASA Astrophysics Data System (ADS)

    Rasoulzadeh, M.; Ghaznavi-Ghoushchi, M. B.

    2010-06-01

    Posicast-based control is a widely used method in vibration reduction of lightly damped oscillatory systems especially in mechanical fields. The target systems to apply Posicast method are the systems which are excited by pulse inputs. Using the Posicast idea, the input pulse is reshaped into a new pulse, which is called Posicast pulse. Applying the generated Posicast pulse reduces the undesired oscillatory manner of under-test systems. In this paper, a fully CMOS Pulse pre-shaper circuit for realization of Posicast command is proposed. Our design is based on delay-and-add approach for the incoming pulses. The delay is done via a modified Schmitt Trigger-like circuit. The adder circuit is implemented by a simple non-binary analog adder terminated by a passive element. Our proposed design has a reasonable flexibility in configuration of time delay and amplitude of the desired pulse-like shapes. The delay is controlled via the delay unit and the pre-shaped pulse's amplitudes are controlled by an analog adder unit. The overall system has 18 MOS transistors, one small capacitor, and one resistor. To verify the effectiveness of the recommended method, it is experienced on a real CMOS Op-Amp. HSPICE simulation results, on 0.25u technology, show a significant reduction on overshoot and settling time of the under-test Op-Amp. The mentioned reduction is more than 95% in overshoot and more than 60% in settling time of the system.

  17. Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

    NASA Astrophysics Data System (ADS)

    Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

    2014-07-01

    We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

  18. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  19. Study of CMOS process variation by multiplexing analog characteristics

    E-print Network

    Gettings, Karen Mercedes Gonzlez-Valentn

    2007-01-01

    Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic ...

  20. Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Vishnoi, U.; Noll, T. G.

    2012-09-01

    The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 ?m2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz-1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

  1. A high-dynamic range (HDR) back-side illuminated (BSI) CMOS image sensor for extreme UV detection

    NASA Astrophysics Data System (ADS)

    Wang, Xinyang; Wolfs, Bram; Bogaerts, Jan; Meynants, Guy; BenMoussa, Ali

    2012-03-01

    This paper describes a back-side illuminated 1 Megapixel CMOS image sensor made in 0.18um CMOS process for EUV detection. The sensor applied a so-call "dual-transfer" scheme to achieve low noise, high dynamic range. The EUV sensitivity is achieved with backside illumination use SOI-based solution. The epitaxial silicon layer is thinned down to less than 3um. The sensor is tested and characterized at 5nm to 30nm illumination. At 17.4nm targeted wavelength, the detector external QE (exclude quantum yield factor) reaches almost 60%. The detector reaches read noise of 1.2 ph- (@17.4nm), i.e. close to performance of EUV photon counting.

  2. SEMICONDUCTOR INTEGRATED CIRCUITS: A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

    NASA Astrophysics Data System (ADS)

    Shimao, Xiao; Yunfeng, Yu; Chengyan, Ma; Tianchun, Ye; Ming, Yin

    2010-03-01

    The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 ?m 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

  3. Photonic Crystal Microcavities in a Microelectronics 45-nm SOI CMOS Technology

    NASA Astrophysics Data System (ADS)

    Poulton, Christopher Vincent; Zeng, Xiaoge; Wade, Mark T.; Shainline, Jeffrey Michael; Orcutt, Jason S.; Popovic, Milos A.

    2015-03-01

    We demonstrate the first monolithically integrated linear photonic crystal microcavities in an advanced SOI CMOS microelectronics process (IBM 45nm 12SOI) with no in-foundry process modifications. The cavities were integrated into a standard microelectronics design flow meeting process design rules, and fabricated alongside transistors native to the process. We demonstrate both 1520nm wavelength and 1180nm cavity designs using different cavity implementations due to design rule constraints. For the 1520nm and 1180nm designs, loaded quality factors of 2,000 and 4,000 are measured, and intrinsic quality factors of 100,000 and 60,000 are extracted. We also demonstrate an evanescent coupling geometry which decouples the cavity and waveguide-coupling design.

  4. Digital architectures for hybrid CMOS/nanodevice circuits

    NASA Astrophysics Data System (ADS)

    Strukov, Dmitri B.

    This dissertation describes architectures of digital memories and reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice ("CMOL") technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two-terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack. The most straightforward possible application of CMOL circuits is terabit-scale "resistive" memories, in which nanodevices (e.g., single molecules) would be used as single-bit, memory cells, while the semiconductor subsystem would perform all the peripheral (input/output, coding/decoding, line driving, and sense amplification) functions. Using bad-bit exclusion and error-correcting codes synergistically we show that CMOL memories with a nano/CMOS pitch ratio close to 1/3 may overcome purely semiconductor memories in useful density if the fraction of bad nanodevices is below 15%, even for the 30 ns upper bound on the total access time. As the nanotechnology matures, and the pitch ratio approaches an order of magnitude, the CMOL memories may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm2 density even for the plausible defect fraction of 2%. Even greater defect tolerance (about 20% for 99% circuit yield) can be achieved in uniform a cell-FPGA-like CMOL circuits. In such circuits, two-terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. The cell-based architecture is based on a uniform CMOL fabric of "tiles", while each tile consists of 12 four-transistor basic cells and one latch cell. To evaluate the potential performance of CMOL FPGA we have developed a completely custom design automation tools. Using these tools we have successfully mapped on CMOL FPGA the well known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption.

  5. A 0.5-GHz CMOS digital RF memory chip

    NASA Astrophysics Data System (ADS)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  6. CMOS sensor as charged particles and ionizing radiation detector

    NASA Astrophysics Data System (ADS)

    Cruz-Zaragoza, E.; Pia Lpez, I.

    2015-01-01

    This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained.

  7. A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

    PubMed

    Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

    2013-11-21

    As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 ?m 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

  8. A large area CMOS detector for shutterless collection of x-ray diffraction data

    NASA Astrophysics Data System (ADS)

    Thompson, A. C.; Westbrook, E. M.; Lavender, W. M.; Nix, J. C.

    2014-03-01

    Recent developments in CMOS devices have improved their radiation hardness, response linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large (14.8 x 9.4 cm) CMOS sensors with a pixel size of 100 x100 microns are now available that can be butted together on three sides. We have fabricated a 6-tile system in a 2x3 array with a 28.2 x 29.5 cm continuous imaging area. To make an x-ray detector the CMOS sensor is covered with a 3 mm flat fibre-optic plate (for radiation protection) and a Gd2O2S:Tb scintillator screen. A special feature of these systems is that they can be read out continuously at 10 frames/sec with excellent dynamic range without interrupting data collection. We have installed this system at beamline 4.4.2 of the Advanced Light Source synchrotron. Anomalous diffraction data were recorded without an x-ray shutter, rotating the crystal sample continuously with an exposure time of 0.1 sec/frame and a rotation speed of 1/sec for 180 degrees. The 1,800 frame datasets were processed in D*TREK and XDS data analysis programs and experimental phases were determined in PHENIX. The crystallographic results are typically significantly better than equivalent data recorded on a conventional CCD system, due to the 10X finer angular resolution of the recorded data. Very large systems can now be made that would have an active area of 56 x 59 cm2 with 33 x 106 pixels.

  9. Full colour RGB OLEDs on CMOS for active-matrix OLED microdisplays

    NASA Astrophysics Data System (ADS)

    Kreye, D.; Toerker, M.; Vogel, U.; Amelung, J.

    2006-08-01

    Microdisplays are used in various optical devices such as headsets, viewfinders and helmet-mounted displays. The use of organic light emitting diodes (OLEDs) in a microdisplay on silicone substrate provides the opportunity of lower power consumption and higher optical performance compared to other near-to-eye display technologies. Highly efficient, low-voltage, top emitting OLEDs are well suitable for the integration into a CMOSprocess. By reducing the operating voltage for the OLEDs below 5V, the costs for the CMOS process can be reduced significantly, because a standard process without high-voltage option can be used. Various OLED stacks on silicone substrate are presented, suitable for full colour (RGB) applications. Red and green emitting phosphorescent OLEDs and blue emitting fluorescent OLEDs all with doped charge transport layers were prepared on a two metal layer CMOS test substrate without active transistor area. Afterwards, the different test displays were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.)

  10. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    PubMed Central

    Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

    2012-01-01

    This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Youngs modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Eulers beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Youngs modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 ?m standard CMOS process, and the experimental results refer to Osterbergs work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

  11. Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

    PubMed

    Gu, Ming; Chakrabartty, Shantanu

    2013-08-15

    This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 ? m CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/ ()C (27 ()C- 57()C), while consuming less than 100 nW of power. PMID:23955789

  12. A CMOS pressure sensor with integrated interface for passive RFID applications

    NASA Astrophysics Data System (ADS)

    Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

    2014-12-01

    This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18??m CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2?fF?kPa?1. The sensor interface consumes only 1.1?W of power at 0.5?V voltage supply, which is at least an order of magnitude better than state-of-the-art designs.

  13. CMOS-MEMS test-key for extracting wafer-level mechanical properties.

    PubMed

    Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

    2012-01-01

    This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young's modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler's beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young's modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 ?m standard CMOS process, and the experimental results refer to Osterberg's work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

  14. Compact CMOS Camera Demonstrator (C3D) for Ukube-1

    NASA Astrophysics Data System (ADS)

    Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

    2011-09-01

    The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

  15. 604 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 Low-Power BiCMOS Circuits for High-Speed Interchip Communication

    E-print Network

    Elrabaa, Muhammad E. S.

    for High-Speed Interchip Communication M. S. Elrabaa, M. I. Elmasry, and D. S. Malhi Abstract--A universal] and CMOS pseudo ECL or CMOS 100 K ECL [8]­[9], to CMOS Gunning transceiver logic (GTL) [10]. The CMOS reduced-swing trans- ceivers have limited speed, and the CMOS true or pseudo ECL are complicated to design

  16. Integrated CMOS-selenium x-ray detector for digital mammography

    NASA Astrophysics Data System (ADS)

    Andre, Michael P.; Spivey, Brett A.; Martin, Peter J.; Morsell, Arthur L.; Atlas, Eugene; Pellegrino, Tony

    1998-07-01

    This paper describes a novel area detector for direct conversion and readout of the x-ray energy that eliminates multiple conversions and coupling stages which degrade performance. The pixel array and readout electronics are fabricated on the same piece of silicon. The detector consists of a uniform layer (approximately 300 micrometers) of amorphous selenium alloy vapor-deposited on an electronic readout array fabricated using conventional complementary metal oxide semiconductor (CMOS). The CMOS array features 66 micrometer pixels in a 1024 X 832 array providing a 5.5 X 6.75 cm image area. Each pixel has active circuitry including signal amplification, pixel selection and reset, while peripheral circuitry on one end of the array provides shift registers, sample and hold and multiplexing. The CMOS readout array was fabricated at a standard facility on a 10-cm diameter silicon wafer using 2 micrometer CMOS process. Fifteen separate image sensors were assembled for evaluation in a 3 X 5 format to provide a 20 X 27 cm composite field of view. Missing data between sensors is recovered by acquiring three sub-exposures, between which the array is translated diagonally approximately 2 mm. Total exposure time for an average breast is less than one second. Conversion efficiency was found to be approximately 120 electrons per absorbed x-ray (19 keV average). Electronic readout noise was measured to be 2.4 ADU corresponding to approximately 500 electrons. Detective quantum efficiency was found to be 0.65 at low spatial frequency (0.25 lp/mm) and at 0.2 at high spatial frequency (8 lp/mm) for x-ray fluence ranging from 5 - 35 mR. Images of an ACR phantom show visualization of all of the fibers, specks and masses when displayed with a linear lookup table on a high-resolution monitor. These studies demonstrated that there is a slight but measurable image retention evident as 'ghost' images. The two most effective means to reduce this effect are flushing the sensors with infrared light or x-rays between exposures and reversing the applied voltage on the selenium layer. A number of improvements designed to increase sensitivity and reduce noise also have been identified and are being implemented. Sample images were acquired from four volunteer human subjects at exposure factors identical to their film-screen mammograms. The results suggest that the detector performance is suitable for further clinical investigation.

  17. An integrated CMOS micromechanical resonator high-Q oscillator

    Microsoft Academic Search

    Clark T.-C. Nguyen; Roger T. Howe

    1999-01-01

    A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

  18. A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR

    E-print Network

    Dudek, Piotr

    A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR Piotr Dudek and Peter J. Hicks functions as an analogue microprocessor (AµP). The AµP executes software programs, in a way akin to a digital microprocessor, while nevertheless operating on analogue sampled data values. This enables

  19. 2210 Experiment 13 CMOS Logic T. Roppel Nov. 2009 1

    E-print Network

    Niu, Guofu

    as a function of the input voltage over the range of 0 to +5 V. Use the Bit-Bucket variable DC source to provide) does your inverter switch logic levels? (b) What are the output logic level voltages? (c) What logic inverter circuit is shown in Fig. 1. Figure 1. CMOS logic inverter. When MP is on, MN is off

  20. Intensity Histogram CMOS Image Sensor for Adaptive Optics

    E-print Network

    Cauwenberghs, Gert

    Intensity Histogram CMOS Image Sensor for Adaptive Optics Yu M. Chi, Gary Carhart , Mikhail A imaging mode and 4.6mW in high-speed histogram mode. Applications include real-time adaptive optics control for laser communications. I. INTRODUCTION Adaptive optical systems are highly useful