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1

A high gain n-well\\/gate tied PMOSFET image sensor fabricated from a standard CMOS process  

Microsoft Academic Search

The performance of a high gain photodetector fabricated using a standard 0.8-?m, triple metal, n-well CMOS process is reported, The photodetector is formed by connecting the gate of the PMOSFET and n-well together while keeping both floating. The depletion region induced by the floating gate and the well-to-substrate p-n junction separate the optically generated electron-hole pairs in the direction perpendicular

Weiquan Zhang; Mansun Chan

2001-01-01

2

A low cost uncooled infrared microbolometer focal plane array using the CMOS n-well layer  

Microsoft Academic Search

This paper reports a low-cost, 256-pixel uncooled infrared microbolometer focal plane array (FPA) implemented using a 0.8 ?m CMOS process where the n-well layer is used as the active microbolometer material. The suspended n-well structure is obtained by simple front-end bulk etching of the fabricated CMOS dies, while the n-well region is protected from etching by electrochemical etch-stop technique within

Deniz Sabuncuoglu Tezcan; Selim Eminoglu; Orhan Sevket Akar; Tayfun Akin

2001-01-01

3

A novel high-gain CMOS image sensor using floating N-well\\/gate tied PMOSFET  

Microsoft Academic Search

The development of low power CMOS imaging systems has received a lot of attention. The main obstacle comes from the low responsivity and unscalability of the photo sensor. In this work, we have designed and fabricated a highly responsive photo sensor from a standard MOSIS HP0.8 ?m n-well CMOS process. The photo sensor is obtained by connecting the n-well with

Weiquan Zhang; Mansun Chan; P. K. Ko

1998-01-01

4

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors  

Microsoft Academic Search

This paper is devoted to the study of total ionizing dose effects in deep N-well (DNW) CMOS monolithic active pixel sensors (MAPS) for particle tracking fabricated in a STMicroelectronics 130 nm process. DNW-MAPS samples were exposed to gamma-rays up to a final dose of 1100 krad(SiO2) and then subjected to a 100degC annealing cycle. Ionizing radiation tolerance was tested by

Lodovico Ratti; Claudio Andreoli; Luigi Gaioni; Massimo Manghisoni; Enrico Pozzati; Valerio Re; Gianluca Traversi

2009-01-01

5

Status and perspectives of deep N-well 130 nm CMOS MAPS  

NASA Astrophysics Data System (ADS)

Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices are fabricated in a commercial 130 nm CMOS process, and the triple well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. Because of the high integration density of such a technology, complex digital functions can be included in each pixel, implementing a sparsified readout architecture of the pixel matrix with time stamping. This paper reviews the features of the ``ILC class'' and ``SuperB class'' MAPS devices, discussing their different design in terms of pixel pitch, analog signal processing, and digital readout architecture. For SuperB, a data-driven, continuously operating readout scheme was adopted along with a macropixel matrix arrangement, whereas for the ILC the matrix is read out in the long intertrain period. In both versions, the address of hit pixels is transmitted off-chip along with the time stamp. The experimental performance of the chips provides an assessment of the Deep N-Well MAPS potential in view of future applications. The paper also discusses the way forward in the development of these devices, outlining the issues that have to be tackled to design full size Deep N-Well MAPS for actual experiments. These sensors could take advantage from technological advances in microelectronic industry, such as vertical integration. The impact of these new technologies on the design and performance of DNW pixel sensors could be large, with potential benefit for various device features, from the charge collection properties to the digital readout architecture.

Re, Valerio

2009-03-01

6

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector  

NASA Astrophysics Data System (ADS)

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-12-01

7

CMOS Process Monitor  

NASA Astrophysics Data System (ADS)

A CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Jenings, G. A.; Hicks, K. A.

1988-02-01

8

Low-cost uncooled infrared detectors in CMOS process  

Microsoft Academic Search

This paper reports the implementation and comparison of two low-cost uncooled infrared microbolometer detectors that can be implemented using standard n-well CMOS processes. One type is based on a suspended n-well resistor, which is implemented in a 0.8?m CMOS process and has a pixel size of 80?m×80?m with a fill factor of 13%; and the other type is based on

Selim Eminoglu; Deniz Sabuncuoglu Tezcan; M. Yusuf Tanrikulu; Tayfun Akin

2003-01-01

9

Low 1\\/f noise and DC offset RF mixer for direct conversion receiver using parasitic vertical NPN bipolar transistor in deep n-well CMOS technology  

Microsoft Academic Search

RF characteristics of the parasitic vertical NPN bipolar junction transistor (BJT) available in 0.18 ?m foundry deep n-well CMOS technology are reported for the first time. The experimental results show that the vertical NPN BJT has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of early voltage, 2.3 GHz

Ilku Nam; Young Jin Kim; Kwyro Lee

2003-01-01

10

In situ characterization of CMOS post-process micromachining  

Microsoft Academic Search

We have developed and demonstrated a new methodology for in situ monitoring and characterization of CMOS post-process micromachining utilizing integrated circuits and micromachine test-structures. In our demonstration, the circuits provide automated readout of N-well resistors surrounding each of the 140 test pit structures at up to 14,000 samples per second per device during the post-process silicon etch and, thus, also

Brett Warneke; Kristofer S. J. Pister

2001-01-01

11

End-of-fabrication CMOS process monitor  

NASA Technical Reports Server (NTRS)

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

12

High Energy Ion Implantation for C-MOS Isolation N-Wells Technology: Some Problems Related to the Use of Multicharged Phosphorous Ions in an Industrial Context.  

National Technical Information Service (NTIS)

It has been shown that high energy ion implantation can be a very attractive technique for the realisation of isolation wells in C-MOS technology. This technique needs high energy ion implantation equipment which is still rare and expensive, so the use of...

P. Spinelli J. Escaron A. Soubie M. Bruel

1984-01-01

13

Low-cost small-pixel uncooled infrared detector for large focal plane arrays using a standard CMOS process  

Microsoft Academic Search

This paper reports the development of a low-cost, small pixel uncooled infrared detector using a standard CMOS process. The detector is based on a suspended and thermally isolated p+-active\\/n-well diode whose forward voltage changes due to an increase in the pixel temperature with absorbed infrared radiation. The detector is obtained with simple post-CMOS etching steps on dies fabricated using a

Selim Eminoglu; M. Yusuf Tanrikulu; Deniz S. Tezcan; Tayfun Akin

2002-01-01

14

Schottky barrier diodes for millimeter wave detection in a foundry CMOS process  

Microsoft Academic Search

CoSi2-Si Schottky barrier diodes on an n-well and on a p-well\\/substrate are fabricated without a guard ring in a 130-nm foundry CMOS process. The nand p-type diodes with an area of 16×0.32×0.32 ?m2 achieve cutoff frequencies of ?1.5 and ?1.2 THz at 0-V bias, respectively. These are the highest cutoff frequencies for Schottky diodes fabricated in foundry silicon processes. The

Swaminathan Sankaran; Kenneth K. O

2005-01-01

15

An Integrated Circuit for the in Situ Characterization of CMOS Best-Process Micromachining  

Microsoft Academic Search

We have developed an integrated circuit for in situ monitoring and characterization of CMOS post-process micromachining. In our demonstration, the circuit provides automated readout of N-well resistors surrounding each of 140 micromachining test structures at up to 14,000 samples per second per device during the post-process silicon etch. We use this circuit to examine the effect of pit size, surrounding

Brett Warneke; Kristofer S. J. Pister

2000-01-01

16

An approach to the optical interconnect made in standard CMOS process  

NASA Astrophysics Data System (ADS)

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-?m standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

Changliang, Yu; Luhong, Mao; Xindong, Xiao; Sheng, Xie; Shilin, Zhang

2009-05-01

17

Fabrication of the planar angular rotator using the CMOS process  

Microsoft Academic Search

This investigation proposes a novel planar angular rotator fabricated by the conventional CMOS process. Following the 0.6 ?m SPTM (single poly triple metal) CMOS process, the device is completed by a simple post-process with maskless etching. The suspension unit rotates around its geometric center with electrostatic actuation. In addition to having a single rotatory component, 2×2 and 3×3 arrayed components

Hunrzlin Chen; Chienliu Chang; Kaihsiang Yen; Huiwen Huang; Jinhung Chio; Chingyi Wu; Peizen Chang

2000-01-01

18

Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source  

NASA Astrophysics Data System (ADS)

We present a study of radiation effects on MOSFET transistors irradiated with a 60Co source to a total absorbed dose of 1.5 Mrad. The transistor test structures were manufactured using a commercial 150 nm CMOS process and are composed of transistors of different types (NMOS and PMOS), dimensions and insulation from the bulk material by means of deep n-wells. We have observed a degradation of electrical characteristics of both PMOS and NMOS transistors, namely a large increase of the leakage current of the NMOS transistors after irradiation.

Carna, M.; Havranek, M.; Hejtmanek, M.; Janoska, Z.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2014-06-01

19

IGBT scaling principle toward CMOS compatible wafer processes  

NASA Astrophysics Data System (ADS)

A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

Tanaka, Masahiro; Omura, Ichiro

2013-02-01

20

A new process for CMOS MEMS capacitive sensors with high sensitivity and thermal stability  

Microsoft Academic Search

Structure curling induces thermal instability into CMOS MEMS capacitive sensors. The charging effect during reactive ion etching damages the existing on-chip MOS transistors and drastically reduces the yield rate of chips. This paper presents a novel post-CMOS process that solves the problems and leads to CMOS MEMS capacitive sensors with high sensitivity and thermal stability. The novel process was demonstrated

S. S. Tan; C. Y. Liu; L. K. Yeh; Y. H. Chiu; Klaus Y. J. Hsu

2011-01-01

21

BiCMOS process integration and device optimization: Basic concepts and new trends  

Microsoft Academic Search

Contents The process integration issues and the aspects of CMOS and bipolar transistor optimization in BiCMOS technology are reviewed in this article. In one section, a sample BiCMOS fabrication process is discussed to provide an entry to the subject for readers who are not familiar with the details and the nomenclature of semiconductor technology. The remainder of the paper deals

J. N. Burghartz

1996-01-01

22

Characterization of a monolithic silicon MEMS technology in standard CMOS process  

Microsoft Academic Search

This paper presents a comparative analysis between two specific post-processing techniques (RIE dry etching and TMAH wet etching) that are suitable for implementing a monolithic CMOS compatible MEMS fabrication technology. Further, an experimental investigation is presented which details the fabrication of MEMS structures by TMAH post etching of a CMOS chip fabricated in a standard AMI 1.5 micrometers CMOS process.

Kuntao Ye; Fred R. Beyette

2001-01-01

23

Bridging Defects Resistance Measurements in a CMOS Process  

Microsoft Academic Search

Measurements on process-related defect nionitwing ,wcijers are presented in order to euuluute the i,csisluiict. ,ualu,e of b ridyzng deJects zn CMOS VLSI circu~ts. 'I'he inethodoloyy u sed is dlustrated and statzstics OIL the 1.esistance values are p resented. As a result, the vast niajoi-zty of the measured brzdges have a 1o.w 7.eszsta.nce. Only a small percentage of the brzdges has

Rosa Rodríguez-montañés; Joan Figueras; Eric Bruls

1992-01-01

24

Translinear signal processing circuits in standard CMOS FPAA  

Microsoft Academic Search

In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 ?? 5 cell array. As implementation examples, a four-quadrant multiplier with five decade

L. Martinez-Alvarado; J. Madrenas; Daniel Fernández

2009-01-01

25

A low-cost uncooled infrared microbolometer detector in standard CMOS technology  

Microsoft Academic Search

This paper reports the development of a low-cost uncooled infrared microbolometer detector using a commercial 0.8 ?m CMOS process, where the CMOS n-well layer is used as the infrared sensitive material. The n-well is suspended by front-end bulk-micromachining of the fabricated CMOS dies using electrochemical etch-stop technique in TMAH. Since this approach does not require any lithography or infrared sensitive

Deniz Sabuncuoglu Tezcan; Selim Eminoglu; Tayfun Akin

2003-01-01

26

Optimal fabrication process for mems pressure sensor by 8inch CMOS  

Microsoft Academic Search

We have developed the MEMS piezo pressure sensor by utilizing CMOS process modules and tool-sets to challenge faster time to market and faster time to volume with high yield. The MEMS device has the commonality of process, tools, material, and design system and qualification method with 0.35um CMOS device. The CMOS integration approach also showed the high quality as small

Tadashi Kai; Katsuyuki Inoue; Y. Adachi

2010-01-01

27

Self-calibrated humidity sensor in CMOS without post-processing.  

PubMed

A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

28

Evaluation of a CMOS/SOS Process Using Process Validation Wafers.  

National Technical Information Service (NTIS)

The objective of this work was to determine baseline electrical parameters that could be used to evaluate a fabrication process. Two lots of wafers containing NBS-16 test chips were fabricated at a commercial vendor in a radiation-hard, CMOS/SOS process. ...

J. S. Suehle L. W. Linholm G. M. Marshall

1982-01-01

29

Novel color processing architecture for digital cameras with CMOS image sensors  

Microsoft Academic Search

This paper presents a color processing architecture for digital color cameras utilizing complementary metal oxide semiconductor (CMOS) image sensors. The proposed architecture gives due consideration to the peculiar aspects of CMOS image sensors and the human visual perception related to the particular application of digital color photography. A main difference between the proposed method arid the conventional systems is the

Chaminda Weerasinghe; Wanqing Li; Igor Kharitonenko; Magnus Nilsson; Sue Twelves

2005-01-01

30

Noise performance and ionizing radiation tolerance of CMOS Monolithic Active Pixel Sensors using the 0.18?m CMOS process  

NASA Astrophysics Data System (ADS)

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few ?m), a detection efficiency of gtrsim99.9%, very low material budget (0.05% X0) and good radiation tolerance (gtrsim 1 Mrad, gtrsim 1014 neq/cm2) [1]. This recommends them as an interesting technology for various applications in heavy ion and particle physics. For the vertex detectors of CBM and ALICE, we are aiming at developing large scale sensors with an integration time of 30?s. Reaching this goal is eased by features available in CMOS-processes with 0.18?m feature size. To exploit this option, some sensor designs have been migrated from the previously used 0.35?m processes to this novel process. We report about our first findings with the devices obtained with a focus on noise and the tolerance to ionizing radiation.

Doering, D.; Baudot, J.; Deveaux, M.; Linnik, B.; Goffe, M.; Senyukov, S.; Strohauer, S.; Stroth, J.; Winter, M.

2014-05-01

31

Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process  

Microsoft Academic Search

The effects of the gate-oxide reliability of MOSFETs on operational amplifiers were investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The tested operating conditions include unity-gain buffer (close-loop configuration) and comparator (open-loop configuration) under different input frequencies and signals. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, were measured

Jung-Sheng Chen; Ming-Dou Ker

2005-01-01

32

An optically differential reconfigurable gate array using a 0.18 ?m CMOS process  

Microsoft Academic Search

This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18?m-5 metal CMOS process technology. ODRGA is a type of field programmable gate arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35?m-3 metal CMOS process technology, their gate-density remains

M. Watanabe; Fuminori Kobayashi

2004-01-01

33

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process  

NASA Astrophysics Data System (ADS)

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

2013-04-01

34

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process.  

PubMed

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

35

Integration of solid-state nanopores in a 0.5 ?m cmos foundry process  

PubMed Central

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

36

A novel RFID tag chip with temperature sensor in standard CMOS process  

Microsoft Academic Search

This paper presents a novel RFID tag chip with temperature sensor in 0.18?m standard CMOS process. It consists of four blocks: RF\\/analog front-end circuit, 192-bit non-volatile memory (NVM), temperature sensor and digital baseband circuit. A CMOS UHF rectifier with dynamic bias using switch capacitor is proposed to improve the efficiency of rectification, while avoiding using costly Schottky diodes. We design

Qi Zhang; Peng Feng; Shenghua Zhou; Zhiqing Geng; Nanjian Wu

2010-01-01

37

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

38

CMOS Programmable Imager Implementing Pre-Processing Operations  

Microsoft Academic Search

The CMOS Imager presented integrates a 2D photoreceptor array with a nine input analog processor on the same focal plane. The analog processor is fully programmable, performing multiply-accumulate operations. A VLSI implementation of spatial convolution operations performed on images is presented. A modified photoreceptor is presented that is based on current mode for signal transmission, thus decreasing the effect of

Khaled N. Salama; Ahmed M. El-Tawil; Ahmed M. Soliman; Hassan O. Elwan

1999-01-01

39

Fabrication of a grating light modulator using standard CMOS processes  

Microsoft Academic Search

A deformable grating light modulator (GLM) also known as a grating light valve TM (GLV) offers fast switching time, low loss, and potential simplicity in fabrication, which are desirable for free-space optical switching systems. The purpose of this paper is to report on the fabrication of a GLM using standard CMOS technology and its simulation results, for use as both

Araya Pothisorn; Alex J Hariz; Bruce Wedding; Opas Trithaveesak

2011-01-01

40

A Unified C-BiCMOS Buffer Driver Using a CMOS\\/SOI Process for High Speed and Low Energy Operation  

Microsoft Academic Search

A new operation mode for a lateral unified C (Complementary) -BiCMOS buffer driver circuit based on a partially depleted CMOS\\/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a n- or p-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFET, with a normal pull-up or pull-down MOSFET as a

Takashi Hamahata; Toshiro Akino

41

CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe.  

National Technical Information Service (NTIS)

Neural probes are made on silicon substrate using a micromachining process with low temperature steps only. A deep silicon etch ('boschh') process was used for the probe shaping. CMOS compatibility of the process was checked and reported in this paper. Te...

S. K. An S. J. Oh S. J. Kim

2001-01-01

42

A new process for CMOS MEMS capacitive sensors with high sensitivity and thermal stability  

NASA Astrophysics Data System (ADS)

Structure curling induces thermal instability into CMOS MEMS capacitive sensors. The charging effect during reactive ion etching damages the existing on-chip MOS transistors and drastically reduces the yield rate of chips. This paper presents a novel post-CMOS process that solves the problems and leads to CMOS MEMS capacitive sensors with high sensitivity and thermal stability. The novel process was demonstrated with a capacitive accelerometer in 0.35 µm CMOS technology. The accelerometer contains a thermally stable MEMS sensor and an on-chip CMOS sensing circuit with a chopper stabilization scheme. The temperature stabilization was achieved by forming a thick single-crystal silicon (SCS) layer at the bottom of the multi-layer MEMS structure. No leakage current due to charge damage was ever observed in the sample chips. The proposed process also led to minimal undercut of the SCS layer after MEMS structure release. The sensitivity of the accelerometer is 595 mV g-1, and the overall noise floor is 50 µg Hz-1/2 which corresponds to an effective capacitance noise floor of 0.024 aF Hz-1/2. The zero-g temperature coefficient of the accelerometer output voltage is only 1 mV °C-1 in the temperature range from 0 to 70 °C, which corresponds to an effective acceleration variation rate of 1.68 mg °C-1.

Tan, S. S.; Liu, C. Y.; Yeh, L. K.; Chiu, Y. H.; Hsu, Klaus Y. J.

2011-03-01

43

High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process  

Microsoft Academic Search

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting

Koen De Munck; Deniz Sabuncuoglu Tezcan; Tom Borgers; Wouter Ruythooren; P. De Moor; S. Sedky; C. Toccafondi; J. Bogaerts; C. Van Hoof

2006-01-01

44

High performance NPN BJTs in standard CMOS process for GSM transceiver and DVB-H tuner  

Microsoft Academic Search

We report a high performance NPN bipolar junction transistor (BJT) processed in standard CMOS process that is applied to realize the direct conversion GSM receiver and DVB-H tuner. Through the variation of the base doping profile, performance of the NPN BJT has been tailored to meet the requirements of the RF circuits. Careful optimization is performed using both simulation and

Jedon Kim; Hansu Oh; Chulho Chung; Joo-Hyun Jjeong; Hyunwoo Lee; Seok-Hee Hwang; In-Chul Hwang; Young-Jin Kim; Kyushik Hong; Eunseung Jung; Kwang-Pyuk Suh

2006-01-01

45

The fabrication process and characteristics of light loss free zero-space microlenses for CMOS image sensor  

Microsoft Academic Search

We report a novel method to fabricate zero-space microlenses without light loss for CMOS image sensor. Classical microlenses for CMOS image sensor, adopted for achieving high quality images by providing appropriate propagation and collection of light onto photo diode, are typically formed by patterning and thermal flowing process of square type photo resist array sequentially. In that process, sufficient spaces

Sang U. Lee; Jeong L. Park; Jae S. Choi; Jeong G. Lee

2005-01-01

46

A merged process for thick single-crystal Si resonators and BiCMOS circuitry  

Microsoft Academic Search

A simple process has been developed which combines thick single-crystal Si micromechanical devices with a bipolar complimentary metal-oxide-semiconductor (BiCMOS) integrated circuit process. This merged process allows the integration of Si mechanical resonators as thick as 11 ?m with any integrated circuit process with the addition of only a single masking step. The process does not require the use of Si

J. W. Weigold; A.-C. Wong; C. T.-C. Nguyen; S. W. Pang

1999-01-01

47

Application of RTA to a 0.8-?m BiCMOS process  

NASA Astrophysics Data System (ADS)

RTA has been established as a key process element in a sub-micron BiCMOS flow. The major advantage of RTA is that a temperature pulse > 1000 degree(s)C can be used to break-up the interfacial oxide in the polysilicon emitter contact to provide enhanced current gain with low-emitter resistance but with little impact on the CMOS. The RTA emitter anneal also serves to simultaneously flow BPSG to planarize the wafer prior to metallization. Contact reflow is also advantageous for a tapered structure to improve metal step-coverage.

Reuss, Robert H.

1994-02-01

48

A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process  

Microsoft Academic Search

A novel programmable element has been developed and evaluated for state of the art CMOS processes. This element is based on agglomeration of the Ti-silicide layer on top of poly fuses. Various aspects of this programmable device including characterization and optimization of physical and electrical aspects of the element, programming yield, and reliability have been studied. Development of a novel

Mohsen Alavi; Mark Bohr; Jeff Hicks; Martin Denham; Allen Cassens; Dave Douglas; Min-Chun Tsai

1997-01-01

49

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS  

Microsoft Academic Search

The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

Martin von Arx; Oliver Paul; Henry Baltes

2000-01-01

50

Performance and applications of a two axes fluxgate magnetic field sensor fabricated by a CMOS process  

Microsoft Academic Search

Fluxgate magnetic field sensors offer a wide field of applications in the nT and ?T range. The thin film fabrication of the solenoids in the metalization layers and the core in the intermetal dielectrics of a CMOS process has been successfully developed in recent years. Using these monolithic integrated two axes fluxgate magnetic field sensors a system has been built,

H Grüger; R Gottfried-Gottfried

2001-01-01

51

Coupling Advanced Atomistic Process and Device Modeling for Optimizing Future CMOS Devices  

Microsoft Academic Search

For the first time, we show the coupling between advanced atomistic process and device modeling and its applicability for 65nm PMOS and NMOS technology. This technique can be used to simulate and get some important insights to improve and optimize future CMOS devices

B. Colombeau; S. H. Yeong; S. M. Pandey; F. Benistant; M. Jaraiz; S. Chui

2006-01-01

52

A 1-V CMOS Current Reference With Temperature and Process Compensation  

Microsoft Academic Search

A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, VREF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, IREF , nearly independent of temperature by mutual

Abdelhalim Bendali; Yves Audet

2007-01-01

53

Characterization of sub-100 nm CMOS process using screening experiment technique  

NASA Astrophysics Data System (ADS)

The relative sensitivity of the CMOS device parameters on various process steps are evaluated through a systematic study. A large set of 21 process parameters that could affect the device behavior have been investigated through Plackett-Burman screening design of experiment for 100 nm CMOS disposable spacer process technique. First-order regression models obtained from the experimental data in terms of these 21 process parameters, for threshold voltage Vtsat, subthreshold slope SSsat, on-state current Idsatdrive, and leakage current Idsatleak in the saturation region, are used to determine the statistical significance of each process parameters in terms of their rank. The ranking order, indicating the statistical significance of the respective process parameters, differs between NMOS and PMOS devices. Further, a sub-set of top 10 significant process parameters are picked for NMOS device, to perform Monte-Carlo process/device simulations to estimate the statistics of the device parameters. Monte-Carlo process/device simulations were also performed in terms of all the 21 process parameters, and the statistics are again evaluated. The statistics that are computed with 10 and 21 parameters are indeed close, implying the variability arising from the remaining 11 relatively insignificant parameters is negligible. This choice of the subset of 10 significant process parameters simplifies the Design of Experiment, for second-order response-surface-modeling for a detailed study of the CMOS process.

Srinivasaiah, H. C.; Bhat, Navakanta

2005-03-01

54

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process  

Microsoft Academic Search

A new gateless anti-fuse cell with 45 nm CMOS fully compatible process has been developed for advanced programmable logic applications. This gateless anti-fuse cell processed by pure logic process and decoupled with logic gate oxide has a highly stable and five orders of on\\/off current window. It also exhibits superior program performance by only 5 V operation with no more

Yi-Hung Tsai; Hsin-Ming Chen; Hsin-Yi Chiu; Hung-Sheng Shih; Han-Chao Lai; Ya-Chin King; Chrong Jung Lin

2007-01-01

55

A discrete-time Bluetooth receiver in a 0.13?m digital CMOS process  

Microsoft Academic Search

A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13?m digital CMOS process.

K. Muhammad; D. Leipold; B. Staszewski; Y.-C. Ho; C. M. Hung; K. Maggio; C. Fernando; T. Jung; J. Wallberg; J.-S. Koh; S. John; I. Deng; O. Moreira; R. Staszewski; R. Katz; O. Friedman

2004-01-01

56

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing  

PubMed Central

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely.

Bravo, Ignacio; Balinas, Javier; Gardel, Alfredo; Lazaro, Jose L.; Espinosa, Felipe; Garcia, Jorge

2011-01-01

57

Efficient smart CMOS camera based on FPGAs oriented to embedded image processing.  

PubMed

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L; Espinosa, Felipe; García, Jorge

2011-01-01

58

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array  

PubMed Central

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 ?m CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Lopez-Huerta, Francisco; Herrera-May, Agustin L.; Estrada-Lopez, Johan J.; Zuniga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

59

P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP  

Microsoft Academic Search

In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual-VTh assignment based on a novel statistical Design of Experiments-Integer Linear

Garima Thakral; Saraju P. Mohanty; Dhruva Ghai; Dhiraj K. Pradhan

2010-01-01

60

A process\\/physics-based compact model for nonclassical CMOS device and circuit design  

Microsoft Academic Search

A process\\/physics-based compact model (UFDG) for nonclassical MOSFETs having ultra-thin Si bodies (UTB) is overviewed. The model, in essence, is a compact Poisson–Schrödinger solver, including accountings for short-channel effects, and is applicable to nanoscale fully depleted (FD) SOI MOSFETs as well as generic double-gate (DG) devices. The utility of UFDG in nonclassical CMOS device design, as well as circuit design,

J. G. Fossum; L. Ge; M.-H. Chiang; V. P. Trivedi; M. M. Chowdhury; L. Mathew; G. O. Workman; B.-Y. Nguyen

2004-01-01

61

UV-enhanced photodetector with nanocrystalline-TiO2 thin film via CMOS compatible process  

Microsoft Academic Search

This research presents nanocrystal titaniumdioxide (nanocrystal-TiO2) film deposition technique with CMOS compatible process [1] to extend the optical response bandwidth of silicon based photodetecting devices toward ultraviolet range [2]. The thin films were initially deposited as Titanium Nitride (TiN) using DC magnetron reactive sputtering system. It was then annealed under nitrogen atmosphere at 800°C. After analyzing crystal structures and surface

W. Bunjongpru; P. Panprom; S. Porntheeraphat; R. Meananeatra; W. Jeamsaksiri; A. Srisuwan; W. Chaisriratanakul; E. Chaowicharat; A. Pankiew; C. Hruanun; A. Poyai; J. Nukeaw

2011-01-01

62

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering  

Microsoft Academic Search

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential

C.-H. Ge; C.-C. Lin; C.-H. Ko; C.-C. Huang; Y.-C. Huang; B.-W. Chan; B.-C. Perng; C.-C. Sheu; P.-Y. Tsai; L.-G. Yao; C.-L. Wu; C.-J. Chen; C.-T. Wang; S.-C. Lin; Y.-C. Yeo; C. Hu

2003-01-01

63

Comparison of nonvolatile memory cells for molybdenum gate analog BeCMOS process  

Microsoft Academic Search

Floating gate nonvolatile memory cells fabricated with a molybdenum gate triple well BeCMOS process are described. Programming, endurance and retention characteristics of two types of cells are compared. The first type is programmed through the gate oxide with Fowler-Nordheim tunnelling and the second through the control gate - floating gate silicon nitride dielectric with Frenkel-Poole emission. The measured endurance for

H. Ronkainen; K. Theqvist

2002-01-01

64

Circuit design of voltage mode center of gravity defuzzifier in CMOS process  

Microsoft Academic Search

In this paper a voltage input-output center of gravity (COG) defuzzifier circuit is designed without using divider in CMOS 0.35 ?m process. We have used transconductance amplifier (TCA) structure as a multiplier with voltage-input - current-output for implementation of defuzzifier by exploiting of voltage follower aggregation principle. Good results have been obtained from the point of accuracy and speed.

Pourya Hoseini; Abdollah Khoei; Khayrollah Hadidi

2010-01-01

65

A Low-Power Robust Humidity Sensor in a Standard CMOS Process  

Microsoft Academic Search

This paper presents a low-cost thermal-conductivity-based humidity sensor implemented using a 0.6-mum CMOS process, where suspended p-n junction diodes are used as the humidity-sensitive elements. The measurement method uses the difference between the thermal conductivities of air and water vapor at high temperatures by comparing the output voltages of two heated and thermally isolated diodes; one of which is exposed

Burak Okcan; Tayfun Akin

2007-01-01

66

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Woo, D. S.

1977-01-01

67

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM  

NASA Technical Reports Server (NTRS)

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

68

RF-MEMS switching devices using vertical comb-drive actuation in the CMOS process  

NASA Astrophysics Data System (ADS)

Radio frequency micro-electro-mechanical system (RF-MEMS) switching devices using vertical comb-drive actuation toward low-voltage actuation, fast response are presented in this paper. The switching devices, which comprise comb-drive electrodes, are actuated entirely by the electrostatic forces applied not only for the down-state but also for the up-state. The cost-effective MEMS process compatible with the complementary metal oxide semiconductor (CMOS) process is presented in this paper as well. The fabrication process is composed by adapting the CMOS 0.18 µm back end of line (BEOL) process on 200 mm wafers. The MEMS process in the CMOS process enables the realization of passive devices integrated with active devices, which is effective for size and cost reduction. Two metal interconnection layers in the BEOL process are used for the MEMS process. Interconnection aluminum and inter-layer dielectric tetraethoxysilane (TEOS) are used as MEMS structural material and sacrificial material, respectively. The chemical mechanical polishing (CMP) process is implemented to planarize the sacrificial material surface. The structures were fabricated using a simple low-cost two-mask process. The characteristics of switching capacitors, C-V, RF performance, switching speed and continuous drive cycles are measured on the fabricated devices. The capacitance ratio for the down-state/up-state is Cdown/Cup = 5.4. The characteristics of switching speed response/actuation voltage in the down-state and up-state are 4.5 µs/5 V and 8.0 µs/5 V, respectively. The switching speed is stable up to 107 cycles in spite of the fact that the unipolar voltage speed is stable up to 107 cycles.

Naito, Y.; Nakamura, K.; Onishi, K.

2010-04-01

69

High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25? Standard CMOS Process  

Microsoft Academic Search

This paper reports on a low-voltage CMOS power MOSFET layout technique, implemented in a 0.25 mum, 5-metal layers CMOS process that is suitable for high speed switching power devices. The proposed hybrid waffle (HW) layout technique organizes MOSFET fingers in a square grid (waffle) arrangement. It is designed to provide an effective trade-off between the width of diagonal source\\/drain metal

Abraham Yoo; Marian Chang; Olivier Trescases; Wai Tung Ng

2008-01-01

70

0.8V ultralow-power CMOS analog multiplexer for remote biological and chemical signal processing  

NASA Astrophysics Data System (ADS)

A CMOS analog multiplexer circuit has been designed for operation at 0.8 V. The circuit consists of transmission gates as switches and an inverter. MOSFETs in the design of multiplexer use the dynamic body bias method. The forward body bias is limited to no more than 0.4 V to avoid CMOS latch-up. The reverse body bias is limited to 0.4 V and allows the MOSFET to turn-off fully and suppresses the sub-threshold leakage. The improved dynamic threshold MOSFET (DTMOS) inverter is engaged to achieve low voltage operation. The CMOS multiplexer chip was designed in standard 1.5 ?m n-well CMOS technology and simulated using SPICE. Excellent agreement was obtained between the simulated output waveform and corresponding experimentally measured behavior. The power dissipation is close to 70 nW and signal-to-leakage ratio is 120 dB. The proposed low voltage, ultra-low power analog multiplexer would find application for on-chip neural microprobes and other applications.

Zhang, Chuang; Srivastava, Ashok; Ajmera, Pratul K.

2004-07-01

71

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit  

Microsoft Academic Search

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well\\/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal

Michael L Simpson; Gary S Sayler; Greg Patterson; David E Nivens; Eric K Bolton; James M Rochelle; James C Arnott; Bruce M Applegate; Steven Ripp; Michael A Guillorn

2001-01-01

72

Low-noise silicon avalanche photodiodes fabricated in conventional CMOS technologies  

Microsoft Academic Search

We present a simple design technique that allows the fabrication of UV\\/blue-selective avalanche photodiodes in a conventional CMOS process. The photodiodes are fabricated in a twin tub 0.8 ?m CMOS technology. An efficient guard-ring structure is created using the lateral diffusion of two n-well regions separated by a gap of 0.6 ?m. When operated at a multiplication gain of 20,

Alexis Rochas; Alexandre R. Pauchard; P.-A. Besse; D. Pantic; Z. Prijic; R. S. Popovic

2002-01-01

73

A 4\\/spl times\\/64 pixel CMOS image sensor for 3-D measurement applications  

Microsoft Academic Search

Abstract A4x64 pixel array CMOS image ,sensor which ,can capture three-dimensional images has been integrated in a0.5?m n-well standard CMOS process. It is based on time-of-flight method ,and employs,an active ,laser pulse illumination,at 900nm ,optical ,wavelength. ,System bandwidth,is limited by the refreshing time of the active laser source. The sensor employs,the so-called \\

O. Elkhalili; O. M. Schrey; P. Mengel; M. Petermann; W. Brockherde; B. J. Hosticka

2004-01-01

74

A 4×64 pixel CMOS image sensor for 3D measurement applications  

Microsoft Academic Search

A 4×64 pixel CMOS image sensor which can capture three-dimensional images has been integrated in a 0.5?m n-well standard CMOS processes. It is based on time-of-flight method and employs an active laser pulse illumination at 900nm optical wavelength. System bandwidth is limited by the refreshing time of the active laser source. The sensor employs the so-called \\

O. M. Schrey; O. Elkhalili; P. Mengel; M. Petermann; W. Brockherde; B. J. Hosticka

2003-01-01

75

Design of radiation hard CMOS APS image sensors in a 0.35-?m standard process  

NASA Astrophysics Data System (ADS)

A CMOS APS Image sensor test chip was designed employing the physical design techniques of enclosed geometry and guard ring, and according to the design rules of a 0.35-micrometers CMOS standard process that has a gate oxide thickness of approximately 7.0 nm. Three sets of radiation tolerant photodiode active pixels were developed employing these design techniques. They are N-type, and H-type pixels. Each of the pixels is a square pixel with a 16.2 micrometers pitch. The yielded fill-factor is approximately 50 percent. Depending on the pixel-type and the layout, the simulated output voltage swing ranges from 300 mV to 1.1 V. The peripheral circuits, which include decoders, row/column drivers, and I/O pads, were also developed. All NMOS transistors in the peripheral circuits were laid out employing the physical design techniques of enclosed geometry and P-type guard ring. Integrating the pixels and the peripheral circuits into the design of radiation hard CMOS APS image sensor has bene completed. The size of the pixel array is 256 by 256, constituting an imaging area of approximately 4.1 mm X 4.1 mm. The total size of the die is approximately 5.2 mm X 5.0 mm. The total number of the I/O pads is 42. Plans to irradiate these image sensor using Cobalt-60 to determine the level of their radiation hardness are currently being devised.

Eid, Sayed I.; Chan, Tony Y.; Fossum, Eric R.; Tsai, Richard H.; Spagnuolo, Robert; Deily, John J.

2001-05-01

76

Photo-Spectrometer Realized In A Standard Cmos Ic Process  

DOEpatents

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Simpson, Michael L. (Knoxville, TN); Ericson, M. Nance (Knoxville, TN); Dress, William B. (Knoxville, TN); Jellison, Gerald E. (Oak Ridge, TN); Sitter, Jr., David N. (Tucson, AZ); Wintenberg, Alan L. (Knoxville, TN)

1999-10-12

77

Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices  

NASA Astrophysics Data System (ADS)

We demonstrate a novel poly-Si gate engineering by laser thermal process (LTP) to suppress gate depletion for high performance sub-40 nm CMOS devices. To show the full advantage of LTP, an optimized BEOL process has been employed to suppress dopant deactivation and achieve a reduction of electrical inversion gate oxide thickness by 0.1/0.06 nm (PMOS/NMOS), which improves the Ion current by 11/7% (PMOS/NMOS). Furthermore, a novel source-drain rapid thermal annealing (SD-RTA) has been developed to suppress dopant dose loss to achieve a 5% improvement of the Ion current for NMOS.

Yamamoto, T.; Okabe, K.; Kubo, T.; Goto, K.; Morioka, H.; Wang, Y.; Lin, T.; Talwar, S.; Kase, M.; Sugii, T.

2004-11-01

78

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.

1980-01-01

79

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology  

NASA Astrophysics Data System (ADS)

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.

Ajayan, K. R.; Bhat, Navakanta

2012-10-01

80

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation  

NASA Astrophysics Data System (ADS)

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

81

Current mode ADC design in a 0.5-?m CMOS process  

NASA Astrophysics Data System (ADS)

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-?m CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance, this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 ?A. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64 ?A quantization range and a 5 V supply voltage/±256 ?A quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.

Yong, Sun; Fengchang, Lai; Yizheng, Ye

2009-06-01

82

Modeling and Manufacturing of a Micromachined Magnetic Sensor Using the CMOS Process without Any Post-Process  

PubMed Central

The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA.

Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

2014-01-01

83

Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors  

Microsoft Academic Search

In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper

Luigi Gaioni; Massimo Manghisoni; Lodovico Ratti; Valerio Re; Gianluca Traversi

2011-01-01

84

Plasma-induced oxide contamination in a 0.35-um CMOS process  

NASA Astrophysics Data System (ADS)

Plasma contamination in a 0.35 micrometer triple-level metal CMOS process was investigated in response to anomalous dc parametric test data. Electrical PMOS transistor performance and both physical and electrical gate oxide thickness were significantly degraded upon exposure of a sacrificial oxide to a plasma ash following a masked, P-channel threshold adjust ion implant. The contamination was isolated to a specific asher, found to be radial in nature across a wafer, and consistently worse in one of the two chambers used during the ash process. The contamination dramatically reduced the wet etch rate of the sacrificial oxide, leading to incomplete removal prior to gate oxide growth. Increasing the wet strip time of the sacrificial oxide improved the ability to remove this contaminated film, but was limited by minimal field oxide thickness requirements to avoid field inversion. Transferring the ash process to an alternative, low-damage, down-stream asher eliminated the plasma contamination.

Karnett, Marty P.; Zhou, Jingrong; Ghosh, Sumanta; Echtle, Danny; Fritz, L.; Manley, M.; Scott, G.

1996-09-01

85

Design and fabrication of micromirror for MOEMS devices by CMOS-MEMS common process  

NASA Astrophysics Data System (ADS)

This paper would propose the design and fabrication methodology of micro mirror for MOEMS devices by CMOS-MEMS common process of CIC, Taiwan. The outstanding features of CMOS-MEMS are mass production, low connections, high precision and easy to combine the circuit with low noise. A {2X3} opposite type Micro Array Thermal Actuator, MATA, is applied to drive the micro mirror for rotation. Such MOEMS would be as a high precision micro positioning device applied on the micro fabrication equipment. A novel elevating structure for the lift of micro mirror is proposed. Warped suspension beam is originally applied on elevating a micro mirror in this work. A modified elevating structure is proposed to improve the lift of micro mirror from 1.1 ?m to 14 ?m compared to original design. There are three parameters, width, length of the modified elevating structure and the number of single thermal actuators of parallel type MATA, for the performance simulation. The effects of operation voltage varied with three parameters on the displacement of Z axis direction are investigated. The optimum dimension of width, length of modified elevating structure and numbers of single thermal actuator are 10 ?m, 240 ?m and {1x4} MATA, respectively. Finally, comparisons of mask configuration and real part of finished devices are discussed by SEM photos. The surface quality of micro mirror is almost perfect and the material of micro mirror is aluminum.

Tsai, Chien-Chung; Cheng, Pao-Ting; Tseng, Yao-Chen

2005-01-01

86

A robust color signal processing with wide dynamic range WRGB CMOS image sensor  

NASA Astrophysics Data System (ADS)

We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor. The image sensor was fabricated through a 0.18 ?m CMOS technology and has a 45 degrees oblique pixel array, the 4.2 ?m effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY) signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate color processing with a large margin to the sensitivity fluctuation and noise has been achieved.

Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

2011-01-01

87

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

88

AN UNCOOLED MICROBOLOMETER INFRARED DETECTOR IN ANY STANDARD CMOS TECHNOLOGY  

Microsoft Academic Search

This paper reports a new microbolometer structure with the CMOS n-well layer as the active element. The n-well structures are suspended and thermally isolated by post-etching of fabricated and bonded CMOS chips, while the n-well regions are protected from etching by the electrochemical etch-stop technique in a TMAH solution. The characterization results of the fabricated chips show that the n-well

D. S. Tezcan; F. Koçer; T. Akin

1999-01-01

89

CMOS\\/BiCMOS power amplifier technology trend in Japan  

Microsoft Academic Search

Aiming for 2-5GHz band transceiver system on a chip, the integration of RF section has been developed by using conventional CMOS\\/BiCMOS (SiGeCMOS) process. The attempts to integrate power amplifiers (PA's) have been successful for low transmit power system such as Bluetooth, but these attempts are very limited due to the poor power handling capability of FET's in CMOS and the

Noriharu Suematsu; Shintaro Shinjo

2001-01-01

90

Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor  

NASA Astrophysics Data System (ADS)

This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

2013-09-01

91

Analysis of a Floating Gate Metal-Nitride-Metal-Oxide-Silicon Transistor in an Analog BeCMOS Process  

NASA Astrophysics Data System (ADS)

Stacked gate nonvolatile memory cells were tested with a molybdenum gate BeCMOS process. Writing and erasing with Poole-Frenkel conduction and writing with drain avalanche injection are characterised. The measured endurance was found to be more than 10000 cycles and the estimated retention more than 10y. These properties are comparable to polysilicon gate devices.

Ronkainen, Hannu; Theqvist, Kristian

92

Introducing photonic devices for 40Gbits/s wavelength division multiplexing transceivers on 300-mm SOI wafers using CMOS processes  

NASA Astrophysics Data System (ADS)

We demonstrate the feasibility of producing advanced silicon photonic devices for future data communication nodes at 40Gbps using CMOS compatible processes in a 300mm wafer fab. Basic building blocks are shown together with various wavelength division multiplexing solutions. All the devices presented are integrated on 220nm SOI or locally grown epitaxial germanium.

Baudot, Charles; Fédéli, Jean-Marc; Marris-Morini, Delphine; Caire-Remonnay, Boris; Virot, Léopold; Olivier, Ségolène; Myko, André; Grosse, Philippe; Grand, Gilles; Ben Bakir, Badhise; Hartmann, Jean-Michel; Allouti, Nacima; Barnola, Sébastien; Vizioz, Christian; Rivoire, Maurice; Seignard, Aurélien; Vulliet, Nathalie; Souhaité, Aurélie; Messaoudène, Sonia; O'Connor, Ian; Vivien, Laurent; Menezo, Sylvie; Boeuf, Frédéric

2014-03-01

93

An X-Band CMOS Multifunction-Chip FMCW Radar  

Microsoft Academic Search

A fully integrated, miniaturized, low-power frequency-modulated continuous wave (FMCW) multifunction chip realized by typical 1P6M 0.18 mum deep n-well CMOS technology is presented for the first time. The multifunction chip consists of VCO, buffer amplifier, 3-dB power divider, isolators, driving amplifiers, mixer, low-noise amplifier, attenuator, etc., necessary for carrying out the X-band RF signal processing of the FMCW signals interfaced

C. K. C. Tzuang; Chi-Ho Chang; Hsien-Shun Wu; Sen Wang; Si-Xian Lee; Chih-Chia Chen; Chi-Yang Hsu; Kun-Hung Tsai; Johnsea Chen

2006-01-01

94

CMOS foundry implementation of Schottky diodes for RF detection  

Microsoft Academic Search

Schottky diodes for RF power measurement were designed and fabricated using a commercial n-well CMOS foundry process through the MOSIS service. The Schottky diodes are implemented by modifying the SCMOS technology file of the public-domain graphics layout editor, MAGIC, or by explicitly implementing the appropriate CIF layers. The modifications allow direct contact of first-layer metal to the low-doped substrate. Current-voltage

Veljko MilanoviC; Michael Gaitan; Janet C. Marshall; Mona E. Zaghloul

1996-01-01

95

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.  

PubMed

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-01-01

96

High reliability HV-CMOS transistors in standard CMOS technology  

Microsoft Academic Search

A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6?m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds

W. F. Sun; L. X. Shi

2003-01-01

97

Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes  

Microsoft Academic Search

This paper introduces the processing core of a full-custom mixed-signal CMOS chip intended for an active-contour-based technique, the so-called pixel-level snakes (PLS). Among the different parameters to optimize on the top-down design flow our methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a discrete-time cellular neural network with a correspondence between pixel and processing

V. M. Brea; David L. Vilariño; Ari Paasio; Diego Cabello

2004-01-01

98

A discrete time quad-band GSM\\/GPRS receiver in a 90nm digital CMOS process  

Microsoft Academic Search

We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing

K. Muhammad; Y. C. Ho; T. Mayhugh; C. M. Hung; T. Jung; I. Elahi; C. Lin; I. Deng; C. Fernando; J. Wallberg; S. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; M. C. Lee; R. B. Staszewski; K. Maggio

2005-01-01

99

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes  

Microsoft Academic Search

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si

H. Contopanagos; A. G. Nassiopoulou

2006-01-01

100

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process  

Microsoft Academic Search

A new 45 nm multiple time programming (MTP) cell with self-aligned nitride storage node has been proposed for logic NVM applications. The CMOS fully logic compatible cell has been successfully demonstrated in 45 nm CMOS technology with an ultra small cell size of 0.14 mum2. This cell adapting source side injection programming scheme has a wide on\\/off window and superior

Chia-En Huang; Hsin-Ming Chen; Han-Chao Lai; Ying-Je Chen; Ya-Chin King; Chrong Jung Lin

2007-01-01

101

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Woo, D. S.

1982-01-01

102

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process  

NASA Astrophysics Data System (ADS)

A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two-dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is -120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is -169 dBc/Hz.

Haijun, Gao; Lingling, Sun; Xiaofei, Kuang; Liheng, Lou

2012-07-01

103

Scaling trends in SET pulse widths in Sub-100 nm bulk CMOS processes.  

SciTech Connect

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Narasimham, Balaji; Ahlbin, Jonathan R.; Schrimpf, Ronald D.; Gadlage, Matthew J.; Massengill, Lloyd W.; Vizkelethy, Gyorgy; Reed, Robert A.; Bhuva, Bharat L.

2010-07-01

104

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit  

Microsoft Academic Search

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few

Eric K. Bolton; Gary S. Sayler; David E. Nivens; James M. Rochelle; Steven Ripp; Michael L. Simpson

2002-01-01

105

Very low cost graded SiGe base bipolar transistors for a high performance modular BiCMOS process  

Microsoft Academic Search

We report a new super self-aligned graded SiGe base transistor that uses high energy implantation, rather than epitaxial growth, to form the sub-collector region. This new inexpensive process yields a device with fT of 52 GHz and fmax of 70 GHz with the addition of only 4 lithography levels over our 0.25 ?m CMOS technology without any changes to the

C. A. King; M. R. Frei; M. Mastrapasqua; K. K. Ng; Y. O. Kim; R. W. Johnson; S. Moinian; S. Martin; H.-I. Cong; F. P. Klemens; R. Tang; D. Nguyen; T.-I. Hsu; T. Campbell; S. J. Molloy; L. B. Fritzinger; T. G. Ivanov; K. K. Bourdelle; C. Lee; Y.-F. Chyan; M. S. Carroll; C. W. Leung

1999-01-01

106

Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process  

Microsoft Academic Search

Power gain (fMAX) of 350 GHz and cut-off frequency (fT) of 280 GHz is demonstrated for 36 nm Lpoly devices in a 45 nm bulk CMOS process. A record fT of 350 GHz (intrinsic fT 425 GHz), without any loss of fMAX is seen in 28 nm Lpoly devices. Combination of advanced lithography and liner stress effect can be leveraged

Hongmei Li; B. Jagannathan; Jing Wang; Tai-Chi Su; S. Sweeney; J. J. Pekarik; Yun Shi; D. Greenberg; Zhenrong Jin; R. Groves; L. Wagner; S. Csutak

2007-01-01

107

Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process  

Microsoft Academic Search

The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the dc stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency,

Ming-Dou Ker; Jung-Sheng Chen

2008-01-01

108

A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology  

Microsoft Academic Search

A focal-plane array (FPA) for room-temperature detection of 0.65-THz radiation has been fully integrated in a low-cost 0.25 mum CMOS process technology. The circuit architecture is based on the principle of distributed resistive self-mixing and facilitates broadband direct detection well beyond the cutoff frequency of the technology. The 3 timesZ 5 pixel array consists of differential on-chip patch antennas, NMOS

Erik Ojefors; Ullrich R. Pfeiffer; Alvydas Lisauskas; Hartmut G. Roskos

2009-01-01

109

The First Fully Integrated Quad-Band GSM\\/GPRS Receiver in a 90-nm Digital CMOS Process  

Microsoft Academic Search

We present the receiver in the first single-chip GSM\\/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive

Khurram Muhammad; Yo-Chuol Ho; Terry L. Mayhugh; Chih-Ming Hung; T. Jung; Imtinan Elahi; Charles Lin; Irene Deng; C. Fernando; J. L. Wallberg; S. K. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; Meng-Chang Lee; Roman Staszewski; K. Maggio

2006-01-01

110

Designing a ring-VCO for RFID transponders in 0.18 ?m CMOS process.  

PubMed

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 ?m process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. PMID:24587731

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

111

Low loss, high contrast planar optical waveguides based on low-cost CMOS compatible LPCVD processing  

NASA Astrophysics Data System (ADS)

A new class of integrated optical waveguide structures ("TriPleX") is presented, based on low cost CMOS-compatible LPCVD processing of alternating Si3N4 and SiO2 layers. The technology allows for medium and high index-contrast waveguides that exhibit low channel attenuation. In addition, TriPleX waveguides are suitable for operation at wavelengths from visible (< 500 nm) through the infra-red range (2 ?m and beyond). The geometry is basically formed by a rectangular cross-section of silicon nitride (Si3N4) filled with and encapsulated by silicon dioxide (SiO2). The birefringence and minimal bend radius of the waveguide are completely controlled by the geometry of the waveguide layer structures. Experiments on typical geometries show excellent characteristics for telecom wavelengths at ~1300 nm-1600 nm (channel attenuation <= 0.06 dB/cm, Insertion Loss (IL) <= 0.15 dB, Polarization Dependent Loss (PDL) <= 0.1 dB, Group Birefringence (Bg) << 1×10-4, bend radius <= 50-100 ?m).

Hoving, Willem; Heideman, Rene; Geuzebroek, Douwe; Leinse, Arne; Klein, Edwin; Dekker, Ronald

2008-05-01

112

Stacked CMOS SRAM cell  

NASA Astrophysics Data System (ADS)

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

Chen, C.-E.; Lam, H. W.; Malhi, S. D. S.; Pinizzotto, R. F.

1983-08-01

113

A low-cost infrared absorbing structure for an uncooled infrared detector in a standard CMOS process  

NASA Astrophysics Data System (ADS)

This paper introduces a low-cost infrared absorbing structure for an uncooled infrared detector in a standard 0.5 ?m CMOS technology and post-CMOS process. The infrared absorbing structure can be created by etching the surface sacrificial layer after the CMOS fabrication, without any additional lithography and deposition procedures. An uncooled infrared microbolometer is fabricated with the proposed infrared absorbing structure. The microbolometer has a size of 65 × 65 ?m2 and a fill factor of 37.8%. The thermal conductance of the microbolometer is calculated as 1.33 × 10?5 W/K from the measured response to different heating currents. The fabricated microbolometer is irradiated by an infrared laser, which is modulated by a mechanical chopper in a frequency range of 10–800 Hz. Measurements show that the thermal time constant is 0.995 ms and the thermal mass is 1.32 × 10?8 J/K. The responsivity of the microbolometer is about 3.03 × 104 V/W at 10 Hz and the calculated detectivity is 1.4 × 108 cm·Hz1/2/W.

Ning, Shen; Zhen'an, Tang; Jun, Yu; Zhengxing, Huang

2014-03-01

114

Novel processes for modular integration of silicon-germanium MEMS with CMOS electronics  

NASA Astrophysics Data System (ADS)

Equipment control, process development and materials characterization for LPCVD poly-SiGe for MEMS applications are investigated in this work. In order to develop a repeatable process in an academic laboratory, equipment monitoring methods are implemented and new process gases are explored. With the dopant gas BCl3, the design-of-experiments technique is used to study the dependencies of deposition rate, resistivity, average residual stress, strain gradient and wet etch rate in hydrogen-peroxide. Structural layer requirements for general MEMS applications are met within the process temperature constraint imposed by CMOS electronics. However, the strain gradient required for inertial sensor applications is difficult to achieve with as-deposited films. Approaches to reduce the strain gradient of LPCVD poly-SiGe are investigated. Correlation between the strain gradient and film microstructure is found using stress-depth profiling and cross-sectional TEM analysis. The effects of film deposition conditions on film microstructure are also determined. Boron-doped poly-SiGe films generally have vertically oriented grains---either conical or columnar in shape. Films with conical grain structure have large strain gradient due to highly compressive stress in the lower (initially deposited) region of the film. Films with small strain gradient usually have columnar grain structure with low defect density. It is also found that the uniformity of films deposited in a batch LPCVD reactor can be improved by increasing the deposited film thickness, using a proper seeding layer, and/or depositing the film in multiple layers. The best strain gradient achieved in our academic research laboratory is 1.1x10-6 mum-1 for a ˜3.5 mum thick film deposited at 410°C in 8 hours, with a worst-case variation across a 150 mm-diameter wafer of 1.6x10 -5 mum-1 and a worse-case variation across a load of twenty-five wafers of 7x10-5 mum-1. The effects of post-deposition annealing and argon implantation on mechanical properties are also studied. While the as-deposited film can achieve the desired mechanical properties, post-deposition processing at elevated temperatures can degrade the strain gradient.

Low, Carrie Wing-Zin

115

Silicon-CMOS BEOL compatible material systems and processing for on-chip optical interconnect components  

NASA Astrophysics Data System (ADS)

Optical interconnects are being actively pursued at smaller length scales in microelectronics to overcome the speed and bandwidth limitations of electrical interconnects. An on-chip implementation of optical interconnects requires the materials and processing to be compatible with the Back End Of the Line (BEOL) silicon Complementary Metal-Oxide Semiconductor (CMOS) transistor technology. This thesis looks at some materials and processing schemes for on-chip passive optical components that satisfy the above compatibility requirements. Silica xerogel (porous silicon oxide) is used in this work to demonstrate high refractive index contrast waveguides. A binary solvent technique for open bowl, striation-free spin coating with excellent porosity control was developed. Plasma deposited silicon oxide and a hybrid alkoxy-siloxane polymer were used as the core materials. Reduction of the intrinsic stress of the plasma deposited silicon oxide was found to be essential for structural stability. Penetration issues exist for the alkoxy-siloxane polymer/xerogel system, which were overcome with the use of an optically thin silicon oxide capping layer. This thesis also deals with the fabrication vertically reflecting micro-mirrors. A sacrificial layer based isotropic etching technique was explored to make angular facets for micro-mirror fabrication. The theory of this process is presented followed by numerical simulations and experiments. An isotropic wet etching technique is shown to be a reliable process for the fabrication of flat mirror faces. However, due to penetration of the etchant into the etch-stop/sacrificial material interface, the angle obtained was less than predicted. Various strategies to overcome this problem are presented. A similar penetration related angle decrease was not observed for a plasma etching based process. The angular facet in the alkoxy-siloxane polymer core that would function as the mirror surface was also fabricated by a pattern transfer method involving transferring the angle from a template to the waveguide using a CF4/O 2 based reactive ion etching (RIE). Metallization of the mirror faces was done using a self-aligned technique, which ensures metal deposition only on the angular facet and also eliminates a lithography step. A reflection efficiency of 83% was measured for these micro-mirrors using a prism-coupler based setup.

Ponoth, Shom S.

116

High-Q Solenoid Inductors With a CMOS-Compatible Concave-Suspending MEMS Process  

Microsoft Academic Search

This paper presents micromachined solenoid inductors that are fabricated in a standard CMOS silicon substrate (with a resistivity of 1-8 Omega . cm). The solenoid is concavely embedded in a silicon cavity with the silicon wafer surface remaining a plane, and mechanically suspended to form an air gap from the bottom of the silicon cavity. In addition to facilitating flip-chip

Lei Gu; Xinxin Li

2007-01-01

117

Design and implementation of two key image processing techniques for CMOS image sensor based on fpga  

Microsoft Academic Search

Automatic white balance and color filter array interpolation are two important function of image signal processor for CMOS image sensor. This paper describes the designs and implementations of new automatic white balance method and color interpolation method on FPGA. This white balance method can effectively get the better of the defects of gray world and gray world-retinex methods by calculating

Yu Zhang; Su-ying Yao; Na Zhang; Jiang-tao Xu

2008-01-01

118

Die-level, post-CMOS processes for fabricating open-gate, field-effect biosensor arrays with on-chip circuitry  

NASA Astrophysics Data System (ADS)

Field-effect sensors have been applied extensively to numerous biomedical applications. To develop biosensor arrays in large scale, integration with signal-processing circuits on a single chip is crucial for avoiding wiring complexity and reducing noise interference. This paper proposes and compares two CMOS-compatible processes that allow open-gate, field-effect transistors (OGFETs) to be fabricated at the die level. The polygates of transistors are removed to maximize the transconductance. The CMOS compatibility further facilitates the monolithic integration with circuitry. Based on images and electrical measurements taken at different stages of the post-CMOS processes, a more feasible and reliable process is identified. The robustness of the fabricated OGFETs against the micromachining process and against moisture is further examined and discussed. Finally, the capability of the OGFETs in detecting ion concentrations, biomolecules, and electrophysiological signals is demonstrated.

Chang, S. R.; Chang, C. H.; Lin, J. S.; Lu, S. C.; Lee, Y. T.; Yeh, S. R.; Chen, H.

2008-11-01

119

A CMOS vision chip with SIMD processing element array for 1 ms image processing  

Microsoft Academic Search

Conventional image processing systems use a video signal as a transmission signal between an image sensor and image processor. The video rate, however, is not fast enough for some applications such as visual feedback for robot control, automobiles, gesture recognition for human interfaces, high speed visual inspection, microscope image processing, and so on. For such applications, the video signal, which

M. Ishikawa; K. Ogawa; T. Komuro; I. Ishii

1999-01-01

120

SEMICONDUCTOR INTEGRATED CIRCUITS: An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process  

NASA Astrophysics Data System (ADS)

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.

Ming, Liu; Hong, Chen; Changmeng, Li; Zhihua, Wang

2010-06-01

121

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process  

NASA Astrophysics Data System (ADS)

This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm2, and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G-1with a standard deviation of 2.5 mV G-1. The measured output noise floor is 354 µG Hz-1/2, corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C-1 below 85 °C.

Tseng, Sheng-Hsiang; S-C Lu, Michael; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

2012-05-01

122

A thermally robust Ni-FUSI process using in 65 nm CMOS technology  

Microsoft Academic Search

The interest in the low resistivity fully silicided (FUSI) gate increased significantly because of promising in use as contact\\u000a to the source, drain, and gate for sub?65 nm\\/45 nm CMOS devices. NiSi is potentially an attractive material due to its capability\\u000a to maintain low resistivity even for channel length down to 100 nm. The Formation of thermally stable silicide gates is important\\u000a for

S. Y. Tan; C. L. Sung; W. F. Wu

2007-01-01

123

A 1.8-V frequency synthesizer for WCDMA in 0.18-?m CMOS process  

Microsoft Academic Search

This research describes the design of a fully integrated fractional-N frequency synthesizer for the local oscillator in IMT-2000 system using 0.18-?m CMOS technology and 1.8-V single power supply. The designed fractional-N synthesizer contains following components. Modified charge pump uses active cascode transistors to achieve the high output impedance. A multi-modulus prescaler has modified ECL-like D flip-flop with additional diode-connected transistors

Young-Mi Lee; Ju-Sang Lee; Ri-A Ju; Kang-Wook Kim; Sang-Dae Yu

2002-01-01

124

Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing  

Microsoft Academic Search

Digital RF Processor (DRPTM)-based GSM\\/EDGE transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency\\/phase and amplitude analog domains. Using the concept of digital at the service of analog, DRP transmitters employ a number of estimation and compensation algorithms to provide robust performance in the presence of CMOS

Khurram Waheed; Robert B. Staszewski

2008-01-01

125

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS  

Microsoft Academic Search

The paper proposed estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency\\/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which

Khurram Waheed; Robert Bogdan Staszewski

2007-01-01

126

0.5 Micron Gate CMOS Technology Using E-Beam\\/Optical Mix Lithography  

Microsoft Academic Search

A high performance CMOS process using mix e-beam\\/optical lithography has been developed for VLSI applications. The 0.5 ¿m channel devices are fabricated with shallow N+ and P+ source\\/drain junctions. Self-aligned silicide on gate and diffusions reduces the sheet resistance to 5 ohm\\/sq.. The shallow retrograde N-well formed by multiple high energy phosphorous implants without a drive-in a allows the use

L. K. Wang; Y. Taur; D. Moy; R. H. Dennard; K. Chiong; F. Hohn; P. J. Coane; A. Edenfeld; S. Carbaugh; D. Kenney; S. Schnur

1986-01-01

127

Pseudo 2-transistor active pixel sensor using an n-well\\/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate  

Microsoft Academic Search

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well\\/gate-tied\\u000a p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The\\u000a proposed sensor has been fabricated using a 0.35 ?m 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS)\\u000a logic process. The pseudo 2-transistor APS consists of two NMOSFETs

Sang-Ho Seo; Min-Woong Seo; Jae-Sung Kong; Jang-Kyoo Shin; Pyung Choi

2008-01-01

128

MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 ?m CMOS process  

NASA Astrophysics Data System (ADS)

Design and simulation of mixed analog-digital circuits working at low temperature, typically between 77 K and 200 K, requires advanced compact models incorporating most of the physical effects occurring in cooled MOSFET. In this paper, some specific effects, such as freeze-out in LDD regions or quantization of the inversion layer in silicon sub-bands, observed at intermediate temperature are described and tentatively modeled. This study is performed on a dual gate oxide CMOS technology with 0.18 ?m/1.8 V and 0.35 ?m/3.3 V MOSFET transistors. Some improvements of compact models will allow a very precise description of MOS transistors for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures. Data on low frequency noise and transistor matching at low temperature are also presented.

Martin, P.; Royet, A. S.; Guellec, F.; Ghibaudo, G.

2011-08-01

129

Investigation of a seesaw structure for elevating the micro-optical device by CMOS-MEMS process  

NASA Astrophysics Data System (ADS)

The paper proposed a novel seesaw structure for elevating the micro optical device by the driving force of micro array thermal actuator, MATA. The effects of elevating structure, lateral connection arm structure, immobile structure and width of vertical connection arm on the maximum displacements and the variation of surface flatness of the elevated micro mirror surface varied with operation voltage are investigated. The motion behavior of the elevated micro mirror is stimulated and analyzed to get the maximum displacement and inclined angle of the device. The results demonstrate a pair of {1 x 2} parallel type MATA for the elevating structure, simple beam for the lateral connection arm structure, single thermal actuator for the immobile structure and 10µm for width of vertical connection arm are the optimum design for the micro optical device. The maximum displacement and inclined angle of the proposed micro optical device are 34.7µm and 10o, respectively. The device is fabricated by Taiwan Semiconductor Manufacture Cooperation, TSMC 0.35µm 2P4M mixed signal model, based upon CIC CMOS-MEMS process. The paper will examine whether CIC CMOS-MEMS could fully support to fabricate the integrated component for MOEMS.

Tsai, Chien-Chung; Tsai, Shang-Che; Huang, Yi-Cheng

2007-01-01

130

The 1.2 micron CMOS technology  

NASA Technical Reports Server (NTRS)

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.

1985-01-01

131

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 ?m CMOS process.  

PubMed

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

132

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 ?m CMOS Process.  

PubMed

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

133

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 ?m CMOS Process  

PubMed Central

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

134

Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography  

NASA Astrophysics Data System (ADS)

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing non-compliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.

Knecht, Jeffrey; Bolkhovsky, Vladimir; Sage, Jay; Tyrrell, Brian; Wheeler, Bruce; Wynn, Charles

2008-03-01

135

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures  

PubMed Central

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n+/p-sub, n-well/p-sub and p+/n-well/p-sub. All structures were fabricated in a 0.5 ?m 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated—the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 × and 1.6 × over the n+/p-sub and p+/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 × and 1.2 × improvement over the n+/p-sub and p+/n-well/p-sub diodes, respectively) while the p+/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity.

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2010-01-01

136

Charged particle detection performances of CMOS pixel sensors produced in a 0.18?m process with a high resistivity epitaxial layer  

NASA Astrophysics Data System (ADS)

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50?m thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35?m CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz0.18?m CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq/cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz0.18?m CMOS process for the ALICE ITS upgrade.

Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

2013-12-01

137

Research note Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits  

Microsoft Academic Search

Key building blocks - simple ternary inverter, positive ternary inverter and negative ternary inverter have been designed for operation at a low voltage -1 V in 2 lm, n-well standard CMOS process and simulated in SPICE3 for use in the design of ternary logic circuits. The back-gate bias method has been used in conjunction with the width\\/ channel (W\\/L) ratio

A. Srivastava

2000-01-01

138

Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits  

Microsoft Academic Search

Key building blocks – simple ternary inverter, positive ternary inverter and negative ternary inverter have been designed for operation at a low voltage – ±1 V in 2 ?m, n-well standard CMOS process and simulated in SPICE3 for use in the design of ternary logic circuits. The back-gate bias method has been used in conjunction with the width\\/channel (W\\/L) ratio

A. Srivastava

2000-01-01

139

A post-CMOS micromachined lateral accelerometer  

Microsoft Academic Search

In a post-complementary metal-oxide-semiconductor (CMOS) micromachining technology, the process flow enables the integration of micromechanical structures with conventional CMOS circuits which are low-cost and readily available. This paper presents a lateral capacitive sensing accelerometer fabricated in the post-CMOS process. Design advantages include electrically isolated multimetal routing on microstructures to create full-bridge capacitive sensors, and integration to increase transducer sensitivity by

Hao Luo; Gang Zhang; L. Richard Carley; Gary K. Fedder

2002-01-01

140

CMOS array design automation techniques  

NASA Technical Reports Server (NTRS)

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lombardi, T.; Feller, A.

1976-01-01

141

Grayscale lithography process study applied to zero-gap microlenses for sub-2?m CMOS image sensors  

NASA Astrophysics Data System (ADS)

Microlens arrays are used on CMOS image sensors to focus incident light onto the appropriate photodiode and thus improve the device quantum efficiency. As the pixel size shrinks, the fill factor of the sensor (i.e. ratio of the photosensitive area to the total pixel area) decreases and one way to compensate this loss of sensibility is to improve the microlens photon collection efficiency. This can be achieved by developing zero-gap microlens processes. One elegant solution to pattern zero-gap microlenses is to use a grayscale reticle with varying optical densities which locally modulate the UV light intensity, allowing the creation of continuous relief structure in the resist layer after development. Contrary to conventional lithography for which high resist contrast is appreciated to achieve straight resist pattern profiles, grayscale lithography requires smooth resist contrast curve. In this study we demonstrate the efficiency of grayscale lithography to generate sub-2?m diameter microlens with a positive-tone photoresist. We also show that this technique is resist and process (film thickness, development normality and exposure conditions) dependent. Under the best conditions, spherical zero-gap microlenses as well as aspherical and off-axis microlenses, which are impossible to obtain with the conventional reflow method, were obtained with satisfying process latitude.

Audran, S.; Vaillant, J.; Farys, V.; Hirigoyen, F.; Huss, E.; Mortini, B.; Cowache, C.; Berthier, L.; Mortini, E.; Fantuz, J.; Arnaud, O.; Depoyan, L.; Sundermann, F.; Baron, C.; Reynard, J.-P.

2010-03-01

142

Sensitivity of CMOS based imagers and scaling perspectives  

Microsoft Academic Search

CMOS based imagers are beginning to compete against CCDs in many areas of the consumer market because of their system-on-a-chip capability. Sensitivity, however, is a main weakness of CMOS imagers and enhancements and deviations from standard CMOS processes are necessary to keep up sensitivity with downscaled process generations. In the introductory section several definitions for the sensitivity of image sensors

Tarek Lulé; Stephan Benthien; Holger Keller; Frank Mütze; Peter Rieve; Konstantin Seibel; Michael Sommer; Markus Böhm

2000-01-01

143

CMOS magnetic sensor arrays  

Microsoft Academic Search

The design of a monolithic 64×64-element array of magnetic sensors, which is implemented in a standard 3-?m CMOS process, is described. The individual magnetic field sensors are split-drain MAGFETS. A split-drain MAGFET is a field-effect transistor that has one source, one gate, and two drains. When current is flowing in the FET in the absence of a magnetic field, both

James J. Clark

1988-01-01

144

A low-power CMOS ASIC for X-ray Silicon Drift Detectors low-noise pulse processing  

NASA Astrophysics Data System (ADS)

We present an Application Specific Integrated Circuit (ASIC), named VEGA-1, designed and manufactured for low-power analog pulse processing of signals from Silicon Drift Detectors (SDDs). The VEGA-1 ASIC consists of an analog and a digital/mixed-signal section to achieve all the functionalities and specifications required for high-resolution X-ray spectroscopy in the energy range from 500 eV to 60 keV with low power consumption. The VEGA-1 ASIC has been designed and manufactured in 0.35-?m CMOS mixed-signal technology in single and 32-channel version with dimensions of 200 ?m × 500 ?m per channel. A minimum intrinsic ENC of 12 electrons r.m.s. at 3.6 ?s shaping time and room temperature is measured for the ASIC without detector. The VEGA-1 has been tested with Q10-SDD designed in Trieste and fabricated at FBK, with an active area of 10 mm2 and a thickness of 450 ?m. The aforementioned detector has an anode current of about 180 pA at +22°C. A minimum Equivalent Noise Charge (ENC) of 16 electrons r.m.s. at 3.0 ?s shaping time and ?30°C has been demonstrated with a total measured power consumption of 482 ?W.

Ahangarianabhari, M.; Bertuccio, G.; Macera, D.; Malcovati, P.; Grassi, M.; Rashevsky, A.; Rashevskaya, I.; Vacchi, A.; Zampa, G.; Zampa, N.; Fuschino, F.; Evangelista, Y.; Campana, R.; Labanti, C.; Feroci, M.

2014-03-01

145

Overview of photon counting detectors based on CMOS processed single photon avalanche diodes (SPAD), InGaAs APDs, and novel hybrid (tube + APD) detectors  

NASA Astrophysics Data System (ADS)

An overview of photon counting detection using CMOS compatible Single Photon Avalanche Diodes (SPAD) will be presented. These SPADs have a planar structure, and are processed using CMOS technology. The most promising aspect of this technology is the potential for building large area arrays that can be operated in photon counting mode - without the read-out noise and bulkiness associated with low noise CCD cameras. Using the iAQC (integrated Active Quenching Circuit) produced by Micro-Photonics Devices, a low noise InGaAs/InAlAs APD will be characterized for photon counting. Finally, Characterization data from a photon counting module using Intevac"s IPD"s (Tube+APD hybrd) will be presented for photon counting at 1064nm.

Bertone, Nick; Biasi, Roberto; Dion, Bruno

2005-04-01

146

SEMICONDUCTOR INTEGRATED CIRCUITS: An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process  

NASA Astrophysics Data System (ADS)

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 ?m CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

Peijun, Gao; J, Oh N.; Hao, Min

2009-08-01

147

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process  

NASA Technical Reports Server (NTRS)

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

2006-01-01

148

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

149

Study on low noise CMOS image sensor  

Microsoft Academic Search

With the advance of semiconductor technology and the development of multimedia techniques, CMOS image sensor is extensively applied in medical and other industrial areas. Integrator array is the front-end processing circuit of CMOS image sensor, whose performance directly determines the image quality generated by image sensor. Currently, integrator array has become one research hot spot. The main works of this

Xu Wang; Hongyan Yang; Wuchen Wu

2010-01-01

150

Process optimization of developer soluble organic BARC and its characteristics in CMOS devices  

Microsoft Academic Search

As the IC industry is moving toward 90nm node or below, the critical dimension size of implant layers has shrunk to 250nm or smaller. To achieve better CD uniformity, dyed KrF resist and top anti-reflective coating (TARC) are commonly used in advanced photo process of implant layers, while typical organic BARC are not used because it requires dry etch process

Yeon Hwa Lim; Young Keun Kim; Jae Sung Choi; Jeong Gun Lee

2005-01-01

151

Process optimization of developer soluble organic BARC and its characteristics in CMOS devices  

NASA Astrophysics Data System (ADS)

As the IC industry is moving toward 90nm node or below, the critical dimension size of implant layers has shrunk to 250nm or smaller. To achieve better CD uniformity, dyed KrF resist and top anti-reflective coating (TARC) are commonly used in advanced photo process of implant layers, while typical organic BARC are not used because it requires dry etch process that damages the substrate and needs additional process steps. In order to overcome those shortcomings, developable BARC is introduced. It is a new type of BARC which is soluble to developer, TMAH solution, in the resist development step. This developer-soluble KrF BARC consists of polyamic acid and its solubility to alkaline could be adjusted by changing bake condition. In this experiment, we evaluated the margin of developable BARC process. Developable BARC reduces the standing wave of photoresist and improves the ID bias and CD uniformity as applied to implant feature printing. However, Developable BARC has a narrow thermal process margin. It is the profile of developable BARC that easily changes according to the coating thickness or thermal process conditions. Even in the same bake conditions, developable BARC profile changes according to the pattern densities. To observe the effects of developable BARC on the device performance, we compare electrical data of devices produced with and without developable BARC. They have the differences in the threshold voltage, leakage current and saturation current. Probably, the residues of the developable BARC after the development bring about the differences.

Lim, Yeon Hwa; Kim, Young Keun; Choi, Jae Sung; Lee, Jeong Gun

2005-05-01

152

Low-k materials as interlayer dielectrics in CMOS: The effects of deposition and processing on N-channel MOSFET's characteristics  

NASA Astrophysics Data System (ADS)

We report on comprehensive studies of the effects, on n- channel metal-oxide-silicon field-effect transistors (MOSFETs), of deposition and processing of low-k interlayer dielectrics (ILDs) in complementary MOS (CMOS). We have explored the ILD candidacy of fluorinated silicon oxide (FSO), fluorinated poly(erylene)ethers (FLARE), and divinylsiloxane-benzocyclobutane (BCB). We have observed that FLARE and BCB degradation by plasma exposures manifests itself as changes in the physical properties especially leakage current, which is observed to increase by several orders of magnitude. This degradation is proposed to result from bond scissioning, bond cross-linking and void formation processes which are promoted by ion bombardment, ultra-violet radiation, and plasma charging mechanisms associated with plasma exposures. The latter mechanism is suggested to be the dominant degradation mechanism in FLARE and BCB and is observed to contribute the largest share to MOSFET's damage from via etching of FLARE or BCB, as a second ILD, in a 0.35 and 0.5 ?m channel length full flow CMOS process. The severity of this MOSFET damage is significantly reduced by the inclusion of a thin insulating Si3N4 layer underneath the ILD or annealing at 350°C in forming gas (94% N2 and 6% H2). In CMOS processes utilizing FSO as an ILD we have observed that fluorine interactions, coupled with plasma charging, adversely affects MOSFET's Fowler-Nordheim reliability via fluorine passivation/depassivation of bulk gate oxide and oxide/silicon interface defects. Overall, these results underscore the negative effects of ILD processing on MOSFET's characteristics and call for these effects to be reckoned with in making the choice of a suitable low-k ILD.

Trabzon, Levent

2000-10-01

153

Radiation tolerant circuits designed in 2 commercial 0.25{micro} CMOS processes  

SciTech Connect

Characterization of simple devices as well as complex circuits, in two commercial 0.25{micro} processes, demonstrates a high level (up to 58 Mrad) radiation tolerance of these technologies. They are also very likely to be immune to single event gate damage according to the results from 200 MeV-protons irradiation.

Mekkaoui, A. [and others

2001-03-08

154

Design and implementation of operational amplifiers with programmable characteristics in a 90nm CMOS process  

Microsoft Academic Search

Operational amplifiers (op-amps) serve as the basic building blocks in almost every analog and mixed-signal electronic circuit. However, one of the most common problems in op-amp design is the variation in the op-amp's performance caused by process variations during fabrication. As such, it is of utmost importance that provisions be made on the op-amp to compensate for possible deviations in

S. C. dela Cruz; M. delos Reyes; Terence C. Gaffud; T. Abaya; M. Gusad; M. D. Rosales

2009-01-01

155

Traveling wave electrode design for ultra compact carrier-injection HBT-based electroabsorption modulator in a 130nm BiCMOS process  

NASA Astrophysics Data System (ADS)

Silicon photonic system, integrating photonic and electronic signal processing circuits in low-cost silicon CMOS processes, is a rapidly evolving area of research. The silicon electroabsorption modulator (EAM) is a key photonic device for emerging high capacity telecommunication networks to meet ever growing computing demands. To replace traditional large footprint Mach-Zehnder Interferometer (MZI) type modulators several small footprint modulators are being researched. Carrier-injection modulators can provide large free carrier density change, high modulation efficiency, and compact footprint. The large optical bandwidth and ultra-fast transit times of 130nm HBT devices make the carrierinjection HBT-based EAM (HBT-EAM) a good candidate for ultra-high-speed optical networks. This paper presents the design and 3D full-wave simulation results of a traveling wave electrode (TWE) structure to increase the modulation speed of a carrier-injection HBT-EAM device. A monolithic TWE design for an 180um ultra compact carrier-injection-based HBT-EAM implemented in a commercial 130nm SiGe BiCMOS process is discussed. The modulator is electrically modeled at the desired bias voltage and included in a 3D full-wave simulation using CST software. The simulation shows the TWE has a S11 lower than -15.31dB and a S21 better than -0.96dB covering a bandwidth from DC-60GHz. The electrical wave phase velocity is designed close to the optical wave phase velocity for optimal modulation speed. The 3D TWE design conforms to the design rules of the BiCMOS process. Simulation results show an overall increase in modulator data rate from 10Gbps to 60Gbps using the TWE structure.

Fu, Enjin; Joyner Koomson, Valencia; Wu, Pengfei; Huang, Z. Rena

2014-03-01

156

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications  

NASA Technical Reports Server (NTRS)

This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

1994-01-01

157

Localization-based super-resolution microscopy with an sCMOS camera part III: camera embedded data processing significantly reduces the challenges of massive data handling.  

PubMed

We present a camera embedded data processing method for localization microscopy (LM) with faster detectors such as scientific complementary metal-oxide semiconductor (sCMOS) cameras. Based on the natural sparsity of single molecule images, this method utilizes the field programmable gate array chip inside a camera to identify and export only the regions containing active molecules instead of raw data. Through numerical simulation and experimental analysis, we found that this method can greatly reduce data volume (<10%) with negligible loss of useful information (<0.2%) at molecular densities <0.2 molecules/?m(2), thus significantly reducing the challenges of data transfer, storage, and analysis in LM. PMID:23722738

Ma, Hongqiang; Kawai, Hiroyuki; Toda, Eiji; Zeng, Shaoqun; Huang, Zhen-Li

2013-06-01

158

Ge technology beyond Si CMOS  

NASA Astrophysics Data System (ADS)

To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at <= 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to <= 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-?/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

Chin, Albert

2012-12-01

159

A 5 MHz silicon CMOS hierarchical boost DC-DC converter design using macromodels for a 1U process  

Microsoft Academic Search

This work presents an innovative design of a high frequency and potentially highly efficient boost DC-DC converter with an input voltage of 2.7-3.3 V and with a programmable output voltage of 4-9 V. Current sourcing capability is between 40 mA-360 mA. A low power boost DC-DC converter designed in CMOS which partially uses circuit macromodels-designed and tested using Cadence tools-for

Mark S. Hooper; J. W. Hall; S. Kenny

2002-01-01

160

Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes  

Microsoft Academic Search

The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21 A in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as

Federico A. Altolaguirre; Ming-Dou Ker

2011-01-01

161

A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process  

Microsoft Academic Search

This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator, and start-up calibration, which achieves a constant damping factor and fractional loop bandwidth over a 0.18 MHz to 600 MHz range of output frequencies and PVT conditions, with output jitter less than 0.04 UIPP. The 0.18 mm2 chip is implemented in 90 nm CMOS, operates over a 0.7

J. Lin; B. Haroun; T. Foo; Jin-Sheng Wang; B. Helmick; S. Randall; T. Mayhugh; C. Barr; J. Kirkpatric

2004-01-01

162

On-chip p-MOSFET dosimetry [CMOS ICs  

Microsoft Academic Search

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation-induced oxide and interface charge. The design employs closed-geometry FETs and a zero-biased n-well to eliminate leakage currents. The FETs are operated using a constant current chosen to greatly reduce the FET's temperature sensitivity. The dose sensitivity of these p-FETs

M. G. Buehler; B. R. Blaes; G. A. Soli; G. R. Tardio

1993-01-01

163

An ultra-low-power area-efficient non-volatile memory in a 0.18 ?m single-poly CMOS process for passive RFID tags  

NASA Astrophysics Data System (ADS)

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 ?m single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 ?m single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 ?m2 and 0.12 mm2, respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 ?W/0.69 ?W at a read/write rate of (268 kb/s)/(3.0 kb/s).

Xiaoyun, Jia; Peng, Feng; Shengguang, Zhang; Nanjian, Wu; Baiqin, Zhao; Su, Liu

2013-08-01

164

Simulation, fabrication and characterization of a 3.3 V flash ZE 2PROM array implemented in a 0.8 ?m CMOS process  

NASA Astrophysics Data System (ADS)

This paper describes a Zener based flash memory cell (ZE 2PROM), programmed from hot electrons generated by a heavily doped reverse biased p +n + junction attached to the drain. The cell can be implemented in a NOR type memory array. It uses an orthogonal write technique to achieve fast programming with low power dissipation and reduced drain disturbance. The modeling of the charge transfer behavior of the flash ZE 2PROM cell is also done to describe the charging and discharging of the floating gate during programming and erasing. The flash ZE 2PROM arrays were implemented in a 0.8 ?m lithography CMOS process flow in which the n-LDD step was replaced with a one sided p + boron implant with a doping level of ˜10 19 cm -3. This minor change to a standard CMOS process, makes the concept highly attractive for embedded memory applications. A programming time of 850 ns at 3.3 V supply was achieved on fabricated test devices.

Ranaweera, J.; Ng, W. T.; Salama, C. A. T.

1999-02-01

165

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels  

PubMed Central

In this paper we present a novel, quadruple well process developed in a modern 0.18 ?m CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 ?m pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-01-01

166

Graphene/Si CMOS Hybrid Hall Integrated Circuits.  

PubMed

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

167

Graphene/Si CMOS Hybrid Hall Integrated Circuits  

PubMed Central

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

168

Review of radiation damage studies on DNW CMOS MAPS  

NASA Astrophysics Data System (ADS)

Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10?cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7·1013cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1k?cm) epitaxial layer.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

2013-12-01

169

Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities  

NASA Astrophysics Data System (ADS)

The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied 0.13 ?m ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4×4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips.

Gabrielli, A.; SLIM5 Collaboration

170

An ultra-high-speed ECL-BiCMOS technology with silicon fillet self-aligned contacts  

Microsoft Academic Search

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay

Teyin M. Liu; Gen M. Chin; Duk Y. Jeon; Mark D. Morris; Robert W. Johnson; Maurice Tarsia; Helen H. Kim; Marcio Cerullo; Kwing F. Lee; JanMye James Sung; Kei-Shun Lau; Tzu-Yin Chiu; Alexander M. Voshchenkov; Robert G. Swartz

1994-01-01

171

CMOS image sensors  

Microsoft Academic Search

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most

A. El Gamal; H. Eltoukhy

2005-01-01

172

CMOS current-mode multivalued PLAs  

Microsoft Academic Search

A programmable logic array (PLA) structure for implementation of multivalued combinational and sequential systems is proposed. The PLA is integrable by using a conventional CMOS process and makes a NOR\\/TSUM two-level implementation of multivalued functions, which can consume less silicon area than an equivalent binary implementation. Pseudo-nMOS and dynamic CMOS implementations for the proposed PLA are also presented, using current-mode

F. J. Pelayo; A. Prieto; A. Lloris; J. Ortega

1991-01-01

173

Integrated polarization-analyzing CMOS image sensor  

Microsoft Academic Search

A CMOS image sensor with an integrated wire grid polarizer to sense the polarization of light is presented. The chip consists of an array of 128 by 128 pixels, it occupies an area of 5x4 mm 2 and it has been designed and fabricated in a CMOS 180nm process. Extinction ratio of 6.3 and 7.7 were achieved. The sensor is

Mukul Sarkar; David San Segundo Bello; Chris Van Hoof; Albert J. P. Theuwissen

2010-01-01

174

CMOS magnetic sensors with integrated ferromagnetic parts  

Microsoft Academic Search

The paper deals with Hall and flux-gate magnetic field sensors consisting of integrated combination of CMOS ASICs and planar ferromagnetic components. Ferromagnetic parts are made of a soft amorphous alloy, integrated at the CMOS wafer in a post-processing production phase. When the sensors are exposed to an in-plane magnetic field, under the peripheries of ferromagnetic parts appears a strong magnetic

Radivoje S. Popovic; Predrag M. Drljaca; Pavel Kejik

2006-01-01

175

CMOS image sensors for sensor networks  

Microsoft Academic Search

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 ?m CMOS process. The imagers embed\\u000a an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision\\u000a on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low\\u000a power operation. This

Eugenio Culurciello; Andreas G. Andreou

2006-01-01

176

HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter  

Microsoft Academic Search

HSST\\/BiCMOS technology has been developed by merging a novel 0.3 ?m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 ?m CMOS process. The HSST bipolar transistor size is 2.5 times smaller than that of 1 ?m SST-1B with an emitter 0.4 ?m wide. This results from a 0.3 ?m design rule, a collector polysilicon

S. Konaka; T. Kobayashi; T. Matsuda; M. Ugajin; K. Imai; T. Sakai

1990-01-01

177

Performance optimization of a high speed super self-aligned BiCMOS technology  

Microsoft Academic Search

The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter\\/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, fmax, has been increased from 25.9 GHz to 33.5 GHz. Since all the process parameters related to CMOS are kept constant, high speed CMOS circuit operation is maintained without

T. M. Liu; G. M. Chin; M. D. Morris; D. Y. Jeon; R. W. Johnson; V. D. Archer; M. J. Tarsia; H. H. Kim; M. Cerullo; K. F. Lee; J. M. Sung; K. Lau; M. D. Feuer; A. M. Voshchenkov; R. G. Swartz

1993-01-01

178

Checkered white-RGB color LOFIC CMOS image sensor  

Microsoft Academic Search

We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1\\/3.3-inch optical format, 1280H x 480V pixels, 4.2-?m effective pixel pitch along with 45° direction was designed and fabricated through 0.18-?m 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image

Shun Kawada; Shin Sakai; Yoshiaki Tashiro; Shigetoshi Sugawa

2010-01-01

179

CMOS microelectrode array for bidirectional interaction with neuronal networks  

Microsoft Academic Search

A CMOS metal-electrode-based micro system for bidirectional communication (stimulation and recording) with neuronal cells in vitro is presented. The chip overcomes the interconnect challenge that limits today's bidirectional microelectrode arrays. The microsystem has been fabricated in an industrial CMOS technology with several post-CMOS processing steps to realize 128 biocompatible electrodes and to ensure chip stability in physiological saline. The system

Flavio Heer; Sadik Hafizovic; Wendy Franks; Axel Blau; C. Ziegler; A. Hierlemann

2006-01-01

180

A lateral capacitive CMOS accelerometer with structural curl compensation  

Microsoft Academic Search

We present successful experimental results from the first lateral capacitive accelerometer to be designed and manufactured in a conventional CMOS process. Compatibility with conventional CMOS provides advantages of low cost, high yield and fast prototyping that should be transferable to any CMOS foundry. A fully differential capacitive-bridge interface which cannot be realized in polysilicon technology is designed and implemented. Out-of-plane

Gang Zhang; Huikai Xie; Lauren E. de Rosset; Gary K. Fedder

1999-01-01

181

Wafer bonding for MEMS and CMOS integration  

NASA Astrophysics Data System (ADS)

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.

Dragoi, V.; Pabo, E.; Burggraf, J.; Mittendorfer, G.

2011-05-01

182

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

Microsoft Academic Search

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force

Weiquan Zhang

2000-01-01

183

A 12 mW wide dynamic range CMOS front end for a portable GPS receiver  

Microsoft Academic Search

At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35?m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications

A. R. Shahani; D. K. Shaeffer; T. H. Lee

1997-01-01

184

Fundamental performance differences of CMOS and CCD imagers: part V  

NASA Astrophysics Data System (ADS)

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

185

A Novel Multilayer Aperture-Coupled Cavity Resonator for Millimeter-Wave CMOS RFICs  

Microsoft Academic Search

A novel millimeter-wave cavity resonator, completely compatible with commercial CMOS fabrication techniques, has been designed and fabricated in a 0.25-mum CMOS process and tested. The resonator employs a capacitively loaded cavity topology effectively implemented using the CMOS multimetal-layer and via-hole structure. The CMOS capacitively loaded cavity resonator, including two coupling apertures and microstrip feed lines, occupies an area of 2

Meng Miao; Cam Nguyen

2007-01-01

186

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-?m CMOS process  

NASA Astrophysics Data System (ADS)

A fully integrated multi-mode multi-band directed-conversion radio frequency (RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator (LO) switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface (SPI) module. The front-end is fabricated in a TSMC 0.18-?m RF CMOS process and occupies an area of 1.3 mm2. The measured double-sideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.

Rui, Guo; Haiying, Zhang

2012-09-01

187

SEMICONDUCTOR INTEGRATED CIRCUITS: A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 ?m CMOS process  

NASA Astrophysics Data System (ADS)

A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks—including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU—in a 0.18 ?m CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 × 3.8 mm2 including pads.

Jingchao, Wang; Chun, Zhang; Zhihua, Wang

2010-08-01

188

Optical-thermal simulation applied to the study of the pattern effects induced by the sub-melt laser anneal process in advanced CMOS technologies  

NASA Astrophysics Data System (ADS)

We present a study of the temperature non-homogeneities induced by millisecond laser annealing in advanced CMOS technologies at die level. Because of the design, the device layout at the wafer surface introduces during this anneal significant spatial variations of optical absorption and heat transfer that can induce temperature non-uniformities over the die, often called `pattern effects'. These temperature variations are becoming a major issue, since they are the origin of significant device properties dispersion. A complete optical and thermal simulation set has been developed to estimate the temperature variations induced by the topologies at the wafer surface during the laser anneal process. The modelling has been validated by either a comparison with another software or reflectometry and electrical measurements on real structures. This work demonstrates that the temperature variations are caused either by optical coupling or by thermal properties dispersion present at the wafer surface at the anneal step. Finally, we demonstrate that the impact of the thin-film interferences and diffraction phenomena is the critical issue for these pattern effects.

Colin, A.; Morin, P.; Cacho, F.; Bono, H.; Beneyton, R.; Mathiot, D.; Fogarassy, E.

2011-08-01

189

SEMICONDUCTOR INTEGRATED CIRCUITS: Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-?m low power CMOS process  

NASA Astrophysics Data System (ADS)

Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q2 random walk NMOS current source layout routing method, a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-?m CMOS process. The total consumption is only 10 mW from a single 1.2-V power supply, and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively. When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate, the SFDR is measured to be 70 dB. The die area is about 0.2 mm2.

Bulu, Xu; Bowen, Shao; Xia, Lin; Wei, Yi; Yun, Liu

2010-09-01

190

LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)  

SciTech Connect

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

2000-01-01

191

Characterization and comparison of lateral amorphous semiconductors with embedded Frisch grid detectors on 0.18?m CMOS processed substrate for medical imaging applications  

NASA Astrophysics Data System (ADS)

An indirect digital x-ray detector is designed, fabricated, and tested. The detector integrates a high speed, low noise CMOS substrate with two types of amorphous semiconductors on the circuit surface. Using a laterally oriented layout a-Si:H or a-Se can be used to coat the CMOS circuit and provide high speed photoresponse to complement the high speed circuits possible on CMOS technology. The circuit also aims to reduce the effect of slow carriers by integrated a Frisch style grid on the photoconductive layer to screen for the slow carriers. Simulations show a uniform photoresponse for photons absorbed on the top layer and an enhanced response when using a Frisch grid. EQE and noise results are presented. Finally, possible applications and improvements to the area of indirect x-ray imaging that are capable of easily being implemented on the substrate are suggested.

Hristovski, Christos; Goldan, Amir; Majid, Shaikh Hasibul; Wang, Kai; Shafique, Umar; Karim, Karim

2011-03-01

192

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers  

NASA Astrophysics Data System (ADS)

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

2011-10-01

193

Delta Doping High Purity CCDs and CMOS for LSST  

NASA Technical Reports Server (NTRS)

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

194

Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate  

Microsoft Academic Search

We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAIN gate HfAlSiON p-FET for hp 32 nm low standby power (LSTP) CMOS devices. Low V, of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AIN-cap formation of TiAIN and subsequent intermixing between AIN-cap and HfSiON by high temperature

M. Kadoshima; T. Matsuki; M. Sato; T. Aminaka; E. Kurosawa; A. Ohta; H. Yoshinaga; S. Miyazaki; K. Shiraishi; K. Yamabe; K. Yamada; T. Aoyama; Y. Nara; Y. Ohji

2007-01-01

195

Monolithic piezoresistive CMOS magnetic field sensors  

Microsoft Academic Search

Two original electromechanical magnetic sensors have been developed using a fully industrial fabrication process that relies on bulk wet etching of CMOS dies. The first device uses the Lorentz force to actuate a U-shaped cantilever beam, while piezoresistive polysilicon gauges convert the beam bending into an electrical signal. A 2?T sensor resolution is demonstrated, making this device suitable for earth

Vincent Beroulle; Yves Bertrand; Laurent Latorre; Pascal Nouet

2003-01-01

196

Transistor matching in analog CMOS applications  

Microsoft Academic Search

This paper gives an overview of MOSFET mismatch effects that form a performance\\/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease

Marcel J. M. Pelgrom; Hans P. Tuinhout; Maarten Vertregt

1998-01-01

197

An integrated CMOS interface for lambda sensor  

Microsoft Academic Search

Automotive pollution can be reduced by suitably controlling the mixture that is fed to the cylinders. This can be performed by means of a feedback loop including a lambda sond and a processing unit which controls the electronic fuel injectors. This paper describes a CMOS interface which adapts the output signal of a lambda sensor to allow its feeding into

L. Civardi; U. Gatti; F. Maloberti; G. Torelli

1994-01-01

198

Integrated tunable CMOS laser.  

PubMed

An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications. PMID:24514318

Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B; Yu, Paul K L; Van Orden, Derek; Spann, John Y; Blivin, Christopher C; He, Lina; Cai, Hong; Dallesasse, John M; Stone, Robert J; Mizrahi, Amit

2013-11-18

199

All-CMOS night vision viewer with integrated microdisplay  

NASA Astrophysics Data System (ADS)

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

200

Integrated Cmos Linear Dosimeter  

Microsoft Academic Search

This paper presents a review of radiation sensors; their basic principles and a possible use as built-in sensors in Integrated Circuits exposed to ionizing radiation. Two radiation dosimeters are discussed: threshold and linear. All are CMOS circuits compatible with standard technology using pMOSFET sensors. An integrated dosimetry system including microprocessor interface for remote monitoring is described.

O. Calvo; M. González; C. Romero; E. García-Moreno; E. Isern; M. Roca; J. Segura

1998-01-01

201

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

202

SEMICONDUCTOR INTEGRATED CIRCUITS: Low power CMOS preamplifier for neural recording applications  

NASA Astrophysics Data System (ADS)

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 ?Vrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 ?W from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-?m N-well CMOS 2P4M process.

Xu, Zhang; Weihua, Pei; Beiju, Huang; Hongda, Chen

2010-04-01

203

Carbon Nanotube-Based CMOS Gas Sensor IC: Monolithic Integration of Pd Decorated Carbon Nanotube Network on a CMOS Chip and Its Hydrogen Sensing  

Microsoft Academic Search

The integration of carbon nanotube (CNT)-based sensor and readout complementary metal-oxide-semiconductor integrated chip (CMOS IC) to detect hydrogen gas in a single chip is presented. First, we have fabricated the CMOS IC us- ing the standard 0.35-µm CMOS process. Then, we have built 8 × 8 CNT-based sensor cells on it using a proposed tractable postprocessing strategy and judicious electrode

Sung Min Seo; Jun Ho Cheon; Seok Hyang Kim; Tae June Kang; Jung Woo Ko; In-Young Chung; Yong Hyup Kim; Young June Park

2011-01-01

204

Packaged CMOS-MEMS free-free beam oscillator  

NASA Astrophysics Data System (ADS)

In this paper a self-oscillator based on a polysilicon free-free beam resonator monolithically integrated and packaged in a 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology is presented. The oscillator is capable of providing a 350 mVPP sinusoidal signal at 25.6 MHz, with a bias polarization voltage of 7 V. The microelectromechanical systems (MEMS) resonator is packaged using only the back-end-of-line metal layers of the CMOS technology, providing a complete low-cost CMOS-MEMS processing for on-chip frequency references.

Marigó, E.; Verd, J.; López, J. L.; Uranga, A.; Barniol, N.

2013-11-01

205

Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process  

SciTech Connect

The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and overlay on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described.

Allen, R.A.; Cresswell, M.W.; Linholm, L.W.; Owen, J.C. III; Ellenwood, C.H. [National Inst. of Standards and Technology, Gaithersburg, MD (United States); Hill, T.A.; Benecke, J.D.; Volk, S.R.; Stewart, H.D. [Sandia National Labs., Albuquerque, NM (United States)

1994-02-01

206

Low-Power SOI CMOS Transceiver  

NASA Technical Reports Server (NTRS)

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

207

Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation  

Microsoft Academic Search

This paper presents heterogeneous integration of single-walled carbon nanotubes (SWNTs) with CMOS integrated circuits using die-level post processing. The chip was fabricated using the AMI 0.5 mum CMOS Technology. An electroless zincation process was performed over the Aluminum assembly electrodes (Metal 3 of CMOS technology) to clean and to coat the electrodes with a thin Zinc layer. Low temperature dielectrophoretic

Chia-Ling Chen; Vinay Agarwal; Sameer Sonkusale; Mehmet R. Dokmeci

2008-01-01

208

A 0.13µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation  

NASA Astrophysics Data System (ADS)

A 2.4GHz 0.13µm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13µm CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

209

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process  

Microsoft Academic Search

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design

Chun-Hsien Lien; Chi-Hsueh Wang; Chin-Shen Lin; Pei-Si Wu; Kun-You Lin; Huei Wang

2009-01-01

210

A linear-control wide-band CMOS attenuator  

Microsoft Academic Search

A fully-CMOS controllable attenuator with a multi-octave bandwidth is presented. The linearity of the attenuation control is ensured by a constant-current reference device in a feedback loop, and another self-adjusting control loop is adopted for matching. Realized with a standard 0.8-?m CMOS process, the circuit has a bandwidth of DC-900 MHz with an attenuation tuning range of >28 dB. The

Risto Kaunisto; Petri Korpi; Jiri Kiraly; Kari Haloneri

2001-01-01

211

Low power CMOS adaptive electronic central pattern generator design  

Microsoft Academic Search

In this paper, low power VLSI implementation of adaptive analog controller for autonomous robot is presented using standard CMOS process with 2V supply voltage. Electronic neuron and synapse circuit are developed based on Hindmarsh-Rose neuron model and first order synapse model. In order to achieve low power consumption, CMOS subthreshold circuit techniques are used. The power consumption is 4.8 mW

Young Jun Lee; Jihyun Lee; Yong-Bin Kim; Joseph Ayers

2005-01-01

212

A 13.4GHz CMOS frequency divider  

Microsoft Academic Search

This paper describes the design ofa 13.4 GHz 1\\/2-frequency divider fabricated in a partially-scaled 0.1 ?m bulk CMOS technology. The circuit design is heavily influenced by the device structures and layout rules. To reduce both fabrication cost and turnaround time, the CMOS process scales only channel length to 0.1 ?m and gate oxide to 40 Å. Design rules for other

B. Razavi; K. F. Lee; Ran-Hong Yan

1994-01-01

213

Hafnium oxide and hafnium aluminum oxide for CMOS applications  

Microsoft Academic Search

The continued scaling of the CMOS gate dielectric to its fundamental limit governed by the large gate leakage current requires the introduction of high-k material for sub-100-nm technology nodes. This dissertation research deals with the physical and electrical properties of a promising high-k candidate, hafnium oxide, as a gate dielectric for CMOS applications. Hafnium oxide made by the Jet-Vapor-Deposition process

Wenjuan Zhu

2003-01-01

214

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability  

NASA Astrophysics Data System (ADS)

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 ?m×16 ?m was fabricated in a 0.18 ?m CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

215

2.4GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency  

Microsoft Academic Search

A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-$\\\\mu{\\\\hbox {m}}$ CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency $(f_{T})$ is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor $f_{ T}$, the loss of the

Jin-Siang Syu; Chinchun Meng; Chia-Ling Wang

2011-01-01

216

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

217

Electronics and photonics convergence on Si CMOS platform  

NASA Astrophysics Data System (ADS)

The present paper describes Si microphotonics and its current status of electronics and photonics convergence on Si platform based on monolithic integration using CMOS (Complementary Metal Oxide Semiconductor) technologies. The Si CMOS platform is advantageous over III-V semiconductor based platform because of a short time-lag between basic research and commercialization in terms of the standardized materials and processes. To implement photonic devices on the Si CMOS platform, it is important to reduce materials diversity in current photonics devices. Low loss SiNx waveguides with sharp bends, high performance strained Ge photodetectors for C+L band, and demultiplexer/multiplexer for WDM (wavelength division multiplexing) have been successfully implemented on the Si CMOS platform. The current targets are cost-effective OADMs (optical add-drop multiplexers) for optical communication and optical clocking for Si LSIs beyond Cu-low k technologies.

Wada, Kazumi

2004-07-01

218

A 60GHz down-converting CMOS single-gate mixer  

Microsoft Academic Search

A quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60-GHz, is presented. Also a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers. The performance of a fully-integrated mixer fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency

Sohrab Emami; Chinh H. Doan; Ali M. Niknejad; Robert W. Brodersen

2005-01-01

219

A high-frequency fully differential BiCMOS operational amplifier  

Microsoft Academic Search

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-?m BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin,

Andrew N. Karanicolas; Kenneth K. O; John Y. A. Wang; Hae-Seung Lee; R. L. Reif

1991-01-01

220

Integration of Solar Cells on Top of CMOS Chips Part I: aSi Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process

Jiwu Lu; Alexey Y. Kovalgin; Karine H. M. van der Werf; Ruud E. I. Schropp; Jurriaan Schmitz

2011-01-01

221

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations  

Microsoft Academic Search

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-?m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate\\/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more

Hsiu-Yu Cheng; Ya-Chin King

2003-01-01

222

Development and characterization of CMOS-based monolithic X-ray imager sensor  

Microsoft Academic Search

We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

2007-01-01

223

IR CMOS: infrared enhanced silicon imaging  

NASA Astrophysics Data System (ADS)

SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

2013-06-01

224

CMOS wafer bonding for back-side illuminated image sensors fabrication  

Microsoft Academic Search

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing

V. Dragoi; A. Filbert; S. Zhu; G. Mittendorfer

2010-01-01

225

Total dose hardness of a commercial SiGe BiCMOS technology  

Microsoft Academic Search

Over the past decade SiGe HBT technology has progressed from the laboratory to practical commercial applications. When integrated into a CMOS process, this technology has potential applications in low-cost space systems. In this paper, we report results of total ionizing dose testing of a SiGe\\/CMOS process accessible through a commercial foundry

N. van Vonno; Robert Lucas; David Thornberry

1999-01-01

226

Large area CMOS image sensors  

Microsoft Academic Search

CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to

R. Turchetta; N. Guerrini; I. Sedgwick

2011-01-01

227

Review of CMOS image sensors  

Microsoft Academic Search

The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still

M. Bigas; Enric Cabruja; Josep Forest; Joaquim Salvi

2006-01-01

228

Compact CMOS multispectral/polarimetric camera  

NASA Astrophysics Data System (ADS)

A novel, compact visible multispectral, polarimetric camera is under development. The prototype is capable of megapixel imaging with sixteen wavebands and three polarimetric images. The entire system encompasses a volume less than 125mm x 100mm x 75mm. The system is based on commercial megapixel class CMOS sensors and incorporates real time processing of hyperspectral cube data using a proprietary processor system based on state of the art FPGA technology.

Catanzaro, Brian; Lorenz, Jim; Dombrowski, Mark

2006-06-01

229

A novel CMOS magnetic field sensor array  

Microsoft Academic Search

A CMOS magnetic field sensor array that can be implemented along with analog and digital signal processing circuitry in the form of a single integrated circuit for instrumentation or measurement is discussed. The design realizes a single sensor device through interconnection of a few n-channel magnetic-field-sensitive MOSFETs (MAGFETs) in one circuit. The experimental measurements suggest that the interconnection, which forms

Durgamadhab Misra

1990-01-01

230

CMOS-integrated stress sensor systems  

Microsoft Academic Search

Sensor systems based on piezoresistors have found a wide variety of applications whenever mechanical stress due to external mechanical input is to be determined. Such sensor elements are fabricated using commercial CMOS processes enabling the realization of highly integrated systems with electronics for signal amplification and multiplexing. They combine stress-sensing elements such as Wheatstone bridges, 4- and 8-terminal well-based devices,

P. Ruther; M. Baumann; P. Gieschke; M. Herrmann; B. Lemke; K. Seidl; O. Paul

2010-01-01

231

High-speed CMOS circuit technique  

Microsoft Academic Search

Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

JIREN YUAN; CHRISTER SVENSSON

1989-01-01

232

A photovoltaic-driven and energy-autonomous CMOS implantable sensor.  

PubMed

An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest ?W's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-?W integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes. PMID:23853178

Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

2012-08-01

233

Surface enhanced biodetection on a CMOS biosensor chip  

NASA Astrophysics Data System (ADS)

We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-? and IFN-?). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

2012-02-01

234

CMOS compatible nanoscale nonvolatile resistance switching memory.  

PubMed

We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications. PMID:18217785

Jo, Sung Hyun; Lu, Wei

2008-02-01

235

Low-power 2-D fully integrated CMOS fluxgate magnetometer  

Microsoft Academic Search

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works

Predrag M. Drljaca; Pavel Kejik; Franck Vincent; Dominique Piguet; Radivoje S. Popovic

2005-01-01

236

A 77 GHz 90 nm CMOS transceiver for FMCW radar applications  

Microsoft Academic Search

The fisrt 77 GHz frequency modulated continuos wave (FMCW) radar transceiver IC with an accurate FMCW signal generator using a 90 nm CMOS process is presented. To realize accurate FMCW radar system in CMOS, a PLL synthesizer that is able to output linear FMCW frequency is applied. Measured radar performances, output spectrum and distance of a target, show the transceiver

Toshiya Mitomo; Naoko Ono; Hiroaki Hoshino; Yoshiaki Yoshihara; IOsamu Watanabe; Ichiro Seto

2009-01-01

237

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications  

Microsoft Academic Search

The first 77 GHz frequency modulated continuous wave (FMCW) radar transceiver IC with an accurate FMCW chirp signal generator using a 90 nm CMOS process is presented. To realize accurate FMCW radar system in CMOS, a PLL synthesizer based FMCW generator with chirp smoothing technique that is able to output linear FMCW frequency chirp using a nonlinear reference chirp signal

Toshiya Mitomo; Naoko Ono; Hiroaki Hoshino; Yoshiaki Yoshihara; Osamu Watanabe; Ichiro Seto

2010-01-01

238

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics  

Microsoft Academic Search

Deep-submicron complementary MOS processes have made the development of ASICs for HEP instrumentation possible. In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even

M. Manghisoni; L. Ratti; V. Re; V. Speziali; G. Traversi

2006-01-01

239

A low-cost CMOS compatible serpentine-structured polysilicon-based microbolometer array  

Microsoft Academic Search

This work reports the design, fabrication and initial characterization of novel low-cost CMOS compatible microbolometers and a 16×16 demonstration focal plane array based on the new technology. The bolometers are fabricated as part of a standard CMOS process with maskless postprocessing that includes frontside isotropic silicon dry etching in order to release the serpentine microstructures of the bolometers. FPA readout

Eran Socher; Yehuda Sinai; Y. Nemirovsky

2003-01-01

240

A 90-V subscriber line interface circuit (SLIC) in a CMOS technology  

Microsoft Academic Search

A fully CMOS line interface circuit has been developed as an interface to the subscriber line. This design has been done in a 90-V 1?m CMOS process and performs high voltage functions of an electrical central office subscriber line interface circuit without any transformer and trimming. This design overcomes challenges of SLIC integration such as accurate current sensing, stability on

M. B. Vahidfar; S. Mehrmanesh; A. Tajalli; M. Atarodi

2002-01-01

241

CMOS scaling for high performance and low power-the next ten years  

Microsoft Academic Search

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios

BIJAN DAVARI; ROBERT H. DENNARD; GHAVAM G. SHAHIDI

1995-01-01

242

Prospects of CMOS technology for high-speed optical communication circuits  

Microsoft Academic Search

This paper describes the capabilities of deep-submi- cron CMOS technologies for the realization of highly integrated optical communication transceivers in the range of tens of gigabits per second. Following an overview of a CMOS process, the design of traditional and modern transceivers is presented and speed and integration issues are discussed. Next, the problem of equalization is addressed. Finally, the

Behzad Razavi

2002-01-01

243

An embedded analog spatial filter design of the current-mode CMOS image sensor  

Microsoft Academic Search

This investigation presents an embedded analog spatial filter, EASF, in a current-mode CMOS image sensor. The EASF successfully identifies the output value of the pixel in B\\/W so as to benefit specific real world applications. Over the last few years, image quality has been improved by better progress in CMOS process technology; however, low cost issue regarding the integration of

Pei-Yung Hsiao; Yu-Chun Hsu; Wen-Ta Lee; Chia-Chun Tsai; Chia-Hao Lee

2004-01-01

244

A high speed camera system based on an image sensor in standard CMOS technology  

Microsoft Academic Search

In this contribution a novel camera system developed for high speed imaging will be presented. The core of the system consists of a CMOS image sensor manufactured in a 1 ?m standard CMOS process. The special merit of the image sensor is the capability to acquire more than 1000 frames\\/s using a global electronic shutter in each sensor cell. The

Nenad Stevanovic; Matthias Hillebrand; Bedrich J. Hosticka; Uri Iurgel; Andreas Teuner

1999-01-01

245

A CMOS Humidity Sensor for Passive RFID Sensing Applications  

PubMed Central

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

246

Design and characterization of avalanche photodiodes in submicron CMOS technologies  

NASA Astrophysics Data System (ADS)

The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15?m process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

2014-03-01

247

A CMOS humidity sensor for passive RFID sensing applications.  

PubMed

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

248

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

249

An array-based CMOS biochip for electrical detection of DNA with multilayer self-assembly gold nanoparticles  

Microsoft Academic Search

This paper presents an array-based CMOS biochip for DNA detection using self-assembly multilayer gold nanoparticles (AuNPs). The biochip is fabricated by a TSMC 0.35?m standard CMOS process and post-CMOS micromachining processes. Before taking DNA detection measurements, self-assembly monolayer of AuNPs is established on SiO2 surface between two microelectrodes. The gap distance between the two microelectrodes in this study is less

Yi-Ting Cheng; Ching-Chin Pun; Chien-Ying Tsai; Ping-Hei Chen

2005-01-01

250

Transistor sizing in CMOS circuits  

Microsoft Academic Search

The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

Mehmet A. Cirit

1987-01-01

251

Millimeter-wave CMOS design  

Microsoft Academic Search

Abstract—This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak of 135 GHz has been achieved with optimal device layout. The inductive quality factor is proposed as a more representative metric for transmission lines,

C. H. Doan; S. Emami; A. M. Niknejad; R. W. Brodersen

2005-01-01

252

Monolithic multiple axis accelerometer design in standard CMOS  

NASA Astrophysics Data System (ADS)

Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Out postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all spacial coordinates from a widely-accessible source and at a minimal cost. Fabrication of accelerometers for all three axes and associated electronics on a single piece of silicon reduces the cost of 3D acceleration detection while increasing sensor reliability.

Warneke, Brett; Hoffman, Eric G.; Pister, Kristofer S. J.

1995-09-01

253

IR CMOS: ultrafast laser-enhanced silicon detection  

NASA Astrophysics Data System (ADS)

SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

2011-05-01

254

Black silicon enhanced photodetectors: a path to IR CMOS  

NASA Astrophysics Data System (ADS)

SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Homayoon, H.; Alie, S.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

2010-04-01

255

Predictions of CMOS compatible on-chip optical interconnect  

Microsoft Academic Search

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect

Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas A. Nelson; David H. Albonesi; Philippe M. Fauchet; Eby G. Friedman

256

Deep p-well pixel technology for CMOS back illuminated image sensors  

Microsoft Academic Search

A new technological solution for backside illuminated CMOS imagers is proposed. The pixel area consists of an n-well\\/substrate photo diode and a deep p-well, which contains the APS pixel circuitry as well as additional application specific circuits. This structure was analyzed using Silvaco's ATLAS device simulator. Simulation results show that this structure provides low cross-talk, high photo response and effectively

Y. David; U. Efron

2006-01-01

257

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

NASA Astrophysics Data System (ADS)

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

Zhang, Weiquan

2000-12-01

258

Characterization of spectral optical responsivity of Si-photodiode junction combinations available in a 0.35?m HV-CMOS technology  

NASA Astrophysics Data System (ADS)

The 0.35?m HV-CMOS process technology utilizes several junctions with different doping levels and depths. This process supports complete modular 3V and 5V standard CMOS functionality and offers a wide set of HV transistor types capable for operating voltages from 20V to 120V made available with only 2 more mask adders [1]. Compared to other reported integration of photo detection functionalities in normal CMOS processes [2] or special modified process technologies [3] a much wider variety of junction combinations is already intrinsically available in the investigated technology. Such junctions include beside the standard n+ and p+ source/drain dopings also several combinations of shallow and deep tubs for both p-wells and n-wells. The availability of junction from submicron to 7?m depths enables the selection of appropriate spectral sensitivity ranging from ultraviolet to infrared wavelengths. On the other side by appropriate layouts the contributions of photocurrents of shallower or deeper photo carrier generation can be kept to a minimum. We also show that by analytically modelling the space charge regions of the selected junctions the drift and diffusion carrier contributions can be calculated with a very good match indicating also the suppression of diffusion current contribution. We present examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 380-450nm, 450-600nm or 700-900nm. By appropriate junction choice the ratios of the generated photo currents in their respective peak zones can exhibit more than a factor of 10 compared to the other photo diode combinations. This enables already without further filter implementation a very good spectral resolution for colour sensing applications. Finally the possible junction combinations are also assessed by the achievable dark current for optimized signal to noise characteristic.

Kraxner, A.; Wachmann, E.; Jonak-Auer, I.; Teva, J.; Park, J. M.; Minixhofer, R.

2013-05-01

259

Figures of merit for CMOS SPADs and arrays  

NASA Astrophysics Data System (ADS)

SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

2013-05-01

260

Photon Counting Imager using CMOS Compatible Photodetectors  

Microsoft Academic Search

This work describes a CMOS compatible photodetector purposed for a photon counting imager. Several structures have been designed and implemented using standard industrial CMOS technology. First test results are presented in this paper.

Ville Nieminen; Juha Kostamovaara; Anssi Mäkynen

2006-01-01

261

A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation  

Microsoft Academic Search

A new operation mode for a lateral unified-complementary BiCMOS (hereafter abbreviated as U-CBiCMOS) buffer driver based on a partially depleted CMOS\\/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a n- or p-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFET, with a normal pull-up or pull-down MOSFET as

Toshiro Akino; Takashi Hamahata

2006-01-01

262

Design and research of RS232 communication circuit used for 0.6um CMOS sensor IC  

Microsoft Academic Search

A RS232 transmitter interface circuit used for CMOS sensor IC has been developed in a 0.6mum CMOS technology, which makes it possible to integrate CMOS sensors and subsequent signal processing and communication interface circuits in a single chip. The positive and negative voltages (+7.6V\\/-6.1V under +5V single supply) are achieved with on-chip charge pump, which are used as supply of

Sun-Ying; Zhu-Dazhong

2006-01-01

263

Reset noise suppression in two-dimensional CMOS photodiode pixels through column-based feedback-reset  

Microsoft Academic Search

We present a new CMOS photodiode imager pixel with ultralow read noise through on-chip suppression of reset noise via column-based feedback circuitry. In a 0.5 ?m CMOS process, the pixel occupies only 10×10 ?m2 area. Data from a 2562 CMOS imager indicates imager operation with read noise as low as 6 electrons without employing on- or off-chip correlated double sampling.

B. Pain; T. J. Cunningham; B. Hancock; G. Yang; S. Seshadri; M. Ortiz

2002-01-01

264

Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well  

Microsoft Academic Search

In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 ?m rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage

Weifeng Sun; Longxing Shi

2005-01-01

265

Optimum Design of CMOS DC-DC Converter for Mobile Applications  

NASA Astrophysics Data System (ADS)

In recent years, low output power CMOS DC-DC converters which integrate power stage MOSFETs and a PWM controller using CMOS process have been used in many mobile applications. In this paper, we propose the calculation method of CMOS DC-DC converter efficiency and report optimum design of CMOS DC-DC converter based on this method. By this method, converter efficiencies are directly calculated from converter specifications, dimensions of power stage MOSFET and device parameters. Therefore, this method can be used for optimization of CMOS DC-DC converter design, such as dimensions of power stage MOSFET and switching frequency. The efficiency calculated by the proposed method agrees well with the experimental results.

Katayama, Yasushi; Edo, Masaharu; Denta, Toshio; Kawashima, Tetsuya; Ninomiya, Tamotsu

266

CMOS digital intra-oral sensor for x-ray radiography  

NASA Astrophysics Data System (ADS)

In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

2011-03-01

267

Multiemitter BiCMOS logic circuit family  

Microsoft Academic Search

A new multiemitter BiCMOS circuit using half-micrometer BiCMOS technology with a 3.6-V supply provides 85 % improvement in delay over CMOS design and 40 % improvement over conventional BiCMOS. This benefit is demonstrated in a 64-b carry look-ahead adder where most of the gates have a high number of inputs. A complete logic circuit family based on the multiemitter (ME)

Gerard Boudon; Pierre Mollier; Ieng Ong; Jean-Paul Nuez; Daniel Mauchauffee; Dominique Plassat; Jean-Louis Simonet; Frank Wallart

1991-01-01

268

Single Photon CMOS Imaging Through Noise Minimization  

Microsoft Academic Search

\\u000a This chapter presents the theory and circuitry necessary to build CMOS image sensors with single photon detection capability.\\u000a The chapter begins with the basic theory of CMOS image sensor photon detection. Then a discussion about additive noise systems\\u000a and the sources of noise in CMOS image sensors is presented. Signal amplification and bandwidth control in low-noise CMOS\\u000a image sensors are

Boyd Fowler

269

A resistorless CMOS current reference with temperature compensation  

NASA Astrophysics Data System (ADS)

A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 ?m CMOS process. The output current is 1.5 ?A, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98 ppm/°C, and the line regulation is 0.45%/V. The occupied chip area is 0.065 mm2.

Wei, Yan; Xin, Tian; Wenhong, Li; Ran, Liu

2011-03-01

270

Low capacitance CMOS silicon photodetectors for optical clock injection  

NASA Astrophysics Data System (ADS)

We have studied the response of CMOS compatible detectors fabricated in a silicon-on-sapphire (SOS) process, operated under short pulse excitation in the blue. These high speed, low capacitance detectors would be suitable for very precise, surface-normal clock injection with silicon CMOS. We characterize the capacitance of the detector structure through a combination of experimental techniques and circuit-level and electromagnetic simulations. The transit-time-limited response of the detectors is validated through pump-probe experiments. Detector response times of ˜35 ps have been measured, and devices have capacitance as low as ˜4 fF.

Latif, S.; Kocabas, S. E.; Tang, L.; Debaes, C.; Miller, D. A. B.

2009-06-01

271

Predictive Technology Model of Enhanced CMOS Devices  

Microsoft Academic Search

\\u000a The scaling of traditional bulk CMOS structure has slowed down in recent years as fundamental physical and process limits\\u000a are rapidly approached. For instance, short-channel effects, such as drain-induced-barrier-lowering (DIBL) and threshold voltage\\u000a (Vth) rolloff, severely increase leakage current and degrade the Ion\\/Ioff ratio (Fig. 2.11) [1]. To overcome these difficulties and continue the path projected by Moore’s law, new materials

Yu Cao

272

High-sensitivity 2.5-mum pixel CMOS image sensor realized using Cu interconnect layers  

Microsoft Academic Search

We have adapted Cu interconnect layers to realize a high sensitivity in a small-pixel CMOS image sensor with a pixel size of 2.5 × 2.5 mum. We used the 1P3M CMOS process, and applied Back End of Line (BEOL) with a design rule equivalent to the 90-nm process. The Cu process features a fill factor that is about 15% greater

Keiji Tatani; Yoshiyuki Enomoto; Atsuhiko Yamamoto; Takayuki Goto; Hideshi Abe; Teruo Hirayama

2006-01-01

273

Low-light hyperspectral imager for characterization of biological samples based on an sCMOS image sensor  

NASA Astrophysics Data System (ADS)

The new "scientific CMOS" (sCMOS) sensor technology has been tested for use in hyperspectral imaging. The sCMOS offers extremely low readout noise combined with high resolution and high speed, making it attractive for hyperspectral imaging applications. A commercial HySpex hyperspectral camera has been modified to be used in low light conditions integrating an sCMOS sensor array. Initial tests of fluorescence imaging in challenging light settings have been performed. The imaged objects are layered phantoms labelled with controlled location and concentration of fluorophore. The camera has been compared to a state of the art spectral imager based on CCD technology. The image quality of the sCMOS-based camera suffers from artifacts due to a high density of pixels with excessive noise, attributed to the high operating temperature of the array. Image processing results illustrate some of the benefits and challenges of the new sCMOS technology.

Hernandez-Palacios, J.; Randeberg, L. L.; Haug, I. J.; Baarstad, I.; Løke, T.; Skauli, T.

2011-02-01

274

Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers  

Microsoft Academic Search

The small signal properties of polysilicon TFT opamps have been investigated in this paper. A method for the scaling of gm (transconductance) and gds (output conductance) has been proposed, facilitating their estimates for various transistors in operational amplifiers. The analysis of two CMOS opamps fabricated by a low temperature, glass compatible poly-Si TFT process is demonstrated in comparison to the

Hai-Gang Yang; Steve Fluxman; Carlo Reita; Piero Migliorato

1994-01-01

275

CMOS current amplifiers exhibiting independent AC and DC current amplification  

Microsoft Academic Search

A CMOS circuit topology is demonstrated for the amplification of high-frequency AC currents without requiring similar DC current amplification. This technique is useful for current-domain amplification and processing of signals when low DC power consumption is necessary. Large amounts of AC gain can be achieved using this technique without requiring equivalent DC current gain, which would increase power consumption. Two

Drew Guckenberger; Kevin Kornegay

2005-01-01

276

A 900 MHz low phase noise CMOS quadrature oscillator  

Microsoft Academic Search

A novel method for designing quadrature oscillators is presented. The technique is based on differential coupling at the second harmonic frequency of two separate oscillators. The desired coupling is obtained using an integrated transformer which is attached to the common-mode nodes of two differential oscillators. A 900 MHz prototype has been implemented in a 0.35 ?m CMOS process. The oscillator

Josk Cabanillas; Laurent Dussopt; J. M. Lopez-Villegas; G. M. Rebeiz

2002-01-01

277

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

278

A CMOS image sensor zero power dynamic range increasing technique  

Microsoft Academic Search

A development of in-pixel dynamic range (DR) increasing technique without charging extra power for CMOS image sensor was realized in this paper. Recently, many researches reported that high dynamic range can be achieved through processing the image signals with ADCs or counters built inside the pixel, and some other methods require adjustable circuit block to maneuver photo-generated charges by a

Tsung-Hsun Tsai; Ching-Chun Wang

2009-01-01

279

A CMOS RISC CPU with on-chip parallel cache  

Microsoft Academic Search

This CMOS CPU in a 0.55 ?m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given

Ehsan Rashid; Eric Delano; Ken Chan; Michael Buckley; J. Zheng; F. Schumacher; G. Kurpanek; J. Shelton; T. Alexander; N. Noordeen; M. Ludwig; A. Scherer; C. Amir; D. Cheung; P. Sabada; R. Rajamani; N. Fiduccia; B. Ches; K. Eshghi; F. Eatock; D. Renfrow; J. Keller; P. Ilgenfritz; I. Krashinsky; D. Weatherspoon; S. Ranade; D. Goldberg; W. Bryg

1994-01-01

280

A fuzzy optimization method for CMOS operational amplifier design  

Microsoft Academic Search

The aim of the paper is to present a fuzzy method for the optimization of the CMOS operational amplifier design. Our method uses fuzzy systems or fuzzy sets in all stages involved in the optimization process. In order to reduce the time spent for circuit performance evaluation, we use fuzzy system to model each circuit performance. The optimization problem formulation

Gabriel OLTEAN; Costin MIRON; S. Zahan; Mihaela GORDAN

2000-01-01

281

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K.

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

282

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)  

Microsoft Academic Search

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer

L. Mathew; Y. Du; A. V.-Y. Thean; M. Sadd; A. Vandooren; C. Parker; T. Stephens; R. Mora; R. Rai; M. Zavala; D. Sing; S. Kalpat; J. Hughes; R. Shimer; S. Jallepalli; G. Workman; W. Zhang; J. G. Fossum; B. E. White; B.-Y. Nguyen; J. Mogab

2004-01-01

283

CMOS technology characterization for analog and RF design  

Microsoft Academic Search

The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's “digital” technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution.

Behzad Razavi

1999-01-01

284

Design of a CMOS Tapered Cascaded Multistage Distributed Amplifier  

Microsoft Academic Search

This paper presents the design and measurement of a distributed amplifier (DA) in a standard 90-nm CMOS process. To improve the gain and bandwidth (BW) of the DA, the use of an elevated coplanar waveguide line and also impedance tapering in the synthesized sections are proposed. The effects of elevation and shielding filaments on the impedance, loss, and effective dielectric

Amin Arbabian; Ali M. Niknejad

2009-01-01

285

Total dose hardness of three commercial CMOS microelectronics foundries  

Microsoft Academic Search

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 ?m and 0.8 ?m processes, an Orbit 1.2 ?m process, and an AMI 1.6 ?m process. We

J. V. Osborn; R. C. Lacoe; D. C. Mayer; G. Yabiku

1998-01-01

286

Damage effect on CMOS detector irradiated by single-pulse laser  

NASA Astrophysics Data System (ADS)

Imaging systems are widespread observation tools used to fulfill various functions such as recognition, detection and identification. These devices such as CMOS and CCD can be damaged by laser. It is very important to study the damage mechanism of CMOS and CCD. Previous studies focused on the interference and damage of CCD. There were only a few researches on the interaction of CMOS and the laser. In this paper, using a 60ns, 1064 nm single-pulse laser to radiate the front illuminated CMOS detector, the typical experiment phenomena were observed and the corresponding energy density thresholds were measured. According to the experiment phenomena, hard damage process of CMOS can be divided into 3 stages. Based on the structure and working principle of CMOS, studying the damage mechanism of 3 stages by theoretical analysis, point damage was caused by the increase in leakage current due to structural defects resulting from thermal effects, half black line damage and black lines cross damage were caused by signal interruption due to that the device circuit fuses were cut. Enhancing the laser energy density, the damaged area expanded. Even if the laser energy density reached 1.95 J/cm2, black lines has covered most of the detector pixels, the detector still not completely lapsed, the undamaged area can imaging due to that pixels of CMOS were separated with each other. Experiments on CMOS by laser pulses at the wavelength of 1064 nm and the pulse duration in 25ps was carried out, then the thresholds with different pulse durations were measured and compared. Experiments on CMOS by fs pulsed laser at the frequency of 1 Hz, 10 Hz and 1000 Hz were carried out, respectively, the results showed that a high-repetition-rate laser was easier to damage CMOS compared to single-shot laser.

Guo, Feng; Zhu, Rongzhen; Wang, Ang; Cheng, Xiang'ai

2013-09-01

287

Fully analogue LMS adaptive notch filter in BiCMOS technology [SLIC appls  

Microsoft Academic Search

A fully analogue adaptive notch filter for meter pulse applications in analogue subscriber line systems is presented. Processed in 1 ?m BiCMOS this circuit uses the benefits of accurate SC-filters, low offset comparators and linear multipliers

T. Linder; H. Zojer

1994-01-01

288

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.  

PubMed

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200?mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Kazior, Thomas E

2014-03-28

289

CMOS-integrated silicon 3d force sensor system for micro component coordinate measurement machines  

Microsoft Academic Search

This paper reports a CMOS-integrated three-axial force sensor system realized using a post-CMOS compatible low-temperature fabrication process which allows to process single IC dies as obtained from multi-project wafer (MPW) runs. The sensor system can be applied in coordinate measurement machines used for three-dimensional metrology of microcomponents. It is based on a flexible micromechanical cross structure suspended through thin silicon

B. Levey; P. Gieschke; M. Doelle; A. Trautmann; P. Ruther; O. Paul

2007-01-01

290

A CMOS Time-of-Flight Range Image Sensor With Gates-on-Field-Oxide Structure  

Microsoft Academic Search

This paper presents a new type of CMOS time-of-flight (TOF) range image sensor using single-layer gates on field oxide structure for photo conversion and charge transfer. This simple structure allows the realization of a dense TOF range imaging array with 1515 mum2 pixels in a standard CMOS process. Only an additional process step to create an n-type buried layer which

Shoji Kawahito; Izhal Abdul Halin; Takeo Ushinaga; Tomonari Sawada; Mitsuru Homma; Yasunari Maeda

2007-01-01

291

Low Power CMOS Digital Design  

Microsoft Academic Search

: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which

Anantha P. Chandrakasan; Samuel Sheng; Robert W. Brodersen

1995-01-01

292

Single Photon Imaging in CMOS  

Microsoft Academic Search

CMOS single photon detectors enable large pixel arrays and integrated ancillary circuits. As a consequence, higher timing accuracy and reduced power consumption can be achieved at lower costs. This paper discusses applications and implementation considerations to take into account when designing single photon imagers

Edoardo Charbon

2006-01-01

293

Anodic Ta 2O 5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication  

NASA Astrophysics Data System (ADS)

This paper reports a CMOS compatible fabrication procedure that enables electrowetting-on-dielectric (EWOD) technology to be post-processed on foundry CMOS technology. With driving voltages less than 15 V it is believed to be the lowest reported driving voltage for any material system compatible with post-processing on completed integrated circuits wafers. The process architecture uses anodically grown tantalum pentoxide as a pinhole free high dielectric constant insulator with an overlying 16 nm layer of Teflon-AF ®, which provides the hydrophobic surface for droplets manipulation. This stack provides a very robust dielectric, which maintains a sufficiently high capacitance per unit area for effective operation at a reduced voltage (15 V) which is more compatible with standard CMOS technology. The paper demonstrates that the sputtered tantalum layer used for the electrodes and the formation of the insulating dielectric can readily be integrated with both aluminium and copper interconnect used in foundry CMOS.

Li, Y.; Parkes, W.; Haworth, L. I.; Stokes, A. A.; Muir, K. R.; Li, P.; Collin, A. J.; Hutcheon, N. G.; Henderson, R.; Rae, B.; Walton, A. J.

2008-09-01

294

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio  

Microsoft Academic Search

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

2007-01-01

295

Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based Detector  

Microsoft Academic Search

As the pixel size of CMOS image sensors (CIS) shrink, problems associated with crosstalk become more severe for devices built using mainstream CMOS processing. This high crosstalk increases the amount of noise added to the final image (via an increase of the off-diagonal terms in the color correction matrix (CCM)) and degrades the modulation transfer function (MTF). Reducing dark current

Eric Stevens; Hirofumi Komori; Hung Doan; Hiroaki Fujita; Jeffery Kyan; Christopher Parks; Gang Shi; Cristian Tivarus; Jian Wu

2008-01-01

296

A 1\\/4in 2M pixel CMOS image sensor with 1.75 transistor\\/pixel  

Microsoft Academic Search

A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented. This image achieves a 2.25?m pixel pitch with 25% aperture ratio in a 0.25?m IP2M CMOS process.

M. Mori; M. Katsuno; S. Kasuga; T. Murata; T. Yamaguchi

2004-01-01

297

Development of CMOS-compatible membrane projection lithography  

NASA Astrophysics Data System (ADS)

Recently we have demonstrated membrane projection lithography (MPL) as a fabrication approach capable of creating 3D structures with sub-micron metallic inclusions for use in metamaterial and plasmonic applications using polymer material systems. While polymers provide several advantages in processing, they are soft and subject to stress-induced buckling. Furthermore, in next generation active photonic structures, integration of photonic components with CMOS electronics is desirable. While the MPL process flow is conceptually simple, it requires matrix, membrane and backfill materials with orthogonal processing deposition/removal chemistries. By transitioning the MPL process flow into an entirely inorganic material set based around silicon and standard CMOS-compatible materials, several elements of silicon microelectronics can be integrated into photonic devices at the unit-cell scale. This paper will present detailed fabrication and characterization data of these materials, emphasizing the processing trade space as well as optical characterization of the resulting structures.

Burckel, D. Bruce; Samora, Sally; Wiwi, Mike; Wendt, Joel R.

2013-09-01

298

Dissection of c-MOS degron  

PubMed Central

c-MOS, a MAP kinase kinase kinase, is a regulator of oocyte maturation. The concentration of c-MOS is controlled in part through its conditional degradation. Previous studies proposed the ‘second-codon rule’, according to which the N-terminal proline (Pro) of c-MOS is a destabilizing residue that targets c-MOS for degradation. We analyzed the degradation signal (degron) of c-MOS in Xenopus oocytes, found it to be a portable degron, and demonstrated that, contrary to the model above, the N-terminal Pro residue of c-MOS is entirely dispensable for its degradation if Ser-2 (encoded Ser-3) of c-MOS is replaced by a small non-phosphorylatable residue such as Gly. The dependence of c-MOS degradation on N-terminal Pro is shown to be caused by a Pro-mediated downregulation of the net phosphorylation of Ser-2, a modification that halts c-MOS degradation in oocytes. Thus, the N-terminal Pro residue of c-MOS is not a recognition determinant for a ubiquitin ligase, in agreement with earlier evidence that Pro is a stabilizing residue in the N-end rule.

Sheng, Jun; Kumagai, Akiko; Dunphy, William G.; Varshavsky, Alexander

2002-01-01

299

Flicker noise behavior of MOSFETs fabricated in 0.5 ?m fully depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate, and strong inversion  

Microsoft Academic Search

This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in the Peregrine 0.5 ?m fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented

M. N. Ericson; J. M. Rochelle; B. J. Blalock; D. M. Binkley; A. L. Wintenberg; B. D. Williamson

2003-01-01

300

Noise behavior of MOSFETs fabricated in 0.5 ?m fully-depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate,, and strong inversion  

Microsoft Academic Search

This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in a 0.5 ?m fully-depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the noise behavior of SOS devices will be presented and discussed with

M. N. Ericson; J. M. Rochelle; B. J. Blalock; D. M. Binkley; A. L. Wintenberg; B. D. Williamson

2002-01-01

301

A low-cost modular SiGe BiCMOS technology and analog passives for high-performance RF and wide-band applications  

Microsoft Academic Search

We present a low-cost 0.25 ?m SiGe BiCMOS technology that is being manufactured in an 8-inch production line. The technology includes modules for super-self-aligned (SSA) SiGe transistors, poly resistors, metal-oxide-metal (MOM) capacitors and thick-metal inductors added to a CMOS core process without any change to the CMOS process. With the independently developed modules and a high-energy implanted collector buried layer,

R. Tang; C. Leung; D. Nguyen; T. Hsu; L. Fritzinger; S. Molloy; T. Esry; T. Ivanov; J. Chu; M. Carroll; J. Huang; W. Moller; T. Campbell; W. Cochran; C. King; M. Frei; M. Mastrapasqua; K. Ng; C. Chen; R. Johnson; R. Pullela; V. Archer; J. Krska; S. Moinian; H. Cong

2000-01-01

302

CMOS image sensor with contour enhancement  

NASA Astrophysics Data System (ADS)

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5?m DPTM CMOS process.

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-05-01

303

Research-grade CMOS image sensors for demanding space applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2004-06-01

304

Research-grade CMOS image sensors for remote sensing applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

2004-11-01

305

Higher efficiency silicon CMOS light-emitting devices (450nm - 750nm) using current density and carrier injection techniques  

NASA Astrophysics Data System (ADS)

In this paper we report on the dependency of quantum efficiency of an avalanching light emitting junction on current density and on the injection current from an adjacent lying forward biased junction. In particular, we report on the interpretation of results and modelling of the physical processes responsible for the light emission. The phenomenon was observed in a three terminal silicon bipolar junction CMOS light emitting device (Si BJ CMOS LED). Our observations show that the overall quantum efficiency and light emission from these type of devices can be improved to the 10-3 regime. The optical emissions is about four orders higher than the low frequency detectivity for silicon CMOS detectors of comparable dimension. The three terminal device also enable modulation of the light emission by a third terminal contact. The device has the potential of being fully integratable with standard CMOS integrated circuitry with no adaptation to the CMOS design and processing procedures.

Snyman, Lukas W.; du Plessis, Monuko; Aharoni, Herzl

2005-03-01

306

CMOS planar 2D micro-fluxgate sensor  

Microsoft Academic Search

An electronic compass made of a new planar 2D micro-fluxgate sensor is presented. The magnetometer is integrated in a standard CMOS process, and uses a post-processed cross-shaped ferromagnetic amorphous core. This core is diagonally placed above a single square excitation coil common to both measurement axes. The silicon chip includes the driving and readout electronics, the excitation and pick-up coils

L. Chiesi; P. Kejik; B. Janossy; R. S. Popovic

2000-01-01

307

Single core fully integrated CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

A new fully integrated 2D micro-fluxgate magnetometer is presented. This magnetometer is integrated in a standard CMOS process and uses a ferromagnetic core integrated on the chip by a photolithographic post-process compatible with the integrated circuit technology. The cross-shaped ferromagnetic core is placed diagonally above four excitation coils, two for each measurement axis. A novel electronic signal extraction technique is

Predrag M. Drlja?a; Pavel Kejik; Franck Vincent; Dominique Piguet; François Gueissaz; Radivoje S. Popovi?

2004-01-01

308

1\\/f noise in CMOS transistors for analog applications  

Microsoft Academic Search

Noise measurements of the 1\\/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 ?m and 0.5 ?m technologies are compared and it is found that the more advanced process, with 0.5 ?m technology, exhibits significantly reduced 1\\/f noise, due to optimized

Yael Nemirovsky; Igor Brouk; Claudio G. Jakobson

2001-01-01

309

High speed CMOS technology for ASIC application  

Microsoft Academic Search

In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 µm, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD3structure is employed for 1.0 µm

H. Ooka; S. Murakami; M. Murayama; K. Yoshida; S. Takao; O. Kudoh

1986-01-01

310

1\\/f noise in advanced CMOS transistors  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology is dominant in the microelectronics industry for a wide range of applications, including analog, digital, RF, and sensor systems. The advantages of silicon CMOS technology compared to bipolar technology as well as transistors in other semiconductors is well-established. CMOS technology scaling has been a main drive for continuous progress in the silicon based semiconductor industry over

Yael Nemirovsky; Dan Corcos; Igor Brouk; Amikam Nemirovsky; Samir Chaudhry

2011-01-01

311

Performance of downward scaled CMOS\\/SOS  

Microsoft Academic Search

MOS\\/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS\\/ SOS devices. Furthermore, short channel CMOS\\/SOS device performance has been discussed in comparison with the CMOS\\/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through

Sinji TAGUCHI; Hiroyuki TANGO; Kenji MAEGUCHI; Luong Mo Dang

1979-01-01

312

An advanced 0.4 ?m BiCMOS technology for high performance ASIC applications  

Microsoft Academic Search

An advanced 0.4 ?m BiCMOS technology has been developed for high-performance ASIC (application-specific integrated circuit) applications. The technology consists of a core 3.3 V CMOS process featuring 0.4 ?m effective channel lengths into which a high-performance n-p-n device module has been integrated. The ECL (emitter coupled logic) circuits are designed to operate with a conventional supply voltage of 5.2 V

J. Kirchgessner; J. Teplik; V. Ilderem; D. Morgan; R. Parmar; S. R. Wilson; J. Freeman; C. Tracy; S. Cosentino

1991-01-01

313

A half-micron super self-aligned BiCMOS technology for high speed applications  

Microsoft Academic Search

We report the process design, device characteristics and circuit performance of a new ultra high speed, high density, half-micron super self-aligned BiCMOS technology. The minimum CMOS gate delay was measured to be 38 psec on 0.5 ?m gate and 50 psec on 0.6 ?M gate ring oscillators at 5 volt. Bipolar gate delay was measured to be 31 psec on

T. M. Liu; G. M. Chin; D. Y. Jeon; M. D. Morris; V. D. Archer; H. H. Kim; M. Cerullo; K. F. Lee; J. M. Sung; K. Lau; T. Y. Chiu; A. M. Voshchenkov; R. G. Swartz

1992-01-01

314

An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications  

Microsoft Academic Search

This paper proposes a new low-voltage high resolution complementary metal oxide semiconductor (CMOS) comparator circuit suitable\\u000a for biosensor applications. The comparator compensates for differential input offset through single-ended sampled-data preamplification.\\u000a Simulations were carried out using a 130 nm IBM CMOS (CMRF8SF) process technology. Monte Carlo simulations incorporating mismatch\\u000a between devices (based on width and length of devices) indicate that the design

2008-01-01

315

High sensitivity and no-cross-talk pixel technology for embedded CMOS image sensor  

Microsoft Academic Search

A high-photosensitivity and no-cross-talk pixel technology has been developed for an embedded active-pixel CMOS image sensor using a 0.35-?m CMOS logic process. To increase photosensitivity, we developed a deep low-concentration p-well (deep p-well) photodiode. To suppress pixel cross-talk caused by obliquely incident light, a double-metal photoshield was used. The cross-talk caused by electron diffusion in the substrate was suppressed by

M. Furumiya; H. Ohkubo; Y. Muramatsu; S. Kurosawa; Y. Nakashiba

2000-01-01

316

High-sensitivity and no-crosstalk pixel technology for embedded CMOS image sensor  

Microsoft Academic Search

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-?m CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si3N4 film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used

Masayuki Furumiya; Hiroaki Ohkubo; Yasunori Muramatsu; Susumu Kurosawa; Fuyuki Okamoto; Yuki Fujimoto; Yasutaka Nakashiba

2001-01-01

317

A SiGe HBT BiCMOS technology for mixed signal RF applications  

Microsoft Academic Search

We present results of IBM's Silicon Germanium HBT 0.35 ?m Leff BiCMOS process with 3 level metal on 200 mm wafers. CMOS devices, as well as resistors, capacitors, inductors and other key passive elements are integrated into a high performance SiGe HBT NPN technology without sacrificing key bipolar characteristics (ft, fmax). These results demonstrate the potential of designing analog\\/mixed signal

D. C. Ahlgren; G. Freeman; S. Subbanna; R. Groves; D. Greenberg; J. Malinowski; D. Nguyen-Ngoc; S. J. Jeng; K. Stein; K. Schonenberg; D. Kiesling; B. Martin; S. Wu; D. L. Harame; B. Meyerson

1997-01-01

318

Design of a 15MHz CMOS continuous-time filter with on-chip tuning  

Microsoft Academic Search

A fifth-order CMOS continuous-time Bessel filter with a tunable 6- to 15-MHz cutoff frequency is described. This fully balanced transconductance-capacitor (Gm-C) leapfrog filter achieves a dynamic range of 55 dB while dissipating 96 mW in a 5-V 0.9-?m CMOS process. The author reviews the disk drive application and filtering requirements, and explains why the G m-C continuous-time filtering approach was

J. M. Khoury

1991-01-01

319

A 200MHz CMOS phase-locked loop with dual phase detectors  

Microsoft Academic Search

,4bstrszct —A high-frequency integrated CMOS phase-locked loop (PLL) inckrdlng two phase detectors is presented. Tfse design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase- frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2-pm CMOS p-well process was used to fabricate the circuit.

KURT M. WARE; HAE-SEUNG LEE; CHARLES G. SODINI

1989-01-01

320

A 65-nm CMOS Fully Integrated Transceiver Module for 60GHz Wireless HD Applications  

Microsoft Academic Search

A fully integrated WirelessHD compatible 60-GHz transceiver module in 65-nm CMOS process is presented, covering the four standard channels. The silicon die is flip-chipped on top of a low-cost HTCC module which also includes an external 65-nm CMOS PA and large beamwidth antennas targeting industrial manufacturability. The module achieves a 16QAM OFDM mod- ulation wireless link with 3.8 Gbps over

Alexandre Siligaris; Olivier Richard; Baudouin Martineau; Christopher Mounet; Fabrice Chaix; Romain Ferragut; Cedric Dehos; Jérôme Lanteri; Laurent Dussopt; Silas D. Yamamoto; Romain Pilard; Pierre Busson; Andreia Cathelin; Didier Belot; Pierre Vincent

2011-01-01

321

A 2.2M CMOS image sensor for high-speed machine vision applications  

Microsoft Academic Search

This paper describes a 2.2 Megapixel CMOS image sensor made in 0.18 mum CMOS process for high-speed machine vision applications. The sensor runs at 340 fps with digital output using 16 LVDS channels at 480MHz. The pixel array counts 2048x1088 pixels with a 5.5um pitch. The unique pixel architecture supports a true correlated double sampling, thus yields a noise level

Xinyang Wang; Jan Bogaerts; Guido Vanhorebeek; Koen Ruythoren; Bart Ceulemans; Gérald Lepage; Pieter Willems; Guy Meynants

2010-01-01

322

High-performance CMOS variability in the 65-nm regime and beyond  

Microsoft Academic Search

Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a

Kerry Bernstein; David J. Frank; Anne E. Gattiker; Wilfried Haensch; Brian L. Ji; Sani R. Nassif; Edward J. Nowak; Dale J. Pearson; Norman J. Rohrer

2006-01-01

323

Technologies for (sub-) 45nm Analog\\/RF CMOS - Circuit Design Opportunities and Challenges  

Microsoft Academic Search

The new process module and device architecture options emerging for (sub-) 45nm CMOS, lead to both opportunities and challenges for analog\\/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for

S. Decoutere; P. Wambacq; V. Subramanian; J. Borremans; A. Mercha

2006-01-01

324

Ultra-thin SOI CMOS with selective CVD tungsten for low-resistance source and drain  

Microsoft Academic Search

This paper describes a new ultra-thin SOI-CMOS structure with reduced parasitic diffusion layer resistance. Using a selective CVD tungsten process on the source and drain regions, we experimentally investigate the characteristics of the selectively grown W for SOI layers of various thicknesses (10-200 nm) and CMOS device characteristics. For this structure, the reaction between SOI-Si and W is unnecessary, and

Digh Hisamoto; Kaori Nakamura; Masayoshi Saito; Nobuyoshi Kobayashi; S. Kimura; R. Nagai; T. Nishida; E. Takeda

1992-01-01

325

1Gb\\/s integrated optical detectors and receivers in commercial CMOS technologies  

Microsoft Academic Search

The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and

T. K. Woodward; Ashok V. Krishnamoorthy

1999-01-01

326

Multiple type biosensors fabricated using the CMOS BioMEMS platform  

Microsoft Academic Search

This paper reports a CMOS BioMEMS (biological micro-electromechanical system) platform for monolithically integrated multi-type biosensors and readout circuits. Gold is implemented in the current CMOS MEMS platform as an absorption layer for bio targets by wafer-level process tools. The characteristics of the gold and piezoresistive cantilever structures are analyzed. Two kinds of biosensors are fabricated and investigated in this work.

Hann-Huei Tsai; Chen-Fu Lin; Ying-Zong Juang; I-Long Wang; Yu-Cheng Lin; Ruey-Lue Wang; Hung-Yin Lin

2010-01-01

327

A 300mV 494GOPS\\/W reconfigurable dual-supply 4Way SIMD vector processing accelerator in 45nm CMOS  

Microsoft Academic Search

High-throughput parallel SIMD vector computations are the most performance and power-critical operations in multimedia, graphics and signal processing workloads. An array of SIMD vector processing engines delivers high- throughput short bit-width arithmetic operations on large data sets with orders of magnitude higher energy efficiencies vs. general-purpose cores. A reconfigurable 4-way SIMD engine targeted for on-die acceleration of vector processing in

Himanshu Kaul; Mark A. Anders; Sanu K. Mathew; Steven K. Hsu; Amit Agarwal; Ram K. Krishnamurthy; Shekhar Borkar

2009-01-01

328

High current CMOS operational amplifier  

Microsoft Academic Search

This paper describes a low voltage CMOS operational amplifier, which is capable of driving heavy resistive and capacitive loads. Robust and power efficient compensation is achieved by using Miller compensation together with a high bandwidth stage. Measurements show that the amplifier achieves 5.7 MHz unity gain frequency and 61° phase margin when driving 1nF||1k? load, while drawing 2.4mA from 1.5V

Mikko Loikkanen; Juha Kostamovaara

2005-01-01

329

A CMOS vision system on-chip with multicore sensory processing architecture for image analysis above 1,000F/s  

NASA Astrophysics Data System (ADS)

This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand's frame-per-second rate. The chip employs a distributed processing architecture with a pre-processing stage consisting of an array of programmable sensory-processing cells, and a post-processing stage consisting of a digital microprocessor. The pre-processing stage operates as a retina-like sensor front-end. It performs parallel processing of the images captured by the sensors which are embedded together with the processors. This early processing serves to extract image features relevant to the intended tasks. The front-end incorporates also smart read-out structures which are conceived to transmit only these relevant features, thus precluding full gray-scale frames to be coded and transmitted. The chip is capable to close action-reaction loops based on the analysis of visual flow at rates above 1,000F/s with power budget below 1W peak. Also, the incorporation of processors close to the sensors enables signal-dependent, local adaptation of the sensor gains and hence highdynamic range signal acquisition.

Rodríguez-Vázquez, Angel; Domínguez-Castro, Rafael; Jiménez-Garrido, Francisco; Morillas, Sergio

2010-02-01

330

A 5.8GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-?m CMOS technology [WLANs  

Microsoft Academic Search

A 5.8-GHz two-stage high-linearity low-voltage CMOS low-nose amplifier (LNA) has been developed in a 0.35-?m pure digital CMOS technology without any additional mask or post-processing steps. A two-stage architecture is used to simultaneously optimize the gain and noise performance. Based on the modified CMOS model valid for RF range, the LNA with fully on-chip input, output and inter-stage matching was

Ren-Chieh Liu; Chung-Rung Lee; Chorng-Kuang Wang

2002-01-01

331

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass  

PubMed Central

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

332

Teledyne Imaging Sensors: silicon CMOS imaging technologies for x-ray, UV, visible, and near infrared  

NASA Astrophysics Data System (ADS)

Teledyne Imaging Sensors develops and produces high performance silicon-based CMOS image sensors, with associated electronics and packaging for astronomy and civil space. Teledyne's silicon detector sensors use two technologies: monolithic CMOS, and silicon PIN hybrid CMOS. Teledyne's monolithic CMOS sensors are large (up to 59 million pixels), low noise (2.8 e- readout noise demonstrated, 1-2 e- noise in development), low dark current (<10 pA/cm2 at 295K) and can provide in-pixel snapshot shuttering with >103 extinction and microsecond time resolution. The QE limitation of frontside-illuminated CMOS is being addressed with specialized microlenses and backside illumination. A monolithic CMOS imager is under development for laser guide star wavefront sensing. Teledyne's hybrid silicon PIN CMOS sensors, called HyViSITM, provide high QE for the x-ray through near IR spectral range and large arrays (2K×2K, 4K×4K) are being produced with >99.9% operability. HyViSI dark current is 5-10 nA/cm2 (298K), and further reduction is expected from ongoing development. HyViSI presently achieves <10 e- readout noise, and new high speed HyViSI arrays being produced in 2008 should achieve <4 e- readout noise at 900 Hz frame rate. A Teledyne 640×480 pixel HyViSI array is operating in the Mars Reconnaissance Orbiter, a 1K×1K HyViSI array will be launched in 2008 in the Orbiting Carbon Observatory, and HyViSI arrays are under test at several astronomical observatories. The advantages of CMOS in comparison to CCD include programmable readout modes, faster readout, lower power, radiation hardness, and the ability to put specialized processing within each pixel. We present one example of in-pixel processing: event driven readout that is optimal for lightning detection and x-ray imaging.

Bai, Yibin; Bajaj, Jagmohan; Beletic, James W.; Farris, Mark C.; Joshi, Atul; Lauxtermann, Stefan; Petersen, Anders; Williams, George

2008-08-01

333

Smart CMOS image sensor for lightning detection and imaging.  

PubMed

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

334

A back-illuminated megapixel CMOS image sensor  

NASA Technical Reports Server (NTRS)

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

335

A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF  

Microsoft Academic Search

Traditionally, CMOS operational amplifiers apply cascoding techniques to ensure an acceptable gain with a minimal number of gain stages. The use of cascode transistors, however, limits the lowest supply voltage of a CMOS op amp. Lowering the threshold voltage of the MOS process, a development already initiated by many VLSI processing facilities, does not lead to a lower minimum supply

Ruud G. H. Eschauzier; Ron Hogervorst; Johan H. Huijsing

1994-01-01

336

A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 ?m2 6-T SRAM cell  

Microsoft Academic Search

This paper presents a highly-manufacturable process technology featuring SiGe HBT devices fully integrated into a 90 nm leading-edge high performance CMOS technology. The technology was developed on a 300 mm wafer platform, and supports process elements including RF CMOS devices, a MIM capacitor, precision resistors, high-Q inductors and varactors.

K. Kuhn; M. Agostinelli; S. Ahmed; S. Chambers; S. Cea; S. Christensen; P. Fischer; J. Gong; C. Kardas; T. Letson; L. Henning; A. Murthy; H. Muthali; B. Obradovic; P. Packan; S. W. Pae; I. Post; S. Putna; K. Raol; A. Roskowski; R. Soman; T. Thomas; P. Vandervoorn; M. Weiss; I. Young

2002-01-01

337

Transistor sizing for low power CMOS circuits  

Microsoft Academic Search

A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area.

Manjit Borah; Robert Michael Owens; Mary Jane Irwin

1996-01-01

338

JFET-CMOS microstrip front-end  

Microsoft Academic Search

While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper.

W. Buttler; V. Liberali; G. Lutz; F. Maloberti; P. F. Manfredi; V. Re; V. Speziali

1989-01-01

339

On fault detection in CMOS logic networks  

Microsoft Academic Search

This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test

Kuang-Wei Chiang; Zvonko G. Vranesic

1983-01-01

340

5GHz CMOS LC VCOs with wide tuning ranges  

Microsoft Academic Search

A 4.8-GHz LC voltage-controlled oscillator (VCO) optimized for maximum tuning range was designed and fabricated using 0.25-?m 1P5M CMOS process. The optimized design used an inverse proportionality between the two parasitic capacitances of the inductor and the MOS transistors for minimizing the parasitic capacitance at the oscillation node. The fabricated LC VCO has a wide tuning range of 20.3% from

Byunghun Min; Hanggeun Jeong

2005-01-01

341

A reconfigurable op-amp\\/DDA CMOS amplifier architecture  

Microsoft Academic Search

A simple architecture for a configurable op-amp or differential difference amplifier (DDA) is presented. The circuitry can be configured as an input\\/output rail to rail high-speed op-amp, or as a DDA. The circuit was simulated using SPICE and fabricated in a 2-?m CMOS process through MOSIS. Configured as an op-amp, it achieves a positive and negative slew rate of 16

Seyed R. Zarabadi; Frode Larsen; Mohammed Ismail

1992-01-01

342

Total dose radiation response of CMOS compatible SOI MESFETs  

Microsoft Academic Search

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi2 Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The

John Spann; Vadim Kushner; Trevor J. Thornton; Jinman Yang; A. Balijepalli; H. J. Barnaby; Xiao Jie Chen; D. Alexander; W. T. Kemp; S. J. Sampson; M. E. Wood

2005-01-01

343

CMOS analog front-end for conversational video phone modem  

Microsoft Academic Search

A description is given of an analog front-end chip relating to a video phone for transmission of audio signals and freeze-frame video images over voice-grade telephone lines. The device is implemented in a 3-?m CMOS process, utilizes switched-capacitor circuit technology and contains major functional blocks, such as a synchronous demodulator, transmit\\/receive filters, baseband and interpolating filters, an 8-bit digital-to-analog converter,

C. W. Solomon; L. Ozcolak; G. Sellani; W. E. Brisco

1989-01-01

344

A Translinear, Log-Domain FPAA on Standard CMOS Technology  

Microsoft Academic Search

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I\\/O programmable cell, which allows for easier connectivity between the signal-processing core

Daniel Fernandez; Luís Martinez-Alvarado; Jordi Madrenas

2012-01-01

345

Multilayer CMOS device fabricated on laser recrystallized silicon islands  

Microsoft Academic Search

Multilayer CMOS devices were fabricated by a laser recrystallization technology. The single crystalline silicon islands embedded in an insulator on the top of MOS IC were studied. To minimize the thermal influence on a lower IC during the fabrication process, a CVD-SiO2was used as a retaining wall of silicon islands instead of a LOCOS. In addition, a planarized heat sink

S. Akiyama; S. Ogawa; M. Yoneda; N. Yoshii; Y. Terui

1983-01-01

346

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT  

NASA Astrophysics Data System (ADS)

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

2013-12-01

347

Peak crosstalk noise estimation in CMOS VLSI circuits  

Microsoft Academic Search

Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of flight delay of the signal through the interconnect. In this paper, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver

Kevin T. Tang; Eby G. Friedman

1999-01-01

348

Accelerated life testing effects on CMOS microcircuit characteristics  

NASA Technical Reports Server (NTRS)

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

1977-01-01

349

A new CMOS-based digital imaging detector for applications in mammography  

NASA Astrophysics Data System (ADS)

We have developed a CMOS-based x-ray imaging detector in the same form factor of a standard film cassette (18 cm × 24 cm) for Small Field-of-view Digital Mammography (SFDM) applications. This SFDM cassette is based on our three-side buttable, 25 mm × 50 mm, 48?m active-pixel CMOS sensor modules and utilizes a 150?m columnar CsI(Tl) scintillator. For imaging up to 100 mm × 100 mm field-of-view, a number of CMOS sensor modules need to be tiled and electronically synchronized together. By using fiber-optic communication, acquired images from the SFDM cassette can be transferred, processed and displayed on a review station within approximately 5 seconds of exposure, greatly enhancing patient flow. We present the physical performance of this CMOS-based SFDM cassette, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and more subjective criteria, by evaluating images from a phantom study and the clinical studies of our collaborators. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for digital mammography today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. The SFDM cassette can be employed in various mammography applications, including spot imaging, stereotactic biopsy imaging, core biopsy and surgical biopsy specimen radiography. This study demonstrates that all the image quality requirements for demanding mammography applications can be addressed with CMOS technology.

Baysal, Mehmet A.; Toker, Emre

2005-09-01

350

CMOS foveal image sensor chip  

NASA Technical Reports Server (NTRS)

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

351

Nanowatt-Power-Level Automatic Switch Combining ED-CMOS Circuit and LED  

NASA Astrophysics Data System (ADS)

A nanowatt-power-level automatic switch that combines a multi-Vth CMOS level converter and an LED as a photodiode has been developed for a sensor application. The level converter is a single-input latch-type multi-Vth CMOS circuit featuring the use of an enhancement-mode nMOSFET and a depletion-mode common-gate nMOSFET as a pair of driver transistors. The ED-CMOS level converter cuts the DC current path; and the LED, which generates a high output voltage under illumination, suppresses the leakage current of the depletion-mode common-gate nMOSFET in the ED-CMOS level converter, resulting in nanowatt-order power dissipation. To verify the effectiveness of the ED-CMOS circuit, a prototype level converter was fabricated on a 0.6-µm CMOS process and used in an automatic switch in a wireless mouse. The switch is composed of two LEDs, a current-mirror circuit, the level converter, and a power switch MOSFET. It senses when a hand grabs or releases the mouse and automatically turns the mouse on or off, respectively. The measured power dissipation of the mouse is 3nW in the standby mode.

Utsunomiya, Fumiyasu; Douseki, Takakuni

352

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.  

PubMed

Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power. PMID:23366924

Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

2012-01-01

353

High-Voltage-Input Level Translator Using Standard CMOS  

NASA Technical Reports Server (NTRS)

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

354

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

355

Seamless integration of CMOS and microfluidics using flip chip bonding  

NASA Astrophysics Data System (ADS)

We demonstrate the microassembly of PDMS (polydimethylsiloxane) microfluidics with integrated circuits made in complementary metal-oxide-semiconductor (CMOS) processes. CMOS-sized chips are flip chip bonded to a flexible polyimide printed circuit board (PCB) with commercially available solder paste patterned using a SU-8 epoxy. The average resistance of each flip chip bond is negligible and all connections are electrically isolated. PDMS is attached to the flexible polyimide PCB using a combination of oxygen plasma treatment and chemical bonding with 3-aminopropyltriethoxysilane. The total device has a burst pressure of 175 kPA which is limited by the strength of the flip chip attachment. This technique allows the sensor area of the die to act as the bottom of the microfluidic channel. The SU-8 provides a barrier between the pad ring (electrical interface) and the fluids; post-processing is not required on the CMOS die. This assembly method shows great promise for developing analytic systems which combine the strengths of microelectronics and microfluidics into one device.

Welch, David; Blain Christen, Jennifer

2013-03-01

356

Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays  

PubMed Central

We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400×400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 ?m × 30 ?m. The devices exhibited sensitivity of 6.2 ?C/Rcm2 with corresponding dark current of ?2.7 nA/cm2, and a 80 ?m FWHM planar image response to a 50 ?m slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 ?m spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 ?m), fast readout speeds (8 fps for a 3200×3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes.

Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

2009-01-01

357

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

PubMed Central

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

2010-01-01

358

Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays.  

PubMed

We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI(2)) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400x400 pixel HgI(2)-coated CMOS readout chips are presented, where the pixel grid is 30 mum x 30 mum. The devices exhibited sensitivity of 6.2 muC/Rcm(2) with corresponding dark current of approximately 2.7 nA/cm(2), and a 80 mum FWHM planar image response to a 50 mum slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 mum spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 mum), fast readout speeds (8 fps for a 3200x3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

Hartsough, Neal E; Iwanczyk, Jan S; Nygard, Einar; Malakhov, Nail; Barber, William C; Gandhi, Thulasidharan

2009-08-01

359

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

NASA Astrophysics Data System (ADS)

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, -1.9 and 6.5 pm V-1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

Doll, Joseph C.; Petzold, Bryan C.; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L.

2010-02-01

360

A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces  

Microsoft Academic Search

A 25 MHz all-CMOS clock generator is demonstrated where measured performance makes it suitable for direct replacement of the reference crystal oscillator (XO) for serial wire interfaces. Fabricated in a 0.25 mum 1P5M logic CMOS process, and with no external components, the developed clock generator dissipates 59.4 mW while exhibiting plusmn152 ppm frequency error over process, plusmn10% variation in the

Michael S. Mccorquodale; Scott M. Pernia; Sundus Kubba; Gordy A. Carichner; Justin D. O'day; Eric D. Marsman; Jon Kuhn; Richard B. Brown

2008-01-01

361

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS  

Microsoft Academic Search

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

2004-01-01

362

Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors  

Microsoft Academic Search

A scheme for low-voltage CMOS op-amp operation with rail-to-rail input and output signal swing and constant gm is presented. Single-ended and fully differential versions are discussed. The scheme is based on the use of multiple-input floating-gate transistors and allows direct implementation of linear weighted addition of continuous-time signals. Simulations are presented that verify the scheme operating with a 1.2-V single

J. Ramirez-Angulo; R. G. Carvajal; J. Tombs; A. Torralba

2001-01-01

363

A CMOS 18 THz? 248 Mb\\/s transimpedance amplifier and 155 Mb\\/s LED-driver for low cost optical fiber links  

Microsoft Academic Search

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 ?m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is

Mark Ingels; Geert Van der Plas; Jan Crols; Michel Steyaert

1994-01-01

364

CMOS Alcohol Sensor Employing ZnO Nanowire Sensing Films  

NASA Astrophysics Data System (ADS)

This paper reports on the utilization of zinc oxide nanowires (ZnO NWs) on a silicon on insulator (SOI) CMOS micro-hotplate for use as an alcohol sensor. The device was designed in Cadence and fabricated in a 1.0 ?m SOI CMOS process at XFAB (Germany). The basic resistive gas sensor comprises of a metal micro-heater (made of aluminum) embedded in an ultra-thin membrane. Gold plated aluminum electrodes, formed of the top metal, are used for contacting with the sensing material. This design allows high operating temperatures with low power consumption. The membrane was formed by using deep reactive ion etching. ZnO NWs were grown on SOI CMOS substrates by a simple and low-cost hydrothermal method. A few nanometer of ZnO seed layer was first sputtered on the chips, using a metal mask, and then the chips were dipped in a zinc nitrate hexahydrate and hexamethylenetramine solution at 90° C to grow ZnO NWs. The chemical sensitivity of the on-chip NWs were studied in the presence of ethanol (C2H5OH) vapour (with 10% relative humidity) at two different temperatures: 200 and 250° C (the corresponding power consumptions are only 18 and 22 mW). The concentrations of ethanol vapour were varied from 175-1484 ppm (pers per million) and the maximum response was observed 40% (change in resistance in %) at 786 ppm at 250° C. These preliminary measurements showed that the on-chip deposited ZnO NWs could be a promising material for a CMOS based ethanol sensor.

Santra, S.; Ali, S. Z.; Guha, P. K.; Hiralal, P.; Unalan, H. E.; Dalal, S. H.; Covington, J. A.; Milne, W. I.; Gardner, J. W.; Udrea, F.

2009-05-01

365

CMOS \\  

Microsoft Academic Search

Fully integrated imaging receivers present a method of low power free-space optical communication with advantages over radio frequency and single element optical communication for a variety of network scenarios. This paper discusses the theoretical performance of such receivers and the design of a single \\

Brian S. Leibowitz; Bernhard E. Boser; Kristofer S. J. Pister; Berkeley Sensor

2001-01-01

366

Physics of Modern VLSI CMOS  

NASA Astrophysics Data System (ADS)

The Integrated Circuit (IC) was invented in 1958, and modern CMOS was invented in 1980. The semiconductor physics that underlies the IC was discovered in the early part of the past century, and, by the early 60's, it was simplified and codified such that it could be used by engineers to design transistors of ever shrinking size and increasing performance. However, in the past 5-10 years, the ``engineering physics'' of the 60's is becoming increasingly inadequate. Empirical corrections are being made to allow for quantum and non-equilibrium Boltzmann transport effects. Moreover, as features in CMOS transistors reach atomic dimensions, continuum physics is no longer adequate, and devices must be designed increasingly, at the atomic level. In the past 30 years, transistor gate length has shrunk by a factor of 100X: from 10 um to 0.1 um. And it is expected to shrink by about another factor of 10X to 10 nm in the next 10-15 years. However, as transistors approach the end of scaling, the physics to design them will become increasingly complex: *Gate oxide, which is today a few monolayers (10A) thick will be replaced with new materials with high dielectric constant. *Metal gate electrodes will replace poly-Si, and the interface, which sets the effective work-function, needs to be understood. *Carrier scattering in the inversion layer in the presence of increasingly high electric fields (horizontal and vertical) needs to be better understood. *Tunneling will increasingly dominate transistor behavior. *The discrete positioning of dopants will increasingly affect transistor performance. *Transistors will become increasingly ballistic. *Stress in the channel is increasing to the point where it has large impact on device performance. *And new materials will be introduced into the Source/Drain and channel. Each of these issues will be discussed, and the unresolved physics issues will be identified

Buss, Dennis

2005-03-01

367

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

368

CMOS Image Sensors with Video Compression  

Microsoft Academic Search

This paper describes CMOS image sensors integrating video compression circuits. The on-sensor compression is particularly useful for the low-power design of moving picture compression hardware, which is demanded especially in the mobile computing and telephony. Recent progress of the CMOS image sensor technology allows us to realise the integration of high-performance image sensor and computational functions on a chip. An

Shoji Kawahito; Yoshiaki Tadokoro; Akira Matsuzawa

1998-01-01

369

CMOS Photodetectors Integrated With Plasmonic Color Filters  

Microsoft Academic Search

A single-pixel plasmonic complementary metal oxide semiconductor (CMOS) photo sensor consisting of a plasmonic color filter integrated on a CMOS photodiode was fabricated using electron beam lithography and dry etch. The photocurrent measurement results confirmed the three primary color filtering responses that could be achieved in a single layer of nanostructured aluminium film. Finite-difference time-domain simulation demonstrated a good agreement

Qin Chen; Danial Chitnis; Kirsty Walls; Tim D. Drysdale; Steve Collins; David R. S. Cumming

2012-01-01

370

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

371

CMOS \\/ CMOL architectures for spiking cortical column  

Microsoft Academic Search

We present a spiking cortical column model based on neural associative memory, and demonstrate architectures for emulating the cortical column model with nanogrid molecular circuitry. We investigate a number of options for cost-effective hardware with digital CMOS and mixed-signal CMOL, a hybrid CMOS\\/nanogrid technology. We also give an example of a dynamic learning algorithm that is a suitable match to

Changjian Gao; Mazad S. Zaveri; Dan W. Hammerstrom

2008-01-01

372

Design and defect tolerance beyond CMOS  

Microsoft Academic Search

ABSTRACT It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advance- ment of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement\\/replacement to CMOS must show,significant gains in at least one of the key met- rics (including speed, power and cost) for at least a

Xiaobo Sharon Hu; Alexander Khitun; Konstantin K. Likharev; Michael T. Niemier; Mingqiang Bao; Kang L Wang

2008-01-01

373

Bipolar transistor equivalents in CMOS technology  

Microsoft Academic Search

A CMOS circuit element equivalent to a bipolar junction transistor (BJT) which provides symmetrical performances of npn\\/pnp and ideality factor programming is proposed. Simulation showed that the ?, and Early voltage are superior to those of a typical BJT below about 1.65 GHz in a 0.8 ?m CMOS technology and the fabricated prototype has 2.3×10-16 A of IS, 2.4 mA

Gyudong Kim; Min-Kyu Kim; Wonchan Kim; Abdesselam Bouzerdoum

1995-01-01

374

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

NASA Astrophysics Data System (ADS)

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Davidson, Bradley Darren

375

A 0.24 ?m SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz ft HBT and 0.18 ?m Lett CMOS  

Microsoft Academic Search

A new base-after-gate integration scheme has been developed to integrate a 47 GHz ft, 65 GHz FmaxSiGe HBT process with a 0.24 ?m CMOS technology having 0.18 ?m Leff and 5 nm gate oxide. We discuss the benefits and challenges of this integration scheme which decouples the HBT from the CMOS thermal cycles. We also describe the resulting 0.24 ?m

S. A. St. Onge; D. L. Harame; J. S. Dunn; S. Subbanna; D. C. Ahlgren; G. Freeman; B. Jagannathan; J. Jeng; K. Schonenberg; K. Stein; R. Groves; D. Coolbaugh; N. Feilchenfeld; P. Geiss; M. Gordon; P. Gray; D. Hershberger; S. Kilpatrick; R. Johnson; A. Joseph; L. Lanzerotti; J. Malinowski; B. Orner; M. Zierak

1999-01-01

376

High-performance Optical Receivers Using Conventional Sub-micron CMOS Technology for Optical Communication Applications  

NASA Astrophysics Data System (ADS)

A novel sub-micron total-CMOS common-gate Transimpedance Amplifier (TIA) has been designed for high-speed optical communication applications. This total-CMOS approach has given a tremendous flexibility in optimizing the circuit for high performance. The new design shows superior performance compared to recent common-gate and common-base TIAs. Using conventional 0.8 µm CMOS process parameters, simulations showed a transimpedance gain of 69.0 dB over a 3.5 GHz bandwidth, approaching the technology fT of 10 GHz. The mean input referred noise current density was calculated to be 21.2 pA/Hz0.5 at 3.5 GHz, giving an input optical sensitivity of -20.4 dBm for a BER of 10-9. This allows a data transmission easily at 2.5 Gbps for a NRZ synchronous link. The power consumption is only 44 mW when AC coupled to a 50 ? load. In addition, the TIA was designed to tolerate a relatively wide variation in bias conditions while preserving stability. Moreover, simulations using a 0.6 µm CMOS process showed even lower noise and wider bandwidth now at 6.0 GHz. The new design approaches similar IC designs in Si-bipolar or GaAs technologies. The design is the first reported TIA, which combines such features and using conventional 0.8 µm CMOS transistors with fT = 10 GHz.

Touati, F.; Douss, S.; Elfadil, N.; Nadir, Z.; Suwailam, M. B.; Loulou, M.

377

A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking  

NASA Astrophysics Data System (ADS)

With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 ?m CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

Degerli, Y.; Guilloux, F.; Orsini, F.

2014-05-01

378

Nanoscale CMOS: potential nonclassical technologies versus a hypothetical bulk-silicon technology  

NASA Astrophysics Data System (ADS)

Using our process/physics-based compact models (UFDG and UFPDB) in Spice3, we project device characteristics and CMOS performances of nonclassical UTB (FD/SOI and DG) and classical, hypothetical bulk-Si technologies optimized at the Lg = 28 nm node. For the nonclassical MOSFETs (generally with metal gates for Vt control) with the same UTB thickness ( tSi), the DG devices are shown to be far superior for SCE control. Also, with regard to speed, the DG devices are generally superior to the FD/SG counterparts because of higher drive currents. However, for light loads and moderate supply voltages, a suboptimal FD/SG design (with the same tSi) for both LOP and HP CMOS applications is found to yield speeds comparable to the DG designs, even though its current drive is much lower and its SCEs are much more severe. This surprising result is explained by the much lower FD/SG intrinsic gate capacitance, CG( VGS). When the FD/SG CMOS design is optimized by aggressive scaling of the UTB thickness, its high- VDD speed diminishes (but is still comparable to that of DG CMOS) because of higher CG at intermediate gate voltages, while its low- VDD speed improves due to increased current. Compared to these nonclassical CMOS designs, the delay of the classical bulk-Si/SG CMOS is predicted to be much longer due mainly to its high CG in the weak/moderate inversion region and relatively low drive current. Finally, we show how FD/SOI CMOS speed is degraded as the BOX is thinned, thereby suggesting that such thinning is not a good design tradeoff.

Kim, Seung-Hwan; Fossum, Jerry G.

2005-04-01

379

Challenges in mixed-signal IC design of CNN chips in submicron CMOS  

Microsoft Academic Search

Summary form only given. The contrast observed between the performance of artificial vision machines and “natural” vision system is due to the inherent parallelism of the former. In particular, the retina combines image sensing and parallel processing to reduce the amount of data transmitted for subsequent processing by the following stages of the human vision system. Industrial applications demand CMOS

A. Rodriguez-Vazquez; R. Dominguez-Castro; S. Espejo

1998-01-01

380

High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology  

Microsoft Academic Search

The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate

Min Park; Seonghearn Lee; Hyun Kyu Yu; Jin Gun Koo; Kee Soo Nam

1997-01-01

381

Thermally and electrically isolated single crystal silicon structures in CMOS technology  

Microsoft Academic Search

Thermally and electrically isolated single crystal silicon structures have been fabricated using a post-processing anisotropic tetramethyl ammonium hydroxide (TMAH) electrochemical etch. The process was carried out on CMOS circuits fabricated by a commercial foundry. Since the etch consists of a single micromachining step performed on packaged and bonded dice, this technique has the potential for cost-effective prototyping and production of

Richard J. Reay; Erno H. Klaassen; Gregory T. A. Kovacs

1994-01-01

382

A scalable neural chip with synaptic electronics using CMOS integrated memristors.  

PubMed

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. PMID:23999447

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

383

A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application  

SciTech Connect

A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

Eaton, W.P. [New Mexico, Albuquerque, NM (United States); Smith, J.H. [Sandia National Labs., Albuquerque, NM (United States)

1994-12-31

384

A scalable neural chip with synaptic electronics using CMOS integrated memristors  

NASA Astrophysics Data System (ADS)

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

2013-09-01

385

45nm CMOS platform technology (CMOS6) with high density embedded memories  

Microsoft Academic Search

This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um2 trench capacitor DRAM and 0.247um2 6Tr.SRAM embedded memories.

M. Iwai; A. Oishi; T. Sanuki; Y. Takegawa; T. Komoda; Y. Morimasa; K. Ishimaru; M. Takayanagi; K. Eguchi; D. Matsushita; K. Muraoka; K. Sunouchi; T. Noguchi

2004-01-01

386

A SOI-RF-CMOS technology on high resistivity SIMOX substrates for microwave applications to 5 GHz  

Microsoft Academic Search

A silicon-on-insulator (SOI) RF complementary metal-oxide-semiconductor (CMOS) technology for microwave applications up to 5 GHz has been developed. The technology is based on ultra large scale integration (ULSI) CMOS processing using a high resistivity separation through implanted oxygen (SIMOX) substrate of typically 10 k?cm. Dedicated RF n-channel and RF p-channel MOSFET's with an effective channel length of 0.20 and 0.40

Dietmar Eggert; Peter Huebler; Arnd Huerrich; Heinz Kueck; Wolfram Budde; Matthias Vorwerk

1997-01-01

387

A fully integrated CMOS-MEMS pressure sensor with on-chip ?-? analog-to-digital converter  

Microsoft Academic Search

This paper describes a fully integrated CMOS-MEMS pressure sensor implemented in a standard 0.6 ?m process from AMS. The fabricated chip includes all necessary components from pressure sensor to A\\/D-converter and decimation filter. The pressure sensitive diaphragm is fabricated using one single postprocessing step. Theoretical background is provided along with simulated results laying the fundament for the implemented CMOS design.

Dag T. Wisland; K. Oysted

2004-01-01

388

A real-time JPEG encoder for 1.3 mega pixel CMOS image sensor SoC  

Microsoft Academic Search

In this paper, we propose a hardware architecture of low-power and real-time JPEG encoder for 1.3 mega pixels CMOS image sensor SoC which can be applied to mobile communication devices. The proposed architecture has an efficient interface scheme with CMOS image sensor and other peripherals for real-time encoding. The JPEG encoder supports the base-line JPEG mode, and processes motion images

Kyeong-Yuk Min; Jong-Wha Chong

2004-01-01

389

Analysis of Total Dose-Induced Dark Current in CMOS Image Sensors From Interface State and Trapped Charge Density Measurements  

Microsoft Academic Search

The origin of total ionizing dose induced dark current in CMOS image sensors is investigated by comparing dark current measurements to interface state density and trapped charge density measurements. Two types of photodiode and several thick-oxide-FETs were manufactured using a 0.18-?m CMOS image sensor process and exposed to 10-keV X-ray from 3 krad to 1 Mrad. It is shown that

V. Goiffon; C. Virmontois; P. Magnan; S. Girard; P. Paillet

2010-01-01

390

A miniaturized magnetic-field sensor system consisting of a planar fluxgate sensor and a CMOS readout circuitry  

Microsoft Academic Search

We report on a miniaturized magnetic-field sensor system consisting of a fluxgate sensor fabricated in CMOS-compatible planar technology and a CMOS-ASIC for sensor supply, readout and signal processing using the second-harmonic principle with a feedback loop for zero-field operation. The system exhibits a sensitivity of 9.2±0.1 mV ?T?1 for a magnetic field range of ±90 ?T and a temperature range

R Gottfried-Gottfried; W Budde; R Jähne; H Kück; B Sauer; S Ulbricht; U Wende

1996-01-01

391

3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS\\/Nanomaterial Hybrid Digital Circuits  

Microsoft Academic Search

In this paper, we introduce a novel reconfigurable architecture, named 3D field-programmable gate array (3D nFPGA), which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS nanohybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and

Chen Dong; Deming Chen; Sansiri Haruehanroengra; Wei Wang

2007-01-01

392

A 12mW wide dynamic range CMOS front-end for a portable GPS receiver  

Microsoft Academic Search

This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-?m (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer

Arvin R. Shahani; Derek K. Shaeffer; Thomas H. Lee

1997-01-01

393

CMOS compatible integration of three-dimensional microfluidic systems based on low-temperature transfer of SU8 films  

Microsoft Academic Search

A novel approach to integrate densely packed CMOS devices with three-dimensional (3-D) microfluidic systems created at the wafer level using low temperature processes is introduced. The approach is based on low temperature (<50°C) bonding and releasing of non-UV-exposed SU-8 films onto a SU-8 structured Si wafer bearing CMOS devices and multilayered lithography in the non-UV-exposed SU-8 films to form 3-D

Zheng-chun Peng; Zhong-geng Ling; Mark Tondra; Chang-geng Liu; Min Zhang; Kun Lian; Jost Goettert; Josef Hormes

2006-01-01

394

Fully integrated 5GHz CMOS VCOs with on chip low frequency feedback circuit for 1\\/f induced phase noise suppression  

Microsoft Academic Search

Fully integrated RF CMOS VCOs with on chip low frequency feedback circuit for 1\\/f induced phase noise suppression are presented. Both Colpitts and differential type VCO circuits are implemented at 5- 6GHz in 0.18 µm CMOS process. The measured Colpitts VCO is working at 5.4-5.75GHz with 1.8V power supply. The core VCO consumes 15mW DC power. The phase noise is

Yi Lin; K. H. To; J. S. Hamel; W. M. Huang

2002-01-01

395

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

396

Impact of CMOS device scaling in ASICs on radiation immunity  

Microsoft Academic Search

Roadmaps for CMOS device technology has shown fast pace scaling in recent years. Mainstream CMOS devices have been produced with feature sizes between 0.1 and 0.25 ?m since the year 2000 and the so called \\

H. Ragaie; S. Kayed

2002-01-01

397

Full field laser Doppler flowmetry with custom made CMOS sensors  

NASA Astrophysics Data System (ADS)

Recently, full field laser Doppler perfusion imaging has been implemented using a commercial CMOS image sensor coupled with a digital signal processor. The advantage over scanning laser Doppler imaging is that movement artifacts are reduced and the scanning speed of the system is increased due to the absence of moving scanning components. A custom made CMOS sensor offers several advantages over commercial cameras as the specifications can be tailored to the signals of interest. An important advantage of custom made sensors is that on-chip processing allows the data bottleneck that exists between the photodetector array and processing electronics to be overcome, as the processed data can be read out from the image sensor to a PC or display at a low data rate. We demonstrate advancements made by our group in this area. In this paper a system is described which combines a 32x32 pixel array with on-chip processing linked to a field programmable gate array. Results are demonstrated using a rotating diffuser, a vibrating test target and blood flow in tissue. Methods for efficiently using silicon when implementing the signal processing on-chip are discussed.

He, Diwei; Hoang, Nguyen; Hayes-Gill, Barrie R.; Crowe, John A.; Zhu, Yiqun; Morgan, Stephen P.

2009-02-01

398

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips  

NASA Astrophysics Data System (ADS)

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

399

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate  

PubMed Central

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 ?m UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is ?42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 ?A, and low distortion of less than 1% (referred to 100 dB).

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

400

CMOS compatible silicon-based Mach-Zehnder optical modulators with improved extinction ratio  

NASA Astrophysics Data System (ADS)

Improved Extinction Ratio of 25 dB was demonstrated in silicon based optical modulators on CMOS platform in China. The measurement results agree with the simulation, followed by a discussion about the effects of both propagation loss in Mach-Zehnder arms and power ratio at beam splitters and combiners. The analyses indicate that many considerations have to be taken into design and development of the compatible fabrication of these integrated silicon photonics, especially for the improved extinction ratio of optical modulators. In this summary, we propose the integrated optical modulators in SOI by use of the compatible CMOS processes under the modern CMOS foundry in Chinese homeland. And the measured results were shown, the fast response modulator with the data transmission rate of 10 Gbps.

Li, Zhiyong; Zhou, Liang; Hu, Yingtao; Xiao, Xi; Yu, Yude; Yu, Jinzhong

2011-11-01

401

RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications  

NASA Astrophysics Data System (ADS)

New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS ‘Receiver-on-a-Chip’ is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 ?m RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

Jackson, Suzy A.

2004-06-01

402

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

403

Measurements with a CMOS pixel sensor in magnetic fields  

NASA Astrophysics Data System (ADS)

CMOS technique, which is the standard process used by most of the semiconductor factories worldwide, allows the production of both cheap and highly integrated sensors. The prototypes MIMOSA -I and MIMOSA-II were designed by the IReS-LEPSI collaboration in order to investigate the potential of this new technique for charged particle tracking (Design and Testing of Monolithic Active Pixel Sensors for Charged Particle Tracking, LEPSI, IN2P3, Strasbourg, France). For this purpose it is necessary to study the effects of magnetic fields as they appear in high-energy physics on these sensors. MIMOSA: Minimum Ionizing particle MOS Active pixel sensor.

de Boer, W.; Bartsch, V.; Bol, J.; Dierlamm, A.; Grigoriev, E.; Hauler, F.; Herz, O.; Jungermann, L.; Koppenhöfer, M.; Sopczak, A.; Schneider, Th.

2002-07-01

404

A high speed CMOS A/D converter  

NASA Technical Reports Server (NTRS)

This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

Wiseman, Don R.; Whitaker, Sterling R.

1992-01-01

405

Silicon nanowires integrated with CMOS circuits for biosensing application  

NASA Astrophysics Data System (ADS)

We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

Jayakumar, G.; Asadollahi, A.; Hellström, P.-E.; Garidis, K.; Östling, M.

2014-08-01

406

A spatiotemporal CMOS imager for nanosecond low power pulse detections  

Microsoft Academic Search

Nowadays, imagers based on CMOS active pixel sensors (APS) have performances that are competitive with those based on charge-coupled devices (CCD). CMOS imagers offer advantages in on-chip functionalities, system power reduction, cost and miniaturization. The aim of the FAst MOS Imager (FAMOSI) project is to reproduce streak camera functionality with a CMOS imager. We present FAMOSI 2, which has a

F. Morel; J.-P. Le Normand; C.-V. Zint; W. Uhring; Y. Hu

2004-01-01

407

High-temperature Complementary Metal Oxide Semiconductors (CMOS)  

NASA Technical Reports Server (NTRS)

The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

Mcbrayer, J. D.

1981-01-01

408

Low power, CMOS digital autocorrelator spectrometer for spaceborne applications  

NASA Technical Reports Server (NTRS)

A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

Chandra, Kumar; Wilson, William J.

1992-01-01

409

Cascode voltage switch logic: A differential CMOS logic family  

Microsoft Academic Search

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

L. Heller; W. Griffin; J. Davis; N. Thoma

1984-01-01

410

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker  

NASA Astrophysics Data System (ADS)

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

2013-08-01

411

Adiabatic circuits: converter for static CMOS signals  

NASA Astrophysics Data System (ADS)

Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage. By means of adder structures designed for a 0.13µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

Fischer, J.; Amirante, E.; Bargagli-Stoffi, A.; Schmitt-Landsiedel, D.

2003-05-01

412

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique  

PubMed Central

In this study we used the commercial 0.35 ?m CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

413

Performance comparison of CMOS-based photodiodes for high-resolution and high-sensitivity digital mammography  

NASA Astrophysics Data System (ADS)

In order to develop a high-resolution and high-sensitivity digital mamographic detector, to use a commercially-available and well-developed CMOS image sensor (CIS) process can be a cost-effective way. However, in any commercial CIS process, several different types of n- or p-layers can be used so that various pn-junction structures could be formed depending on the choice of n- and p-layer combination. We performed a comparative analysis on the characteristics of three types of photodiodes formed on a high-resistivity p-type epitaxial wafer by applying three available n-layer processes in order to develop the high-sensitivity photodiode for a scintillator-based X-ray imaging detector. As a preliminar study, a small test-version CIS chip with an 80 × 80 pixel array of a 3-transistor active pixel sensor structure, 50 ?m pitch and 80{%} fill factor was fabricated. The pixel area is subdivided into four 40 × 40 sub-arrays and 3 different types of photodides are designed for each sub-array by using n+, n- and n-well layers. All other components are designed to be identical for impartial comparison of the photodiodes only. Among 3 types, the n-/p-epi photodiode exhibited high charge-to-voltage gain (0.86 ?V/e-), high quantum efficiency (49% at 532 nm wavelength) and low dark current (294 pA/cm2). The test CIS chip was coupled to a phosphor screen, Lanex Fine or Lanex Regular, both composed of Gd2O2S:Tb, and was tested using X-rays in a mammography setting. Among 6 cases, n-/p-epi photodiode coupled with the Lanex Regular also showed the highest sensitivity of 30.5 mV/mR.

Bae, J. H.; Cho, M.; Kim, M. S.; Lee, D. H.; Cho, G.

2011-12-01

414

Focal-plane-arrays and CMOS readout techniques of infrared imaging systems  

Microsoft Academic Search

A discussion of CMOS readout technologies for infrared (IR) imaging systems is presented. First, the description of various types of IR detector materials and structures is given. The advances of detector fabrication technology and microelectronics process technology have led to the development of large format array of IR imaging detectors. For such large IR FPAs which is the critical component

Chih-Cheng Hsieh; Chung-Yu Wu; Far-Wen Jih; Tai-Ping Sun

1997-01-01

415

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS  

Microsoft Academic Search

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM) and how it controls calibration and compensation for

Roman Staszewski; Robert Bogdan Staszewski; Tom Jung; Thomas Murphy; Imran Bashir; Oren Eliezer; Khurram Muhammad; Mitch Entezari

2010-01-01

416

A fast low noise CMOS charge sensitive preamplifier for column parallel CCD readout  

Microsoft Academic Search

A fast, low noise charge sensitive preamplifier for column parallel CCD readout application is presented. This prototype has been implemented on a commercial CMOS 65nm process. This preamplifier consists of a two stage transconductance amplifier with capacitive feedback to accommodate two gain ranges and a second transconductance amplifier to reset the circuit. An equivalent noise charge of 37 electrons for

J. P. Walder; Peter Denes; Carl Grace; Henrik von der Lippe; Bob Zheng

2011-01-01

417

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration  

Microsoft Academic Search

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this

Xavier Gagnard; Thierry Mourier

2010-01-01

418

Test structures for characterization and comparative analysis of CMOS image sensors  

Microsoft Academic Search

A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized

David X. d. Yang; Hao Min; Boyd A. Fowler; Abbas El Gamal; Mark Beiley; Kit Cham

1996-01-01

419

An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems  

Microsoft Academic Search

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process.

J. Christiansen

1995-01-01

420

Multi level RTS in proton irradiated CMOS image sensors manufactured in deep submicron technology  

Microsoft Academic Search

A new automated method able to detect multi level random telegraph signals in pixel arrays and to extract their main characteristics is presented. The proposed method is applied to several proton irradiated pixel arrays manufactured using a 0.18 ?m CMOS process dedicated to imaging. Despite the large proton energy range and the large fluence range used, similar exponential RTS amplitude

V. Goiffon; G. R. Hopkinson; P. Magnan; F. Bernard; G. Roland; O. Saint-Pe

2008-01-01

421

Multilevel RTS in Proton Irradiated CMOS Image Sensors Manufactured in a Deep Submicron Technology  

Microsoft Academic Search

A new automated method able to detect multilevel random telegraph signals (RTS) in pixel arrays and to extract their main characteristics is presented. The proposed method is applied to several proton irradiated pixel arrays manufactured using a 0.18 mum CMOS process dedicated to imaging. Despite the large proton energy range and the large fluence range used, similar exponential RTS amplitude

V. Goiffon; G. R. Hopkinson; P. Magnan; F. Bernard; G. Rolland; O. Saint-Pe

2009-01-01

422

A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits  

Microsoft Academic Search

This paper describes and discusses an intrinsic approach to hardware evolution of analog electronic circuits using a Field Programmable Transistor Array (FPTA). The FPTA is fabricated in a 0:6 m CMOS process and consists of 16 16 transistor cells. The chip allows to configure the gate geometry as well as the connectivity of each of the 256 transistors. Evolutionary algorithms

Jörg Langeheine; Joachim Becker; Simon Fölling; Karlheinz Meier; Johannes Schemmel

2001-01-01

423

0.1 ?m CMOS devices using low-impurity-channel transistors (LICT)  

Microsoft Academic Search

Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 ?m CMOS devices. Attention is given to device fabrication criteria, key process technologies used, and the features achieved using LICTs

M. Aoki; T. Ishii; T. Yoshimura; Y. Kiyota; S. Iijima; T. Yamanaka; T. Kure; K. Ohyu; T. Nishida; S. Okazaki; K. Seki; K. Shimohigashi

1990-01-01

424

A 57-to-66GHz quadrature PLL in 45nm digital CMOS  

Microsoft Academic Search

A completely integrated PLL is realized in 45 nm digital CMOS, using two techniques to enable the coverage of the 57-to-66 GHz band. First, the targeted band of 9 GHz (plus margin for process variations) is divided in two parts, each part being covered by a separate oscillator. This relaxes the tunability requirements for each oscillator. To enable direct conversion,

K. Scheir; G. Vandersteen; Y. Rolain; P. Wambacq

2009-01-01

425

Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design  

Microsoft Academic Search

The increasing number of interconnect layers that are needed in a CMOS process to meet the routing and power re- quirements of large digital circuits also yield significant advantages for analog applications. The reverse thickness scaling of the top metal layer can be exploited in the design of low-loss transmission lines. Coplanar transmission lines in the top metal layers take

Bendik Kleveland; Carlos H. Diaz; Dieter Vook; Liam Madden; Thomas H. Lee; S. Simon Wong

2001-01-01

426

Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS  

Microsoft Academic Search

Logic testing has some well known limitations for circuits with failures causing intermediate voltage levels or, even, correct logic outputs with parametric deuiations from the fault free specificattons. For these failures current testing might be considered as a complementary technique to logic testing. In this work, these physical defects widely encountered in ioday’s CMOS processes, are modelled taking into account

Rosa Rodríguez-montañés; J. A. Segura; Víctor H. Champac; Joan Figueras; J. A. Rubio

1991-01-01

427

Thermally excited silicon oxide beam and bridge resonators in CMOS technology  

Microsoft Academic Search

The design, fabrication, and characterization of thermally excited silicon oxide beam and bridge resonators by a modern industrial CMOS process combined with one additional maskless etching step is reported. The resonant frequencies, vibration amplitudes, and mode shapes of the devices are measured using a laser heterodyne interferometer. The acoustic transmitting and receiving sensitivities of the resonant structures in air are

Oliver Brand; Henry Baltes; Urs Baldenweg

1993-01-01

428

A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler  

Microsoft Academic Search

This paper presents the design and realization of a downconversion mixer fabricated in a standard 130 nm commercial CMOS process and aimed at applications in the 60 GHz ISM band. A balanced mixer configuration was implemented using a layout efficient 90deg hybrid coupler which serves as a diplexer to inject the LO signal while also providing two outputs with 3

R. E. Amaya; Cornelius J. Verver

2009-01-01

429

Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS  

Microsoft Academic Search

We report on the design and characterization of an ultralow-power converter, designed for use in baseband digitization in wireless sensor network radio receivers. The converter uses a successive approximation architecture and operates robustly with a supply voltage as low as 450 mV, overcoming charge leakage limitations. Implemented in a 90 nm CMOS process, this design achieves a figure of merit

Simone Gambini; Jan Rabaey

2007-01-01

430

Low voltage CMOS bandgap references with temperature compensated reference current output  

Microsoft Academic Search

Techniques for designing low voltage bandgap references providing both reference voltage and current outputs are proposed. By modifying the bandgap load or the bandgap core, the temperature dependences of the voltage output and the current output can be compensated separately. Based on the proposed techniques, a IV bandgap reference was designed in a conventional 0.18um CMOS process. Opamp was not

Edward K. F. Lee

2010-01-01

431

CMOS fully compatible microwave detector based on MOSFET operating in resistive regime  

Microsoft Academic Search

A microwave detector featuring full compatibility with standard CMOS process is presented. It is based on the channel resistance nonlinearity of a MOSFET operating in ohmic regime. The detecting sensitivity is shown to be tuned to below mW power by properly setting the bias voltage of the gate and of the drain of the transistor. Experiments with 180-nm gate length

Giorgio Ferrari; Laura Fumagalli; Marco Sampietro; Enrico Prati; Marco Fanciulli

2005-01-01

432

Low Voltage Low Power CMOS Image Sensor with A New Rail-to-Rail Readout Circuit  

Microsoft Academic Search

In this paper a new rail-to-rail pixel readout architecture is proposed to enhance the performance of CMOS image sensor for both low voltage and low power applications. Due to this new readout circuit, the enough input voltage swing under a low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under

HWANG-CHERNG CHOW; JEN-BOR HSIAO

2006-01-01

433

A new rail-to-rail readout circuit of CMOS image sensor for low power applications  

Microsoft Academic Search

In order to enhance the performance of CMOS image sensor under lower supply voltage, a new rail-to-rail pixel readout architecture is proposed in this paper. Due to the new readout circuit, the enough input voltage swing under low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under lower voltage using

Hwang-Cherng Chow; J.-B. Hsiao

2005-01-01

434

Surface micromachined, digitally force-balanced accelerometer with integrated CMOS detection circuitry  

Microsoft Academic Search

The authors have described a surface micromachined accelerometer with digital electrostatic feedback using ?-? modulation technique, fabricated in a modular CMOS\\/microstructure process. Detection circuits have been tested successfully. The unity gain buffer with low input capacitance can also be used for other capacitive detection applications. The accelerometer has been characterized in the self-testing mode and has demonstrated the functionality of

Weijie Yun; Roger T. Howe; Paul R. Gray

1992-01-01

435

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors  

PubMed Central

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT.

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

436

Fabrication and characterization of CMOS-MEMS magnetic microsensors.  

PubMed

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5-200 mT. PMID:24172287

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

437

Analysis and optimization of safe-operating-area of LUDMOS transistors based on 0.18 µm SOI CMOS technology  

NASA Astrophysics Data System (ADS)

This paper is focused on the design and optimization of power LDMOS transistors (VBR > 120 V) with the purpose of integrating them with a new generation of smart-power technology based upon 0.18 µm SOI-CMOS technology. Different LDMOS design structures with optimal R_{on{\\raise-1pt\\-sp}} /VBR trade-off have been analyzed in order to compare their electrical safe-operating-area (SOA). The influence of some important design parameters such as the STI length (LSTI) and technological concerns such as the P-well and N-well mask position distance is also exhaustively analyzed in this work.

Cortés, I.; Toulon, G.; Morancho, F.; Urresti, J.; Perpiñà, X.; Villard, B.

2010-04-01

438

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

439

Non-overlapping super self-aligned BiCMOS with 87 ps low power ECL  

Microsoft Academic Search

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi\\/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is

T.-Y. Chiu; G. M. Chin; M. Y. Lau; R. C. Hanson; M. D. Morris; K. F. Lee; A. M. Voshchenkov; R. G. Swatrz; V. D. Archer; M. T. Y. Liu; S. N. Finegan; M. D. Feuer

1988-01-01

440

Scaling studies of CMOS SRAM soft-error tolerances—From 16K to 256K  

Microsoft Academic Search

The processing and design geometric scaling effects on the soft-error tolerance levels of the 16K 2-µm technology and the 256K 1-µm technology CMOS SRAMs are separated by fabricating the 16K 2-µm design with the 1-µm process. Although the 1-µm twin-tub process is inherently more tolerant than the p-well process to soft errors, the densely packed 1-µm memory cells become very

J. S. Fu; K. H. Lee; R. Koga; F. W. Hewlett; R. Flores; R. E. Anderson; J. C. Desko; W. J. Nagy; J. A. Shimer; R. A. Kohler; S. D. Steenwyk

1987-01-01

441

Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS  

NASA Astrophysics Data System (ADS)

The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length ˜1000 mum and width ˜150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only ˜1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height up to a hundred times higher than its thickness. This natural deflection results from the relaxation of internal stresses inside the thin films which are part of the microactuator. These internal stresses are intrinsics to the host CMOS process. We have developed a model of the microactuator's initial deflection using mechanical properties of thin films and dimensions of the structure. Actuation experiments were performed in order to characterize the deflection of the microactuator with respect to the heating of the bilayers (separately and together). We have developed a thermal actuation analytical model for an n-layers multimorph structure, which takes into account the initial deflection resulting from the relaxation of stresses as well as the deflection due to the temperature increase during the electrothermal activation of the bilayers. (Abstract shortened by UMI.)

Ressejac, Isabelle

442

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch  

NASA Astrophysics Data System (ADS)

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 ?m pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 ?m pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

443

Design and fabrication of a CMOS-compatible MHP gas sensor  

NASA Astrophysics Data System (ADS)

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ˜19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

Li, Ying; Yu, Jun; Wu, Hao; Tang, Zhenan

2014-03-01

444

Two and multi-terminal CMOS\\/BiCMOS Si LED's  

Microsoft Academic Search

Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented.

Monuko Du Plessis; Herzl Aharoni; Lukas W. Snyman

2005-01-01

445

Two and multi-terminal CMOS\\/BiCMOS Si LED’s  

Microsoft Academic Search

Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented.

Monuko du Plessis; Herzl Aharoni; Lukas W. Snyman

2005-01-01

446

Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process  

Microsoft Academic Search

The authors report silicon avalanche photodetectors (APDs) fabricated with 0.18 mum standard complementary metal-oxide-semiconductor (CMOS) process without any process modification or a special substrate. When the bias is above the avalanche breakdown voltage, CMOS-compatible APD (CMOS-APD) exhibits negative photoconductance in photocurrent-voltage relationship and rf peaking in the photodetection frequency response. The reflection coefficient measurement of CMOS-APD indicates that rf peaking

Hyo-Soon Kang; Myung-Jae Lee; Woo-Young Choi

2007-01-01

447

Scanning probe lithography approach for beyond CMOS devices  

NASA Astrophysics Data System (ADS)

As present CMOS devices approach technological and physical limits at the sub-10 nm scale, a `beyond CMOS' information-processing technology is necessary for timescales beyond the semiconductor technology roadmap. This requires new approaches to logic and memory devices, and to associated lithographic processes. At the sub-5 nm scale, a technology platform based on a combination of high-resolution scanning probe lithography (SPL) and nano-imprint lithography (NIL) is regarded as a promising candidate for both resolution and high throughput production. The practical application of quantum-effect devices, such as room temperature single-electron and quantum-dot devices, then becomes feasible. This paper considers lithographic and device approaches to such a `single nanometer manufacturing' technology. We consider the application of scanning probes, capable of imaging, probing of material properties and lithography at the single nanometer scale. Modified scanning probes are used to pattern molecular glass based resist materials, where the small particle size (<1 nm) and mono-disperse nature leads to more uniform and smaller lithographic pixel size. We also review the current status of single-electron and quantum dot devices capable of room-temperature operation, and discuss the requirements for these devices with regards to practical application.

Durrani, Zahid; Jones, Mervyn; Kaestner, Marcus; Hofer, Manuel; Guliyev, Elshad; Ahmad, Ahmad; Ivanov, Tzvetan; Zoellner, Jens-Peter; Rangelow, Ivo W.

2013-03-01

448

A CMOS active pixel sensor for retinal stimulation  

NASA Astrophysics Data System (ADS)

Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

2006-02-01

449

Effective Crosstalk Isolation With Post-CMOS Selectively Grown Porous Silicon Technique for Radio Frequency System-on-Chip (SOC) Applications  

Microsoft Academic Search

In this letter, post-CMOS substrate selective-transformation engineering based on the selectively grown porous silicon (SGPS) technique is demonstrated to effectively suppress substrate crosstalk. The testing structures for crosstalk isolation are fabricated in a standard 0.18-mum CMOS process, and porous silicon trenches are selectively grown after processing from the backside of the silicon wafer. For a testing structure with 250-mum separation

Chen Li; Huailin Liao; Chuan Wang; Ru Huang; Yangyuan Wang

2008-01-01

450

Low energy CMOS for space applications  

NASA Technical Reports Server (NTRS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

451

A modeling technique for CMOS gates  

Microsoft Academic Search

In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing simulators in order to improve their accuracy. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each

Alexander Chatzigeorgiou; Spiridon Nikolaidis; Ioannis Tsoukalas

1999-01-01

452

Tunable oscillating CMOS pixel for subretinal implants  

Microsoft Academic Search

Partial visual capabilities for some kind of blindness are still possible through direct electrical stimulation of retinal tissue. In this work, tunable implantable silicon CMOS pixel are presented and experimentally validated. Pulse width, stimulating output current and light sensibility may be regulated by external voltages, making this solution suitable for an auto-adapting artificial retina. Power consumption due to light detection

M. Mazza; P. Renaud; A. M. Ionescu; D. Bertrand

2005-01-01

453

Analysis of noise in CMOS image sensor  

Microsoft Academic Search

CMOS image sensors based on active pixel sensors (APS) are now the preferred technology for most imaging applications. With advanced technology, reduced channel size, novel designs extending the more established pixels based on three transistors (3T design) into four transistors (4T design employing pinned photodiodes), the performance keeps improving [1-2]. Noise sets a limit on image sensor performance, mainly under

I. Brouk; A. Nemirovsky; Y. Nemirovsky

2008-01-01

454

CMOS Equivalent Model of Ferroelectric RAM  

Microsoft Academic Search

The current research work in the paper is the representation of FRAM (Ferroelectric Random Access Memory) as an equivalent Model of Ferroelectric memory cell in Spice Tool. This Equivalent CMOS based model is designed to work at par with the behaviour working of the FRAM. The crux of the design of ferroelectric capacitor in the Ferroelectric Random Access Memory lies

Parvinder S. Sandhu; Iqbaldeep Kaur; Amit Verma; Birinderjit S. Kalyan; Jagdeep Kaur; Sanyam Anand

2010-01-01

455

A fully integrated CMOS nanoscale biosensor microarray  

Microsoft Academic Search

This paper presents a fully integrated CMOS mi- croarray for biosensor applications. A 64-pixel working electrode array with optimized reference and counter electrode structure is proposed to improve symmetry, and the feature sizes of electrodes have been scaled down to 600nm. The circuit utilizes the decoding scheme of memories to simplify the pixel design while shares potentiostat opamp and current

Lei Zhang; Xiangqing He; Yan Wang; Zhiping Yu

2011-01-01

456

Silicon on sapphire CMOS for optoelectronic microsystems  

Microsoft Academic Search

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that

A. G. Andreou; Z. K. Kalayjian; A. Apsel; P. O. Pouliquen; R. A. Athale; G. Simonis; R. Reedy

2001-01-01

457

Minimizing power consumption in digital CMOS circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

1995-01-01

458

Low noise monolithic CMOS front end electronics  

Microsoft Academic Search

Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in

G. Lutz; W. Buttler; H. Bergmann; P. Holl; B. J. Hosticka; P. F. Manfredi; G. Zimmer

1988-01-01

459

High-Performance CMOS Gate Array.  

National Technical Information Service (NTIS)

Mitsubishi Electric's unique gate-isolation configuration, which permits hybrid integration, was employed to develop a CMOS gate array having two gate modes: a 3 micrometer mode (3ns/gate) with 2,600, 1,600, and 1,100 gates; and a 2 micrometer mode (1.5ns...

M. Ueda T. Arakawa Y. Kuramitsu K. Okazaki K. Sugisaki

1984-01-01

460

CMOS-MEMS Downconversion Mixer-Filters.  

National Technical Information Service (NTIS)

The potential use of CMOS-MEMS downconversion mixer-filters in future reconfigurable integrated radios is demonstrated. Analytical and simulation models have been developed to enable mixer-filter design. An array of cantilever mixer-filters is designed an...

U. Arslan

2005-01-01

461

A comparative study of CMOS LNAs  

Microsoft Academic Search

Three CMOS RF low noise amplifier circuits have been designed and simulated. These LNAs are intended for use in 402-405 MHz medical implant communication service transceivers. The inductively degenerated common source LNA (CS-LNA) topology is currently popular because it achieves high gain, low noise figure, and high linearity. In this paper cascode LNA with inductive source degeneration, LC folded cascode

Sherif A. Saleh; Maurits Ortmanns; Yiannos Manoli

2007-01-01

462

Power-delay characteristics of CMOS adders  

Microsoft Academic Search

An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are

Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin

1994-01-01

463

Current-Mode CMOS Galois Field Circuits  

Microsoft Academic Search

Use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions has been consid- ered in a number of recent papers. In this paper, we present an application of these circuits in realization of Galois field operations. We also give a new algorithm for determination of polynomial representations for arbitrary functions over a class of Galois fields implementable with

Zeljko Zilic; Zvonko G. Vranesic

1993-01-01

464

Low temperature CMOS-a brief review  

Microsoft Academic Search

Bulk silicon CMOS applications at cryogenic temperatures are considered. It is argued that device improvements obtained from exploiting the dependence of physical characteristics of silicon at low temperature are above and beyond those improvements obtained from the usual geometric scaling of device dimensions. As device geometries continue to shrink into the deep submicrometer regime, second-order effects begin to limit further

William F. Clark; Badih El-Kareh; Renato G. Pires; Stephen L. Titcomb; Richard L. Anderson

1992-01-01

465

Minimizing Power Consumption in CMOS Circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technol- ogy used to implement the digital circuits, the circuit style and topology, the architecture for implement- ing the circuits and at the highest level the algorithms that are being implemented. The most

Anantha P. Chandrakasan; Robert W. Brodersen

466

Low power SEU immune CMOS memory circuits  

NASA Technical Reports Server (NTRS)

The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

Liu, M. N.; Whitaker, Sterling

1992-01-01

467

65-nm CMOS Monolithically Integrated Subterahertz Transmitter  

Microsoft Academic Search

This letter presents a transmitter for subterahertz ra- diation (up to 160 GHz), which consists of a nonlinear transmission line (NLTL) and an extremely wideband (EWB) slot antenna on a silicon substrate of low resistivity (10 ? · cm). The fabrication was realized using a commercially available 65-nm CMOS pro- cess. On-wafer characterization of the whole transmitter, of the stand-alone

Xin Hu; Lorenzo Tripodi; Marion K. Matters-Kammerer; Shi Cheng; Anders Rydberg

2011-01-01

468

SOC CMOS technology for personal Internet products  

Microsoft Academic Search

Worldwide demand for Personal Internet Products is increasing rapidly, and will shape the directions of CMOS technology in the years ahead. Personal Internet Products are loosely defined in this paper as communication, computing and consumer products, which are enabled by the Internet: cell phones, PDAs, WLANs, Internet audio\\/video, ADSL, cable modems etc. Personal Internet Products are based on Digital Signal

Dennis Buss; Brian L. Evans; Jeff Bellay; William Krenik; Baher Haroun; Dirk Leipold; Ken Maggio; Jau-Yuann Yang; Ted Moise

2003-01-01

469

Research directions in beyond CMOS computing  

NASA Astrophysics Data System (ADS)

The International Technology Roadmap for Semiconductors has identified five promising research directions in beyond CMOS computing technology that are discussed here. Alternate state variables beyond electronic charge are introduced. Momentum and spin relaxation times for electrons in GaAs are calculated and show that magnetic systems are less strongly coupled to the thermal environment than systems based on electronic charge.

Bourianoff, George I.; Gargini, Paolo A.; Nikonov, Dmitri E.

2007-11-01

470

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.  

PubMed

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

471

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking  

PubMed Central

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-01-01

472

A concurrent 0.18-?m CMOS self-biased dual-band driver amplifier for IEEE 802.11 a\\/b\\/g  

Microsoft Academic Search

A 2.4 GHz\\/5.2 GHz self-biased dual band CMOS driver amplifier with a 9.8-dBm output power using TSMC 0.18-?m 1P6M standard CMOS process is described. The CMOS amplifier designed on Rogers RO4003 printed-circuit-board (PCB) with a single input and a single output signal chain is simultaneously optimized for wireless local area network (WLAN) 2.4 GHz\\/5.2 GHz applications. Simulation results show that

C. F. Jou; Kllo-Hua Cheng; Jia-Liang Chen

2004-01-01

473

Failure analysis of a half-micron CMOS IC technology  

SciTech Connect

We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S. [and others

1996-08-01

474

Design and Fabrication of High-Efficiency CMOS/CCD Imagers  

NASA Technical Reports Server (NTRS)

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata

2007-01-01

475

CMOS low data rate imaging method based on compressed sensing  

NASA Astrophysics Data System (ADS)

Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

Xiao, Long-long; Liu, Kun; Han, Da-peng

2012-07-01

476

A CMOS integrated circuit for pulse-shaped discrimination  

SciTech Connect

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the zero crossing of the shaped signal. The circuit is designed to interface with two photomultiplier tubes -- one for pulse processing and one for coincidence detection. Two Outputs from the IC, a start and stop, can be used with a high speed timing system for pulse characterization with minimal external control. The circuit was fabricated in Orbit 1.2{mu}m CMOS and operates from a 5-V supply. Specifics of the design including overall topology, charge sensitive preamplifier and CFD characteristics, shaping method and time constant selections, system timing, and implementation are discussed. Circuit performance is presented including dynamic range, timing walk, system dead time, and power consumption.

Frank, S.S.; Ericson, M.N.; Simpson, M.L.; Todd, R.A.; Hutchinson, D.P.

1995-06-01

477

120×90 element thermopile array fabricated with CMOS technology  

NASA Astrophysics Data System (ADS)

This paper presents the first-ever 120×90 element thermoelectric IR focal plane array (FPA) fabricated wiht CMOS technology. The device has a high repsonsivity of 3,900 V/W and a low cost potential. The overall chip size is 14.4 mm × 11.0 mm with a 12.0 mm × 9.0 mm imaging area. The device structure was optimzed for a vacuum-sealed package. Each detector consists of two pairs of p-n polysilicon thermocouples and an NMOS transistor and has external dimensions of 100?m x 100?m and an internal electrical resistance of 90k?. The precisely patterned Au-black IR absorbing layer was achieved by both a low-pressure vapor deposition technique and a lift-off technique utilizing a PSG sacrificial layer. These techniques make it possible to obtain a Au-black pattern with the same degree of accuracy as with the CMOS process. The Au-black layer showed high absorpitivty of more than 90 percent to the light source with a wavelength of from 8 to 13?m. This performance is suitable for consumer electronics as well as automotive applications.

Hirota, Masaki; Nakajima, Yasushi; Saito, Masanori; Satou, Fuminori; Uchiyama, Makato

2003-01-01

478

Design and optimization of high voltage LDMOS transistors on 0.18 ?m SOI CMOS technology  

NASA Astrophysics Data System (ADS)

This paper analyses the voltage capability of lateral power ( VBR > 120 V) P- and N-channel MOS transistors manufactured on a 0.18 ?m SOI CMOS technology by means of TCAD numerical simulations. The measured breakdown voltage results as a function of the handle wafer voltage of power LDMOS transistors are compared with TCAD numerical simulation with the purpose of understanding the problems arising in the measured structures. Some important design parameters such as the STI length ( LSTI) and technological concerns like the P-well and N-well doping profiles have a strong influence on the voltage capability. As a consequence, some design solutions are proposed in this work to improve the performances of the fabricated LDMOS structures.

Toulon, G.; Cortés, I.; Morancho, F.; Hugonnard-Bruyère, E.; Villard, B.; Toren, W. J.

2011-07-01

479

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays  

PubMed Central

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 ?m two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/?Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz.

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

480

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors  

NASA Astrophysics Data System (ADS)

This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 ?m CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

2013-08-01

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