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Sample records for n-well cmos process

  1. P-well or N-well CMOS technology for advanced SEU-hard SRAMs

    SciTech Connect

    Fu, J.S.

    1988-01-01

    The decoupling resistances required for SEU hardening CMOS SRAMs of the 2..mu..m p-well and n-well technologies are compared. An advanced device-plus-circuit simulator has been used to illuminate the underpinings of why one technology is intrinsically more SEU tolerant than the other. 3 refs., 5 figs.

  2. Carbon Nanotube Integration with a CMOS Process

    PubMed Central

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  3. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  4. The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process.

    SciTech Connect

    Ball, D. R.; Ahlbin, Jonathan R.; Gadlage, Matthew J.; Massengill, Lloyd W.; Witulski, A. W.; Reed, R. A.; Vizkelethy, Gyorgy; Bhuva, Bharat L.

    2010-07-01

    Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

  5. A Standard CMOS Humidity Sensor without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 μW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023–10 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

  6. Fabrication of the planar angular rotator using the CMOS process

    NASA Astrophysics Data System (ADS)

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  7. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  8. A CCD/CMOS process for integrated image acquisition and early vision signal processing

    NASA Astrophysics Data System (ADS)

    Keast, Craig L.; Sodini, Charles G.

    The development of technology which integrates a four phase, buried-channel CCD in an existing 1.75 micron CMOS process is described. The four phase clock is employed in the integrated early vision system to minimize process complexity. Signal corruption is minimized and lateral fringing fields are enhanced by burying the channel. The CMOS process for CCD enhancement is described, which highlights a new double-poly process and the buried channel, and the integration is outlined. The functionality and transfer efficiency of the process enhancement were appraised by measuring CCD shift registers at 100 kHz. CMOS measurement results are presented, which include threshold voltages, poly-to-poly capacitor voltage and temperature coefficients, and dark current. A CCD/CMOS processor is described which combines smoothing and segmentation operations. The integration of the CCD and the CMOS processes is found to function due to the enhancement-compatible design of the CMOS process and the thorough employment of CCD module baseline process steps.

  9. CMOS prototype for retinal prosthesis applications with analog processing

    NASA Astrophysics Data System (ADS)

    Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Matsumoto-Kuwabara, Y.; Moreno-Cadenas, J. A.; Flores-Nava, L. M.

    2014-12-01

    A core architecture for analog processing, which emulates a retina's receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

  10. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

  11. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  12. Development of a radiation-hard CMOS process

    NASA Technical Reports Server (NTRS)

    Power, W. L.

    1983-01-01

    It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

  13. Monolithic integration of high bandwidth waveguide coupled Ge photodiode in a photonic BiCMOS process

    NASA Astrophysics Data System (ADS)

    Lischke, S.; Knoll, D.; Zimmermann, L.

    2015-03-01

    Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and highspeed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at λ= 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

  14. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  15. High-voltage CMOS detectors

    NASA Astrophysics Data System (ADS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  16. Integration of complex optical functionality in a production CMOS process

    NASA Astrophysics Data System (ADS)

    Gunn, Lawrence C., III

    Optical functionality has been developed within the confines of an existing CMOS process. As of this writing, 10Gigabit modulators, electrically tunable optical filters, waveguides, and grating coupler technology have been successfully implemented alongside the existing transistors in the Freescale Hip7SOI process. This technology will be used to manufacture high bandwidth optical interconnections directly on silicon chips, allowing a new type of network and computing infrastructure to be developed. This work is covered in two distinct phases. First, the exploratory work done to gain experience with high index contrast silicon waveguides primarily served to uncover challenges related with simulation of these devices, and with the practical limitations of efficiently coupling the resulting waveguide devices with the outside world. The second phase began as the grating coupler emerged to address the coupling challenge. It became feasible to conceive of a commercially viable technology based on silicon photonics. The coupler has been evolved to a high level, currently achieving coupling loss of less than 1dB. Once the light is on chip, filtering and modulation technology are implemented. The reverse-biased plasma dispersion modulator has a 3dB roll-off of 10GHz, and an insertion loss less than 5dB. Optical filters based on ring resonators, arrayed waveguide gratings, and interleavers have all been implemented, often with world record performance, and many of the devices have been made electronically tunable to compensate for manufacturing variations and environmental excursions. Finally, circuitry has been designed and constructed on the same die with the optical functionality, fully demonstrating the ability to achieve monolithic integration of these devices.

  17. Overview of CMOS process and design options for image sensor dedicated to space applications

    NASA Astrophysics Data System (ADS)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  18. Advanced simulation technology for etching process design for CMOS device applications

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki; Fukasawa, Masanaga; Tatsumi, Tetsuya

    2016-07-01

    Plasma etching is a critical process for the realization of high performance in the next generation of CMOS devices. To predict and control fluctuations in the etching properties accurately during mass production, it is essential that etching process simulation technology considers fluctuations in the plasma chamber wall conditions, the effects of by-products on the critical dimensions, the Si recess dependence on the wafer open area ratio and local pattern structure, and the time-dependent plasma-induced damage distribution associated with the three-dimensional feature scale profile at the 100 nm level. This consideration can overcome the issues with conventional simulations performed under the assumed ideal conditions, which are not accurate enough for practical process design. In this article, these advanced process simulation technologies are reviewed, and, from the results of suitable process simulations, a new etching system that automatically controls the etching properties is proposed to enable stable CMOS device fabrication with high yields.

  19. Micro-electro-mechanical bandpass filters for signal processing by standard CMOS process

    NASA Astrophysics Data System (ADS)

    Huang, Tsungwei; Chang, Peizen; Lee, ChiYuan; Xiao, Fuyuan

    2000-06-01

    This investigation fabricates a laminated-suspension microelectromechanical filter by a fully compatible CMOS process. Experimentally, due to the top metal layer begin used as the etch-resistant mask during the subsequent dry etching. Therefore, this study performs maskless etching with plasma and obtains excellent result including high selectivity and full release of the structure. Additionally, the MEMS filter can be driven by applying low-voltage of around 5 volts and a measured center frequency of around 13.1kHz and a quality factor of around 1871 were obtained for a single-comb resonator operate din air. The filter proposed herein has a monolithic integration capability with the relative electric circuits.

  20. Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

    PubMed Central

    Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

    2011-01-01

    This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

  1. Efficient smart CMOS camera based on FPGAs oriented to embedded image processing.

    PubMed

    Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L; Espinosa, Felipe; García, Jorge

    2011-01-01

    This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

  2. Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

    PubMed

    Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

    2015-02-01

    An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change. PMID:24956395

  3. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    PubMed Central

    López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  4. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

    NASA Astrophysics Data System (ADS)

    Qianqian, Lei; Min, Lin; Yin, Shi

    2013-03-01

    A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 μm CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within ±0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.

  5. Analog CMOS design for optical coherence tomography signal detection and processing.

    PubMed

    Xu, Wei; Mathine, David L; Barton, Jennifer K

    2008-02-01

    A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented. PMID:18269983

  6. Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

    NASA Technical Reports Server (NTRS)

    Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

    2009-01-01

    There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

  7. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1977-01-01

    Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

  8. Photo-Spectrometer Realized In A Standard Cmos Ic Process

    DOEpatents

    Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

    1999-10-12

    A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

  9. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    PubMed

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  10. Integration of solid-state nanopores in a 0.5 μm cmos foundry process

    PubMed Central

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-01-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  11. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process

    NASA Astrophysics Data System (ADS)

    Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

    2013-04-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  12. Sub-bandgap polysilicon photodetector in zero-change CMOS process for telecommunication wavelength.

    PubMed

    Meng, Huaiyu; Atabaki, Amir; Orcutt, Jason S; Ram, Rajeev J

    2015-12-14

    We report a defect state based guided-wave photoconductive detector at 1360-1630 nm telecommunication wavelength directly in standard microelectronics CMOS processes, with zero in-foundry process modification. The defect states in the polysilicon used to define a transistor gate assists light absorption. The body crystalline silicon helps form an inverse ridge waveguide to confine optical mode. The measured responsivity and dark current at 25 V forward bias are 0.34 A/W and 1.4 μA, respectively. The 3 dB bandwidth of the device is 1 GHz. PMID:26699053

  13. A linearity-enhanced time-domain CMOS thermostat with process-variation calibration.

    PubMed

    Chen, Chun-Chi; Lin, Yi

    2014-01-01

    This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-μm 2P4M CMOS process, and a robust resolution of 0.05 °C and dissipation of 25 μW were achieved at a sample rate of 10 samples/s. An inaccuracy of -0.35 °C to 1.35 °C was achieved after one-point calibration at temperatures ranging from -40 °C to 120 °C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

  14. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1980-01-01

    The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

  15. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  16. Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

    PubMed

    Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

    2013-01-01

    The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration. PMID:24110276

  17. Lithography with infrared illumination alignment for advanced BiCMOS backside processing

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Schulz, K.; Behrendt, U.; Wietstruck, M.; Kaynak, M.; Marschmeyer, S.; Tillack, B.

    2014-10-01

    Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVG®NT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 μm across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG®40NT automated measurement system

  18. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    NASA Astrophysics Data System (ADS)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  19. Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

    NASA Astrophysics Data System (ADS)

    Ajayan, K. R.; Bhat, Navakanta

    2012-10-01

    With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.

  20. On-chip nanostructures for polarization imaging and multispectral sensing using dedicated layers of modified CMOS processes

    NASA Astrophysics Data System (ADS)

    Junger, Stephan; Tschekalinskij, Wladimir; Verwaal, Nanko; Weber, Norbert

    2011-03-01

    Sub-wavelength gratings and hole arrays in metal films are applicable for polarization and spectral selective sensors, respectively. We demonstrate the fabrication of wire grid polarizers using standard complementary metal-oxide semiconductor (CMOS) processes. Extraordinary optical transmission of hole arrays was achieved by using the dedicated layer of a modified CMOS process. The structures were simulated using the finite-difference time-domain (FDTD) method and fabricated using the work flow of integrated circuits. A high-speed polarization image sensor with a pixel size of 6 μm was designed and demonstrated, and multispectral sensing was implemented using nanostructures with different spectral filter performances on a single chip.

  1. CMOS array of photodiodes with electronic processing for 3D optical reconstruction

    NASA Astrophysics Data System (ADS)

    Hornero, Gemma; Montane, Enric; Chapinal, Genis; Moreno, Mauricio; Herms, Atila

    2001-04-01

    It is well known that laser time-of-flight (TOF) and optical triangulation are the most useful optical techniques for distance measurements. The first one is more suitable for large distances, since for short range of distances high modulation frequencies of laser diodes (©200-500MHz) are needed. For these ranges, optical triangulation is simpler, as it is only necessary to read the projection of the laser point over a linear optical sensor without any laser modulation. Laser triangulation is based on the rotation of the object. This motion shifts the projected point over the linear sensor, resulting on 3D information, by means of the whole readout of the linear sensor in each angle position. On the other hand, a hybrid method of triangulation and TOF can be implemented. In this case, a synchronized scanning of a laser beam over the object results in different arrival times of light to each pixel. The 3D information is carried by these delays. Only a single readout of the linear sensor is needed. In this work we present the design of two different linear arrays of photodiodes in CMOS technology, the first one based on the Optical triangulation measurement and the second one based in this hybrid method (TFO). In contrast to PSD (Position Sensitive Device) and CCDs, CMOS technology can include, on the same chip, photodiodes, control and processing electronics, that in the other cases should be implemented with external microcontrollers.

  2. High-speed bipolar phototransistors in a 180 nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Zimmermann, H.

    2013-01-01

    Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm2 and 100×100 μm2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p− epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc. PMID:23847388

  3. A robust color signal processing with wide dynamic range WRGB CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

    2011-01-01

    We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor. The image sensor was fabricated through a 0.18 μm CMOS technology and has a 45 degrees oblique pixel array, the 4.2 μm effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY) signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate color processing with a large margin to the sensitivity fluctuation and noise has been achieved.

  4. High-speed bipolar phototransistors in a 180 nm CMOS process.

    PubMed

    Kostov, P; Gaberl, W; Zimmermann, H

    2013-03-01

    Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm(2) and 100×100 μm(2). Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p(+) wafer with a p(-) epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc. PMID:23847388

  5. Modeling and Manufacturing of a Micromachined Magnetic Sensor Using the CMOS Process without Any Post-Process

    PubMed Central

    Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

    2014-01-01

    The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA. PMID:24732100

  6. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    PubMed Central

    Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

    2015-01-01

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

  7. Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

    NASA Astrophysics Data System (ADS)

    Ma, Xiao-Hua; Hao, Yue; Sun, Bao-Gang; Gao, Hai-Xia; Ren, Hong-Xia; Zhang, Jin-Cheng; Zhang, Jin-Feng; Zhang, Xiao-Ju; Zhang, Wei-Dong

    2006-01-01

    N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

  8. CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

    NASA Astrophysics Data System (ADS)

    Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

    2015-12-01

    Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

  9. Avoiding sensor blindness in Geiger mode avalanche photodiode arrays fabricated in a conventional CMOS process

    NASA Astrophysics Data System (ADS)

    Vilella, E.; Diéguez, A.

    2011-12-01

    The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

  10. Nonlinear optical signal processing in high figure of merit CMOS compatible platforms

    NASA Astrophysics Data System (ADS)

    Moss, D. J.; Morandotti, R.

    2015-05-01

    Photonic integrated circuits that exploit nonlinear optics in order to generate and process signals all-optically have achieved performance far superior to that possible electronically - particularly with respect to speed. Although silicon-on-insulator has been the leading platform for nonlinear optics for some time, its high two-photon absorption at telecommunications wavelengths poses a fundamental limitation. We review the recent achievements based in new CMOS-compatible platforms that are better suited than SOI for nonlinear optics, focusing on amorphous silicon and Hydex glass. We highlight their potential as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement.

  11. Scaling Behavior of Carbon Nanotube-based Biosensors Integrated on CMOS Signal-processing Circuits

    NASA Astrophysics Data System (ADS)

    Lee, Byung Yang; Sung, Moon Gyu; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cho, Eunju; Hong, Seunghun; Seo, Sung Min; Cheon, Jun-Ho; Lee, Hyunjoong; Kim, Suhwan; Park, Young June; Chung, In-Young

    2010-03-01

    We built uniform arrays of carbon nanotube (CNT)-based biosensors via linker-free directed assembly strategy, where surface molecular patterns were utilized to direct the assembly of CNTs onto specific regions of the devices. The sensor arrays were utilized to detect ammonia and Hg^+ ions with high sensitivity and selectivity, and the scaling behavior of sensor sensitivity was studied by parallel detection of multiple sensors. We found that the scaling behavior of the sensor sensitivity can be explained by the combination of two effects: adsorption of analyte molecules onto CNT surface and the transconductance change of the CNT junctions. Furthermore, 64 CNT-based sensors were integrated with CMOS circuits into a single-die system-on-a-chip for the detection of glutamate, a neurotransmitter, by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors.

  12. Ge microdisk with lithographically-tunable strain using CMOS-compatible process.

    PubMed

    Sukhdeo, David S; Petykiewicz, Jan; Gupta, Shashank; Kim, Daeik; Woo, Sungdae; Kim, Youngmin; Vučković, Jelena; Saraswat, Krishna C; Nam, Donguk

    2015-12-28

    We present germanium microdisk optical resonators under a large biaxial tensile strain using a CMOS-compatible fabrication process. Biaxial tensile strain of ~0.7% is achieved by means of a stress concentration technique that allows the strain level to be customized by carefully selecting certain lithographic dimensions. The partial strain relaxation at the edges of a patterned germanium microdisk is compensated by depositing compressively stressed silicon nitride layer. Two-dimensional Raman spectroscopy measurements along with finite-element method simulations confirm a relatively homogeneous strain distribution within the final microdisk structure. Photoluminescence results show clear optical resonances due to whispering gallery modes which are in good agreement with finite-difference time-domain optical simulations. Our bandgap-customizable microdisks present a new route towards an efficient germanium light source for on-chip optical interconnects. PMID:26831991

  13. Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

    NASA Astrophysics Data System (ADS)

    Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

    2013-09-01

    This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

  14. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    PubMed

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  15. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    PubMed Central

    He, Diwei; Nguyen, Hoang C.; Hayes-Gill, Barrie R.; Zhu, Yiqun; Crowe, John A.; Gill, Cally; Clough, Geraldine F.; Morgan, Stephen P.

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  16. New interpretation of photonic yield processes (450-750nm) in multi-junction Si CMOS LEDs: simulation and analyses

    NASA Astrophysics Data System (ADS)

    Snyman, Lukas W.; Bellotti, Enrico

    2010-02-01

    Emission levels in the 450-750nm range of about 80-100 fold higher than that emitted by single junction avalanche LEDs, has been obtained. CMOS Si LED p+-i-np+ structures were modeled in order to investigate the effect of various depletion layer profiles and defect engineering on the photonic transitions in the 1.4 to 2.8 eV, 450-750nnm regime. Modeling and device simulation results showed that by utilizing a short lowly doped layer in between a highly doped p+ layer and n layer can enhance the photonic yields by orders of magnitude through an increase in the dynamic carrier densities in the device and favoring enhanced lateral multiplication processes. The electric field profile should be of the order of 5 x 105 V.cm-1 and about 0.5 micron long. Injecting of carriers of opposite charge type from an opposing forward bias junction further enhance the photonic yield. These models and interpretations is confirmed by analyses of device designs as realized in 1.2 μm and 0.35 CMOS technology. The device design involved normal CMOS design and processing procedures with no excessive micro-dimensioning. The current devices operated in the 8-10V, 1uA - 2mA regime and yield emission intensities of up to 100 nW.μm-2. The current emission levels are about three orders higher than the low frequency detectability limit of Si CMOS p-n detectors of corresponding area. The particular design favors higher emission levels towards the 750nm wavelength region. This makes diverse electro-optical applications possible such as optical communication on chip, diverse optical signal processing and wave-guiding. It also enables realization of on chip Micro-Optical-Electro-Mechanical Sensors (MOEMS), which could lead to the development of so-called "smart chips" utilizing standard CMOS integrated circuitry.

  17. A CMOS high resolution, process/temperature variation tolerant RSSI for WIA-PA transceiver

    NASA Astrophysics Data System (ADS)

    Tao, Yang; Yu, Jiang; Jie, Li; Jiangfei, Guo; Hua, Chen; Jingyu, Han; Guiliang, Guo; Yuepeng, Yan

    2015-08-01

    This paper presents a high resolution, process/temperature variation tolerant received signal strength indicator (RSSI) for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The active area of the RSSI is 0.24 mm2. Measurement results show that the proposed RSSI has a dynamic range more than 70 dB and the linearity error is within ±0.5 dB for an input power from -70 to 0 dBm (dBm to 50 Ω), the corresponding output voltage is from 0.81 to 1.657 V and the RSSI slope is 12.1 mV/dB while consuming all of 2 mA from a 1.8 V power supply. Furthermore, by the help of the integrated compensation circuit, the proposed RSSI shows the temperature error within ±1.5 dB from -40 to 85 °C, and process variation error within ±0.25 dB, which exhibits good temperature-independence and excellent robustness against process variation characteristics. Project supported by the National High Technology Research and Development Program of China (No. 2011AA040102).

  18. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1982-01-01

    The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

  19. Evaluation of Mo-doped Ti salicide process for sub-0.18-μm CMOS

    NASA Astrophysics Data System (ADS)

    Chao, Chih-Ping; Kittl, Jorge A.; Hong, Qi-Zhong; Shiau, Wei-Tsun; Rodder, Mark; Chen, Ih-Chin

    1998-09-01

    For scaled CMOS technology with gate length down to sub-0.25 micrometer, the conventional Ti salicide suffers from high polygate sheet resistance (Rsheet) due to difficulty in the low resistivity C54 TiSi2 phase transition. To improve the sub 0.25 micrometer TiSi2 Rsheet, pre-amorphization implant (PAI) was added to achieve low Rsheet down to approximately 0.1 micrometer gate length, and PAI based TiSi2 has been the base-line salicide process for current 0.25 micrometer CMOS technology. However, various studies on sub 0.18 micrometer devices have shown that PAI process tends to induce additional S/D dopant diffusion and results in the series resistance (RSD) increase and drive current degradation, especially for pMOS transistors. On the other hand, Mo implant was found effective in enhancing the C54 TiSi2 formation for narrow lines and has the potential to realize a simplified TiSi2 process with one single thermal step. However, the Mo based Ti salicide is still relatively new to date, and a complete CMOS study is helpful in identifying the trade-offs for such a process. In this work, we present a detailed CMOS evaluation of Mo doped TiSi2 process. Two different Mo based processes are studied: (1) Mo implant into gate before gate pattern (Mo-A case). In this case, the source/drain (S/D) diffusion regions have minimal Mo doping. (2) Mo implant into gate and S/D regions right before the S/D anneal (Mo-B case). For both Mo-A and Mo-B processes, we also studied the effect of Mo doses and the difference between the conventional 2-step rapid thermal process (RTP), low-temperature formation plus Ti strip plus high-temperature anneal, and the 1-step RTP process, namely low-T formation plus Ti stripe, where the high-T anneal is skipped. The results of the Mo processes are compared with three other reference salicide processes: conventional TiSi2 without PAI (Conv.), TiSi2 with Ge or As PAI and the emerging CoSi2 technology. The following CMOS care-abouts are evaluated for

  20. Design and implementation of non-linear image processing functions for CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Musa, Purnawarman; Sudiro, Sunny A.; Wibowo, Eri P.; Harmanto, Suryadi; Paindavoine, Michel

    2012-11-01

    Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 64×64 pixels image sensor built in a standard CMOS Technology 0.35 μm including non-linear image processing. The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 2×2 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 40×40 mu m. The total area of the 64×64 pixels is 12.5mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (10K frames per second), minima/maxima calculations in less then one ms.

  1. System on chip thermal vacuum sensor based on standard CMOS process

    NASA Astrophysics Data System (ADS)

    Jinfeng, Li; Zhen'an, Tang; Jiaqi, Wang

    2009-03-01

    An on-chip microelectromechanical system was fabricated in a 0.5 μm standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 105 Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/ Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 ω resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  2. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    NASA Technical Reports Server (NTRS)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  3. Design and application of a metal wet-etching post-process for the improvement of CMOS-MEMS capacitive sensors

    NASA Astrophysics Data System (ADS)

    Tsai, Ming-Han; Sun, Chih-Ming; Liu, Yu-Chia; Wang, Chuanwei; Fang, Weileun

    2009-10-01

    This study presents a process design methodology to improve the performance of a CMOS-MEMS gap-closing capacitive sensor. In addition to the standard CMOS process, the metal wet-etching approach is employed as the post-CMOS process to realize the present design. The dielectric layers of the CMOS process are exploited to form the main micro mechanical structures of the sensor. The metal layers of the CMOS process are used as the sensing electrodes and sacrificial layers. The advantages of the sensor design are as follows: (1) the parasitic capacitance is significantly reduced by the dielectric structure, (2) in-plane and out-of-plane sensing gaps can be reduced to increase the sensitivity, and (3) plate-type instead of comb-type out-of-plane sensing electrodes are available to increase the sensing electrode area. To demonstrate the feasibility of the present design, a three-axis capacitive CMOS-MEMS accelerometers chip is implemented and characterized. Measurements show that the sensitivities of accelerometers reach 11.5 mV G-1 (in the X-, Y-axes) and 7.8 mV G-1 (in the Z-axis), respectively, which are nearly one order larger than existing designs. Moreover, the detection of 10 mG excitation using the three-axis accelerometer is demonstrated for both in-plane and out-of-plane directions.

  4. Novel processes for modular integration of silicon-germanium MEMS with CMOS electronics

    NASA Astrophysics Data System (ADS)

    Low, Carrie Wing-Zin

    Equipment control, process development and materials characterization for LPCVD poly-SiGe for MEMS applications are investigated in this work. In order to develop a repeatable process in an academic laboratory, equipment monitoring methods are implemented and new process gases are explored. With the dopant gas BCl3, the design-of-experiments technique is used to study the dependencies of deposition rate, resistivity, average residual stress, strain gradient and wet etch rate in hydrogen-peroxide. Structural layer requirements for general MEMS applications are met within the process temperature constraint imposed by CMOS electronics. However, the strain gradient required for inertial sensor applications is difficult to achieve with as-deposited films. Approaches to reduce the strain gradient of LPCVD poly-SiGe are investigated. Correlation between the strain gradient and film microstructure is found using stress-depth profiling and cross-sectional TEM analysis. The effects of film deposition conditions on film microstructure are also determined. Boron-doped poly-SiGe films generally have vertically oriented grains---either conical or columnar in shape. Films with conical grain structure have large strain gradient due to highly compressive stress in the lower (initially deposited) region of the film. Films with small strain gradient usually have columnar grain structure with low defect density. It is also found that the uniformity of films deposited in a batch LPCVD reactor can be improved by increasing the deposited film thickness, using a proper seeding layer, and/or depositing the film in multiple layers. The best strain gradient achieved in our academic research laboratory is 1.1x10-6 mum-1 for a ˜3.5 mum thick film deposited at 410°C in 8 hours, with a worst-case variation across a 150 mm-diameter wafer of 1.6x10 -5 mum-1 and a worse-case variation across a load of twenty-five wafers of 7x10-5 mum-1. The effects of post-deposition annealing and argon

  5. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  6. Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

    NASA Astrophysics Data System (ADS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-10-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  7. Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

    NASA Astrophysics Data System (ADS)

    Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

    2014-06-01

    A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10μs latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

  8. On-chip skin color detection using a triple-well CMOS process

    NASA Astrophysics Data System (ADS)

    Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

    2004-03-01

    In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

  9. Polarization- and wavelength-sensitive sub-wavelength structures fabricated in the metal layers of deep submicron CMOS processes

    NASA Astrophysics Data System (ADS)

    Junger, Stephan; Tschekalinskij, Wladimir; Verwaal, Nanko; Weber, Norbert

    2010-05-01

    Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm. We describe the design and simulation of these metal structures using the finite-difference timedomain (FDTD) method. The spectral response of the test structures was measured for different polarizations, where the gratings showed typical features of wire grid polarizers. Using a 180 nm CMOS image sensor process, an image sensor with 6 μm pixel size was designed and fabricated with different polarization selective structures allowing for polarization imaging. A polarization camera using this image sensor is demonstrated, visualizing stress birefringence as an application example. Finally, first results on the fabrication of hole arrays with a period of 320 nm are presented, showing color filters with enhanced transmission.

  10. CMOS-liquid-crystal-based image transceiver device

    NASA Astrophysics Data System (ADS)

    Efron, Uzi; Davidov, Isak; Sinelnikov, Vladimir; Levin, Ilya

    2001-05-01

    A CMOS-Liquid Crystal-Based Image Transceiver Device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaginary and display in a single array structure. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel elements are designed to provide image sensor part of the pixel is based on an n-well photodiode and a three-transistors readout circuit. The imaging function is based on a back- illuminated sensor configuration. In order to provide a high imager fill-factor, two pixel configuration are proposed: 1) A p++/p-/p-well silicon structure using twin- well CMOS process; 2) an n-well processed silicon structure with a micro-lens array. The display portion of the IT device is to be fabricate don a silicon-based reflective, active matrix driver, using nematic liquid crystal material. The reflective display pixel electrode is driven by an n-MOS transistor, formed in the corresponding pixel region on the silicon substrate. The timing, sequencing and control of the IT device array are designed in a pipeline array processing scheme. A preliminary prototype system and device design have been performed and the first test device is currently being tested. Details of the device design as well as its smart goggle applications are presented.

  11. CMOS/LCOS-based image transceiver device: II

    NASA Astrophysics Data System (ADS)

    Efron, Uzi; Davidov, Isak; Sinelnikov, Vladimir; Friesem, Asher A.

    2001-11-01

    A CMOS-liquid crystal-based image transceiver device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaging and display in a single array configuration. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel elements are designed to provide efficient imaging in the visible range as well as driver capabilities for the overlying liquid crystal modulator. The image sensor part of the pixel is based on an n-well photodiode and a three-transistor readout circuit. The imaging function is based on a back- illuminated sensor configuration. In order to provide a high imager fill-factor, two pixel configurations are proposed: 1) A p++/p-/p-well silicon structure using twin- well CMOS process; 2) An n-well processed silicon structure with a micro-lens array. The display portion of the IT device is to be fabricated on a silicon-based reflective, active matrix driver, using nematic liquid crystal material, in LCOS technology. The timing, sequencing and control of the IT device array are designed in a pipeline array processing scheme. A preliminary prototype system and device design have been performed and the first test device is currently undergoing testing. Details of the device design as well as its Smart Goggle applications are presented.

  12. CMOS Geiger photodiode array with integrated signal processing for imaging of 2D objects using quantum dots

    NASA Astrophysics Data System (ADS)

    Stapels, Christopher J.; Lawrence, William G.; Gurjar, Rajan S.; Johnson, Erik B.; Christian, James F.

    2008-08-01

    Geiger-mode photodiodes (GPD) act as binary photon detectors that convert analog light intensity into digital pulses. Fabrication of arrays of GPD in a CMOS environment simplifies the integration of signal-processing electronics to enhance the performance and provide a low-cost detector-on-a-chip platform. Such an instrument facilitates imaging applications with extremely low light and confined volumes. High sensitivity reading of small samples enables twodimensional imaging of DNA arrays and for tracking single molecules, and observing their dynamic behavior. In this work, we describe the performance of a prototype imaging detector of GPD pixels, with integrated active quenching for use in imaging of 2D objects using fluorescent labels. We demonstrate the integration of on-chip memory and a parallel readout interface for an array of CMOS GPD pixels as progress toward an all-digital detector on a chip. We also describe advances in pixel-level signal processing and solid-state photomultiplier developments.

  13. Design and implementation of IEEE 802.11ac MAC controller in 65 nm CMOS process

    NASA Astrophysics Data System (ADS)

    Peng, Cheng; Bin, Wu; Yong, Hei

    2016-02-01

    An IEEE-802.11ac-1*1 wireless LAN system-on-a-chip (SoC) that integrates an analog front end, a digital base-band processor and a media access controller has been implemented in 65 nm CMOS technology. It can provide significantly increased throughput, high efficiency rate selection, and fully backward compatibility with the existing 802.11a/n WLAN protocols. Especially the measured maximum throughput of UDP traffic can be up to 267 Mbps. Project supported by the National Great Specific Project of China (No. 2012ZX03004004_001).

  14. Investigation of a seesaw structure for elevating the micro-optical device by CMOS-MEMS process

    NASA Astrophysics Data System (ADS)

    Tsai, Chien-Chung; Tsai, Shang-Che; Huang, Yi-Cheng

    2007-01-01

    The paper proposed a novel seesaw structure for elevating the micro optical device by the driving force of micro array thermal actuator, MATA. The effects of elevating structure, lateral connection arm structure, immobile structure and width of vertical connection arm on the maximum displacements and the variation of surface flatness of the elevated micro mirror surface varied with operation voltage are investigated. The motion behavior of the elevated micro mirror is stimulated and analyzed to get the maximum displacement and inclined angle of the device. The results demonstrate a pair of {1 x 2} parallel type MATA for the elevating structure, simple beam for the lateral connection arm structure, single thermal actuator for the immobile structure and 10μm for width of vertical connection arm are the optimum design for the micro optical device. The maximum displacement and inclined angle of the proposed micro optical device are 34.7μm and 10 °, respectively. The device is fabricated by Taiwan Semiconductor Manufacture Cooperation, TSMC 0.35μm 2P4M mixed signal model, based upon CIC CMOS-MEMS process. The paper will examine whether CIC CMOS-MEMS could fully support to fabricate the integrated component for MOEMS.

  15. Analysis of pixel circuits in CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Mei, Zou; Chen, Nan; Yao, Li-bin

    2015-04-01

    CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-μm CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.

  16. Micro ethanol sensors with a heater fabricated using the commercial 0.18 μm CMOS process.

    PubMed

    Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

  17. An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

    2014-01-01

    This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

  18. Ionization versus displacement damage effects in proton irradiated CMOS sensors manufactured in deep submicron process

    NASA Astrophysics Data System (ADS)

    Goiffon, V.; Magnan, P.; Saint-Pé, O.; Bernard, F.; Rolland, G.

    2009-10-01

    Proton irradiation effects have been studied on CMOS image sensors manufactured in a 0.18 μm technology dedicated to imaging. The ionizing dose and displacement damage effects were discriminated and localized thanks to 60Co irradiations and large photodiode reverse current measurements. The only degradation observed was a photodiode dark current increase. It was found that ionizing dose effects dominate this rise by inducing generation centers at the interface between shallow trench isolations and depleted silicon regions. Displacement damages are is responsible for a large degradation of dark current non-uniformity. This work suggests that designing a photodiode tolerant to ionizing radiation can mitigate an important part of proton irradiation effects.

  19. An Unassisted Low-Voltage-Trigger ESD Protection Structure in a 0.18-µm CMOS Process without Extra Process Cost

    NASA Astrophysics Data System (ADS)

    Li, Bing; Shan, Yi

    In order to quickly discharge the electrostatic discharge (ESD) energy, an unassisted low-voltage-trigger ESD protection structure is proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structure. Moreover there is no need to add any extra mask or do any process modification for the new structure. The proposed structure has been verified in foundry's 0.18-µm CMOS process.

  20. Impact of silicide layer on single photon avalanche diodes in a 130 nm CMOS process

    NASA Astrophysics Data System (ADS)

    Cheng, Zeng; Palubiak, Darek; Zheng, Xiaoqing; Deen, M. Jamal; Peng, Hao

    2016-09-01

    Single photon avalanche diode (SPAD) is an attractive solid-state optical detector that offers ultra-high photon sensitivity (down to the single photon level), high speed (sub-nanosecond dead time) and good timing performance (less than 100 ps). In this work, the impact of the silicide layer on SPAD’s characteristics, including the breakdown voltage, dark count rate (DCR), after-pulsing probability and photon detection efficiency (PDE) is investigated. For this purpose, two sets of SPAD structures in a standard 130 nm complementary metal oxide semiconductor (CMOS) process are designed, fabricated, measured and compared. A factor of 4.5 (minimum) in DCR reduction, and 5 in PDE improvements are observed when the silicide layer is removed from the SPAD structure. However, the after-pulsing probability of the SPAD without silicide layer is two times higher than its counterpart with silicide. The reasons for these changes will be discussed.

  1. Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

    PubMed Central

    Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

  2. Which Photodiode to Use: A Comparison of CMOS-Compatible Structures

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2010-01-01

    While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n+/p-sub, n-well/p-sub and p+/n-well/p-sub. All structures were fabricated in a 0.5 μm 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated—the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 × and 1.6 × over the n+/p-sub and p+/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 × and 1.2 × improvement over the n+/p-sub and p+/n-well/p-sub diodes, respectively) while the p+/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity. PMID:20454596

  3. Designing a ring-VCO for RFID transponders in 0.18 μm CMOS process.

    PubMed

    Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

    2014-01-01

    In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. PMID:24587731

  4. PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Hofbauer, M.; Zimmermann, H.

    2012-01-01

    This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high −3 dB bandwidth at low collector–emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm2 and 100 × 100 μm2. Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done. PMID:23482349

  5. A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

    NASA Astrophysics Data System (ADS)

    Bo, Zhong; Zhangming, Zhu

    2016-05-01

    A 0.1–1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter (LPF) is significantly decreased by implementing a dual path charge pump (CP) technique in this PLL. Subject to specified power consumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator (VCO), CP and phase/frequency detector (PFD) in order to minimize clock jitter. This method could improve 3–6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal–oxide–metal (MOM) capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is ‑102 dBc/Hz @ 1 MHz offset frequency. Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the National High-Tech Program of China (No. 2013AA014103).

  6. Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

    PubMed Central

    Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

    2014-01-01

    In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency. PMID:24587731

  7. Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

    2006-01-01

    We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

  8. Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Panicacci, Roger; Pain, Bedabrata; Zhou, Zhimin; Nakamura, Junichi; Fossum, Eric R.

    1996-03-01

    Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 micrometers pitch in a 1.2 micrometers n-well CMOS process and a 40 micrometers pitch in a 2 micrometers n-well CMOS process. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 (mu) W at a 5 KHz conversion rate.

  9. Low-cost uncooled infrared detector arrays in standard CMOS

    NASA Astrophysics Data System (ADS)

    Eminoglu, Selim; Tanrikulu, M. Y.; Akin, Tayfun

    2003-09-01

    This paper reports the development of a low-cost 128 x 128 uncooled infrared focal plane array (FPA) based on suspended and thermally isolated CMOS p+-active/n-well diodes. The FPA is fabricated using a standard 0.35 μm CMOS process followed by simple post-CMOS bulk micromachining that does not require any critical lithography or complicated deposition steps; and therefore, the cost of the uncooled FPA is almost equal to the cost of the CMOS chip. The post-CMOS fabrication steps include an RIE etching to reach the bulk silicon and an anisotropic silicon etching to obtain thermally isolated pixels. During the RIE etching, CMOS metal layers are used as masking layers, and therefore, narrow openings such as 2 μm can be defined between the support arms. This approach allows achieving small pixel size of 40 μm x 40 μm with a fill factor of 44%. The FPA is scanned at 30 fps by monolithically integrated multi-channel parallel readout circuitry which is composed of low-noise differential transconductance amplifiers, switched capacitor (SC) integrators, sample-and-hold circuits, and various other circuit blocks for reducing the effects of variations in detector voltage and operating temperature. The fabricated detector has a temperature coefficient of -2 mV/K, a thermal conductance value of 1.8 x 10-7 W/K, and a thermal time constant value of 36 msec, providing a measured DC responsivity (R) of 4970 V/W under continuous bias. Measured detector noise is 0.69 μV in 8 kHz bandwidth at 30 fps scanning rate, resulting a measured detectivity (D*) of 9.7 x 108 cm√HzW. Contribution of the 1/f noise component is found to be negligible due to the single crystal nature of the silicon n-well and its low value at low bias levels. The noise of the readout circuit is measured as 0.76 μV, resulting in an expected NETD value of 1 K when scanned at 30 fps using f=1 optics. This NETD value can be decreased below 350 mK by decreasing the electrical bandwidth with the help of increased

  10. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

    NASA Astrophysics Data System (ADS)

    Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

  11. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  12. On the processing aspects of high performance hybrid backside illuminated CMOS imagers

    NASA Astrophysics Data System (ADS)

    De Vos, Joeri; De Munck, Koen; Minoglou, Kiki; Ramachandra Rao, Padmakumar; Akif Erismis, Mehmet; De Moor, Piet; Sabuncuoglu Tezcan, Deniz

    2011-07-01

    In this paper we present a successful integration scheme of a backside (BS) illuminated 1024 × 1024 pixel, 30 µm thin, sensor array that is flip chipped on a read-out IC die with 10 µm diameter indium micro bumps, where the pixel pitch is 22.5 µm. A novel BS alignment strategy to avoid Pyrex glass as a temporary carrier for wafer thinning is described. Pyrex is namely not compatible in a high-end Si process environment due to its fragile and contaminating nature. Further special attention is given to critical steps leading toward high broadband quantum efficiency of 80-90%. It is also shown that through the introduction of high aspect ratio pixel separating trenches, inter-pixel electrical crosstalk can be avoided.

  13. High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

    NASA Technical Reports Server (NTRS)

    Mueller, Carl; Alterovitz, Samuel; Croke, Edward; Ponchak, George

    2004-01-01

    System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced

  14. A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

    PubMed Central

    Zhang, Fan; Niu, Hanben

    2016-01-01

    In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

  15. Simulation, fabrication and characterization of a 3.3 V flash ZE 2PROM array implemented in a 0.8 μm CMOS process

    NASA Astrophysics Data System (ADS)

    Ranaweera, J.; Ng, W. T.; Salama, C. A. T.

    1999-02-01

    This paper describes a Zener based flash memory cell (ZE 2PROM), programmed from hot electrons generated by a heavily doped reverse biased p +n + junction attached to the drain. The cell can be implemented in a NOR type memory array. It uses an orthogonal write technique to achieve fast programming with low power dissipation and reduced drain disturbance. The modeling of the charge transfer behavior of the flash ZE 2PROM cell is also done to describe the charging and discharging of the floating gate during programming and erasing. The flash ZE 2PROM arrays were implemented in a 0.8 μm lithography CMOS process flow in which the n-LDD step was replaced with a one sided p + boron implant with a doping level of ˜10 19 cm -3. This minor change to a standard CMOS process, makes the concept highly attractive for embedded memory applications. A programming time of 850 ns at 3.3 V supply was achieved on fabricated test devices.

  16. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    NASA Technical Reports Server (NTRS)

    Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

    1994-01-01

    This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

  17. Fabrication of CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  18. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  19. 5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    PubMed Central

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  20. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

    PubMed Central

    Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

    2014-01-01

    The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

  1. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  2. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2012-01-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

  3. A microfluidic device integrating dual CMOS polysilicon nanowire sensors for on-chip whole blood processing and simultaneous detection of multiple analytes.

    PubMed

    Kuan, Da-Han; Wang, I-Shun; Lin, Jiun-Rue; Yang, Chao-Han; Huang, Chi-Hsien; Lin, Yen-Hung; Lin, Chih-Ting; Huang, Nien-Tsu

    2016-08-01

    The hemoglobin-A1c test, measuring the ratio of glycated hemoglobin (HbA1c) to hemoglobin (Hb) levels, has been a standard assay in diabetes diagnosis that removes the day-to-day glucose level variation. Currently, the HbA1c test is restricted to hospitals and central laboratories due to the laborious, time-consuming whole blood processing and bulky instruments. In this paper, we have developed a microfluidic device integrating dual CMOS polysilicon nanowire sensors (MINS) for on-chip whole blood processing and simultaneous detection of multiple analytes. The micromachined polymethylmethacrylate (PMMA) microfluidic device consisted of a serpentine microchannel with multiple dam structures designed for non-lysed cells or debris trapping, uniform plasma/buffer mixing and dilution. The CMOS-fabricated polysilicon nanowire sensors integrated with the microfluidic device were designed for the simultaneous, label-free electrical detection of multiple analytes. Our study first measured the Hb and HbA1c levels in 11 clinical samples via these nanowire sensors. The results were compared with those of standard Hb and HbA1c measurement methods (Hb: the sodium lauryl sulfate hemoglobin detection method; HbA1c: cation-exchange high-performance liquid chromatography) and showed comparable outcomes. Finally, we successfully demonstrated the efficacy of the MINS device's on-chip whole blood processing followed by simultaneous Hb and HbA1c measurement in a clinical sample. Compared to current Hb and HbA1c sensing instruments, the MINS platform is compact and can simultaneously detect two analytes with only 5 μL of whole blood, which corresponds to a 300-fold blood volume reduction. The total assay time, including the in situ sample processing and analyte detection, was just 30 minutes. Based on its on-chip whole blood processing and simultaneous multiple analyte detection functionalities with a lower sample volume requirement and shorter process time, the MINS device can be

  4. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  5. A diffractive multispectral image sensor with on- and off-die signal processing and on-die optics in 0.18-micron CMOS

    NASA Astrophysics Data System (ADS)

    Thomas, Christopher; Hornsey, Richard

    2007-02-01

    On-die optics have been proposed for imaging, spectral analysis, and communications applications. These systems typically require extra process steps to fabricate on-die optics. Fabrication of diffractive optics using the metal layers in commercial CMOS processes circumvents this requirement, but produces optical elements with poor imaging behavior. This paper discusses the application of Wiener filtering to reconstruction of images suffering from blurring and chromatic aberration, and to identification of the position and wavelength of point sources. Adaptation of this approach to analog and digital FIR implementations are discussed, and the design of a multispectral imaging sensor using analog FIR filtering is presented. Simulations indicate that off-die post-processing can determine point source wavelength to within 5% and position to within +/-0.05 radian, and resolve features 0.4 radian in size in images illuminated by white light. The analog hardware implementation is simulated to resolve features 0.4 radian in size illuminated by monochromatic light, and 0.7 radian with white light.

  6. Development of cryogenic readout electronics using fully-depleted-silicon-on-insulator CMOS process for future space borne far-infrared image sensors

    NASA Astrophysics Data System (ADS)

    Nagata, Hirohisa; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi

    2009-12-01

    We measured the static characteristics and noise spectra of FD-SOI-CMOS at liquid helium temperature where many bulk-CMOS transistors suffer from anomalous behaviors on the current-voltage curves such as kink phenomena. The test results showed that the static characteristics depend on the layouts of the FD-SOI-CMOS transistor. While a body floating FD-SOI-CMOS transistor showed strong anomalous effects on the I-V curves, body-tied and ST ones showed much better static characteristics than the body floating one. Using the characteristics derived from the FET measurements, we show that a low power and high gain preamplifier suitable for far-infrared detectors can be designed.

  7. ESD protection design for advanced CMOS

    NASA Astrophysics Data System (ADS)

    Huang, Jin B.; Wang, Gewen

    2001-10-01

    ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

  8. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  9. Characterization and reliability of CMOS microstructures

    NASA Astrophysics Data System (ADS)

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  10. SEMICONDUCTOR INTEGRATED CIRCUITS: A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

    NASA Astrophysics Data System (ADS)

    Jingchao, Wang; Chun, Zhang; Zhihua, Wang

    2010-08-01

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks—including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU—in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 × 3.8 mm2 including pads.

  11. A 0.23 pJ 11.05-bit ENOB 125-MS/s pipelined ADC in a 0.18 μm CMOS process

    NASA Astrophysics Data System (ADS)

    Yong, Wang; Jianyun, Zhang; Rui, Yin; Yuhang, Zhao; Wei, Zhang

    2015-05-01

    This paper describes a 12-bit 125-MS/s pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 μm CMOS process. A gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.79 least significant bit (LSB) and 0.86 LSB, respectively, at the full sampling rate. The ADC exhibits an effective number of bits (ENOB) of more than 11.05 bits at the input frequency of 10.5 MHz. The ADC also achieves a 10.5 bits ENOB with the Nyquist input frequency at the full sample rate. In addition, the ADC consumes 62 mW from a 1.9 V power supply and occupies 1.17 mm2, which includes an on-chip reference buffer. The figure-of-merit of this ADC is 0.23 pJ/step. Project supported by the Foundation of Shanghai Municipal Commission of Economy and Informatization (No. 130311).

  12. Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Hurwitz, Paul; Mann, Richard; Qamar, Yasir; Chaudhry, Samir; Zwingman, Robert; Howard, David; Racanelli, Marco

    2012-06-01

    Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.

  13. Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

    NASA Astrophysics Data System (ADS)

    Lee, Kwang Hong; Bao, Shuyu; Zhang, Li; Kohen, David; Fitzgerald, Eugene; Tan, Chuan Seng

    2016-08-01

    The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.

  14. Characterization and comparison of lateral amorphous semiconductors with embedded Frisch grid detectors on 0.18μm CMOS processed substrate for medical imaging applications

    NASA Astrophysics Data System (ADS)

    Hristovski, Christos; Goldan, Amir; Majid, Shaikh Hasibul; Wang, Kai; Shafique, Umar; Karim, Karim

    2011-03-01

    An indirect digital x-ray detector is designed, fabricated, and tested. The detector integrates a high speed, low noise CMOS substrate with two types of amorphous semiconductors on the circuit surface. Using a laterally oriented layout a-Si:H or a-Se can be used to coat the CMOS circuit and provide high speed photoresponse to complement the high speed circuits possible on CMOS technology. The circuit also aims to reduce the effect of slow carriers by integrated a Frisch style grid on the photoconductive layer to screen for the slow carriers. Simulations show a uniform photoresponse for photons absorbed on the top layer and an enhanced response when using a Frisch grid. EQE and noise results are presented. Finally, possible applications and improvements to the area of indirect x-ray imaging that are capable of easily being implemented on the substrate are suggested.

  15. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  16. Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

    PubMed Central

    Huang, Yue; Mason, Andrew J.

    2013-01-01

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

  17. Implantable CMOS Biomedical Devices

    PubMed Central

    Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

    2009-01-01

    The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented. PMID:22291554

  18. CMOS floating-point vector-arithmetic unit

    NASA Astrophysics Data System (ADS)

    Timmermann, D.; Rix, B.; Hahn, H.; Hosticka, B. J.

    1994-05-01

    This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 micron double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

  19. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  20. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  1. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  2. Ink-Jet Printed CMOS Electronics from Oxide Semiconductors.

    PubMed

    Garlapati, Suresh Kumar; Baby, Tessy Theres; Dehm, Simone; Hammad, Mohammed; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2015-08-01

    Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation. PMID:25867029

  3. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  4. Theoretical performance analysis for CMOS based high resolution detectors.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  5. Fully CMOS-compatible titanium nitride nanoantennas

    NASA Astrophysics Data System (ADS)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  6. CCD and CMOS sensors

    NASA Astrophysics Data System (ADS)

    Waltham, Nick

    The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

  7. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  8. CMOS Compatible 3-Axis Magnetic Field Sensor using Hall Effect Sensing

    NASA Astrophysics Data System (ADS)

    Locke, Joshua R.

    The purpose of this study is to design, fabricate and test a CMOS compatible 3-axis Hall effect sensor capable of detecting the earth's magnetic field, with strength's of ˜50 muT. Preliminary testing of N-well Van Der Pauw structures using strong neodymium magnets showed proof of concept for hall voltage sensing, however, poor geometry of the structures led to a high offset voltage. A 1-axis Hall effect sensor was designed, fabricated and tested with a sensitivity of 1.12x10-3 mV/Gauss using the RIT metal gate PMOS process. Poor geometry and insufficient design produced an offset voltage of 0.1238 volts in the 1-axis design; prevented sensing of the earth's magnetic field. The new design features improved geometry for sensing application, improved sensitivity and use the RIT sub-CMOS process. The completed 2-axis device showed an average sensitivity to large magnetic fields of 0.0258 muV/Gauss at 10 mA supply current.

  9. OLED-on-CMOS integration for optoelectronic sensor applications

    NASA Astrophysics Data System (ADS)

    Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Törker, Michael; Grillberger, Christiane; Amelung, Jörg

    2007-02-01

    Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

  10. A 16-channel CMOS preamplifier for laser ranging radar receivers

    NASA Astrophysics Data System (ADS)

    Liu, Ru-qing; Zhu, Jing-guo; Jiang, Yan; Li, Meng-lin; Li, Feng

    2015-10-01

    A 16-channal front-end preamplifier array has been design in a 0.18um CMOS process for pulse Laser ranging radar receiver. This front-end preamplifier array incorporates transimpedance amplifiers(TIAs) and differential voltage post-amplifier(PAMP),band gap reference and other interface circuits. In the circuit design, the regulated cascade (RGC) input stage, Cherry-Hooper and active inductor peaking were employed to enhance the bandwidth. And in the layout design, by applying the layout isolation structure combined with P+ guard-ring(PGR), N+ guard-ring(NGR),and deep-n-well(DNW) for amplifier array, the crosstalk and the substrate noise coupling was reduced effectively. The simulations show that a single channel receiver front-end preamplifier achieves 95 dBΩ transimpedance gain and 600MHz bandwidth for 3 PF photodiode capacitance. The total power of 16-channel front-end amplifier array is about 800mW for 1.8V supply.

  11. Biosensing with integrated CMOS nanopores

    NASA Astrophysics Data System (ADS)

    Uddin, Ashfaque; Yemenicioglu, Sukru; Chen, Chin-Hsuan; Corgliano, Ellie; Milaninia, Kaveh; Xia, Fan; Plaxco, Kevin; Theogarajan, Luke

    2012-10-01

    This paper outlines our recent efforts in using solid-state nanopores as a biosensing platform. Traditionally biosensors concentrate mainly on the detection platform and not on signal processing. This decoupling can lead to inferior sensors and is exacerbated in nanoscale devices, where device noise is large and large dynamic range is required. This paper outlines a novel platform that integrates the nano, micro and macroscales in a closely coupled manner that mitigates many of these problems. We discuss our initial results of DNA translocation through the nanopore. We also briefly discuss the use of molecular recognition properties of aptamers with the versatility of the nanopore detector to design a new class of biosensors in a CMOS compatible platform.

  12. Spectrum acquisition of detonation based on CMOS

    NASA Astrophysics Data System (ADS)

    Li, Yan; Bai, Yonglin; Wang, Bo; Liu, Baiyu; Xue, Yingdong; Zhang, Wei; Gou, Yongsheng; Bai, Xiaohong; Qin, Junjun; Xian, Ouyang

    2010-10-01

    The detection of high-speed dynamic spectrum is the main method to acquire transient information. In order to obtain the large amount spectral data in real-time during the process of detonation, a CMOS-based system with high-speed spectrum data acquisition is designed. The hardware platform of the system is based on FPGA, and the unique characteristic of CMOS image sensors in the rolling shutter model is used simultaneously. Using FPGA as the master control chip of the system, not only provides the time sequence for CIS, but also controls the storage and transmission of the spectral data. In the experiment of spectral data acquisition, the acquired information is transmitted to the host computer through the CameraLink bus. The dynamic spectral curve is obtained after the subsequent processing. The experimental results demonstrate that this system is feasible in the acquisition and storage of high-speed dynamic spectrum information during the process of detonation.

  13. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  14. Interferometric comparison of the performance of a CMOS and sCMOS detector

    NASA Astrophysics Data System (ADS)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  15. IR CMOS: infrared enhanced silicon imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

    2013-06-01

    SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

  16. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  17. Depleted CMOS pixels for LHC proton-proton experiments

    NASA Astrophysics Data System (ADS)

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  18. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  19. Regenerative switching CMOS system

    DOEpatents

    Welch, James D.

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  20. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  1. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  2. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    PubMed

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips. PMID:26654281

  3. Quantitative optical metrology with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Furlong, Cosme; Kolenovic, Ervin; Ferguson, Curtis F.

    2004-08-01

    Recent advances in laser technology, optical sensing, and computer processing of data, have lead to the development of advanced quantitative optical metrology techniques for high accuracy measurements of absolute shapes and deformations of objects. These techniques provide noninvasive, remote, and full field of view information about the objects of interest. The information obtained relates to changes in shape and/or size of the objects, characterizes anomalies, and provides tools to enhance fabrication processes. Factors that influence selection and applicability of an optical technique include the required sensitivity, accuracy, and precision that are necessary for a particular application. In this paper, sensitivity, accuracy, and precision characteristics in quantitative optical metrology techniques, and specifically in optoelectronic holography (OEH) based on CMOS cameras, are discussed. Sensitivity, accuracy, and precision are investigated with the aid of National Institute of Standards and Technology (NIST) traceable gauges, demonstrating the applicability of CMOS cameras in quantitative optical metrology techniques. It is shown that the advanced nature of CMOS technology can be applied to challenging engineering applications, including the study of rapidly evolving phenomena occurring in MEMS and micromechatronics.

  4. A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

    SciTech Connect

    Maj, Piotr; Grybos, P.; Szczgiel, R.; Kmon, P.; Drozd, A.; Deptuch, G.

    2013-11-07

    We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 m. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

  5. A CMOS readout system for very large detector capacitances

    NASA Astrophysics Data System (ADS)

    Schoeneberg, U.; Hosticka, B. J.; Fent, J.; Oberlack, H.; Zimmer, G.

    1990-03-01

    In this contribution we present readout electronics for a liquid-argon calorimeter. It has been designed and optimized for operation at cryogenic temperatures and it is integrated in an n-well 2 μm CMOS technology. The chip contains 16 analog channels with switched-capacitor circuits for charge collection, storage, and amplification, and averaging and correlated double sampling circuits for noise reduction. Further components include a trigger generator, an analog multiplexer, digital control circuits for analog switching, and 50 ω cable drivers.

  6. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  7. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  8. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  9. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  10. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  11. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    SciTech Connect

    Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

  12. Improved Space Object Observation Techniques Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  13. Large area CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  14. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

    NASA Astrophysics Data System (ADS)

    Mingyuan, Yu; Ting, Li; Jiaqi, Yang; Shuangshuang, Zhang; Fujiang, Lin; Lin, He

    2016-07-01

    This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

  15. Development of on-CMOS chip micro-photonic and MOEMS systems

    NASA Astrophysics Data System (ADS)

    Snyman, Lukas W.; Okhai, Timothy; Bourouina, Tarik; Noell, Wilfried

    2011-03-01

    Advanced 3D CAD and optical simulation software were used to design first iteration on-CMOS chip MOEMS micro-systems. A Si Avalanche-based LED and an array of detectors interface laterally with a single arm canti-lever system, all to be fabricated with CMOS technology. Silicon nitride wave-guides are used as optical propagation channels offering losses of lower than 1dB.cm-1. Micro-bending and multi-planing of the wave guiding is possible. Far-field manipulation of the emitted channel radiation is possible. Mechanically designed and sensor systems can be added by means of CMOS post processing techniques. The emission level of the Si CMOS Av LEDs is 10+3 higher than the detectivity of silicon p-i-n detectors, offering good dynamic range in detection and data analyses. The mature processing characteristics of CMOS technology offers high integration possibilities and low cost manufacturing of the designed systems.

  16. High-performance monolithic CMOS detectors for space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Vignon, Bruno; Magnan, Pierre; Farre, Jean A.; Corbiere, Franck; Martin-Gonthier, Philippe

    2001-12-01

    During the last 10 years, research about CMOS image sensors (also called APS - Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on chip control and processing electronics, low power dissipation, high level of radiation tolerance... Many image sensor companies, institutes and laboratories have demonstrated the compatibility of CMOS image sensors with consumer applications: micro-cameras, video-conferencing, digital- still cameras. And recent designs have shown that APS is getting closer to the CCD in terms of performance level. However, he large majority of the existing products do not offer the specific features which are required for many space applications. ASTRIUM and SUPAERO/CIMI have decided to work together in view of developing CMOS image sensors dedicated to space business. After a brief presentation of the team organization for space image sensor design and production, the latest results of a high performances 512 X 512 pixels CMOS device characterization are presented with emphasis on the achieved electro-optical performance. Finally, the on going and short-term coming activities of the team are discussed.

  17. Challenges of nickel silicidation in CMOS technologies

    SciTech Connect

    Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet; Baumann, Frieder; Klymko, Nancy; Nummy, Karen; Sun, Bing; Jordan-Sweet, Jean; Yu, Jian; Zhu, Frank; Narasimha, Shreesh; Chudzik, Michael

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  18. Impact of technology trends on SEU in CMOS SRAMs

    SciTech Connect

    Dodd, P.E.; Sexton, F.W.; Hash, G.L.; Shaneyfelt, M.R.; Draper, B.L.; Farino, A.J.; Flores, R.S.

    1996-12-01

    The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. The authors study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation to the development of a 0.5-{micro}m radiation-hardened CMOS SRAM is presented.

  19. Optimum Design of CMOS DC-DC Converter for Mobile Applications

    NASA Astrophysics Data System (ADS)

    Katayama, Yasushi; Edo, Masaharu; Denta, Toshio; Kawashima, Tetsuya; Ninomiya, Tamotsu

    In recent years, low output power CMOS DC-DC converters which integrate power stage MOSFETs and a PWM controller using CMOS process have been used in many mobile applications. In this paper, we propose the calculation method of CMOS DC-DC converter efficiency and report optimum design of CMOS DC-DC converter based on this method. By this method, converter efficiencies are directly calculated from converter specifications, dimensions of power stage MOSFET and device parameters. Therefore, this method can be used for optimization of CMOS DC-DC converter design, such as dimensions of power stage MOSFET and switching frequency. The efficiency calculated by the proposed method agrees well with the experimental results.

  20. CMOS digital intra-oral sensor for x-ray radiography

    NASA Astrophysics Data System (ADS)

    Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

    2011-03-01

    In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

  1. Integration of GMR-based spin torque oscillators and CMOS circuitry

    NASA Astrophysics Data System (ADS)

    Chen, Tingsu; Eklund, Anders; Sani, Sohrab; Rodriguez, Saul; Malm, B. Gunnar; Åkerman, Johan; Rusu, Ana

    2015-09-01

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  2. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.

    PubMed

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  3. An SEU-hardened CMOS data latch design

    SciTech Connect

    Rockett, L.R. Jr.

    1988-12-01

    A Single Event Upset (SEU)-hardened Complementary Metal-Oxide Semiconductor (CMOS) data latch design is described. The hardness is achieved by virtue of the latch design, thus no fabrication process or design groundrule development is required. Hardness is gained with comparatively little adverse impact on performance. Cyclotron tests provided hardness verification.

  4. Overcoming scaling concerns in a radiation-hardening CMOS technology

    SciTech Connect

    Maimon, J.; Haddad, N.

    1999-12-01

    Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.

  5. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  6. Thin Film on CMOS Active Pixel Sensor for Space Applications

    PubMed Central

    Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

    2008-01-01

    A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

  7. Spectrometer with CMOS demodulation of fiber optic Bragg grating sensors

    NASA Astrophysics Data System (ADS)

    Christiansen, Martin Brokner

    A CMOS imager based spectrometer is developed to interrogate a network containing a large number of Bragg grating sensors. The spectrometer uses a Prism-Grating- Prism (PGP) to spectrally separate serially multiplexed Bragg reflections on a single fiber. As a result, each Bragg grating produces a discrete spot on the CMOS imager that shifts horizontally as the Bragg grating experiences changes in strain or temperature. The reflected wavelength of the spot can be determined by finding the center of the spot produced. The use of a randomly addressable CMOS imager enables a flexible sampling rate. Some fibers can be interrogated at a high sampling rate while others can be interrogated at a low sampling rate. However, the use of a CMOS imager leads to several unique problems in terms of signal processing. These include a logarithmic pixel response, a low signal-to-noise ratio, a long pixel time constant, and software issues. The expected capabilities of the CMOS imager based spectrometer are determined with a theoretical model. The theoretical model tests three algorithms for determining the center of the spot: single row centroid, single row parabolic fit, and entire spot centroid. The theoretical results are compared to laboratory test data and field test data. The CMOS based spectrometer is capable of interrogating many optical fibers, and in the configuration tested, the fiber bundle consisted of 23 fibers. Using this system, a single fiber can be interrogated from 778 nm to 852 nm at 2100 Hz or multiple fibers can be interrogated over the same wavelength so that the total number of fiber interrogations is up to 2100 per second. The reflected Bragg wavelength can be determined within +/-3pm, corresponding to a +/-3μɛ uncertainty.

  8. Characterization of Depleted Monolithic Active Pixel detectors implemented with a high-resistive CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Rymaszewski, P.; Hirono, T.; Krüger, H.; Wermes, N.

    2016-07-01

    We present the recent development of DMAPS (Depleted Monolithic Active Pixel Sensor), implemented with a Toshiba 130 nm CMOS process. Unlike in the case of standard MAPS technologies which are based on an epi-layer, this process provides a high-resistive substrate that enables larger signal and faster charge collection by drift in a 50 - 300 μm thick depleted layer. Since this process also enables the use of deep n-wells to isolate the collection electrodes from the thin active device layer, NMOS and PMOS transistors are available for the readout electronics in each pixel cell. In order to characterize the technology, we implemented a simple three transistor readout with a variety of pixel pitches and input FET sizes. This layout variety gives us a clue on sensor characteristics for future optimization, such as the input detector capacitance or leakage current. In the initial measurement, the radiation spectra were obtained from 55Fe with an energy resolution of 770 eV (FWHM) and 90Sr with the MVP of 4165 e-.

  9. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  10. A novel multi-actuation CMOS RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  11. A novel colour-sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-10-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  12. Fully CMOS analog and digital SiPMs

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-03-01

    Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon-number resolving capability and immunity to magnetic fields. We present three families of analog SiPM fabricated in a reliable and cost-effective fully standard planar CMOS technology with a total photosensitive area of 1×1 mm2. These three families have different active areas with fill-factors (21%, 58.3%, 73.7%) comparable to those of commercial SiPM, which are developed in vertical (current flow) custom technologies. The peak photon detection efficiency in the near-UV tops at 38% (fill-factor included) comparable to commercial custom-process ones and dark count rate density is just a little higher than the best-in-class commercial analog SiPMs. Thanks to the CMOS processing, these new SiPMs can be integrated together with active components and electronics both within the microcell and on-chip, in order to act at the microcell level or to perform global pre-processing. We also report CMOS digital SiPMs in the same standard CMOS technology, based on microcells with digitalized processing, all integrated on-chip. This CMOS digital SiPMs has four 32×1 cells (128 microcells), each consisting of SPAD, active quenching circuit with adjustable dead time, digital control (to switch off noisy SPADs and readout position of detected photons), and fast trigger output signal. The achieved 20% fill-factor is still very good.

  13. Planar CMOS analog SiPMs: design, modeling, and characterization

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  14. A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

    NASA Astrophysics Data System (ADS)

    Rui, Guo; Haiying, Zhang

    2012-09-01

    A fully integrated multi-mode multi-band directed-conversion radio frequency (RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator (LO) switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface (SPI) module. The front-end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm2. The measured double-sideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.

  15. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    PubMed

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  16. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  17. CMOS self-powered monolithic light-direction sensor with digitalized output.

    PubMed

    Wang, Hongyi; Luo, Tao; Lu, Zhijian; Song, Hongjiang; Christen, Jennifer Blain

    2014-05-01

    We present a novel self-powered chip to detect the direction of incident light. This chip directly provides digitized output without the need of any off-chip power supply or optical or mechanical components. The chip was implemented in a standard 0.5 μm CMOS process. A microscale metal baffle was created by stacking all metal layers, contacts, and vias available in the process to produce on-chip shadowing. N-well/p+ photodiode arrays are located on both sides of the baffle to sense light. The photocurrent generated by a photodiode depends on the size of the photodiode and the shadowing. The shadowed area depends on the incident angle of the light. A current mirror circuit is used to compare the currents generated by the photodiodes on the opposite sides of the baffle and, consequently, provide a digital signal to indicate the incident light angle. Compared with the ideal linear digital light-angle detector with the same resolution, the presented sensor achieved the maximum error of only 2 deg over 110 deg test range. PMID:24784060

  18. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  19. CMOS output buffer wave shaper

    NASA Technical Reports Server (NTRS)

    Albertson, L.; Whitaker, S.; Merrell, R.

    1990-01-01

    As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

  20. CMOS image sensor with contour enhancement

    NASA Astrophysics Data System (ADS)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  1. Steps toward fabricating cryogenic CMOS compatible single electron devices for future qubits.

    SciTech Connect

    Wendt, Joel Robert; Childs, Kenton David; Ten Eyck, Gregory A.; Tracy, Lisa A.; Eng, Kevin; Stevens, Jeffrey; Nordberg, Eric; Carroll, Malcolm S.; Lilly, Michael Patrick

    2008-08-01

    We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 mum complementary metal oxide semiconductor (CMOS) process intended to operate at 100 mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2 K is presented.

  2. CMOS downsizing toward sub-10 nm

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2004-04-01

    Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation.

  3. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  4. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  5. A programmable second order oversampling CMOS sigma-delta analog-to-digital converter for low-power sensor interface electronics

    NASA Astrophysics Data System (ADS)

    Soundararajan, R.; Srivastava, A.; Xu, Y.

    2010-04-01

    A programmable second order oversampling sigma-delta analog-to-digital converter (ADC) is designed and fabricated in 0.5 μm n-well CMOS process for low-power interface electronics of a sensor node in wireless sensor networks. The sigma-delta ADC can be programmed to operate at three different oversampling ratios of 16, 32, and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor module. The major part of power is consumed in the decimator of the ADC by the integrators which operate at the highest sampling rate. Hence, an alternate design is introduced in the integrator stages by inserting sign extension coder circuits and reusing the same integrators for different resolutions and oversampling ratios. The programmable ADC can be interfaced with on or off-chip nanosensors for detection of traces of toxic gases and chemicals.

  6. Novel CMOS readout techniques for uncooled pyroelectric IR FPA

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Chin, Yuan-Lung; Chung, Wen-Yaw; Hsiung, Shen-Kan; Chou, Jung-Chuan

    1998-09-01

    Based on the application of the source follower per detector (SFD) input biasing technique, a new redout structure for the IR focal-plane-array (FPA), called the variable gain source follower per detector (VGSFD) is proposed and analyzed. The readout circuit of VGSFD of a unit cell of pyroelectric sensor under investigation, is composed of a source follower per detector circuit, high gain amplifier, and the reset switch. The VGSFD readout chip has been designed in 0.5 micrometers double-poly-double-metal n-well CMOS technology in various formats from 8 by 8 to 128 by 128. The experimental 8 by 8 VGSFD measurement results of the fabricated readout chip at room temperature have successfully verified both the readout function and performance. The high gain, low power, high sensitivity readout performances are achieved in a 50 by 50 micrometers (superscript 2) pixel size.

  7. Development of radiation hard CMOS active pixel sensors for HL-LHC

    NASA Astrophysics Data System (ADS)

    Pernegger, Heinz

    2016-07-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  8. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; French, M.; Manolopoulos, S.; Tyndel, M.; Allport, P.; Bates, R.; O'Shea, V.; Hall, G.; Raymond, M.

    2003-03-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to tape. Because of the large number of pixels, data reduction is needed on the sensor itself or just outside. This brings in stringent requirements on the temporal noise as well as to the sensor uniformity, expressed as a Fixed Pattern Noise (FPN). A pixel architecture with an additional transistor is proposed. This architecture, coupled to correlated double sampling of the signal will allow cancellation of the two dominant noise sources, namely the reset or kTC noise and the FPN. A prototype has been designed in a standard 0.25 μm CMOS technology. It has also a structure for electrical calibration of the sensor. The prototype is functional and detailed tests are under way.

  9. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  10. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  11. Biosensor system-on-a-chip including CMOS-based signal processing circuits and 64 carbon nanotube-based sensors for the detection of a neurotransmitter.

    PubMed

    Lee, Byung Yang; Seo, Sung Min; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cheon, Jun-Ho; Cho, Eunju; Lee, Hyunjoong; Chung, In-Young; Park, Young June; Kim, Suhwan; Hong, Seunghun

    2010-04-01

    We developed a carbon nanotube (CNT)-based biosensor system-on-a-chip (SoC) for the detection of a neurotransmitter. Here, 64 CNT-based sensors were integrated with silicon-based signal processing circuits in a single chip, which was made possible by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors. The chip was utilized to detect glutamate, a neurotransmitter, where ammonia, a byproduct of the enzymatic reaction of glutamate and glutamate oxidase on CNT-based sensors, modulated the conductance signals to the CNT-based sensors. This is a major technological advancement in the integration of CNT-based sensors with microelectronics, and this chip can be readily integrated with larger scale lab-on-a-chip (LoC) systems for various applications such as LoC systems for neural networks. PMID:20300676

  12. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  13. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  14. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    PubMed Central

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  15. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

  16. Improved Space Object Orbit Determination Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  17. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  18. A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

    PubMed

    Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

    2012-08-01

    An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes. PMID:23853178

  19. Fundamental performance differences between CMOS and CCD imagers: Part II

    NASA Astrophysics Data System (ADS)

    Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

    2007-09-01

    A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

  20. A fully integrated CMOS inverse sine circuit for computational systems

    NASA Astrophysics Data System (ADS)

    Seon, Jong-Kug

    2010-08-01

    An inverse trigonometric function generator using CMOS technology is presented and implemented. The development and synthesis of inverse trigonometric functional circuits based on the simple approximation equations are also introduced. The proposed inverse sine function generator has the infinite input range and can be used in many measurement and instrumentation systems. The nonlinearity of less than 2.8% for the entire input range of 0.5 Vp-p with a small-signal bandwidth of 3.2 MHz is achieved. The chip implemented in 0.25 μm CMOS process operates from a single 1.8 V supply. The measured power consumption and the active chip area of the inverse sine function circuit are 350 μW and 0.15 mm2, respectively.

  1. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  2. TID Simulation of Advanced CMOS Devices for Space Applications

    NASA Astrophysics Data System (ADS)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  3. A CMOS image sensor dedicated to medical gamma camera application

    NASA Astrophysics Data System (ADS)

    Salahuddin, Nur S.; Paindavoine, Michel; Ginhac, Dominique; Parmentier, Michel; Tamda, Najia

    2005-03-01

    Generally, medical Gamma Camera are based on the Anger principle. These cameras use a scintillator block coupled to a bulky array of photomultiplier tube (PMT). To simplify this, we designed a new integrated CMOS image sensor in order to replace bulky PMT photodetetors. We studied several photodiodes sensors including current mirror amplifiers. These photodiodes have been fabricated using a CMOS 0.6 micrometers process from Austria Mikro Systeme (AMS). Each sensor pixel in the array occupies respectively, 1mm x 1mm area, 0.5mm x 0.5mm area and 0.2mm 0.2mm area with fill factor 98 % and total chip area is 2 square millimeters. The sensor pixels show a logarithmic response in illumination and are capable of detecting very low green light emitting diode (less than 0.5 lux) . These results allow to use our sensor in new Gamma Camera solid-state concept.

  4. Diffuse reflectance measurements using lensless CMOS imaging chip

    NASA Astrophysics Data System (ADS)

    Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

    2014-10-01

    To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 μm thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

  5. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  6. A new CMOS-based digital imaging detector for applications in mammography

    NASA Astrophysics Data System (ADS)

    Baysal, Mehmet A.; Toker, Emre

    2005-09-01

    We have developed a CMOS-based x-ray imaging detector in the same form factor of a standard film cassette (18 cm × 24 cm) for Small Field-of-view Digital Mammography (SFDM) applications. This SFDM cassette is based on our three-side buttable, 25 mm × 50 mm, 48μm active-pixel CMOS sensor modules and utilizes a 150μm columnar CsI(Tl) scintillator. For imaging up to 100 mm × 100 mm field-of-view, a number of CMOS sensor modules need to be tiled and electronically synchronized together. By using fiber-optic communication, acquired images from the SFDM cassette can be transferred, processed and displayed on a review station within approximately 5 seconds of exposure, greatly enhancing patient flow. We present the physical performance of this CMOS-based SFDM cassette, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and more subjective criteria, by evaluating images from a phantom study and the clinical studies of our collaborators. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for digital mammography today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. The SFDM cassette can be employed in various mammography applications, including spot imaging, stereotactic biopsy imaging, core biopsy and surgical biopsy specimen radiography. This study demonstrates that all the image quality requirements for demanding mammography applications can be addressed with CMOS technology.

  7. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    PubMed Central

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, −1.9 and 6.5 pm V−1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  8. A CMOS TDI image sensor for Earth observation

    NASA Astrophysics Data System (ADS)

    Rushton, Joseph E.; Stefanov, Konstantin D.; Holland, Andrew D.; Endicott, James; Mayer, Frederic; Barbier, Frederic

    2015-09-01

    Time Delay and Integration (TDI) is used to increase the Signal to Noise Ratio (SNR) in image sensors when imaging fast moving objects. One important TDI application is in Earth observation from space. In order to operate in the space radiation environment, the effect that radiation damage has on the performance of the image sensors must be understood. This work looks at prototype TDI sensor pixel designs, produced by e2v technologies. The sensor is a CCD-like charge transfer device, allowing in-pixel charge summation, produced on a CMOS process. The use of a CMOS process allows potential advantages such as lower power consumption, smaller pixels, higher line rate and extra on-chip functionality which can simplify system design. CMOS also allows a dedicated output amplifier per column allowing fewer charge transfers and helping to facilitate higher line rates than CCDs. In this work the effect on the pixels of radiation damage from high energy protons, at doses relevant to a low Earth orbit mission, is presented. This includes the resulting changes in Charge Transfer inefficiency (CTI) and dark signal.

  9. Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays

    PubMed Central

    Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

    2009-01-01

    We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400×400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 μm × 30 μm. The devices exhibited sensitivity of 6.2 μC/Rcm2 with corresponding dark current of ∼2.7 nA/cm2, and a 80 μm FWHM planar image response to a 50 μm slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 μm spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 μm), fast readout speeds (8 fps for a 3200×3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

  10. Cryogenic CMOS circuits for single charge digital readout.

    SciTech Connect

    Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  11. Cryogenic CMOS circuits for single charge digital readout

    NASA Astrophysics Data System (ADS)

    Eng, Kevin; Gurrieri, T. M.; Hamlet, J.; Carroll, M. S.

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35μm CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to ˜120ns, while consuming ˜10μW. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  12. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    NASA Astrophysics Data System (ADS)

    Doll, Joseph C.; Petzold, Bryan C.; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L.

    2010-02-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, -1.9 and 6.5 pm V-1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

  13. CMOS-sensors for energy-resolved X-ray imaging

    NASA Astrophysics Data System (ADS)

    Doering, D.; Amar-Youcef, S.; Baudot, J.; Deveaux, M.; Dulinski, W.; Kachel, M.; Linnik, B.; Müntz, C.; Stroth, Joachim

    2016-01-01

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ``color sensitive" X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors.

  14. Radiation-hard silicon gate bulk CMOS cell family

    SciTech Connect

    Gibbon, C. F.; Habing, D. H.; Flores, R. S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved.

  15. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  16. Analysis of noise characteristics for the active pixels in CMOS image sensors for X-ray imaging

    NASA Astrophysics Data System (ADS)

    Kim, Young Soo; Cho, Gyuseong; Bae, Jun-Hyung

    2006-09-01

    CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal to noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs, and we performed experimental measurements and comparisons with theoretical estimations. To derive noise source of the pixels, we designed and fabricated four types of CMOS active pixels, and each pixel is composed of a photodiode and three MOS transistors. The size of these pixels is 100 μm×100 μm. The test chip was fabricated using ETRI 0.8 μm (2P/2M) standard CMOS process. It was found that the dominant noise in CMOS active pixels is shot noise during integration under normal operating conditions. And, it was also seen that epitaxial type pixels have similar noise level compared to non-epitaxial type, and the noise of diffusion type pixel is larger than for a well type pixel on the same substrate type.

  17. Flexible packaging and integration of CMOS IC with elastomeric microfluidics

    NASA Astrophysics Data System (ADS)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-05-01

    We have demonstrated flexible packaging and integration of CMOS IC chips with PDMS microfluidics. Microfluidic channels are used to deliver both liquid samples and liquid metals to the CMOS die. The liquid metals are used to realize electrical interconnects to the CMOS chip. As a demonstration we integrated a CMOS magnetic sensor die and matched PDMS microfluidic channels in a flexible package. The packaged system is fully functional under 3cm bending radius. The flexible integration of CMOS ICs with microfluidics enables previously unavailable flexible CMOS electronic systems with fluidic manipulation capabilities, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing.

  18. Multiband CMOS sensor simplify FPA design

    NASA Astrophysics Data System (ADS)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  19. A quasi-passive CMOS pipeline D/A converter

    NASA Technical Reports Server (NTRS)

    Wang, Fong-Jim; Temes, Gabor C.; Law, Simon

    1989-01-01

    A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.

  20. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  1. Simulation of SEU transients in CMOS ICs

    SciTech Connect

    Kaul, N.; Bhuva, B.L.; Kerns, S.E. )

    1991-12-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

  2. A high frame rate, 16 million pixels, radiation hard CMOS sensor

    NASA Astrophysics Data System (ADS)

    Guerrini, N.; Turchetta, R.; Van Hoften, G.; Henderson, R.; McMullan, G.; Faruqi, A. R.

    2011-03-01

    CMOS sensors provide the possibility of designing detectors for a large variety of applications with all the benefits and flexibility of the widely used CMOS process. In this paper we describe a novel CMOS sensor designed for transmission electron microscopy. The overall design consists of a large 61 × 63 mm2 silicon area containing 16 million pixels arranged in a 4K × 4K array, with radiation hard geometry. All this is combined with a very fast readout, the possibility of region of interest (ROI) readout, pixel binning with consequent frame rate increase and a dynamic range close to 12 bits. The high frame rate has been achieved using 32 parallel analogue outputs each one operating at up to 20 MHz. Binning of pixels can be controlled externally and the flexibility of the design allows several possibilities, such as 2 × 2 or 4 × 4 binning. Other binning configurations where the number of rows and the number of columns are not equal, such as 2 × 1 or 2 × 4, are also possible. Having control of the CMOS design allowed us to optimise the pixel design, in particular with regard to its radiation hardness, and to make optimum choices in the design of other regions of the final sensor. An early prototype was also designed with a variety of geometries in order to optimise the readout structure and these are presented. The sensor was manufactured in a 0.35 μm standard CMOS process.

  3. Deposition of titanium dioxide nanoparticles on the membrane of a CMOS-MEMS resonator

    NASA Astrophysics Data System (ADS)

    Ahmed, A. Y.; Dennis, J. O.; Khir, M. H. Md; Saad, M. N. Mohamad

    2014-10-01

    A CMOS-MEMS resonator is optimized as a highly sensitive gas sensor. The principle of detection is based on change in resonant frequency of the resonator due to adsorption/absorption of trace gases onto the active material on the resonator membrane. The resonator was successfully fabricated using 0.35 μm CMOS technology and post-CMOS micromachining process. The post-CMOS process is used to etch the silicon substrate and silicon oxide to release the suspended structures of the devices. Preliminary trials of nanocrystalline Titania paste (TiO2) was screen-printed on three aluminum plates of sizes 2mm × 2 mm. One of the samples was analysed as prepared while the other two samples were sintered at 300°C and 550°C, respectively. Physical observation indicated a change of the color for heated samples as compared to the unheated one. EDX results indicates a carbon (C) peak with average weight % of 18.816 in the as prepared sample and absence of the peaks for the samples sintered at 300°C and 550°C. EDX results also show that the TiO2 used consists of a uniform distribution of spherical shaped nanoparticles with a diameter of about 13.49 to 48.42 nm. Finally, the Titania paste was successfully deposit on the membrane of the CMOS-MEMS resonator for use as the gas sensitive membrane of the sensor.

  4. Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

    PubMed

    Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

    2016-02-01

    Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications. PMID:26780441

  5. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    NASA Astrophysics Data System (ADS)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  6. Total-dose and charge-trapping effects in gate oxides for CMOS LSI devices

    SciTech Connect

    Singh, R.S.; Kaputa, D.J.; Korman, C.S.; Surowiec, E.P.

    1984-12-01

    The effect of gamma irradiation on CMOS devices fabricated using 3 Micron CMOS BULK process has been studied as a function of gate oxide processing and subsequent annealing. Threshold shifts, speed degradation, and power supply currents were measured as a function of total dose up to 10/sup 6/ Rad (Si). Using hot electron injection techniques, trapping densities and capture cross-sections of the traps in each oxide type have been determined at pre- and post-irradiation levels. Power supply leakage and speed performance of the devices were recovered within three to five hours by annealing them at 125/sup 0/C, +10 V bias.

  7. Measurements on HV-CMOS active sensors after irradiation to HL-LHC fluences

    NASA Astrophysics Data System (ADS)

    Ristic, B.

    2015-04-01

    During the long shutdown (LS) 3 beginning 2022 the LHC will be upgraded for higher luminosities pushing the limits especially for the inner tracking detectors of the LHC experiments. In order to cope with the increased particle rate and radiation levels the ATLAS Inner Detector will be completely replaced by a purely silicon based one. Novel sensors based on HV-CMOS processes prove to be good candidates in terms of spatial resolution and radiation hardness. In this paper measurements conducted on prototypes built in the AMS H18 HV-CMOS process and irradiated to fluences of up to 2·1016 neq cm-2 are presented.

  8. A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Degerli, Y.; Guilloux, F.; Orsini, F.

    2014-05-01

    With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 μm CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

  9. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    NASA Astrophysics Data System (ADS)

    Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

    2013-09-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  10. A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application

    SciTech Connect

    Eaton, W.P.; Smith, J.H.

    1994-12-31

    A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

  11. Design of a CMOS-based multichannel integrated biosensor chip for bioelectronic interface with neurons.

    PubMed

    Zhang, Xin; Wong, Wai Man; Zhang, Yulong; Zhang, Yandong; Gao, Fei; Nelson, Richard D; Larue, John C

    2009-01-01

    In this paper we present the design and prototyping of a 24-channel mixed signal full-customized CMOS integrated biosensor chip for in vitro extracellular recording of neural signals. Design and implementation of hierarchical modules including microelectrode electrophysiological sensors, analog signal buffers, high gain amplifier and control/interface units are presented in detail. The prototype chip was fabricated by MOSIS with AMI C5 0.5 microm, double poly, triple metal layer CMOS technology. The electroless gold plating process is used to replace the aluminum material obtained from the standard CMOS process with biocompatible metal gold in the planner microelectrode array sensors to prevent cell poisoning and undesirable electrochemical corrosion. The biosensor chip provides a satisfactory signal-to-noise ratio for neural signals with amplitudes and frequencies within the range of 600microV - 2mV and 100 Hz to 10KHz, respectively. PMID:19965239

  12. Adiabatic circuits: converter for static CMOS signals

    NASA Astrophysics Data System (ADS)

    Fischer, J.; Amirante, E.; Bargagli-Stoffi, A.; Schmitt-Landsiedel, D.

    2003-05-01

    Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage. By means of adder structures designed for a 0.13µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

  13. Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

    PubMed

    Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

    2015-05-01

    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process. PMID:25782697

  14. Nanopore-CMOS Interfaces for DNA Sequencing.

    PubMed

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  15. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  16. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  17. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    NASA Technical Reports Server (NTRS)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  18. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    PubMed

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  19. Performance Analysis of Visible Light Communication Using CMOS Sensors

    PubMed Central

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  20. High total dose effects on CMOS/SOI technology

    SciTech Connect

    Flament, O.; Dupont-Nivet, E.; Leray, J.L.; Pere, J.F.; Delagnes, E. ); Auberton-Herve, A.J.; Giffard, B. ); Borel, G.; Ouisse, T. )

    1992-06-01

    This paper reports that, CMOS silicon on insulator technology has shown its ability to process hardened components which remain functional after irradiation with a total dose of several tens of Megarads. New tests on elementary transistors and 29101 microprocessor have been made at doses up to 100 Mrad (SiO{sub 2}) and above. Results of irradiation at these total doses are presented for different biases, together with the post-irradiation behavior of the components. All the observations show that new parameters must be taken into account for hardness insurance at a high level of total dose.

  1. Silicon nanowires integrated with CMOS circuits for biosensing application

    NASA Astrophysics Data System (ADS)

    Jayakumar, G.; Asadollahi, A.; Hellström, P.-E.; Garidis, K.; Östling, M.

    2014-08-01

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  2. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  3. A CMOS image sensor with stacked photodiodes for lensless observation system of digital enzyme-linked immunosorbent assay

    NASA Astrophysics Data System (ADS)

    Takehara, Hironari; Miyazawa, Kazuya; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Kim, Soo Hyeon; Iino, Ryota; Noji, Hiroyuki; Ohta, Jun

    2014-01-01

    A CMOS image sensor with stacked photodiodes was fabricated using 0.18 µm mixed signal CMOS process technology. Two photodiodes were stacked at the same position of each pixel of the CMOS image sensor. The stacked photodiodes consist of shallow high-concentration N-type layer (N+), P-type well (PW), deep N-type well (DNW), and P-type substrate (P-sub). PW and P-sub were shorted to ground. By monitoring the voltage of N+ and DNW individually, we can observe two monochromatic colors simultaneously without using any color filters. The CMOS image sensor is suitable for fluorescence imaging, especially contact imaging such as a lensless observation system of digital enzyme-linked immunosorbent assay (ELISA). Since the fluorescence increases with time in digital ELISA, it is possible to observe fluorescence accurately by calculating the difference from the initial relation between the pixel values for both photodiodes.

  4. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    PubMed

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process. PMID:27337723

  5. Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

    NASA Astrophysics Data System (ADS)

    Vilella, E.; Benoit, M.; Casanova, R.; Casse, G.; Ferrere, D.; Iacobucci, G.; Peric, I.; Vossebeld, J.

    2016-01-01

    HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article.

  6. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  7. Fast-moving target tracking system based on CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Miao, Zhun; Jiang, Jie; Zhang, Guangjun

    2008-10-01

    This paper introduces a fast-moving target tracking system based on CMOS (Complementary Metal-Oxygen Semiconductor) image sensor. A pipeline parallel architecture of region segmentation and first order moment algorithms on FPGA (Field Programmable Gate Array) platform enables driving the high frame rate CMOS image sensor and processing real-time images at the same time, extracting coordinates of the bright target spots in the high-rate consecutive image frames. In the end of this paper, an experiment proved that this system performs well in tracking fast-moving target in satisfying demand of speed and accuracy.

  8. Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

    PubMed Central

    Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

  9. Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor

    NASA Astrophysics Data System (ADS)

    Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

    2014-09-01

    A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35 μm CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35 dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 Ω-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10 kΩ, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

  10. Radiation Tolerance of 65nm CMOS Transistors

    DOE PAGESBeta

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  11. SEU hardening of CMOS memory circuit

    NASA Technical Reports Server (NTRS)

    Whitaker, S.; Canaris, J.; Liu, K.

    1990-01-01

    This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

  12. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  13. Low power SEU immune CMOS memory circuits

    NASA Technical Reports Server (NTRS)

    Liu, M. N.; Whitaker, Sterling

    1992-01-01

    The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

  14. A fail-safe CMOS logic gate

    NASA Technical Reports Server (NTRS)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  15. CMOS preamplifiers for detectors large and small

    SciTech Connect

    O`Connor, P.

    1997-12-31

    We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

  16. Low energy CMOS for space applications

    NASA Astrophysics Data System (ADS)

    Panwar, Ramesh; Alkalaj, Leon

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  17. Swap intensified WDR CMOS module for I2/LWIR fusion

    NASA Astrophysics Data System (ADS)

    Ni, Yang; Noguier, Vincent

    2015-05-01

    The combination of high resolution visible-near-infrared low light sensor and moderate resolution uncooled thermal sensor provides an efficient way for multi-task night vision. Tremendous progress has been made on uncooled thermal sensors (a-Si, VOx, etc.). It's possible to make a miniature uncooled thermal camera module in a tiny 1cm3 cube with <1W power consumption. For silicon based solid-state low light CCD/CMOS sensors have observed also a constant progress in terms of readout noise, dark current, resolution and frame rate. In contrast to thermal sensing which is intrinsic day&night operational, the silicon based solid-state sensors are not yet capable to do the night vision performance required by defense and critical surveillance applications. Readout noise, dark current are 2 major obstacles. The low dynamic range at high sensitivity mode of silicon sensors is also an important limiting factor, which leads to recognition failure due to local or global saturations & blooming. In this context, the image intensifier based solution is still attractive for the following reasons: 1) high gain and ultra-low dark current; 2) wide dynamic range and 3) ultra-low power consumption. With high electron gain and ultra low dark current of image intensifier, the only requirement on the silicon image pickup device are resolution, dynamic range and power consumption. In this paper, we present a SWAP intensified Wide Dynamic Range CMOS module for night vision applications, especially for I2/LWIR fusion. This module is based on a dedicated CMOS image sensor using solar-cell mode photodiode logarithmic pixel design which covers a huge dynamic range (> 140dB) without saturation and blooming. The ultra-wide dynamic range image from this new generation logarithmic sensor can be used directly without any image processing and provide an instant light accommodation. The complete module is slightly bigger than a simple ANVIS format I2 tube with <500mW power consumption.

  18. A 64 single photon avalanche diode array in 0.18 µm CMOS standard technology with versatile quenching circuit for quick prototyping

    NASA Astrophysics Data System (ADS)

    Uhring, Wilfried; Le Normand, Jean-Pierre; Zint, Virginie; Dumas, Norbert; Dadouche, Foudil; Malasse, Imane; Scholz, Jeremy

    2012-04-01

    Several works have demonstrated the successfully integration of Single-photon avalanche photodiodes (SPADs) operating in Geiger mode in a standard CMOS circuit for the last 10 years. These devices offer an exceptional temporal resolution as well as a very good optical sensitivity. Nevertheless, it is difficult to predict the expected performances of such a device. Indeed, for a similar structure of SPAD, some parameter values can differ by two orders of magnitude from a technology to another. We proposed here a procedure to identify in just one or two runs the optimal structure of SPAD available for a given technology. A circuit with an array of 64 SPAD has been realized in the Tower-Jazz 0.18 μm CMOS image sensor process. It encompasses an array of 8 different structures of SPAD reproduced in 8 diameters in the range from 5 μm up to 40 μm. According to the SPAD structures, efficient shallow trench insulator and/or P-Well guard ring are used for preventing edge breakdown. Low dark count rate of about 100 Hz are expected thanks to the use of buried n-well layer and a high resistivity substrate. Each photodiode is embedded in a pixel which includes a versatile quenching circuitry and an analog output of its cathode voltage. The quenching system is configurable in four operation modes; the SPAD is disabled, the quenching is completely passive, the reset of the photodiode is active and the quenching is fully active. The architecture of the array makes possible the characterization of every single photodiode individually. The parameters to be measured for a SPAD are the breakdown avalanche voltage, the dark count rate, the dead time, the timing jitter, the photon detection probability and the after-pulsing rate.

  19. Strained SOI/SGOI dual-channel CMOS technology based on the Ge condensation technique

    NASA Astrophysics Data System (ADS)

    Tezuka, Tsutomu; Nakaharai, Shu; Moriyama, Yoshihiko; Hirashita, Norio; Toyoda, Eiji; Numata, Toshinori; Irisawa, Toshifumi; Usuda, Koji; Sugiyama, Naoharu; Mizuno, Tomohisa; Takagi, Shin-ichi

    2007-01-01

    Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs were fabricated by oxidizing strained SiGe layers on SOI substrates at high temperatures. It was found that strain was accumulated in the SGOI channels during this process, called Ge condensation, associated with the increase in the Ge fraction. Significant hole-mobility enhancements up to a factor of 10 were observed due to the high Ge fractions over 0.5 and large strain values over 1%. The SGOI pMOSFETs were also co-integrated with strained SOI nMOSFETs or ultra-thin SOI nMOSFETs to form dual-channel CMOS devices. The dual-channel structures were fabricated by conventional CMOS processes combined with the Ge condensation process and selective epitaxial growth processes. High hole mobility was observed in the SGOI pMOSFETs of the CMOS devices, whereas an enhancement or no degradation of electron mobility was observed in the strained or the unstrained SOI nMOSFETs. Based on the measured carrier mobility of the long-channel nMOSFETs and pMOSFETs, short-channel CMOS performance enhancement of around 30% was estimated.

  20. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  1. 3D integration of sub-surface photonics with CMOS

    NASA Astrophysics Data System (ADS)

    Jalali, Bahram; Indukuri, Tejaswi; Koonath, Prakash

    2006-02-01

    The integration of photonics and electronics on a single silicon substrate requires technologies that can add optical functionalities without significantly sacrificing valuable wafer area. To this end, we have developed an innovative fabrication process, called SIMOX 3-D Sculpting, that enables monolithic optoelectronic integration in a manner that does not compromise the economics of CMOS manufacturing. In this technique, photonic devices are realized in subsurface silicon layers that are separated from the surface silicon layer by an intervening SiO II layer. The surface silicon layer may then be utilized for electronic circuitry. SIMOX 3-D sculpting involves (1) the implantation of oxygen ions into a patterned silicon substrate followed by (2) high temperature anneal to create buried waveguide-based photonic devices. This process has produced subterranean microresonators with unloaded quality factors of 8000 and extinction ratios >20dB. On the surface silicon layers, MOS transistor structures have been fabricated. The small cross-sectional area of the waveguides lends itself to the realization of nonlinear optical devices. We have previously demonstrated spectral broadening and continuum generation in silicon waveguides utilizing Kerr optical nonlinearity. This may be combined with microresonator filters for on-chip supercontiuum generation and spectral carving. The monolithic integration of CMOS circuits and optical modulators with such multi-wavelength sources represent an exciting avenue for silicon photonics.

  2. Smart CMOS image sensor for lightning detection and imaging.

    PubMed

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

  3. Scanning probe lithography approach for beyond CMOS devices

    NASA Astrophysics Data System (ADS)

    Durrani, Zahid; Jones, Mervyn; Kaestner, Marcus; Hofer, Manuel; Guliyev, Elshad; Ahmad, Ahmad; Ivanov, Tzvetan; Zoellner, Jens-Peter; Rangelow, Ivo W.

    2013-03-01

    As present CMOS devices approach technological and physical limits at the sub-10 nm scale, a `beyond CMOS' information-processing technology is necessary for timescales beyond the semiconductor technology roadmap. This requires new approaches to logic and memory devices, and to associated lithographic processes. At the sub-5 nm scale, a technology platform based on a combination of high-resolution scanning probe lithography (SPL) and nano-imprint lithography (NIL) is regarded as a promising candidate for both resolution and high throughput production. The practical application of quantum-effect devices, such as room temperature single-electron and quantum-dot devices, then becomes feasible. This paper considers lithographic and device approaches to such a `single nanometer manufacturing' technology. We consider the application of scanning probes, capable of imaging, probing of material properties and lithography at the single nanometer scale. Modified scanning probes are used to pattern molecular glass based resist materials, where the small particle size (<1 nm) and mono-disperse nature leads to more uniform and smaller lithographic pixel size. We also review the current status of single-electron and quantum dot devices capable of room-temperature operation, and discuss the requirements for these devices with regards to practical application.

  4. A CMOS active pixel sensor for retinal stimulation

    NASA Astrophysics Data System (ADS)

    Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

    2006-02-01

    Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

  5. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  6. A Low-Cost CMOS Programmable Temperature Switch

    PubMed Central

    Li, Yunlong; Wu, Nanjian

    2008-01-01

    A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  7. Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS

    NASA Astrophysics Data System (ADS)

    Ressejac, Isabelle

    The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length ˜1000 mum and width ˜150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only ˜1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height

  8. Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

    NASA Astrophysics Data System (ADS)

    Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

    2014-03-01

    We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

  9. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  10. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    PubMed Central

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  11. Design and fabrication of a CMOS-compatible MHP gas sensor

    SciTech Connect

    Li, Ying; Yu, Jun Wu, Hao; Tang, Zhenan

    2014-03-15

    A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  12. Performance comparison of CMOS-based photodiodes for high-resolution and high-sensitivity digital mammography

    NASA Astrophysics Data System (ADS)

    Bae, J. H.; Cho, M.; Kim, M. S.; Lee, D. H.; Cho, G.

    2011-12-01

    In order to develop a high-resolution and high-sensitivity digital mamographic detector, to use a commercially-available and well-developed CMOS image sensor (CIS) process can be a cost-effective way. However, in any commercial CIS process, several different types of n- or p-layers can be used so that various pn-junction structures could be formed depending on the choice of n- and p-layer combination. We performed a comparative analysis on the characteristics of three types of photodiodes formed on a high-resistivity p-type epitaxial wafer by applying three available n-layer processes in order to develop the high-sensitivity photodiode for a scintillator-based X-ray imaging detector. As a preliminar study, a small test-version CIS chip with an 80 × 80 pixel array of a 3-transistor active pixel sensor structure, 50 μm pitch and 80{%} fill factor was fabricated. The pixel area is subdivided into four 40 × 40 sub-arrays and 3 different types of photodides are designed for each sub-array by using n+, n- and n-well layers. All other components are designed to be identical for impartial comparison of the photodiodes only. Among 3 types, the n-/p-epi photodiode exhibited high charge-to-voltage gain (0.86 μV/e-), high quantum efficiency (49% at 532 nm wavelength) and low dark current (294 pA/cm2). The test CIS chip was coupled to a phosphor screen, Lanex Fine or Lanex Regular, both composed of Gd2O2S:Tb, and was tested using X-rays in a mammography setting. Among 6 cases, n-/p-epi photodiode coupled with the Lanex Regular also showed the highest sensitivity of 30.5 mV/mR.

  13. Failure analysis of a half-micron CMOS IC technology

    SciTech Connect

    Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S.

    1996-08-01

    We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

  14. Development of a low power Delay-Locked Loop in two 130 nm CMOS technologies

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moron, J.; Swientek, K.

    2016-02-01

    The design and measurement results of two low power DLL prototypes for applications in particle physics readout systems are presented. The DLLs were fabricated in two different 130 nm CMOS technologies, called process A and process B, giving the opportunity to compare these two CMOS processes. Both circuits generate 64 uniform clock phases and operate at similar frequency range, from 20 MHz up to 60 MHz (10 MHz - 90 MHz in process B). The period jitter of both DLLs is in the range 2.5 ps - 12.1 ps (RMS) and depends on the selected output phase. The complete DLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption of around 0.7 mW at typical 40 MHz input. The DLL prototype, designed in process A, occupies 680 μm × 210 μm, while the same circuit designed in process B occupies 430 μm × 190 μm.

  15. Further developments on a novel color sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-05-01

    The Transverse Field Detector (TFD) is a recently proposed Silicon pixel device designed to perform color imaging without the use of color filters. The color detection principle is based on the dependence of the Silicon absorption coefficient from the wavelength and relies on the generation of a suitable transverse electric field configuration, within the semiconductor active layer, to drive photocarriers generated at different depths towards different collecting electrodes. Each electrode has in this way a different spectral response with respect to the incoming wavelength. Pixels with three or four different spectral responses can be implemented within ~ 6 μm of pixel dimension. Thanks to the compatibility with standard triple well CMOS processes, the TFD can be used in an Active Pixel Sensor exploiting a dedicated readout topology, based on a single transistor charge amplifier. The overall APS electronics includes five transistors (5T) and a feedback capacitance, with a resulting overall fill factor around 50%. In this work the three colors and four colors TFD pixel simulations and implementations in a 90 nm standard CMOS triple well technology are described. Details on the design of a TFD APS mini matrix are provided and preliminary experimental results on four colors pixels are presented.

  16. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 μA. PMID:25230305

  17. Single donor electronics and quantum functionalities with advanced CMOS technology.

    PubMed

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-16

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature. PMID:26871255

  18. CMOS-TDI detector technology for reconnaissance application

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  19. Reliability issue on pipeline defects in CMOS memory devices

    NASA Astrophysics Data System (ADS)

    Youn, So; Terrell, Kyle; Wu, Chau-Chin; Shy, Paul; Lien, Chuen-Der

    1996-09-01

    Pipeline defects have recently been reported in a leakage source of CMOS devices when die shrink. We report the observed physical defects which shorted source and drain under .6 u short channel CMOS devices by the Wright-etching of the defective devices. We also found pipeline defects filled with phosphorous doped n-type material by the cross- sectioning of the pipeline in the channel of NMOS transistor. We also observed that devices are failing during high temperature reliability test, which causes single bit failure. This indicates that there are many potential defective die to reach assembly process even though most of detectives are discarded at wafer sort. SEM analysis identifies that location of defective parts is decorated with a pair of protruding holes at the 90 degree corner of field island of faulty pass-gate of SRAM. These pipeline defects are caused mainly by the compressed stress from field oxide. Reliability and yield have been improved since the pipeline were minimized after relieving stress on pass- gate.

  20. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

  1. Single donor electronics and quantum functionalities with advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-01

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  2. CMOS low data rate imaging method based on compressed sensing

    NASA Astrophysics Data System (ADS)

    Xiao, Long-long; Liu, Kun; Han, Da-peng

    2012-07-01

    Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

  3. High-stage analog accumulator for TDI CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  4. CMOS mm-wave transceivers for Gbps wireless communication

    NASA Astrophysics Data System (ADS)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  5. A CMOS Imager with Focal Plane Compression using Predictive Coding

    NASA Technical Reports Server (NTRS)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  6. Evaluation of a CMOS image detector for low-cost and power medical x-ray imaging applications

    NASA Astrophysics Data System (ADS)

    Smith, Scott T.; Bednarek, Daniel R.; Wobschall, Darold C.; Jeong, Myoungki; Kim, Hyunkeun; Rudin, Stephen

    1999-05-01

    Recent developments in CMOS image detectors are changing the way digital imaging is performed for many applications. The replacement of charge coupled devices (CCDs), with CMOS detectors is a desirable paradigm shift that will depend on the ability to match the high performance characteristics of CCDs. Digital X-ray imaging applications (chest X-ray, mammography) would benefit greatly from this shift because CMOS detectors have the following inherent characteristics: (1) Low operating power (5 - 10 times lower than CCD/processing electronics). (2) Standard CMOS manufacturing process (CCD requires special manufacturing). (3) On-chip integration of analog/digital processing functions (difficult with CCD). (4) Low Cost (5 - 10 times lower cost than CCD). The achievement of both low cost and low power is highly desirable for portable applications as well as situations where large, expensive X-ray imaging machines are not feasible (small hospitals and clinics, emergency medical vehicles, remote sites). Achieving this goal using commercially available components would allow rapid development of such digital X-ray systems as compared with the development difficulties incurred through specialized direct detectors and systems. The focus of this paper is to evaluate a CMOS image detector for medical X-ray applications and to demonstrate the results obtained from a prototype CMOS digital X-ray camera. Results from the images collected from this optically-coupled camera are presented for a particular lens, X-ray conversion screen, and demagnification factor. Further, an overview of the overall power consumption and cost of a multi-sensor CMOS mosaic compared to its CCD counterpart are also reported.

  7. Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies

    NASA Astrophysics Data System (ADS)

    Garcia, Jose C.; Montiel-Nelson, Juan A.; Sosa, Javier; Navarro, Hector; Sarmiento, Roberto

    2003-04-01

    A new transient macromodel for the cells used in DCFL GaAs and CMOS digital design is introduced in this paper. The numerical solution determines accurate propagation delay times. The macromodel is based on the differential equation for the output voltage in terms of currents and capacitances. An straightforward treatment of the differential equation for an inverter in DCFL GaAs and CMOS has been obtained. It could be resolved numerically by a 4th order Runge Kutta method. Good agreement is obtained between the HSPICE simulation and the computation of the propagation delays for DCFL GaAs and CMOS basic gates: INV, NOR, OR and NAND. There is no error between HSPICE and our computation of propagation delay time for the high to low (tphl) and low to high (tplh) transitions. The propagation delay times for two types of transition were measured and compared with HSPICE. The results demonstrate that our approach matches with HSPICE with no error. The numerical method was programmed in C language. In addition, computation time analysis is provided and numerical solution is several orders of magnitude faster than HSPICE. Work is in progress to obtain the macromodel of a standard cell library for digital application both for a 0.6 microns E/D GaAs process (H-GaAsIV) from Vitesse Semiconductor and for a 0.18 microns logic/mixed-signal CMOS process (1P6M) from TSMC Corp.

  8. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  9. Noise in a CMOS digital pixel sensor

    NASA Astrophysics Data System (ADS)

    Chi, Zhang; Suying, Yao; Jiangtao, Xu

    2011-11-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.

  10. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  11. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  12. CMOS-array design-automation techniques

    NASA Technical Reports Server (NTRS)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  13. Radiation effects on scientific CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Liyan, Liu; Xiaohui, Liu; Xiaofeng, Jin; Xiang, Li

    2015-11-01

    A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to 110 MeV·cm2/mg.

  14. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    NASA Astrophysics Data System (ADS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-11-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus™ X-ray machine, two scintillators of Lanex™ Fine and Regular, and two CMOS APS array of RadEye™ were used under the conditions of 50 kV p/1 mAs and 100 kV p/1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS.

  15. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

  16. CMOS-controlled rapidly tunable photodetectors

    NASA Astrophysics Data System (ADS)

    Chen, Ray

    With rapidly increasing data bandwidth demands, wavelength-division-multiplexing (WDM) optical access networks seem unavoidable in the near future. To operate WDM optical networks in an efficient scheme, wavelength reconfigurability and scalability of the network are crucial. Unfortunately, most of the existing wavelength tunable technologies are neither rapidly tunable nor spectrally programmable. This dissertation presents a tunable photodetector that is designed for dynamic-wavelength allocation WDM network environments. The wavelength tuning mechanism is completely different from existing technologies. The spectrum of this detector is programmable through low-voltage digital patterns. Since the wavelength selection is achieved by electronic means, the device wavelength reconfiguration time is as fast as the electronic switching time. In this dissertation work, we have demonstrated a tunable detector that is hybridly integrated with its customized CMOS driver and receiver with nanosecond wavelength reconfiguration time. In addition to its nanosecond wavelength reconfiguration time, the spectrum of this detector is digitally programmable, which means that it can adapt to system changes without re-fabrication. We have theoretically developed and experimentally demonstrated two device operating algorithms based on the same orthogonal device-optics basis. Both the rapid wavelength tuning time and the scalability make this novel device very viable for new reconfigurable WDM networks. By taking advantage of CMOS circuit design, this detector concept can be further extended for simultaneous multiple wavelength detection. We have developed one possible chip architecture and have designed a CMOS tunable optical demux for simultaneous controllable two-wavelength detection.

  17. Efficient design of CMOS TSC checkers

    NASA Technical Reports Server (NTRS)

    Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

    1990-01-01

    This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

  18. Correct CMOS IC defect models for quality testing

    NASA Technical Reports Server (NTRS)

    Soden, Jerry M.; Hawkins, Charles F.

    1993-01-01

    Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

  19. Behavior of faulty double BJT BiCMOS logic gates

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  20. A radiation hardened SONOS/CMOS EEPROM family

    SciTech Connect

    Klein, V.F.; Wood, G.M.; Buller, J.F. . Semiconductor Sector); Murray, J.R.; Rodriquez, J.L. )

    1990-01-01

    There has long been a need for fast read nonvolatile, rad hard memories for military and space applications. Recent advances in EEPROM technology now allow this need to be met for many applications. Harris/Sandia have developed a 16k and a 256k rad hard EEPROM. The EEPROMs utilize a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory transistor integrated into a 2 {mu}m, rad hard two level metal CMOS process. Both the 16k and the 256k parts have been designed to interface with the Intel 8085 or 80C51 and National 32000 series microprocessors and feature page and block clear modes. Both parts are functionally identical, and are produced by the same fabrication process. They are also pin for pin compatible with each other, except for the extra address and ground pins on the 256k. This paper describes the characteristics of this EEPROM family. 1 ref.

  1. A radiation hardened SONOS/CMOS EEPROM family

    NASA Astrophysics Data System (ADS)

    Klein, V. F.; Wood, G. M.; Buller, J. F.; Murray, J. R.; Rodriquez, J. L.

    1990-07-01

    There has long been a need for fast read nonvolatile, rad hard memories for military and space applications. Recent advances in Electrically Erasably Programmable Read Only Memory (EEPROM) technology now allow this need to be met for many applications. Harris/Sandia have developed a 16k and a 256k rad hard EEPROM. The EEPROMs utilize a Silicon Oxide Nitride Oxide Silicon (SONOS) memory transistor integrated into a 2 microns rad hard two level metal CMOS process. Both the 16k and the 256k parts were designed to interface with the Intel 8085 or 80C51 and National 32000 series microprocessors and feature page and block clear modes. Both parts are functionally identical, and are produced by the same fabrication process. They are also pin for pin compatible with each other, except for the extra address and ground pins on the 256k. The characteristics of this EEPROM family are described.

  2. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    NASA Astrophysics Data System (ADS)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  3. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

    PubMed

    Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented. PMID:27104122

  4. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

    2013-08-01

    This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

  5. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    PubMed

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices. PMID:27302586

  6. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    NASA Astrophysics Data System (ADS)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 μm 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 kΩ under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of  -117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  7. CMOS VCSEL driver circuit for 25+Gbps/channel short-reach parallel optical links

    NASA Astrophysics Data System (ADS)

    Shibata, Masumi

    This thesis proposes a new CMOS driver for Vertical Cavity Surface Emitting LASER (VCSEL) diode arrays. A VCSEL is a promising light source for optical communication. However, its threshold voltage (1.5V for a 850-nm VCSEL) exceeds the rated supply voltage of nanoscale CMOS technologies. This makes difficult designing a driver sourcing a modulated current to a VCSELs anode directly, an arrangement suitable for low-cost parallel optical links. To overcome this problem, a combination of analog circuit techniques is proposed including a novel pad shield driving technique. A prototype fabricated in a 65-nm CMOS technology achieved 26-Gb/s bit-rate and 1.80-pJ/b power efficiency with an optical modulation amplitude (OMA) of +1.8dBm and 3.1ps-rms jitter when driving a 850-nm 14Gb/s commercial VCSEL. This is the highest-speed anode-driving CMOS VCSEL driver reported to date. Also it has the best power efficiency and the smallest area (0:024 mm2) amongst anode-driving drivers in any process technology.

  8. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 μm 1 Poly 4 Metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  9. Single-Photon Avalanche Diodes (SPAD) in CMOS 0.35 μm technology

    NASA Astrophysics Data System (ADS)

    Pellion, D.; Jradi, K.; Brochard, N.; Prêle, D.; Ginhac, D.

    2015-07-01

    Some decades ago single photon detection used to be the terrain of photomultiplier tube (PMT), thanks to its characteristics of sensitivity and speed. However, PMT has several disadvantages such as low quantum efficiency, overall dimensions, and cost, making them unsuitable for compact design of integrated systems. So, the past decade has seen a dramatic increase in interest in new integrated single-photon detectors called Single-Photon Avalanche Diodes (SPAD) or Geiger-mode APD. SPAD are working in avalanche mode above the breakdown level. When an incident photon is captured, a very fast avalanche is triggered, generating an easily detectable current pulse. This paper discusses SPAD detectors fabricated in a standard CMOS technology featuring both single-photon sensitivity, and excellent timing resolution, while guaranteeing a high integration. In this work, we investigate the design of SPAD detectors using the AMS 0.35 μm CMOS Opto technology. Indeed, such standard CMOS technology allows producing large surface (few mm2) of single photon sensitive detectors. Moreover, SPAD in CMOS technologies could be associated to electronic readout such as active quenching, digital to analog converter, memories and any specific processing required to build efficient calorimeters1

  10. Electroabsorption modulators for CMOS compatible optical interconnects in III-V and group IV materials

    NASA Astrophysics Data System (ADS)

    Roth, Jonathan Edgar

    While electrical systems excel at information processing, photonics is useful in systems for high-bandwidth, low-loss signal transmission. As photonics technology has become increasingly widespread and has been deployed at shorter distance scales than traditional long-haul networks, it has become important to efficiently integrate photonics components with electrical integrated circuits. Optoelectronic modulators used as transmitters are an important class of device for use in optical interconnects. Many optoelectronic modulator designs use waveguides. Coupling light into waveguides requires a difficult alignment step. This dissertation will describe a number of optoelectronic modulators that do not have the tight alignment constraints associated with waveguide-based modulators. The eased alignment constraints may be important for the practical manufacturing and packaging of systems using optical interconnects. Most currently deployed photonics technologies also use substrates other than silicon and materials incompatible with CMOS manufacturing. Recently we discovered a strong quantum-confined Stark effect in Ge/SiGe quantum well structures that can be used to create efficient optoelectronic modulators on silicon substrates. Optoelectronic modulators using this technology can be fabricated with conventional CMOS foundry processes, possibly on the same chips as CMOS circuits. In this dissertation, an optical interconnect operating in the C-band will be presented. We believe this is the first such device employing an optical transmitter flip-chip bonded to silicon CMOS. A number of novel modulators will be presented, which are fabricated on silicon substrates, and employ Ge/SiGe quantum well structures. These modulators include a novel architecture known as the side-entry modulator, which is designed for monolithic integration with electronics. One side-entry modulator achieved over 3 dB of contrast in the telecommunications C-band for a voltage swing of 1V. Such a

  11. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    PubMed Central

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  12. An 8.12 μW wavelet denoising chip for PPG detection and portable heart rate monitoring in 0.18 μm CMOS

    NASA Astrophysics Data System (ADS)

    Xiang, Li; Xu, Zhang; Peng, Li; Xiaohui, Hu; Hongda, Chen

    2016-05-01

    A low power wavelet denoising chip for photoplethysmography (PPG) detection and portable heart rate monitoring is presented. To eliminate noise and improve detection accuracy, Harr wavelet (HWT) is chosen as the processing tool. An optimized finite impulse response structure is proposed to lower the computational complexity of proposed algorithm, which is benefit for reducing the power consumption of proposed chip. The modulus maxima pair location module is design to accurately locate the PPG peaks. A clock control unit is designed to further reduce the power consumption of the proposed chip. Fabricated with the 0.18 μm N-well CMOS 1P6M technology, the power consumption of proposed chip is only 8.12 μW in 1 V voltage supply. Validated with PPG signals in multiparameter intelligent monitoring in intensive care databases and signals acquired by the wrist photoelectric volume detection front end, the proposed chip can accurately detect PPG signals. The average sensitivity and positive prediction are 99.91% and 100%, respectively.

  13. Ultra low power CMOS technology

    NASA Technical Reports Server (NTRS)

    Burr, J.; Peterson, A.

    1991-01-01

    This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

  14. Novel CMOS electron imaging sensor

    NASA Astrophysics Data System (ADS)

    Finkelstein, Hod; Ginosar, Ran

    1998-09-01

    Electron detector arrays are employed in numerous imaging applications, from low-light-light-level imaging to astronomy, electron microscopy, and nuclear instrumentation. The majority of these detectors are fabricated with dedicated processes, use the semiconductor as a stopping and detecting layer, and utilize CCD-type charge transfer and detection. We present a new detector, wherein electrons are stopped by an exposed metal layer, and are subsequently detected either through charge collection in a CCD-type well, or by a measurement of a potential drop across a capacitor which is discharged by these electrons. Spatial localization is achieved by use of two metal planes, one for protecting the underlying gate structures, and another, with metal pixel structures, for 2D detection. The new device does not suffer from semiconductor non-uniformities, and blooming effects are minimized. It is effective for electrons with energies of 2-6 keV. The unique structure makes it possible to achieve a high fill factor, and to incorporate on-chip processing. An imaging chip implementing several test structures incorporating the new detector has been fabricated using a 2 micron double-poly double-metal process, and tested inside a JEOL 640 electron microscope.

  15. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor.

    PubMed

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P Glenn; Maxwell, Karen L

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  16. A new visible watermarking technique applied to CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yu, Pingping; Shang, Yan; Li, Chunming

    2013-10-01

    This paper presents a new visible watermarking solution for CMOS image sensor which can enhance secure features of captured images. Visible watermarks are embedded in the Bayer format image data and can be transferred by the subsequent interpolation process. A piecewise function is setup based on the gray scale resolution characteristics of human eyes. Watermark stretch factor can be adaptively chosen according to the gray value of the current pixel. The advantage of this algorithm is that the watermark has the same visibility in different image brightness region. A number of color images have been used to test the method. In order to check the robustness of watermarked images, we conducted adding noise and filtering experiments, results show that the visibility of watermark is also good after the experiments. The approach allows a digital watermark to be embedded in an image immediately upon its capture, before leaving the imaging chip.

  17. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  18. Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  19. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  20. A New CMOS Read-out IC for Uncooled Microbolometer Infrared Image Sensor

    NASA Astrophysics Data System (ADS)

    Hwang, Sang Joon; Shin, Ho Hyun; Sung, Man Young

    2008-10-01

    An uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems (MEMS) process, so the value of the microbolometer resistor has a process variation. Also, the reference resistor, which is used to connect to the microbolometer, is fabricated by a standard CMOS process, and the difference between the values of the microbolometer resistor and the reference resistor generates an unwanted output signal for the same input from the sensor array. In order to minimize this problem, a new CMOS read-out integrated circuit (ROIC) was designed. Instead of a single input mode, a differential input mode scheme and a simple method to compensate the resistor value are proposed. Using results from a computer simulation, it is observed that the output characteristic of the ROIC was improved and the effect of the process variation was decreased without using complex compensation circuits. Based on the simulation results, a prototype device including an ROIC that was fabricated by a standard 0.25um CMOS process and a microbolometer with a 16 x 16 sensor array was fabricated and characterized.

  1. CMOS-compatible RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lakamraju, Narendra V.; Kim, Bruce; Phillips, Stephen M.

    2004-08-01

    Mobile technologies have relied on RF switches for a long time. Though the basic function of the switch has remained the same, the way they have been made has changed in the recent past. In the past few years work has been done to use MEMS technologies in designing and fabricating an RF switch that would in many ways replace the electronic and mechanical switches that have been used for so long. The work that is described here is an attempt to design and fabricate an RF MEMS switch that can handle higher RF power and have CMOS compatible operating voltages.

  2. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  3. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  4. A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device.

    PubMed

    Lee, Myung-Jae; Sun, Pengfei; Charbon, Edoardo

    2015-05-18

    This paper reports on the first implementation of a single-photon avalanche diode (SPAD) in standard silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The SPAD is realized in a circular shape, and it is based on a P(+)/N-well junction along with a P-well guard-ring structure formed by lateral diffusion of two closely spaced N-well regions. The SPAD electric-field profile is analyzed by means of simulation to predict the breakdown voltage and the effectiveness of premature edge breakdown. Measurements confirm these predictions and also provide a complete characterization of the device, including current-voltage characteristics, dark count rate (DCR), photon detection probability (PDP), afterpulsing probability, and photon timing jitter. The SOI CMOS SPAD has a PDP above 25% at 490-nm wavelength and, thanks to built-in optical sensitivity enhancement mechanisms, it is as high as 7.7% at 850-nm wavelength. The DCR is 244 Hz/μm2, and the afterpulsing probability is less than 0.1% for a dead time longer than 200 ns. The SPAD exhibits a timing response without exponential tail and provides a remarkable timing jitter of 65 ps (FWHM). The new device is well suited to operate in backside illumination within complex three-dimensional (3D) integrated circuits, thus contributing to a great improvement of fill factor and jitter uniformity in large arrays. PMID:26074572

  5. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  6. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  7. Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

    NASA Technical Reports Server (NTRS)

    Cable, J. S.; Carter, J. R.; Witteles, A. A.

    1986-01-01

    Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

  8. Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project.

    NASA Astrophysics Data System (ADS)

    Huffman, B. T.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hoeferkamp, M.; Hommels, L. B. A.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, J.; Liang, Z.; Mandić, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2016-02-01

    The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with the AMS H35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

  9. IR CMOS: the digital nightvision solution to sub-1 mLux imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Vineis, C.; Palsule, C.; Jiang, J.; Joy, T.

    2015-05-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux at 60 FPS with a 720P CMOS image sensor in a compact, low latency camera. The camera contains a 1 inch (16 mm) optical format sensor and streams uncompressed video over CameraLink with row wise image latency below 1 msec. Sub mLux imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancement is achieved by utilizing SiOnyx's proprietary ultrafast laser semiconductor processing technology that enhances the absorption of light within a thin pixel layer. Our technology demonstrates a 10 fold improvement in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see-spot.

  10. CMOS dielectrophoretic Lab-on-Chip platform for manipulation and monitoring of cells.

    PubMed

    Kyoungchul Park; Kabiri, Shideh; Sonkusale, Sameer

    2015-08-01

    We propose a novel Complementary Metal Oxide Semiconductor (CMOS) based Lab-on-Chip (LoC) platform for trapping, rotation and detection of cells and microorganism utilizing dielectrophoresis (DEP). DEP is a highly selective function of the permittivity, size and shape of the entity, and also depends on the permittivity of its environment; these dependencies can be used to identify and trap particles of interest with high precision. Real-time monitoring of such cellular manipulation is also desirable. Towards this goal, we have implemented a three-dimensional (3D) octa-pole electrode structure directly using the built-in metal layers of standard complementary metal-oxide-semiconductor (CMOS) process and demonstrate trapping and rotating of yeast cells. Moreover, we implement an impedance readout circuitry to monitor this process in situ. Paper presented both simulation and experimental results validating the platform. PMID:26738034

  11. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis.

    PubMed

    Hageman, Kristin N; Kalayjian, Zaven K; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A; Fridman, Gene Y; Dai, Chenkai; Pouliquen, Philippe O; Georgiou, Julio; Della Santina, Charles C; Andreou, Andreas G

    2016-04-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 °/s for the MVP2 and 2.0-14.2 °/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference ( t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  12. High-Q CMOS-integrated photonic crystal microcavity devices

    PubMed Central

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  13. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

    PubMed Central

    Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

    2015-01-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  14. Packaging commercial CMOS chips for lab on a chip integration.

    PubMed

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

  15. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  16. Optical characterization of CMOS compatible micro optics fabricated by mask-based and mask-less hybrid lithography

    NASA Astrophysics Data System (ADS)

    Wang, Sunglin; Summitt, Chris; Johnson, Lee; Zaverton, Melissa; Milster, Tom; Takashima, Yuzuru

    2014-09-01

    We report a CMOS compatible fabrication and optical characterization of the micrometer scale optical coupler, a 45° mirror-based optical coupler for inter-layer optical coupling. A newly proposed mask-based and mask-less hybrid lithography process enables accurate surface profile of the micrometer sized 45° mirror by using a CMOS compatible buffer coat material. Surface profile inspected by an optical interferometry agrees well with SEM based inspection results. Experimental and theoretical results for routing and coupling of laser beam in 90° will be discussed.

  17. High-speed modulator with interleaved junctions in zero-change CMOS photonics

    NASA Astrophysics Data System (ADS)

    Alloatti, L.; Cheian, D.; Ram, R. J.

    2016-03-01

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  18. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    NASA Technical Reports Server (NTRS)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  19. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    NASA Astrophysics Data System (ADS)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  20. The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

    PubMed Central

    Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

    2014-01-01

    Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

  1. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  2. A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixels Using Pinned Diodes

    NASA Astrophysics Data System (ADS)

    Yasutomi, Keita; Tamura, Toshihiro; Furuta, Masanori; Itoh, Shinya; Kawahito, Shoji

    This paper describes a high-speed CMOS image sensor with a new type of global electronic shutter pixel. A global electronic shutter is necessary for imaging fast-moving objects without motion blur or distortion. The proposed pixel has two potential wells with pinned diode structure for two-stage charge transfer that enables a global electronic shuttering and reset noise canceling. A prototype high-speed image sensor fabricated in 0.18μm standard CMOS image sensor process consists of the proposed pixel array, 12-bit column-parallel cyclic ADC arrays and 192-channel digital outputs. The sensor achieves a good linearity at low-light intensity, demonstrating the perfect charge transfer between two pinned diodes. The input referred noise of the proposed pixel is measured to be 6.3 e-.

  3. A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

    PubMed Central

    Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

    2008-01-01

    A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications.

  4. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    NASA Astrophysics Data System (ADS)

    Feng, Zhou; Ting, Gao; Fei, Lan; Wei, Li; Ning, Li; Junyan, Ren

    2010-11-01

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  5. 2.4 GHz CMOS power amplifier with mode-locking structure to enhance gain.

    PubMed

    Lee, Changhyun; Park, Changkun

    2014-01-01

    We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2). PMID:25045755

  6. Gate-leakage-tolerant circuits in deep sub-100-nm CMOS technologies

    NASA Astrophysics Data System (ADS)

    Kang, Sung-Mo; Yang, Ge; Wang, Zhongda

    2004-03-01

    The leakage power consumption in deep sub-100nm CMOS systems is projected to become a significant part of the total power dissipation. Although the dual Vt CMOS process helps reduce the subthreshold leakage current, the gate leakage problem poses a significant design challenge. We introduce gate leakage tolerant circuits. We describe two new circuit techniques to suppress gate leakage currents in dual Vt Domino circuits. In standby mode, proposed circuits generate low inputs and low outputs for all Domino stages to suppress gate leakage currents in the NMOS logic tree. Simulation results using 45nm BSIM4 SPICE models for 32-bit adders show that adders using the two proposed circuits can reduce the standby gate leakage by 66% and 90%, respectively. Proposed adders have 7% active power overhead to achieve the same speed as single Vt domino adder and the area penalty is minimal with careful layout.

  7. Characterization of zeolite-trench-embedded microcantilevers with CMOS strain gauge for integrated gas sensor applications

    NASA Astrophysics Data System (ADS)

    Inoue, Shu; Denoual, Matthieu; Awala, Hussein; Grand, Julien; Mintova, Sveltana; Tixier-Mita, Agnès; Mita, Yoshio

    2016-04-01

    Custom-synthesized zeolite is coated and fixed into microcantilevers with microtrenches of 1 to 5 µm width. Zeolite is a porous material that absorbs chemical substances; thus, it is expected to work as a sensitive chemical-sensing head. The total mass increases with gas absorption, and the cantilever resonance frequency decreases accordingly. In this paper, a thick zeolite cantilever sensor array system for high sensitivity and selectivity is proposed. The system is composed of an array of microcantilevers with silicon deep trenches. The cantilevers are integrated with CMOS-made polysilicon strain gauges for frequency response electrical measurement. The post-process fabrication of such an integrated array out of a foundry-made CMOS chip is successful. On the cantilevers, three types of custom zeolite (FAU-X, LTL, and MFI) are integrated by dip and heating methods. The preliminary measurement has shown a clear shift of resonance frequency by the chemical absorbance of ethanol gas.

  8. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    NASA Astrophysics Data System (ADS)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal–oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  9. 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

    PubMed Central

    2014-01-01

    We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2. PMID:25045755

  10. A CMOS analog front-end chip for amperometric electrochemical sensors

    NASA Astrophysics Data System (ADS)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  11. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

    PubMed

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-01-01

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

  12. A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications.

    PubMed

    Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Mirzaei, Maryam; Ayala-Charca, Giancarlo; Awwad, Falah; Sawan, Mohamad

    2015-06-01

    In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents. PMID:25134090

  13. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

    PubMed Central

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-01-01

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

  14. A CMOS compatible Microbulk Micromegas-like detector using silicon oxide as spacer material

    NASA Astrophysics Data System (ADS)

    Blanco Carballo, V. M.; Fransen, M.; van der Graaf, H.; Lu, J.; Schmitz, J.

    2011-02-01

    We present a new Micro Pattern Gaseous Detector (MPGD) fabricated with nonpolymeric materials. The device structure is similar to a Microbulk Micromegas design, consisting of a punctured metal grid supported by a continuous perforated insulating structure. In this detector, the supporting structure is made out of silicon oxide. Devices were tested in He/ iC 4H 10 (80/20) and Ar/ iC 4H 10 (80/20) gas mixtures under 55Fe irradiation. Gas gain of 20,000 and energy resolution below 13% FWHM were achieved. The CMOS compatibility of the fabrication process has been studied in Timepix chips as well as individual 0.13-μm technology CMOS transistors. Complete detectors have been fabricated on top of Timepix chips. In an Ar/ iC 4H 10 (80/20) gas mixture 55Fe decay events were recorded operating the Timepix chip in 2D readout mode.

  15. A digitally calibrated CMOS RMS power detector for RF automatic gain control

    NASA Astrophysics Data System (ADS)

    Taotao, Yan; Hui, Wang; Jinbo, Li; Jianjun, Zhou

    2013-03-01

    This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency (RF) root-mean-square (RMS) power detector for high accuracy RF automatic gain control (AGC). The proposed RMS power detector demonstrates accurate power detection in the presence of process, supply voltage, and temperature (PVT) variations by employing a digital calibration scheme. It also consumes low power and occupies a small chip area. The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz. Implemented in a 0.18 μm CMOS process and occupying a small die area of 263 × 214 μm2, the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.

  16. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

    PubMed

    Hussain, Aftab M; Hussain, Muhammad M

    2016-06-01

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. PMID:26607553

  17. CMOS micromachined probes by die-level fabrication for extracellular neural recording

    NASA Astrophysics Data System (ADS)

    Ho, Meng-Han; Chen, Hsin; Tseng, Fouriers; Yeh, Shih-Rung; S-C Lu, Michael

    2007-02-01

    In this paper, we present the design, fabrication and characterization of CMOS micromachined probes for extracellular neural recording. A convenient fabrication process is proposed for making integrated recording probes at the die level, providing a low-cost solution for academic research as compared to the more expensive wafer-level approach adopted in prior work. The devices are fabricated in a standard 0.35 µm CMOS process, followed by post-CMOS micromachining steps to form the probes. The on-chip circuit, used for recording action potential signals of neural activities, provides a stable dc bias when operating in electrolyte. The subthreshold transistor at the circuit input provides a tunable resistance value between 10 MΩ up to GΩ. The circuit consumes a total power of 790 µW and has an output noise of 19.3 µV Hz-1/2 at 100 Hz. The recorded action potential from the stimulated ventral nerve cord of a crayfish is about 0.6 mV with a pulse width of about 1.2 ms.

  18. A simple and low-cost biofilm quantification method using LED and CMOS image sensor.

    PubMed

    Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

    2014-12-01

    A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P < 0.01) and the coefficients of variation (CVs) were approximately threefold lower at the CMOS image-sensor platform. PMID:25455019

  19. Integrated pressure-sensing microsystem by CMOS IC technology for barometal applications

    NASA Astrophysics Data System (ADS)

    Zhou, Minxin; Huang, Qing-An

    2001-10-01

    Most currently integrated silicon microsystems available for pressure sensing are based on preprocessing before CMOS IC technology. These microsystems are generally very sensitive to parasitism effect and not available for IC-compatible process. This limits the accuracy of the microsystem and batch-fabrication. Calibration cost is also increased. To overcome these problems, a new generation of pressure microsystems without preprocessing CMOS IC technology has been proposed. This pressure-sensing system consists of a miniature silicon capacitive sensor, fabricated with silicon-silicon bonding technique, and a detection integrated circuit. Only the standard layers of CMOS process are used to build the system and only several photolithography steps are necessary to achieve the micromachined structure in postprocessing, so a high long-term stability could be assured. The entire system converts absolute pressure changes, in the pressure range useful for barometal applications, to frequency changes. A reference capacitor is used in the system and a (delta) C model is applied to cancel out temperature dependence and to compensate non-linearity. The pressure range of the sensor is from 0.5 bar to 1.5bar and the temperature varies between -25 degree(s)C and -60 degree(s)C. A sensitivity of 50Hz/Torr could be achieved.

  20. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    SciTech Connect

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y.

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  1. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  2. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  3. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  4. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    SciTech Connect

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  5. 1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

    PubMed

    Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

    2010-01-01

    This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications. PMID:20040430

  6. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  7. High-speed multicolour photometry with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

    2012-11-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ≃14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

  8. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  9. CMOS monolithic pixel sensors research and development at LBNL

    NASA Astrophysics Data System (ADS)

    Contarato, D.; Bussat, J.-M.; Denes, P.; Greiner, L.; Kim, T.; Stezelberger, T.; Wieman, H.; Battaglia, M.; Hooberman, B.; Tompkins, L.

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  10. CMOS front end electronics for the ATLAS muon detector

    SciTech Connect

    Huth, J.; Oliver, J.; Hazen, E.; Shank, J.

    1997-12-31

    An all-CMOS design for an integrated ASD (Amplifier-Shaper-Discriminator) chip for readout of the ATLAS Monitored Drift Tubes (MDTs) is presented. Eight channels of charge-sensitive preamp, two-stage pole/zero shaper, Wilkinson ADC and discriminator with programmable hysteresis are integrated on a single IC. Key elements have been prototyped in 1.2 and 0.5 micron CMOS operating at 5V and 3.3V respectively.

  11. CMOS Image Sensors: Electronic Camera On A Chip

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  12. RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications

    NASA Astrophysics Data System (ADS)

    Jackson, Suzy A.

    2004-06-01

    New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS ‘Receiver-on-a-Chip’ is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 μm RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

  13. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Schmitz, A.; Tielert, R.

    2005-05-01

    Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  14. Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

    NASA Astrophysics Data System (ADS)

    Naumowicz, M.; Melosik, M.; Katarzynski, P.; Handkiewicz, A.

    2013-09-01

    The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.

  15. Spin blockade in a triple silicon quantum dot in CMOS technology

    NASA Astrophysics Data System (ADS)

    Prati, E.; Petretto, G.; Belli, M.; Mazzeo, G.; Cocco, S.; de Michielis, M.; Fanciulli, M.; Guagliardo, F.; Vinet, M.; Wacquez, R.

    2012-02-01

    We study the spin blockade (SB) phenomenon by quantum transport in a triple quantum dot made of two single electron transistors (SET) on a CMOS platform separated by an implanted multiple donor quantum dot [1]. Spin blockade condition [2] has been used in the past to realize single spin localization and manipulation in GaAs quantum dots [3]. Here, we reproduce the same physics in a CMOS preindustrial silicon quantum device. Single electron quantum dots are connected via an implanted quantum dot and exhibit SB in one current direction. We break the spin blockade by applying a magnetic field of few tesla. Our experimental results are explained by a theoretical microscopic scheme supported by simulations in which only some of the possible processes through the triple quantum dot are spin blocked, according to the asymmetry of the coupling capacitances with the control gates and the central dot. Depending on the spin state, the SB may be both lifted and induced. Spin control in CMOS quantum dots is a necessary condition to realize large fabrication of spin qubits in some solid state silicon quantum device architectures.[0pt] [1] Pierre et al., Appl. Phys. Lett., 95, 24, 242107 (2009); [2] Liu et al., Phys. Rev. B 77, 073310 (2008); [3] Koppens et al., Nature 442, 766-771 (2006)

  16. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

    PubMed

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<-9 dB) with excellent transmission efficiency (averagely -1.9 dB) from 110 GHz-325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author's knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

  17. On-chip polarizer on image sensor using advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Sasagawa, Kiyotaka; Wakama, Norimitsu; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

    2014-03-01

    The structures in advanced complementary metal-oxide-semiconductor (CMOS) integrated circuit technology are in the range of deep-submicron. It allows designing and integrating nano-photonic structures for the visible to near infrared region on a chip. In this work, we designed and fabricated an image sensor with on-pixel metal wire grid polarizers by using a 65-nm standard CMOS technology. It is known that the extinction ratio of a metal wire grid polarizer is increased with decrease in the grid pitch. With the metal wire layers of the 65-nm technology, the grid pitch sufficiently smaller than the wavelengths of visible light can be realized. The extinction ratio of approximately 20 dB has been successfully achieved at a wavelength of 750 nm. In the CMOS technologies, it is usual to include multiple metal layers. This feature is also useful to increase the extinction ratio of polarizers. We designed dual layer polarizers. Each layer partially reflects incident light. Thus, the layers form a cavity and its transmission spectrum depends on the layer position. The extinction ratio of 19.2 dB at 780 nm was achieved with the grid pitch greater than the single layer polarizer. The high extinction ratio is obtained only red to near infrared region because the fine metal layers of deepsubmicron standard CMOS process is usually composed of Cu. Thus, it should be applied for measurement or observation where wide spectrum is not required such as optical rotation measurement of optically active materials or electro-optic imaging of RF/THz wave.

  18. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    NASA Astrophysics Data System (ADS)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  19. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    NASA Astrophysics Data System (ADS)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  20. A CMOS ASIC Design for SiPM Arrays.

    PubMed

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  1. Label-free immunodetection with CMOS-compatible semiconducting nanowires.

    PubMed

    Stern, Eric; Klemic, James F; Routenberg, David A; Wyrembak, Pauline N; Turner-Evans, Daniel B; Hamilton, Andrew D; LaVan, David A; Fahmy, Tarek M; Reed, Mark A

    2007-02-01

    Semiconducting nanowires have the potential to function as highly sensitive and selective sensors for the label-free detection of low concentrations of pathogenic microorganisms. Successful solution-phase nanowire sensing has been demonstrated for ions, small molecules, proteins, DNA and viruses; however, 'bottom-up' nanowires (or similarly configured carbon nanotubes) used for these demonstrations require hybrid fabrication schemes, which result in severe integration issues that have hindered widespread application. Alternative 'top-down' fabrication methods of nanowire-like devices produce disappointing performance because of process-induced material and device degradation. Here we report an approach that uses complementary metal oxide semiconductor (CMOS) field effect transistor compatible technology and hence demonstrate the specific label-free detection of below 100 femtomolar concentrations of antibodies as well as real-time monitoring of the cellular immune response. This approach eliminates the need for hybrid methods and enables system-scale integration of these sensors with signal processing and information systems. Additionally, the ability to monitor antibody binding and sense the cellular immune response in real time with readily available technology should facilitate widespread diagnostic applications. PMID:17268465

  2. Effect of body biasing on single-event induced charge collection in deep N-well technology

    NASA Astrophysics Data System (ADS)

    Ding, Yi; Hu, Jian-Guo; Qin, Jun-Rui; Tan, Hong-Zhou

    2015-07-01

    As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits (ICs). At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design (TCAD) simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.

  3. A 512×512 CMOS Monolithic Active Pixel Sensor with integrated ADCs for space science

    NASA Astrophysics Data System (ADS)

    Prydderch, M. L.; Waltham, N. J.; Turchetta, R.; French, M. J.; Holt, R.; Marshall, A.; Burt, D.; Bell, R.; Pool, P.; Eyles, C.; Mapson-Menard, H.

    2003-10-01

    In the last few years, CMOS sensors have become widely used for consumer applications, but little has been done for scientific instruments. In this paper we present the design and experimental characterisation of a Monolithic Active Pixel Sensor (MAPS) intended for a space science application. The sensor incorporates a 525×525 array of pixels on a 25 μm pitch. Each pixel contains a detector together with three transistors that are used for pixel reset, pixel selection and charge-to-voltage conversion. The detector consists of four n-well/p-substrate diodes combining optimum charge collection and low noise performance. The array readout is column-parallel with adjustable gain column amplifiers and a 10-bit single slope ADC. Data conversion takes place simultaneously for all the 525 pixels in one row. The ADC slope can be adjusted in order to give the best dynamic range for a given brightness of a scene. The digitised data are output on a 10-bit bus at 3 MHz. An on-chip state machine generates all of the control signals needed for the readout. All of the bias currents and voltages are generated on chip by a DAC that is programmable through an I 2C compatible interface. The sensor was designed and fabricated on a standard 0.5 μm CMOS technology. The overall die size is 16.7 mm×19.9 mm including the associated readout electronics and bond pads. Preliminary test results show that the full-scale design works well, meeting the Star Tracker requirements with less than 1-bit noise, good linearity and good optical performance.

  4. System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

    PubMed

    Lee, Sung Pil

    2015-10-01

    Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display. PMID:26726359

  5. Uncooled CMOS terahertz imager using a metamaterial absorber and pn diode.

    PubMed

    Escorcia, Ivonne; Grant, James; Gough, John; Cumming, David R S

    2016-07-15

    We demonstrate a low-cost uncooled terahertz (THz) imager fabricated in a standard 180 nm CMOS process. The imager is composed of a broadband THz metamaterial absorber coupled with a diode microbolometer sensor where the pn junction is used as a temperature sensitive device. The metamaterial absorber array is integrated in the top metallic layers of a six metal layer process allowing for complete monolithic integration of the metamaterial absorber and sensor. We demonstrate the capability of the detector for stand-off imaging applications by using it to form transmission and reflection images of a metallic object hidden in a manila envelope. PMID:27420510

  6. A CMOS readout circuit for microstrip detectors

    NASA Astrophysics Data System (ADS)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  7. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    NASA Astrophysics Data System (ADS)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz

  8. Design and implementation of a 1-V transformer magnetic feedback low-noise amplifier (LNA) at 5-6 GHz, in a 90 nm complementary metal-oxide-semiconductor (CMOS) process

    NASA Astrophysics Data System (ADS)

    Kytonaki, Eleni-Sotiria; Simitsakis, Paschalis; Bazigos, Antonios; Papananos, Yannis

    2011-02-01

    In this study, a low-noise amplifier (LNA) suitable for low-voltage operation is presented. The LNA operates at a frequency range between 5 and 6 GHz. Its topology exploits magnetic feedback to achieve high reverse isolation and low noise performance without a significant degradation of the gain and linearity of the circuit. The design has been fabricated, considering full electrostatic discharge protection, in a modern 90 nm complementary metal-oxide-semiconductor process. The measured performance, at 5.4 GHz, shows a reverse isolation of -17.3 dB, a gain of 10.4 dB, a noise figure of 0.98 dB and an input intercept point of 1.4 dBm. The circuit dissipates 12.5 mW from a 1 V supply, while it occupies 0.162 mm2 of the die area.

  9. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  10. Smart CMOS sensor for wideband laser threat detection

    NASA Astrophysics Data System (ADS)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  11. Passive radiation detection using optically active CMOS sensors

    NASA Astrophysics Data System (ADS)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  12. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  13. Charge collection studies in irradiated HV-CMOS particle detectors

    NASA Astrophysics Data System (ADS)

    Affolder, A.; Andelković, M.; Arndt, K.; Bates, R.; Blue, A.; Bortoletto, D.; Buttar, C.; Caragiulo, P.; Cindro, V.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Gorišek, A.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, G.; Liang, Z.; Mandić, I.; Maneuski, D.; McMahon, S.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zavrtanik, M.; Zhang, J.; Zhu, H.

    2016-04-01

    Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

  14. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  15. A hierarchical approach to test generation for CMOS VLSI circuits

    NASA Astrophysics Data System (ADS)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  16. CMOS solid state photomultipliers for ultra-low light levels

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

    2011-05-01

    Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

  17. Fabrication and Electrical Characterization of Strained Si-on-insulator/Strained SiGe-on-insulator Dual Channel CMOS structures with High-Mobility Channels

    NASA Astrophysics Data System (ADS)

    Tezuka, Tsutomu; Nakaharai, Shu; Moriyama, Yoshihiko; Hirashita, Norio; Toyoda, Eiji; Sugiyama, Naoharu; Mizuno, Tomohisa; Takagi, Shinichi

    Mobility enhancement technologies by incorporating strain in MOSFETs have been recognized as key technologies for scaled CMOS devices. The most promising channel materials for n- and p-channel MOSFETs are tensily-strained Si and compressively-strained Ge (SiGe), respectively, from the viewpoint of their high mobility values. In this paper, dual channel CMOS structures with strained Si-on-insulator (strained-SOI)-nMOSFETs and strained SiGe-on-insulator (strained-SGOI)-pMOSFETs are demonstrated as well as their high channel mobility and current drive enhancements. Strained Si channels on a relaxed SGOI substrate and Ge-rich strained SGOI channels are located on the nMOS and pMOS regions of the same wafer, respectively. The dual channel structure was fabricated by a CMOS process combined with the Ge condensation process, in which the epitaxially grown SiGe layer on the SOI substrate was locally oxidized at high temperatures. As a result, significant electron- and hole-mobility enhancements for the strained SOI and SGOI channels were observed as well as the drain current enhancements. Based on the measured mobility for the nMOS and pMOS channels in the CMOS devices, CMOS performance enhancement of 30% was estimated.

  18. Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

    SciTech Connect

    Blaes, B.R.; Soli, G.A.; Buehler, M.G. )

    1991-12-01

    This paper describes a methodology for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-{mu}m n-well CMOS 4k-bit test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 {mu}m was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 Mev cm{sup 2}/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV cm{sup 2}/mg was determined.

  19. Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

    NASA Technical Reports Server (NTRS)

    Blaes, B. R.; Soli, G. A.; Buehler, M. G.

    1991-01-01

    A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

  20. Manufacture and characterization of high Q-factor inductors based on CMOS-MEMS techniques.

    PubMed

    Yang, Ming-Zhi; Dai, Ching-Liang; Hong, Jin-Yu

    2011-01-01

    A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively. PMID:22163726

  1. Manufacture and Characterization of High Q-Factor Inductors Based on CMOS-MEMS Techniques

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Hong, Jin-Yu

    2011-01-01

    A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively. PMID:22163726

  2. Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

    NASA Astrophysics Data System (ADS)

    Nam, Ilku; Moon, Hyunwon; Woo, Doo Hyung

    In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

  3. Post-CMOS compatible high-throughput fabrication of AlN-based piezoelectric microcantilevers

    NASA Astrophysics Data System (ADS)

    Pérez-Campos, A.; Iriarte, G. F.; Hernando-Garcia, J.; Calle, F.

    2015-02-01

    A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3-Cl2-Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

  4. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    NASA Astrophysics Data System (ADS)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  5. CMOS Cell Sensors for Point-of-Care Diagnostics

    PubMed Central

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  6. Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

    NASA Technical Reports Server (NTRS)

    Trotter, J. D.

    1982-01-01

    The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

  7. Etch challenges for DSA implementation in CMOS via patterning

    NASA Astrophysics Data System (ADS)

    Pimenta Barros, P.; Barnola, S.; Gharbi, A.; Argoud, M.; Servin, I.; Tiron, R.; Chevalier, X.; Navarro, C.; Nicolet, C.; Lapeyre, C.; Monget, C.; Martinez, E.

    2014-03-01

    This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

  8. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J. A.; Metaxas, M. G.; Royle, G. J.; Speller, R.; Venanzi, C.; van der Stelt, P. F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J. M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS).

  9. Design of CMOS logic gates for TID radiation

    NASA Technical Reports Server (NTRS)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  10. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    NASA Astrophysics Data System (ADS)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  11. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  12. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  13. Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

    PubMed Central

    Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

    2008-01-01

    With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field.

  14. Prototype Active Silicon Sensor in 150 nm HR-CMOS technology for ATLAS Inner Detector Upgrade

    NASA Astrophysics Data System (ADS)

    Rymaszewski, P.; Barbero, M.; Breugnon, P.; Godiot, S.; Gonella, L.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Liu, J.; Pangaud, P.; Peric, I.; Rozanov, A.; Wang, A.; Wermes, N.

    2016-02-01

    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

  15. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

    PubMed Central

    Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

    2009-01-01

    We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed. PMID:22389592

  16. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

    PubMed

    Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

    2009-01-01

    We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed. PMID:22389592

  17. A 65 nm CMOS LNA for Bolometer Application

    NASA Astrophysics Data System (ADS)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  18. Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Krüger, H.; Wermes, N.

    2015-03-01

    We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e-) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 μm thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

  19. Integrated on-chip 0.35 μm BiCMOS current-mode DC-DC buck converter

    NASA Astrophysics Data System (ADS)

    Lee, Chan-Soo; Kim, Nam-Soo; Gendensuren, Munkhsuld; Choi, Jae-Ho; Choi, Joong-Ho

    2012-12-01

    A current-mode DC-DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC-DC converter is fabricated with 0.35 µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3 MHz switching frequency with a supply voltage of 5 V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30 µH off-chip inductor and 100 µF off-chip capacitor.

  20. CMOS image sensor integrated with micro-LED and multielectrode arrays for the patterned photostimulation and multichannel recording of neuronal tissue.

    PubMed

    Nakajima, Arata; Kimura, Hiroshi; Sawadsaringkarn, Yosmongkol; Maezawa, Yasuyo; Kobayashi, Takuma; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

    2012-03-12

    We developed a complementary metal oxide semiconductor (CMOS) integrated device for optogenetic applications. This device can interface via neuronal tissue with three functional modalities: imaging, optical stimulation and electrical recording. The CMOS image sensor was fabricated on 0.35 μm standard CMOS process with built-in control circuits for an on-chip blue light-emitting diode (LED) array. The effective imaging area was 2.0 × 1.8 mm². The pixel array was composed of 7.5 × 7.5 μm² 3-transistor active pixel sensors (APSs). The LED array had 10 × 8 micro-LEDs measuring 192 × 225 μm². We integrated the device with a commercial multichannel recording system to make electrical recordings. PMID:22418489

  1. Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

    1987-01-01

    Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

  2. Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs

    NASA Astrophysics Data System (ADS)

    Nuñez, Juan; Avedillo, María J.; Quintana, José M.

    2011-05-01

    The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.

  3. Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

    NASA Astrophysics Data System (ADS)

    Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

    2014-07-01

    We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

  4. High dynamic range CMOS image sensor with pixel level ADC and in-situ image enhancement

    NASA Astrophysics Data System (ADS)

    Harton, Austin V.; Ahmed, Mohamed I.; Beuhler, Allyson; Castro, Francisco; Dawson, Linda M.; Herold, Barry W.; Kujawa, Gregory; Lee, King F.; Mareachen, Russell D.; Scaminaci, Tony J.

    2005-03-01

    We describe a CMOS image sensor with pixel level analog to digital conversion (ADC) having high dynamic range (>100db) and the capability of performing many image processing functions at the pixel level during image capture. The sensor has a 102x98 pixel array and is implemented in a 0.18um CMOS process technology. Each pixel is 15.5um x15.5um with 15% fill factor and is comprised of a comparator, two 10 bit memory registers and control logic. A digital to analog converter and system processor are located off-chip. The photodetector produces a photocurrent yielding a photo-voltage proportional to the impinging light intensity. Once the photo-voltage is less than a predetermined global reference voltage; a global code value is latched into the pixel data buffer. This process prevents voltage saturation resulting in high dynamic range imaging. Upon completion of image capture, a digital representation of the image exists at the pixel array, thereby, allowing image data to be accessed in a parallel fashion from the focal plane array. It is demonstrated that by appropriate variation of the global reference voltage with time, it is possible to perform, during image capture, thresholding and image enhancement operations, such as, contrast stretching in a parallel manner.

  5. Photocurrent estimation from multiple nondestructive samples in CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Liu, Xinqiao; El Gamal, Abbas

    2001-05-01

    CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic range, while achieving higher SNR than using other dynamic range enhancement schemes. The high dynamic range image is constructed by appropriately scaling each pixel's last sample before saturation. Conventional CDS is used to reduce offset FPN and reset noise. This simple high dynamic range image construction scheme, however, does not take full advantage of the multiple samples. Readout noise power, which doubles as a result of performing CDS, remain as high as in conventional sensor operation. As a result dynamic range is only extended at the high illumination end. The paper explores the use of linear mean-square-error estimation to more fully exploit the multiple pixel samples to reduce readout noise and thus extend dynamic range at the low illumination end. We present three estimation algorithms: (1) a recursive estimator when reset noise and offset FPN are ignored, (2) a non-recursive algorithm when reset noise and FPN are considered, and (3) a recursive estimation algorithm for case (2), which achieves mean square error close to the non-recursive algorithm without the need to store all the samples. The later recursive algorithm is attractive since it requires the storage of only a few pixel values per pixel, which makes its implementation in a single chip digital imaging system feasible.

  6. sCMOS detector for imaging VNIR spectrometry

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  7. Compact CMOS Camera Demonstrator (C3D) for Ukube-1

    NASA Astrophysics Data System (ADS)

    Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

    2011-09-01

    The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

  8. First measurement of the in-pixel electron multiplying with a standard imaging CMOS technology: Study of the EMCMOS concept

    NASA Astrophysics Data System (ADS)

    Brugière, Timothée; Mayer, Fréderic; Fereyre, Pierre; Guérin, Cyrille; Dominjon, Agnés; Barbier, Rémi

    2015-07-01

    Scientific low light imaging devices benefit today from designs for pushing the mean noise to the single electron level. When readout noise reduction reaches its limit, signal-to-noise ratio improvement can be driven by an electron multiplication process, driven by impact ionization, before adding the readout noises. This concept already implemented in CCD structures using extra-pixel shift registers can today be integrated inside each pixel in CMOS technology. The EBCMOS group at IPNL is in charge of the characterization of new prototypes developed by E2V using this concept: the electron multiplying CMOS (EMCMOS). The CMOS technology enables electron multiplication inside the photodiode itself, and thus, an overlap of the charge integration and multiplication. A new modeling has been developed to describe the output signal mean and variance after the impact ionization process in such a case. In this paper the feasibility of impact ionization process inside a 8 μm-pitch pixel is demonstrated. The new modeling is also validated by data and a value of 0.32% is obtained for the impact ionization parameter α with an electric field intensity of 24 V / μm.

  9. Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

    2016-05-01

    In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

  10. Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Vishnoi, U.; Noll, T. G.

    2012-09-01

    The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit

  11. Low light level CMOS sensor for night vision systems

    NASA Astrophysics Data System (ADS)

    Gross, Elad; Ginat, Ran; Nesher, Ofer

    2015-05-01

    For many years image intensifier tubes were used for night vision systems. In 2014, Elbit systems developed a digital low-light level CMOS sensor, with similar sensitivity to a Gen II image-intensifiers, down to starlight conditions. In this work we describe: the basic principle behind this sensor, physical model for low-light performance estimation and results of field testing.

  12. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  13. CMOS image sensors as an efficient platform for glucose monitoring.

    PubMed

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-01

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

  14. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  15. Upper-Bound Estimates Of SEU in CMOS

    NASA Technical Reports Server (NTRS)

    Edmonds, Larry D.

    1990-01-01

    Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

  16. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  17. Attributes and drawbacks of submicron CMOS for IR FPA readouts

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.

    1998-09-01

    The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

  18. Relationship between IBICC imaging and SEU in CMOS ICs

    SciTech Connect

    Sexton, F.W.; Horn, K.M.; Doyle, B.L.; Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F.

    1993-03-01

    Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

  19. Relationship between IBICC imaging and SEU in CMOS ICs

    SciTech Connect

    Sexton, F.W.; Horn, K.M.; Doyle, B.L. ); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. )

    1993-01-01

    Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

  20. Reliability design of CMOS image sensor for space applications

    NASA Astrophysics Data System (ADS)

    Xie, Ning; Chen, Shijun; Chen, Yongping

    2013-08-01

    In space applications, sensors work in very harsh space environment. Thus the reliability design must be carefully considered. This paper addresses the techniques which effectively increase the reliability of CMOS image sensors. A radiation tolerant pixel design which is implemented in a sun tracker sensor is presented. Measurement results of total dose radiation, SEL, SEU, etc prove the radiation immunity of the sensor.

  1. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    NASA Technical Reports Server (NTRS)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  2. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  3. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  4. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  5. Neutron induced soft errors in CMOS memories under reduced bias

    SciTech Connect

    Hazucha, P.; Svensson, C.; Johansson, K.

    1998-12-01

    A custom designed 16 kbit CMOS memory was irradiated by 14 MeV neutrons and 100 MeV neutrons. SEU cross sections were evaluated under different supply voltages. The cross section values are compared to those predicted by the BGR model.

  6. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  7. INDEP approach for leakage reduction in nanoscale CMOS circuits

    NASA Astrophysics Data System (ADS)

    Sharma, Vijay Kumar; Pattanaik, Manisha; Raj, Balwinder

    2015-02-01

    Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.

  8. Direct readout of gaseous detectors with tiled CMOS circuits

    NASA Astrophysics Data System (ADS)

    Visschers, J. L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; van der Graaf, H.; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-03-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside.

  9. Hybrid CMOS SiPIN detectors as astronomical imagers

    NASA Astrophysics Data System (ADS)

    Simms, Lance Michael

    Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge

  10. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

    PubMed Central

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

  11. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

    NASA Astrophysics Data System (ADS)

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-07-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<‑9 dB) with excellent transmission efficiency (averagely ‑1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

  12. A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

    PubMed

    Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

    2013-11-21

    As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

  13. CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

    PubMed

    Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

    2016-06-01

    Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS. PMID:26357405

  14. Contact CMOS imaging of gaseous oxygen sensor array

    PubMed Central

    Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

    2014-01-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

  15. Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

    NASA Astrophysics Data System (ADS)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

    2015-12-01

    This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

  16. Dc characterization of lateral bipolar devices in standard CMOS technology: a new model for base current partitioning

    NASA Astrophysics Data System (ADS)

    Corsi, F.; Di Ciano, M.; Marzocca, C.

    1999-05-01

    As is generally known, compared with MOSFETs bipolar transistors provide better performance in terms of small signal transconductance, intrinsic cut-off frequency and noise characteristics, at the cost of a more expensive technology. A good compromise between the low costs proper of standard CMOS technology and the excellent performance typical of bipolar devices can be achieved by using bipolar transistors derived from MOS structures. Naturally suitable models combined with efficient parameter extraction techniques are mandatory to provide designers with reliable simulation tools. A dc parameter extraction procedure for a PNP lateral transistor realized in a standard CMOS technology based on an existing composite circuit model is presented here. The extraction results provide accurate fitting between measured and simulated data for different operating regions without resort to numerical optimization, thus preserving the physical meaning of the extracted parameters and retaining a good correlation with process variations.

  17. CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

    NASA Astrophysics Data System (ADS)

    Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2016-04-01

    This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

  18. A high-dynamic range (HDR) back-side illuminated (BSI) CMOS image sensor for extreme UV detection

    NASA Astrophysics Data System (ADS)

    Wang, Xinyang; Wolfs, Bram; Bogaerts, Jan; Meynants, Guy; BenMoussa, Ali

    2012-03-01

    This paper describes a back-side illuminated 1 Megapixel CMOS image sensor made in 0.18um CMOS process for EUV detection. The sensor applied a so-call "dual-transfer" scheme to achieve low noise, high dynamic range. The EUV sensitivity is achieved with backside illumination use SOI-based solution. The epitaxial silicon layer is thinned down to less than 3um. The sensor is tested and characterized at 5nm to 30nm illumination. At 17.4nm targeted wavelength, the detector external QE (exclude quantum yield factor) reaches almost 60%. The detector reaches read noise of 1.2 ph- (@17.4nm), i.e. close to performance of EUV photon counting.

  19. Development of a CMOS MEMS pressure sensor with a mechanical force-displacement transduction structure

    NASA Astrophysics Data System (ADS)

    Cheng, Chao-Lin; Chang, Heng-Chung; Chang, Chun-I.; Fang, Weileun

    2015-12-01

    This study presents a capacitive pressure sensor with a mechanical force-displacement transduction structure based on the commercially available standard CMOS process (the TSMC 0.18 μm 1P6M CMOS process). The pressure sensor has a deformable diaphragm to support a movable plate with an embedded sensing electrode. As the diaphragm is deformed by the ambient pressure, the movable plate and its embedded sensing electrode are displaced. Thus, the pressure is detected from the capacitance change between the movable and fixed electrodes. The undeformed movable electrode will increase the effective sensing area between the sensing electrodes, thereby improving the sensitivity. Experimental results show that the proposed pressure sensor with a force-displacement transducer will increase the sensitivity by 126% within the 20 kPa-300 kPa absolute pressure range. Moreover, this study extends the design to add pillars inside the pressure sensor to further increase its sensing area as well as sensitivity. A sensitivity improvement of 117% is also demonstrated for a pressure sensor with an enlarged sensing electrode (the overlap area is increased two fold).

  20. Full colour RGB OLEDs on CMOS for active-matrix OLED microdisplays

    NASA Astrophysics Data System (ADS)

    Kreye, D.; Toerker, M.; Vogel, U.; Amelung, J.

    2006-08-01

    Microdisplays are used in various optical devices such as headsets, viewfinders and helmet-mounted displays. The use of organic light emitting diodes (OLEDs) in a microdisplay on silicone substrate provides the opportunity of lower power consumption and higher optical performance compared to other near-to-eye display technologies. Highly efficient, low-voltage, top emitting OLEDs are well suitable for the integration into a CMOSprocess. By reducing the operating voltage for the OLEDs below 5V, the costs for the CMOS process can be reduced significantly, because a standard process without high-voltage option can be used. Various OLED stacks on silicone substrate are presented, suitable for full colour (RGB) applications. Red and green emitting phosphorescent OLEDs and blue emitting fluorescent OLEDs all with doped charge transport layers were prepared on a two metal layer CMOS test substrate without active transistor area. Afterwards, the different test displays were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.)

  1. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    PubMed Central

    Chuang, Wan-Chun; Hu, Yuh-Chung; Chang, Pei-Zen

    2012-01-01

    This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive. PMID:23235449

  2. A CMOS pressure sensor with integrated interface for passive RFID applications

    NASA Astrophysics Data System (ADS)

    Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

    2014-12-01

    This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18 μm CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2 fF kPa-1. The sensor interface consumes only 1.1 µW of power at 0.5 V voltage supply, which is at least an order of magnitude better than state-of-the-art designs.

  3. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGESBeta

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  4. CMOS-Compatible Silicon-Nanowire-Based Coulter Counter for Cell Enumeration.

    PubMed

    Chen, Yu; Guo, Jinhong; Muhammad, Hamidullah; Kang, Yuejun; Ary, Sunil K

    2016-02-01

    A silicon-nanowire-based Coulter counter has been designed and fabricated for particle/cell enumeration. The silicon nanowire was fabricated in a fully complementary metal-oxide-semiconductor (CMOS)-compatible process and used as a field effect transistor (FET) device. The Coulter counter device worked on the principle of potential change detection introduced by the passing of microparticles/cells through a sensing channel. Device uniformity was confirmed by scanning electron microscopy and transmission electron microscopy. Current-voltage measurement showed the high sensitivity of the nanowire FET device to the surface potential change. The results revealed that the silicon-nanowire-based Coulter counter can differentiate polystyrene beads with diameters of 8 and 15 μm. Michigan Cancer Foundation-7 (MCF-7) cells have been successfully counted to validate the device. A fully CMOS-compatible fabrication process can help the device integration and facilitate the development of sensor arrays for high throughput application. With appropriate sample preparation steps, it is also possible to expand the work to applications such as rare-cells detection. PMID:26799578

  5. A novel Bayer-like WRGB color filter array for CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Honda, Hiroto; Iida, Yoshinori; Itoh, Go; Egawa, Yoshitaka; Seki, Hiromichi

    2007-02-01

    We have developed a CMOS image sensor with a novel color filter array(CFA) where one of the green pixels of the Bayer pattern was replaced with a white pixel. A transparent layer has been fabricated on the white pixel instead of a color filter to realize over 95% transmission for visible light with wavelengths of 400-700 nm. Pixel pitch of the device was 3.3 um and the number of pixels was 2 million (1600H x 1200V). The novel Bayer-like WRGB (White-Red-Green-Blue) CFA realized higher signal-to-noise ratios of interpolated R, G, and B values in low illumination (3lux) by 6dB, 1dB, and 6dB, respectively, compared with those of the Bayer pattern, with the low-noise pre-digital signal process. Furthermore, there was no degradation of either resolution or color representation for the interpolated image. This new CFA has a great potential to significantly increase the sensitivity of CMOS/CCD image sensors with digital signal processing technology.

  6. A time-domain CMOS oscillator-based thermostat with digital set-point programming.

    PubMed

    Chen, Chun-Chi; Lin, Shih-Hao

    2013-01-01

    This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-mm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s. PMID:23385403

  7. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    PubMed Central

    Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  8. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  9. Efficient design method for cell allocation in hybrid CMOS/nanodevices using a cultural algorithm with chaotic behavior

    NASA Astrophysics Data System (ADS)

    Pan, Zhong-Liang; Chen, Ling; Zhang, Guang-Zhao

    2016-04-01

    The hybrid CMOS molecular (CMOL) circuit, which combines complementary metal-oxide-semiconductor (CMOS) components with nanoscale wires and switches, can exhibit significantly improved performance. In CMOL circuits, the nanodevices, which are called cells, should be placed appropriately and are connected by nanowires. The cells should be connected such that they follow the shortest path. This paper presents an efficient method of cell allocation in CMOL circuits with the hybrid CMOS/nanodevice structure; the method is based on a cultural algorithm with chaotic behavior. The optimal model of cell allocation is derived, and the coding of an individual representing a cell allocation is described. Then the cultural algorithm with chaotic behavior is designed to solve the optimal model. The cultural algorithm consists of a population space, a belief space, and a protocol that describes how knowledge is exchanged between the population and belief spaces. In this paper, the evolutionary processes of the population space employ a genetic algorithm in which three populations undergo parallel evolution. The evolutionary processes of the belief space use a chaotic ant colony algorithm. Extensive experiments on cell allocation in benchmark circuits showed that a low area usage can be obtained using the proposed method, and the computation time can be reduced greatly compared to that of a conventional genetic algorithm.

  10. Improvement of signal-to-noise ratio by stochastic resonance in sigmoid function threshold systems, demonstrated using a CMOS inverter

    NASA Astrophysics Data System (ADS)

    Ueda, Michihito

    2010-05-01

    Stochastic resonance (SR) has become a well-known phenomenon that can enhance weak periodic signals with the help of noise. SR is an interesting phenomenon when applied to signal processing. Although it has been proven that SR does not always improve the signal-to-noise ratio (SNR), in a strongly nonlinear system such as simple threshold system, SR does in fact improve SNR for noisy pulsed signals at appropriate noise strength. However, even in such cases, when noise is weak, the SNR is degraded. Since the noise strength cannot be known in advance, it is difficult to apply SR to real signal processing. In this paper, we focused on the shape of the threshold at which SR did not degrade the SNR when noise was weak. To achieve output change when noise was weak, we numerically analyzed a sigmoid function threshold system. When the slope around the threshold was appropriate, SNR did not degrade when noise was weak and instead was improved at suitable noise strength. We also demonstrated SNR improvement for noisy pulsed voltages using a CMOS inverter, a very common threshold device. The input-output property of a CMOS inverter resembles the sigmoid function. By inputting the noisy signal voltage to a CMOS inverter, we measured the input and output voltages and analyzed the SNRs. The results showed that SNR was effectively improved over a wide range of noise strengths.

  11. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  12. Pattern transfer of directed self-assembly patterns for CMOS device applications

    NASA Astrophysics Data System (ADS)

    Tsai, Hsin-Yu; Miyazoe, Hiroyuki; Engelmann, Sebastian; Liu, Chi-Chun; Gignac, Lynne; Bucchignano, James; Klaus, David; Breslin, Chris; Joseph, Eric; Cheng, Joy; Sanders, Daniel; Guillorn, Michael

    2013-10-01

    A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line-space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal-oxide-semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

  13. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    NASA Astrophysics Data System (ADS)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  14. Room temperature lasing in GeSn alloys: A path to CMOS-compatible infrared lasers

    NASA Astrophysics Data System (ADS)

    Li, Zairui; Zhao, Yun; Gallagher, James; Menéndez, José; Kouvetakis, John; Agha, Imad; Mathews, Jay

    The semiconductor industry has been pushing silicon photonics development for many years, resulting in the realization of many CMOS-compatible optoelectronic devices. However, one challenge that has not been overcome is the development of Si-based lasers. Recently, GeSn alloys grown on Si have shown much promise in the field of infrared optoelectronics. These alloy films are compatible with CMOS processing, have band gaps in the infrared, and the band structure of GeSn can be tuned via Sn concentration to induce direct band gap emission. In this work, we report on room temperature lasing in optically-pumped waveguides fabricated from GeSn films grown epitaxially on Si(100) substrates. The waveguides were defined using standard UV photolithography and dry-etched in a Cl plasma. The end facets were mirror polished, and Al was deposited on one facet to enhance cavity quality. The waveguides were optically-pumped using a 976nm wavelength solid-state laser, and the corresponding emission was measured. The dependence of the emission power on the pump power shows a clear transition between spontaneous and stimulated emission, thereby demonstrating room temperature lasing.

  15. A high efficiency PWM CMOS class-D audio power amplifier

    NASA Astrophysics Data System (ADS)

    Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

    2009-02-01

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  16. Ultra-sensitive detection of adipocytokines with CMOS-compatible silicon nanowire arrays

    NASA Astrophysics Data System (ADS)

    Pui, Tze-Sian; Agarwal, Ajay; Ye, Feng; Tou, Zhi-Qiang; Huang, Yinxi; Chen, Peng

    2009-09-01

    Perfectly aligned arrays of single-crystalline silicon nanowires were fabricated using top-down CMOS-compatible techniques. We demonstrate that these nanowire devices are able to detect adipocytokines secreted by adipose cells with femtomolar sensitivity, high specificity, wide detection range, and ability for parallel monitoring. The nanowire sensors also provide a novel tool to reveal the poorly understood signaling mechanisms of these newly recognized signaling molecules, as well as their relevance in common diseases such as obesity and diabetes.Perfectly aligned arrays of single-crystalline silicon nanowires were fabricated using top-down CMOS-compatible techniques. We demonstrate that these nanowire devices are able to detect adipocytokines secreted by adipose cells with femtomolar sensitivity, high specificity, wide detection range, and ability for parallel monitoring. The nanowire sensors also provide a novel tool to reveal the poorly understood signaling mechanisms of these newly recognized signaling molecules, as well as their relevance in common diseases such as obesity and diabetes. Electronic supplementary information (ESI) available: Process diagram of nanowire fabrication; specificity of nanowire detection; induced differentiation of 3T3-L1 cells. See DOI: 10.1039/b9nr00092e

  17. Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

    PubMed

    Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

    2014-01-01

    This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency. PMID:24772012

  18. A low-power column-parallel ADC for high-speed CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  19. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    NASA Astrophysics Data System (ADS)

    Guang, Yang; Wang, Yao; Jiangwei, Yin; Renliang, Zheng; Wei, Li; Ning, Li; Junyan, Ren

    2009-01-01

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  20. Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications

    PubMed Central

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

    2014-01-01

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance. PMID:25540471

  1. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

    NASA Astrophysics Data System (ADS)

    Sharma, Vijay Kumar; Pattanaik, Manisha

    2015-11-01

    Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

  2. Negative Differential Transconductance in Silicon CMOS Quantum Well Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Naquin, Clint; Lee, Mark; Edwards, Hal; Chatterjee, Tathagata; Mathur, Guru

    2014-03-01

    Quantum well (QW) devices are potentially useful as high-speed oscillators and sensors, as well as high-density memory and multi-state logic. Historically, these devices have been built using III-V heterostructures grown epitaxially in the vertical direction. Silicon CMOS field effect transistors (FETs) that incorporate QWs through the lateral confinement of a silicon inversion layer are of particular interest due to their capability for mass production and industrial scalability. We report on the observation of negative differential transconductance (NDTC) in a set of Si CMOS QW FETs fabricated using industrial 45 nm node processing. Measurements of drain current as a function of gate voltage from 5 K to room temperature were conducted, and local current maxima and minima were observed leading to negative differential transconductance. When voltage-biasing the body terminal, NDTC appears at temperatures as high as 218 K; however, for measurements taken with the body terminal current-biased, NDTC appears at higher temperatures with peak-to-valley ratios (PVR) greater than two.

  3. 12-inch-wafer-scale CMOS active-pixel sensor for digital mammography

    NASA Astrophysics Data System (ADS)

    Heo, Sung Kyn; Kosonen, Jari; Hwang, Sung Ha; Kim, Tae Woo; Yun, Seungman; Kim, Ho Kyung

    2011-03-01

    This paper describes the development of an active-pixel sensor (APS) panel, which has a field-of-view of 23.1×17.1 cm and features 70-μm-sized pixels arranged in a 3300×2442 array format, for digital mammographic applications. The APS panel was realized on 12-inch wafers based on the standard complementary metal-oxide-semiconductor (CMOS) technology without physical tiling processes of several small-area sensor arrays. Electrical performance of the developed panel is described in terms of dark current, full-well capacity and leakage current map. For mammographic imaging, the optimized CsI:Tl scintillator is experimentally determined by being combined with the developed panel and analyzing im aging characteristics, such as modulation-transfer function, noise-power spectrum, detective quantum efficiency, image l ag, and contrast-detail analysis by using the CDMAM 3.4 phantom. With these results, we suggest that the developed CMOS-based detector can be used for conventional and advanced digital mammographic applications.

  4. A high speed, low power consumption LVDS interface for CMOS pixel sensors

    NASA Astrophysics Data System (ADS)

    Shi, Zhan; Tang, Zhenan; Tian, Yong; Pham, Hung; Valin, Isabelle; Jaaskelainen, Kimmo

    2015-01-01

    The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-μm CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW.

  5. CMOS image sensor noise reduction method for image signal processor in digital cameras and camera phones

    NASA Astrophysics Data System (ADS)

    Yoo, Youngjin; Lee, SeongDeok; Choe, Wonhee; Kim, Chang-Yong

    2007-02-01

    Digital images captured from CMOS image sensors suffer Gaussian noise and impulsive noise. To efficiently reduce the noise in Image Signal Processor (ISP), we analyze noise feature for imaging pipeline of ISP where noise reduction algorithm is performed. The Gaussian noise reduction and impulsive noise reduction method are proposed for proper ISP implementation in Bayer domain. The proposed method takes advantage of the analyzed noise feature to calculate noise reduction filter coefficients. Thus, noise is adaptively reduced according to the scene environment. Since noise is amplified and characteristic of noise varies while the image sensor signal undergoes several image processing steps, it is better to remove noise in earlier stage on imaging pipeline of ISP. Thus, noise reduction is carried out in Bayer domain on imaging pipeline of ISP. The method is tested on imaging pipeline of ISP and images captured from Samsung 2M CMOS image sensor test module. The experimental results show that the proposed method removes noise while effectively preserves edges.

  6. Spatial optical crosstalk in CMOS image sensors integrated with plasmonic color filters.

    PubMed

    Yu, Yan; Chen, Qin; Wen, Long; Hu, Xin; Zhang, Hui-Fang

    2015-08-24

    Imaging resolution of complementary metal oxide semiconductor (CMOS) image sensor (CIS) keeps increasing to approximately 7k × 4k. As a result, the pixel size shrinks down to sub-2μm, which greatly increases the spatial optical crosstalk. Recently, plasmonic color filter was proposed as an alternative to conventional colorant pigmented ones. However, there is little work on its size effect and the spatial optical crosstalk in a model of CIS. By numerical simulation, we investigate the size effect of nanocross array plasmonic color filters and analyze the spatial optical crosstalk of each pixel in a Bayer array of a CIS with a pixel size of 1μm. It is found that the small pixel size deteriorates the filtering performance of nanocross color filters and induces substantial spatial color crosstalk. By integrating the plasmonic filters in the low Metal layer in standard CMOS process, the crosstalk reduces significantly, which is compatible to pigmented filters in a state-of-the-art backside illumination CIS. PMID:26368174

  7. Wide tuning-range CMOS VCO based on a tunable active inductor

    NASA Astrophysics Data System (ADS)

    Babaei Kia, Hojjat; Khari A'ain, Abu; Grout, Ian

    2014-01-01

    In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is -85 dBc/Hz at a 1 MHz frequency offset. The output power is from -3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.

  8. Using Polynomials to Simplify Fixed Pattern Noise and Photometric Correction of Logarithmic CMOS Image Sensors

    PubMed Central

    Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

    2015-01-01

    An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient. PMID:26501287

  9. Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

    PubMed

    Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

    2015-01-01

    An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient. PMID:26501287

  10. A 16 × 16 CMOS Capacitive Biosensor Array Towards Detection of Single Bacterial Cell.

    PubMed

    Couniot, Numa; Francis, Laurent A; Flandre, Denis

    2016-04-01

    We present a 16 × 16 CMOS biosensor array aiming at impedance detection of whole-cell bacteria. Each 14 μm × 16 μm pixel comprises high-sensitive passivated microelectrodes connected to an innovative readout interface based on charge sharing principle for capacitance-to-voltage conversion and subthreshold gain stage to boost the sensitivity. Fabricated in a 0.25 μm CMOS process, the capacitive array was experimentally shown to perform accurate dielectric measurements of the electrolyte up to electrical conductivities of 0.05 S/m, with maximal sensitivity of 55 mV/fF and signal-to-noise ratio (SNR) of 37 dB. As biosensing proof of concept, real-time detection of Staphylococcus epidermidis binding events was experimentally demonstrated and provides detection limit of ca. 7 bacteria per pixel and sensitivity of 2.18 mV per bacterial cell. Models and simulations show good matching with experimental results and provide a comprehensive analysis of the sensor and circuit system. Advantages, challenges and limits of the proposed capacitive biosensor array are finally described with regards to literature. With its small area and low power consumption, the present capacitive array is particularly suitable for portable point-of-care (PoC) diagnosis tools and lab-on-chip (LoC) systems. PMID:25974947

  11. A Low-power CMOS BFSK Transceiver for Health Monitoring Systems

    PubMed Central

    Kim, Sungho; Lepkowski, William; Wilk, Seth J.; Thornton, Trevor J.; Bakkaloglu, Bertan

    2014-01-01

    A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of −70dBm and −98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10−3 at the input powers of −70dBm at 1.2V and −98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW. PMID:24473462

  12. A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

    PubMed

    Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

    2011-01-01

    A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10(-3) at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW. PMID:24473462

  13. A low-noise CMOS pixel direct charge sensor, Topmetal-II-

    NASA Astrophysics Data System (ADS)

    An, Mangmang; Chen, Chufeng; Gao, Chaosong; Han, Mikyung; Ji, Rong; Li, Xiaoting; Mei, Yuan; Sun, Quan; Sun, Xiangming; Wang, Kai; Xiao, Le; Yang, Ping; Zhou, Wei

    2016-02-01

    We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a < 15e- analog noise and a 200e- minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.

  14. A CMOS Energy Harvesting and Imaging (EHI) Active Pixel Sensor (APS) Imager for Retinal Prosthesis.

    PubMed

    Ay, S U

    2011-12-01

    A CMOS image sensor capable of imaging and energy harvesting on same focal plane is presented for retinal prosthesis. The energy harvesting and imaging (EHI) active pixel sensor (APS) imager was designed, fabricated, and tested in a standard 0.5 μm CMOS process. It has 54 × 50 array of 21 × 21 μm(2) EHI pixels, 10-bit supply boosted (SB) SAR ADC, and charge pump circuits consuming only 14.25 μW from 1.2 V and running at 7.4 frames per second. The supply boosting technique (SBT) is used in an analog signal chain of the EHI imager. Harvested solar energy on focal plane is stored on an off-chip capacitor with the help of a charge pump circuit with better than 70% efficiency. Energy harvesting efficiency of the EHI pixel was measured at different light levels. It was 9.4% while producing 0.41 V open circuit voltage. The EHI imager delivers 3.35 μW of power was delivered to a resistive load at maximum power point operation. The measured pixel array figure of merit (FoM) was 1.32 pW/frame/pixel while imager figure of merit (iFoM) including whole chip power consumption was 696 fJ/pixel/code for the EHI imager. PMID:23852551

  15. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

    NASA Astrophysics Data System (ADS)

    Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

    2016-05-01

    A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source–gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate–source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base–emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from ‑40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is ‑31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

  16. Digital spatial wavelength domain multiplexing (DSWDM) using a prism-grating-prism (PGP) and a CMOS imager: implementation and initial testing

    NASA Astrophysics Data System (ADS)

    Christiansen, Martin B.; Chen, Steve; Baldwin, Christopher S.; Niemczuk, John B.; Kiddy, Jason S.; Chen, Peter C.; Kopola, Harri K.; Aikio, Mauri; Suopajarvi, Pekka; Buckley, Steven G.

    2001-08-01

    A CMOS imager-based spectrometer is used to interrogate a network containing a large number of Bragg grating sensors on multiple fibers as part of a proprietary structural health monitoring system. The spectrometer uses a Prism-Grating-Prism (PGP) to spectrally separate serially multiplexed Bragg reflections on a single fiber. As a result, each Bragg grating produces a discrete spot on the CMOS imager that shifts horizontally as the Bragg grating experiences changes in strain or temperature. The reflected wavelength of the Bragg grating can be determined by finding the center of the spot produced. The use of a random addressing CMOS imager enables a flexible sampling rate. Some fibers can be interrogated at a high sampling rate while others can be interrogated at a lower sampling rate. However, the use of a CMOS camera brings several specific problems in terms of signal processing. These include a logarithmic pixel response, a low signal-to-noise ratio, the long pixel time constant, obtaining sufficient process priority for the control program, and proper selection of the window of interest. In this paper we investigate computer algorithms and hardware solutions to address these problems. We also present experimental data to validate these solutions including calibration data and initial field-testing data with 24 sensors on 4 fibers.

  17. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    PubMed Central

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  18. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

    PubMed

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  19. A low-power and small-area column-level ADC for high frame-rate CMOS pixel sensor

    NASA Astrophysics Data System (ADS)

    Zhang, L.; Morel, F.; Hu-Guo, C.; Hu, Y.

    2014-07-01

    CMOS pixel sensors (CPS) have demonstrated performances meeting the specifications of the International Linear Collider (ILC) vertex detector (VTX). This paper presents a low-power and small-area 4-bit column-level analog-to-digital converter (ADC) for CMOS pixel sensors. The ADC employs a self-timed trigger and completes the conversion by performing a multi-bit/step approximation. As in the outer layers of the ILC vertex detector hit density is of the order of a few per thousand, in order to reduce power consumption, the ADC is designed to work in two modes: active mode and idle mode. The ADC is fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. It is implemented with 48 columns in a sensor prototype. Each column ADC covers an area of 35 ×545 μm2. The measured temporal noise and Fixed Pattern Noise (FPN) are 0.96 mV and 0.40 mV, respectively. The power consumption, for a 3 V supply and 6.25 MS/s sampling rate, is 486 μW during idle time, which is by far the most frequently employed one. This value rises to 714 μW in the case of the active mode. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.49/-0.28 LSB and 0.29/-0.20 LSB, respectively.

  20. An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

    PubMed Central

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

    2015-01-01

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863