Sample records for n-well cmos process

  1. A low cost uncooled infrared microbolometer focal plane array using the CMOS n-well layer

    Microsoft Academic Search

    Deniz Sabuncuoglu Tezcan; Selim Eminoglu; Orhan Sevket Akar; Tayfun Akin

    2001-01-01

    This paper reports a low-cost, 256-pixel uncooled infrared microbolometer focal plane array (FPA) implemented using a 0.8 ?m CMOS process where the n-well layer is used as the active microbolometer material. The suspended n-well structure is obtained by simple front-end bulk etching of the fabricated CMOS dies, while the n-well region is protected from etching by electrochemical etch-stop technique within

  2. Status and perspectives of deep N-well 130 nm CMOS MAPS

    Microsoft Academic Search

    Valerio Re

    2009-01-01

    Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices

  3. A Low-Cost 128 128 Uncooled Infrared Detector Array in CMOS Process

    Microsoft Academic Search

    Selim Eminoglu; Mahmud Yusuf Tanrikulu; Tayfun Akin

    2008-01-01

    This paper discusses the implementation of a low-cost 128 times 128 uncooled infrared microbolometer detector array together with its integrated readout circuit (ROC) using a standard 0.35 mum n-well CMOS and post-CMOS MEMS processes. The detector array can be created with simple bulk-micromachining processes after the CMOS fabrication, without the need for any complicated lithography or deposition steps. The array

  4. Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

    SciTech Connect

    Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

    2011-10-20

    Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

  5. High-Q capacitors implemented in a CMOS process for low-power wireless applications

    Microsoft Academic Search

    Chih-Ming Hung; Yo-Chuol Ho; I-Chang Wu

    1998-01-01

    In a foundry 0.8-?m CMOS process, low-cost capacitors with a measured Q factor of around 50 at 3 GHz and high intrinsic capacitance\\/area (~200 nF\\/cm2) were demonstrated. When extrapolated to 900 MHz, the Q factor is greater than 100. The capacitors use a poly-to-n-well MOS structure which has been commonly dismissed for high-Q applications due to the high n-well sheet

  6. Photonic integration in a commercial scaled bulk-CMOS process

    E-print Network

    Kaertner, Franz X.

    We demonstrate the first photonic chip designed for a commercial bulk CMOS process (65 nm-node) using standard process layers combined with post-processing, enabling dense photonic integration with high-performance ...

  7. Process flow innovations for photonic device integration in CMOS

    NASA Astrophysics Data System (ADS)

    Beals, Mark; Michel, J.; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Kimerling, L. C.; Pomerene, A.; Carothers, D.; Beattie, J.; Kopa, A.; Apsel, A.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.

    2008-02-01

    Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.

  8. Quantification of Shallow-junction Dopant Loss during CMOS Process

    SciTech Connect

    Buh, G.H.; Park, T.; Jee, Y.; Hong, S.J.; Ryoo, C.; Yoo, J.; Lee, J.W.; Yon, G.H.; Jun, C.S.; Shin, Y.G.; Chung, U.-In; Moon, J.T. [Semiconductor R and D Center, Samsung Electronics Co., Ltd., Yongin-City, Gyeonggi-Do, 449-711 (Korea, Republic of)

    2005-09-09

    We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively.

  9. Abstract -CMOS processes that have been developed primarily for logic are now increasingly used for ana-

    E-print Network

    McNeill, John A.

    that provide a system development ap- proach for mixed signal circuitry on digital CMOS processes. Index TermsPage: 1 Abstract - CMOS processes that have been developed primarily for logic are now increasingly - Mixed analog-digital design, MOS inte- grated circuits, CMOS analog integrated circuits, an- alog

  10. Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation

    E-print Network

    Mohanty, Saraju P.

    Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits under Process Variation Abstract In sub-65nm CMOS technology, switching power and gate as well paths in a nano- CMOS transistor during power dissipation in different states of operation [4, 16, 24

  11. Reconfigurable Hybrid CMOS\\/Nanodevice Circuits for Image Processing

    Microsoft Academic Search

    Dmitri B. Strukov; Konstantin K. Likharev

    2007-01-01

    We have analyzed two options of using hybrid CMOS\\/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the

  12. Logic compatible process technology for embedded atom switches in CMOS

    NASA Astrophysics Data System (ADS)

    Okamoto, Koichiro; Tada, Munehiro; Banno, Naoki; Iguchi, Noriyuki; Sakamoto, Toshitsugu; Hada, Hiromitsu

    2015-05-01

    We have developed a CMOS logic compatible process for embedding Cu atom switches in a Cu/low-k back-end-of-line without degrading interconnect and switch performance characteristics. The key technologies are (i) burying a via-interlayer dielectric layer between the switches without voids, followed by surface planarization using chemical mechanical polishing, and (ii) introducing a Ta protective second top electrode, which realizes simultaneous via-openings to both the switches and the lower interconnects without degrading physical morphology and electric properties of the switches. The developed process enables us to integrate the atom switches on logic with only two additional masks at low cost.

  13. Portable design rules for bulk CMOS

    NASA Astrophysics Data System (ADS)

    Griswold, T. W.

    1982-10-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  14. Portable design rules for bulk CMOS

    NASA Technical Reports Server (NTRS)

    Griswold, T. W.

    1982-01-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  15. A modular merged technology process including submicron CMOS logic, nonvolatile memories, linear functions, and power components

    Microsoft Academic Search

    Michael Smayling; Jack Reynolds; Donald Redwine; Steve Keller; Georges Falessi

    1993-01-01

    A process technology which merges submicron 5-V CMOS logic with high-voltage CMOS for nonvolatile memory, analog functions, and power drivers is described. Memory functions utilize high-density X-cell EPROMs (electrically programmble read-only memories) and low-complexity EEPROMs (electrically erasable programmable read-only memories). Power components include 50-V drain-extended CMOS transistors, as well as isolated 60-V `HSD' (high-side-drive) and 90 V `LSD' (low-side-drive) power

  16. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

  17. Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process

    Microsoft Academic Search

    Jason S. Orcutt; Anatol Khilo; M. A. Popovic; C. W. Holzwarth; B. Moss; Hanqing Li; M. S. Dahlem; T. D. Bonifield; F. X. Kartner; E. P. Ippen; J. L. Hoyt; R. J. Ram; V. Stojanovic

    2008-01-01

    We demonstrate the first photonic chip designed in a commercial bulk CMOS process (65 nm node) using standard process layers combined with scalable post-processing, enabling dense photonic integration with high-performance microprocessor electronics.

  18. Design rules for RCA self-aligned silicon-gate CMOS/SOS process

    NASA Technical Reports Server (NTRS)

    1977-01-01

    The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

  19. Development of a radiation-hard CMOS process

    NASA Technical Reports Server (NTRS)

    Power, W. L.

    1983-01-01

    It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

  20. Noise performance and ionizing radiation tolerance of CMOS Monolithic Active Pixel Sensors using the 0.18?m CMOS process

    NASA Astrophysics Data System (ADS)

    Doering, D.; Baudot, J.; Deveaux, M.; Linnik, B.; Goffe, M.; Senyukov, S.; Strohauer, S.; Stroth, J.; Winter, M.

    2014-05-01

    CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few ?m), a detection efficiency of gtrsim99.9%, very low material budget (0.05% X0) and good radiation tolerance (gtrsim 1 Mrad, gtrsim 1014 neq/cm2) [1]. This recommends them as an interesting technology for various applications in heavy ion and particle physics. For the vertex detectors of CBM and ALICE, we are aiming at developing large scale sensors with an integration time of 30?s. Reaching this goal is eased by features available in CMOS-processes with 0.18?m feature size. To exploit this option, some sensor designs have been migrated from the previously used 0.35?m processes to this novel process. We report about our first findings with the devices obtained with a focus on noise and the tolerance to ionizing radiation.

  1. P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP

    E-print Network

    Mohanty, Saraju P.

    P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP Garima variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow of SRAM have become very critical with the advancement of CMOS technology which is used for its

  2. Fabrication of Wireless Micro Pressure Sensor Using the CMOS Process

    PubMed Central

    Dai, Ching-Liang; Lu, Po-Wei; Wu, Chyan-Chyi; Chang, Chienliu

    2009-01-01

    In this study, we fabricated a wireless micro FET (field effect transistor) pressure sensor based on the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The wireless micro pressure sensor is composed of a FET pressure sensor, an oscillator, an amplifier and an antenna. The oscillator is adopted to generate an ac signal, and the amplifier is used to amplify the sensing signal of the pressure sensor. The antenna is utilized to transmit the output voltage of the pressure sensor to a receiver. The pressure sensor is constructed by 16 sensing cells in parallel. Each sensing cell contains an MOS (metal oxide semiconductor) and a suspended membrane, which the gate of the MOS is the suspended membrane. The post-process employs etchants to etch the sacrificial layers in the pressure sensor for releasing the suspended membranes, and a LPCVD (low pressure chemical vapor deposition) parylene is adopted to seal the etch holes in the pressure. Experimental results show that the pressure sensor has a sensitivity of 0.08 mV/kPa in the pressure range of 0500 kPa and a wireless transmission distance of 10 cm. PMID:22291534

  3. Post assembly process development for Monolithic OptoPill integration on silicon CMOS

    E-print Network

    Lei, Yi-Shu Vivian, 1979-

    2004-01-01

    Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that ...

  4. Monolithic integration of high bandwidth waveguide coupled Ge photodiode in a photonic BiCMOS process

    NASA Astrophysics Data System (ADS)

    Lischke, S.; Knoll, D.; Zimmermann, L.

    2015-03-01

    Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and highspeed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at ?= 1.55?m, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

  5. Design of radiation hard CMOS APS image sensors in a 0.35-um standard process

    Microsoft Academic Search

    El-Sayed I. Eid; Tony Y. Chan; Eric R. Fossum; Richard H. Tsai; Robert Spagnuolo; John J. Deily

    2001-01-01

    A CMOS APS Image sensor test chip was designed employing the physical design techniques of enclosed geometry and guard ring, and according to the design rules of a 0.35-micrometers CMOS standard process that has a gate oxide thickness of approximately 7.0 nm. Three sets of radiation tolerant photodiode active pixels were developed employing these design techniques. They are N-type, and

  6. Wide intrascene dynamic range CMOS APS using dual sampling

    Microsoft Academic Search

    Orly Yadid-Pecht; Eric R. Fossum

    1997-01-01

    A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 6464 element prototype sensor with dual output architecture was fabricated using a 1.2 ?m n-well CMOS process with 20.4 ?m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding

  7. A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS

    NASA Astrophysics Data System (ADS)

    Yasaitis, John A.; Judy, Michael; Brosnihan, Tim; Garone, Peter M.; Pokrovskiy, Nikolay; Sniderman, Debbie; Limb, Scott; Howe, Roger T.; Boser, Bernhard E.; Palaniapan, Moorthi; Jiang, Xuesong; Bhave, Sunil

    2003-01-01

    A new MEMS process module, called Mod MEMS, has been developed to monolithically integrate thick (5-10um), multilayer polysilicon MEMS structures with sub-micron CMOS. This process is particularly useful for advanced inertial MEMS products such as automotive airbag accelerometers where reduced cost and increased functionality is required, or low cost, high performance gyroscopes where thick polysilicon (>6um) and CMOS integration is required to increase poly mass and stiffness, and reduce electrical parasitics in order to optimize angular rate sensing. In this paper we will describe the new modular process flow, development of the critical unit process steps, integration of the module with a foundry sub-micron CMOS process, and provide test data on several inertial designs fabricated with this process.

  8. A new leakage mechanism of Co salicide and optimized process conditions [for CMOS

    Microsoft Academic Search

    Ken-ichi Goto; Atsuo Fushida; Junichi Watanabe; Takae Sukegawa; Yoko Tada; Tomoji Nakamura; Tatsuya Yamazaki; Toshihiro Sugii

    1999-01-01

    We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-?m CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo

  9. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 10, OCTOBER 1997 1759 CMOS Active Pixel Sensor with On-Chip Successive

    E-print Network

    Fossum, Eric R.

    ) is reported. A 64 2 64 element CMOS APS implemented in a 1.2-m n-well single-poly, double-metal process-s/ksample and occupy 0.05 mm2 of chip area. I. INTRODUCTION RECENTLY, CMOS active pixel sensors (APS) have shown. Architecture of CMOS APS with on-chip column-parallel ADC. [e.g., 30 samples/s]. We have been pursuing column

  10. Converting a bulk radiation-hardened BiCMOS technology into a dielectrically-isolated process

    Microsoft Academic Search

    M. Delaus; D. Emily; B. Mappes; R. Pease

    1993-01-01

    A radiation-hardened dielectrically isolated BiCMOS process has been developed by retrofitting dielectric isolation to an existing radiation-hardened JI (junction-isolated) process. The process is fabricated on a bonded-wafer silicon-on-insulator (SOI) substrate and employs deep trenches for lateral device isolation. The isolation technique employed is similar to that used on advanced commercial complementary-bipolar processes. Trench\\/substrate induced defects are sensitive to the device

  11. Ionizing Radiation Effects on CMOS Imagers Manufactured in Deep Submicron Process

    E-print Network

    Mailhes, Corinne

    , ionizing radiation, total dose, dark current, STI, hardening by design, RHDB 1. INTRODUCTION Ionizing a large dynamic range. This can significantly impact the radiation hardness of "in-pixel" devices whichIonizing Radiation Effects on CMOS Imagers Manufactured in Deep Submicron Process Vincent Goiffona

  12. Process-dependent thin-film thermal conductivities for thermal CMOS MEMS

    Microsoft Academic Search

    Martin von Arx; Oliver Paul; Henry Baltes

    2000-01-01

    The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

  13. Impact of Layout on 90nm CMOS Process Parameter Fluctuations Liang-Teck Pang, Borivoje Nikolic

    E-print Network

    Nikolic, Borivoje

    Impact of Layout on 90nm CMOS Process Parameter Fluctuations Liang-Teck Pang, Borivoje Nikolic University of California, Berkeley, USA Abstract A test chip has been built to study the effects of layout magnitude of WID and D2D variations, its spatial correlation, and the impact of layout styles. The chip

  14. Advances on NiPt SALICIDE process optimization for 28nm CMOS manufacturing

    Microsoft Academic Search

    Yi-Wei Chen; Nien-Ting Ho; J. Lai; J. F. Lin; C. C. Huang; J. Y. Wu; J. M. M. Chu; J. W. Butterbaugh

    2010-01-01

    A NiPt silicide for CMOS ohmic contact formation process extension from 45nm to 28nm node has been achieved through co-optimization of NiPt alloy deposition thickness, Pt additive amount and complementarty wet selective etch process. In this study, it was found thicker NiPt film will lead to lower sheet resistance (Rs)but will reach saturation; meanwhile, will increase NiSi encroachment. To increase

  15. A 1-V 5 ?W CMOS-opamp with bulk-driven input transistors

    Microsoft Academic Search

    K. Lasanen; E. Raisanen-Ruotsalainen; J. Kostamovaara

    2000-01-01

    In this paper, a low-power CMOS operational amplifier for biomedical instrumentation operating with a 1-V supply is described. Large input common-mode range (CMR) is achieved utilizing bulk-driven PMOS-transistors as an input differential pair of the opamp. The opamp was fabricated in a 0.35 ?m n-well double-poly CMOS process with threshold voltages of 0.5 V and 0.65 V. The open-loop gain

  16. A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors

    Microsoft Academic Search

    Christian Menolfi; Qiuting Huang

    1997-01-01

    A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-?m single-poly n-well CMOS process.

  17. Design of 1-THz field effect transistor detectors in 180-nm standard CMOS process

    NASA Astrophysics Data System (ADS)

    Liu, Zhao-yang; Liu, Li-yuan; Wu, Nan-jian

    2013-08-01

    This paper presents a design of 1-THz imaging detectors implemented in 180-nm standard CMOS process. Device simulator is adopted to simulate the performances of the detectors and the results are well consistent with the theoretical predictions. An on-chip patch antenna is designed aided by HFSS. The simulated peak directivity and gain of antenna are 6.9dBi and 4.4dBi, respectively. The -10dB impedance bandwidth of the antenna is 28 GHz, which corresponds to 2.8% relative bandwidth. To improve power transfer efficiency, we extract the input impedance of the MOSFET and design a matching network inserted between the MOSFET and antenna. Imaging pixels have been arranged in a 3 x 5 array in 180-nm standard CMOS process.

  18. 50-V LCD driver integrated in standard 5-V CMOS process

    Microsoft Academic Search

    V. Valencic; H. Ballan; P. Deval; B. Hochet; M. Declercq

    1994-01-01

    A multi-purpose row\\/column driver for panel Liquid Crystal Displays (LCD) has integrated in a standard unmodified low-voltage 2 ?m CMOS process. Driving capability of 50 V @ 200 kHz data-in clock rate and internal bias high-voltage generation are the main features of the driver. The circuit architecture is such as to allow parallel as well as multiplexed LCD driver applications

  19. A Low-noise Low-offset Op Amp in 0.35?m CMOS Process

    Microsoft Academic Search

    Zhineng Zhu; Raghu Tumati; Scott Collins; Rosemary Smith; David E. Kotecki

    2006-01-01

    This paper describes a new structure for a low-noise, low-offset, high-speed operational amplifier with a bandwidth up to 10 MHz, designed in a 0.35 ?m CMOS process. Design strategies are discussed for minimizing both thermal noise and flicker noise. Special techniques are investigated to maximize the unity gain bandwidth. A digital trimming method is explored to correct for a 10

  20. A novel pH sensitive ISFET with on chip temperature sensing using CMOS standard process

    Microsoft Academic Search

    Yuan-Lung Chin; Jung-Chuan Chou; Tai-Ping Sun; Wen-Yaw Chung; Shen-Kan Hsiung

    2001-01-01

    A monolithic chip processing method is reported, which includes the ion sensitive field effect transistor (ISFET) of the pH sensor, pn diode of temperature sensor and readout circuit using 0.5?m double poly double metal (DPDM) standard CMOS product with UMC IC foundry company. We have designed a planar diffused silicon diode on a n-channel pH sensitive ISFET sensor to act

  1. Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

    Microsoft Academic Search

    T. Suligoj; J. K. O. Sin; K. L. Wang

    2005-01-01

    Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (CBC)

  2. P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP

    Microsoft Academic Search

    Garima Thakral; Saraju P. Mohanty; Dhruva Ghai; Dhiraj K. Pradhan

    2010-01-01

    In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual-VTh assignment based on a novel statistical Design of Experiments-Integer Linear

  3. Current mode integrators and their applications in low-voltage high frequency CMOS signal processing

    E-print Network

    Smith, Sterling Lane

    1993-01-01

    accuracy and linearity. To further complicate the design engineer's job, tbe power supply voltage is limited to 5v for most systems. The small supply voltages reduce the available signal swing in the analog circuits and limit the use of cascoding... of the requirements for the degree of MASTER OF SCIENCE December 1993 Major Subject: Electrical Engineering CURRENT MODE INTEGRATORS AND THEIR APPLICATIONS IN LOW-VOLTAGE HIGH FREQUENCY CMOS SIGNAL PROCESSING A Thesis by STERLING LANE SMITH Submitted to Texas...

  4. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1977-01-01

    Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

  5. Lithography with infrared illumination alignment for advanced BiCMOS backside processing

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Schulz, K.; Behrendt, U.; Wietstruck, M.; Kaynak, M.; Marschmeyer, S.; Tillack, B.

    2014-10-01

    Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP's 0.25/0.13 ?m high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVGNT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 ?m across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP's 0.25/0.13 ?m SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

  6. Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

    NASA Technical Reports Server (NTRS)

    Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

    2009-01-01

    There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

  7. A process/physics-based compact model for nonclassical CMOS device and circuit design

    NASA Astrophysics Data System (ADS)

    Fossum, J. G.; Ge, L.; Chiang, M.-H.; Trivedi, V. P.; Chowdhury, M. M.; Mathew, L.; Workman, G. O.; Nguyen, B.-Y.

    2004-06-01

    A process/physics-based compact model (UFDG) for nonclassical MOSFETs having ultra-thin Si bodies (UTB) is overviewed. The model, in essence, is a compact Poisson-Schrdinger solver, including accountings for short-channel effects, and is applicable to nanoscale fully depleted (FD) SOI MOSFETs as well as generic double-gate (DG) devices. The utility of UFDG in nonclassical CMOS device design, as well as circuit design, is stressed, and demonstrated by using it in Spice3 to design UTB MOSFETs and to project extremely scaled DG and FD/SOI CMOS performances. Also, calibration of UFDG to fabricated FinFETs yields new physical insights about these potentially viable nanoscale DG devices, and about model requirements for them.

  8. 21 psec switching 0.1 ?m-CMOS at room temperature using high performance Co salicide process

    Microsoft Academic Search

    T. Yamazaki; K. Goto; T. Fukano; Y. Nara; T. Sugii; T. Ito

    1993-01-01

    In this paper we report a record of 0.1 ?m-CMOS switching delay of 21 psec per gate at room temperature operation. Good subthreshold characteristics are achieved for 0.1 pm gate length n-MOS and p-MOS. Conventional Ti, Pt and Co self-aligned silicide process (salicide) degraded the 0.1 pm CMOS switching delay because the gate sheet resistances increased at fine-line. In contrast,

  9. Photo-Spectrometer Realized In A Standard Cmos Ic Process

    DOEpatents

    Simpson, Michael L. (Knoxville, TN); Ericson, M. Nance (Knoxville, TN); Dress, William B. (Knoxville, TN); Jellison, Gerald E. (Oak Ridge, TN); Sitter, Jr., David N. (Tucson, AZ); Wintenberg, Alan L. (Knoxville, TN)

    1999-10-12

    A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

  10. A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration

    PubMed Central

    Chen, Chun-Chi; Lin, Yi

    2014-01-01

    This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-?m 2P4M CMOS process, and a robust resolution of 0.05 C and dissipation of 25 ?W were achieved at a sample rate of 10 samples/s. An inaccuracy of ?0.35 C to 1.35 C was achieved after one-point calibration at temperatures ranging from ?40 C to 120 C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

  11. A linearity-enhanced time-domain CMOS thermostat with process-variation calibration.

    PubMed

    Chen, Chun-Chi; Lin, Yi

    2014-01-01

    This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-?m 2P4M CMOS process, and a robust resolution of 0.05 C and dissipation of 25 ?W were achieved at a sample rate of 10 samples/s. An inaccuracy of -0.35 C to 1.35 C was achieved after one-point calibration at temperatures ranging from -40 C to 120 C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs. PMID:25310469

  12. The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

    PubMed Central

    2010-01-01

    Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 ?V/K for p-leg and ?94 ?V/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature. PMID:21076666

  13. On-Chip RF Pulse Power Detector Using FIB as a Post-CMOS Fabrication Process

    Microsoft Academic Search

    Woochul Jeon; Todd M. Firestone; John C. Rodgers; John Melngailis

    2006-01-01

    RF pulse power detectors on a CMOS chip may be useful in studying and mitigating the effects of unwanted RF radiation on chip performance. Focused ion beam (FIB) milling and ion-induced deposition were used as post-fabrication steps to build Schottky diodes on the CMOS chips fabricated using MOSIS. The standard CMOS layout of chips had Schottky diodes and was fabricated

  14. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    PubMed

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 ?m CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/?Newton. The overall power dissipation is 132.8 ?W. PMID:25314707

  15. Design of CMOS-APS smart imagers with mixed signal processing and analysis of their transfer characteristics

    Microsoft Academic Search

    Karel Fliegel; Jan Svihlk; Martin Rerbek

    2006-01-01

    CMOS imagers based on Active Pixel Sensors (APS) are very important among others because of their possible technical innovations leading to ultra-low power image acquisition or efficient on-chip image preprocessing. Implementation of the image processing tasks (focal plane preprocessing and subsequent image processing) can be done effectively only with the consideration of known transfer characteristics of the imager itself. Geometrical

  16. Research of photodetector and its array in standard CMOS technology

    Microsoft Academic Search

    Jiantao Bian; Xiang Cheng; Chao Chen

    2007-01-01

    Silicon photodetector is easy to be integrated with all kinds of Silicon IC to get monolithically OEIC. And the photodetector array is also widely applied. A kind of CMOS-process-compatible N+\\/N-Well\\/P-Sub photodetector and its array are analyzed in this paper. Depended on the basic time-dependent equations of photodetctor and analyzed by Laplace transform method, the intrinsic frequency response characteristic is numerically

  17. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    NASA Astrophysics Data System (ADS)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  18. Design and fabrication of micromirror for MOEMS devices by CMOS-MEMS common process

    NASA Astrophysics Data System (ADS)

    Tsai, Chien-Chung; Cheng, Pao-Ting; Tseng, Yao-Chen

    2005-01-01

    This paper would propose the design and fabrication methodology of micro mirror for MOEMS devices by CMOS-MEMS common process of CIC, Taiwan. The outstanding features of CMOS-MEMS are mass production, low connections, high precision and easy to combine the circuit with low noise. A {2X3} opposite type Micro Array Thermal Actuator, MATA, is applied to drive the micro mirror for rotation. Such MOEMS would be as a high precision micro positioning device applied on the micro fabrication equipment. A novel elevating structure for the lift of micro mirror is proposed. Warped suspension beam is originally applied on elevating a micro mirror in this work. A modified elevating structure is proposed to improve the lift of micro mirror from 1.1 ?m to 14 ?m compared to original design. There are three parameters, width, length of the modified elevating structure and the number of single thermal actuators of parallel type MATA, for the performance simulation. The effects of operation voltage varied with three parameters on the displacement of Z axis direction are investigated. The optimum dimension of width, length of modified elevating structure and numbers of single thermal actuator are 10 ?m, 240 ?m and {1x4} MATA, respectively. Finally, comparisons of mask configuration and real part of finished devices are discussed by SEM photos. The surface quality of micro mirror is almost perfect and the material of micro mirror is aluminum.

  19. Application of monolithic CMOS switched-capacitor filters and amplifiers for signal processing

    NASA Astrophysics Data System (ADS)

    Hampel, D.; Bradshaw, J. L.

    1980-10-01

    A custom monolithic CMOS array was designed and integrated for use in meeting the analog conditioning requirements for microsignal processors. These processors are used in 'smart' sensors for the purposes of detection and classification. Constrained by very low power dissipation requirements, this array provides a variety of bandpass and low-pass filter functions and programmable CMOS operational amplifiers for AGC amplification for signals in the audio region. Specifically, the custom chip contains 12 poles based on switched-capacitor techniques partitioned into a six-pole low-pass filter ladder configuration, and three two-pole bandpass and low-pass state variable filter configurations. The amplifiers were used in conjunction with an associated microprocessor for software-controlled AGC. A mask change can provide for different capacitor ratios, and hence, frequency responses. Also, the switch clock rates can be used to vary the filter characteristics. Operating from a single +5 V supply, this standard process chip dissipates about 2 mW, and meets all predicted performance characteristics.

  20. Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

    PubMed

    Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

    2015-01-01

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

  1. Bipolar process integration for a 0.25 ?m BiCMOS SRAM technology using shallow trench isolation

    Microsoft Academic Search

    H. Tian; A. Perera; C. Subramanian; D. Pham; J. Damiano; J. Scott; T. McNelly; R. Zaman; J. Hayden

    1997-01-01

    This paper describes bipolar process integration issues for a 0.25 ?m BiCMOS SRAM technology which uses shallow trench isolation. In particular, we discuss: (1) minimization of arsenic buried layer induced surface step at the trench edge and its impact on gate poly bridging and bipolar collector to emitter leakage; (2) elimination of end of range damage from the selectively implanted

  2. Low power 1 GHz charge pump phase-locked loop in 0.18 m CMOS process

    Microsoft Academic Search

    A. Zaziabl

    2010-01-01

    Demand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because

  3. A 33-mpixel 120-fps CMOS image sensor using 0.11-?m CIS process

    NASA Astrophysics Data System (ADS)

    Yasue, Toshio; Hayashida, Tetsuya; Yonai, Jun; Kitamura, Kazuya; Watabe, Toshihisa; Ootake, Hiroshi; Shimamoto, Hiroshi; Kosugi, Tomohiko; Watanabe, Takashi; Aoyama, Satoshi; Kawahito, Shoji

    2014-05-01

    We have been researching and developing a CMOS image sensor that has 2.8 ?m x 2.8 ?m pixel, 33-Mpixel resolution (7680 horizontal pixels x 4320 vertical pixels), 120-fps frame rate, and 12-bit analog-to-digital converter for "8K Super Hi-Vision." In order to improve its sensitivity, we used a 0.11-?m nanofabricated process and attempted to increase the conversion gain from an electron charge to a voltage in the pixel. The prototyped image sensor shows a sensitivity of 2.4 V/lxs, which is 1.6 times higher than that of a conventional image sensor. This image sensor also realized the input-referred random noise as low as 2.1 e-rms.

  4. Monolithic process for co-integration of GaAs MESFET and silicon CMOS devices and circuits

    NASA Astrophysics Data System (ADS)

    Shichijo, Hisashi; Taddiken, Albert H.; Kao, Yung-Chung; Matyi, Richard

    1990-03-01

    A monolithic process to cointegrate Si CMOS and GaAs MESFET devices and circuits on a silicon chip through epitaxial growth of a GaAs layer on a prefabricated Si wafer is described. By embedding the GaAs layer in Si recesses in selected regions of a Si wafer, the cointegration has been realized in a coplanar structure appropriate for IC processing. On a monolithically integrated wafer, a 2-micron gate length Si CMOS ring oscillator showed a minimum delay of 570 ps/gate, and a 1-micron gate GaAs MESFET BFL ring oscillator had a minimum delay of 68 ps/gate. These results indicate that the individual device speed is not degraded by monolithic integration. Some changes in threshold voltage, however, were observed for Si CMOS devices after the GaAs device fabrication. A composite ring oscillator consisting of a string of Si CMOS inverters and a string of GaAs MESFET inverters connected in a ring has been successfully fabricated.

  5. A CMOS-compatible 2-D vertical Hall magnetic-field sensor using active carrier confinement and post-process micromachining

    Microsoft Academic Search

    M Paranjape; L. M Landsberger; Mojtaba Kahrizi

    1996-01-01

    This work presents a CMOS-based magnetic-field sensor for the detection of magnetic-field vector components that occur parallel to the chip surface. The device employs two vertical Hall plate structures embedded in the substrate orthogonal to each other. The sensor is fabricated using a standard 3 ?m CMOS process provided by a commercial integrated circuit (IC) manufacturer, and a maskless post-process

  6. Current mode integrators and their applications in low-voltage high frequency CMOS signal processing

    E-print Network

    Smith, Sterling Lane

    1993-01-01

    Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented.. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve...

  7. A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology

    Microsoft Academic Search

    Erik Ojefors; Ullrich R. Pfeiffer; Alvydas Lisauskas; Hartmut G. Roskos

    2009-01-01

    A focal-plane array (FPA) for room-temperature detection of 0.65-THz radiation has been fully integrated in a low-cost 0.25 mum CMOS process technology. The circuit architecture is based on the principle of distributed resistive self-mixing and facilitates broadband direct detection well beyond the cutoff frequency of the technology. The 3 timesZ 5 pixel array consists of differential on-chip patch antennas, NMOS

  8. The First Fully Integrated Quad-Band GSM\\/GPRS Receiver in a 90-nm Digital CMOS Process

    Microsoft Academic Search

    Khurram Muhammad; Yo-Chuol Ho; Terry L. Mayhugh; Chih-Ming Hung; T. Jung; Imtinan Elahi; Charles Lin; Irene Deng; C. Fernando; J. L. Wallberg; S. K. Vemulapalli; S. Larson; T. Murphy; D. Leipold; P. Cruise; J. Jaehnig; Meng-Chang Lee; Roman Staszewski; K. Maggio

    2006-01-01

    We present the receiver in the first single-chip GSM\\/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive

  9. Timing design and image processing of CMOS sensor LUPA-4000 based on FPGA

    NASA Astrophysics Data System (ADS)

    Xin, Li

    2014-11-01

    This article describes a method of the timing sequence design for CMOS image sensor LUPA-4000. A FPGA based imaging system with the function of adjustable integration time, multiple-slope integration, parallel integration an reading, windowing readout has been designed. This design can satisfy the frequency of 66M limit frequency of LUPA-4000 and 20 frames of a second. As the fixed noise of LUPA-4000 is aloud and the image is not clear, an efficient real-time image processing algorithm is also described in this paper. First a black image should be acquired as the fixed noise image. The real-time images can be send out after subtracting the noise image. This method can effectively eliminate the fixed noise o f the image, as the same time, the original image information has been maintained in the maximum degree. The test experiments on FPGA shows this design can drive LUPA-4000 working properly. Also this design takes full advantage of the accessibility features of the device, which provides a wider dynamic range and more flexible application of the device. The image sensor driven by this design improves imaging quality, which can be used for space exploration, especially for small space dynamic target tracking.

  10. Designing a Ring-VCO for RFID Transponders in 0.18??m CMOS Process

    PubMed Central

    Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

    2014-01-01

    In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42?GHz operated active RFID transponders compatible with IEEE 802.11?b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18??m process is adopted for designing the circuit with 1.5?V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.52.54?GHz and dissipates 2.47?mW of power. It exhibits a phase noise of ?126.62?dBc/Hz at 25?MHz offset from 2.42?GHz carrier frequency. PMID:24587731

  11. IEEE TRANSACTIONS ON NUCLEAR SCIENCE. VOL. 43. NO.3. JUNE 19'16 CMOS Charged Particle Spectrometers

    E-print Network

    Fossum, Eric R.

    region. Space Technology Research Vehicle-2 (STRV2) APS CMOS prawn and electron spectrometer design the numher of cell upsets. III. CMOS APS SPECTROMETER DESIGN Current CMOS chip spectrometer designs are both fahricated in 1.2 !J-II1 n-well technology through MOS Implementation System (MOSIS). The CMOS APS

  12. Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

    NASA Astrophysics Data System (ADS)

    Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

    2014-06-01

    A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

  13. Novel processes for modular integration of silicon-germanium MEMS with CMOS electronics

    NASA Astrophysics Data System (ADS)

    Low, Carrie Wing-Zin

    Equipment control, process development and materials characterization for LPCVD poly-SiGe for MEMS applications are investigated in this work. In order to develop a repeatable process in an academic laboratory, equipment monitoring methods are implemented and new process gases are explored. With the dopant gas BCl3, the design-of-experiments technique is used to study the dependencies of deposition rate, resistivity, average residual stress, strain gradient and wet etch rate in hydrogen-peroxide. Structural layer requirements for general MEMS applications are met within the process temperature constraint imposed by CMOS electronics. However, the strain gradient required for inertial sensor applications is difficult to achieve with as-deposited films. Approaches to reduce the strain gradient of LPCVD poly-SiGe are investigated. Correlation between the strain gradient and film microstructure is found using stress-depth profiling and cross-sectional TEM analysis. The effects of film deposition conditions on film microstructure are also determined. Boron-doped poly-SiGe films generally have vertically oriented grains---either conical or columnar in shape. Films with conical grain structure have large strain gradient due to highly compressive stress in the lower (initially deposited) region of the film. Films with small strain gradient usually have columnar grain structure with low defect density. It is also found that the uniformity of films deposited in a batch LPCVD reactor can be improved by increasing the deposited film thickness, using a proper seeding layer, and/or depositing the film in multiple layers. The best strain gradient achieved in our academic research laboratory is 1.1x10-6 mum-1 for a 3.5 mum thick film deposited at 410C in 8 hours, with a worst-case variation across a 150 mm-diameter wafer of 1.6x10 -5 mum-1 and a worse-case variation across a load of twenty-five wafers of 7x10-5 mum-1. The effects of post-deposition annealing and argon implantation on mechanical properties are also studied. While the as-deposited film can achieve the desired mechanical properties, post-deposition processing at elevated temperatures can degrade the strain gradient.

  14. Analysis of pixel circuits in CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Mei, Zou; Chen, Nan; Yao, Li-bin

    2015-04-01

    CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-?m CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.

  15. Which Photodiode to Use: A Comparison of CMOS-Compatible Structures

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2010-01-01

    While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n+/p-sub, n-well/p-sub and p+/n-well/p-sub. All structures were fabricated in a 0.5 ?m 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricatedthe standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 and 1.6 over the n+/p-sub and p+/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 and 1.2 improvement over the n+/p-sub and p+/n-well/p-sub diodes, respectively) while the p+/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity. PMID:20454596

  16. A 12.3mW 12.5Gb\\/s Complete Transceiver in 65-nm CMOS Process

    Microsoft Academic Search

    Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Noboru Masuda; Takashi Takemoto; Fumio Yuki; Tatsuya Saito

    2010-01-01

    A 12.3-mW 12.5-Gb\\/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer\\/demultiplexer (MUX\\/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector

  17. Additive electroplating technology as a post-CMOS process for the production of MEMS acceleration-threshold switches for transportation applications

    NASA Astrophysics Data System (ADS)

    Michaelis, Sven; Timme, Hans-Jrg; Wycisk, Michael; Binder, Josef

    2000-06-01

    This paper presents an acceleration-threshold sensor fabricated with an electroplating technology which can be integrated on top of a pre-processed CMOS signal processing circuit. The device can be manufactured using a standard low-cost CMOS production line and then adding the mechanical sensor elements via a specialized back-end process. This makes the system especially interesting for automotive applications, such as airbag safety systems or transportation shock monitoring systems, where smaller size, improved functionality, high reliability and low costs are important.

  18. New energy recovery CMOS XNOR\\/XOR gates

    Microsoft Academic Search

    Y. Xu; A. Srivastava

    2007-01-01

    In this paper, new energy recovery CMOS XNOR\\/XOR gates have been proposed. These circuits have been simulated using Cadence\\/Spectre along with three other XNOR\\/XOR gates. The results show that the new CMOS XNOR\\/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR\\/XOR gates fabricated in standard 0.5 mum n-well

  19. A 60GHz double-balanced homodyne down-converter in 65-nm CMOS process

    Microsoft Academic Search

    Pooyan Sakian; Reza Mahmoudi; Paul van Zeijl; Maarten Lont; Arthur van Roermund

    2009-01-01

    A fully differential 60 GHz down-converter in 65-nm CMOS technology is presented. The circuit, including the buffers, draws 5 mA from a 1.2 V supply. The measured power conversion gain is 4 dB with an IF 3 dB bandwidth of 1.3 GHz. Measured IIP2 and IIP3 are 16.6 and -6 dBm respectively. The mixer will be part of a 60

  20. Low-Power CMOS Interface for Recording and Processing Very Low Amplitude Signals

    Microsoft Academic Search

    A. Harb; Y. Hu; M. Sawan; A. Abdelkerim; M. M. Elhilali

    2004-01-01

    In this paper, we describe a low-power low-voltage CMOS very low signal acquisition analog front-end of sensor electronic interfaces. These interfaces are mainly dedicated to biomedical implantable devices. In this work, we focus on the implantable bladder controller. Since the nerve signal has very low amplitude and low frequency, it is, at first fed to a low-voltage chopper amplifier to

  1. A CCD\\/CMOS-based imager with integrated focal plane signal processing

    Microsoft Academic Search

    Craig L. Keast; Charles G. Sodini

    1993-01-01

    Using a CCD\\/CMOS technology, a fully parallel 44 focal plane processor, which performs image acquisition, smoothing, and segmentation, has been fabricated and characterized. In this chip, image brightness is converted into signal charge using charge-coupled-device (CCD) imaging techniques. The Gaussian smoothing operation is approximated by the repeated application of a simple nearest-neighbor binomial convolution mask, realizing the first known use

  2. An ultra low power CMOS motion detector

    Microsoft Academic Search

    Sang-Hyeok Yang; Kyoung-Bum Kim; Eung-Ju Kim; Kwang-Hyun Baek; Suki Kim

    2009-01-01

    This paper proposes a CMOS motion detector which consumes extremely low power. CMOS image sensor pixels in this motion detector senses image and image data are converted into just one-bit by using clocked comparators. Because using one-bit data makes additional processing units simple, total power consumption of this CMOS motion detector can be reduced. That is, internal memory which is

  3. CMOS PIN fiber receiver and DVD OEIC

    Microsoft Academic Search

    A. Ghazi; T. Heide; H. Zimmermann; P. Seegebrecht

    1999-01-01

    Two monolithically integrated PIN CMOS OEICs (optoelectronic integrated circuits) are presented: A high-speed CMOS PIN fiber receiver for optical data transmission and optical interconnects and a CMOS PIN OEIC for optical storage systems. Both OEICs were integrated in a 1.0 ?m twin-well CMOS-process, using PIN-photodiodes as photodetectors. For the high-speed fiber receiver a NRZ data rate of 622 Mbit\\/s is

  4. CMOS and post-CMOS on-chip microwave pulse power detectors

    Microsoft Academic Search

    Woochul Jeon; John Melngailis

    2006-01-01

    Schottky diode microwave pulse power detectors were fabricated by both a CMOS process and a post-CMOS process. Focused ion beam (FIB) milling and ion-induced deposition were used for the post-CMOS fabrication. Fabricated detectors were tested under RF direct injection and RF radiation. CMOS fabricated Schotty diode power detectors had 820ns pulse response time, 36dBm dynamic range, and began to detect

  5. Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0.18 CMOS Technology

    E-print Network

    Lee, Jong Duk

    #12;Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0 been investigated in the CMOS APS with test patterns fabricated with the 0.18 CMOS technology. We sensors (APS), fabricated using a standard CMOS process, have advantages of low power consumption, low

  6. MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 ?m CMOS process

    NASA Astrophysics Data System (ADS)

    Martin, P.; Royet, A. S.; Guellec, F.; Ghibaudo, G.

    2011-08-01

    Design and simulation of mixed analog-digital circuits working at low temperature, typically between 77 K and 200 K, requires advanced compact models incorporating most of the physical effects occurring in cooled MOSFET. In this paper, some specific effects, such as freeze-out in LDD regions or quantization of the inversion layer in silicon sub-bands, observed at intermediate temperature are described and tentatively modeled. This study is performed on a dual gate oxide CMOS technology with 0.18 ?m/1.8 V and 0.35 ?m/3.3 V MOSFET transistors. Some improvements of compact models will allow a very precise description of MOS transistors for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures. Data on low frequency noise and transistor matching at low temperature are also presented.

  7. FDTD-based optical simulations methodology for CMOS image sensors pixels architecture and process optimization

    NASA Astrophysics Data System (ADS)

    Hirigoyen, Flavien; Crocherie, Axel; Vaillant, Jrme M.; Cazaux, Yvon

    2008-02-01

    This paper presents a new FDTD-based optical simulation model dedicated to describe the optical performances of CMOS image sensors taking into account diffraction effects. Following market trend and industrialization constraints, CMOS image sensors must be easily embedded into even smaller packages, which are now equipped with auto-focus and short-term coming zoom system. Due to miniaturization, the ray-tracing models used to evaluate pixels optical performances are not accurate anymore to describe the light propagation inside the sensor, because of diffraction effects. Thus we adopt a more fundamental description to take into account these diffraction effects: we chose to use Maxwell-Boltzmann based modeling to compute the propagation of light, and to use a software with an FDTD-based (Finite Difference Time Domain) engine to solve this propagation. We present in this article the complete methodology of this modeling: on one hand incoherent plane waves are propagated to approximate a product-use diffuse-like source, on the other hand we use periodic conditions to limit the size of the simulated model and both memory and computation time. After having presented the correlation of the model with measurements we will illustrate its use in the case of the optimization of a 1.75?m pixel.

  8. Highly sensitive Hall sensor in CMOS technology

    Microsoft Academic Search

    H Blanchard; F De Montmollin; J Hubin; R. S Popovic

    2000-01-01

    We present a highly sensitive Hall device fabricated in a standard CMOS technology and combined with integrated flux concentrators acting as magnetic amplifiers. The active area of the Hall plate is in a buried n-well with a shape optimized by removing the parts less sensitive to the magnetic field. The effect of the shape of the concentrators is studied. This

  9. Prediction of CMOS APS design enabling maximum photoresponse for scalable CMOS technologies

    Microsoft Academic Search

    Igor Shcherback; Orly Yadid-Pecht

    2004-01-01

    This brief represents the CMOS active pixel sensor (APS) photoresponse model use for maximum pixel photosignal prediction in scalable CMOS technologies. We have proposed a simple approximation determining the technology-scaling effect on the overall device photoresponse. Based on the above approximation and the data obtained from the CMOS 0.5 ?m process thorough investigation we have theoretically predicted, designed, measured and

  10. Over 10 GHz lateral silicon photodetector fabricated on silicon-on-insulator substrate by CMOS-compatible process

    NASA Astrophysics Data System (ADS)

    Li, Gen; Maekita, Kazuaki; Mitsuno, Hiroya; Maruyama, Takeo; Iiyama, Koichi

    2015-04-01

    We report a design and implementation of lateral silicon photodetectors fabricated on a silicon-on-insulator (SOI) substrate in a complementary CMOS-compatible process. In addition, we disscuss the structure dependences on the frequency and optimum design for a maximum bandwidth. A standard device fabricated with a 210 nm absorbing layer, a finger width of 1.00 m, a finger spacing of 1.63 m, a square detector area of 20 20 m2, and a pad size of 60 60 m2 achieved a bandwidth of 12.6 GHz at a bias voltage of 10 V, with a responsivity of 7.5 mA/W at 850 nm wavelength. A photodetector with the same geometry, which was fabricated with a smaller pad size of 30 30 m2, exhibited a bandwidth of 13.6 GHz.

  11. Thermally actuated CMOS micromirrors

    Microsoft Academic Search

    J. Bhler; J. Funk; O. Paul; F.-P. Steiner; H. Baltes

    1995-01-01

    Thermally actuated micromirrors fabricated using a standard CMOS process and one subsequent anisotropic silicon etch step are presented. The device consists of a mirror plate supported by bimorph cantilever beams. Even short beams show a large deflection effect. A theoretical analysis valid for n-morph bending beams has been derived and found to be consistent with experimental and computer-simulation results.

  12. High-speed binary CMOS image sensor using a high-responsivity MOSFET-type photodetector

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Choi, Pyung; Shin, Jang-Kyoo

    2015-03-01

    In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-?m process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.

  13. CMOS array design automation techniques

    NASA Technical Reports Server (NTRS)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  14. A 4Gbps 0.57pJ\\/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS

    Microsoft Academic Search

    Suresh Srinivasan; Sanu Mathew; Vasantha Erraguntla; Ram Krishnamurthy

    2009-01-01

    This paper describes an all-digital on-die true random number generator implemented in 45 nm CMOS technology, with random bit throughput of 4 Gbps and total energy consumption of 0.57 pJ\\/bit. A 2-step tuning mechanism enables robust operation in the presence of up to 20% fabrication-time process variation as well as immunity to run-time voltage and temperature fluctuation. The 100% use

  15. A design of sub-band generator for MB-OFDM UWB application in 0.13 ?m RF CMOS process

    Microsoft Academic Search

    Joon Sung Park; YoungGun Pu; Young-Shin Kim; Chul Nam; Kang-Yoon Lee

    2008-01-01

    This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (ultra-wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and

  16. A CCD\\/CMOS image motion sensor

    Microsoft Academic Search

    Massimo Gottardi; Woodward Yang

    1993-01-01

    Presents a 1D image motion sensor with a 115-pixel linear image sensor and analog CCD\\/CMOS processors that correlates two image frames that are spatially shifted between -5 and +5 pixels, to estimate object motion over a range of 1 to 5000 pixels\\/s. The CCD\\/CMOS smart sensor chip is fabricated with a standard double poly, double metal, 2-?m CMOS\\/CCD process available

  17. Process Uniformity and Challenges of AlGaN/GaN MIS-HEMTs on 200-mm Si (111) Substrates Fabricated with CMOS-Compatible Process and Integration

    NASA Astrophysics Data System (ADS)

    Selvaraj, S. L.; Kamath, A.; Wang, W.; Chen, Z.; Win, K. T.; Phua, T. S.; Lo, G. Q.

    2015-04-01

    We report the device characteristics and uniformity of AlGaN/GaN MIS-HEMTs fabricated on a full 200-mm (8-in) GaN-on-Si substrate using CMOS-compatible non-Au and non-lift-off-based fabrication process. An I Dmax and g m of 387 mA/mm and 82 mS/mm were, respectively, measured across a 200-mm wafer. We have observed a good uniformity of device characteristics, namely I D (average 345 mA/mm; %? of 5%), g m (average of 82 mS/mm; %? of 4.9%), R d (average of 10.2 ? mm; %? of 8.3%) and V br (average of 277 V, %? of 17%) for AlGaN/GaN MIS-HEMTs grown on a 200-mm silicon substrate. For wafer line-yield, a very low wafer breakage (2%) was observed.

  18. A low-power CMOS ASIC for X-ray Silicon Drift Detectors low-noise pulse processing

    NASA Astrophysics Data System (ADS)

    Ahangarianabhari, M.; Bertuccio, G.; Macera, D.; Malcovati, P.; Grassi, M.; Rashevsky, A.; Rashevskaya, I.; Vacchi, A.; Zampa, G.; Zampa, N.; Fuschino, F.; Evangelista, Y.; Campana, R.; Labanti, C.; Feroci, M.

    2014-03-01

    We present an Application Specific Integrated Circuit (ASIC), named VEGA-1, designed and manufactured for low-power analog pulse processing of signals from Silicon Drift Detectors (SDDs). The VEGA-1 ASIC consists of an analog and a digital/mixed-signal section to achieve all the functionalities and specifications required for high-resolution X-ray spectroscopy in the energy range from 500 eV to 60 keV with low power consumption. The VEGA-1 ASIC has been designed and manufactured in 0.35-?m CMOS mixed-signal technology in single and 32-channel version with dimensions of 200 ?m 500 ?m per channel. A minimum intrinsic ENC of 12 electrons r.m.s. at 3.6 ?s shaping time and room temperature is measured for the ASIC without detector. The VEGA-1 has been tested with Q10-SDD designed in Trieste and fabricated at FBK, with an active area of 10 mm2 and a thickness of 450 ?m. The aforementioned detector has an anode current of about 180 pA at +22C. A minimum Equivalent Noise Charge (ENC) of 16 electrons r.m.s. at 3.0 ?s shaping time and -30C has been demonstrated with a total measured power consumption of 482 ?W.

  19. Wide dynamic range and high-sensitivity CMOS active pixel sensor using output voltage feedback structure

    NASA Astrophysics Data System (ADS)

    Jo, Sung-Hyun; Bae, Myunghan; Choi, Byoung-Soo; Kim, Jeongyeob; Shin, Jang-Kyoo

    2014-05-01

    This paper presents a novel high-sensitivity and wide dynamic range complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) with an overlapping control gate. The proposed APS has a high-sensitivity gate/bodytied (GBT) photodetector with an overlapping control gate that makes it possible to control the sensitivity of the proposed APS. The floating gate of the GBT photodetector is connected to the n-well and the overlapping control gate is placed on top of the floating gate for varying the sensitivity of the proposed APS. Dynamic range of the proposed APS is significantly increased due to the output voltage feedback structure. Maximum sensitivity of the proposed APS is 50 V/luxs in the low illumination range and dynamic range is greater than 110 dB. The proposed sensor has been fabricated by using 2-poly 4-metal 0.35 ?m standard CMOS process and its characteristics have been evaluated.

  20. Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

    2006-01-01

    We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

  1. A CMOS Magnetic Sensor Chip for Biomedical Applications

    E-print Network

    Liu, PENG

    2012-01-01

    CMOS bead relaxation detector significantly reduces the powerpower saving 5.6 Chip Implementation The microbead detector is implemented in 0.18 m CMOS.detectors with all building blocks implemented in CMOS process are compact, low-power and

  2. Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

    NASA Astrophysics Data System (ADS)

    Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

    2008-11-01

    In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 ?m 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 6.2 ?m2. The sensitivity of the proposed pixel is 49 lux/(Vs). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

  3. A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

    Microsoft Academic Search

    Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; S. Okazaki; Katsuji Satomi; Hironori Akamatsu; Hirofumi Shinohara

    2008-01-01

    The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic

  4. Thermoelectric infrared sensors by CMOS technology

    Microsoft Academic Search

    Rene Lenggenhager; Henry Baltes; Jon Peer; Martin Forster

    1992-01-01

    The authors report two integrated thermoelectric infrared sensors on thin silicon oxide\\/nitride microstructures realized by industrial CMOS IC technology, followed by one compatible single maskless anisotropic etching step. No additional material is needed to enhance infrared absorption since the passivation layer, as provided by the CMOS process, is sufficient for certain spectral bands. The responsivities are between 12 and 28

  5. CMOS Microsystems for Phase Fluorometric Biochemical Monitoring

    Microsoft Academic Search

    Alexander N. Cartwright; Vamsy P. Chodavarapu; Sung Jin Kim; Rachel M. Bukowski; Albert H. Titus; Frank V. Bright

    2007-01-01

    This article will present a review of our recent work on the development of Complementary Metal-Oxide Semiconductor (CMOS) detection and signal processing interfaces for fluorescence based biochemical sensors as well as the development of a new sensor. We will discuss a number of microsystems that integrate CMOS Application Specific Integrated Circuits (ASICs) with nanoporous sensor materials. Specifically, sol-gel derived xerogel

  6. CMOS Architecture of Synchronous Pulse-Coupled Neural Network and Its Application to Image Processing

    E-print Network

    Wilamowski, Bogdan Maciej

    Processing Yasuhiro Ota Bogdan M. Wilamowski Image Information Products Hdqrs. College of Engineering MINOLTA the five key axon properties of (i) threshold of excitation, (ii) refractory period, (iii) constant pulse

  7. RTD\\/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

    Microsoft Academic Search

    J. I. Bergman; J. Chang; Y. Joo; B. Matinpour; J. Laskar; N. M. Jokerst; M. A. Brooke; B. Brar

    1999-01-01

    The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed

  8. Low-Noise CMOS Circuits for On-Chip Signal Processing in Focal-Plane Arrays

    Microsoft Academic Search

    Bedabrata Pain

    1993-01-01

    The performance of focal-plane arrays can be significantly enhanced through the use of on-chip signal processing. Novel, in-pixel, on-focal-plane, analog signal-processing circuits for high-performance imaging are presented in this thesis. The presence of a high background-radiation is a major impediment for infrared focal-plane array design. An in-pixel, background-suppression scheme, using dynamic analog current memory circuit, is described. The scheme also

  9. Development of a RF Bipolar Transistor in a Standard 0.35m CMOS Technology

    E-print Network

    Ng, Wai Tung

    Development of a RF Bipolar Transistor in a Standard 0.35m CMOS Technology I-Shan Michael Sun-0021, Japan ABSTRACT A RF Bipolar Transistor integrated to a standard 0.35m CMOS process is presented compared to previously published BiCMOS technologies. Key Words 0.35m CMOS Technology, RF Silicon Bipolar

  10. 0.15-?m RF CMOS technology compatible with logic CMOS for low-voltage operation

    Microsoft Academic Search

    Masanobu Saito; Mizuki Ono; Ryuichi Fujimoto; Hiroshi Tanimoto; Nobuyuki Ito; Takashi Yoshitomi; Tatsuya Ohguro; Hisayo Sasaki Momose; Hiroshi Iwai

    1998-01-01

    Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption.

  11. NiPt salicide process improvement for 28 nm CMOS with Pt(10%) additive

    Microsoft Academic Search

    Jerander Lai; Yi-Wei Chen; Nien-Ting Ho; Yu Shan Shiu; J. F. Lin; Shuen Chen Lei; Nick Z. H. Chang; Ling Chun Chou; C. C. Huang; J. Y. Wu

    This study successfully demonstrates 5080% NiSi defect reduction and P-FET 3% leakage improvement using Pt(10at.%) additive for 28nm node silicide process. Additionally, this study also discovers that lower thermal budget is required for getting same thick NiSi and better NiSi Rs distribution with higher concentration of Pt additive.

  12. Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

    Microsoft Academic Search

    Saibal Mukhopadhyay; Keejong Kim; Hamid Mahmoodi; Kaushik Roy

    2007-01-01

    In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and\\/or delay of a ring oscillator is used to determine the

  13. Ultra-Low-Voltage 20GHz Frequency Dividers Using Transformer Feedback in 0.18- m CMOS Process

    Microsoft Academic Search

    Hui Zheng; Howard C. Luong

    2008-01-01

    This paper presents the design and analysis of ultra- low-voltage (ULV) high-frequency dividers using transformer feedback. Specifically, a differential-input differential-output injection-locked (IL) divider topology with transformer feedback and a wideband transformer-coupled (TC) divider with quadrature outputs are demonstrated, both of which can operate well at supply voltages as low as the device's threshold voltages. Fabricated in a standard 0.18-mum CMOS

  14. pn photodiode in 0.35-?m high-voltage CMOS with 1.2-GHz bandwidth

    NASA Astrophysics Data System (ADS)

    Enne, Reinhard; Steindl, Bernhard; Schneider-Hornstein, Kerstin; Zimmermann, Horst

    2014-11-01

    A pn-junction photodiode with a bandwidth in the GHz range is presented. This photodiode is fabricated in a standard 0.35-?m high-voltage CMOS process with deep n-wells which can isolate negative substrate potentials down to -100 V from the MOS transistors. This photodiode can, therefore, be implemented together with circuits on the same chip. At a reverse bias voltage of -90 V, a bandwidth of 1.2 GHz was measured for 670-nm light. The breakdown voltage of this photodiode is about -180 V.

  15. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  16. An integrated, CMOS, constant-fraction timing discriminator for multichannel detector systems

    SciTech Connect

    Simpson, M.L.; Britton, C.L.; Wintenberg, A.L.; Young, G.R. [Oak Ridge National Lab., TN (United States)] [Oak Ridge National Lab., TN (United States)

    1995-08-01

    An integrated, CMOS, constant-fraction timing discriminator (CFD) designed to accommodate the special requirements of large, multichannel `el detector systems is described. This CFD features on-chip, zero-crossing shaping and an automatic walk setting to limit the number of user adjustments. The circuit is realized in the Orbit 1.2 micron, N-well, CMOS process and operates with a 5 V power supply. The time walk in a 100:1 dynamic range ({minus}15 mV to {minus}1.5 V) is less than {+-}250 ps for a 10 ns rise time/10 ns fall time signal, yet the power dissipation is about 2 mW/channel. The discriminator has a 170 micron pitch, is 800 microns long, and is structured for arraying multiple channels on a single die. In this work, the fully integrated, CMOS CFD that was designed for the lead-glass calorimeter of the WA-98 experiment is described. This circuit also has applications for some detector subsystems in the Relativistic Heavy Ion Collider (RHIC) detector, PHENIX.

  17. CMOS photodetectors\\/receivers for smart-pixel based photonic systems

    Microsoft Academic Search

    Jianjing Tang; Sunil Konanki; Bharath Seshadri; Boon K. Lee; Robert C. Chi; Andrew J. Steckl; Fred R. Beyette

    2000-01-01

    The design, characterization and evaluation of CMOS based silicon photodetectors\\/photoreceivers suitable for smart-pixel based applications are presented. Implemented with a conventional CMOS fabrication process, these photodetectors\\/receiver circuits can be reliably fabricated for smart-pixel based photonic information processing systems that combine the parallelism associated with optics and the data processing capabilities associated with CMOS logic. Several different CMOS based photodetector structures

  18. HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter

    Microsoft Academic Search

    S. Konaka; T. Kobayashi; T. Matsuda; M. Ugajin; K. Imai; T. Sakai

    1990-01-01

    HSST\\/BiCMOS technology has been developed by merging a novel 0.3 ?m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 ?m CMOS process. The HSST bipolar transistor size is 2.5 times smaller than that of 1 ?m SST-1B with an emitter 0.4 ?m wide. This results from a 0.3 ?m design rule, a collector polysilicon

  19. CMOS technology using SEG isolation technique

    Microsoft Academic Search

    N. Endo; N. Kasai; A. Ishitani; Y. Kurogi

    1983-01-01

    An advanced bulk CMOS process has been developed using SEG (Selective Epitaxial Growth) isolation technique and high impurity concentration substrate, in order to suppress latch-up phenomenon. CMOS devices are fabricated on epitiaxial layer, which is selectively grown over p-type silicon substrate surrounded by a 2 m thick SiO2insulator, using a reduced pressure SiH2Cl2-H2-HCl system. P-channel devices are formed in an

  20. Post-CMOS integration of germanium microstructures

    Microsoft Academic Search

    A. E. Franke; D. Bilic; D. T. Chang; P. T. Jones; T.-J. King; R. T. Howe; G. C. Johnson

    1999-01-01

    Polycrystalline germanium (poly-Ge) microstructures have been fabricated on standard CMOS wafers. Conventional low pressure chemical vapor deposition (LPCVD) and rapid thermal annealing (RTA) processes were used to achieve low-resistivity (2.3 m?-cm) tensile poly-Ge structural films, with a thermal budget which is compatible with Al (2% Si) metallization. The CMOS circuitry was passivated with low-temperature oxide and amorphous Si; the latter

  1. High speed submicron BiCMOS memory

    Microsoft Academic Search

    Masahide Takada; Kazuyuki Nakamura; Tohru Yamazaki

    1995-01-01

    This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 ?m, 0.55 ?m and 0.4 ?m design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron

  2. CMOS-Integrated RF MEMS Resonators

    Microsoft Academic Search

    Maxim K. Zalalutdinov; Joshua D. Cross; Jeffrey W. Baldwin; Bojan R. Ilic; Wenzhe Zhou; Brian H. Houston; Jeevak M. Parpia

    2010-01-01

    We present a design approach that enables monolithic integration of high-quality-factor (Q) radio-frequency (RF) microelectromechanical systems (MEMS) resonators with CMOS electronics. Commercially available CMOS processes that feature two polysilicon layers and field oxide isolation can be used to implement this approach. By using a nonplanar resonator geometry in conjunction with mechanical stress in polycrystalline silicon (poly) gate layers, we create

  3. Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies

    E-print Network

    Finkelstein, Hod

    2007-01-01

    CMOS technology, based on a new shallow-trench isolationtechnologies, especially DRAM processes, offer deep-trench isolation.Isolation Bounded Single-Photon Avalanche Diodes in Commercial Deep Submicron CMOS Technologies

  4. CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers

    E-print Network

    Xu, Rui

    2010-10-12

    and Bluetooth are mostly narrow band based. To implement UWB technologies on CMOS imposes the development of CMOS front-end building blocks which can perform wideband signal processing such as amplifying, frequency conversion, frequency generation as well...

  5. CMOS MEMS - present and future

    Microsoft Academic Search

    Henry Baltes; Oliver Brand; Andreas Hierlemann; Dirk Lange; Christoph Hagleitner

    2002-01-01

    The paper reviews the state-of-the-art in the field of CMOS-based microelectromechanical systems (MEMS). The different CMOS MEMS fabrication approaches, pre-CMOS, intermediate-CMOS, and post-CMOS, are summarized and examples are given. Two microsystems fabricated with post-CMOS micromachining are presented, namely a mass-sensitive chemical sensor for detection of organic volatiles in air and a 10-cantilever force sensor array for application in scanning probe

  6. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 m CMOS Process

    PubMed Central

    Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

    2014-01-01

    The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 m CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 W from 1.8 V supply and 88.05 A average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

  7. CMOS-based microsensors ISBN 87-89935-50-0 21

    E-print Network

    Akin, Tayfun

    dynamic range. A 16x16 test array is fabricated using a 0.8m CMOS process. Each detector pixel imagers are challenged by CMOS imagers that have advantages like low cost, low power consumption CMOS process. The detector diode in each pixel is reverse biased, and when incoming photons

  8. CMOS-MEMS membrane for audio-frequency acoustic actuation

    Microsoft Academic Search

    Kaigham J. Gabriel

    2001-01-01

    Using CMOS-MEMS micromachining techniques we have constructed a prototype earphone that is audible from 1 to 15 kHz. The fabrication of the acoustic membrane consists of only two steps in addition to the prior post-CMOS micromachining steps developed at CMU. The ability to build a membrane directly on a standard CMOS chip, integrating mechanical structures with signal processing electronics will

  9. An Embedded DRAM for CMOS ASICs John Poulton

    E-print Network

    Poulton, John W.

    An Embedded DRAM for CMOS ASICs John Poulton Department of Computer Science University of North, will also require more memory than can easily be supported on logic-oriented ASIC processes. Most ASIC. This paper describes development of a DRAM, compatible with a standard CMOS ASIC process, that provides

  10. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  11. Ion traps fabricated in a CMOS foundry

    NASA Astrophysics Data System (ADS)

    Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

    2014-07-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  12. Ion traps fabricated in a CMOS foundry

    E-print Network

    K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

    2014-06-13

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  13. Ion traps fabricated in a CMOS foundry

    E-print Network

    Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

    2014-01-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  14. Clocked CMOS calculator circuitry

    Microsoft Academic Search

    Y. Suzuki; K. Odagawa; T. Abe

    1973-01-01

    A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail. The CMOS-LSI includes 3300 elements and has a chip size of about 200 mil square, operates at 6 V supply voltage, and dissipates power of about 1 mW at a clock frequency of 50 kHz.

  15. CMOS Oscillators INTRODUCTION

    E-print Network

    Markatos, Evangelos P.

    . To determine the frequency of oscillation, it is necessary to examine the propagation delay of the inverters. CMOS propagation delay depends on supply voltage and load ca- pacitance. Several curves for propagation delay for Fair- child's 74C line of CMOS gates are reproduced in Figure 3. From these, the natural

  16. Novel low-temperature CMOS-compatible full-wafer-bonding process for the fabrication of 3D embedded microchannels using SU-8

    NASA Astrophysics Data System (ADS)

    Blanco, Francisco J.; Agirregabiria, Maria; Tijero, Maria; Berganzo, Javier; Garcia, Jorge; Arroyo, Maria; Ruano, Jesus M.; Aramburu, Inigo; Mayora, Kepa

    2004-04-01

    This article describes a novel low temperature full wafer adhesive bonding process to fabricate three-dimensional (3-D) embedded microchannels using SU-8 photoresist as structural material. The technology development includes an improvement of the SU-8 photolithography process in order to produce high uniformity films using Taguchi methodology. After that, 3-D embedded microchannels are fabricated by a low temperature adhesive bonding of the the SU-8 thick-films. The process parameters have been chosen in order to achieve a strong and void-free bond. Different examples using this new technology are shown, including bonding between Silicon, Pyrex and combinations of them, in order to obtain 3-D interconnected microchannels between the wafers. Microchannels with vertical smooth walls and aspect ratios up to five have been obtained. Channels depth from 40 to 60 ?m and 10 to 250 ?m width have been achieved. Liquid has been introduced into the channels verifying a good sealing of the 3-D microchannels. The fabrication procedure described in this article is fast, reproducible, CMOS compatible and easily implemented using standard photolithography and bonding equipment.

  17. CMOS foundry Schottky diode microwave power detector fabrication, Spice modeling, and application

    Microsoft Academic Search

    W. Jeon; J. Melngailis

    2006-01-01

    CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35mu CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schotkty diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits

  18. CMOS Schottky diode microwave power detector fabrication, Spice modeling, and applications

    Microsoft Academic Search

    Woochul Jeon; John Melngailis; Robert W. Newcomb

    2006-01-01

    CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35? CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schottky diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits and a low-voltage reference circuit.

  19. A 12 mW wide dynamic range CMOS front end for a portable GPS receiver

    Microsoft Academic Search

    A. R. Shahani; D. K. Shaeffer; T. H. Lee

    1997-01-01

    At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35?m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications

  20. Differential Mode CMOS Active Pixel Sensor (APS) for Optically Programmable Gate Array (OPGA)

    E-print Network

    Fossum, Eric R.

    1 Differential Mode CMOS Active Pixel Sensor (APS) for Optically Programmable Gate Array (OPGA@photobit.com Abstract A differential mode CMOS active pixel sensor (APS) was designed, fabricated, and tested as part.35 m standard CMOS process technology. I. Introduction Field programmable gate arrays (FPGA) are widely

  1. Radiation-induced dark signal in 0.5-um CMOS APS image sensors

    Microsoft Academic Search

    El-Sayed I. Eid; Richard H. Tsai; Eric R. Fossum; Robert Spagnuolo; John J. Deily; Hal Anthony

    2000-01-01

    A CMOS APS image sensor test chip, which was designed employing the physical design techniques of enclosed geometry and guard rings and fabricated in a 0.5-micrometers CMOS process, underwent a Co60 (gamma) -ray irradiation experiment. The experiment demonstrated that implementing the physical design techniques of enclosed geometry and guard rings in CMOS APS image sensors is possible. It verified that

  2. Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

    E-print Network

    Fossum, Eric R.

    using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detectorLow Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology Eric R. Fossum Center using a highly specialized fabrication process that is not generally CMOS compatible. Separate support

  3. A JFET-CMOS Technology for Low-Noise Sensor Interface Circuits

    Microsoft Academic Search

    Hidekuni Takao; Rikiya Asaoka; Kazuaki Sawada; Shoji Kawahito; Makoto Ishida

    2003-01-01

    In this paper, fabrication technology and device characteristics of junction field effect transistor (JFET) which can be integrated in CMOS sensor interface circuits are presented. The JFET is applicable to CMOS (operational) amplifiers to realize a very low-noise front-end amplifier in sensor interface circuits. It is formed with isolated p-well area in CMOS device. Extra processes to a standard CMOS

  4. Linear array of CMOS double pass metal micromirrors

    Microsoft Academic Search

    Johannes Buehler; Franz-Peter Steiner; Henry Baltes

    1996-01-01

    Low-cost linear arrays of deflectable micromirrors using a CMOS process to define both on-chip circuitry and the mirror structure are presented. The mirrors consist of the second CMOS metallization deposited in two successive passes in order to establish a thick metal layer for the stiff mirror plate as well as a thin one for the flexible hinges. The mirrors are

  5. CMOS technology characterization for analog and RF design

    Microsoft Academic Search

    Behzad Razavi

    1998-01-01

    Characterization of CMOS technologies for digital applications often proves inadequate for analog and RF design. This paper describes a set of characterization vehicles and tests that quantify the analog behavior of active and passive devices in CMOS processes, in particular, properties that are not represented accurately in SPICE models. Test structures and circuits are introduced for measuring speed, noise, linearity,

  6. Analog CMOS high-frequency continuous wavelet transform circuit

    Microsoft Academic Search

    E. W. Justh; F. J. Kub

    1999-01-01

    A 16-channel analog CMOS high-frequency continuous wavelet transform circuit has been realized. The circuit performs a time-frequency decomposition of a high-frequency input signal. A 100 MHz operating frequency, 45 MHz bandwidth, and 40 mW\\/channel power dissipation have been achieved using a 0.5 ?m CMOS process

  7. CMOS APS crosstalk: modeling, technology and design trends

    Microsoft Academic Search

    Shcherback Igor; Belenky Alex; O. Yadid-Pecht

    2004-01-01

    In this work based on a unique sub-micron scanning system (S-cube system) measurements of the lateral photoresponse and crosstalk (CTK) in CMOS active pixel sensor (APS) have been investigated and an analytical model was developed for crosstalk estimation in photodiode based CMOS APS arrays. Based on handy process and design data only, our model estimates the CTK contribution to the

  8. Analysis of 1\\/f noise in CMOS APS

    Microsoft Academic Search

    Hui Tian; Abbas El Gamal

    2000-01-01

    As CMOS technology scales, the effect of 1\\/f noise on low frequency analog circuits such as CMOS image sensors becomes more pronounced, and therefore must be more accurately estimated. analysis of 1\\/f noise is typically performed in the frequency domain even though the process is nonstationary. To find out if the frequency domain analysis produces acceptable results, the paper introduces

  9. Circuit technologies for BiCMOS VLSIs as computer elements

    Microsoft Academic Search

    H. Maejima; T. Bandoh; Y. Nishio; T. Fukushima; M. Odaka; A. Hotta

    1989-01-01

    System requirements for VLSI technologies are reviewed and circuit technologies for BiCMOS VLSIs as computer elements are described. The following topics are dealt with: circuits for logic gates-conventional circuits and feedback type circuits for finer process; circuits for macrocells-CMOS logic circuits with bipolar sense circuits; and circuits for application-specific memories-sense amplifiers with comparators

  10. Fundamental performance differences of CMOS and CCD imagers: part V

    NASA Astrophysics Data System (ADS)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  11. Total ionizing dose radiation hardness of the ATLAS MDT-ASD and the HP-Agilent 0.5 um CMOS process

    E-print Network

    Posch, C

    2002-01-01

    A total ionizing dose (TID) test of the MDT-ASD, the ATLAS MDT front-end chip has been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5 um CMOS process (AMOS14TB). The accumulated TID at the end of the test was 300 krad, delivered by 160 MeV protons at a rate of approximately 70 rad/sec. All 10 irradiated chips retained their full functionality and performance and showed only irrelevantly small changes in device parameters. As the total accumulated dose is substantially higher than the relevant ATLAS Radiation Tolerance Criteria (RTCtid), the results of this test indicate that MDT-ASD meets the ATLAS TID radiation hardness requirements. In addition, the results of this test correspond well with results of a 30 keV gamma TID irradiation test performed by us on an earlier prototype at the CERN x-ray facility as well as with results of other irradiation test on this process found in literature.

  12. CMOS compatible edge coupled capacitive MEMS switch for RF applications

    Microsoft Academic Search

    Shumin Zhang; Wansheng Su; M. E. Zaghloul

    2007-01-01

    This paper presents the design, simulation and fabrication of a CMOS process compatible capacitive MEMS switch. The MEMS switch uses thermal actuation and finger structures for capacitive coupling. The design is fabricated using commercial 0.6 um CMOS process and post-processed using mask-less RIE process. Results show that the insertion loss is 0.7 dB at 2 GHz and the isolation is

  13. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  14. A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

    Microsoft Academic Search

    Philippe Roche; Gilles Gasiot; Slawosz Uznanski; Jean-Marc Daveau; Josep Torras-Flaquer; Sylvain Clerc; Reno Harboe-Sorensen

    2010-01-01

    This paper presents new experimental and modeling evidences that advanced commercial CMOS technologies get intrinsically harder against space radiations with technology downscaling. A 65 nm commercial bulk CMOS process can deliver improved radiation-tolerance without sacrificing electrical performance.

  15. Design of a 1 V low power CMOS bandgap reference based on resistive subdivision

    Microsoft Academic Search

    K. Lasanen; V. Korkala; E. Raisanen-Ruotsalainen; J. Kostamovaara

    2002-01-01

    The design of a CMOS bandgap reference (BGR), for portable applications with medium accuracy, is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 0.750 V

  16. A Low-Power\\/Low-Voltage CMOS Wireless Interface at 5.7 GHz With Dry Electrodes for Cognitive Networks

    Microsoft Academic Search

    Nuno Srgio Dias; Joo Paulo Carmo; Paulo Mateus Mendes; Jos Higino Correia

    2011-01-01

    This paper describes a low-power\\/low-voltage CMOS wireless interface (CMOS-WiI) at 5.7 GHz with dry electrodes for congnitive networks. The electrodes are 4 4 microtip arrays and acquire electroencephalogram (EEG) signals in key- points for processing. The CMOS-WiI was fabricated in a UMC 0.18 RF CMOS process and its total power consumption is 23 mW with a voltage-supply of only 1.5

  17. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  18. An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

    Microsoft Academic Search

    H. Tran; K. Fung; D. Bell; R. Chapman; M. Harward; T. Suzuki; R. Havemann; R. Eklund; R. Fleck; D. Le; C. Wei; N. Iyengar; M. Rodder; R. Haken; D. Scott

    1989-01-01

    A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I\\/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m 2 full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time.

  19. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  20. Graphene for CMOS and Beyond CMOS Applications

    Microsoft Academic Search

    Sanjay K. Banerjee; Leonard Franklin Register; Emanuel Tutuc; Dipanjan Basu; Seyoung Kim; Dharmendar Reddy; Allan H. MacDonald

    2010-01-01

    Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated

  1. A CMOS Integrated Power Detector for UWB

    Microsoft Academic Search

    Kenneth A. Townsend; James W. Haslett; John Nielsen

    2007-01-01

    An integrated CMOS RF power detector for wideband systems that does not require additional processing steps is presented. The received signal modulates the resistance of a MOSFET biased in triode to produce a DC current at the input of a transimpedance amplifier proportional to the received power. The resulting voltage is applied to an auto-zeroed logarithmic amplifier that provides offset

  2. Transistor matching in analog CMOS applications

    Microsoft Academic Search

    Marcel J. M. Pelgrom; Hans P. Tuinhout; Maarten Vertregt

    1998-01-01

    This paper gives an overview of MOSFET mismatch effects that form a performance\\/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease

  3. A SubMicron BiCMOS Technology for Telecommunications

    Microsoft Academic Search

    R. Hadaway; P. Kempf; P. Schvan; M. Rowlandson; V. Ho; J. Kolk; B. Tait; D. Sutherland; G. Jolly; I. Emesh

    1991-01-01

    A high performance, 0.8 m, analog-digital technology is presented. Telecommunication circuit and system diversity has been accommodated by incorporating modular device options into a triple-level-metal BiCMOS process.

  4. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 1263 Dual-Self-Timed CMOS Logic for

    E-print Network

    Yoo, Hoi-Jun

    , SEPTEMBER 1998 1263 Dual- Self-Timed CMOS Logic for Low Subthreshold Current Multigigabit Synchronous DRAM, for the optimization of the width of the MOS transistors in the circuit, and for the determination of the delay time Hoi-Jun Yoo Abstract--A subthreshold current reduction logic, the dual-VT self-timed (DVST) logic

  5. A CMOS humidity sensor with on-chip calibration

    Microsoft Academic Search

    Y. Y. Qiu; C. Azeredo-Leme; L. R. Alccer; J. E. Franca

    2001-01-01

    This paper describes a capacitive humidity sensor with on-chip calibration circuit fabricated by a standard CMOS process to achieve a cost-effective solution for accurate and reliable humidity measurement. The humidity sensing property on-chip is obtained by a post-processing step after the standard CMOS fabrication and whereby a commercial polyimide is deposited on the packaged chip. The sensing principle of the

  6. An Immunoassay Platform Based on CMOS Hall Sensors

    Microsoft Academic Search

    Turgut Aytur; P. Robert Beatty; Bernhard Boser; Tomohiro Ishikawa

    2002-01-01

    We describe an immunoassay utilizing standard CMOS technology. An array of Hall sensors is used to detect the magnetic beads that serve as the assay signal. Electrical and magnetic modulation is employed to improve the sensitivity of the sensors. The devices receive two post-processing steps to improve sensitivity and biocompatibility. We have fabricated prototype devices using a 0.25-m BiCMOS process,

  7. IR CMOS: ultrafast laser-enhanced silicon detection

    Microsoft Academic Search

    M. U. Pralle; J. E. Carey; H. Homayoon; J. Sickler; X. Li; J. Jiang; D. Miller; C. Palsule; J. McKee

    2011-01-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near\\/shortwave infrared (NIR\\/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches.

  8. Radiation-hardened N (+) gate CMOS\\/SOS

    Microsoft Academic Search

    G. W. Hughes; G. J. Brucker; R. K. Smeltzer

    1981-01-01

    Process development work for a hardened N+ polysilicon-gate CMOS\\/SOS process has demonstrated that it is possible to make functional 4K CMOS\\/SOS static RAMs that are hard to 5 x 10 to the 5th power rads without the implementation of special hardened circuit design techniques. Present circuit probe yields are low, limited by the lack of a hardened low-temperature contoured field

  9. Black silicon enhanced photodetectors: a path to IR CMOS

    Microsoft Academic Search

    M. U. Pralle; J. E. Carey; H. Homayoon; S. Alie; J. Sickler; X. Li; J. Jiang; D. Miller; C. Palsule; J. McKee

    2010-01-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near\\/shortwave infrared (NIR\\/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches.

  10. Embedded Solenoid Inductors for RF CMOS Power Amplifiers Yong-Kyu Yoon, Emery Chen, Mark G. Allen, and Joy Laskar

    E-print Network

    Embedded Solenoid Inductors for RF CMOS Power Amplifiers Yong-Kyu Yoon, Emery Chen, Mark G. Allen with a foundry-fabricated CMOS RF power amplifier, is described. The embedded nature of these inductors allows circuitry, four inductors are post-processed onto a foundry-fabricated RF CMOS power amplifier. DESIGN

  11. A Method for Estimating Quantum Efficiency for CMOS Image Boyd Fowler, Abbas El Gamal, David Yang, and Hui Tian

    E-print Network

    El Gamal, Abbas

    method for measuring QE for a CCD sensor is not adequate for CMOS APS since it does not take pixel APS test structures implemented in a 0.35 um CMOS process are reported. Using 6 different chips for CCDs and CMOS APS are very different. In a CCD sensor the output response can be expressed as a linear

  12. Abstract--This work presents a semi -analytical diffusion-limited CMOS Active Pixel Sensor (APS) pixel photoresponse model use

    E-print Network

    Abstract-- This work presents a semi -analytical diffusion-limited CMOS Active Pixel Sensor (APS of a photodiode based CMOS APS field of applicability is not constrained by a specific technology process; it can) pixel photoresponse model use for maximum pixel photosignal prediction in scalable CMOS technologies

  13. 128X128 CMOS PHOTODIODE-TYPE ACTIVE PIXEL SENSOR WITH ON-CHIP TIMING, CONTROL AND SIGNAL CHAIN ELECTRONICS

    E-print Network

    Fossum, Eric R.

    ABSTRACT A 128x128 element CMOS active pixel image sensor (APS) with on-chip timing, control, and signal process with a 19.2 tm pixel pitch. The sensor uses a photodiode-type CMOS APS pixel with in-pixel source of two differential analog channels. The CMOS APS chip reported here has peiformance suitable for many

  14. Modeling and Estimation of FPN Components in CMOS Image Abbas El GamaVL, Boyd Fowlera, Hao Minb, Xinqiao Liua

    E-print Network

    El Gamal, Abbas

    ) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial in both PPS and APS. The APS pixel components were uncorrelated. Keywords: CMOS image sensor, fixedModeling and Estimation of FPN Components in CMOS Image Sensors Abbas El GamaVL, Boyd Fowlera, Hao

  15. Variability-Aware Optimization of Nano-CMOS Active Pixel Sensors using Design and Analysis of Monte Carlo Experiments

    E-print Network

    Mohanty, Saraju P.

    Variability-Aware Optimization of Nano-CMOS Active Pixel Sensors using Design and Analysis of Monte for 32nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR nano- CMOS implementation of an APS array optimized to be mis- match and process variation tolerant

  16. Investigation of the influence of unwanted micro lenses caused by semiconductor processing excursions on optical behavior of CMOS photodiodes

    NASA Astrophysics Data System (ADS)

    Kraxner, Andrea; Park, Jong Mun; Minixhofer, Rainer

    2015-03-01

    In this work the influence of nanoscale particles caused by processing excursions during back end of line (BEOL) processing on top of the photodiode active region was examined. To investigate the influence of the particles on the photodiode performance, wafer level optical responsivity measurements were done. In addition to the measurements the effect of the particles was simulated with a simplified model based on a modified transfer matrix method (MTMM)1 . The simulation and measurements are in very good agreement with each other and lead to the conclusion that even though some decrease of sensitivity was observed, the overall system variability was reduced by the presence of particles. Furthermore, the influence of the dielectric stack layer thickness variability on the photon flux density is reduced.

  17. N+\\/P junction leakage characteristics of Co salicide process for 0.15 ?m CMOS devices

    Microsoft Academic Search

    Key-Min Lee; Chel-Jong Choi; Joo-Hyoung Lee; Tae-Yeon Seong; Young-Jin Park; Sung-Kwon Hong; Jae-Gyung Ahn; Hi-Deok Lee

    2002-01-01

    We have proposed that As dopants in the n+\\/p active region are redistributed during Co salicidation process, especially in the active edge area in contact with the field oxide. The dopant redistribution has been verified through a novel two-dimensional (2-D) dopant profiling method, i.e., the transmission electron microscope (TEM) combined with selective chemical etching. It was shown that As dopants

  18. An 0.5-m CMOS Analog Random Access Memory Chip for TeraOPS Speed Multimedia Video Processing

    Microsoft Academic Search

    Ricardo Carmona-galn; ngel Rodrguez-vzquez; Servando Espejo-meana; Rafael Domnguez-castro; Tams Roska; Tibor Kozek; Leon O. Chua

    1999-01-01

    Data compressing, data coding, and communica- tions in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing powerin the order of trillions of oper- ations per second (TeraOPS). Compared with conventional dig- ital technology, cellular neural\\/nonlinear network (CNN)-based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the

  19. PIN photodiodes with significantly improved responsivities implemented in a 0.35µm CMOS\\/BiCMOS technology

    Microsoft Academic Search

    I. Jonak-Auer; A. Marchlewski; S. Jessenig; A. Polzer; W. Gaberl; A. Schmiderer; E. Wachmann; H. Zimmermann

    2010-01-01

    We report on monolithically integrated PIN photodiodes whose responsivity values could be significantly enhanced over the whole spectral range by the implementation of a Bottom Antireflective Coating (BARC) process module into austriamicrosystems 0.35mum CMOS as well as high-speed SiGe BiCMOS technologies. The resulting photodiodes achieve excellent responsivities together with low capacitances and high bandwidths. We processed finger-photodiodes with interdigitated n+

  20. New full-voltage-swing multi-drain/multi-collector complementary BiCMOS buffers (M 2 CBiCMOS)

    NASA Astrophysics Data System (ADS)

    El-Hady, M.; ElSaid, M. H.; Hafez, I. M.; Haddara, H.

    1995-01-01

    In this short paper we introduce new complementary BiCMOS buffers employing multidrain/multi-collector structures. These circuits offer near rail-to-rail output voltage, less circuit complexity, less process complexity, and high performance at scaled down power supply voltages (<2 V). The new circuits are configured in a way that ensures the implemented pnp BJTs (even poor ones) do not appreciably affect the speed performance. The introduced circuits are simulated and compared to conventional BiCMOS and CBiCMOS buffers.

  1. CMOS distributed amplifiers

    Microsoft Academic Search

    Juan C. Ranurez; Yogesh K. Ramadass; M. Jamal Deen

    2004-01-01

    This paper reviews the characteristics of broadband distributed amplifiers (DA) and traveling wave amplifiers (TWA) implemented in CMOS technology. The basic equations that govern the performance and design of DAs in terms of gain, bandwidth, matching and noise are summarized, as well as the implications of the use of transmission lines to replace on-chip inductors. The difficulties that arise for

  2. CMOS APS MTF modeling

    Microsoft Academic Search

    Igor Shcherback; Orly Yadid-Pecht

    2001-01-01

    In this paper, a unified model, based on a thorough analysis of experimental data, is developed for the overall modulation transfer function (MTF) estimation for CMOS image sensors. The model covers the physical diffusion effect together with the influence of the pixel active area geometrical shape. Comparison of both our predicted results and the MTF calculated from the point spread

  3. Statistical Analysis of Steady State Leakage Currents in Nano-CMOS Devices

    E-print Network

    Mohanty, Saraju P.

    issues under process variation. I. INTRODUCTION As process technology scales below 65 nano-meter regimeStatistical Analysis of Steady State Leakage Currents in Nano-CMOS Devices Jawar Singh, Jimson@cs.bris.ac.uk, smohanty@unt.edu Abstract-- Motivated by the problem of process variation in nano-scale CMOS, in this paper

  4. CMOS serial link for fully duplexed data communication

    NASA Astrophysics Data System (ADS)

    Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

    1995-04-01

    This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

  5. Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-?m to 90-nm generation

    Microsoft Academic Search

    P. Hazucha; T. Karnik; J. Maiz; S. Walstra; B. Bloechel; J. Tschanz; G. Dermer; S. Hareland; P. Armstrong; S. Borkar

    2003-01-01

    The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 ?m, 0.18 ?m, 0.13 ?m, and 90 nm showed an increase of 8% per generation.

  6. An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 m CMOS process

    Microsoft Academic Search

    Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei Huang

    2011-01-01

    A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by ?122

  7. CMOS MEMS capacitive absolute pressure sensor

    NASA Astrophysics Data System (ADS)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 m CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  8. A resistorless CMOS current reference with temperature compensation

    Microsoft Academic Search

    Yan Wei; Tian Xin; Li Wenhong; Liu Ran

    2011-01-01

    A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 mum CMOS process. The output current is 1.5 muA, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98

  9. An integrated CMOS distributed amplifier utilizing packaging inductance

    Microsoft Academic Search

    Patrick J. Sullivan; Bernard A. Xavier; Walter H. Ku

    1997-01-01

    An integrated CMOS distributed amplifier is presented. The required inductance needed for the distributed waveguide structure is realized by the parasitic packaging inductance of a plastic surface-mount package. A fully packaged three-stage distributed amplifier fabricated in a 0.8-?m CMOS process is presented. The distributed amplifier has a unity gain cutoff frequency of 4.7 GHz, a gain of 5 dB, with

  10. BiCMOS OEIC with enhanced sensitivity for DVD systems

    Microsoft Academic Search

    K. Kieschnick; H. Zimmermann; P. Seegebrecht

    2001-01-01

    A new BiCMOS OEIC with enhanced sensitivity for advanced optical storage systems is presented. The photodiode and the amplifier are monolithically integrated on the same substrate in an industrial 0:8 m BiCMOS process. The OEIC shows a sensitivity of 43.3mV\\/W in combination with a -3 dB-bandwidth of 60.2 MHz.

  11. Phase noise analysis and design of CMOS differential ring VCO

    Microsoft Academic Search

    Honghui Deng; Yongsheng Yin; Gaoming Du

    2009-01-01

    A complete six-order CMOS differential ring voltage-controlled oscillator (VCO) is designed with a 0.35\\/m CMOS process in this paper. The circuit has been successfully applied in a CPPLL of a high-speed high-resolution DAC, and has been successfully taped out and passed the test. The relative factors that influence the VCO phase noise are analyzed comprehensively to instruct the circuit design.

  12. W-band pulsed radar receiver in low cost CMOS

    Microsoft Academic Search

    Ning Zhang; K. O. Kenneth

    2010-01-01

    A CMOS heterodyne receiver integrating a phase-locked loop that includes a bulk of transmitter functions for W-band pulsed radar is realized using low leakage transistors of a low cost 65-nm bulk CMOS process with 5 thin and 1 thick metal layers used to manufacture cell phone RFIC's. The peak conversion gain of receiver is 7 dB and the minimum NF

  13. CMOS device optimization for mixed-signal technologies

    Microsoft Academic Search

    P. A. Stolk; H. P. Tuinhout; R. Duffy; E. Augendre; L. P. Bellefroid; M. J. B. Bolt; J. Croon; C. J. J. Dachs; F. R. J. Huisman; A. J. Moonen; Y. V. Ponomarev; R. F. M. Roes; M. Da Rold; E. Seevinck; K. N. Sreerambhatla; R. Surdeanu; R. M. D. A. Velghe; M. Vertregt; M. N. Webster; N. K. J. van Winkelhoff; A. T. A. Zegers-Van Duijnhoven

    2001-01-01

    This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction

  14. CMOS-based resonant sensors

    Microsoft Academic Search

    Oliver Brand

    2005-01-01

    The paper provides an overview of resonant sensors based on CMOS technology. Applications of these sensors range from inertial sensors to chemical\\/biochemical sensors, from atomic force microscopy to high-frequency filters. CMOS technology enables to co-integrate the resonant microstructures with necessary analog and digital circuit functions. The paper discusses CMOS-based fabrication approaches for resonant sensors, possible sensing and actuation schemes, suitable

  15. Micromachined thermally based CMOS microsensors

    Microsoft Academic Search

    HENRY BALTES; OLIVER PAUL; OLIVER BRAND

    1998-01-01

    An integrated circuit (IC) approach to thermal microsensors is presented. The focus is on thermal sensors with on-chip bias and signal conditioning circuits made by industrial complementary metal-oxide-semiconductor (CMOS) IC technology in combination with post-CMOS micromachining or deposition techniques. CMOS materials and physical effects pertinent to thermal sensors are summarized together with basic structures used for microheaters, thermistors, thermocouples, thermal

  16. Analytical models of CMOS APS

    Microsoft Academic Search

    Victor A. Shilin; Pavel A. Skrylev; A. L. Stempkovsky

    2002-01-01

    The comparison of the CMOS APS and CCD device features has been made. It is expedient to develop high resolution and wide dynamic range systems with the PhCCD and simple systems with CMOS APS, which allows developing camera-on-a-chip. Schematic and layout types of CMOS APS pixel: with 3, 4 transistors per pixel, and with 5 transistors per two pixels have

  17. A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology

    Microsoft Academic Search

    Haigang Yang; Hongguang Sun; Jinghong Han; Jinbao Wei; Zengjin Lin; Shanhong Xia; Hua Zhong

    2005-01-01

    A monolithic pH sensor system has been studied and developed, based on standard CMOS technology. The micro system includes an on-chip integration of differential ISFET\\/REFET sensing devices, metal constructed pseudo reference electrode (PRE) and front-end measurement electronics. A post CMOS process flow is devised in our laboratory to allow the ISFET to be fabricated in a standard CMOS foundry with

  18. A 60GHz down-converting CMOS single-gate mixer

    Microsoft Academic Search

    Sohrab Emami; Chinh H. Doan; Ali M. Niknejad; Robert W. Brodersen

    2005-01-01

    A quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60-GHz, is presented. Also a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers. The performance of a fully-integrated mixer fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency

  19. Development and characterization of CMOS-based monolithic X-ray imager sensor

    Microsoft Academic Search

    Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

    2007-01-01

    We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

  20. CMOS-MEMS transverse-mode square plate resonator with high Q and low motional impedance

    Microsoft Academic Search

    Ming-Huang Li; Wen-Chien Chen; Sheng-Shian Li

    2011-01-01

    An integrated CMOS-MEMS transverse-mode square plate resonator centered at 6.52 MHz has been demonstrated with Qs ranging from 800 to 1,900, and specifically with the lowest motional impedance of 35 k? compared to any other CMOS-MEMS counterparts to date by the combination of large transduction area and pull-in mechanism to achieve deep-submicron electrode-to-resonator gap spacing using a foundry-oriented CMOS-MEMS process.

  1. A 76 x 77mm2, 16.85 Million Pixel CMOS APS Image Sensor

    Microsoft Academic Search

    Suat U. Ay; Eric R. Fossum

    A 16.85 million pixel (4,096 x 4,114), single die (76mmx77mm) CMOS active pixel sensor (APS) image sensor with 1.35Me- pixel well-depth was designed, fabricated, and tested in a 0.5m CMOS process with a stitching option. A hybrid photodiode-photogate (HPDPG) APS pixel technology was developed. Pixel pitch was 18m. The developed image sensor was the world's largest single- die CMOS image

  2. A CMOS imager with on-chip variable resolution for light-adaptive imaging

    Microsoft Academic Search

    Zhimin Zhou; B. Pain; E. Fossum

    1998-01-01

    In addition to advantages of lower power and system miniaturization through camera-on-a-chip implementation, the CMOS active pixel image sensor (APS) enables development of smart imagers by integrating custom CMOS signal processing circuits on the focal plane. This CMOS APS imager is capable of enhancing signal to noise ratio (S\\/N) under low illumination through summation of signals from neighboring pixels. On-chip

  3. System-on-package ultra-wideband transmitter using CMOS impulse generator

    Microsoft Academic Search

    Junwoo Lee; Young-Jin Park; Myunghoi Kim; Changwook Yoon; Joungho Kim; Kwan-Ho Kim

    2006-01-01

    In this paper, a low-cost CMOS ultra-wideband (UWB) impulse transmitter module with a compact form factor is proposed for impulse-radio communications. The module consists of a CMOS impulse generator, a compact bandpass filter (BPF), and a printed planar UWB antenna. The impulse generator is designed using a Samsung 0.35-?m CMOS process for low-cost and low-power fabrication. The measurement shows the

  4. Building strong partnerships with CMOs.

    PubMed

    Dye, Carson F

    2014-07-01

    CFOs and chief medical officers (CMOs) can build on common traits to form productive partnerships in guiding healthcare organizations through the changes affecting the industry. CFOs can strengthen bonds with CMOs by taking steps to engage physicians on their own turf--by visiting clinical locations and attending medical-executive committee meetings, for example. Steps CFOs can take to help CMOs become more acquainted with the financial operations of health systems include demonstrating the impact of clinical decisions on costs and inviting CMOs to attend finance-related meetings. PMID:25076635

  5. Amplex, a low-noise, low-power analog CMOS signal processor for multi-element silicon particle detectors

    Microsoft Academic Search

    Eric Beuville; Kurt Borer; Enrico Guido Chesi; Erik H. M. Heijne; Pierre Jarron; Bohdan Lisowski; Simon Singh

    1990-01-01

    AMPLEX is a monolithic analog signal processor fabricated in 3 mum n-well CMOS and originally designed for the inner silicon detector of the UA2 Experiment at the CERN SPS Collider. However, it is suitable for various other types of detectors, and results are also given for a multiwire proportional chamber (MWPC). The chip contains 16 channels, each consisting of a

  6. A novel capacitive-type humidity sensor using CMOS fabrication technology

    Microsoft Academic Search

    Lei Gu; Qing-An Huang; Ming Qin

    2004-01-01

    This paper reports a novel capacitive humidity sensor integrated on a polysilicon heater. The sensor was fabricated with the industrial standard CMOS process to achieve a cost-effective solution for accurate and reliability. The sensing material polyimide was obtained by a post-processing step after the standard CMOS fabrication. The sensing principle of the sensor is based on the dielectric constant change

  7. CMOS Imaging Technology with Embedded Early Image Christophe Jean-Michel Basset

    E-print Network

    Perona, Pietro

    CMOS Imaging Technology with Embedded Early Image Processing Thesis by Christophe Jean suggested a partnership with JPL and the CMOS imaging group, Professors Ali Hajimiri, Christof Koch, Alain is to combine the processing unit with an active pixel sensors (APS) pixel array. This complementary metal

  8. Variation-Aware TED -Based Approach for Nano-CMOS RTL Leakage Optimization

    E-print Network

    Mohanty, Saraju P.

    Variation-Aware TED - Based Approach for Nano-CMOS RTL Leakage Optimization S. Banerjee, J. Mathew--As technology scales down to nanometer regime the process variations have profound effect on circuit char- acteristics. Meeting timing and power constraints under such process variations in nano-CMOS circuit design

  9. CMOS Gates Demonstration

    NSDL National Science Digital Library

    This website, hosted by the University of Hamburg, provides an in depth description of the basic operation of CMOS circuits including inverters, NAND gates, and NOR gates. Circuit simulations are shown and power dissipation is discussed. Some of these include: inverters, NAND and NOR gates, transmission gates, D-latch with T-gates, power consumption, complex gates and SRAM cells. Overall, the site is perfect for undergraduate computer science majors to learn more about the exciting topic of semiconductors.

  10. Integrated CMOS RF amplifier

    NASA Technical Reports Server (NTRS)

    Charity, C.; Whitaker, S.; Purviance, J.; Canaris, M.

    1990-01-01

    This paper reports an integrated 2.0 micron CMOS RF amplifier designed for amplification in the 420-450 MHz frequency band. Design techniques are shown for the test amplifier configuration. Problems of decreased amplifier bandwidth, gain element instability, and low Q values for the inductors were encountered. Techniques used to overcome these problems are discussed. Layouts of the various elements are described and a summary of the simulation results are included. Test circuits have been submitted to MOSIS for fabrication.

  11. Mitigating defective CMOS to Non-CMOS vias in CMOS\\/Molecular memories

    Microsoft Academic Search

    Nor Zaidi Haron; Said Hamdioui

    2010-01-01

    CMOS\\/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits. Similarly to existing 3D technology, vertical vias are utilized to connect the two components. Because of

  12. IR CMOS: infrared enhanced silicon imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

    2013-06-01

    SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

  13. Advances in fully CMOS integrated photonic devices

    NASA Astrophysics Data System (ADS)

    Michel, Jurgen; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Giziewicz, W. P.; Beals, M.; Kimerling, L. C.; Kopa, A.; Apsel, A. B.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.; Pomerene, A.; Carothers, D.; Grove, M. J.

    2007-02-01

    The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell University, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable optical filters.

  14. Wide-IF-Band CMOS Mixer Design

    Microsoft Academic Search

    Pei-Yuan Chiang; Chao-Wei Su; Sz-Yun Luo; Robert Hu; Christina F. Jou

    2010-01-01

    A wide-IF-band transistor mixer has been designed using a 0.13-??m RF-CMOS process where its RF frequency is 8.7-17.4 GHz, local oscillator (LO) fixed at 17.4 GHz, and IF up to 8.7 GHz. Proper layout arrangement for the Marchand balun has been discussed and then implemented; the output amplitude and phase imbalance are less than 0.5 dB and 1 ?? measured

  15. High-speed CMOS circuit technique

    Microsoft Academic Search

    JIREN YUAN; CHRISTER SVENSSON

    1989-01-01

    Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

  16. Accurate modeling and parameter extraction for meander-line N-well resistors

    Microsoft Academic Search

    Rizwan Murji; M. Jamal Deen

    2005-01-01

    Accurate modeling and efficient parameter extraction of a scalable lumped-element model for n-well meander-line resistors that are suitable for radio frequency integrated circuit (RF IC) applications is presented. The equivalent circuit is similar to the spiral inductor model but with modifications to the element equations. Direct extraction of component values is performed by analysis of measured Y-parameters. The extracted results

  17. 60GHz Four-Element Phased-Array Transmit\\/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

    Microsoft Academic Search

    Jing-Lin Kuo; Yi-Fong Lu; Ting-Yi Huang; Yi-Long Chang; Yi-Keng Hsieh; Pen-Jui Peng; I.-Chih Chang; Tzung-Chuen Tsai; Kun-Yao Kao; Wei-Yuan Hsiung; James Wang; Yungping Alvin Hsu; Kun-You Lin; Hsin-Chia Lu; Yi-Cheng Lin; Liang-Hung Lu; Tian-Wei Huang; Ruey-Beei Wu; Huei Wang

    2012-01-01

    AThe 60-GHz four-element phased-array transmit\\/receive (TX\\/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining\\/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital

  18. Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

    E-print Network

    Wladyslaw Szczesniak

    2008-01-07

    This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

  19. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  20. IR CMOS: ultrafast laser-enhanced silicon imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Hong, C.; Sahebi, F.; Palsule, C.; McKee, J.

    2012-06-01

    SiOnyx has developed a CMOS image sensor with enhanced infrared sensitivity. The technology deployed in this remarkable device is based on SiOnyx's proprietary ultrafast laser semiconductor process. We have established a high volume manufacturing process while maintaining complete compatibility with standard CMOS image sensor process flows. The enhanced performance proves the viability of a highly scalable low cost digital infrared sensor. The spectral sensitivity is from 400 to 1200 nm with measured quantum efficiency improvements of more than 3x at 940 nm.

  1. Noise Behavior of a 180 nm CMOS SOI Technology for Detector Front-End Electronics

    Microsoft Academic Search

    Valerio Re; Luigi Gaioni; Massimo Manghisoni; Lodovico Ratti; Valeria Speziali; Gianluca Traversi; Ray Yarema

    2008-01-01

    This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully

  2. Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

    Microsoft Academic Search

    V. Re; L. Gaioni; M. Manghisoni; L. Ratti; V. Speziali; G. Traversi; R. Yarema

    2007-01-01

    This paper is motivated by the growing interest of the detector and readout electronics community towards silicon- on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm

  3. Impact of CMOS technology scaling on the atmospheric neutron soft error rate

    Microsoft Academic Search

    Peter Hazucha; Christer Svensson

    2000-01-01

    We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size LG. A different

  4. High-Speed Peripheral Circuit for Geiger-Mode Avalanche Photodiode in Standard CMOS Technology

    E-print Network

    Choi, Woo-Young

    standard CMOS technology. With the proposed AQRC scheme, the dead time is decreased to 7 ns. I monitoring of CMOS processes and circuits, optical time domain reflectometry (OTDR), laser ranging reset, and delay circuits which are consisted of three inverters and control transistors. Although

  5. Design of radiation tolerant CMOS APS system-on-a-chip image sensors

    Microsoft Academic Search

    El-Sayed Eid; Suat U. Ay; Eric R. Fossum

    2002-01-01

    A methodology for designing radiation tolerant CMOS APS SOC image sensors is presented. It is based on the experimental results of test chips that had been designed, fabricated, and characterized. Details of the basic building blocks of a proposed design are presented. The proposed design is in a 0.35-?m CMOS standard process. The radiation tolerance level could be up to

  6. Thin, fully depleted monolithic active pixel sensor based on 3D integration of heterogeneous CMOS layers

    Microsoft Academic Search

    W. Dulinski; G. Bertolone; R. de Masi; Y. Degerli; A. Dorokhov; F. Morel; F. Orsini; L. Ratti; C. Santos; V. Re; X. Wei; M. Winter

    2009-01-01

    On the way towards fast, radiation tolerant and ultra thin CMOS radiation sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). In this process, each wafer may be thinned down to about 10 microns end equipped with through-silicon vias (TSV) allowing for electrical interconnection between wafers at a very

  7. Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits

    E-print Network

    Mohanty, Saraju P.

    the design space. However, in nano-CMOS technology, this is not the case. The effects of process variationGeostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits Oghenekarho Okobiah1 , Saraju P. Mohanty2 , and Elias Kougianos3 NanoSystem Design Laboratory (NSDL, http

  8. An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier

    Microsoft Academic Search

    M. A. Abdalla; C. Frjdh; C. S. Petersson

    2001-01-01

    We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in

  9. High voltage AlGaN/GaN metaloxidesemiconductor high-electron mobility transistors with regrown In0.14Ga0.86N contact using a CMOS compatible gold-free process

    NASA Astrophysics Data System (ADS)

    Liu, Xinke; Amin Bhuiyan, Maruf; S/O Somasuntharam, Pannirselvam; Beng Soh, Chew; Liu, Zhihong; Zhi Chi, Dong; Liu, Wei; Lu, Youming; Yu, Wenjie; Seow Tan, Leng; Yeo, Yee-Chia

    2014-12-01

    We report the fabrication and characterization of high voltage AlGaN/GaN metaloxidesemiconductor high-electron mobility transistors (MOSHEMTs) with selectively regrown In0.14Ga0.86N contact using a CMOS compatible gold-free process. Device with the regrown InGaN contact with a gate-to-drain spacing LGD of 5 m achieves an off-state breakdown voltage VBR of 800 V and on-state resistance Ron of 2 m?cm2. The VBR achieved in this work is higher than those of gold-free GaN MOSHEMTs with gate-to-drain spacing LGD below 10 m.

  10. An array-based CMOS biochip for electrical detection of DNA with multilayer self-assembly gold nanoparticles

    Microsoft Academic Search

    Yi-Ting Cheng; Ching-Chin Pun; Chien-Ying Tsai; Ping-Hei Chen

    2005-01-01

    This paper presents an array-based CMOS biochip for DNA detection using self-assembly multilayer gold nanoparticles (AuNPs). The biochip is fabricated by a TSMC 0.35?m standard CMOS process and post-CMOS micromachining processes. Before taking DNA detection measurements, self-assembly monolayer of AuNPs is established on SiO2 surface between two microelectrodes. The gap distance between the two microelectrodes in this study is less

  11. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  12. Regenerative switching CMOS system

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  13. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  14. Laser Operation of Nitride Laser Diodes with GaN Well Layer in 340 nm Band

    NASA Astrophysics Data System (ADS)

    Kuwabara, Masakazu; Yamashita, Yoji; Torii, Kousuke; Yoshida, Harumasa

    2013-08-01

    We have reported the laser operation of a short-wavelength ultraviolet laser diode with multiple quantum wells composed of GaN well layers. The GaN well-width is estimated to be around 1-1.5 nm. We have simulated whole laser-diode structure, and calculated wave-function overlap integrals. It is provided the integral becomes the maximum value in the well-width of 1.5 nm. The laser operation has been achieved in 340-nm-band under the pulsed current mode at room temperature. The wavelength is far from the wavelength corresponding to band gap of GaN, and the shortest lasing wavelength ever reported for a semiconductor laser composed of binary compound well layer. Moreover, the device has been realized on an Al0.2Ga0.8N underlying layer with 0.1 lower AlN mole fraction margin than that of a previous reported 342 nm laser-diode with an Al0.3Ga0.7N underlying layer. These results provide a chance to the next stage for a shorter-wavelength ultraviolet laser diode.

  15. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    SciTech Connect

    Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

  16. Predictions of CMOS compatible on-chip optical interconnect

    Microsoft Academic Search

    Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas A. Nelson; David H. Albonesi; Philippe M. Fauchet; Eby G. Friedman

    Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect

  17. Delay modeling and glitch estimation for CMOS circuits

    E-print Network

    Shiau, Yan-Chyuan

    1988-01-01

    the timing delay. 15 CHAPTER IV CAPACITANCE MODELING 4. 1 Units Used in Project The timing library I construct is based on the MOSIS CMOS 3prn processing parameters. Some important units are defined as following that will be used in this project: Time... CMOS process and simulate the output response by running SPICE. If we use different tool based on different technologies to calculate timing response, we may get distinct result dued to separate device parameters. 4. 3. 2 Circuit Structure A node...

  18. IR CMOS: ultrafast laser-enhanced silicon detection

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

    2011-06-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

  19. Black silicon enhanced photodetectors: a path to IR CMOS

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Homayoon, H.; Alie, S.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

    2010-04-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

  20. CMOS self-powered monolithic light-direction sensor with digitalized output.

    PubMed

    Wang, Hongyi; Luo, Tao; Lu, Zhijian; Song, Hongjiang; Christen, Jennifer Blain

    2014-05-01

    We present a novel self-powered chip to detect the direction of incident light. This chip directly provides digitized output without the need of any off-chip power supply or optical or mechanical components. The chip was implemented in a standard 0.5 ?m CMOS process. A microscale metal baffle was created by stacking all metal layers, contacts, and vias available in the process to produce on-chip shadowing. N-well/p+ photodiode arrays are located on both sides of the baffle to sense light. The photocurrent generated by a photodiode depends on the size of the photodiode and the shadowing. The shadowed area depends on the incident angle of the light. A current mirror circuit is used to compare the currents generated by the photodiodes on the opposite sides of the baffle and, consequently, provide a digital signal to indicate the incident light angle. Compared with the ideal linear digital light-angle detector with the same resolution, the presented sensor achieved the maximum error of only 2 deg over 110 deg test range. PMID:24784060

  1. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several advantages over the voltage-mode. The most important advantages of using current-mode technique are: reduced power consumption of the chip, ease of arithmetic operations implementation, simplification of the circuit design and hence reduced layout complexity.

  2. Noise Sources in Bulk CMOS

    Microsoft Academic Search

    Kent H. Lundberg

    The noise behavior of bulk CMOS devices is dominated primarily by two noise sources: thermal noise and ?icker (1=f) noise. Other sources that are sometimes present in the noise spectrum are shot noise, generation\\/recombination noise, and \\\\popcorn\\

  3. Transistor sizing in CMOS circuits

    Microsoft Academic Search

    Mehmet A. Cirit

    1987-01-01

    The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

  4. Reliability evaluation of CMOS RAMs

    Microsoft Academic Search

    C. J. Salvo; A. T. Sasaki

    1982-01-01

    The results of an evaluation of the reliability of a 1K x 1 bit CMOS RAM and a 4K x 1 bit CMOS RAM for the USAF are reported. The tests consisted of temperature cycling, thermal shock, electrical overstress-static discharge and accelerated life test cells. The study indicates that the devices have high reliability potential for military applications. Use-temperature failure

  5. A 76 x 77mm\\/sup 2\\/, 16.85 Million Pixel CMOS APS Image Sensor

    Microsoft Academic Search

    Suat U. Ay; Eric R. Fossum

    2006-01-01

    A 16.85 million pixel (4,096 times 4,114), single die (76mm times 77mm) CMOS active pixel sensor (APS) image sensor with 1.35Me- pixel well-depth was designed, fabricated, and tested in a 0.5mum CMOS process with a stitching option. A hybrid photodiode-photogate (HPDPG) APS pixel technology was developed. Pixel pitch was 18mum. The developed image sensor was the world's largest single-die CMOS

  6. Figures of merit for CMOS SPADs and arrays

    NASA Astrophysics Data System (ADS)

    Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

    2013-05-01

    SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

  7. CMOS APS PHOTORESPONSE AND CROSSTALK OPTIMIZATION ANALYSIS FOR SCALABLE CMOS TECHNOLOGIES

    E-print Network

    1 CMOS APS PHOTORESPONSE AND CROSSTALK OPTIMIZATION ANALYSIS FOR SCALABLE CMOS TECHNOLOGIES Igor developed for photoresponse estimation of a photodiode based CMOS Active Pixel Sensor (APS). We show its use for maximum pixel photosignal prediction and CMOS APS crosstalk (CTK) optimization. Our model reveals

  8. High-voltage MOS transistors compatible with CMOS VLSI technology

    NASA Astrophysics Data System (ADS)

    Podmiotko, Wlodzimierz

    1992-08-01

    In this paper high-voltage MOS transistors structures fabricated using a standard CMOS technology and a special design technique are presented. The design, characterization, and modeling of n-MOS, with the breakdown voltage of 50 V, and p-MOS, with the breakdown voltage of 130 V, fabricated using a standard 3 micrometers CMOS process are discussed. In addition, the possibility of high-voltage buffer circuit realization which is composed of n-MOS and p-MOS transistors, operating with the supply system USS equals 0, UDD equals 5 V, UE equals - 40 V, self-isolated from low-voltage components is demonstrated.

  9. A very high frequency CMOS Variable Gain Amplifier

    E-print Network

    Tan, Siang Tong

    2001-01-01

    A VERY HIGH FREQUENCY CMOS VARIABLE GAIN AMPLIFIER A Thesis by SIANG TONG TAN Submitted to the Office of Graduate Studies of Texas AgrM University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE December 2001... of an analog multiplier, current gain stages, and resistor loads is designed for very high frequency applications. The gain can be programmed from OdB to 40dB with -3dB bandwidth greater than 200MHz and 500MHz in 0. 5ltm and 0. 35pm CMOS process...

  10. Finding Open Faults In CMOS Circuits

    NASA Technical Reports Server (NTRS)

    Chandramouli, R.

    1984-01-01

    Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.

  11. CMOS time-resolved, contact, and multispectral fluorescence imaging for DNA molecular diagnostics.

    PubMed

    Guo, Nan; Cheung, Kawai; Wong, Hiu Tong; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  12. Multiemitter BiCMOS logic circuit family

    Microsoft Academic Search

    Gerard Boudon; Pierre Mollier; Ieng Ong; Jean-Paul Nuez; Daniel Mauchauffee; Dominique Plassat; Jean-Louis Simonet; Frank Wallart

    1991-01-01

    A new multiemitter BiCMOS circuit using half-micrometer BiCMOS technology with a 3.6-V supply provides 85 % improvement in delay over CMOS design and 40 % improvement over conventional BiCMOS. This benefit is demonstrated in a 64-b carry look-ahead adder where most of the gates have a high number of inputs. A complete logic circuit family based on the multiemitter (ME)

  13. CMOS technology characterization for analog and RF design

    Microsoft Academic Search

    Behzad Razavi

    1999-01-01

    The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's digital technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution.

  14. Analog CMOS synaptic learning circuits adapted from invertebrate biology

    Microsoft Academic Search

    Christian Schneider; Howard Card

    1991-01-01

    Analog CMOS circuits implementing abstractions of certain biological synaptic processes are presented. In particular, the circuits extract features of synaptic learning observed in the marine mollusk Aplysia. Two types of nonassociative learning, habituation and sensitization, as well as associative learning (classical conditioning), are modeled. The synaptic learning rules used by Aplysia are considerably more complex than those typically used in

  15. A Planar CMOS Field-Emission Vacuum Magnetic Sensor

    Microsoft Academic Search

    Paul J. French; Anthony J. Kenyon; David M. Garner

    2009-01-01

    We have fabricated a CMOS vacuum magnetic sensor that exploits the deflection of an electron beam produced by field emission by a perpendicular magnetic field. The device is planar and fabricated by conventional lithography and etching processes. An extremely high magnetic field sensitivity of 4times103%\\/T is reported.

  16. The Evolution of Digital Imaging: From CCD to CMOS

    E-print Network

    La Rosa, Andres H.

    the grandfathers of the digital imaging revolution, which has all but converted cameras and video recorders fromThe Evolution of Digital Imaging: From CCD to CMOS A Micron White Paper Digital imaging began into electrical charges have become increasingly efficient. The processes for transforming optical to digital have

  17. Verity - A formal verification program for custom CMOS circuits

    Microsoft Academic Search

    Andreas Kuehlmann; Arvind Srinivasan; David P. Lapotin

    1995-01-01

    In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of cur- rent generation processors and the necessity for manual designer intervention through- out the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the

  18. A 0.06 mm2 1.0 V 2.5 mW 10 bit 250 MS/s current-steering D/A converter in 65 nm GP CMOS process

    NASA Astrophysics Data System (ADS)

    Yawei, Guo; Li, Li; Peng, Ou; Zhida, Hui; Xu, Cheng; Xiaoyang, Zeng

    2014-06-01

    A 10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard VT core devices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity (INL) yield with both end-point line and best-fit line. A formula is derived for the relationship of INL and output impedance. The relation of dynamic range and output impedance is also discussed. The double centroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to overcome the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.

  19. Radio-frequency integrated-circuit design for CMOS single-chip UWB systems

    E-print Network

    Jin, Yalin

    2009-05-15

    integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF...

  20. A 0.18 ?m BiCMOS technology featuring 120\\/100 GHz (fT\\/fmax) HBT and ASIC-compatible CMOS using copper interconnect

    Microsoft Academic Search

    A. Joseph; D. Coolbaugh; M. Zierak; R. Wuthrich; P. Geiss; Z. He; X. Liu; B. Orner; J. Johnson; G. Freeman; D. Ahlgren; B. Jagannathan; L. Lanzerotti; V. Ramachandran; J. Malinowski; H. Chen; J. Chu; P. Gray; R. Johnson; J. Dunn; S. Subbanna; K. Schonenberg; D. Harame; R. Groves; K. Watson; D. Jadus; M. Meghelli; A. Rylyakov

    2001-01-01

    A BiCMOS technology is presented that integrates a high performance NPN (fT=120 GHz and fmax=100 GHz), ASIC compatible 0.11 ?m Leff CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved

  1. Above-CMOS aSi and CIGS solar cells for powering autonomous microsystems

    Microsoft Academic Search

    J. Lu; W. Liu; A. Y. Kovalgin; Y. Sun; R. E. I. Schropp; J. Schmitz

    2010-01-01

    Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copper-indium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress can be resolved while maintaining standard photovoltaic processing.

  2. Strained-SOI\\/SGOI Dual Channel CMOS Technology Based on Ge Condensation Technique

    Microsoft Academic Search

    T. Tezuka; S. Nakaharai; Y. Moriyama; N. Hirashita; E. Toyoda; T. Numata; T. Irisawa; K. Usuda; N. Sugiyama; T. Mizuno; S. I. Takagi

    2006-01-01

    In this paper, fabrication of the dual channel CMOS devices based on the Ge-condensation technique is demonstrated as well as their mobility and current drive enhancements. Ge-rich strained SGOI pMOSFETs were integrated with strained Si\\/SGOI nMOSFETs by a CMOS process combined with the Ge condensation process, in which the strain in the SGOI layers were properly controlled. As a result,

  3. CMUT-in-CMOS ultrasonic transducer arrays with on-chip electronics

    Microsoft Academic Search

    X. Cheng; D. F. Lemmerhirt; O. D. Kripfgans; M. Zhang; C. Yang; C. A. Rich; J. B. Fowlkes

    2009-01-01

    Integration of a 2D ultrasound transducer array with front-end signal conditioning electronics poses significant fabrication and packaging challenges due to the required number of elements and small element pitch. In this paper, we demonstrate a CMUT-in-CMOS approach that produces ultrasonic transducers and circuits on a single chip using a standard foundry CMOS process, augmented only with two blanket post-process steps

  4. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  5. Programmable multiresolution CMOS active pixel sensor Roger Panicacci, Sabrina Kemeny, Larry Matthies, Bedabrata Pain, and Eric R. Fossum

    E-print Network

    Fossum, Eric R.

    Programmable multiresolution CMOS active pixel sensor Roger Panicacci, Sabrina Kemeny, Larry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off necessary for the task at hand and eliminate unnecessary processing steps. The multiresolution image data

  6. A very low offset voltage auto-zero stabilized CMOS operational amplifier Daniel DZAHINI (1), Hamid Ghazlane (2)

    E-print Network

    Paris-Sud XI, Université de

    A very low offset voltage auto-zero stabilized CMOS operational amplifier Daniel DZAHINI (1), Hamid Abstract: A high precision operational amplifier has been developed in a standard .8µ CMOS process less than 2µV -100nV/°C. The amplifier with its output buffer consumes 5mW at a supply voltage of +/- 2

  7. Abstract --We describe a MEMS-on-CMOS microsystem to encage, culture, and monitor cells. The system was designed

    E-print Network

    Maryland at College Park, University of

    Abstract -- We describe a MEMS-on-CMOS microsystem to encage, culture, and monitor cells. A MEMS process flow was developed for the fabrication of closeable micro-vials to contain each cell, a custom bio-amplifier CMOS chip was designed, fabricated, and tested, and the fabrication of the MEMS

  8. Fully CMOS analog and digital SiPMs

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-03-01

    Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon-number resolving capability and immunity to magnetic fields. We present three families of analog SiPM fabricated in a reliable and cost-effective fully standard planar CMOS technology with a total photosensitive area of 11 mm2. These three families have different active areas with fill-factors (21%, 58.3%, 73.7%) comparable to those of commercial SiPM, which are developed in vertical (current flow) custom technologies. The peak photon detection efficiency in the near-UV tops at 38% (fill-factor included) comparable to commercial custom-process ones and dark count rate density is just a little higher than the best-in-class commercial analog SiPMs. Thanks to the CMOS processing, these new SiPMs can be integrated together with active components and electronics both within the microcell and on-chip, in order to act at the microcell level or to perform global pre-processing. We also report CMOS digital SiPMs in the same standard CMOS technology, based on microcells with digitalized processing, all integrated on-chip. This CMOS digital SiPMs has four 321 cells (128 microcells), each consisting of SPAD, active quenching circuit with adjustable dead time, digital control (to switch off noisy SPADs and readout position of detected photons), and fast trigger output signal. The achieved 20% fill-factor is still very good.

  9. Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio

    Microsoft Academic Search

    Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

    2007-01-01

    Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

  10. Comparison of passive and active pixel schemes for CMOS visible imagers

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.; Luo, J.; Kleinhans, W. E.; Liu, T.

    1998-09-01

    An active pixel sensor (APS) integrated in standard CMOS process technology is shown to be superior to an alternative passive pixel sensor (PPS). Further, the CMOS APS provides video sensitivity and SNR comparable to CCDs. Though the CMOS PPS has lower performance, it offers >50% optical fill factor without microlenses and can be produced at lower cost for applications not requiring broadcast quality SNR (>35 dB) under low light conditions (<20 lx). APS and PPS SNRs of 50 dB and 44 dB are reported at 200 lx using green filtering with ~80 nm bandpass.

  11. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  12. Metrology Of Silicide Contacts For Future CMOS

    NASA Astrophysics Data System (ADS)

    Zollner, Stefan; Gregory, Richard B.; Kottke, M. L.; Vartanian, Victor; Wang, Xiang-Dong; Theodore, David; Fejes, P. L.; Conner, J. R.; Raymond, Mark; Zhu, Xiaoyan; Denning, Dean; Bolton, Scott; Chang, Kyuhwan; Noble, Ross; Jahanbani, Mohamad; Rossow, Marc; Goedeke, Darren; Filipiak, Stan; Garcia, Ricardo; Jawarani, Dharmesh; Taylor, Bill; Nguyen, Bich-Yen; Crabtree, P. E.; Thean, Aaron

    2007-09-01

    Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low-resistance contacts between the back-end (W plugs and Cu interconnects) and front-end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and CoSi2, NiSi is a mid-gap silicide, i.e., the Fermi level of the NiSi metal is pinned half-way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source-drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band-edge silicides, such as PtSi for contacts to p-type or rare earth silicides for contacts to n-type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufacturing, with special emphasis on x-ray reflectance and x-ray fluorescence. We also report measurement methods useful for development of a PtSi PMOS module.

  13. A novel colour-sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-10-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  14. CMOS image sensor with contour enhancement

    NASA Astrophysics Data System (ADS)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 1616 2D circuit array are implemented using CSMC 0.5?m DPTM CMOS process.

  15. A CMOS baseband receiver for wireless broadband communications

    Microsoft Academic Search

    Seunghyun Jang; Seung-Sik Lee; Sang-Sung Choi; Kwang-Chun Lee

    2010-01-01

    This paper presents an UWB baseband receiver including VGAs, LPFs, FGAs and IO buffers, fully integrated in 130 nm CMOS process. The voltage gain range by two VGAs and a FGA for each I\\/Q path is from -5 to +65 dB providing a dynamic range of 70 dB. For a more stable operation against variations in process, voltage and temperature

  16. Low-power CMOS energy detector for noncoherent impulse-radio UWB receivers

    Microsoft Academic Search

    N. Dehaese; M. Battista; R. Vauche?; S. Bourdel; J. Gaubert; O. Fourquin; N. Tall

    2010-01-01

    A low power CMOS energy detector for 3.1-10.6 GHz non-coherent impulse-radio UWB receivers is implemented in a 0.13 ?m CMOS process. The detector architecture is based on a squarer circuit realized with MOS transistors biased in the sub-threshold region. The squared signal is integrated using a low pass amplifier that allows the receiver gain to be optimized. A comparator with

  17. Front end electronics for silicon strip detectors in 90nm CMOS technology: advantages and challenges

    Microsoft Academic Search

    J. Kaplon; M. Noy

    2010-01-01

    We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. The primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors in Super Large Hadron Collider (SLHC) experiments [1]. In the presented design we

  18. The integrated 2W high voltage\\/high power 0. 12-?m RF CMOS power amplifier

    Microsoft Academic Search

    L. Wu; R. Tao; U. Basaran; J. Luger; I. Dettmann; M. Berroth

    2004-01-01

    A 2W HiVP power amplifier for GSM mobile communication system is designed using 0.12-m CMOS process. To solve the problem of low breakdown voltage in deep-submicron CMOS technology, the new High Voltage\\/High Power (HiVP) device configuration is used. With HiVP configuration, a large voltage can be divided by several devices, so that the voltage drop on each device is reduced.

  19. Design Considerations for Sub-mW RF CMOS Low-Noise Amplifiers

    Microsoft Academic Search

    Derek Ho; Shahriar Mirabbasi

    2007-01-01

    Design considerations for sub-mW fully integrated narrow-band RF CMOS low-noise amplifiers (LNAs) are presented. The impacts of device-level properties and biasing on gain, noise, linearity, and power consumption of an LNA are discussed. Based on the design trade-offs discussed in the paper, a cascode LNA is designed and simulated in a standard 90 nm CMOS process to operate in the

  20. 1Gb\\/s integrated optical detectors and receivers in commercial CMOS technologies

    Microsoft Academic Search

    T. K. Woodward; Ashok V. Krishnamoorthy

    1999-01-01

    The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and

  1. A K-band integrated bandpass filter in 90-nm CMOS technology

    Microsoft Academic Search

    Vikram Sekar; Kamran Entesari

    2011-01-01

    This paper investigates the design and imple- mentation of integrated bandpass filters in standard 90-nm CMOS technology for K-band applications. A Chebyshev bandpass filter with a measured 7% 1-dB bandwidth at 20 GHz is realized using lumped-element components. Meander- line inductors are implemented using the thick metallization layer of the CMOS process to improve the filter quality factor. Metal-insulator-metal (MIM)

  2. Technologies for (sub-) 45nm Analog\\/RF CMOS - Circuit Design Opportunities and Challenges

    Microsoft Academic Search

    S. Decoutere; P. Wambacq; V. Subramanian; J. Borremans; A. Mercha

    2006-01-01

    The new process module and device architecture options emerging for (sub-) 45nm CMOS, lead to both opportunities and challenges for analog\\/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for

  3. RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications

    Microsoft Academic Search

    Suzy A. Jackson; CSIRO Australia

    2004-01-01

    New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS Receiver-on-a-Chip is being developed as part of an Australia Telescope program looking at technologies associated with the

  4. Performance and power evaluation of a 3D CMOS\\/nanomaterial reconfigurable architecture

    Microsoft Academic Search

    Chen Dong; Deming Chen; Sansiri Tanachutiwat; Wei Wang

    2007-01-01

    In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS-nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the

  5. Wide-Band CMOS Circuit Design Techniques for RF Amplifier and Ring VCO

    Microsoft Academic Search

    N. Ishihara; R. Ujiie; K. Shibata; H. Sato

    2007-01-01

    RF CMOS circuit design techniques for ultrawideband (UWD) applications are presented. In the RF amplifier design, a combination of a constant-k filter and a resistive shunt feedback circuit is suggested for wide-band operation. We report that a circuit integrated by using 0.13-mum CMOS process technology has achieved an operation bandwidth from 2 to 5.8 GHz with a peak gain of

  6. Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters

    Microsoft Academic Search

    Johan Wernehag; Henrik Sjland

    2009-01-01

    An active polyphase filter capable of high frequency quadrature signal generation has been analyzed. The resistors of the\\u000a classical passive polyphase filter have been replaced by transconductors, CMOS inverters (F. Tillman and H. Sjland, Proceedings of the Norchip Conference (pp. 1215), Nov. 2005; Analog Integrated Circuits and Signal Processing, 50(1) 712, 2007). A three-stage 0.13?m CMOS active polyphase filter has

  7. A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

    Microsoft Academic Search

    Kyu Hwan An; Dong Ho Lee; Ockgoo Lee; Hyungwook Kim; Jeonghu Han; Woonyun Kim; Chang-Ho Lee; Haksun Kim; Joy Laskar

    2009-01-01

    A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mum CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31

  8. Optoelectronic recirculating implementation of crossover interconnection network based on CMOS\\/SEED smart pixel technology

    Microsoft Academic Search

    Fengguang Luo; Mingcui Cao; K. W Wong; L. M Cheng

    1999-01-01

    A recirculating implementation of the crossover interconnection network based on optoelectronic architecture is presented in this paper. A flip-chip assembled CMOS\\/SEED (self-electro-optic-effect device) smart pixel array is used in this construction. The SEED array performs the optical-electrical conversion using a number of detectors and modulators while the CMOS devices handle the efficient logical processing. A combination of these two devices

  9. CMOS-based smart-electrode-type retinal stimulator with bullet-shaped bulk Pt electrodes.

    PubMed

    Tokuda, T; Ito, T; Kitao, T; Noda, T; Sasagawa, K; Terasawa, Y; Tashiro, H; Kanda, H; Fujikado, T; Ohta, J

    2011-01-01

    A CMOS-based flexible retinal stimulator equipped with bullet-shaped bulk Pt electrodes was fabricated and demonstrated. We designed a new CMOS unit chip with an on-chip stimulator, single- and multi-site stimulation modes, and monitoring functions. We have developed a new structure and packaging process of flexible retinal stimulator with bullet-type bulk Pt electrode. We have confirmed the retinal stimulation functionality in an in vivo stimulation trial on rabbit's retina. PMID:22255884

  10. Design and characterization of CMOS APS imagers with two different technologies

    Microsoft Academic Search

    Cyril Cavadore; Johannes Solhusvik; Pierre Magnan; Anne Gautrand; Yavuz Degerli; Francis Lavernhe; Jean A. Farre; Olivier Saint-Pe; Robert Davancens; Michel Tulet

    1998-01-01

    In the paper, we present experimental results from measurements on CMOS PAS imager designed by CIMI-SUPAERO on two different technologies. In both cases, pixels with photoMos and photodiode structures have been designed. The first circuit has been developed using a standard CMOS DLP\\/DLM 1.2 micrometers process from Austria Micro Systems. The detector array consists of 32 X 32 square pixels

  11. A single chip CMOS APS camera with direct frame difference output

    Microsoft Academic Search

    Shyh-Yih Ma; Liang-Gee Chen

    1999-01-01

    A CMOS active pixel sensor with direct frame difference output is reported in this paper. The proposed pixel circuit includes a photodiode and nine transistors and is optimized for low voltage operation. A 12896 pixel prototype camera chip with an on-chip 8-bit pipeline ADC was fabricated in a 0.5 ?m double poly double metal CMOS process. At 3.3 V, the

  12. A Two-Step Readout CMOS Image Sensor Active Pixel Architecture

    E-print Network

    Hornsey, Richard

    A Two-Step Readout CMOS Image Sensor Active Pixel Architecture Tsung-Hsun Tsai and Richard Hornsey@cse.yorku.ca, hornsey@cse.yorku.ca Abstract--In this paper, we introduce a 5-transistor (5T) active pixel sensor (APS with an array of 32 92 pixels in a 0.13m digital CMOS process and tested with a 1.25 V supply voltage. I

  13. A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

    Microsoft Academic Search

    Atsushi Ohba; Shigeki Ohbayashi; Toru Shiomi; Satoshi Takano; Kenji Anami; Hiroki Honda; Yoshiyuki Ishigaki; Masahiro Hatanaka; Shigeo Nagao; Shimpei Kayano

    1991-01-01

    A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 ?m BiCMOS process. An improved buffer with a high-level output of nearly VCC is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a

  14. An advanced 0.4 ?m BiCMOS technology for high performance ASIC applications

    Microsoft Academic Search

    J. Kirchgessner; J. Teplik; V. Ilderem; D. Morgan; R. Parmar; S. R. Wilson; J. Freeman; C. Tracy; S. Cosentino

    1991-01-01

    An advanced 0.4 ?m BiCMOS technology has been developed for high-performance ASIC (application-specific integrated circuit) applications. The technology consists of a core 3.3 V CMOS process featuring 0.4 ?m effective channel lengths into which a high-performance n-p-n device module has been integrated. The ECL (emitter coupled logic) circuits are designed to operate with a conventional supply voltage of 5.2 V

  15. A 5.2mW 240550MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18?m CMOS process

    Microsoft Academic Search

    Mostafa Savadi Oskooei; N. Masoumi; M. Kamarei

    2008-01-01

    A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-?m CMOS technology\\u000a is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240550MHz. The gain of the filter is tuned\\u000a about 44dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4dBm is achieved for a power consumption

  16. A 3.4pJ FeRAM-enabled D flip-flop in 0.13m CMOS for nonvolatile processing in digital systems

    E-print Network

    Qazi, Masood

    Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance ...

  17. A wide band CMOS RF power detector

    Microsoft Academic Search

    Yijun ZhouandMichael; M. Chia Yan Wah

    2006-01-01

    This paper presents a wide band CMOS RF power detector using 0.25 mum technology. It includes a CMOS power detector unit, a chopper modulator and a logarithmic amplifier. Chopper technique is applied to reduce the dc offset. The CMOS RF power detector achieves 45 dB dynamic range with bandwidth up to 6 GHz. The power consumption is 17 mW from

  18. RF power amplifier integration in CMOS technology

    Microsoft Academic Search

    Y. J. E. Chen; M. Hamai; D. Heo; A. Sutono; S. Yoo; J. Laskar

    2000-01-01

    This paper explores different levels of integration for CMOS RF power amplifiers, including integration fully on chip, integration with LTCC passive components, and integration with off-chip components. At 1.9 GHz, the fully on-chip integrated CMOS PA can deliver 20 dBm output power with 16% efficiency. Because the LTCC inductors have much higher Q than the on-chip inductors, the CMOS PA

  19. Performance of downward scaled CMOS\\/SOS

    Microsoft Academic Search

    Sinji TAGUCHI; Hiroyuki TANGO; Kenji MAEGUCHI; Luong Mo Dang

    1979-01-01

    MOS\\/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS\\/ SOS devices. Furthermore, short channel CMOS\\/SOS device performance has been discussed in comparison with the CMOS\\/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through

  20. High speed CMOS technology for ASIC application

    Microsoft Academic Search

    H. Ooka; S. Murakami; M. Murayama; K. Yoshida; S. Takao; O. Kudoh

    1986-01-01

    In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 m, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD3structure is employed for 1.0 m

  1. Novel low-temperature CMOS-compatible full-wafer-bonding process for the fabrication of 3D embedded microchannels using SU8

    Microsoft Academic Search

    Francisco J. Blanco; Maria Agirregabiria; Maria Tijero; Javier Berganzo; Jorge Garcia; Maria Arroyo; Jesus M. Ruano; Inigo Aramburu; Kepa Mayora

    2004-01-01

    This article describes a novel low temperature full wafer adhesive bonding process to fabricate three-dimensional (3-D) embedded microchannels using SU-8 photoresist as structural material. The technology development includes an improvement of the SU-8 photolithography process in order to produce high uniformity films using Taguchi methodology. After that, 3-D embedded microchannels are fabricated by a low temperature adhesive bonding of the

  2. Reliability evaluation of CMOS RAMs

    NASA Astrophysics Data System (ADS)

    Salvo, C. J.; Sasaki, A. T.

    The results of an evaluation of the reliability of a 1K x 1 bit CMOS RAM and a 4K x 1 bit CMOS RAM for the USAF are reported. The tests consisted of temperature cycling, thermal shock, electrical overstress-static discharge and accelerated life test cells. The study indicates that the devices have high reliability potential for military applications. Use-temperature failure rates at 100 C were 0.54 x 10 to the -5th failures/hour for the 1K RAM and 0.21 x 10 to the -5th failures/hour for the 4K RAM. Only minimal electrostatic discharge damage was noted in the devices when they were subjected to multiple pulses at 1000 Vdc, and redesign of the 7 Vdc quiescent parameter of the 4K RAM is expected to raise its field threshold voltage.

  3. Process dependent antenna ratio rules for HSQ and FSG back-ends of (embedded flash) 0.18 ?m CMOS technology

    Microsoft Academic Search

    A. Scarpa; M. Diekema; C. van der Schaar; H. Valk; A. Harke; F. G. Kuper

    2002-01-01

    The charging damage induced by the inter-metal dielectric deposition in a hydrogen silsequioxane (HSQ) and in a fluorinated-silica glass (FSG) now are compared in a worst case scenario experiment, carried out in a 0.18 ?m embedded flash process. It is shown that different charging damage mechanisms take place in the two flows, calling for different definitions of antenna ratios and

  4. CMOS microelectrode array for the monitoring of electrogenic cells

    Microsoft Academic Search

    F. Heer; W. Franks; A. Blau; S. Taschini; C. Ziegler; A. Hierlemann; H. Baltes

    2004-01-01

    Signal degradation and an array size dictated by the number of available interconnects are the two main limitations inherent to standalone microelectrode arrays (MEAs). A new biochip consisting of an array of microelectrodes with fully-integrated analog and digital circuitry realized in an industrial CMOS process addresses these issues. The device is capable of on-chip signal filtering for improved signal-to-noise ratio

  5. Variable gain CMOS potentiostat for dissolved oxygen sensor

    Microsoft Academic Search

    Mei Yee Ng; Yuzman Yusoff

    2010-01-01

    This paper presents a variable gain potetiostat designed for the electrochemical control of Dissolved Oxygen (DO) sensors. The design is targeted for implementation using MIMOS 0.35 um CMOS process technology at 3.3V. The potentiostat amplifier for dissolved oxygen utilizes three electrodes (working, reference and counter) which work together to form the electrochemical reaction. There are several types of DO sensor

  6. A CMOS focal-plane array for heterodyne terahertz imaging

    Microsoft Academic Search

    Ullrich R. Pfeiffer; E. Ojefors; A. Lisaukas; D. Glaab; H. G. Roskos

    2009-01-01

    In this paper we present a focal-plane array (FPA) for heterodyne imaging at 0.65-THz in a low-cost 0.25-mum CMOS process technology. The 3times5 pixel array is fully integrated on chip and consists of differential patch antennas, NMOS square-law mixers, and 43-dB low-IF amplifiers. The NMOS square-law mixers are based on distributed resistive self-mixing and facilitate mixing well beyond the cutoff

  7. A CMOS focal-plane array for terahertz imaging

    Microsoft Academic Search

    U. R. Pfeiffer; E. Ojefors; A. Lisauskas; D. Glaab; F. Voltolina; V. M. F. Nzogang; P. H. Bolivar; H. G. Roskos

    2008-01-01

    A terahertz focal-plane array (FPA) for video-rate imaging applications has been fabricated in a commercially available CMOS process technology. The 3times5 pixel array uses conventional low-cost quarter-micron NMOS transistors for incoherent power detection. Each pixel has a size of 150times150 mum2 and consists of an on-chip antenna, an incoherent power detection circuit, and a 43-dB amplifier with a 1.6-MHz bandwidth.

  8. Adaptive Denoising Filter Algorithm for CMOS Image Sensor Testing Applications

    Microsoft Academic Search

    Chun-Lung Hsu; Chen-Wei Lan; Yu-Chih Lo; Yu-Sheng Huang

    2010-01-01

    This paper proposes an adaptive de-nosing filter (ADF) algorithm to effectively remove the image defects for the CMOS image sensor testing applications. Based on the median filter technique, the proposed ADF algorithm develops a pre-processing method to generate adaptive detection windows for pixel defect de-noising of an image. Experimental results and comparisons show that the proposed ADF algorithm can provide

  9. Influence of pixel topology on performances of CMOS APS imagers

    Microsoft Academic Search

    Pierre Magnan; Anne Gautrand; Yavuz Degerli; C. Marques; Francis Lavernhe; Cyril Cavadore; F. Corbiere; Jean A. Farre; Olivier Saint-Pe; Michel Tulet; Robert Davancens

    2000-01-01

    This paper describes a 128 X 128 pixels prototype array organized as sub-arrays of 32 X 32 pixels each, with 21 micrometers pixel pitch. The sub-arrays, photodiode or photogate based, are implemented using a standard 0.7 micrometers CMOS process. Various topologies of the photosensitive area have been implemented and some of them have an optical metal shield over the so-called

  10. Normal Optical Flow measurement on a CMOS APS imager

    Microsoft Academic Search

    Swati Mehta; Ralph Etienne-cummings

    2004-01-01

    Results from a 2-D dense Normal Optical Flow measurement chip implemented in 0.5 ?m CMOS process are presented. The chip has a 9252 array of APS pixels, occupies an area of 4.5 mm2 and consumes 2.6 mW power. To illustrate the operation of the chip, we present the results of individual blocks and then the whole structure. We also demonstrate

  11. Challenges in integrated CMOS transceivers for short distance wireless

    Microsoft Academic Search

    Khurram Muhammad; Robert B. Straszewski; Poras T. Balsara

    2001-01-01

    This paper presents recent trends in the area of integrated CMOS transceiver design for short distance wireless applications. This application is characterized by very low-cost and low-power so- lutions. Current challenges and recent trends are described and digital-oriented design opportunities for increasing integration out- lined. Signal processing approaches applied to the front-end elec- tronics find an increasing emphasis and are

  12. CMOS\\/SOS memory circuits for radiation environments

    Microsoft Academic Search

    TEGZE P. HARASZTI

    1978-01-01

    Memory circuit techniques which combine radiation hardness with high density, high speed, and low power dissipation have been developed. CMOS\\/SOS circuits featuring self-compensation, self-biasing, and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations may occur as the result of exposure to a nuclear radiation event or from MOS device processing, temperature, or power-supply effects. The

  13. Del 1: Grunnleggende Digital CMOS YNGVAR BERG

    E-print Network

    Sahay, Sundeep

    Del 1: Grunnleggende Digital CMOS YNGVAR BERG I. Innhold TRANSISTOR SOM BRYTER anvendt i enkleMOS transistorer. Pass transistorer og transmisjonsporter. Tristate buffer og tristate inverter. Ulike typer. 2. Transistor som bryter. Kapittel 1.3 side 9. 3. CMOS inverter. Kapittel 1.4.1 side 10. 4. NAND

  14. Output transition time modeling of CMOS structures

    Microsoft Academic Search

    Philippe Maurine; Mustapha Rezzoug; Daniel Auvergne

    2001-01-01

    Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates

  15. Optimum design of CMOS APS imagers

    Microsoft Academic Search

    Victor A. Shilin; Pavel A. Skrylev; Alexander L. Stempkovsky

    2003-01-01

    The main problem for CMOS active pixel sensors (APS) design is its fill factor and photosensitivity improvement. Using developed CMOS APS models we have solved this problem as mathematical optimization task. The fill factor is the aim function. The limits are: time delays, signal-to-noise ratio, horizontal and vertical MTFs, pixel sizes, and project rules. The simulation results for APS based

  16. JPL CMOS Active Pixel Sensor Technology

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  17. A CMOS signed multiplier using wave pipelining

    Microsoft Academic Search

    V. D. Nguyen; W. Liu; C. T. Gray; R. K. Cavin

    1993-01-01

    The authors present a high-performance 8 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption.

  18. Maintaining the benefits of CMOS scaling when scaling bogs down

    Microsoft Academic Search

    Edward J. Nowak

    2002-01-01

    A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it

  19. NanoNano--CMOS MixedCMOS Mixed--Signal CircuitSignal CircuitNanoNano CMOS MixedCMOS Mixed Signal CircuitSignal Circuit MetamodelingMetamodeling TechniquesTechniques

    E-print Network

    Mohanty, Saraju P.

    NanoNano--CMOS MixedCMOS Mixed--Signal CircuitSignal CircuitNanoNano CMOS MixedCMOS Mixed Signal NanoSystem Design Laboratory (NSDL, http://nsdl.cse.unt.edu), University of North Texas Denton TX 76203 This paper targets sampling techniques which are technology independent and the amount that is needed

  20. A New CMOS Read-out IC for Uncooled Microbolometer Infrared Image Sensor

    Microsoft Academic Search

    Sang Joon Hwang; Ho Hyun Shin; Man Young Sung

    2008-01-01

    An uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems (MEMS) process, so the value of the microbolometer resistor has a process variation. Also, the reference resistor, which is used to connect to the microbolometer, is fabricated by a standard CMOS process, and the difference between the values of the microbolometer

  1. Root Cause Analysis and Elimination of NPN EB Leakage Yield Loss in a SiGe BiCMOS Technology

    Microsoft Academic Search

    V. Raghavan; B. Ng; R. Singh; Tan Boon Lay

    2007-01-01

    New process solutions were developed to overcome yield loss due to process margin issue, coming from enhanced Emitter Base leakage in a mixed-signal BiCMOS technology. This paper presents failure analysis in a band gap reference circuit malfunction, in a SiGe BiCMOS Technology currently ramped to production. The associated yield loss was significant. In-circuit fault analysis identified leakage at the Emitter

  2. All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

    Microsoft Academic Search

    Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

    2004-01-01

    We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

  3. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 m process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  4. Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays

    PubMed Central

    Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

    2009-01-01

    We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 ?m 30 ?m. The devices exhibited sensitivity of 6.2 ?C/Rcm2 with corresponding dark current of ?2.7 nA/cm2, and a 80 ?m FWHM planar image response to a 50 ?m slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 ?m spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 ?m), fast readout speeds (8 fps for a 32003200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

  5. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    PubMed Central

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  6. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 A/m for n-type 149 A/m for p-type), low off-leakage current (28.1 pA/m for n-type and 79.6 pA/m for p-type), and excellent onoff ratio (1 107 for n-type and 2 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10?1310?11 m2/Hz for n-type and 10?1210?10 m2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  7. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  8. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  9. SSSCC94I SESSION 10I OPTICAL COMMUNICATIONI PAPER TP 10.5 TP 10.5: A 13.4-GHz CMOS Frequency Divider

    E-print Network

    Razavi, Behzad

    structures and layout rules. To reducebothfabricationcost and turnaround time, the CMOS process scales only driven by CKand CK. In orderto minimize the skew betweenCK and CK the non-inverted phase is delayed CMOS Frequency Divider Behzaa Razan, Kwmg F. Lee, Ran-HongYan ATBT Ball Laboratories, Holmdel

  10. CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects Azita Emami-Neyestanak, Samuel Palermo, Hae-Chang Lee and Mark Horowitz

    E-print Network

    Emami-Neyestanak, Azita

    This transceiver uses time division de/multiplexing of 5 to support a bit-time less than 2 F04 inverter delays24.4 CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects Azita Emami CMOS process. A S:1 multiplexing transmitter is used to drive VCSELs for optical transmission

  11. A CMOS 18 THz? 248 Mb\\/s transimpedance amplifier and 155 Mb\\/s LED-driver for low cost optical fiber links

    Microsoft Academic Search

    Mark Ingels; Geert Van der Plas; Jan Crols; Michel Steyaert

    1994-01-01

    The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 ?m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is

  12. The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era

    E-print Network

    Lebeck, Alvin R.

    1 Abstract The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies to the scientists developing the new technologies. DNA-based fabrication produces precise control within a small, it is applicable to any technology with similar characteristics (e.g., scaled CMOS with high process variability

  13. A monolithic optoelectronic receiver in standard 0.7-?m CMOS operating at 180 MHz and 176fJ light input energy

    Microsoft Academic Search

    K. Ayadi; M. Kuijk; P. Heremans; G. Bickel; G. Borghs; R. Vounckx

    1997-01-01

    A novel monolithic optoelectronic receiver\\/converter system is presented in standard 0.7-?m N-well CMOS technology. Differential light input incident on enlarged drains of two MOS transistors of a sense amplifier induces latching in either the digital HIGH state or the digital LOW state. The enlarged drains serve as photodiodes, circumventing hybridization techniques like flip-chip and\\/or solderbumping necessary when using III-V photodiodes.

  14. Bridging faults in BiCMOS circuits

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1993-01-01

    Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

  15. Effect of body biasing on single-event induced charge collection in deep N-well technology

    NASA Astrophysics Data System (ADS)

    Ding, Yi; Hu, Jian-Guo; Qin, Jun-Rui; Tan, Hong-Zhou

    2015-07-01

    As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits (ICs). At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design (TCAD) simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.

  16. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    E-print Network

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  17. High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology

    Microsoft Academic Search

    Min Park; Seonghearn Lee; Hyun Kyu Yu; Jin Gun Koo; Kee Soo Nam

    1997-01-01

    The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate

  18. Measurements on HV-CMOS active sensors after irradiation to HL-LHC fluences

    NASA Astrophysics Data System (ADS)

    Ristic, B.

    2015-04-01

    During the long shutdown (LS) 3 beginning 2022 the LHC will be upgraded for higher luminosities pushing the limits especially for the inner tracking detectors of the LHC experiments. In order to cope with the increased particle rate and radiation levels the ATLAS Inner Detector will be completely replaced by a purely silicon based one. Novel sensors based on HV-CMOS processes prove to be good candidates in terms of spatial resolution and radiation hardness. In this paper measurements conducted on prototypes built in the AMS H18 HV-CMOS process and irradiated to fluences of up to 21016 neq cm?2 are presented.

  19. A large-area CMOS monolithic active pixel sensor for extreme ultraviolet spectroscopy and imaging

    NASA Astrophysics Data System (ADS)

    Prydderch, Mark L.; Waltham, Nick R.; Morrissey, Quentin; French, Marcus; Turchetta, Renato; Pool, Peter

    2004-06-01

    We describe our programme to develop science-grade CMOS active pixel sensors for future space science missions, and in particular an extreme ultra-violet spectrograph for solar physics studies on the ESA Solar Orbiter. Our goal is the development of a large format 4k x 4k pixel CMOS sensor with useful sensitivity in the extreme ultra-violet (EUV) for solar physics spectroscopy and imaging. Our route to EUV sensitivity relies primarily in adapting the back-thinning and rear-illumination techniques first developed for CCD sensors; however we are also exploring the alternative approach of using a front-etch to expose the CMOS photodiodes. We have successfully back-thinned several 525 x 525 prototype CMOS sensors and proved that the devices survived the process both structurally and functionally. We have also been successful in removing the oxide from the front side of a small array of pixels, using focused ion beam etching. Preliminary results from these pixels show they are sensitive in the Ultra Violet. We have also designed a working large format 4k x 3k prototype on a 0.25 micron CMOS imager process.

  20. A high frame rate, 16 million pixels, radiation hard CMOS sensor

    NASA Astrophysics Data System (ADS)

    Guerrini, N.; Turchetta, R.; Van Hoften, G.; Henderson, R.; McMullan, G.; Faruqi, A. R.

    2011-03-01

    CMOS sensors provide the possibility of designing detectors for a large variety of applications with all the benefits and flexibility of the widely used CMOS process. In this paper we describe a novel CMOS sensor designed for transmission electron microscopy. The overall design consists of a large 61 63 mm2 silicon area containing 16 million pixels arranged in a 4K 4K array, with radiation hard geometry. All this is combined with a very fast readout, the possibility of region of interest (ROI) readout, pixel binning with consequent frame rate increase and a dynamic range close to 12 bits. The high frame rate has been achieved using 32 parallel analogue outputs each one operating at up to 20 MHz. Binning of pixels can be controlled externally and the flexibility of the design allows several possibilities, such as 2 2 or 4 4 binning. Other binning configurations where the number of rows and the number of columns are not equal, such as 2 1 or 2 4, are also possible. Having control of the CMOS design allowed us to optimise the pixel design, in particular with regard to its radiation hardness, and to make optimum choices in the design of other regions of the final sensor. An early prototype was also designed with a variety of geometries in order to optimise the readout structure and these are presented. The sensor was manufactured in a 0.35 ?m standard CMOS process.

  1. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

  2. A 150nA 13.4-ppm\\/C switched-capacitor CMOS sub-bandgap voltage reference

    Microsoft Academic Search

    Yan Wei; Li Wenhong; Liu Ran

    2011-01-01

    A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 0.35-mum 3.3-V\\/5-V dual gate mixed-signal CMOS process. The proposed circuit generates a precise sub-bandgap voltage of 1 V. The temperature coefficient of the output voltage is 13.4 ppm\\/C with the temperature varying from -20 to 80 C. The proposed circuit operates properly with the supply voltage down

  3. A 12mW wide dynamic range CMOS front-end for a portable GPS receiver

    Microsoft Academic Search

    Arvin R. Shahani; Derek K. Shaeffer; Thomas H. Lee

    1997-01-01

    This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-?m (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer

  4. A CMOS active pixel sensor based DNA micro-array with nano-metallic particles detection protocol

    Microsoft Academic Search

    Yijin Wang; Chen Xu; Jiong Li; I-Ming Hsing; Mansun Chan

    2005-01-01

    A DNA micro-array (DMA) for DNA detection is reported. The DMA combines a standard CMOS active pixel image sensor with a DNA detection protocol utilizing the binding of DNA targets and probes functionalized with gold nano-particles that can modify the opaqueness at the detection site. The DMA has been fabricated using a 0.5?m CMOS process together with on-chip timing control

  5. CMOS compatible integration of three-dimensional microfluidic systems based on low-temperature transfer of SU8 films

    Microsoft Academic Search

    Zheng-chun Peng; Zhong-geng Ling; Mark Tondra; Chang-geng Liu; Min Zhang; Kun Lian; Jost Goettert; Josef Hormes

    2006-01-01

    A novel approach to integrate densely packed CMOS devices with three-dimensional (3-D) microfluidic systems created at the wafer level using low temperature processes is introduced. The approach is based on low temperature (<50C) bonding and releasing of non-UV-exposed SU-8 films onto a SU-8 structured Si wafer bearing CMOS devices and multilayered lithography in the non-UV-exposed SU-8 films to form 3-D

  6. CMOS APS imager employing 3.3 V 12 bit 6.3 MS\\/s pipelined ADC

    Microsoft Academic Search

    Shy Hamami; Leonid Fleshel; Orly Yadid-pecht

    2004-01-01

    A novel 256x256 CMOS active pixel sensor (APS) system with 12 bit, 6.3 MSample\\/s (MS\\/s) CMOS pipelined analog to digital converter (ADC) integrated on chip is presented. The test chip has been implemented in 0.35m 2P4M process, operated by a 3.3V supply and is expected to dissipate 55mW. The total area of the prototype is 12 mm 2 , and

  7. Design and characterization of ionizing radiation-tolerant CMOS APS image sensors up to 30 Mrd (Si) total dose

    Microsoft Academic Search

    El-Sayed Eid; Tony Y. Chan; E. R. Fossurn; Richard H. Tsai; Robert Spagnuolo; John Deily; Wheaton B. Byers; Joseph C. Peden

    2001-01-01

    An ionizing radiation-tolerant CMOS active pixel sensor (APS) image sensor test chip was designed employing the physical design techniques of enclosed geometry and P-channel guard rings. The test chip was fabricated in a standard 0.35-?m CMOS process that has a gate-oxide thickness of 7.0 nm. It was irradiated by a ?-ray source up to a total ionizing radiation dose level

  8. 3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS\\/Nanomaterial Hybrid Digital Circuits

    Microsoft Academic Search

    Chen Dong; Deming Chen; Sansiri Haruehanroengra; Wei Wang

    2007-01-01

    In this paper, we introduce a novel reconfigurable architecture, named 3D field-programmable gate array (3D nFPGA), which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS nanohybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and

  9. A scalable neural chip with synaptic electronics using CMOS integrated memristors.

    PubMed

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-09-27

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. PMID:23999447

  10. A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring

    SciTech Connect

    Ahmed, A.; Walkey, D.J.; Tarr, N.G. [Carleton Univ., Ottawa, Ontario (Canada). Dept. of Electronics] [Carleton Univ., Ottawa, Ontario (Canada). Dept. of Electronics

    1997-06-01

    A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to a substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles. A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-{micro}m conventional CMOS process with a sense capacitor area of 110 {micro}m{sup 2}. Tests carried out under vacuum conditions using a calibrated {sup 241}Am alpha-particle source showed an output voltage swing of {ge}2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles.

  11. A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application

    SciTech Connect

    Eaton, W.P. [New Mexico, Albuquerque, NM (United States); Smith, J.H. [Sandia National Labs., Albuquerque, NM (United States)

    1994-12-31

    A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

  12. A complementary MOS process

    NASA Technical Reports Server (NTRS)

    Jhabvala, M. D.

    1977-01-01

    The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.

  13. Nanoscale CMOS: potential nonclassical technologies versus a hypothetical bulk-silicon technology

    NASA Astrophysics Data System (ADS)

    Kim, Seung-Hwan; Fossum, Jerry G.

    2005-04-01

    Using our process/physics-based compact models (UFDG and UFPDB) in Spice3, we project device characteristics and CMOS performances of nonclassical UTB (FD/SOI and DG) and classical, hypothetical bulk-Si technologies optimized at the Lg = 28 nm node. For the nonclassical MOSFETs (generally with metal gates for Vt control) with the same UTB thickness ( tSi), the DG devices are shown to be far superior for SCE control. Also, with regard to speed, the DG devices are generally superior to the FD/SG counterparts because of higher drive currents. However, for light loads and moderate supply voltages, a suboptimal FD/SG design (with the same tSi) for both LOP and HP CMOS applications is found to yield speeds comparable to the DG designs, even though its current drive is much lower and its SCEs are much more severe. This surprising result is explained by the much lower FD/SG intrinsic gate capacitance, CG( VGS). When the FD/SG CMOS design is optimized by aggressive scaling of the UTB thickness, its high- VDD speed diminishes (but is still comparable to that of DG CMOS) because of higher CG at intermediate gate voltages, while its low- VDD speed improves due to increased current. Compared to these nonclassical CMOS designs, the delay of the classical bulk-Si/SG CMOS is predicted to be much longer due mainly to its high CG in the weak/moderate inversion region and relatively low drive current. Finally, we show how FD/SOI CMOS speed is degraded as the BOX is thinned, thereby suggesting that such thinning is not a good design tradeoff.

  14. Fully-integrated oscillator in CMOS technology

    Microsoft Academic Search

    Gheorghe Pristavu; Anca-Gabriela Vasilica; Mihai Apostolescu; Gheorghe Brezeanu

    2010-01-01

    This paper describes the architecture of a fully integrated oscillator in CMOS technology, emphasizing the need for a simple design in order to achieve desired performances. The effect of parasitic transitions is investigated and eliminated.

  15. A CMOS-compatible compact display

    E-print Network

    Chen, Andrew R. (Andrew Raymond)

    2005-01-01

    Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

  16. Efficient design of CMOS TSC checkers

    Microsoft Academic Search

    SHAMANNA MANJUNATH; DAMU RADHAKRISHNAN

    1991-01-01

    The design of an efficient, robustly testable CMOS totally self-checking (TSC) checker for k-out-of-2k codes is treated. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers especially under the stuck-open fault model, owing to timing skews and arbitrary delays in the circuit. A new

  17. A 450 MHz CMOS RF power detector

    Microsoft Academic Search

    Stacy Ho

    2001-01-01

    An RF power detector based on a CMOS logarithmic\\/limiting amplifier achieves 50 dB dynamic range at 450 MHz. The logarithmic accuracy is +\\/- 1dB over the temperature range 0 to 85 degC. The chip is fabricated in 0.35 um double-poly triple-metal CMOS and consumes 10 mA with a 3 V supply

  18. CMOS Integrated Nanophotonics for Future Computing Systems

    NASA Astrophysics Data System (ADS)

    Vlasov, Yurii A.

    2011-10-01

    CMOS Integrated Nanophotonics allows ultra-dense monolithic single-chip integration of optical and electrical functions. This technology can enable future Exaflops supercomputers by connecting racks, modules, and chips together with ultra-low power massively parallel optical interconnects. I will describe the progress this field witnessed during last several years starting from explorations of fundamental optical phenomena at the nanoscale through development of advanced nanophotonics devices to demonstration of advanced optoelectronic systems integrated into a single CMOS die.

  19. CMOS imager technology shrinks and image performance

    Microsoft Academic Search

    H. Rhodes; G. Agranov; C. Hong; U. Boettiger; R. Mauritzson; J. Ladd; I. Karasev; J. McKee; E. Jenkins; W. Quinlin; I. Patrick; J. Li; X. Fan; R. Panicacci; S. Smith; C. Mouli; J. Bruce

    2004-01-01

    In this paper, we present a performance summary of CMOS imager pixels from 5.2 ?m to 4.2 ?m using 0.18 ?m imager design rules, then to 3.2 ?m using 0.15 ?m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based

  20. CMOS scaling into the nanometer regime

    Microsoft Academic Search

    Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

    1997-01-01

    Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

  1. Design and defect tolerance beyond CMOS

    Microsoft Academic Search

    Xiaobo Sharon Hu; Alexander Khitun; Konstantin K. Likharev; Michael T. Niemier; Mingqiang Bao; Kang L Wang

    2008-01-01

    ABSTRACT It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advance- ment of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement\\/replacement to CMOS must show,significant gains in at least one of the key met- rics (including speed, power and cost) for at least a

  2. Flexible packaging and integration of CMOS IC with elastomeric microfluidics

    NASA Astrophysics Data System (ADS)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-05-01

    We have demonstrated flexible packaging and integration of CMOS IC chips with PDMS microfluidics. Microfluidic channels are used to deliver both liquid samples and liquid metals to the CMOS die. The liquid metals are used to realize electrical interconnects to the CMOS chip. As a demonstration we integrated a CMOS magnetic sensor die and matched PDMS microfluidic channels in a flexible package. The packaged system is fully functional under 3cm bending radius. The flexible integration of CMOS ICs with microfluidics enables previously unavailable flexible CMOS electronic systems with fluidic manipulation capabilities, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing.

  3. Delay models for timing simulation of CMOS\\/BiCMOS\\/BiNMOS mixed digital circuits

    Microsoft Academic Search

    S. Embabi; R. Damodaran

    1993-01-01

    The authors report on delay models for three basic structures, CMOS, BiCMOS and BiNMOS inverters. The models account for input slope. They also account for the various second order effects such as short channel effects in MOS transistors, high current effects in BJTs, and the device parasitics of MOS and BJT transistors. The error between the delay models and SPICE

  4. CMOS APS photoresponse and crosstalk optimization analysis for scalable CMOS technologies

    Microsoft Academic Search

    I. Shcherback; O. Yadid-Pecht

    2004-01-01

    This work presents an improved semi-analytical model developed for photoresponse estimation of a photodiode based CMOS active pixel sensor (APS). We show its use for maximum pixel photosignal prediction and CMOS APS crosstalk (CTK) optimization. Our model reveals the photosignal and the CTK dependence on the pixel geometrical shape and the pixel arrangement within the array. It brings out clearly

  5. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  6. Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

    NASA Astrophysics Data System (ADS)

    Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 ?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

  7. A nano-metallic-particles-based CMOS image sensor for DNA detection

    NASA Astrophysics Data System (ADS)

    He, Jin; Su, Yan-Mei; Ma, Yu-Tao; Chen, Qin; Wang, Ruo-Nan; Ye, Yun; Ma, Yong; Liang, Hai-Lang

    2012-07-01

    In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano-metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 ?m CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

  8. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  9. Sub-threshold Circuit Design with Shrinking CMOS Devices

    E-print Network

    Calhoun, Benton H.

    Sub-threshold Circuit Design with Shrinking CMOS Devices Benton H. Calhoun, Sudhanshu Khanna, Randy, and these challenges increase as CMOS devices continue shrinking. This paper examines how sub-VT circuits scale

  10. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  11. IIIV/Ge channel MOS device technologies in nano CMOS era

    NASA Astrophysics Data System (ADS)

    Takagi, Shinichi; Zhang, Rui; Suh, Junkyo; Kim, Sang-Hyeon; Yokoyama, Masafumi; Nishi, Koichi; Takenaka, Mitsuru

    2015-06-01

    CMOS utilizing high-mobility IIIV/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing IIIV/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/IIIV films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in IIIV/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the IIIV MOS device technologies, we mainly address the gate stack technology, IIIV channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel IIIV-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using IIIV/Ge channels.

  12. Millimeter-wave Optoelectronic Mixers Based on CMOS-Compatible Si Photodetectors

    E-print Network

    Choi, Woo-Young

    the avalanche process in photodetectors at high reverse bias voltages, efficient optoelectronic mixing with lowMillimeter-wave Optoelectronic Mixers Based on CMOS-Compatible Si Photodetectors Hyo-Soon Kang-749, Korea Abstract -- We present millimeter-wave optoelectronic mixers based on Si photodetectors fabricated

  13. A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING

    E-print Network

    Maryland at College Park, University of

    fabricated a prototype circuit in a commercially- available 1.5 m, 2-metal, 2-poly CMOS process that occupies inputs and the outputs are from: an amplifier, a peak detector, a trough detector, and a level detector contribution. Following the amplifier, we have implemented a peak detector, a trough detector, and a level

  14. A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING

    E-print Network

    Horiuchi, Timothy K.

    fabricated a prototype circuit in a commercially- available 1.5m, 2-metal, 2-poly CMOS process that occupies inputs and the outputs are from: an amplifier, a peak detector, a trough detector, and a level detector contribution. Following the amplifier, we have implemented a peak detector, a trough detector, and a level

  15. DESIGN OF A MICROMACHINED CMOS COMPASS N. Dumas, L. Latorre and P. Nouet

    E-print Network

    Paris-Sud XI, Universit de

    . Hall Effect magnetic sensors pro- vide a standard CMOS solution but are not enough sensi- tive effects, and to be robust to process scatterings without the need of an external trimming. Mixed-mode simulations have been enabled using a behavioral description of the sensor, and validations of the complete

  16. DVD OEIC and 1 Gbit\\/s fiber receiver in CMOS technology

    Microsoft Academic Search

    A. Ghazi; T. Heide; H. Zimmermann; P. Seegebrecht

    2000-01-01

    Two new CMOS OEICs (optoelectronic integrated circuits) with integrated photodiodes for the application in DVD (digital versatile disc) systems and for optical data transmission are presented. Due to the integration of the photodiodes and the analog signal processing circuits on the same chip, smaller dimensions, better immunity against electromagnetic interference (EMI) and faster systems are achievable. Furthermore, a higher reliability

  17. SI-BASED UNRELEASED HYBRID MEMS-CMOS RESONATORS IN 32NM TECHNOLOGY

    E-print Network

    Williams, Brian C.

    it difficult to detect RF and mm-wave signals. The authors have previously demonstrated the Resonant Body, as shown in Fig. 2. On the drive side, acoustic waves are actuated in the Si bar by superimposing DC and RF of the CMOS process, and actively sensed with a Field Effect Transistor (FET) incorporated into the resonant

  18. Surface micromachined, digitally force-balanced accelerometer with integrated CMOS detection circuitry

    Microsoft Academic Search

    Weijie Yun; Roger T. Howe; Paul R. Gray

    1992-01-01

    The authors have described a surface micromachined accelerometer with digital electrostatic feedback using ?-? modulation technique, fabricated in a modular CMOS\\/microstructure process. Detection circuits have been tested successfully. The unity gain buffer with low input capacitance can also be used for other capacitive detection applications. The accelerometer has been characterized in the self-testing mode and has demonstrated the functionality of

  19. A 3-D vertical Hall magnetic field sensor in CMOS technology

    Microsoft Academic Search

    M. Paranjape; L. Ristic; I. Filanovsky

    1991-01-01

    A novel silicon sensor capable of detecting all three magnetic-field components is presented. The device is based on a vertical Hall structure and has been designed and fabricated in a standard 2 ?m CMOS process. Furthermore, a second test structure was implemented by introducing slight changes to the initial design in order to investigate the possibility of increasing device sensitivity.

  20. Monolithic expandable 6 bit 20 MHz CMOS\\/SOS A\\/D converter

    Microsoft Academic Search

    ANDREW G. F. DINGWALL

    1979-01-01

    Standard process CMOS\\/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A\\/D converter. Two chips may be interconnected in a series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates. Design factors and accuracy requirements are reviewed.

  1. Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS

    Microsoft Academic Search

    Rosa Rodrguez-montas; J. A. Segura; Vctor H. Champac; Joan Figueras; J. A. Rubio

    1991-01-01

    Logic testing has some well known limitations for circuits with failures causing intermediate voltage levels or, even, correct logic outputs with parametric deuiations from the fault free specificattons. For these failures current testing might be considered as a complementary technique to logic testing. In this work, these physical defects widely encountered in iodays CMOS processes, are modelled taking into account

  2. Test structures for characterization and comparative analysis of CMOS image sensors

    Microsoft Academic Search

    David X. d. Yang; Hao Min; Boyd A. Fowler; Abbas El Gamal; Mark Beiley; Kit Cham

    1996-01-01

    A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized

  3. An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems

    Microsoft Academic Search

    J. Christiansen

    1995-01-01

    This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process.

  4. Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology

    Microsoft Academic Search

    J. Bevk; S. Kuehne; H. Vaidya; W. Mansfield; G. Hobler; D. M. Boulin; K. Bolan; C. P. Chang; K. P. Cheung; R. Cirelli; J. I. Colonell; J. Frackoviak; M. Frei; C. Gruensfelder; D. C. Jacobson; R. W. Key; F. P. Klemens; W. Y. C. Lai; J. T.-C. Lee; C. T. Liu; R. Liu; M. Oh; H. L. Maynard; D. P. Monroe; O. Nalamasu; C. S. Pai; R. Santiesteban; P. J. Silverman; W. W. Tai; A. Timko; H. Vuong; G. P. Watson; M. J. Thoma; J. T. Clemens; S. J. Hillenius

    1998-01-01

    Summary form only given. We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process

  5. High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE

    Microsoft Academic Search

    S. Inaba; K. Okano; S. Matsuda; M. Fujiwara; A. Hokazono; K. Adachi; K. Ohuchi; H. Suto; H. Fukui; T. Shimizu; S. Mori; H. Oguma; A. Murakoshi; T. Itani; T. Iinuma; T. Kudo; H. Shibata; S. Taniguchi; T. Matsushita; S. Magoshi; Y. Watanabe; M. Takayanagi; A. Azuma; H. Oyamatsu; K. Suguro; Y. Katsumata; Y. Toyoshima; H. Ishiuchi

    2001-01-01

    35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to

  6. A 3.125 Gb/s 5-TAP CMOS Transversal Equalizer

    E-print Network

    Lopez-Rivera, Marcos L.

    2010-07-14

    , and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 m process and it is capable of compensating up to 20 dBs of attenuation at 1.5625 GHz for 15...

  7. PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis

    Microsoft Academic Search

    A. B. Bhattacharyya

    2002-01-01

    Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming numerical approach and relies more on empirical fitting of parameters for short channel devices, the predictive MOSFET model used is relatively simple and can be related to process and layout data with potential of

  8. Focal-plane-arrays and CMOS readout techniques of infrared imaging systems

    Microsoft Academic Search

    Chih-Cheng Hsieh; Chung-Yu Wu; Far-Wen Jih; Tai-Ping Sun

    1997-01-01

    A discussion of CMOS readout technologies for infrared (IR) imaging systems is presented. First, the description of various types of IR detector materials and structures is given. The advances of detector fabrication technology and microelectronics process technology have led to the development of large format array of IR imaging detectors. For such large IR FPAs which is the critical component

  9. A CMOS Image Sensor for DNA Microarrays Samir Parikh, Glenn Gulak, Paul Chow

    E-print Network

    Gulak, P. Glenn

    A CMOS Image Sensor for DNA Microarrays Samir Parikh, Glenn Gulak, Paul Chow University of Toronto-to-digital converter. I. INTRODUCTION DNA microarrays are commonly used to search for DNA sequences. A DNA microarray containing the target ssDNA is introduced to the DNA microarray leading to a pairing or unpairing process

  10. A 3.125 Gb/s 5-TAP CMOS Transversal Equalizer

    E-print Network

    Lopez-Rivera, Marcos L.

    2010-07-14

    , and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 m process and it is capable of compensating up to 20 dBs of attenuation at 1.5625 GHz for 15...

  11. High speed multistage CMOS clock buffers with pulse width control loop

    Microsoft Academic Search

    Fenghao Mu; Christer Svensson

    1999-01-01

    In high speed CMOS clock buffer design, the duty cycle of clock is liable to be influenced when the clock passes through a multistage buffer because the circuit is not strictly digital. Signal quality degradation is caused by temperature and process deviation. In this paper, we address a pulse width control loop (PWCL), to get a required pulse width. To

  12. A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems

    E-print Network

    Barranco, Bernabe Linares

    in the seventies by Chua based on circuit theoretical reasonings. On the other hand, neuromorphic engineering and analyzing potential circuit architectures that would combine a standard CMOS substrate with a memristive to implement real-time brain-like processing learning systems with about 108 neurons and 1012 synapses on one

  13. CMOS-APS for HEP applications: design and test of innovative architectures

    Microsoft Academic Search

    Alessandro Marras; Daniele Passeri; Pisana Placidi; Guido Matrella; Marco Petasecca; Leonello Servoli; Gian Mario Bilei; Paolo Ciampolini

    2005-01-01

    A set of innovative active pixel architectures has been conceived and implemented in standard CMOS technology. Active circuits are introduced into the pixel, to increase S\\/N ratio and to perform basic signal processing. Testing of such devices, however, becomes critical, due to the circuit relative complexity and to the need of accurately evaluating timing and position of the impinging radiation.

  14. High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

    Microsoft Academic Search

    Satoshi Inaba; Kimitoshi Okano; Satoshi Matsuda; Makoto Fujiwara; Akira Hokazono; Kanna Adachi; Kazuya Ohuchi; Hiroyuki Suto; Hironobu Fukui; Takashi Shimizu; Shinji Mori; Hideki Oguma; Atsushi Murakoshi; Takaharu Itani; Toshihiko Iinuma; Tomoyasu Kudo; H. Shibata; S. Taniguchi; M. Takayanagi; A. Azuma; H. Oyamatsu; K. Suguro; Y. Katsumata; Y. Toyoshima; H. Ishiuchi

    2002-01-01

    The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current Ig and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to

  15. A low power 20GHz RF CMOS based phase-locked loop

    Microsoft Academic Search

    Yiming Zhai; Bo Li; Bo Yang; Neil Goldsman

    2009-01-01

    The fast growing wireless communication systems have brought on a constant demand for low cost, low power and highly-integrated portable devices. In response to the evolution, the research and development of RF integrated circuits using low cost CMOS processes has been increased dramatically. A phase-locked loop (PLL) is a negative feedback control system which generates a signal with fixed phase

  16. Schottky Source\\/Drain CMOS Device Optimization with Dopant-Segregated NiPt Silicide

    Microsoft Academic Search

    Y. T. Huang; P. W. Liu; W. T. Chiang; T. L. Tsai; C. H. Tsai; C. T. Tsai; G. H. Ma

    2008-01-01

    We have successfully demonstrated an optimized dopant- segregated Schottky (DSS) source\\/drain CMOS technology featuring 35 nm physical gate length and 1.2 nm gate oxide. Several important device characteristics, including sidewall gate junction leakage suppression, short channel effect (SCE) control, along with drive current performance, are all investigated in this work. Furthermore, we notice that halo implant process is indispensable for

  17. Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

    Microsoft Academic Search

    K. Ohuchi; C. Lavoie; C. Murray; C. D'Emic; J. O. Chu; Bin Yang; P. Besser; L. Gignac; J. Bruley; G. U. Singco; F. Pagette; A. W. Topol; M. J. Rooks; J. J. Bucchignano; V. Narayanan; M. Khare; M. Takayanagi; K. Ishimaru; Dae-Gyu Park; G. Shahidi; P. Solomon

    2007-01-01

    This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10-8 Omega-cm2 for both n+ and p+ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.

  18. 0.1 ?m CMOS devices using low-impurity-channel transistors (LICT)

    Microsoft Academic Search

    M. Aoki; T. Ishii; T. Yoshimura; Y. Kiyota; S. Iijima; T. Yamanaka; T. Kure; K. Ohyu; T. Nishida; S. Okazaki; K. Seki; K. Shimohigashi

    1990-01-01

    Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 ?m CMOS devices. Attention is given to device fabrication criteria, key process technologies used, and the features achieved using LICTs

  19. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  20. Energy Effective 3D Stacked Hybrid NEMFET-CMOS Caches

    E-print Network

    Kuzmanov, Georgi

    -HdpMC) that combines the appealing ultra-low leakage SCCF NEMFET inverter with the versatility of CMOS technology. WeEnergy Effective 3D Stacked Hybrid NEMFET-CMOS Caches Mihai Lefter, Marius Enachescu, George Razvan-stacked hybrid memories as alternative to traditional CMOS SRAMs in L1 and L2 cache implementations and analyse

  1. 1 V full swing bootstrapped CMOS inverter circuit

    Microsoft Academic Search

    Kobchai Dejhan; Paiboon Tooprakai; Somsak Mitatha; Fusak Cheevasuvit; C. Soonyeekan

    2002-01-01

    This paper proposes a low voltage and full swing bootstrapped CMOS inverter circuit, designed by using the output drive CMOS transistors same as the conventional CMOS inverter in both pull up and pull down section. In pull up section, the overdrive at gate of pull up section is used by bootstrapped scheme. The circuit has the high speed full swing

  2. CMOS logic gates Where circuit delays come from

    E-print Network

    Chamberlain, Roger

    times of a CMOS inverter. Which has the largest overall propagation delay, tPD, a NAND gate, or a NOR in complementary arrangements inverter NAND A B (AB)' B A NOR (A+B)' NAND3 Circuit Delays in CMOS Circuits1 CMOS logic gates Where circuit delays come from Implementation of latches and flip flops How

  3. LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY

    E-print Network

    Rincon-Mora, Gabriel A.

    LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock, and Gabriel A. Rincon School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta supply voltages in CMOS integrated circuits. As the channel lengths of CMOS technology decrease

  4. Study of CMOS APS Responsivity Enhancement: Ring-Shaped Photodiode

    E-print Network

    Study of CMOS APS Responsivity Enhancement: Ring-Shaped Photodiode Tatiana Danov, Igor Shcherback the possibilities of CMOS APS spectral response improvement are discussed. Thorough submicron scanning results sensitivity. Index Terms - APS (Active Pixel Sensor), CMOS image sensor, minority carriers, diffusion

  5. Clustered Pixels for CMOS Image Sensors Zhiqiong Yu

    E-print Network

    Hornsey, Richard

    The active pixel sensor (APS) is a pixel architecture commonly used in high quality CMOS image sensors. This thesis presents clustered pixels for CMOS APS. Clustered pixels with a unity gain amplifier (UGA..........................................................................1 1.1.2 Advantages of CMOS APS

  6. A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies

    Microsoft Academic Search

    Klaus von Arnim; Peter Seegebrecht; Roland Thewes; Christian Pacha

    2005-01-01

    A 32b parallel prefix adder demonstrates leakage-current-reduction capabilities of skewed CMOS logic. Sub-100nA leakage currents and single-cycle activation from standby mode is achieved using multi-tox logic gates in 90nm CMOS technology. The data path contains improved sense amplifier-based flip-flops and skewed CMOS logic adapted latches.

  7. Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.

    PubMed

    Shainline, Jeffrey M; Orcutt, Jason S; Wade, Mark T; Nammari, Kareem; Moss, Benjamin; Georgas, Michael; Sun, Chen; Ram, Rajeev J; Stojanovi?, Vladimir; Popovi?, Milo A

    2013-08-01

    We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects. PMID:23903103

  8. A New CMOS Read-out IC for Uncooled Microbolometer Infrared Image Sensor

    Microsoft Academic Search

    Sang Joon Hwang; Ho Hyun Shin; Man Young Sung

    2008-01-01

    An uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems (MEMS)\\u000a process, so the value of the microbolometer resistor has a process variation. Also, the reference resistor, which is used\\u000a to connect to the microbolometer, is fabricated by a standard CMOS process, and the difference between the values of the microbolometer

  9. Linear array of CMOS double pass metal micromirrors

    NASA Astrophysics Data System (ADS)

    Buehler, Johannes; Steiner, Franz-Peter; Baltes, Henry

    1996-09-01

    Low-cost linear arrays of deflectable micromirrors using a CMOS process to define both on-chip circuitry and the mirror structure are presented. The mirrors consist of the second CMOS metallization deposited in two successive passes in order to establish a thick metal layer for the stiff mirror plate as well as a thin one for the flexible hinges. The mirrors are released by sacrificial aluminum and oxide etching. Supercritical point drying is performed in order to avoid sticking of the mirrors to the substrate. The mirrors are electrostatically deflected by biasing the address electrodes implanted into the substrate underneath the mirror plate. Full angular deflection of 4.8 degree(s) of a 30 X 40 micrometers 2 plate is achieved with a driving voltage of 12 V. On-chip circuitry adjacent to each mirror allows to address the pixels by 5 V data pulses. The reflectivity of the aluminum surface for wavelength between 400 and 700 nm was measured to be 83 - 89%. The mirror surface was further characterized using Auger spectroscopy showing that no optically relevant surface modification occur during post- processing. The surface rms roughness measured by atomic force microscopy is in the order of 25 nm.

  10. Scanning probe lithography approach for beyond CMOS devices

    NASA Astrophysics Data System (ADS)

    Durrani, Zahid; Jones, Mervyn; Kaestner, Marcus; Hofer, Manuel; Guliyev, Elshad; Ahmad, Ahmad; Ivanov, Tzvetan; Zoellner, Jens-Peter; Rangelow, Ivo W.

    2013-03-01

    As present CMOS devices approach technological and physical limits at the sub-10 nm scale, a `beyond CMOS' information-processing technology is necessary for timescales beyond the semiconductor technology roadmap. This requires new approaches to logic and memory devices, and to associated lithographic processes. At the sub-5 nm scale, a technology platform based on a combination of high-resolution scanning probe lithography (SPL) and nano-imprint lithography (NIL) is regarded as a promising candidate for both resolution and high throughput production. The practical application of quantum-effect devices, such as room temperature single-electron and quantum-dot devices, then becomes feasible. This paper considers lithographic and device approaches to such a `single nanometer manufacturing' technology. We consider the application of scanning probes, capable of imaging, probing of material properties and lithography at the single nanometer scale. Modified scanning probes are used to pattern molecular glass based resist materials, where the small particle size (<1 nm) and mono-disperse nature leads to more uniform and smaller lithographic pixel size. We also review the current status of single-electron and quantum dot devices capable of room-temperature operation, and discuss the requirements for these devices with regards to practical application.

  11. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  12. 7.2 A ldGb/s, 3 mW CMOS Receiver for Optical Communication Azita Emami-Neyestanak, Dean Liu, Gordon Keeler, Noah Helman and Mark Horowitz

    E-print Network

    Emami-Neyestanak, Azita

    with commercial electronic circuits [2]-[5]. However a dense array of optical detectors requires very low-power7.2 A ldGb/s, 3 mW CMOS Receiver for Optical Communication Azita Emami-Neyestanak, Dean Liu, Gordon and fabricated in a 0.25-pm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic

  13. CMOS optoelectronic database filter: implementation and analysis

    NASA Astrophysics Data System (ADS)

    Tang, Jianjing; Pattanayak, Arunansu; Beyette, Fred R., Jr.

    2003-12-01

    Optical storage devices are being used to meet the growing demand for high capacity archival data storage. A challenging task facing the designers for the next generation of archival storage system is to provide storage capacities several orders of magnitude larger than existing systems while maintaining current data access times. To meet this challenge, we have developed a smart optoelectronic database filter suitable for large capacity relational database systems that use page-oriented optical storage devices. The photonic VLSI chip monolithically integrates a smart-pixel array that incorporates page-oriented optical reading, data manipulation logic, data buffering and filter control circuitry for interfacing the filter chip with an electronic host computer. By selectively passing only the data requested by the query operation, the database filter is able to accomplish the reduction in data rate without loss of valid data or significant delay in data access. The design, testing and performance evaluation of a 32x32-bit database filter fabricated in a 0.35-micron CMOS process is reported. In addition to demonstrating the first fully functioning database filter chip, we present a program that has been developed to simulate the filtering algorithm implemented by the hardware. Queuing theory has been used to perform the system level analysis of the database filter. It is shown that even with the limitation of finite queue capacity, a database filter chip could be controlled to work at near optimal performance where database search time is limited by the data transfer rate going into the host computer. The simulation program has been used to verify the validity of the queuing analysis.

  14. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 C to 80 C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 m CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 C to 80 C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

  15. CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr

    E-print Network

    Choi, Woo-Young

    #12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

  16. ESD protection for wideband RF CMOS LNAs

    Microsoft Academic Search

    D. Linten; S. Thijs; G. Groeseneken

    2010-01-01

    Providing ESD protection for wideband RF CMOS LNAs is a challenging task: it requires both ESD and RF design skills in order to achieve high ESD robustness, while maintaining the overall RF performance. In this paper, an overview of the different wideband RF ESD protection strategies used in the literature is presented.

  17. Status and potential for CMOS terminal PAs

    Microsoft Academic Search

    Domine Leenaerts; Giuseppe Grillo

    2004-01-01

    In this overview, the status and potential for CMOS terminal RF power amplifiers (PAs) are discussed. The paper focuses on two application areas for RF PAs, namely wireless LAN\\/PAN applications, with output power levels up to 24 dBm, and cellular applications with power levels beyond 30 dBm.

  18. CMOS design challenges to power wall

    Microsoft Academic Search

    T. Kuroda

    2001-01-01

    CMOS power dissipation has been increasing due to the increase in power density. The power dissipation increased fourfold every three years until the early 1990's, due to a constant voltage scaling. Recently, a constant field scaling has been applied to reduce power dissipation, where the power density is increased proportional to the 0.7th power of scaling factor, resulting in power

  19. Dew-point relative humidity CMOS microsensors

    Microsoft Academic Search

    S. Baglio; S. Castorina; V. Sacco; N. Savalli; C. Tringali

    2004-01-01

    In this work we present the development of relative humidity (RH) microsensors in standard CMOS technology and bulk micromachining. Miniaturization of RH sensors allows reducing size, response times, power consumption and costs. Our device makes use of dew-point temperature detection approach, to achieve simple operation and high reproducibility. It is based on a suspended plate, anchored to the substrate by

  20. Battery-powered digital CMOS design

    Microsoft Academic Search

    Massoud Pedram; Qing Wu

    2002-01-01

    In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a superlinear function of the average discharge current. Next we show that

  1. CMOS ring oscillators with enhanced frequency operation

    Microsoft Academic Search

    A. El mourabit; Guo-Neng Lu; Ming Zhang; P. Pittet; Y. Birjali; F. Lahjoumri

    2010-01-01

    This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the adding of a CR differentiators-based MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase

  2. CMOS current source based radiation sensors

    Microsoft Academic Search

    E. Garcia-Moreno; R. Picos; E. Isern; M. Roca; K. Suenaga

    2010-01-01

    This paper presents a comparison of two gamma radiation sensors intended to be embedded in CMOS integrated circuits. Both sensors are based on a current source, whose output depends upon the cumulated radiation dose, followed by a current-frequency converter. The two sensors differ in the sensing elements: one uses conventional transistors and the other a floating gate transistor. Results are

  3. Switch level optimization for CMOS circuits

    E-print Network

    Chugh, Pankaj Pravinkumar

    1997-01-01

    In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

  4. Power consumption estimation in CMOS VLSI chips

    Microsoft Academic Search

    Dake Liu; Christer Svensson

    1994-01-01

    Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom

  5. Noise in digital dynamic CMOS circuits

    Microsoft Academic Search

    Patrik Larsson; Christer Svensson

    1994-01-01

    Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits

  6. A comprehensive delay model for CMOS inverters

    Microsoft Academic Search

    Santanu Dutta; Shivaling S. Mahant Shetti; Stephen L. Lusky

    1995-01-01

    A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output

  7. Delay degradation effect in submicronic CMOS inverters

    Microsoft Academic Search

    J. Juan-Chico; M. J. Bellido; A. J. Acosta; A. Barriga; M. Valencia

    1997-01-01

    This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library

  8. Timing and power model for CMOS inverters

    Microsoft Academic Search

    Richard Geiler; Hans-Jrg Pfleiderer

    2003-01-01

    Nowadays, the delay, the output transition time and the short circuit power consumption of CMOS gates depend on the load capacitance and the input transition time. In currently used technology libraries, table models with 25 or more samples are used for calculating by interpolation each of these three variables. Previous work deriving analytical models are based on neglecting the short

  9. Accurate timing model for the CMOS inverter

    Microsoft Academic Search

    L. Bisdounis; S. Nikolaidis; O. Koufopavlou; C. Goutis

    1996-01-01

    This paper introduces an accurate, analytical timing model for the CMOS inverter. Analytical output waveform expressions for all the inverter operation regions and input waveform slopes are derived, which take into account the complete expression of the short-circuit current and the gate-to-drain coupling capacitance

  10. Analytical transient response of CMOS inverters

    Microsoft Academic Search

    A. I. Kayssi; K. A. Sakallah; T. M. Burks

    1992-01-01

    A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step input, a ramp input, and an exponential input. A one-dimensional function dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter macromodel

  11. Minimizing power consumption in digital CMOS circuits

    Microsoft Academic Search

    ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

    1995-01-01

    An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

  12. ELECTROSTATIC DISCHARGE (ESD) PROTECTION IN CMOS

    E-print Network

    Baker, R. Jacob

    ELECTROSTATIC DISCHARGE (ESD) PROTECTION IN CMOS A Thesis Presented in Partial Fulfillment ofthe for the degree ofMaster of Science with a major in Electrical Engineering and titled "ELECTROSTATIC DISCHARGE and evaluated. This thesis begins with a briefoverview of Electrostatic Discharge (ESD) and its reliability

  13. Analysis of temporal noise in CMOS APS

    Microsoft Academic Search

    Hui Tian; Boyd A. Fowler; Abbas El Gamal

    1999-01-01

    Temporal noise sets a fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is well studied and characterized. It is primarily due to the photodetector shot noise and the thermal and 1\\/f noise of the output charge to voltage amplifier. In a CMOS APS several addition sources contribute

  14. CMOS APS ASIC testing and evaluation

    Microsoft Academic Search

    S. Moussa; T. A. Elkhatib; H. Haddara; H. F. Ragaie

    2004-01-01

    An ASIC CMOS image Active Pixel Sensor (APS) with combined linear and logarithmic modes of operation is presented. The chip consists of a 64 x 64 pixel array, together with its digital control and timing circuits. Test structures including individual photodiodes and pixels are also integrated for characterization purpose. The chip features selectable linear and logarithmic modes of operation, digitally

  15. Optimal Layout of CMOS Functional Arrays

    Microsoft Academic Search

    Takao Uehara; William M. Van Cleemput

    1981-01-01

    Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implemention of a random logic function on an array of CMOS transistors. A graph-theoreti cal algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design

  16. CMOS ACTIVE PIXEL SENSOR NITIN N. VELUDANDI

    E-print Network

    Furth, Paul

    to regenerate the image incident on the sensor. A data acquisition system has been developed to test the sensorCMOS ACTIVE PIXEL SENSOR BY NITIN N. VELUDANDI Master's Technical Report Electrical Engineering New Sensor," a master technical report prepared by Nitin N Veludandi, in partial fulfillment

  17. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

  18. Reliability issue on pipeline defects in CMOS memory devices

    NASA Astrophysics Data System (ADS)

    Youn, So; Terrell, Kyle; Wu, Chau-Chin; Shy, Paul; Lien, Chuen-Der

    1996-09-01

    Pipeline defects have recently been reported in a leakage source of CMOS devices when die shrink. We report the observed physical defects which shorted source and drain under .6 u short channel CMOS devices by the Wright-etching of the defective devices. We also found pipeline defects filled with phosphorous doped n-type material by the cross- sectioning of the pipeline in the channel of NMOS transistor. We also observed that devices are failing during high temperature reliability test, which causes single bit failure. This indicates that there are many potential defective die to reach assembly process even though most of detectives are discarded at wafer sort. SEM analysis identifies that location of defective parts is decorated with a pair of protruding holes at the 90 degree corner of field island of faulty pass-gate of SRAM. These pipeline defects are caused mainly by the compressed stress from field oxide. Reliability and yield have been improved since the pipeline were minimized after relieving stress on pass- gate.

  19. High-Q CMOS-integrated photonic crystal microcavity devices.

    PubMed

    Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  20. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

  1. Further developments on a novel color sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-05-01

    The Transverse Field Detector (TFD) is a recently proposed Silicon pixel device designed to perform color imaging without the use of color filters. The color detection principle is based on the dependence of the Silicon absorption coefficient from the wavelength and relies on the generation of a suitable transverse electric field configuration, within the semiconductor active layer, to drive photocarriers generated at different depths towards different collecting electrodes. Each electrode has in this way a different spectral response with respect to the incoming wavelength. Pixels with three or four different spectral responses can be implemented within ~ 6 ?m of pixel dimension. Thanks to the compatibility with standard triple well CMOS processes, the TFD can be used in an Active Pixel Sensor exploiting a dedicated readout topology, based on a single transistor charge amplifier. The overall APS electronics includes five transistors (5T) and a feedback capacitance, with a resulting overall fill factor around 50%. In this work the three colors and four colors TFD pixel simulations and implementations in a 90 nm standard CMOS triple well technology are described. Details on the design of a TFD APS mini matrix are provided and preliminary experimental results on four colors pixels are presented.

  2. W-CMOS blanking device for projection multibeam lithography

    NASA Astrophysics Data System (ADS)

    Jurisch, Michael; Irmscher, Mathias; Letzkus, Florian; Eder-Kapl, Stefan; Klein, Christof; Loeschner, Hans; Piller, Walter; Platzgummer, Elmar

    2010-05-01

    As the designs of future mask nodes become more and more complex the corresponding pattern writing times will rise significantly when using single beam writing tools. Projection multi-beam lithography [1] is one promising technology to enhance the throughput compared to state of the art VSB pattern generators. One key component of the projection multi-beam tool is an Aperture Plate System (APS) to form and switch thousands of individual beamlets. In our present setup a highly parallel beam is divided into 43,008 individual beamlets by a Siaperture- plate. These micrometer sized beams pass through larger openings in a blanking-plate and are individually switched on and off by applying a voltage to blanking-electrodes which are placed around the blanking-plate openings. A charged particle 200x reduction optics demagnifies the beamlet array to the substrate. The switched off beams are filtered out in the projection optics so that only the beams which are unaffected by the blanking-plate are projected to the substrate with 200x reduction. The blanking-plate is basically a CMOS device for handling the writing data. In our work the blanking-electrodes are fabricated using CMOS compatible add on processes like SiO2-etching or metal deposition and structuring. A new approach is the implementation of buried tungsten electrodes for beam blanking.

  3. Monolithic transformers and their application in a differential CMOS RF low-noise amplifier

    Microsoft Academic Search

    Jianjun J. Zhou; David J. Allstot

    1998-01-01

    A 900 MHz low-noise amplifier (LNA) utilizing three monolithic transformers to implement on-chip tuning networks and requiring no external components has been integrated in 2.88 mm2 in a standard digital 0.6 ?m CMOS process. A bias current reuse technique is employed to reduce power dissipation, and process-, voltage-, and temperature-tracking biasing techniques are used. At 900 MHz, the LNA dissipates

  4. High-voltage devices for 0.5-?m standard CMOS technology

    Microsoft Academic Search

    Cedric Bassin; Hussein Ballan; Michel Declercq

    2000-01-01

    The feasibility of the smart voltage extension (SVX) technique featuring complementary high-voltage devices without any modifications of the process steps of an 0.5-?m standard CMOS technology is discussed here. This letter focuses on the optimization of the breakdown voltage of the HVNMOS as well as the possible implementation of the HVPMOS. Different high-voltage options with increasing process modification steps are

  5. Wafer-level hermetic packaged microaccelerometer with fully differential BiCMOS interface circuit

    Microsoft Academic Search

    Hyoungho Ko; Sangjun Park; Byoungdoo Choi; Ahra Lee; Dong-il Dan Cho

    2007-01-01

    This paper presents a microaccelerometer with wafer-level packaged MEMS sensing element with fully differential, continuous-time BiCMOS interface circuit. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the sacrificial bulk micromachining (SBM) process. To protect the silicon structure of the sensing element and to enhance the reliability, a wafer level hermetic packaging process is achieved, using

  6. An uncooled infrared focal plane array for low-cost applications fabricated with standard CMOS technology

    Microsoft Academic Search

    C. Calaza; N. Viarani; G. Pedretti; M. Gottardi; A. Simoni; V. Zanini; M. Zen

    2006-01-01

    This paper reports the design, fabrication and assessment of a low-cost uncooled infrared imager that has been conceived as a general purpose system to be used in a wide range of infrared applications. The imager has been fabricated using the AMS 0.8?m CYE CMOS process together with a compatible front-side bulk micromachining post-process provided by the CMP service of the

  7. High performance 3.3- and 5-V 0.5-?m CMOS technology for ASIC's

    Microsoft Academic Search

    I. C. Kizilyalli; M. J. Thoma; S. A. Lytle; R. Singh; S. C. Vitkavage; P. F. Bechtold; J. W. Kearney; M. M. Rambaud; M. S. Twiford; W. T. Cochran; L. R. Fenstermaker; R. Freyman; Weishi Sun; A. Duncan

    1995-01-01

    Process integration of two manufacturable high performance 0.5-?m CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability

  8. Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

    PubMed

    Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  9. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

    2013-08-01

    This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 ?m CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

  10. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 ?m 1 Poly 4 Metal CMOS process. The pixel size is 100 ?m100 ?m and the pixel array format is 2496 pixels, which provide a field-of-view (FOV) of 9.6 mm2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  11. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    PubMed Central

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 ?m two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/?Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  12. A Low-Voltage High-Speed CMOS Inverter-Based Digital Differential Transmitter with Impedance Matching Control and Mismatch Calibration

    Microsoft Academic Search

    Jun-Hyun Bae; Sang-Hune Park; Jae-Yoon Sim; Hong-June Park

    2009-01-01

    A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a 0.18 ?m CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge

  13. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 10, OCTOBER 2007 2187 CMOS Camera With In-Pixel Temporal Change

    E-print Network

    Cauwenberghs, Gert

    IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 10, OCTOBER 2007 2187 CMOS Camera With In--An array of 90 90 active pixel sensors (APS) with pixel-level embedded differencing and comparison in a 0.5 m 3M2P CMOS, process consumes 4.2 mW of power while operating at 30 fps. Change sensitivity is 2

  14. ISSCC 2003 / SESSION 12 / CMOS IMAGERS, SENSORS AND DISPLAYS / PAPER 12.3 /4 inch 8.3M Pixel Digital Output CMOS APS

    E-print Network

    Fossum, Eric R.

    Pixel Digital Output CMOS APS for UDTV Application I. Takayanagi, M. Shirakawa1 , K. Mitani1 , MISSCC 2003 / SESSION 12 / CMOS IMAGERS, SENSORS AND DISPLAYS / PAPER 12.3 12.3 A 11 /4 inch 8.3M system. A newly developed digital-output CMOS image sensor fabricated in 0.25m CMOS technology

  15. Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

    SciTech Connect

    Holland, S.

    1991-11-01

    A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 {mu}m design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 {mu}A. The input-referred noise of the cascode amplifier is 20 nV/{radical}Hz at 1 MHz.

  16. Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design Dhruva Ghai Saraju P. Mohanty Elias Kougianos

    E-print Network

    Mohanty, Saraju P.

    that may be ap- plied to nanoscale circuits to ensure better yield. A current- starved voltage controlled.5% of the target. 1 Introduction and Motivation As CMOS technology scales to the nanometer region, process. This is a novel methodology for physical design of nanoscale CMOS (nano-CMOS) RF components to meet the required

  17. An RF (R) MS Power Detector in Standard CMOS

    Microsoft Academic Search

    F. H. J. van der Aa

    2006-01-01

    This Master thesis describes the research towards the integration of RF power\\u000adetectors for 3G cellular phones and base stations in CMOS technology1. It\\u000ais a feasibility study with the emphasis on the identification of fundamen-\\u000atal limitations of CMOS (particularly CMOS9) and of a number of squaring\\u000acircuits for this specific application, rather than to meet the target specifica-

  18. Retinomorphic system design in three dimensional SOI-CMOS

    Microsoft Academic Search

    Miriam Adlerstein Marwick; Andreas G. Andreou

    2006-01-01

    Three dimensional (3D) silicon on insulator (SOI)-CMOS technology offers opportunities for integration of truly complex neuromorphic systems that do not suffer from the limitations that hinder neuron-like local connectivity in 2D CMOS technologies. In this paper, we outline the rationale for morphing neural structures into 3D SOI-CMOS systems. We discuss design challenges for mixed signal neuromorphic circuits in single tier

  19. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    Microsoft Academic Search

    Kwang Hyun Kim; Soongpyung Kim; Dong-Won Kang; Dong-Kie Kim

    2006-01-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on

  20. A New Photon Counting Detector: Intensified CMOS-APS

    Microsoft Academic Search

    Giovanni Bonanno; Massimiliano Belluso; Antonio Cal; Alessandro Carbone; Rosario Cosentino; Angelo Modica; Salvo Scuderi; Cristina Timpanaro; Michela Uslenghi

    2004-01-01

    A new type of position sensor (CMOS-APS) used as readout system in MCP-based intensified photon counter is presented. Thanks to CMOS technology, the pixel addressing and the readout circuits as well as the analogue-to-digital converters are integrated into the chip. These unique characteristics make the CMOS-APS a very compact, low power consumption, photon counting system. The more classical Photon Counting

  1. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 ?m CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  2. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

  3. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  4. Lateral IMPATT diodes in standard CMOS technology

    Microsoft Academic Search

    T. Al-Attar; M. D. Mulligan; T. H. Lee

    2004-01-01

    We investigate the use of a lateral IMPATT diode built in 0.25?m CMOS technology as a high frequency power source. These diodes are monolithically integrated in coplanar waveguides and characterized by S-parameter measurements from 40 MHz to 110 GHz. These measurements show excellent agreement with predictions of theoretical models. To our knowledge, this is the first such structure built in

  5. Space efficient CMOS nonlinear transmission lines

    Microsoft Academic Search

    Keith G. Lyon; Fan Yu; Edwin C. Kan

    2009-01-01

    Nonlinear transmission lines (NLTLs) are used in diverse applications such as edge-sharpening, pulse generation, and frequency conversion, however, length of a useful NLTL can require significant MMIC or RFIC real estate. We present an analytical model for the complex propagation constant of lossy, distributed NLTLs and fabricate several NLTLs in 0.25 mum CMOS for verification. Space-saving layout techniques such as

  6. Optimization of CMOS MEMS microwave power sensors

    Microsoft Academic Search

    Veljko MilanoviC; Matt Hopcroft; Christian A. Zincke; Michael Gaitan; Mona E. Zaghloul

    1999-01-01

    AbstractMicromachined power sensors with operation up to 50GHz were recently achieved in CMOS technology [1]. To improve their sensitivity and signal-to-noise ratio, while maintaining microwave performance, several design parameters must be considered, such as the number and placement of thermocouples. This paper presents experimental and analytical thermal characterization of the sensors, which provides insight into,the ,proper ,adjustment ,of the ,layout

  7. Metrology Of Silicide Contacts For Future CMOS

    Microsoft Academic Search

    Stefan Zollner; Richard B. Gregory; M. L. Kottke; Victor Vartanian; Xiang-Dong Wang; David Theodore; P. L. Fejes; J. R. Conner; Mark Raymond; Xiaoyan Zhu; Dean Denning; Scott Bolton; Kyuhwan Chang; Ross Noble; Mohamad Jahanbani; Marc Rossow; Darren Goedeke; Stan Filipiak; Ricardo Garcia; Dharmesh Jawarani; Bill Taylor; Bich-Yen Nguyen; P. E. Crabtree; Aaron Thean

    2007-01-01

    Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low-resistance contacts between the back-end (W plugs and Cu interconnects) and front-end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active

  8. Thermoelectric AC power sensor by CMOS technology

    Microsoft Academic Search

    Dominik Jaeggi; Henry Baltes; David Moser

    1992-01-01

    The authors report the development of a thermoelectric AC power sensor (thermoconverter) realized by industrial CMOS IC technology in combination with postprocessing micromachining. The sensor is based on a polysilicon heating resistor and a polysilicon\\/aluminum thermopile integrated on an oxide microbridge. The thermopile sensitivity is 9.9 mV\\/mW and the burn-out power of the sensor is 50 mW. The time constant

  9. RF-CMOS oscillators with switched tuning

    Microsoft Academic Search

    A. Kral; F. Behbahani; A. A. Abidi

    1998-01-01

    Fully integrated CMOS oscillators are of great interest for use in single-chip wireless transceivers. In most oscillator circuits reported to date that operate in the 0.9 to 2 GHz frequency range, an integrated spiral inductor sets the frequency. It is generally believed that an LC oscillator, even when it uses a low-Q inductor, displays a lower phase noise than a

  10. LiB: a CMOS cell compiler

    Microsoft Academic Search

    Yung-ching Hsieh; Chi-yi Hwang; Youn-long Lin; Yu-chin Hsu

    1991-01-01

    An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981).

  11. Modeling and simulation of CMOS APS

    Microsoft Academic Search

    Beatriz Blanco-Filgueira; P. Lopez; Diego Cabello; J. Ernst; H. Neubauer; J. Hauer

    2009-01-01

    This work studies the importance of the peripheral collection in the overall photoresponse in deep sub-micron CMOS 3T active pixel sensors (APS), focusing on the contribution of the bottom surface of the depletion region. We analyze a semi-analytical expression, inspired by previous works, that models the photoresponse of a set of fabricated pixels with octagonal photodiodes that could be easily

  12. In-pixel autoexposure cmos aps

    Microsoft Academic Search

    Orly Yadid-Pecht; Alexander Belenky

    2003-01-01

    A CMOS active pixel sensor (APS) with in-pixel auto- exposure and a wide dynamic-range linear output is described. The chip features a unique architecture enabling a customized number of additional bits per pixel per readout, with minimal effect on the sensor spatial or temporal resolution. By utilizing multiple read- outs via real-time feedback, each pixel in the field of view

  13. Four-transistor static CMOS memory cells

    Microsoft Academic Search

    L. G. Walker; J. Manoliu; R. D. Rung

    1977-01-01

    A new approach toward size reduction of low-power static memory cells, based on ion-implanted leaky diodes in CMOS circuits, is described. The leaky diodes act as trickle chargers counteracting normal diode leakage currents and can be used in four different cells: a one-sided cell, a two-sided cell, and their complements. The reverse conductance of the implanted diodes must be greater

  14. Battery-powered digital CMOS design

    Microsoft Academic Search

    Massoud Pedram; Qing Wu

    1999-01-01

    In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and

  15. IDDQ testing in CMOS digital ASICs

    Microsoft Academic Search

    Roger Perry

    1992-01-01

    IDDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a

  16. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    PubMed Central

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  17. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  18. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    NASA Astrophysics Data System (ADS)

    Popovi?, Milo A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanovi?, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanovi? (UC Berkeley), Ram (MIT) and Popovi? (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  19. Binary deposition method using standard CMOS structural layers to fabricate optical gratings and microlenses

    NASA Astrophysics Data System (ADS)

    Yang, Lung Jieh; Liu, P. C.; Kang, Shung-Wen; Du, W. C.

    1999-05-01

    The binary lithography combined with precise control of RIE (Reactive Ion Etch) could fabricate the 8-level blazed gratings with the reflective efficiency above 80% in recent years. The pixel size of the 8-level grating is often designed to be 32 microns or even larger due to the manipulation error of the mask-aligner. By the excellent augmentation of the mask-stepper, which is popular in IC industry, the smaller pixel size or the higher-order levels of the gratings could be achieved ideally. Unfortunately, we hardly used the mask- stepper to meet the precision requirement for the excuse of process or material incompatibilities in standard IC process. Herein, we used a 'binary deposition method' as the counterpart of the current binary optics or binary etching method. By the standard CMOS process, all the designers have to do is to edit the layouts of multiple accumulated layers of poly-silicon and metal with a micrometer variation between each two planar layers. A classical demonstration for the 8- level gratings by the standard CMOS layers was depicted in this paper. Therefore, the sub-micron precision of the lithographic stepper is now practically available. Moreover, it even needs no post processing after the CMOS fabrication. A grating layout by the binary deposition method is under the foundry service provided by Chip Implementation Center (CIC), National Science Council, Taiwan, Republic of China. By the appropriate layout design, other reflective optical lenses have chances to be done as well as the blazed gratings similarly.

  20. A CMOS 128-APS linear array integrated with a LVOF for highsensitivity and high-resolution micro-spectrophotometry

    NASA Astrophysics Data System (ADS)

    Liu, Chi; Emadi, Arvin; Wu, Huaiwen; de Graaf, Ger; Wolffenbuttel, Reinoud F.

    2010-04-01

    A linear array of 128 Active Pixel Sensors has been developed in standard CMOS technology and a Linear Variable Optical Filter (LVOF) is added using CMOS-compatible post-process, resulting in a single chip highly-integrated highresolution microspectrometer. The optical requirements imposed by the LVOF result in photodetectors with small pitch and large length in the direction normal to the dispersed spectrum (7.2?m300?m). The specific characteristics of the readout are the small pitch, low optical signals (typically a photocurrent of 100fA~1pA) and a much longer integration time as compared to regular video (typically 100?s~63s). These characteristics enable a very different trade-off between SNR and integration time and IC-compatibility. The system discussed in this paper operates in the visible part of the spectrum. The prototype is fabricated in the AMIS 0.35?m A/D CMOS technology.

  1. Optical characterization of CMOS compatible micro optics fabricated by mask-based and mask-less hybrid lithography

    NASA Astrophysics Data System (ADS)

    Wang, Sunglin; Summitt, Chris; Johnson, Lee; Zaverton, Melissa; Milster, Tom; Takashima, Yuzuru

    2014-09-01

    We report a CMOS compatible fabrication and optical characterization of the micrometer scale optical coupler, a 45 mirror-based optical coupler for inter-layer optical coupling. A newly proposed mask-based and mask-less hybrid lithography process enables accurate surface profile of the micrometer sized 45 mirror by using a CMOS compatible buffer coat material. Surface profile inspected by an optical interferometry agrees well with SEM based inspection results. Experimental and theoretical results for routing and coupling of laser beam in 90 will be discussed.

  2. A 2229GHz UWB Pulse-Radar Receiver Front-End in 0.18- CMOS

    Microsoft Academic Search

    Vipul Jain; Sriramkumar Sundararaman; Payam Heydari

    2009-01-01

    The design of a CMOS 22-29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase\\/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-mum CMOS process, the RX front-end chip occupies a die area of 3 mm2. On-wafer measurements show a conversion gain of

  3. A 280GHz Schottky Diode Detector in 130-nm Digital CMOS

    Microsoft Academic Search

    Ruonan Han; Yaming Zhang; Dominique Coquillat; Hadley Videlier; Wojciech Knap; Elliott Brown; Kenneth K. O

    2011-01-01

    A2 2 array of 280-GHz Schottky-barrier diode detectors with an on-chip patch antenna (255 250 m )i s fab- ricated in a 130-nm logic CMOS process. The series resistance of diode is minimized using poly-gate separation (PGS), and exhibits a cut-off frequency of 2 THz. Each detector unit can detect an incident carrier with 100-Hz 2-MHz amplitude modulation. At 1-MHz

  4. A Low-Power Ultra-Wideband CMOS True RMS Power Detector

    Microsoft Academic Search

    Yijun Zhou; Michael Yan-Wah Chia

    2008-01-01

    This paper introduces a low-power ultra-wideband true root-mean-square power detector with a 0.13-mum CMOS process operating from 125 MHz to 8.5 GHz. The detector utilizes the MOS transistor's square-law characteristic in the strong inversion region to obtain the power information of the input RF signal, and its exponential characteristic in the weak inversion region to realize the linear-in-decibel output. Measured

  5. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    NASA Technical Reports Server (NTRS)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  6. A BiCMOS time-to-digital converter with 30 ps resolution

    Microsoft Academic Search

    Elvi Risnen-ruotsalainen; Timo Rahkonen; Juha Kostamovaara

    1999-01-01

    A time-to-digital converter (TDC) with 32 ps LSB and 2.5 ?s measurement range has been implemented in a 0.8 ?m BiCMOS process. The TDC is based on a main counter and two separate time digitizers for interpolation inside the clock period. The clock frequency of the counter is 100 MHz and the interpolators are based on dual-slope conversion. According to

  7. A 1.2 V micropower CMOS op amp with floating-gate input transistors

    Microsoft Academic Search

    Elvi Riiisanen-Ruotsalainen; Kimmo Lasanen; Juha Kostamovaara

    2000-01-01

    A micropower 1.2 V op amp has been integrated in a 0.35 ?m CMOS process. Floating-gate input transistors are used to increase the input common mode voltage range of the op amp. Measured dc gain of the op amp is 65 dB. With a 9 pF load unity gain bandwidth is 230 kHz and phase margin is 62. Input referred

  8. CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices

    Microsoft Academic Search

    Ilku Nam; Bonkee Kim; Kwyro Lee

    2005-01-01

    Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating\\/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in

  9. An inductorless 900 MHz RF low-noise amplifier in 0.9 ?m CMOS

    Microsoft Academic Search

    Young J. Shin; Klaas Bult

    1997-01-01

    A low cost 900-MHz RF Low-Noise Amplifier is implemented in a standard 0.9 ?m digital CMOS process. The design circumvents the use of both expensive external inductors as well as large on-chip inductors, by employing a gyrator circuit to emulate the inductors. This results in a high gain at RF of 20 dB, a tunable resonance frequency and a chip

  10. Low-power Capacitor Arrays for Charge Redistribution SAR AD Converter in 65nm CMOS

    Microsoft Academic Search

    Xingyuan Tong; Zhangming Zhu; Yintang Yang

    2009-01-01

    Through the research on charge redistribution SAR A\\/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and two-step architecture capacitor arrays is derived and analyzed. Based on SMIC 65 nm CMOS process, 10-bit SAR A\\/D converters of all these architectures are designed to validate these

  11. Resistive Loss and TransImpedance Characterization of Nonlinear Transmission Lines on CMOS SOI Substrate

    Microsoft Academic Search

    Jinsook Kim; Weiping Ni; Edwin C. Kan

    2005-01-01

    We report the characterization of nonlinear transmission lines (NLTL) implemented with the MIT Lincoln Lab 0.18mum FDSOI (fully-depleted silicon-on-insulator) CMOS process up to 35GHz directly from S-parameter measurements. NLTL interconnect can significantly reduce the effective resistance loss while maintaining comparable inductance, capacitance, and conductance to those of normal interconnect lines in a broadband of frequencies. Hence, the signal integrity in

  12. ESD protection design for 1- to 10GHz distributed amplifier in CMOS technology

    Microsoft Academic Search

    Ming-Dou Ker; Yuan-Wen Hsiao; Bing-Jye Kuo

    2005-01-01

    Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-?m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of

  13. A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

    Microsoft Academic Search

    Cristian Marcu; Debopriyo Chowdhury; Chintan Thakkar; Jung-Dong Park; Ling-Kai Kong; Maryam Tabesh; Yanjie Wang; Bagher Afshar; Abhinav Gupta; Amin Arbabian; Simone Gambini; Reza Zamani; Elad Alon; Ali M. Niknejad

    2009-01-01

    This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and

  14. A fully differential BiCMOS OTA for a 10.7MHz bandpass filter

    E-print Network

    Ali, Muhammad Imtiaz

    1993-01-01

    p-well CMOS process, In the circuit presented, the accuracy of the filter response is limited by the low dc gain of the trsnsconductors used. For higher se- lectivity filtering applications some kind of automatic loss compensation (Q... the operating fre- quency makes the frequency response "predistortion" techniques impractical because increasing clock frequencies brings in numerous high frequency effects concurrently [27]. Although SC filters are generally the best monolithic filter...

  15. Synthetic quasi-TEM transmission lines with dummy fills for CMOS miniaturized microwave integrated circuit

    Microsoft Academic Search

    Chao-Wei Wang; Hsien-Shun Wu; Ching-Kuang C. Tzuang

    2011-01-01

    This paper reports an on-chip synthetic transmission line (TL) with dummy fills in the standard CMOS 0.13 m 1P8M process. The synthetic TL so-called the complementary conducting strip transmission line (CCS TL) consists of a single trace and a mesh ground plane. The dummy metals are beneath the signal trace. The measured results show the CCS TL with the dummy

  16. A miniature switching phase shifter in 0.18-m CMOS

    Microsoft Academic Search

    Wei-Je Tseng; Chin-Shen Lin; Zuo-Min Tsai; Huei Wang

    2009-01-01

    A miniature 3-bit switching phase shifter using standard 0.18-?m CMOS process is presented in this paper. By using thin-film meander-line to shrink the size of inductor, the chip area can be reduced to 0.285 mm2. This circuit demonstrates an RMS phase error of smaller than 5.3 and an RMS amplitude error of smaller than 1.3 dB from 21-29 GHz. The

  17. Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

    Microsoft Academic Search

    Nader Akil; Michiel van Duuren; Michiel Slotboom; Wilko Baks; Pierre Goarin; Rob van Schaijk; Pablo G. Tello; Roger Cuppens

    2005-01-01

    The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel\\/source\\/drain

  18. Ultra high speed SiGe NPN for advanced BiCMOS technology

    Microsoft Academic Search

    M. Racanelli; K. Schuegraf; A. Kalburge; A. Kar-Roy; B. Shen; C. Hu; D. Chapek; D. Howard; D. Quon; F. Wang; G. U'ren; L. Lao; H. Tu; J. Zheng; J. Zhang; K. Bell; K. Yin; P. Joshi; S. Akhtar; T. Lee; W. Shi; P. Kempf

    2001-01-01

    A scalable SiGe NPN demonstrating Ft*BVceo product of 340 GHz-V with Ft of 170 GHz and BVceo of 2.0 V together with Fmax of 160 GHz is presented. Peak Ft is reached at a relatively low current density of 6 mA\\/?m2. The device is integrated in a 0.18 ?m BiCMOS process with dual-gate MOS transistors, high voltage NPN transistors, MIM

  19. An accurate design of fully integrated 2.4GHz CMOS cascode LNA

    Microsoft Academic Search

    Chih-Ho Tu; Ying-Zong Juang; Chin-Fong Chiu; Ruey-Lue Wang

    2005-01-01

    This paper presents a full integrated 2.4GHz inductively degenerated cascode low noise amplifier (LNA) realized in a standard TSMC 0.25-?m CMOS process. The source degenerated inductor has been design after the electromagnetic (EM) analysis using the calibrated substrate conditions. The measured performance of the proposed LNA shows the noise figure (NF) of 2.87 dB, the power gain of 13.29 dB,

  20. A 5 GHz CMOS Variable Gain Low Noise Amplifier for wireless LAN Applications

    Microsoft Academic Search

    Shaikh K. Alam; Joanne DeGroat; P. Roblin

    2006-01-01

    This paper describes a 5 GHz fully differential variable gain low noise amplifier (VGLNA) in a 0.18-mum CMOS process. The LNA provides a 50-Omega input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 12.34 dB within 1-dB compression point (iCP1db) of -12.0 dBm and a minimum gain of 6