Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Integrated Circuit Immunity

NASA Technical Reports Server (NTRS)

Sketoe, J. G.; Clark, Anthony

2000-01-01

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2010-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

PubMed

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2011-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

FG Width Scalability of the 3-D Vertical FG NAND Using the Sidewall Control Gate (SCG)

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.

Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface

DTIC Science & Technology

2016-03-17

Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface Austin H. Roach, Matthew J. Gadlage, James D. Ingalls, Aaron...reliability and trust of memories is very important, but because of incomplete documentation provided by commercial vendors and a lack of low-level...shown here that useful information about the trust and reliability of COTS NAND Flash components can be obtained by going beyond the standard product

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

PubMed Central

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-01-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design. PMID:28145438

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.

PubMed

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seung-Jun; Lee, Ki-Hong; Pyi, Seung Ho; Cho, Byung Jin

2016-05-01

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Hung, Chinglin; Takeuchi, Ken

2012-04-01

The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Effect with high density nano dot type storage layer structure on 20 nm planar NAND flash memory characteristics

NASA Astrophysics Data System (ADS)

Sasaki, Takeshi; Muraguchi, Masakazu; Seo, Moon-Sik; Park, Sung-kye; Endoh, Tetsuo

2014-01-01

The merits, concerns and design principle for the future nano dot (ND) type NAND flash memory cell are clarified, by considering the effect of storage layer structure on NAND flash memory characteristics. The characteristics of the ND cell for a NAND flash memory in comparison with the floating gate type (FG) is comprehensively studied through the read, erase, program operation, and the cell to cell interference with device simulation. Although the degradation of the read throughput (0.7% reduction of the cell current) and slower program time (26% smaller programmed threshold voltage shift) with high density (10 × 1012 cm-2) ND NAND are still concerned, the suppress of the cell to cell interference with high density (10 × 1012 cm-2) plays the most important part for scaling and multi-level cell (MLC) operation in comparison with the FG NAND. From these results, the design knowledge is shown to require the control of the number of nano dots rather than the higher nano dot density, from the viewpoint of increasing its memory capacity by MLC operation and suppressing threshold voltage variability caused by the number of dots in the storage layer. Moreover, in order to increase its memory capacity, it is shown the tunnel oxide thickness with ND should be designed thicker (>3 nm) than conventional designed ND cell for programming/erasing with direct tunneling mechanism.

76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-09-07

... Access Memory and Nand Flash Memory Devices and Products Containing Same; Notice of Institution of... importation, and the sale within the United States after importation of certain dynamic random access memory and NAND flash memory devices and products containing same by reason of infringement of certain claims...

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Possibility designing XNOR and NAND molecular logic gates by using single benzene ring

NASA Astrophysics Data System (ADS)

Abbas, Mohammed A.; Hanoon, Falah H.; Al-Badry, Lafy F.

2017-09-01

This study focused on examining electronic transport through single benzene ring and suggested how such ring can be employed to design XNOR and NAND molecular logic gates. The single benzene ring was threaded by a magnetic flux. The magnetic flux and applied gate voltages were considered as the key tuning parameter in the XNOR and NAND gates operation. All the calculations are achieved by using steady-state theoretical model, which is based on the time-dependent Hamiltonian model. The transmission probability and the electric current are calculated as functions of electron energy and bias voltage, respectively. The application of the anticipated results can be a base for the progress of molecular electronics.

Asymmetric programming: a highly reliable metadata allocation strategy for MLC NAND flash memory-based sensor systems.

PubMed

Huang, Min; Liu, Zhaoqing; Qiao, Liyan

2014-10-10

While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme.

Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems

PubMed Central

Huang, Min; Liu, Zhaoqing; Qiao, Liyan

2014-01-01

While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme. PMID:25310473

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Chen, D.; Friendlich, M.; Carts, M. A.; Seidleck, C. M.; LaBel, K. A.

2011-01-01

We have compared the data retention of irradiated commercial NAND flash memories with that of unirradiated controls. Under some circumstanc es, radiation exposure has a significant effect on the retention of f lash memories.

Design of synthetic biological logic circuits based on evolutionary algorithm.

PubMed

Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei

2013-08-01

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.

Buckled Thin-Film Transistors and Circuits on Soft Elastomers for Stretchable Electronics.

PubMed

Cantarella, Giuseppe; Vogt, Christian; Hopf, Raoul; Münzenrieder, Niko; Andrianakis, Panagiotis; Petti, Luisa; Daus, Alwin; Knobelspies, Stefan; Büthe, Lars; Tröster, Gerhard; Salvatore, Giovanni A

2017-08-30

Although recent progress in the field of flexible electronics has allowed the realization of biocompatible and conformable electronics, systematic approaches which combine high bendability (<3 mm bending radius), high stretchability (>3-4%), and low complexity in the fabrication process are still missing. Here, we show a technique to induce randomly oriented and customized wrinkles on the surface of a biocompatible elastomeric substrate, where Thin-Film Transistors (TFTs) and circuits (inverter and logic NAND gates) based on amorphous-IGZO are fabricated. By tuning the wavelength and the amplitude of the wrinkles, the devices are fully operational while bent to 13 μm bending radii as well as while stretched up to 5%, keeping unchanged electrical properties. Moreover, a flexible rectifier is also realized, showing no degradation in the performances while flat or wrapped on an artificial human wrist. As proof of concept, transparent TFTs are also fabricated, presenting comparable electrical performances to the nontransparent ones. The extension of the buckling approach from our TFTs to circuits demonstrates the scalability of the process, prospecting applications in wireless stretchable electronics to be worn or implanted.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

RET selection on state-of-the-art NAND flash

NASA Astrophysics Data System (ADS)

Lafferty, Neal V.; He, Yuan; Pei, Jinhua; Shao, Feng; Liu, QingWei; Shi, Xuelong

2015-03-01

We present results generated using a new gauge-based Resolution Enhancement Technique (RET) Selection flow during the technology set up phase of a 3x-node NAND Flash product. As a testcase, we consider a challenging critical level for this ash product. The RET solutions include inverse lithography technology (ILT) optimized masks with sub-resolution assist features (SRAF) and companion illumination sources developed using a new pixel based Source Mask Optimization (SMO) tool that uses measurement gauges as a primary input. The flow includes verification objectives which allow tolerancing of particular measurement gauges based on lithographic criteria. Relative importance for particular gauges may also be set, to aid in down-selection from several candidate sources. The end result is a sensitive, objective score of RET performance. Using these custom-defined importance metrics, decisions on the final RET style can be made in an objective way.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

PubMed

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

NASA Astrophysics Data System (ADS)

Kim, Do-Bin; Kwon, Dae Woong; Kim, Seunghyun; Lee, Sang-Ho; Park, Byung-Gook

2018-02-01

To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.

Improving Heat Transfer Performance of Printed Circuit Boards

NASA Technical Reports Server (NTRS)

Schatzel, Donald V.

2009-01-01

This paper will explore the ability of printed circuit boards laminated with a Carbon Core Laminate to transfer heat vs. standard printed circuit boards that use only thick layers of copper. The paper will compare the differences in heat transfer performance of printed circuit boards with and without CCL.

Performance of circuit switching in the Internet

NASA Astrophysics Data System (ADS)

Molinero-Fernández, Pablo; McKeown, Nick

2003-04-01

We study the performance of an Internet that uses circuit switching (CS) instead of, or in addition to, packet switching (PS). On the face of it, this would seem a pointless exercise; the Internet is packet switched, and it was deliberately built that way to enable the efficiencies afforded by statistical multiplexing and the robustness of fast rerouting around failures. But link utilization is low particularly at the core of the Internet, which makes statistical multiplexing less important than it once was. Moreover, circuit switches today are capable of rapid reconfiguration around failures. There is also renewed interest in CS because of the ease of building very-high-capacity optical circuit switches. Although several proposals have suggested ways in which CS may be introduced into the Internet, the research presented here is based on Transmission Control Protocol (TCP) switching, in which a new circuit is created for each application flow. Here we explore the performance of a network that uses TCP switching, with particular emphasis on the response time experienced by users. We use simple M/GI/1 and M/GI/N queues to model application flows in both packet-switched and circuit-switched networks, as well as ns-2 simulations. We conclude that because of high-bandwidth long-lived flows, it does not make sense to use CS in shared-access or local area networks. But our results suggest that in the core of the network, where high capacity is needed most, and where peak flow rate is limited by the access link, there is little or no difference in performance between CS and PS. Given that circuit switches can be built to be much faster than packet switches, this suggests that a circuit-switched core warrants further investigation.

Safety and performance enhancement circuit for primary explosive detonators

DOEpatents

Davis, Ronald W [Tracy, CA

2006-04-04

A safety and performance enhancement arrangement for primary explosive detonators. This arrangement involves a circuit containing an energy storage capacitor and preset self-trigger to protect the primary explosive detonator from electrostatic discharge (ESD). The circuit does not discharge into the detonator until a sufficient level of charge is acquired on the capacitor. The circuit parameters are designed so that normal ESD environments cannot charge the protection circuit to a level to achieve discharge. When functioned, the performance of the detonator is also improved because of the close coupling of the stored energy.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on

High performance protection circuit for power electronics applications

NASA Astrophysics Data System (ADS)

Tudoran, Cristian D.; Dǎdârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

2015-12-01

In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a "sensor" or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

High performance protection circuit for power electronics applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tudoran, Cristian D., E-mail: cristian.tudoran@itim-cj.ro; Dădârlat, Dorin N.; Toşa, Nicoleta

2015-12-23

In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as anmore » external, independent protection circuit.« less

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

NASA Astrophysics Data System (ADS)

Choe, Byeong-In; Park, Byung-Gook; Lee, Jong-Ho

2013-06-01

The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (Vth) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL Vth and body doping profile for SSL device. According to simulation work, a high Vth of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron-hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation.

Open circuit versus closed circuit enrichment of anodic biofilms in MFC: effect on performance and anodic communities.

PubMed

Larrosa-Guerrero, Amor; Scott, Keith; Katuri, Krishna P; Godinez, Carlos; Head, Ian M; Curtis, Thomas

2010-08-01

The influence of various carbon anodes; graphite, sponge, paper, cloth, felt, fiber, foam and reticulated vitreous carbon (RVC); on microbial fuel cell (MFC) performance is reported. The feed was brewery wastewater diluted in domestic wastewater. Biofilms were grown at open circuit or under an external load. Microbial diversity was analysed as a function of current and anode material. The bacterial community formed at open circuit was influenced by the anode material. However at closed circuit its role in determining the bacterial consortia formed was less important than the passage of current. The rate and extent of organic matter removal were similar for all materials: over 95% under closed circuit. The biofilm in MFCs working at open circuit and in the control reactors, increased COD removal by up to a factor of nine compared with that for baseline reactors. The average voltage output was 0.6 V at closed circuit, with an external resistor of 300 kOmega and 0.75 V at open circuit for all materials except RVC. The poor performance of this material might be related to the surface area available and concentration polarizations caused by the morphology of the material and the structure of the biofilm. Peak power varied from 1.3 mW m(-2) for RVC to 568 mW m(-2) for graphite with biofilm grown at closed circuit.

Measurement of luminescence decays: High performance at low cost

NASA Astrophysics Data System (ADS)

Sulkes, Mark; Sulkes, Zoe

2011-11-01

The availability of inexpensive ultra bright LEDs spanning the visible and near-ultraviolet combined with the availability of inexpensive electronics equipment makes it possible to construct a high performance luminescence lifetime apparatus (˜5 ns instrumental response or better) at low cost. A central need for time domain measurement systems is the ability to obtain short (˜1 ns or less) excitation light pulses from the LEDs. It is possible to build the necessary LED driver using a simple avalanche transistor circuit. We describe first a circuit to test for small signal NPN transistors that can avalanche. We then describe a final optimized avalanche mode circuit that we developed on a prototyping board by measuring driven light pulse duration as a function of the circuit on the board and passive component values. We demonstrate that the combination of the LED pulser and a 1P28 photomultiplier tube used in decay waveform acquisition has a time response that allows for detection and lifetime determination of luminescence decays down to ˜5 ns. The time response and data quality afforded with the same components in time-correlated single photon counting are even better. For time-correlated single photon counting an even simpler NAND-gate based LED driver circuit is also applicable. We also demonstrate the possible utility of a simple frequency domain method for luminescence lifetime determinations.

National Array of Neutron Detectors (NAND): A versatile tool for nuclear reaction studies

NASA Astrophysics Data System (ADS)

Golda, K. S.; Jhingan, A.; Sugathan, P.; Singh, Hardev; Singh, R. P.; Behera, B. R.; Mandal, S.; Kothari, A.; Gupta, Arti; Zacharias, J.; Archunan, M.; Barua, P.; Venkataramanan, S.; Bhowmik, R. K.; Govil, I. M.; Datta, S. K.; Chatterjee, M. B.

2014-11-01

The first phase of the National Array of Neutron Detectors (NAND) consisting of 26 neutron detectors has been commissioned at the Inter University Accelerator Centre (IUAC), New Delhi. The motivation behind setting up of such a detector system is the need for more accurate and efficient study of reaction mechanisms in the projectile energy range of 5-8 MeV/n using heavy ion beams from a 15 UD Pelletron and an upgraded LINAC booster facility at IUAC. The above detector array can be used for inclusive as well as exclusive measurements of reaction products of which at least one product is a neutron. While inclusive measurements can be made using only the neutron detectors along with the time of flight technique and a pulsed beam, exclusive measurements can be performed by detecting neutrons in coincidence with charged particles and/or fission fragments detected with ancillary detectors. The array can also be used for neutron tagged gamma-ray spectroscopy in (HI, xn) reactions by detecting gamma-rays in coincidence with the neutrons in a compact geometrical configuration. The various features and the performance of the different aspects of the array are described in the present paper.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond; Kim, Hak; Phan, Anthony; Seidleck, Christina; LaBel, Kenneth

2016-01-01

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.

77 FR 37862 - Open-Circuit Self-Contained Breathing Apparatus Remaining Service-Life Indicator Performance...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-25

...; NIOSH-258] Open-Circuit Self-Contained Breathing Apparatus Remaining Service-Life Indicator Performance... open-circuit self-contained breathing apparatus (OC- SCBA) remaining service-life indicators... ``Open-Circuit Self-Contained Breathing Apparatus Remaining Service-Life Indicator Performance...

Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

NASA Astrophysics Data System (ADS)

Tomita, Toshihiro; Miyaji, Kousuke

2015-04-01

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude ΔVth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, ΔVth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, ΔVth distribution slope λ cannot be determined by only considering RDF and single trap.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Statistical modeling of SRAM yield performance and circuit variability

NASA Astrophysics Data System (ADS)

Cheng, Qi; Chen, Yijian

2015-03-01

In this paper, we develop statistical models to investigate SRAM yield performance and circuit variability in the presence of self-aligned multiple patterning (SAMP) process. It is assumed that SRAM fins are fabricated by a positivetone (spacer is line) self-aligned sextuple patterning (SASP) process which accommodates two types of spacers, while gates are fabricated by a more pitch-relaxed self-aligned quadruple patterning (SAQP) process which only allows one type of spacer. A number of possible inverter and SRAM structures are identified and the related circuit multi-modality is studied using the developed failure-probability and yield models. It is shown that SRAM circuit yield is significantly impacted by the multi-modality of fins' spatial variations in a SRAM cell. The sensitivity of 6-transistor SRAM read/write failure probability to SASP process variations is calculated and the specific circuit type with the highest probability to fail in the reading/writing operation is identified. Our study suggests that the 6-transistor SRAM configuration may not be scalable to 7-nm half pitch and more robust SRAM circuit design needs to be researched.

Fault-tolerant NAND-flash memory module for next-generation scientific instruments

NASA Astrophysics Data System (ADS)

Lange, Tobias; Michel, Holger; Fiethe, Björn; Michalik, Harald; Walter, Dietmar

2015-10-01

Remote sensing instruments on today's space missions deliver a high amount of data which is typically evaluated on ground. Especially for deep space missions the telemetry downlink is very limited which creates the need for the scientific evaluation and thereby a reduction of data volume already on-board the spacecraft. A demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter. To enable on-board offline processing for data reduction, the instrument has to be equipped with a high capacity memory module. The module is based on non-volatile NAND-Flash technology, which requires more advanced operation than volatile DRAM. Unlike classical mass memories, the module is integrated into the instrument and allows readback of data for processing. The architecture and safe operation of such kind of memory module is described in the following paper.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Impact of urbanization coupled with drought situations on groundwater quality in shallow (basalt) and deeper (granite) aquifers with special reference to fluoride in Nanded-Waghala Municipal Corporation, Nanded District, Maharashtra (India).

PubMed

Pandith, Madhnure; Kaplay, R D; Potdar, S S; Sangnor, H; Rao, A D

2017-09-01

Rapid expansion in urbanization and industrialization coupled with recent drought conditions has triggered unplanned groundwater development leading to severe stress on groundwater resources in many urban cities of India, particularly cities like Nanded, Maharashtra. In the quest of tapping drinking water requirement, due to recent drought conditions, people from the city are piercing through entire thickness of shallow basalt aquifers to reach productive deeper granite aquifers. Earlier reports from Nanded and surrounding districts suggest that deeper granite aquifer is contaminated with fluoride (geogenic). The study aimed to find out variations in fluoride concentration in shallow basalt (10-167 m) and deeper granite aquifers (below 167 m) and to find out the relationship between fluoride and other ions. Study suggests that concentration of fluoride in shallow basalt aquifer is within maximum permissible limits of Bureau of Indian Standards and deeper granite aquifer contains as high as 4.9 mg/l of fluoride and all samples from granite aquifers are unfit for human consumption. The groundwater from basalt aquifer is mainly Ca-HCO 3- Cl type, and from granite aquifer, it is Ca-Na-Cl type. The correlation plot between F - vs. pH, Na + and HCO 3 - shows a positive correlation and an inverse relationship with Ca 2+ in both aquifers. As recommendations, it is suggested that granite aquifers should not be tapped for drinking purposes; however, in drought situations, water from this aquifer should be blended with treated surface water before supplying for drinking purposes. Efforts may be made to utilize 1.35 MCM of rainwater from available rooftop, which is sufficient to cater for the needs of ~40,800 people annually. Most effective defluoridation techniques like electrolytic de-fluoridation (EDF), ion exchange and reverse osmosis may be adopted along with integrated fluorosis mitigation measures.

Experimental Performance of a Frequency Measurement Circuit.

DTIC Science & Technology

1984-12-01

STANDARDS 1963-A NAVAL POSTGRADUATE SCHOOL Monterey, California N O In DTISEL ECTE. APR 26 1985 THESIS EXPERIMENTAL PERFORMANCE OF A FREQUENCY MEASUREMENT...CIRCUIT by CO George H. Eastwood December 198𔃾 Thesis Advisor: G. A. Myers * Approved for public release; distribution is unlimited. * 85 4 2 105...ACCESSION NO. 3. RECIPIENT’S CATALOG NUMBER 4. TITLE (and Subtitle) S. TYPE OF REPORT & PERIOD COVERED Experimental Performance of a Master’s Thesis

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

PubMed Central

2012-01-01

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Compact self-powered synchronous energy extraction circuit design with enhanced performance

NASA Astrophysics Data System (ADS)

Liu, Weiqun; Zhao, Caiyou; Badel, Adrien; Formosa, Fabien; Zhu, Qiao; Hu, Guangdi

2018-04-01

Synchronous switching circuit is viewed as an effective solution of enhancing the generator’s performance and providing better adaptability for load variations. A critical issue for these synchronous switching circuits is the self-powered realization. In contrast with other methods, the electronic breaker possesses the advantage of simplicity and reliability. However, beside the energy consumption of the electronic breakers, the parasitic capacitance decreases the available piezoelectric voltage. In this technical note, a new compact design of the self-powered switching circuit using electronic breaker is proposed. The envelope diodes are excluded and only a single envelope capacitor is used. The parasitic capacitance is reduced to half with boosted performance while the components are reduced with cost saved.

A new way of measuring wiggling pattern in SADP for 3D NAND technology

NASA Astrophysics Data System (ADS)

Mi, Jian; Chen, Ziqi; Tu, Li Ming; Mao, Xiaoming; Liu, Gong Cai; Kawada, Hiroki

2018-03-01

A new metrology method of quantitatively measuring wiggling patterns in a Self-Aligned Double Patterning (SADP) process for 2D NAND technology has been developed with a CD-SEM metrology program on images from a Review-SEM system. The metrology program provided accurate modeling of various wiggling patterns. The Review-SEM system provided a-few-micrometer-wide Field of View (FOV), which exceeds precision-guaranteed FOV of a conventional CD-SEM. The result has been effectively verified by visual inspection on vertically compressed images compared with Wiggling Index from this new method. A best-known method (BKM) system has been developed with connected HW and SW to automatically measure wiggling patterns.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond L.; Kim, Hak; Phan, Anthony; Seidleck, Christina; Label, Kenneth

2016-01-01

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

Assessment of maternal risk factors associated with low birth weight neonates at a tertiary hospital, Nanded, Maharashtra.

PubMed

Domple, Vijay Kishanrao; Doibale, Mohan K; Nair, Abhilasha; Rajput, Pinkesh S

2016-01-01

To assess the maternal risk factors associated with low birth weight (LBW) neonates at a tertiary hospital, Nanded, Maharashtra. This study was carried out in a tertiary care hospital in Nanded city of Maharashtra between January 2014 and July 2014 among 160 cases (LBW-birth weight ≤2499 g) and 160 controls (normal birth weight-birth weight >2499. Data collection was done by using predesigned questionnaire and also related health documents were checked and collected the expected information during the interview after obtaining informed consent from mothers. The data were analyzed by Epi Info 7 Version. The present study found the significant association among gestational age, sex of baby, type of delivery, maternal age, religion, education of mother and husband, occupation of mother and husband, type of family, maternal height, weight gain, hemoglobin level, planned/unplanned delivery, bad obstetric history, interval between pregnancies, previous history of LBW, underlying disease, tobacco chewing, timing of first antenatal care (ANC) visit, total number of ANC visit, and iron and folic acid (IFA) tablets consumption with LBW. No significant association was found among maternal age, residence, caste, consanguinity of marriage, socioeconomic status, gravida, birth order, multiple pregnancy, and smoking with LBW in our study. It was concluded that hemoglobin level, weight gain during pregnancy, gestational age, planned/unplanned delivery, bad obstetric history, and IFA tablets consumption during pregnancy were independent risk factors for LBW.

Moore's law realities for recording systems and memory storage components: HDD, tape, NAND, and optical

NASA Astrophysics Data System (ADS)

Fontana, Robert E.; Decad, Gary M.

2018-05-01

This paper describes trends in the storage technologies associated with Linear Tape Open (LTO) Tape cartridges, hard disk drives (HDD), and NAND Flash based storage devices including solid-state drives (SSD). This technology discussion centers on the relationship between cost/bit and bit density and, specifically on how the Moore's Law perception that areal density doubling and cost/bit halving every two years is no longer being achieved for storage based components. This observation and a Moore's Law Discussion are demonstrated with data from 9-year storage technology trends, assembled from publically available industry reporting sources.

Total Ionizing Dose Influence on the Single Event Effect Sensitivity in Samsung 8Gb NAND Flash Memories

NASA Astrophysics Data System (ADS)

Edmonds, Larry D.; Irom, Farokh; Allen, Gregory R.

2017-08-01

A recent model provides risk estimates for the deprogramming of initially programmed floating gates via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. This paper extends the model to include TID effects in the control circuitry by including one additional parameter. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

Genetic Circuit Performance under Conditions Relevant for Industrial Bioreactors

PubMed Central

Moser, Felix; Broers, Nicolette J.; Hartmans, Sybe; Tamsir, Alvin; Kerkman, Richard; Roubos, Johannes A.; Bovenberg, Roel; Voigt, Christopher A.

2014-01-01

Synthetic genetic programs promise to enable novel applications in industrial processes. For such applications, the genetic circuits that compose programs will require fidelity in varying and complex environments. In this work, we report the performance of two synthetic circuits in Escherichia coli under industrially relevant conditions, including the selection of media, strain, and growth rate. We test and compare two transcriptional circuits: an AND and a NOR gate. In E. coli DH10B, the AND gate is inactive in minimal media; activity can be rescued by supplementing the media and transferring the gate into the industrial strain E. coli DS68637 where normal function is observed in minimal media. In contrast, the NOR gate is robust to media composition and functions similarly in both strains. The AND gate is evaluated at three stages of early scale-up: 100 ml shake-flask experiments, a 1 ml MTP microreactor, and a 10 L bioreactor. A reference plasmid that constitutively produces a GFP reporter is used to make comparisons of circuit performance across conditions. The AND gate function is quantitatively different at each scale. The output deteriorates late in fermentation after the shift from exponential to constant feed rates, which induces rapid resource depletion and changes in growth rate. In addition, one of the output states of the AND gate failed in the bioreactor, effectively making it only responsive to a single input. Finally, cells carrying the AND gate show considerably less accumulation of biomass. Overall, these results highlight challenges and suggest modified strategies for developing and characterizing genetic circuits that function reliably during fermentation. PMID:23656232

Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability.

PubMed

Lu, Zeqin; Jhoja, Jaspreet; Klein, Jackson; Wang, Xu; Liu, Amy; Flueckiger, Jonas; Pond, James; Chrostowski, Lukas

2017-05-01

This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

Screen Color and Reading Performance on Closed-Circuit Television.

ERIC Educational Resources Information Center

Jacobs, R. J.

1990-01-01

To investigate whether screen color is an important variable in the prescription of closed circuit television (CCTV) systems, 16 adults with low vision were assessed on reading performance on white, green, and amber screens. When the screen luminance and contrast were equated for each CCTV, subjects' reading performance was unaffected by screen…

Advanced Si solid phase crystallization for vertical channel in vertical NANDs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Sangsoo; Son, Yong-Hoon; Semiconductor R and D Center, Samsung Electronics Co., Ltd., Hwasung 445-701

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers weremore » shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.« less

Sentinel 2 MMFU: The first European Mass Memory System Based on NAND-Flash Storage Technology

NASA Astrophysics Data System (ADS)

Staehle, M.; Cassel, M.; Lonsdorfer, U.; Gliem, F.; Walter, D.; Fichna, T.

2011-08-01

Sentinel-2 is the multispectral optical mission of the EU-ESA GMES (Global Monitoring for Environment and Security) program, currently under development by Astrium-GmbH in Friedrichshafen (Germany) for a launch in 2013. The mission features a 490 Mbit/s optical sensor operating at high duty cycles, requiring in turn a large 2.4 Tbit on-board storage capacity.The required storage capacity motivated the selection of the NAND-Flash technology which was already secured by a lengthy period (2004-2009) of detailed testing, analysis and qualification by Astrium GmbH, IDA and ESTEC. The mass memory system is currently being realized by Astrium GmbH.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

Logical NAND and NOR Operations Using Algorithmic Self-assembly of DNA Molecules

NASA Astrophysics Data System (ADS)

Wang, Yanfeng; Cui, Guangzhao; Zhang, Xuncai; Zheng, Yan

DNA self-assembly is the most advanced and versatile system that has been experimentally demonstrated for programmable construction of patterned systems on the molecular scale. It has been demonstrated that the simple binary arithmetic and logical operations can be computed by the process of self assembly of DNA tiles. Here we report a one-dimensional algorithmic self-assembly of DNA triple-crossover molecules that can be used to execute five steps of a logical NAND and NOR operations on a string of binary bits. To achieve this, abstract tiles were translated into DNA tiles based on triple-crossover motifs. Serving as input for the computation, long single stranded DNA molecules were used to nucleate growth of tiles into algorithmic crystals. Our method shows that engineered DNA self-assembly can be treated as a bottom-up design techniques, and can be capable of designing DNA computer organization and architecture.

Measuring circuit

DOEpatents

Sun, Shan C.; Chaprnka, Anthony G.

1977-01-11

An automatic gain control circuit functions to adjust the magnitude of an input signal supplied to a measuring circuit to a level within the dynamic range of the measuring circuit while a log-ratio circuit adjusts the magnitude of the output signal from the measuring circuit to the level of the input signal and optimizes the signal-to-noise ratio performance of the measuring circuit.

Photovoltaic Pixels for Neural Stimulation: Circuit Models and Performance.

PubMed

Boinagrov, David; Lei, Xin; Goetz, Georges; Kamins, Theodore I; Mathieson, Keith; Galambos, Ludwig; Harris, James S; Palanker, Daniel

2016-02-01

Photovoltaic conversion of pulsed light into pulsed electric current enables optically-activated neural stimulation with miniature wireless implants. In photovoltaic retinal prostheses, patterns of near-infrared light projected from video goggles onto subretinal arrays of photovoltaic pixels are converted into patterns of current to stimulate the inner retinal neurons. We describe a model of these devices and evaluate the performance of photovoltaic circuits, including the electrode-electrolyte interface. Characteristics of the electrodes measured in saline with various voltages, pulse durations, and polarities were modeled as voltage-dependent capacitances and Faradaic resistances. The resulting mathematical model of the circuit yielded dynamics of the electric current generated by the photovoltaic pixels illuminated by pulsed light. Voltages measured in saline with a pipette electrode above the pixel closely matched results of the model. Using the circuit model, our pixel design was optimized for maximum charge injection under various lighting conditions and for different stimulation thresholds. To speed discharge of the electrodes between the pulses of light, a shunt resistor was introduced and optimized for high frequency stimulation.

Analysis and performance of paralleling circuits for modular inverter-converter systems

NASA Technical Reports Server (NTRS)

Birchenough, A. G.; Gourash, F.

1972-01-01

As part of a modular inverter-converter development program, control techniques were developed to provide load sharing among paralleled inverters or converters. An analysis of the requirements of paralleling circuits and a discussion of the circuits developed and their performance are included in this report. The current sharing was within 5.6 percent of rated-load current for the ac modules and 7.4 percent for the dc modules for an initial output voltage unbalance of 5 volts.

Effect of Sensors on the Reliability and Control Performance of Power Circuits in the Web of Things (WoT)

PubMed Central

Bae, Sungwoo; Kim, Myungchin

2016-01-01

In order to realize a true WoT environment, a reliable power circuit is required to ensure interconnections among a range of WoT devices. This paper presents research on sensors and their effects on the reliability and response characteristics of power circuits in WoT devices. The presented research can be used in various power circuit applications, such as energy harvesting interfaces, photovoltaic systems, and battery management systems for the WoT devices. As power circuits rely on the feedback from voltage/current sensors, the system performance is likely to be affected by the sensor failure rates, sensor dynamic characteristics, and their interface circuits. This study investigated how the operational availability of the power circuits is affected by the sensor failure rates by performing a quantitative reliability analysis. In the analysis process, this paper also includes the effects of various reconstruction and estimation techniques used in power processing circuits (e.g., energy harvesting circuits and photovoltaic systems). This paper also reports how the transient control performance of power circuits is affected by sensor interface circuits. With the frequency domain stability analysis and circuit simulation, it was verified that the interface circuit dynamics may affect the transient response characteristics of power circuits. The verification results in this paper showed that the reliability and control performance of the power circuits can be affected by the sensor types, fault tolerant approaches against sensor failures, and the response characteristics of the sensor interfaces. The analysis results were also verified by experiments using a power circuit prototype. PMID:27608020

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Improving dynamic performances of PWM-driven servo-pneumatic systems via a novel pneumatic circuit.

PubMed

Taghizadeh, Mostafa; Ghaffari, Ali; Najafi, Farid

2009-10-01

In this paper, the effect of pneumatic circuit design on the input-output behavior of PWM-driven servo-pneumatic systems is investigated and their control performances are improved using linear controllers instead of complex and costly nonlinear ones. Generally, servo-pneumatic systems are well known for their nonlinear behavior. However, PWM-driven servo-pneumatic systems have the advantage of flexibility in the design of pneumatic circuits which affects the input-output linearity of the whole system. A simple pneumatic circuit with only one fast switching valve is designed which leads to a quasi-linear input-output relation. The quasi-linear behavior of the proposed circuit is verified both experimentally and by simulations. Closed loop position control experiments are then carried out using linear P- and PD-controllers. Since the output position is noisy and cannot be directly differentiated, a Kalman filter is designed to estimate the velocity of the cylinder. Highly improved tracking performances are obtained using these linear controllers, compared to previous works with nonlinear controllers.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

NASA Technical Reports Server (NTRS)

Irom, Farokh; Allen, Gregory R.

2012-01-01

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Uncertain behaviours of integrated circuits improve computational performance.

PubMed

Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

2015-11-20

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Genetic circuit design automation.

PubMed

Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A

2016-04-01

Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization. Copyright © 2016, American Association for the Advancement of Science.

Wafer-scalable high-performance CVD graphene devices and analog circuits

NASA Astrophysics Data System (ADS)

Tao, Li; Lee, Jongho; Li, Huifeng; Piner, Richard; Ruoff, Rodney; Akinwande, Deji

2013-03-01

Graphene field effect transistors (GFETs) will serve as an essential component for functional modules like amplifier and frequency doublers in analog circuits. The performance of these modules is directly related to the mobility of charge carriers in GFETs, which per this study has been greatly improved. Low-field electrostatic measurements show field mobility values up to 12k cm2/Vs at ambient conditions with our newly developed scalable CVD graphene. For both hole and electron transport, fabricated GFETs offer substantial amplification for small and large signals at quasi-static frequencies limited only by external capacitances at high-frequencies. GFETs biased at the peak transconductance point featured high small-signal gain with eventual output power compression similar to conventional transistor amplifiers. GFETs operating around the Dirac voltage afforded positive conversion gain for the first time, to our knowledge, in experimental graphene frequency doublers. This work suggests a realistic prospect for high performance linear and non-linear analog circuits based on the unique electron-hole symmetry and fast transport now accessible in wafer-scalable CVD graphene. *Support from NSF CAREER award (ECCS-1150034) and the W. M. Keck Foundation are appreicated.

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash

NASA Astrophysics Data System (ADS)

Zhang, Yu; Jin, Lei; Jiang, Dandan; Zou, Xingqi; Zhao, Zhiguo; Gao, Jing; Zeng, Ming; Zhou, Wenbin; Tang, Zhaoyun; Huo, Zongliang

2018-03-01

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.

Data on the natural ventilation performance of windcatcher with anti-short-circuit device (ASCD).

PubMed

Nejat, Payam; Calautit, John Kaiser; Majid, Muhd Zaimi Abd; Hughes, Ben Richard; Jomehzadeh, Fatemeh

2016-12-01

This article presents the datasets which were the results of the study explained in the research paper 'Anti-short-circuit device: a new solution for short-circuiting in windcatcher and improvement of natural ventilation performance' (P. Nejat, J.K. Calautit, M.Z. Abd. Majid, B.R. Hughes, F. Jomehzadeh, 2016) [1] which introduces a new technique to reduce or prevent short-circuiting in a two-sided windcatcher and also lowers the indoor CO2 concentration and improve the ventilation distribution. Here, we provide details of the numerical modeling set-up and data collection method to facilitate reproducibility. The datasets includes indoor airflow, ventilation rates and CO2 concentration data at several points in the flow field. The CAD geometry of the windcatcher models are also included.

Computer Aided Engineering of Semiconductor Integrated Circuits

DTIC Science & Technology

1976-04-01

from that of the ideal charge-contrpl model. Application of the test developed here to a practical MOS NAND gate demonstrates marked violations of...defining properties: [31] J. E. Meyer, RCA Review, 321, 42 (1971). [32] R.S.C. Cobbold , Theory and Applications of Field-Effect Transistors...decrease of thxs dxs- I ’ [!] H.K.J. Ihantola and J. L. Moll, Solid State Electronics, 7, 423 (1964). [2] R.S.C. Cobbold , Theory and

A Robust High-Performance GPS L1 Receiver with Single-stage Quadrature Redio-Frequency Circuit

NASA Astrophysics Data System (ADS)

Liu, Jianghua; Xu, Weilin; Wan, Qinq; Liu, Tianci

2018-03-01

A low power current reuse single-stage quadrature raido-frequency part (SQRF) is proposed for GPS L1 receiver in 180nm CMOS process. The proposed circuit consists of LNA, Mixer, QVCO, is called the QLMV cell. A two blocks stacked topology is adopted in this design. The parallel QVCO and mixer placed on the top forms the upper stacked block, and the LNA placed on the bottom forms the other stacked block. The two blocks share the current and achieve low power performance. To improve the stability, a float current source is proposed. The float current isolated the local oscillation signal and the input RF signal, which bring the whole circuit robust high-performance. The result shows conversion gain is 34 dB, noise figure is three dB, the phase noise is -110 dBc/Hz at 1MHz and IIP3 is -20 dBm. The proposed circuit dissipated 1.7mW with 1 V supply voltage.

High performance genetic algorithm for VLSI circuit partitioning

NASA Astrophysics Data System (ADS)

Dinu, Simona

2016-12-01

Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

NASA Astrophysics Data System (ADS)

Doi, Masafumi; Tokutomi, Tsukasa; Hachiya, Shogo; Kobayashi, Atsuro; Tanakamaru, Shuhei; Ning, Sheyang; Ogura Iwasaki, Tomoko; Takeuchi, Ken

2016-08-01

NAND flash memory’s reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive V Ref shift (AVS) and V TH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (V Ref) based on temperature, W/E cycles and retention-time. AVS stores the optimal V Ref’s in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between V TH states. DVO reduces BER by 80%.

Amplifier improvement circuit

NASA Technical Reports Server (NTRS)

Sturman, J.

1968-01-01

Stable input stage was designed for the use with a integrated circuit operational amplifier to provide improved performance as an instrumentation-type amplifier. The circuit provides high input impedance, stable gain, good common mode rejection, very low drift, and low output impedance.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

High-performance integrated pick-up circuit for SPAD arrays in time-correlated single photon counting

NASA Astrophysics Data System (ADS)

Acconcia, Giulia; Cominelli, Alessandro; Peronio, Pietro; Rech, Ivan; Ghioni, Massimo

2017-05-01

The analysis of optical signals by means of Single Photon Avalanche Diodes (SPADs) has been subject to a widespread interest in recent years. The development of multichannel high-performance Time Correlated Single Photon Counting (TCSPC) acquisition systems has undergone a fast trend. Concerning the detector performance, best in class results have been obtained resorting to custom technologies leading also to a strong dependence of the detector timing jitter from the threshold used to determine the onset of the photogenerated current flow. In this scenario, the avalanche current pick-up circuit plays a key role in determining the timing performance of the TCSPC acquisition system, especially with a large array of SPAD detectors because of electrical crosstalk issues. We developed a new current pick-up circuit based on a transimpedance amplifier structure able to extract the timing information from a 50-μm-diameter custom technology SPAD with a state-of-art timing jitter as low as 32ps and suitable to be exploited with SPAD arrays. In this paper we discuss the key features of this structure and we present a new version of the pick-up circuit that also provides quenching capabilities in order to minimize the number of interconnections required, an aspect that becomes more and more crucial in densely integrated systems.

Polymorphic Electronic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian

2004-01-01

Polymorphic electronics is a nascent technological discipline that involves, among other things, designing the same circuit to perform different analog and/or digital functions under different conditions. For example, a circuit can be designed to function as an OR gate or an AND gate, depending on the temperature (see figure). Polymorphic electronics can also be considered a subset of polytronics, which is a broader technological discipline in which optical and possibly other information- processing systems could also be designed to perform multiple functions. Polytronics is an outgrowth of evolvable hardware (EHW). The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles. To recapitulate: The essence of EHW is to design, construct, and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The evolution is guided by a search-and-optimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by computational simulation (in which case the evolution is said to be extrinsic), tested in real hardware (in which case the evolution is said to be intrinsic), or tested in random sequences of computational simulation and real hardware (in which case the evolution is said to be mixtrinsic).

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If

Joule-Thief Circuit Performance for Electricity Energy Saving of Emergency Lamps

NASA Astrophysics Data System (ADS)

Nuryanto Budisusila, Eka; Arifin, Bustanul

2017-04-01

The alternative energy such as battery as power source is required as energy source failures. The other need is outdoor lighting. The electrical power source is expected to be a power saving, optimum and has long life operating. The Joule-Thief circuit is one of solution method for energy saving by using raised electromagnetic force on cored coil when there is back-current. This circuit has a transistor operated as a switch to cut voltage and current flowing along the coils. The present of current causing magnetic induction and generates energy. Experimental prototype was designed by using battery 1.5V to activate Light Emitting Diode or LED as load. The LED was connected in parallel or serial circuit configuration. The result show that the joule-thief circuit able to supply LED circuits up to 40 LEDs.

Voltage-Boosting Driver For Switching Regulator

NASA Technical Reports Server (NTRS)

Trump, Ronald C.

1990-01-01

Driver circuit assures availability of 10- to 15-V gate-to-source voltage needed to turn on n-channel metal oxide/semiconductor field-effect transistor (MOSFET) acting as switch in switching voltage regulator. Includes voltage-boosting circuit efficiently providing gate voltage 10 to 15 V above supply voltage. Contains no exotic parts and does not require additional power supply. Consists of NAND gate and dual voltage booster operating in conjunction with pulse-width modulator part of regulator.

The test of VLSI circuits

NASA Astrophysics Data System (ADS)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Design and flight performance evaluation of the Mariners 6, 7, and 9 short-circuit current, open-circuit voltage transducers

NASA Technical Reports Server (NTRS)

Patterson, R. E.

1973-01-01

The purpose of the short-circuit voltage transducer is to provide engineering data to aid the evaluation of array performance during flight. The design, fabrication, calibration, and in-flight performance of the transducers onboard the Mariner 6, 7 and 9 spacecrafts are described. No significant differences were observed in the in-flight electrical performance of the three transducers. The transducers did experience significant losses due to coverslides or adhesive darkening, increased surface reflection, or spectral shifts within coverslide assembly. Mariner 6, 7 and 9 transducers showed non-cell current degradations of 3-1/2%, 3%, and 4%, respectively at Mars encounter and 6%, 3%, and 4-12%, respectively at end of mission. Mariner 9 solar Array Test 2 showed 3-12% current degradation while the transducer showed 4-12% degradation.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

Formal Verification of Digital Logic

DTIC Science & Technology

1991-12-01

INVERT circuit was based upon VHDL code provided in the Zycad Reference Manual [32:Ch 10,73]. The other circuits were based upon VHtDL code written...HALFADD.PL /* This file implements a simple half-adder that * /* is built from inverters and 2 input nand gates. * /* It is based upon a Zycad VHDL file...It is based upon a Zycad VHDL file written by * /* Capt Dave Banton, which is attached below the * /* Prolog code . *load..in(primitive). %h get nor2

Submicrosecond Power-Switching Test Circuit

NASA Technical Reports Server (NTRS)

Folk, Eric N.

2006-01-01

A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a

Implications of electronic short circuiting in plasma sprayed solid oxide fuel cells on electrode performance evaluation by electrochemical impedance spectroscopy

NASA Astrophysics Data System (ADS)

White, B. D.; Kesler, O.

Electronic short circuiting of the electrolyte in a solid oxide fuel cell (SOFC) arising from flaws in the plasma spray fabrication process has been found to have a significant effect on the perceived performance of the electrodes, as evaluated by electrochemical impedance spectroscopy (EIS). The presence of a short circuit has been found to lead to the underestimation of the electrode polarization resistance (R p) and hence an overestimation of electrode performance. The effect is particularly noticeable when electrolyte resistance is relatively high, for example during low to intermediate temperature operation, leading to an obvious deviation from the expected Arrhenius-type temperature dependence of R p. A method is developed for determining the real electrode performance from measurements of various cell properties, and strategies for eliminating the occurrence of short circuiting in plasma sprayed cells are identified.

Parallelizing quantum circuit synthesis

NASA Astrophysics Data System (ADS)

Di Matteo, Olivia; Mosca, Michele

2016-03-01

Quantum circuit synthesis is the process in which an arbitrary unitary operation is decomposed into a sequence of gates from a universal set, typically one which a quantum computer can implement both efficiently and fault-tolerantly. As physical implementations of quantum computers improve, the need is growing for tools that can effectively synthesize components of the circuits and algorithms they will run. Existing algorithms for exact, multi-qubit circuit synthesis scale exponentially in the number of qubits and circuit depth, leaving synthesis intractable for circuits on more than a handful of qubits. Even modest improvements in circuit synthesis procedures may lead to significant advances, pushing forward the boundaries of not only the size of solvable circuit synthesis problems, but also in what can be realized physically as a result of having more efficient circuits. We present a method for quantum circuit synthesis using deterministic walks. Also termed pseudorandom walks, these are walks in which once a starting point is chosen, its path is completely determined. We apply our method to construct a parallel framework for circuit synthesis, and implement one such version performing optimal T-count synthesis over the Clifford+T gate set. We use our software to present examples where parallelization offers a significant speedup on the runtime, as well as directly confirm that the 4-qubit 1-bit full adder has optimal T-count 7 and T-depth 3.

Identification of cognitive factors related to remote work performance using closed circuit TV displays

NASA Technical Reports Server (NTRS)

Clarke, M. M.; Garin, J.

1981-01-01

Operator perceptual cognitive styles as predictors of remote task performance were identified. Remote tasks which require the use of servo controlled master/slave manipulators and closed circuit television for teleoperator repair and maintenance of nuclear fuel recycling systems are examined. A useful procedure for identifying such perceptual styles is described.

A novel high performance ESD power clamp circuit with a small area

NASA Astrophysics Data System (ADS)

Zhaonian, Yang; Hongxia, Liu; Li, Li; Qingqing, Zhuo

2012-09-01

A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.

Acute Effects of Two Different Resistance Circuit Training Protocols on Performance and Perceived Exertion in Semiprofessional Basketball Players.

PubMed

Freitas, Tomás T; Calleja-González, Julio; Alarcón, Francisco; Alcaraz, Pedro E

2016-02-01

This study aimed to investigate the acute effects of two different resistance circuit training protocols on basketball players' physical and technical performance and rating of perceived exertion (RPE). In a repeated-measures, crossover experimental design, 9 semiprofessional basketball players performed a Power Circuit Training (PCT; 45% 1RM) and a High-Resistance Circuit Training (HRC; 6RM), on consecutive weeks. Vertical and horizontal jump performance, 3-points shooting accuracy, repeated-sprint ability (RSA), agility, and upper body power output were measured before and after training. The RPE was assessed 20 minutes after resistance training. One-way repeated-measures analysis of variance showed performance decrements in vertical jump height and peak power, horizontal jump distance, 3-points percentage, bench-press power output, RSA total and ideal time, and agility T-Test at total time following HRC, but not PCT (p ≤ 0.05). The RPE was higher in HRC compared with PCT. The results of this study indicated that HRC was perceived as being harder and produced higher fatigue levels, which in turn lowered acute performance. However, low-to-moderate intensity loads did not negatively affect performance. Thus, completing a PCT session may be the most appropriate option before a practice or game as it avoids acute-resistance-training-induced performance decrements. However, if the objective of the basketball session is to develop or perfect technical skills during fatiguing conditions, HRC may be the more suitable option.

Computer-aided linear-circuit design.

NASA Technical Reports Server (NTRS)

Penfield, P.

1971-01-01

Usually computer-aided design (CAD) refers to programs that analyze circuits conceived by the circuit designer. Among the services such programs should perform are direct network synthesis, analysis, optimization of network parameters, formatting, storage of miscellaneous data, and related calculations. The program should be embedded in a general-purpose conversational language such as BASIC, JOSS, or APL. Such a program is MARTHA, a general-purpose linear-circuit analyzer embedded in APL.

Reduced Error-Related Activation in Two Anterior Cingulate Circuits Is Related to Impaired Performance in Schizophrenia

ERIC Educational Resources Information Center

Polli, Frida E.; Barton, Jason J. S.; Thakkar, Katharine N.; Greve, Douglas N.; Goff, Donald C.; Rauch, Scott L.; Manoach, Dara S.

2008-01-01

To perform well on any challenging task, it is necessary to evaluate your performance so that you can learn from errors. Recent theoretical and experimental work suggests that the neural sequellae of error commission in a dorsal anterior cingulate circuit index a type of contingency- or reinforcement-based learning, while activation in a rostral…

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

NASA Technical Reports Server (NTRS)

1975-01-01

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

Principles of Genetic Circuit Design

PubMed Central

Brophy, Jennifer A.N.; Voigt, Christopher A.

2014-01-01

Cells are able to navigate environments, communicate, and build complex patterns by initiating gene expression in response to specific signals. Engineers need to harness this capability to program cells to perform tasks or build chemicals and materials that match the complexity seen in nature. This review describes new tools that aid the construction of genetic circuits. We show how circuit dynamics can be influenced by the choice of regulators and changed with expression “tuning knobs.” We collate the failure modes encountered when assembling circuits, quantify their impact on performance, and review mitigation efforts. Finally, we discuss the constraints that arise from operating within a living cell. Collectively, better tools, well-characterized parts, and a comprehensive understanding of how to compose circuits are leading to a breakthrough in the ability to program living cells for advanced applications, from living therapeutics to the atomic manufacturing of functional materials. PMID:24781324

High performance digital read out integrated circuit (DROIC) for infrared imaging

NASA Astrophysics Data System (ADS)

Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

2016-05-01

Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid

Therapeutic plasma exchange performed in tandem with hemodialysis without supplemental calcium in the apheresis circuit.

PubMed

Zhao, Yong; Ibrahim, Hiba; Bailey, Jeffrey A; Linden, Jeanne; Hickson, Elda; Haynes, Stefanie; Greene, Mindy; Vauthrin, Michelle; Weinstein, Robert

2017-06-01

Therapeutic plasma exchange (TPE) and hemopoietic progenitor cell (HPC) collection are apheresis procedures that can safely be performed in tandem with hemodialysis. Despite the return of citrate-anticoagulated blood to the patient during HPC collection, it is not necessary to administer supplemental calcium during these procedures because the ionized calcium concentration is restored as the returning blood passes through the dialyzer. It is not known whether this applies to TPE, in which a mixture of blood and pharmaceutical albumin, an avid binder of plasma ionized calcium, is returned to the patient through the dialyzer. We report on three dialysis-dependent patients who required TPE and underwent tandem treatments without supplemental calcium in the apheresis circuit. Overall, ionized calcium fell 4-12% (P = 0.0.024) and patients reported no symptoms of hypocalcemic toxicity. Tandem hemodialysis/TPE can be performed without supplemental calcium in the apheresis circuit. J. Clin. Apheresis 32:154-157, 2017. © 2016 Wiley Periodicals, Inc. © 2016 Wiley Periodicals, Inc.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Nuclear code case development of printed-circuit heat exchangers with thermal and mechanical performance testing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aakre, Shaun R.; Jentz, Ian W.; Anderson, Mark H.

The U.S. Department of Energy has agreed to fund a three-year integrated research project to close technical gaps involved with compact heat exchangers to be used in nuclear applications. This paper introduces the goals of the project, the research institutions, and industrial partners working in collaboration to develop a draft Boiler and Pressure Vessel Code Case for this technology. Heat exchanger testing, as well as non-destructive and destructive evaluation, will be performed by researchers across the country to understand the performance of compact heat exchangers. Testing will be performed using coolants and conditions proposed for Gen IV Reactor designs. Preliminarymore » observations of the mechanical failure mechanisms of the heat exchangers using destructive and non-destructive methods is presented. Unit-cell finite element models assembled to help predict the mechanical behavior of these high-temperature components are discussed as well. Performance testing methodology is laid out in this paper along with preliminary modeling results, an introduction to x-ray and neutron inspection techniques, and results from a recent pressurization test of a printed-circuit heat exchanger. The operational and quality assurance knowledge gained from these models and validation tests will be useful to developers of supercritical CO 2 systems, which commonly employ printed-circuit heat exchangers.« less

Accelerated test techniques for micro-circuits: Evaluation of high temperature (473 k - 573 K) accelerated life test techniques as effective microcircuit screening methods

NASA Technical Reports Server (NTRS)

Johnson, G. M.

1976-01-01

The application of high temperature accelerated test techniques was shown to be an effective method of microcircuit defect screening. Comprehensive microcircuit evaluations and a series of high temperature (473 K to 573 K) life tests demonstrated that a freak or early failure population of surface contaminated devices could be completely screened in thirty two hours of test at an ambient temperature of 523 K. Equivalent screening at 398 K, as prescribed by current Military and NASA specifications, would have required in excess of 1,500 hours of test. All testing was accomplished with a Texas Instruments' 54L10, low power triple-3 input NAND gate manufactured with a titanium- tungsten (Ti-W), Gold (Au) metallization system. A number of design and/or manufacturing anomalies were also noted with the Ti-W, Au metallization system. Further study of the exact nature and cause(s) of these anomalies is recommended prior to the use of microcircuits with Ti-W, Au metallization in long life/high reliability applications. Photomicrographs of tested circuits are included.

Automated Design of Quantum Circuits

NASA Technical Reports Server (NTRS)

Williams, Colin P.; Gray, Alexander G.

2000-01-01

In order to design a quantum circuit that performs a desired quantum computation, it is necessary to find a decomposition of the unitary matrix that represents that computation in terms of a sequence of quantum gate operations. To date, such designs have either been found by hand or by exhaustive enumeration of all possible circuit topologies. In this paper we propose an automated approach to quantum circuit design using search heuristics based on principles abstracted from evolutionary genetics, i.e. using a genetic programming algorithm adapted specially for this problem. We demonstrate the method on the task of discovering quantum circuit designs for quantum teleportation. We show that to find a given known circuit design (one which was hand-crafted by a human), the method considers roughly an order of magnitude fewer designs than naive enumeration. In addition, the method finds novel circuit designs superior to those previously known.

Logic circuits from zero forcing.

PubMed

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

Creating single-copy genetic circuits

PubMed Central

Lee, Jeong Wook; Gyorgy, Andras; Cameron, D. Ewen; Pyenson, Nora; Choi, Kyeong Rok; Way, Jeffrey C.; Silver, Pamela A.; Del Vecchio, Domitilla; Collins, James J.

2017-01-01

SUMMARY Synthetic biology is increasingly used to develop sophisticated living devices for basic and applied research. Many of these genetic devices are engineered using multi-copy plasmids, but as the field progresses from proof-of-principle demonstrations to practical applications, it is important to develop single-copy synthetic modules that minimize consumption of cellular resources and can be stably maintained as genomic integrants. Here we use empirical design, mathematical modeling and iterative construction and testing to build single-copy, bistable toggle switches with improved performance and reduced metabolic load that can be stably integrated into the host genome. Deterministic and stochastic models led us to focus on basal transcription to optimize circuit performance and helped to explain the resulting circuit robustness across a large range of component expression levels. The design parameters developed here provide important guidance for future efforts to convert functional multi-copy gene circuits into optimized single-copy circuits for practical, real-world use. PMID:27425413

A Simple Memristor Model for Circuit Simulations

NASA Astrophysics Data System (ADS)

Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team

This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.

Design and analysis of APD photoelectric detecting circuit

NASA Astrophysics Data System (ADS)

Fang, R.; Wang, C.

2015-11-01

In LADAR system, photoelectric detecting circuit is the key part in photoelectric conversion, which determines speed of respond, sensitivity and fidelity of the system. This paper presents the design of a matched APD Photoelectric detecting circuit. The circuit accomplishes low-noise readout and high-gain amplification of the weak photoelectric signal. The main performances, especially noise and transient response of the circuit are analyzed. In order to obtain large bandwidth, decompensated operational amplifiers are applied. Circuit simulations allow the architecture validation and the global performances to be predicted. The simulation results show that the gain of the detecting circuit is 630kΩ while the bandwidth is 100MHz, and 28dB dynamic range is achieved. Furthermore, the variation of the output pulse width is less than 0.9ns.

In Vitro Evaluation of an Alternative Neonatal Extracorporeal Life Support Circuit on Hemodynamic Performance and Bubble Trap.

PubMed

Spencer, Shannon B; Wang, Shigang; Woitas, Karl; Glass, Kristen; Kunselman, Allen R; Ündar, Akif

2017-01-01

The objective of this study was to evaluate an alternative neonatal extracorporeal life support (ECLS) circuit with a RotaFlow centrifugal pump and Better-Bladder (BB) for hemodynamic performance and gaseous microemboli (GME) capture in a simulated neonatal ECLS system. The circuit consisted of a Maquet RotaFlow centrifugal pump, a Quadrox-iD Pediatric diffusion membrane oxygenator, 8 Fr arterial cannula, and 10 Fr venous cannula. A "Y" connector was inserted into the venous line to allow for comparison between BB and no BB. The circuit and pseudopatient were primed with lactated Ringer's solution and packed human red blood cells (hematocrit 35%). All hemodynamic trials were conducted at flow rates ranging from 100 to 600 mL/min at 36°C. Real-time pressure and flow data were recorded using a data acquisition system. For GME testing, 0.5 cc of air was injected via syringe into the venous line. GME were detected and characterized with or without the BB using the Emboli Detection and Classification Quantifier (EDAC) System. Trials were conducted at flow rates ranging from 200 to 500 mL/min. The hemodynamic energy data showed that up to 75.2% of the total hemodynamic energy was lost from the circuit. The greatest pressure drops occurred across the arterial cannula and increased with increasing flow rate from 10.1 mm Hg at 100 mL/min to 114.3 mm Hg at 600 mL/min. The EDAC results showed that the BB trapped a significant amount of the GME in the circuit. When the bladder was removed, GME passed through the pump head and the oxygenator to the arterial line. This study showed that a RotaFlow centrifugal pump combined with a BB can help to significantly decrease the number of GME in a neonatal ECLS circuit. Even with this optimized alternative circuit, a large percentage of the total hemodynamic energy was lost. The arterial cannula was the main source of resistance in the circuit. © 2016 International Center for Artificial Organs and Transplantation and Wiley Periodicals

Triple effect absorption chiller utilizing two refrigeration circuits

DOEpatents

DeVault, Robert C.

1988-01-01

A triple effect absorption method and apparatus having a high coefficient of performance. Two single effect absorption circuits are combined with heat exchange occurring between a condenser and absorber of a high temperature circuit, and a generator of a low temperature circuit. The evaporators of both the high and low temperature circuits provide cooling to an external heat load.

Differential transimpedance amplifier circuit for correlated differential amplification

DOEpatents

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Performance of In-Pixel Circuits for Photon Counting Arrays (PCAs) Based on Polycrystalline Silicon TFTs

PubMed Central

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A.; Lu, Jeng Ping

2017-01-01

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si) — a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance — information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% FWHM at 70 keV; and the digital components should work well even in the presence of significant TFT variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm. PMID:26878107

Performance of in-pixel circuits for photon counting arrays (PCAs) based on polycrystalline silicon TFTs.

PubMed

Liang, Albert K; Koniczek, Martin; Antonuk, Larry E; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A; Lu, Jeng Ping

2016-03-07

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si)-a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance-information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% full width at half maximum (FWHM) at 70 keV; and the digital components should work well even in the presence of significant thin-film transistor (TFT) variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm.

Circuit strength training improves muscle strength, functional performance and anthropometric indicators in sedentary elderly women.

PubMed

Mazini Filho, Mauro L; Aidar, Felipe J; Gama de Matos, Dihogo; Costa Moreira, Osvaldo; Patrocínio de Oliveira, Cláudia E; de Oliveira Venturini, Gabriela R; Magalhães Curty, Victor; Menezes Touguinha, Henrique; Caputo Ferreira, Maria E

2017-04-26

This study aimed to investigate the effects of circuit strength training on the muscle strength, functional autonomy and anthropometric indicators of the elderly. Were included 65 women divided in two groups: strength training (TG, n= 34) and control group (CG, n = 31). The strength-training group was subjected to a circuit shaped training program, three days per week, for a period of 12 weeks. In each training session, the circuit was repeated three times. In each circuit, all exercises wereperformed once, with 8 to 12 repetitions per exercise, with 30-seconds intervals between each exercise. TG showed significantly changes in body composition post 12 weeks, as decreases in body weight (Δ -1.5±1.8 kg) and BMI (Δ-0.57 ±0.74 kg/m²), and decreases in abdominal (Δ -3±1.61 cm), waist (Δ -1 ± 1.61 cm), hip (Δ -2.75±1.44 cm) and waist hip ratio circumference (Δ -0.02 ± 0.15 cm). For functional autonomy, TG showed increases post 12 weeks by 30-second chair stand (Δ 3.5±0.4 reps), six minute walk (Δ60.95±7.91 m), back scratch (Δ 3.2 ± 1.36 cm), and time up and go tests (Δ -1,62 ±0,15s). TG also showed increases in muscle strength post 12 weeks in both leg press (Δ 11±1,29 kg) and lat pulldown (Δ11 ±0,75 Kg). For CG, Body composition, functional autonomy and muscle strength did not improved in any moment. Hence, circuit strength training provides significant improvements inmuscle strength, functional performance and anthropometric indicators in sedentary elderly women.

Ultra-Low-Energy Sub-Threshold Circuits: Program Overview

DTIC Science & Technology

2007-04-10

with global > 0.1 corner, but so does VUL, VIH 0 .0 5 -_ "or ni n a Global Variatlion 0.0a 0•,lN& 0.24.. 7 Mir" Output Swing Metrics " Need a... VIH . lines plot the VTCs when random local VT mismatch is ap- In Figure 1(b), a NAND gate has sufficient output swing plied to the inverter. One case...the VTC is input-dependent, all inputs are varied simultaneously to >P 1 0 SNM side of largest obtain the worst case ViH and VIL. > 0 ins0nbedsquare

Cell short circuit, preshort signature

NASA Technical Reports Server (NTRS)

Lurie, C.

1980-01-01

Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

Commutation circuit for an HVDC circuit breaker

DOEpatents

Premerlani, William J.

1981-01-01

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

Commutation circuit for an HVDC circuit breaker

DOEpatents

Premerlani, W.J.

1981-11-10

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.

Electro-optical Probing Of Terahertz Integrated Circuits

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

1990-01-01

Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Aberrant functional connectivity in Papez circuit correlates with memory performance in cognitively intact middle-aged APOE4 carriers.

PubMed

Li, Wenjun; Antuono, Piero G; Xie, Chunming; Chen, Gang; Jones, Jennifer L; Ward, B Douglas; Singh, Suraj P; Franczak, Malgorzata B; Goveas, Joseph S; Li, Shi-Jiang

2014-08-01

The main objective of this study is to detect the early changes in resting-state Papez circuit functional connectivity using the hippocampus as the seed, and to determine the associations between altered functional connectivity (FC) and the episodic memory performance in cognitively intact middle-aged apolipoprotein E4 (APOE4) carriers who are at risk of Alzheimer's disease (AD). Forty-six cognitively intact, middle-aged participants, including 20 APOE4 carriers and 26 age-, sex-, and education-matched noncarriers were studied. The resting-state FC of the hippocampus (HFC) was compared between APOE4 carriers and noncarriers. APOE4 carriers showed significantly decreased FC in brain areas that involve learning and memory functions, including the frontal, cingulate, thalamus and basal ganglia regions. Multiple linear regression analysis showed significant correlations between HFC and the episodic memory performance. Conjunction analysis between neural correlates of memory and altered HFC showed the overlapping regions, especially the subcortical regions such as thalamus, caudate nucleus, and cingulate cortices involved in the Papez circuit. Thus, changes in connectivity in the Papez circuit may be used as an early risk detection for AD. Copyright © 2014. Published by Elsevier Ltd.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability

Tunable Low Energy, Compact and High Performance Neuromorphic Circuit for Spike-Based Synaptic Plasticity

PubMed Central

Rahimi Azghadi, Mostafa; Iannella, Nicolangelo; Al-Sarawi, Said; Abbott, Derek

2014-01-01

Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities. PMID:24551089

Tunable low energy, compact and high performance neuromorphic circuit for spike-based synaptic plasticity.

PubMed

Rahimi Azghadi, Mostafa; Iannella, Nicolangelo; Al-Sarawi, Said; Abbott, Derek

2014-01-01

Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities.

Performance evaluation of a burst-mode EDFA in an optical packet and circuit integrated network.

PubMed

Shiraiwa, Masaki; Awaji, Yoshinari; Furukawa, Hideaki; Shinada, Satoshi; Puttnam, Benjamin J; Wada, Naoya

2013-12-30

We experimentally investigate the performance of burst-mode EDFA in an optical packet and circuit integrated system. In such networks, packets and light paths can be dynamically assigned to the same fibers, resulting in gain transients in EDFAs throughout the network that can limit network performance. Here, we compare the performance of a 'burst-mode' EDFA (BM-EDFA), employing transient suppression techniques and optical feedback, with conventional EDFAs, and those using automatic gain control and previous BM-EDFA implementations. We first measure gain transients and other impairments in a simplified set-up before making frame error-rate measurements in a network demonstration.

30 CFR 75.800 - High-voltage circuits; circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-07-01

... shall be equipped with devices to provide protection against under-voltage grounded phase, short circuit... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage circuits; circuit breakers. 75.800... § 75.800 High-voltage circuits; circuit breakers. [Statutory Provisions] High-voltage circuits entering...

Performance improvement of magnetized coaxial plasma gun by magnetic circuit on a bias coil

NASA Astrophysics Data System (ADS)

Edo, Takahiro; Matsumoto, Tadafumi; Asai, Tomohiko; Kamino, Yasuhiro; Inomoto, Michiaki; Gota, Hiroshi

2016-10-01

A magnetized coaxial plasmoid accelerator has been utilized for compact torus (CT) injection to refuel into fusion reactor core plasma. Recently, CT injection experiments have been conducted on the C-2/C-2U facility at Tri Alpha Energy. In the series of experiments successful refueling, i.e. increased particle inventory of field-reversed configuration (FRC) plasma, has been observed. In order to improve the performance of CT injector and to refuel in the upgraded FRC device, called C-2W, with higher confinement magnetic field, magnetic circuit consisting of magnetic material onto a bias magnetic coil is currently being tested at Nihon University. Numerical work suggests that the optimized bias magnetic field distribution realizes the increased injection velocity because of higher conversion efficiency of Lorenz self force to kinetic energy. Details of the magnetic circuit design as well as results of the test experiment and field calculations will be presented and discussed.

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2010-01-01

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature

High performance of PbSe/PbS core/shell quantum dot heterojunction solar cells: short circuit current enhancement without the loss of open circuit voltage by shell thickness control.

PubMed

Choi, Hyekyoung; Song, Jung Hoon; Jang, Jihoon; Mai, Xuan Dung; Kim, Sungwoo; Jeong, Sohee

2015-11-07

We fabricated heterojunction solar cells with PbSe/PbS core shell quantum dots and studied the precisely controlled PbS shell thickness dependency in terms of optical properties, electronic structure, and solar cell performances. When the PbS shell thickness increases, the short circuit current density (JSC) increases from 6.4 to 11.8 mA cm(-2) and the fill factor (FF) enhances from 30 to 49% while the open circuit voltage (VOC) remains unchanged at 0.46 V even with the decreased effective band gap. We found that the Fermi level and the valence band maximum level remain unchanged in both the PbSe core and PbSe/PbS core/shell with a less than 1 nm thick PbS shell as probed via ultraviolet photoelectron spectroscopy (UPS). The PbS shell reduces their surface trap density as confirmed by relative quantum yield measurements. Consequently, PbS shell formation on the PbSe core mitigates the trade-off relationship between the open circuit voltage and the short circuit current density. Finally, under the optimized conditions, the PbSe core with a 0.9 nm thick shell yielded a power conversion efficiency of 6.5% under AM 1.5.

On Demand Internal Short Circuit Device Enables Verification of Safer, Higher Performing Battery Designs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Darcy, Eric; Keyser, Matthew

The Internal Short Circuit (ISC) device enables critical battery safety verification. With the aluminum interstitial heat sink between the cells, normal trigger cells cannot be driven into thermal runaway without excessive temperature bias of adjacent cells. With an implantable, on-demand ISC device, thermal runaway tests show that the conductive heat sinks protected adjacent cells from propagation. High heat dissipation and structural support of Al heat sinks show high promise for safer, higher performing batteries.

Contact-induced crystallinity for high-performance soluble acene-based transistors and circuits

NASA Astrophysics Data System (ADS)

Gundlach, D. J.; Royer, J. E.; Park, S. K.; Subramanian, S.; Jurchescu, O. D.; Hamadani, B. H.; Moad, A. J.; Kline, R. J.; Teague, L. C.; Kirillov, O.; Richter, C. A.; Kushmerick, J. G.; Richter, L. J.; Parkin, S. R.; Jackson, T. N.; Anthony, J. E.

2008-03-01

The use of organic materials presents a tremendous opportunity to significantly impact the functionality and pervasiveness of large-area electronics. Commercialization of this technology requires reduction in manufacturing costs by exploiting inexpensive low-temperature deposition and patterning techniques, which typically lead to lower device performance. We report a low-cost approach to control the microstructure of solution-cast acene-based organic thin films through modification of interfacial chemistry. Chemically and selectively tailoring the source/drain contact interface is a novel route to initiating the crystallization of soluble organic semiconductors, leading to the growth on opposing contacts of crystalline films that extend into the transistor channel. This selective crystallization enables us to fabricate high-performance organic thin-film transistors and circuits, and to deterministically study the influence of the microstructure on the device characteristics. By connecting device fabrication to molecular design, we demonstrate that rapid film processing under ambient room conditions and high performance are not mutually exclusive.

Development of high-performance printed organic field-effect transistors and integrated circuits.

PubMed

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2015-10-28

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

Protection circuits for very high frequency ultrasound systems.

PubMed

Choi, Hojong; Shung, K Kirk

2014-04-01

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (-1.0 dB), THD (-69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications.

Protection Circuits for Very High Frequency Ultrasound Systems

PubMed Central

Shung, K. Kirk

2014-01-01

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (−1.0 dB), THD (−69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications. PMID:24682684

SEU Performance of TAG Based Flip Flops

NASA Technical Reports Server (NTRS)

Shuler, Robert L.; Kouba, Coy; O'Neill, Patrick M.

2005-01-01

We describe heavy ion test results for two new SEU tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5microprocess.

A Cost-Effective Energy-Recovering Sustain Driving Circuit for ac Plasma Display Panels

NASA Astrophysics Data System (ADS)

Lim, Jae Kwang; Tae, Heung-Sik; Choi, Byungcho; Kim, Seok Gi

A new sustain driving circuit, featuring an energy-recovering function with simple structure and minimal component count, is proposed as a cost-effective solution for driving plasma display panels during the sustaining period. Compared with existing solutions, the proposed circuit reduces the number of semiconductor switches and reactive circuit components without compromising the circuit performance and gas-discharging characteristics. In addition, the proposed circuit utilizes the harness wire as an inductive circuit component, thereby further simplifying the circuit structure. The performance of the proposed circuit is confirmed with a 42-inch plasma display panel.

30 CFR 77.800 - High-voltage circuits; circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-07-01

... devices to provide protection against under voltage, grounded phase, short circuit and overcurrent. High... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage circuits; circuit breakers. 77.800... COAL MINES Surface High-Voltage Distribution § 77.800 High-voltage circuits; circuit breakers. High...

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Project Circuits in a Basic Electric Circuits Course

ERIC Educational Resources Information Center

Becker, James P.; Plumb, Carolyn; Revia, Richard A.

2014-01-01

The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

Electronic circuits

NASA Technical Reports Server (NTRS)

1976-01-01

Twenty-nine circuits and circuit techniques developed for communications and instrumentation technology are described. Topics include pulse-code modulation, phase-locked loops, data coding, data recording, detection circuits, logic circuits, oscillators, and amplifiers.

Computer-aided engineering of semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Crossed SMPS MOSFET-based protection circuit for high frequency ultrasound transceivers and transducers.

PubMed

Choi, Hojong; Shung, K Kirk

2014-06-12

The ultrasonic transducer is one of the core components of ultrasound systems, and the transducer's sensitivity is significantly related the loss of electronic components such as the transmitter, receiver, and protection circuit. In an ultrasonic device, protection circuits are commonly used to isolate the electrical noise between an ultrasound transmitter and transducer and to minimize unwanted discharged pulses in order to protect the ultrasound receiver. However, the performance of the protection circuit and transceiver obviously degrade as the operating frequency or voltage increases. We therefore developed a crossed SMPS (Switching Mode Power Supply) MOSFET-based protection circuit in order to maximize the sensitivity of high frequency transducers in ultrasound systems.The high frequency pulse signals need to trigger the transducer, and high frequency pulse signals must be received by the transducer. We therefore selected the SMPS MOSFET, which is the main component of the protection circuit, to minimize the loss in high frequency operation. The crossed configuration of the protection circuit can drive balanced bipolar high voltage signals from the pulser and transfer the balanced low voltage echo signals from the transducer. The equivalent circuit models of the SMPS MOSFET-based protection circuit are shown in order to select the proper device components. The schematic diagram and operation mechanism of the protection circuit is provided to show how the protection circuit is constructed. The P-Spice circuit simulation was also performed in order to estimate the performance of the crossed MOSFET-based protection circuit. We compared the performance of our crossed SMPS MOSFET-based protection circuit with a commercial diode-based protection circuit. At 60 MHz, our expander and limiter circuits have lower insertion loss than the commercial diode-based circuits. The pulse-echo test is typical method to evaluate the sensitivity of ultrasonic transducers

Algorithms and architecture for multiprocessor based circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deutsch, J.T.

Accurate electrical simulation is critical to the design of high performance integrated circuits. Logic simulators can verify function and give first-order timing information. Switch level simulators are more effective at dealing with charge sharing than standard logic simulators, but cannot provide accurate timing information or discover DC problems. Delay estimation techniques and cell level simulation can be used in constrained design methods, but must be tuned for each application, and circuit simulation must still be used to generate the cell models. None of these methods has the guaranteed accuracy that many circuit designers desire, and none can provide detailed waveformmore » information. Detailed electrical-level simulation can predict circuit performance if devices and parasitics are modeled accurately. However, the computational requirements of conventional circuit simulators make it impractical to simulate current large circuits. In this dissertation, the implementation of Iterated Timing Analysis (ITA), a relaxation-based technique for accurate circuit simulation, on a special-purpose multiprocessor is presented. The ITA method is an SOR-Newton, relaxation-based method which uses event-driven analysis and selective trace to exploit the temporal sparsity of the electrical network. Because event-driven selective trace techniques are employed, this algorithm lends itself to implementation on a data-driven computer.« less

Assessment of SOI Devices and Circuits at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

2007-01-01

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Motor "dexterity"?: Evidence that left hemisphere lateralization of motor circuit connectivity is associated with better motor performance in children.

PubMed

Barber, Anita D; Srinivasan, Priti; Joel, Suresh E; Caffo, Brian S; Pekar, James J; Mostofsky, Stewart H

2012-01-01

Motor control relies on well-established motor circuits, which are critical for typical child development. Although many imaging studies have examined task activation during motor performance, none have examined the relationship between functional intrinsic connectivity and motor ability. The current study investigated the relationship between resting state functional connectivity within the motor network and motor performance assessment outside of the scanner in 40 typically developing right-handed children. Better motor performance correlated with greater left-lateralized (mean left hemisphere-mean right hemisphere) motor circuit connectivity. Speed, rhythmicity, and control of movements were associated with connectivity within different individual region pairs: faster speed was associated with more left-lateralized putamen-thalamus connectivity, less overflow with more left-lateralized supplementary motor-primary motor connectivity, and less dysrhythmia with more left-lateralized supplementary motor-anterior cerebellar connectivity. These findings suggest that for right-handed children, superior motor development depends on the establishment of left-hemisphere dominance in intrinsic motor network connectivity.

Faster Evolution of More Multifunctional Logic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.

Reverse engineering of integrated circuits

DOEpatents

Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

2003-01-01

Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2011-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2012-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, David M.

1996-01-01

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

NASA Astrophysics Data System (ADS)

Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

2017-01-01

Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate integrated waveguides, where the waves propagate through air, thus reducing the associated losses. This is the case of the empty substrate integrated waveguide (ESIW) or the air-filled substrate integrated waveguide (air-filled SIW). However, all these SIC are H plane structures, so classical H plane solutions in rectangular waveguides have already been mapped to most of these new SIC. In this paper a novel E plane empty substrate integrated waveguide (ESIW-E) is presented. This structure allows to easily map classical E plane solutions in rectangular waveguide to this new substrate integrated solution. It is similar to the ESIW, although more layers are needed to build the structure. A wideband transition (covering the frequency range between 33 GHz and 50 GHz) from microstrip to ESIW-E is designed and manufactured. Measurements are successfully compared with simulation, proving the validity of this new SIC. A broadband high-frequency phase shifter (for operation from 35 GHz to 47 GHz) is successfully implemented in ESIW-E, thus proving the good performance of this new SIC in a practical application.

Transistor Level Circuit Experiments using Evolvable Hardware

NASA Technical Reports Server (NTRS)

Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

2005-01-01

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

Double-layer rotor magnetic shield performance analysis in high temperature superconducting synchronous generators under short circuit fault conditions

NASA Astrophysics Data System (ADS)

Hekmati, Arsalan; Aliahmadi, Mehdi

2016-12-01

High temperature superconducting, HTS, synchronous machines benefit from a rotor magnetic shield in order to protect superconducting coils against asynchronous magnetic fields. This magnetic shield, however, suffers from exerted Lorentz forces generated in light of induced eddy currents during transient conditions, e.g. stator windings short-circuit fault. In addition, to the exerted electromagnetic forces, eddy current losses and the associated effects on the cryogenic system are the other consequences of shielding HTS coils. This study aims at investigating the Rotor Magnetic Shield, RMS, performance in HTS synchronous generators under stator winding short-circuit fault conditions. The induced eddy currents in different circumferential positions of the rotor magnetic shield along with associated Joule heating losses would be studied using 2-D time-stepping Finite Element Analysis, FEA. The investigation of Lorentz forces exerted on the magnetic shield during transient conditions has also been performed in this paper. The obtained results show that double line-to-ground fault is of the most importance among different types of short-circuit faults. It was revealed that when it comes to the design of the rotor magnetic shields, in addition to the eddy current distribution and the associated ohmic losses, two phase-to-ground fault should be taken into account since the produced electromagnetic forces in the time of fault conditions are more severe during double line-to-ground fault.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, D.M.

1996-11-05

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

Adapting Aquatic Circuit Training for Special Populations.

ERIC Educational Resources Information Center

Thome, Kathleen

1980-01-01

The author discusses how land activities can be adapted to water so that individuals with handicapping conditions can participate in circuit training activities. An initial section lists such organizational procedures as providing vocal and/or visual cues for activities, having assistants accompany the performers throughout the circuit, and…

Crossed SMPS MOSFET-based protection circuit for high frequency ultrasound transceivers and transducers

PubMed Central

2014-01-01

Background The ultrasonic transducer is one of the core components of ultrasound systems, and the transducer’s sensitivity is significantly related the loss of electronic components such as the transmitter, receiver, and protection circuit. In an ultrasonic device, protection circuits are commonly used to isolate the electrical noise between an ultrasound transmitter and transducer and to minimize unwanted discharged pulses in order to protect the ultrasound receiver. However, the performance of the protection circuit and transceiver obviously degrade as the operating frequency or voltage increases. We therefore developed a crossed SMPS (Switching Mode Power Supply) MOSFET-based protection circuit in order to maximize the sensitivity of high frequency transducers in ultrasound systems. The high frequency pulse signals need to trigger the transducer, and high frequency pulse signals must be received by the transducer. We therefore selected the SMPS MOSFET, which is the main component of the protection circuit, to minimize the loss in high frequency operation. The crossed configuration of the protection circuit can drive balanced bipolar high voltage signals from the pulser and transfer the balanced low voltage echo signals from the transducer. Methods The equivalent circuit models of the SMPS MOSFET-based protection circuit are shown in order to select the proper device components. The schematic diagram and operation mechanism of the protection circuit is provided to show how the protection circuit is constructed. The P-Spice circuit simulation was also performed in order to estimate the performance of the crossed MOSFET-based protection circuit. Results We compared the performance of our crossed SMPS MOSFET-based protection circuit with a commercial diode-based protection circuit. At 60 MHz, our expander and limiter circuits have lower insertion loss than the commercial diode-based circuits. The pulse-echo test is typical method to evaluate the sensitivity of

NAND Flash Qualification Guideline

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2012-01-01

Better performing Forward Error Correction on the forward link along with adequate power in the data open an uplink operations trade space that enable missions to: Command to greater distances in deep space (increased uplink margin). Increase the size of the payload data (latency may be a factor). Provides space for the security header/trailer of the CCSDS Space Data Link Security Protocol. Note: These higher rates could be used for relief of emergency communication margins/rates and not limited to improving top-end rate performance. A higher performance uplink could also reduce the requirements on flight emergency antenna size and/or the performance required from ground stations. Use of a selective repeat ARQ protocol may increase the uplink design requirements but the resultant development is deemed acceptable, due the factor of 4 to 8 potential increase in uplink data rate.

Circuit filling factor (CFF) for multiply tuned probes, revisited

NASA Astrophysics Data System (ADS)

Conradi, Mark S.; Zens, Albert P.

2018-07-01

The concept of circuit filling factor (CFF) is re-examined for multi-tuned, multi-inductor probe circuits. The CFF is the fraction of magnetic stored energy residing in the NMR coil. The CFF theorem states that the CFF sums to unity across all the resonant normal modes. It dictates that improved performance from a large CFF in one mode comes at the expense of CFF (and performance) at the other mode(s). Simple analytical calculations of two-mode circuits are used to demonstrate and confirm the CFF theorem. A triple-resonance circuit is calculated to show the large trade-offs involved there. The theorem can provide guidance for choosing the best circuit and relative inductances in multi-nuclear probes. The CFF is directly accessible from ball frequency-shift measurements. We give experimental measures of the CFF from ball shifts and compare to calculated values of the CFF, with good agreement.

Building a Better Neonatal Extracorporeal Life Support Circuit: Comparison of Hemodynamic Performance and Gaseous Microemboli Handling in Different Pump and Oxygenator Technologies.

PubMed

Glass, Kristen; Trivedi, Payal; Wang, Shigang; Woitas, Karl; Kunselman, Allen R; Ündar, Akif

2017-04-01

Neurologic complications during neonatal extracorporeal life support (ECLS) are associated with significant morbidity and mortality. Gaseous microemboli (GME) in the ECLS circuit may be a possible cause. Advances in neonatal circuitry may improve hemodynamic performance and GME handling leading to reduction in patient complications. This study compared hemodynamic performance and GME handling using two centrifugal pumps (Maquet RotaFlow and Medos Deltastream DP3) and polymethylpentene oxygenators (Maquet Quadrox-iD and Medos Hilite 800LT) in a neonatal ECLS circuit model. The experimental circuit was primed with Lactated Ringer's solution and packed human red blood cells (hematocrit 40%) and arranged in parallel with the RotaFlow and DP3 pump, Quadrox-iD and Hilite oxygenator, and Better-Bladder. Hemodynamic trials evaluating pressure drops and total hemodynamic energy (THE) were conducted at 300 and 500 mL/min at 36°C. GME handling was measured after 0.5 mL of air was injected into the venous line using the Emboli Detection and Classification Quantifier System with unique pump, oxygenator, and Better-Bladder combinations. The RotaFlow pump and Quadrox oxygenator arrangement had lower pressure drops and THE loss at both flow rates compared to the DP3 pump and Hilite oxygenator (P < 0.01). Total GME volume and counts decreased with Better-Bladder at both flow rates with all combinations (P < 0.01). Hemodynamic performance and energy loss were similar in all of the circuit combinations. The Better-Bladder significantly decreased GME. All four combinations of pumps and oxygenators also performed similarly in terms of GME handling. © 2017 International Center for Artificial Organs and Transplantation and Wiley Periodicals, Inc.

30 CFR 77.501 - Electric distribution circuits and equipment; repair.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Electric distribution circuits and equipment... OF UNDERGROUND COAL MINES Electrical Equipment-General § 77.501 Electric distribution circuits and equipment; repair. No electrical work shall be performed on electric distribution circuits or equipment...

Changes in fitness and shipboard task performance following circuit weight training programs featuring continuous or interval running.

PubMed

Marcinik, E J; Hodgdon, J A; Englund, C E; O'Brien, J J

1987-01-01

Pre- and post-physiological data were collected on 57 Navy men (mean age = 19.5 years) who participated in either circuit weight training/continuous run (CWT/CR) (N = 31) or circuit weight training/interval run (CWT/IR) (N = 26) programs. Measured variables included 4 measures of upper torso dynamic strength (one repetition maximum [1 RM] for arm curl, bench press, shoulder press, and lat pull-down); two measures of lower torso dynamic strength (1 RM) for knee extension and leg press); one measure of power (number of revolutions completed on an arm ergometer (Monark) at maximum drag); three measures of muscular endurance (number of repetitions at 60% 1 RM for bench press and leg press and maximal number of bent-knee sit-ups in 120 s); one stamina measure (time to exhaustion on a cycle ergometer (Monark) maximal work capacity [MWC] test; and three simulated shipboard tasks: manikin shoulder drag, open/secure a water tight door and paint bucket carry. Composite shipboard performance derived from the summed time (s) required to complete the three tasks was also calculated. Results show performance on the manikin shoulder drag and majority of evaluative fitness measures was significantly (p less than 0.05) enhanced following both circuit weight training/run formats. Significantly (p less than 0.05) higher values for shoulder press (F = 7.2), arm ergometer (F = 5.3), and sit-ups (F = 6.8) and lower values for leg press muscular endurance (F = 5.1) were observed in CWT/IR when compared to CWT/CR.(ABSTRACT TRUNCATED AT 250 WORDS)

Fractal Electronic Circuits Assembled From Nanoclusters

NASA Astrophysics Data System (ADS)

Fairbanks, M. S.; McCarthy, D.; Taylor, R. P.; Brown, S. A.

2009-07-01

Many patterns in nature can be described using fractal geometry. The effect of this fractal character is an array of properties that can include high internal connectivity, high dispersivity, and enhanced surface area to volume ratios. These properties are often desirable in applications and, consequently, fractal geometry is increasingly employed in technologies ranging from antenna to storm barriers. In this paper, we explore the application of fractal geometry to electrical circuits, inspired by the pervasive fractal structure of neurons in the brain. We show that, under appropriate growth conditions, nanoclusters of Sb form into islands on atomically flat substrates via a process close to diffusion-limited aggregation (DLA), establishing fractal islands that will form the basis of our fractal circuits. We perform fractal analysis of the islands to determine the spatial scaling properties (characterized by the fractal dimension, D) of the proposed circuits and demonstrate how varying growth conditions can affect D. We discuss fabrication approaches for establishing electrical contact to the fractal islands. Finally, we present fractal circuit simulations, which show that the fractal character of the circuit translates into novel, non-linear conduction properties determined by the circuit's D value.

Programmable Low-Voltage Circuit Breaker and Tester

NASA Technical Reports Server (NTRS)

Greenfield, Terry

2008-01-01

An instrumentation system that would comprise a remotely controllable and programmable low-voltage circuit breaker plus several electric-circuit-testing subsystems has been conceived, originally for use aboard a spacecraft during all phases of operation from pre-launch testing through launch, ascent, orbit, descent, and landing. The system could also be adapted to similar use aboard aircraft. In comparison with remotely controllable circuit breakers heretofore commercially available, this system would be smaller, less massive, and capable of performing more functions, as needed for aerospace applications.

Non-Foster Circuits for High Performance Antennas: Advantages and Practical Limitations

NASA Astrophysics Data System (ADS)

Jacob, Minu Mariam

The demand for miniaturized, broadband communication systems has created a need for electrically small, broadband antennas. However, all passive electrically small antennas have a fundamental gain-bandwidth limitation related to their electrical size, as first described by Wheeler and Chu. This limitation can be overcome using active non-Foster circuits (negative inductors and/or negative capacitors), which can deliver a broadband input match with active matching techniques, or can help reduce phase dispersion using negative delay effects. This thesis will illustrate the advantages of non-Foster circuits in obtaining broadband small antennas, in addition to examining their practical limitations due to noise in receive applications, and nonlinearity in transmit applications.

RADC SCAT automated sneak circuit analysis tool

NASA Astrophysics Data System (ADS)

Depalma, Edward L.

The sneak circuit analysis tool (SCAT) provides a PC-based system for real-time identification (during the design phase) of sneak paths and design concerns. The tool utilizes an expert system shell to assist the analyst so that prior experience with sneak analysis is not necessary for performance. Both sneak circuits and design concerns are targeted by this tool, with both digital and analog circuits being examined. SCAT focuses the analysis at the assembly level, rather than the entire system, so that most sneak problems can be identified and corrected by the responsible design engineer in a timely manner. The SCAT program identifies the sneak circuits to the designer, who then decides what course of action is necessary.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

"Printed-circuit" rectenna

NASA Technical Reports Server (NTRS)

Dickinson, R. M.

1977-01-01

Rectifying antenna is less bulky structure for absorbing transmitted microwave power and converting it into electrical current. Printed-circuit approach, using microstrip technology and circularly polarized antenna, makes polarization orientation unimportant and allows much smaller arrays for given performance. Innovation is particularly useful with proposed electric vehicles powered by beam microwaves.

Research of vibration control based on current mode piezoelectric shunt damping circuit

NASA Astrophysics Data System (ADS)

Liu, Weiwei; Mao, Qibo

2017-12-01

The piezoelectric shunt damping circuit using current mode approach is imposed to control the vibration of a cantilever beam. Firstly, the simulated inductance with large values are designed for the corresponding RL series shunt circuits. Moreover, with an example of cantilever beam, the second natural frequency of the beam is targeted to control for experiment. By adjusting the values of the equivalent inductance and equivalent resistance of the shunt circuit, the optimal damping of the shunt circuit is obtained. Meanwhile, the designed piezoelectric shunt damping circuit stability is experimental verified. Experimental results show that the proposed piezoelectric shunt damping circuit based on current mode circuit has good vibration control performance. However, the control performance will be reduced if equivalent inductance and equivalent resistance values deviate from optimal values.

Inkjet deposited circuit components

NASA Astrophysics Data System (ADS)

Bidoki, S. M.; Nouri, J.; Heidari, A. A.

2010-05-01

All-printed electronics as a means of achieving ultra-low-cost electronic circuits has attracted great interest in recent years. Inkjet printing is one of the most promising techniques by which the circuit components can be ultimately drawn (i.e. printed) onto the substrate in one step. Here, the inkjet printing technique was used to chemically deposit silver nanoparticles (10-200 nm) simply by ejection of silver nitrate and reducing solutions onto different substrates such as paper, PET plastic film and textile fabrics. The silver patterns were tested for their functionality to work as circuit components like conductor, resistor, capacitor and inductor. Different levels of conductivity were achieved simply by changing the printing sequence, inks ratio and concentration. The highest level of conductivity achieved by an office thermal inkjet printer (300 dpi) was 5.54 × 105 S m-1 on paper. Inkjet deposited capacitors could exhibit a capacitance of more than 1.5 nF (parallel plate 45 × 45 mm2) and induction coils displayed an inductance of around 400 µH (planar coil 10 cm in diameter). Comparison of electronic performance of inkjet deposited components to the performance of conventionally etched items makes the technique highly promising for fabricating different printed electronic devices.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Selection of wires and circuit protective devices for STS Orbiter vehicle payload electrical circuits

NASA Technical Reports Server (NTRS)

Gaston, Darilyn M.

1991-01-01

Electrical designers of Orbiter payloads face the challenge of determining proper circuit protection/wire size parameters to satisfy Orbiter engineering and safety requirements. This document is the result of a program undertaken to review test data from all available aerospace sources and perform additional testing to eliminate extrapolation errors. The resulting compilation of data was used to develop guidelines for the selection of wire sizes and circuit protection ratings. The purpose is to provide guidance to the engineering to ensure a design which meets Orbiter standards and which should be applicable to any aerospace design.

Starting Circuit For Erasable Programmable Logic Device

NASA Technical Reports Server (NTRS)

Cole, Steven W.

1990-01-01

Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

Noise-Aided Logic in an Electronic Analog of Synthetic Genetic Networks

PubMed Central

Hellen, Edward H.; Dana, Syamal K.; Kurths, Jürgen; Kehler, Elizabeth; Sinha, Sudeshna

2013-01-01

We report the experimental verification of noise-enhanced logic behaviour in an electronic analog of a synthetic genetic network, composed of two repressors and two constitutive promoters. We observe good agreement between circuit measurements and numerical prediction, with the circuit allowing for robust logic operations in an optimal window of noise. Namely, the input-output characteristics of a logic gate is reproduced faithfully under moderate noise, which is a manifestation of the phenomenon known as Logical Stochastic Resonance. The two dynamical variables in the system yield complementary logic behaviour simultaneously. The system is easily morphed from AND/NAND to OR/NOR logic. PMID:24124531

Cancellation Circuit for Transmit-Receive Isolation

DTIC Science & Technology

2010-09-01

non -ideal hardware, and the performance of the circuit is limited. One of the major problems is the leakage from the circulator. The leakage disrupts...cancellation circuit was investigated by a series of simulations using Agilent ADS (Agilent Advanced Design System), and hardware tests were conducted to...developed in the WDDPA application, allowing coherent processing of the data from all elements. There are limitations encountered due to non -ideal

Rapid Laser Printing of Paper-Based Multilayer Circuits.

PubMed

Huang, Gui-Wen; Feng, Qing-Ping; Xiao, Hong-Mei; Li, Na; Fu, Shao-Yun

2016-09-27

Laser printing has been widely used in daily life, and the fabricating process is highly efficient and mask-free. Here we propose a laser printing process for the rapid fabrication of paper-based multilayer circuits. It does not require wetting of the paper, which is more competitive in manufacturing paper-based circuits compared to conventional liquid printing process. In the laser printed circuits, silver nanowires (Ag-NWs) are used as conducting material for their excellent electrical and mechanical properties. By repeating the printing process, multilayer three-dimensional (3D) structured circuits can be obtained, which is quite significant for complex circuit applications. In particular, the performance of the printed circuits can be exactly controlled by varying the process parameters including Ag-NW content and laminating temperature, which offers a great opportunity for rapid prototyping of customized products with designed properties. A paper-based high-frequency radio frequency identification (RFID) label with optimized performance is successfully demonstrated. By adjusting the laminating temperature to 180 °C and the top-layer Ag-NW areal density to 0.3 mg cm(-2), the printed RFID antenna can be conjugately matched with the chip, and a big reading range of ∼12.3 cm with about 2.0 cm over that of the commercial etched Al antenna is achieved. This work provides a promising approach for fast and quality-controlled fabrication of multilayer circuits on common paper and may be enlightening for development of paper-based devices.

ADDER CIRCUIT

DOEpatents

Jacobsohn, D.H.; Merrill, L.C.

1959-01-20

An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

ERIC Educational Resources Information Center

Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

2015-01-01

Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

Design of an improved RCD buffer circuit for full bridge circuit

NASA Astrophysics Data System (ADS)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Comparison of the Experimental Performance of Ferroelectric CPW Circuits with Method of Moment Simulations and Conformal Mapping

NASA Technical Reports Server (NTRS)

VanKeuls, Fred W.; Chevalier, Chris T.; Miranda, Felix A.; Carlson, C. M.; Rivkin, T. V.; Parilla, P. A.; Perkins, J. D.; Ginley, D. S.

2001-01-01

Experimental measurements of coplanar waveguide (CPW) circuits atop thin films of ferroelectric Ba(x)Sr(1-x)TiO3 (BST) were made as a function bias from 0 to 200 V and frequency from 0.045 to 20 GHz. The resulting phase shifts are compared with method of moments electromagnetic simulations and a conformal mapping analysis to determine the dielectric constant of the BST films. Based on the correlation between the experimental and the modeled data, an analysis of the extent to which the electromagnetic simulators provide reliable values for the dielectric constant of the ferroelectric in these structures has been performed. In addition, to determine how well the modeled data compare with experimental data, the dielectric constant values were also compared to low frequency measurements of interdigitated capacitor circuits on the same films. Results of these comparisons will be presented.

Artificial immune system algorithm in VLSI circuit configuration

NASA Astrophysics Data System (ADS)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

Printed Graphene Derivative Circuits as Passive Electrical Filters

PubMed Central

Sinar, Dogan

2018-01-01

The objective of this study is to inkjet print resistor-capacitor (RC) low pass electrical filters, using a novel water-based cellulose graphene ink, and compare the voltage-frequency and transient behavior to equivalent circuits constructed from discrete passive components. The synthesized non-toxic graphene-carboxymethyl cellulose (G-CMC) ink is deposited on mechanically flexible polyimide substrates using a customized printer that dispenses functionalized aqueous solutions. The design of the printed first-order and second-order low-pass RC filters incorporate resistive traces and interdigitated capacitors. Low pass filter characteristics, such as time constant, cut-off frequency and roll-off rate, are determined for comparative analysis. Experiments demonstrate that for low frequency applications (<100 kHz) the printed graphene derivative circuits performed as well as the circuits constructed from discrete resistors and capacitors for both low pass filter and RC integrator applications. The impact of mechanical stress due to bending on the electrical performance of the flexible printed circuits is also investigated. PMID:29473890

Printed Graphene Derivative Circuits as Passive Electrical Filters.

PubMed

Sinar, Dogan; Knopf, George K

2018-02-23

The objective of this study is to inkjet print resistor-capacitor ( RC ) low pass electrical filters, using a novel water-based cellulose graphene ink, and compare the voltage-frequency and transient behavior to equivalent circuits constructed from discrete passive components. The synthesized non-toxic graphene-carboxymethyl cellulose (G-CMC) ink is deposited on mechanically flexible polyimide substrates using a customized printer that dispenses functionalized aqueous solutions. The design of the printed first-order and second-order low-pass RC filters incorporate resistive traces and interdigitated capacitors. Low pass filter characteristics, such as time constant, cut-off frequency and roll-off rate, are determined for comparative analysis. Experiments demonstrate that for low frequency applications (<100 kHz) the printed graphene derivative circuits performed as well as the circuits constructed from discrete resistors and capacitors for both low pass filter and RC integrator applications. The impact of mechanical stress due to bending on the electrical performance of the flexible printed circuits is also investigated.

Focal plane infrared readout circuit with automatic background suppression

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Sun, Chao (Inventor); Shaw, Timothy J. (Inventor); Wrigley, Chris J. (Inventor)

2002-01-01

A circuit for reading out a signal from an infrared detector includes a current-mode background-signal subtracting circuit having a current memory which can be enabled to sample and store a dark level signal from the infrared detector during a calibration phase. The signal stored by the current memory is subtracted from a signal received from the infrared detector during an imaging phase. The circuit also includes a buffered direct injection input circuit and a differential voltage readout section. By performing most of the background signal estimation and subtraction in a current mode, a low gain can be provided by the buffered direct injection input circuit to keep the gain of the background signal relatively small, while a higher gain is provided by the differential voltage readout circuit. An array of such readout circuits can be used in an imager having an array of infrared detectors. The readout circuits can provide a high effective handling capacity.

Reconfiguration of parietal circuits with cognitive tutoring in elementary school children

PubMed Central

Jolles, Dietsje; Supekar, Kaustubh; Richardson, Jennifer; Tenison, Caitlin; Ashkenazi, Sarit; Rosenberg-Lee, Miriam; Fuchs, Lynn; Menon, Vinod

2016-01-01

Cognitive development is shaped by brain plasticity during childhood, yet little is known about changes in large-scale functional circuits associated with learning in academically relevant cognitive domains such as mathematics. Here, we investigate plasticity of intrinsic brain circuits associated with one-on-one math tutoring and its relation to individual differences in children’s learning. We focused on functional circuits associated with the intraparietal sulcus (IPS) and angular gyrus (AG), cytoarchitectonically distinct subdivisions of the human parietal cortex with different roles in numerical cognition. Tutoring improved performance and strengthened IPS connectivity with the lateral prefrontal cortex, ventral temporal-occipital cortex, and hippocampus. Crucially, increased IPS connectivity was associated with individual performance gains, highlighting the behavioral significance of plasticity in IPS circuits. Tutoring-related changes in IPS connectivity were distinct from those of the adjacent AG, which did not predict performance gains. Our findings provide new insights into plasticity of functional brain circuits associated with the development of specialized cognitive skills in children. PMID:27618765

Wide-band polarization controller for Si photonic integrated circuits.

PubMed

Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

2016-12-15

A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

Analog integrated circuits design for processing physiological signals.

PubMed

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

42 CFR 84.93 - Gas flow test; open-circuit apparatus.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 42 Public Health 1 2011-10-01 2011-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be performed on all open-circuit apparatus. (b) The flow from the apparatus shall be greater than 200 liters...

42 CFR 84.93 - Gas flow test; open-circuit apparatus.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 42 Public Health 1 2010-10-01 2010-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be performed on all open-circuit apparatus. (b) The flow from the apparatus shall be greater than 200 liters...

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Optimization study on inductive-resistive circuit for broadband piezoelectric energy harvesters

NASA Astrophysics Data System (ADS)

Tan, Ting; Yan, Zhimiao

2017-03-01

The performance of cantilever-beam piezoelectric energy harvester is usually analyzed with pure resistive circuit. The optimal performance of such a vibration-based energy harvesting system is limited by narrow bandwidth around its modified natural frequency. For broadband piezoelectric energy harvesting, series and parallel inductive-resistive circuits are introduced. The electromechanical coupled distributed parameter models for such systems under harmonic base excitations are decoupled with modified natural frequency and electrical damping to consider the coupling effect. Analytical solutions of the harvested power and tip displacement for the electromechanical decoupled model are confirmed with numerical solutions for the coupled model. The optimal performance of piezoelectric energy harvesting with inductive-resistive circuits is revealed theoretically as constant maximal power at any excitation frequency. This is achieved by the scenarios of matching the modified natural frequency with the excitation frequency and equating the electrical damping to the mechanical damping. The inductance and load resistance should be simultaneously tuned to their optimal values, which may not be applicable for very high electromechanical coupling systems when the excitation frequency is higher than their natural frequencies. With identical optimal performance, the series inductive-resistive circuit is recommended for relatively small load resistance, while the parallel inductive-resistive circuit is suggested for relatively large load resistance. This study provides a simplified optimization method for broadband piezoelectric energy harvesters with inductive-resistive circuits.

Advanced Packaging for VLSI/VHSIC (Very Large Scale Integrated Circuits/Very High Speed Integrated Circuits) Applications: Electrical, Thermal, and Mechanical Considerations - An IR&D Report.

DTIC Science & Technology

1987-11-01

developed that can be used by circuit engineers to extract the maximum performance from the devices on various board technologies including multilayer ceramic...Design guidelines have been developed that can be used by circuit engineers to extract the maxi- mum performance from the devices on various board...25 Attenuation and Dispersion Effects ......................................... 27 Skin Effect

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few

Monolithic microwave integrated circuits: Interconnections and packaging considerations

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

1984-01-01

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

Monolithic microwave integrated circuits: Interconnections and packaging considerations

NASA Astrophysics Data System (ADS)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

VLSI circuits implementing computational models of neocortical circuits.

PubMed

Wijekoon, Jayawan H B; Dudek, Piotr

2012-09-15

This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. Copyright © 2012 Elsevier B.V. All rights reserved.

Phased-Array Antenna With Optoelectronic Control Circuits

NASA Technical Reports Server (NTRS)

Kunath, Richard R.; Shalkhauser, Kurt A.; Martzaklis, Konstantinos; Lee, Richard Q.; Downey, Alan N.; Simons, Rainee N.

1995-01-01

Prototype phased-array antenna features control of amplitude and phase at each radiating element. Amplitude- and phase-control signals transmitted on optical fiber to optoelectronic interface circuit (OEIC), then to monolithic microwave integrated circuit (MMIC) at each element. Offers advantages of flexible, rapid electronic steering and shaping of beams. Furthermore, greater number of elements, less overall performance of antenna degraded by malfunction in single element.

Simulation Approach for Timing Analysis of Genetic Logic Circuits.

PubMed

Baig, Hasan; Madsen, Jan

2017-07-21

Constructing genetic logic circuits is an application of synthetic biology in which parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by an appropriate concentration of certain proteins or by different genetic components. These logic circuits work in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits, a capability that we believe will be important for design automation in synthetic biology.

Controlled conjugated backbone twisting for an increased open-circuit voltage while having a high short-circuit current in poly(hexylthiophene) derivatives.

PubMed

Ko, Sangwon; Hoke, Eric T; Pandey, Laxman; Hong, Sanghyun; Mondal, Rajib; Risko, Chad; Yi, Yuanping; Noriega, Rodrigo; McGehee, Michael D; Brédas, Jean-Luc; Salleo, Alberto; Bao, Zhenan

2012-03-21

Conjugated polymers with nearly planar backbones have been the most commonly investigated materials for organic-based electronic devices. More twisted polymer backbones have been shown to achieve larger open-circuit voltages in solar cells, though with decreased short-circuit current densities. We systematically impose twists within a family of poly(hexylthiophene)s and examine their influence on the performance of polymer:fullerene bulk heterojunction (BHJ) solar cells. A simple chemical modification concerning the number and placement of alkyl side chains along the conjugated backbone is used to control the degree of backbone twisting. Density functional theory calculations were carried out on a series of oligothiophene structures to provide insights on how the sterically induced twisting influences the geometric, electronic, and optical properties. Grazing incidence X-ray scattering measurements were performed to investigate how the thin-film packing structure was affected. The open-circuit voltage and charge-transfer state energy of the polymer:fullerene BHJ solar cells increased substantially with the degree of twist induced within the conjugated backbone--due to an increase in the polymer ionization potential--while the short-circuit current decreased as a result of a larger optical gap and lower hole mobility. A controlled, moderate degree of twist along the poly(3,4-dihexyl-2,2':5',2''-terthiophene) (PDHTT) conjugated backbone led to a 19% enhancement in the open-circuit voltage (0.735 V) vs poly(3-hexylthiophene)-based devices, while similar short-circuit current densities, fill factors, and hole-carrier mobilities were maintained. These factors resulted in a power conversion efficiency of 4.2% for a PDHTT:[6,6]-phenyl-C(71)-butyric acid methyl ester (PC(71)BM) blend solar cell without thermal annealing. This simple approach reveals a molecular design avenue to increase open-circuit voltage while retaining the short-circuit current.

Predicting the behavior of microfluidic circuits made from discrete elements

PubMed Central

Bhargava, Krisna C.; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah

2015-01-01

Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand. PMID:26516059

Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

NASA Technical Reports Server (NTRS)

Johnston, Allan H.; Rax, Bernard G.

2006-01-01

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

Reconfiguration of parietal circuits with cognitive tutoring in elementary school children.

PubMed

Jolles, Dietsje; Supekar, Kaustubh; Richardson, Jennifer; Tenison, Caitlin; Ashkenazi, Sarit; Rosenberg-Lee, Miriam; Fuchs, Lynn; Menon, Vinod

2016-10-01

Cognitive development is shaped by brain plasticity during childhood, yet little is known about changes in large-scale functional circuits associated with learning in academically relevant cognitive domains such as mathematics. Here, we investigate plasticity of intrinsic brain circuits associated with one-on-one math tutoring and its relation to individual differences in children's learning. We focused on functional circuits associated with the intraparietal sulcus (IPS) and angular gyrus (AG), cytoarchitectonically distinct subdivisions of the human parietal cortex with different roles in numerical cognition. Tutoring improved performance and strengthened IPS connectivity with the lateral prefrontal cortex, ventral temporal-occipital cortex, and hippocampus. Crucially, increased IPS connectivity was associated with individual performance gains, highlighting the behavioral significance of plasticity in IPS circuits. Tutoring-related changes in IPS connectivity were distinct from those of the adjacent AG, which did not predict performance gains. Our findings provide new insights into plasticity of functional brain circuits associated with the development of specialized cognitive skills in children. Copyright © 2016 Elsevier Ltd. All rights reserved.

Using Sphinx to Improve Onion Routing Circuit Construction

NASA Astrophysics Data System (ADS)

Kate, Aniket; Goldberg, Ian

This paper presents compact message formats for onion routing circuit construction using the Sphinx methodology developed for mixes. We significantly compress the circuit construction messages for three onion routing protocols that have emerged as enhancements to the Tor anonymizing network; namely, Tor with predistributed Diffie-Hellman values, pairing-based onion routing, and certificateless onion routing. Our new circuit constructions are also secure in the universal composability framework, a property that was missing from the original constructions. Further, we compare the performance of our schemes with their older counterparts as well as with each other.

Current limiter circuit system

DOEpatents

Witcher, Joseph Brandon; Bredemann, Michael V.

2017-09-05

An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

Astable Oscillator Circuits using Silicon-on-Insulator Timer Chip for Wide Range Temperature Sensing

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Culley, Dennis; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Two astable oscillator circuits were constructed using a new silicon-on-insulator (SOI) 555 timer chip for potential use as a temperature sensor in harsh environments encompassing jet engine and space mission applications. The two circuits, which differed slightly in configuration, were evaluated between -190 and 200 C. The output of each circuit was made to produce a stream of rectangular pulses whose frequency was proportional to the sensed temperature. The preliminary results indicated that both circuits performed relatively well over the entire test temperature range. In addition, after the circuits were subjected to limited thermal cycling over the temperature range of -190 to 200 C, the performance of either circuit did not experience any significant change.

Circuit-based versus full-wave modelling of active microwave circuits

NASA Astrophysics Data System (ADS)

Bukvić, Branko; Ilić, Andjelija Ž.; Ilić, Milan M.

2018-03-01

Modern full-wave computational tools enable rigorous simulations of linear parts of complex microwave circuits within minutes, taking into account all physical electromagnetic (EM) phenomena. Non-linear components and other discrete elements of the hybrid microwave circuit are then easily added within the circuit simulator. This combined full-wave and circuit-based analysis is a must in the final stages of the circuit design, although initial designs and optimisations are still faster and more comfortably done completely in the circuit-based environment, which offers real-time solutions at the expense of accuracy. However, due to insufficient information and general lack of specific case studies, practitioners still struggle when choosing an appropriate analysis method, or a component model, because different choices lead to different solutions, often with uncertain accuracy and unexplained discrepancies arising between the simulations and measurements. We here design a reconfigurable power amplifier, as a case study, using both circuit-based solver and a full-wave EM solver. We compare numerical simulations with measurements on the manufactured prototypes, discussing the obtained differences, pointing out the importance of measured parameters de-embedding, appropriate modelling of discrete components and giving specific recipes for good modelling practices.

Gate drive latching circuit for an auxiliary resonant commutation circuit

NASA Technical Reports Server (NTRS)

Delgado, Eladio Clemente (Inventor); Kheraluwala, Mustansir Hussainy (Inventor)

1999-01-01

A gate drive latching circuit for an auxiliary resonant commutation circuit for a power switching inverter includes a current monitor circuit providing a current signal to a pair of analog comparators to implement latching of one of a pair of auxiliary switching devices which are used to provide commutation current for commutating switching inverters in the circuit. Each of the pair of comparators feeds a latching circuit which responds to an active one of the comparators for latching the associated gate drive circuit for one of the pair of auxiliary commutating switches. An initial firing signal is applied to each of the commutating switches to gate each into conduction and the resulting current is monitored to determine current direction and therefore the one of the switches which is carrying current. The comparator provides a latching signal to the one of the auxiliary power switches which is actually conducting current and latches that particular power switch into an on state for the duration of current through the device. The latching circuit is so designed that the only time one of the auxiliary switching devices can be latched on is during the duration of an initial firing command signal.

Universal programmable quantum circuit schemes to emulate an operator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantummore » complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.« less

Non-unitary probabilistic quantum computing circuit and method

NASA Technical Reports Server (NTRS)

Williams, Colin P. (Inventor); Gingrich, Robert M. (Inventor)

2009-01-01

A quantum circuit performing quantum computation in a quantum computer. A chosen transformation of an initial n-qubit state is probabilistically obtained. The circuit comprises a unitary quantum operator obtained from a non-unitary quantum operator, operating on an n-qubit state and an ancilla state. When operation on the ancilla state provides a success condition, computation is stopped. When operation on the ancilla state provides a failure condition, computation is performed again on the ancilla state and the n-qubit state obtained in the previous computation, until a success condition is obtained.

30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

Code of Federal Regulations, 2010 CFR

2010-07-01

... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

LEC GaAs for integrated circuit applications

NASA Technical Reports Server (NTRS)

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Analog Computation by DNA Strand Displacement Circuits.

PubMed

Song, Tianqi; Garg, Sudhanshu; Mokhtar, Reem; Bui, Hieu; Reif, John

2016-08-19

DNA circuits have been widely used to develop biological computing devices because of their high programmability and versatility. Here, we propose an architecture for the systematic construction of DNA circuits for analog computation based on DNA strand displacement. The elementary gates in our architecture include addition, subtraction, and multiplication gates. The input and output of these gates are analog, which means that they are directly represented by the concentrations of the input and output DNA strands, respectively, without requiring a threshold for converting to Boolean signals. We provide detailed domain designs and kinetic simulations of the gates to demonstrate their expected performance. On the basis of these gates, we describe how DNA circuits to compute polynomial functions of inputs can be built. Using Taylor Series and Newton Iteration methods, functions beyond the scope of polynomials can also be computed by DNA circuits built upon our architecture.

Dimension scaling effects on the yield sensitivity of HEMT digital circuits

NASA Technical Reports Server (NTRS)

Sarker, Jogendra C.; Purviance, John E.

1992-01-01

In our previous works, using a graphical tool, yield factor histograms, we studied the yield sensitivity of High Electron Mobility Transistors (HEMT) and HEMT circuit performance with the variation of process parameters. This work studies the scaling effects of process parameters on yield sensitivity of HEMT digital circuits. The results from two HEMT circuits are presented.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

Code of Federal Regulations, 2010 CFR

2010-07-01

... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Synthetic Analog and Digital Circuits for Cellular Computation and Memory

PubMed Central

Purcell, Oliver; Lu, Timothy K.

2014-01-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene circuits that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. PMID:24794536

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NASA Astrophysics Data System (ADS)

Houin, G.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-09-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance with hysteresis-free characteristics. A number of approaches were applied to simplify the process, improve device performance and decrease the operating voltage: they include an oxide interfacial layer to decrease contact resistance; a polymer passivation layer to optimize semiconductor/dielectric interface and an anodized high-k oxide as dielectric layer for low voltage operation. The devices fabricated on plastic substrate yielded excellent electrical characteristics, showing mobility of 1.6 cm2/Vs, lack of hysteresis, operation below 5 V and on/off current ratio above 105. An OFET model based on variable ranging hopping theory was used to extract the relevant parameters from the transfer and output characteristics, which enabled us to simulate our devices achieving reasonable agreement with the measurements

Computer-Aided Design of Low-Noise Microwave Circuits

NASA Astrophysics Data System (ADS)

Wedge, Scott William

1991-02-01

Devoid of most natural and manmade noise, microwave frequencies have detection sensitivities limited by internally generated receiver noise. Low-noise amplifiers are therefore critical components in radio astronomical antennas, communications links, radar systems, and even home satellite dishes. A general technique to accurately predict the noise performance of microwave circuits has been lacking. Current noise analysis methods have been limited to specific circuit topologies or neglect correlation, a strong effect in microwave devices. Presented here are generalized methods, developed for computer-aided design implementation, for the analysis of linear noisy microwave circuits comprised of arbitrarily interconnected components. Included are descriptions of efficient algorithms for the simultaneous analysis of noisy and deterministic circuit parameters based on a wave variable approach. The methods are therefore particularly suited to microwave and millimeter-wave circuits. Noise contributions from lossy passive components and active components with electronic noise are considered. Also presented is a new technique for the measurement of device noise characteristics that offers several advantages over current measurement methods.

Digitally Programmable Analogue Circuits for Sensor Conditioning Systems

PubMed Central

Zatorre, Guillermo; Medrano, Nicolás; Sanz, María Teresa; Aldea, Concepción; Calvo, Belén; Celma, Santiago

2009-01-01

This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 μm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components. PMID:22412331

Micromachined integrated quantum circuit containing a superconducting qubit

NASA Astrophysics Data System (ADS)

Brecht, Teresa; Chu, Yiwen; Axline, Christopher; Pfaff, Wolfgang; Blumoff, Jacob; Chou, Kevin; Krayzman, Lev; Frunzio, Luigi; Schoelkopf, Robert

We demonstrate a functional multilayer microwave integrated quantum circuit (MMIQC). This novel hardware architecture combines the high coherence and isolation of three-dimensional structures with the advantages of integrated circuits made with lithographic techniques. We present fabrication and measurement of a two-cavity/one-qubit prototype, including a transmon coupled to a three-dimensional microwave cavity micromachined in a silicon wafer. It comprises a simple MMIQC with competitive lifetimes and the ability to perform circuit QED operations in the strong dispersive regime. Furthermore, the design and fabrication techniques that we have developed are extensible to more complex quantum information processing devices.

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Thermocouple-Signal-Conditioning Circuit

NASA Technical Reports Server (NTRS)

Simon, Richard A.

1991-01-01

Thermocouple-signal-conditioning circuit acting in conjunction with thermocouple, exhibits electrical behavior of voltage in series with resistance. Combination part of input bridge circuit of controller. Circuit configured for either of two specific applications by selection of alternative resistances and supply voltages. Includes alarm circuit detecting open circuit in thermocouple and provides off-scale output to signal malfunctions.

Nonlinear interferometry approach to photonic sequential logic

NASA Astrophysics Data System (ADS)

Mabuchi, Hideo

2011-10-01

Motivated by rapidly advancing capabilities for extensive nanoscale patterning of optical materials, I propose an approach to implementing photonic sequential logic that exploits circuit-scale phase coherence for efficient realizations of fundamental components such as a NAND-gate-with-fanout and a bistable latch. Kerr-nonlinear optical resonators are utilized in combination with interference effects to drive the binary logic. Quantum-optical input-output models are characterized numerically using design parameters that yield attojoule-scale energy separation between the latch states.

Unidirectional invisibility induced by parity-time symmetric circuit

NASA Astrophysics Data System (ADS)

Lv, Bo; Fu, Jiahui; Wu, Bian; Li, Rujiang; Zeng, Qingsheng; Yin, Xinhua; Wu, Qun; Gao, Lei; Chen, Wan; Wang, Zhefei; Liang, Zhiming; Li, Ao; Ma, Ruyu

2017-01-01

Parity-time (PT) symmetric structures present the unidirectional invisibility at the spontaneous PT-symmetry breaking point. In this paper, we propose a PT-symmetric circuit consisting of a resistor and a microwave tunnel diode (TD) which represent the attenuation and amplification, respectively. Based on the scattering matrix method, the circuit can exhibit an ideal unidirectional performance at the spontaneous PT-symmetry breaking point by tuning the transmission lines between the lumped elements. Additionally, the resistance of the reactance component can alter the bandwidth of the unidirectional invisibility flexibly. Furthermore, the electromagnetic simulation for the proposed circuit validates the unidirectional invisibility and the synchronization with the input energy well. Our work not only provides an unidirectional invisible circuit based on PT-symmetry, but also proposes a potential solution for the extremely selective filter or cloaking applications.

Age and visual impairment decrease driving performance as measured on a closed-road circuit.

PubMed

Wood, Joanne M

2002-01-01

In this study the effects of visual impairment and age on driving were investigated and related to visual function. Participants were 139 licensed drivers (young, middle-aged, and older participants with normal vision, and older participants with ocular disease). Driving performance was assessed during the daytime on a closed-road driving circuit. Visual performance was assessed using a vision testing battery. Age and visual impairment had a significant detrimental effect on recognition tasks (detection and recognition of signs and hazards), time to complete driving tasks (overall course time, reversing, and maneuvering), maneuvering ability, divided attention, and an overall driving performance index. All vision measures were significantly affected by group membership. A combination of motion sensitivity, useful field of view (UFOV), Pelli-Robson letter contrast sensitivity, and dynamic acuity could predict 50% of the variance in overall driving scores. These results indicate that older drivers with either normal vision or visual impairment had poorer driving performance compared with younger or middle-aged drivers with normal vision. The inclusion of tests such as motion sensitivity and the UFOV significantly improve the predictive power of vision tests for driving performance. Although such measures may not be practical for widespread screening, their application in selected cases should be considered.

GLPG0492, a novel selective androgen receptor modulator, improves muscle performance in the exercised-mdx mouse model of muscular dystrophy.

PubMed

Cozzoli, Anna; Capogrosso, Roberta Francesca; Sblendorio, Valeriana Teresa; Dinardo, Maria Maddalena; Jagerschmidt, Catherine; Namour, Florence; Camerino, Giulia Maria; De Luca, Annamaria

2013-06-01

Anabolic drugs may counteract muscle wasting and dysfunction in Duchenne muscular dystrophy (DMD); however, steroids have unwanted side effects. We focused on GLPG0492, a new non-steroidal selective androgen receptor modulator that is currently under development for musculo-skeletal diseases such as sarcopenia and cachexia. GLPG0492 was tested in the exercised mdx mouse model of DMD in a 4-week trial at a single high dose (30 mg/kg, 6 day/week s.c.), and the results were compared with those from the administration of α-methylprednisolone (PDN; 1 mg/kg, i.p.) and nandrolone (NAND, 5 mg/kg, s.c.). This assessment was followed by a 12-week dose-dependence study (0.3-30 mg/kg s.c.). The outcomes were evaluated in vivo and ex vivo on functional, histological and biochemical parameters. Similar to PDN and NAND, GLPG0492 significantly increased mouse strength. In acute exhaustion tests, a surrogate of the 6-min walking test used in DMD patients, GLPG0492 preserved running performance, whereas vehicle- or comparator-treated animals showed a significant increase in fatigue (30-50%). Ex vivo, all drugs resulted in a modest but significant increase of diaphragm force. In parallel, a decrease in the non-muscle area and markers of fibrosis was observed in GLPG0492- and NAND-treated mice. The drugs exerted minor effects on limb muscles; however, electrophysiological biomarkers were ameliorated in extensor digitorum longus muscle. The longer dose-dependence study confirmed the effect on mdx mouse strength and resistance to fatigue and demonstrated the efficacy of lower drug doses on in vivo and ex vivo functional parameters. These results support the interest of further studies of GLPG0492 as a potential treatment for DMD. Copyright © 2013 Elsevier Ltd. All rights reserved.

Engineering a robust DNA split proximity circuit with minimized circuit leakage

PubMed Central

Ang, Yan Shan; Tong, Rachel; Yung, Lin-Yue Lanry

2016-01-01

DNA circuit is a versatile and highly-programmable toolbox which can potentially be used for the autonomous sensing of dynamic events, such as biomolecular interactions. However, the experimental implementation of in silico circuit designs has been hindered by the problem of circuit leakage. Here, we systematically analyzed the sources and characteristics of various types of leakage in a split proximity circuit which was engineered to spatially probe for target sites held within close proximity. Direct evidence that 3′-truncated oligonucleotides were the major impurity contributing to circuit leakage was presented. More importantly, a unique strategy of translocating a single nucleotide between domains, termed ‘inter-domain bridging’, was introduced to eliminate toehold-independent leakages while enhancing the strand displacement kinetics across a three-way junction. We also analyzed the dynamics of intermediate complexes involved in the circuit computation in order to define the working range of domain lengths for the reporter toehold and association region respectively. The final circuit design was successfully implemented on a model streptavidin-biotin system and demonstrated to be robust against both circuit leakage and biological interferences. We anticipate that this simple signal transduction strategy can be used to probe for diverse biomolecular interactions when used in conjunction with specific target recognition moieties. PMID:27207880

Fast frequency divider circuit using combinational logic

DOE Office of Scientific and Technical Information (OSTI.GOV)

Helinski, Ryan

The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the ROmore » by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.« less

FELERION: a new approach for leakage power reduction

NASA Astrophysics Data System (ADS)

R, Anjana; Somkuwar, Ajay

2014-12-01

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%-94% as compared to the conventional approach.

Mechanistic equivalent circuit modelling of a commercial polymer electrolyte membrane fuel cell

NASA Astrophysics Data System (ADS)

Giner-Sanz, J. J.; Ortega, E. M.; Pérez-Herranz, V.

2018-03-01

Electrochemical impedance spectroscopy (EIS) has been widely used in the fuel cell field since it allows deconvolving the different physic-chemical processes that affect the fuel cell performance. Typically, EIS spectra are modelled using electric equivalent circuits. In this work, EIS spectra of an individual cell of a commercial PEM fuel cell stack were obtained experimentally. The goal was to obtain a mechanistic electric equivalent circuit in order to model the experimental EIS spectra. A mechanistic electric equivalent circuit is a semiempirical modelling technique which is based on obtaining an equivalent circuit that does not only correctly fit the experimental spectra, but which elements have a mechanistic physical meaning. In order to obtain the aforementioned electric equivalent circuit, 12 different models with defined physical meanings were proposed. These equivalent circuits were fitted to the obtained EIS spectra. A 2 step selection process was performed. In the first step, a group of 4 circuits were preselected out of the initial list of 12, based on general fitting indicators as the determination coefficient and the fitted parameter uncertainty. In the second step, one of the 4 preselected circuits was selected on account of the consistency of the fitted parameter values with the physical meaning of each parameter.

Development, Integration and Testing of Automated Triggering Circuit for Hybrid DC Circuit Breaker

NASA Astrophysics Data System (ADS)

Kanabar, Deven; Roy, Swati; Dodiya, Chiragkumar; Pradhan, Subrata

2017-04-01

A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed.

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Spike timing precision of neuronal circuits.

PubMed

Kilinc, Deniz; Demir, Alper

2018-06-01

Spike timing is believed to be a key factor in sensory information encoding and computations performed by the neurons and neuronal circuits. However, the considerable noise and variability, arising from the inherently stochastic mechanisms that exist in the neurons and the synapses, degrade spike timing precision. Computational modeling can help decipher the mechanisms utilized by the neuronal circuits in order to regulate timing precision. In this paper, we utilize semi-analytical techniques, which were adapted from previously developed methods for electronic circuits, for the stochastic characterization of neuronal circuits. These techniques, which are orders of magnitude faster than traditional Monte Carlo type simulations, can be used to directly compute the spike timing jitter variance, power spectral densities, correlation functions, and other stochastic characterizations of neuronal circuit operation. We consider three distinct neuronal circuit motifs: Feedback inhibition, synaptic integration, and synaptic coupling. First, we show that both the spike timing precision and the energy efficiency of a spiking neuron are improved with feedback inhibition. We unveil the underlying mechanism through which this is achieved. Then, we demonstrate that a neuron can improve on the timing precision of its synaptic inputs, coming from multiple sources, via synaptic integration: The phase of the output spikes of the integrator neuron has the same variance as that of the sample average of the phases of its inputs. Finally, we reveal that weak synaptic coupling among neurons, in a fully connected network, enables them to behave like a single neuron with a larger membrane area, resulting in an improvement in the timing precision through cooperation.

Approximate circuits for increased reliability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hamlet, Jason R.; Mayo, Jackson R.

2015-08-18

Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the referencemore » circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.« less

Robust Design of Biological Circuits: Evolutionary Systems Biology Approach

PubMed Central

Chen, Bor-Sen; Hsu, Chih-Yuan; Liou, Jing-Jia

2011-01-01

Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are given in silico with the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise. PMID:22187523

Robust design of biological circuits: evolutionary systems biology approach.

PubMed

Chen, Bor-Sen; Hsu, Chih-Yuan; Liou, Jing-Jia

2011-01-01

Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are given in silico with the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise.

Processing circuit with asymmetry corrector and convolutional encoder for digital data

NASA Technical Reports Server (NTRS)

Pfiffner, Harold J. (Inventor)

1987-01-01

A processing circuit is provided for correcting for input parameter variations, such as data and clock signal symmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit. The corrector circuit further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit so that encoded data may be furnished to a modulator at a high data rate for transmission.

Waveshaping electronic circuit

NASA Technical Reports Server (NTRS)

Harper, T. P.

1971-01-01

Circuit provides output signal with sinusoidal function in response to bipolar transition of input signal. Instantaneous transition shapes into linear rate of change and linear rate of change shapes into sinusoidal rate of change. Circuit contains only active components; therefore, compatibility with integrated circuit techniques is assured.

Design of low loss helix circuits for interference fitted and brazed circuits

NASA Technical Reports Server (NTRS)

Jacquez, A.

1983-01-01

The RF loss properties and thermal capability of brazed helix circuits and interference fitted circuits were evaluated. The objective was to produce design circuits with minimum RF loss and maximum heat transfer. These circuits were to be designed to operate at 10 kV and at 20 GHz using a gamma a approximately equal to 1.0. This represents a circuit diameter of only 0.75 millimeters. The fabrication of this size circuit and the 0.48 millimeter high support rods required considerable refinements in the assembly techniques and fixtures used on lower frequency circuits. The transition from the helices to the waveguide was designed and the circuits were matched from 20 to 40 GHz since the helix design is a broad band circuit and at a gamma a of 1.0 will operate over this band. The loss measurement was a transmission measurement and therefore had two such transitions. This resulting double-ended match required tuning elements to achieve the broad band match and external E-H tuners at each end to optimize the match for each frequency where the loss measurement was made. The test method used was a substitution method where the test fixture was replaced by a calibrated attenuator.

Quasi-Linear Circuit

NASA Technical Reports Server (NTRS)

Bradley, William; Bird, Ross; Eldred, Dennis; Zook, Jon; Knowles, Gareth

2013-01-01

This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output

Traveling-Wave Tube Cold-Test Circuit Optimization Using CST MICROWAVE STUDIO

NASA Technical Reports Server (NTRS)

Chevalier, Christine T.; Kory, Carol L.; Wilson, Jeffrey D.; Wintucky, Edwin G.; Dayton, James A., Jr.

2003-01-01

The internal optimizer of CST MICROWAVE STUDIO (MWS) was used along with an application-specific Visual Basic for Applications (VBA) script to develop a method to optimize traveling-wave tube (TWT) cold-test circuit performance. The optimization procedure allows simultaneous optimization of circuit specifications including on-axis interaction impedance, bandwidth or geometric limitations. The application of Microwave Studio to TWT cold-test circuit optimization is described.

Electrical circuit modeling and analysis of microwave acoustic interaction with biological tissues.

PubMed

Gao, Fei; Zheng, Qian; Zheng, Yuanjin

2014-05-01

Numerical study of microwave imaging and microwave-induced thermoacoustic imaging utilizes finite difference time domain (FDTD) analysis for simulation of microwave and acoustic interaction with biological tissues, which is time consuming due to complex grid-segmentation and numerous calculations, not straightforward due to no analytical solution and physical explanation, and incompatible with hardware development requiring circuit simulator such as SPICE. In this paper, instead of conventional FDTD numerical simulation, an equivalent electrical circuit model is proposed to model the microwave acoustic interaction with biological tissues for fast simulation and quantitative analysis in both one and two dimensions (2D). The equivalent circuit of ideal point-like tissue for microwave-acoustic interaction is proposed including transmission line, voltage-controlled current source, envelop detector, and resistor-inductor-capacitor (RLC) network, to model the microwave scattering, thermal expansion, and acoustic generation. Based on which, two-port network of the point-like tissue is built and characterized using pseudo S-parameters and transducer gain. Two dimensional circuit network including acoustic scatterer and acoustic channel is also constructed to model the 2D spatial information and acoustic scattering effect in heterogeneous medium. Both FDTD simulation, circuit simulation, and experimental measurement are performed to compare the results in terms of time domain, frequency domain, and pseudo S-parameters characterization. 2D circuit network simulation is also performed under different scenarios including different sizes of tumors and the effect of acoustic scatterer. The proposed circuit model of microwave acoustic interaction with biological tissue could give good agreement with FDTD simulated and experimental measured results. The pseudo S-parameters and characteristic gain could globally evaluate the performance of tumor detection. The 2D circuit network

Nucleic acids for the rational design of reaction circuits.

PubMed

Padirac, Adrien; Fujii, Teruo; Rondelez, Yannick

2013-08-01

Nucleic acid-based circuits are rationally designed in vitro assemblies that can perform complex preencoded programs. They can be used to mimic in silico computations. Recent works emphasized the modularity and robustness of these circuits, which allow their scaling-up. Another new development has led to dynamic, time-responsive systems that can display emergent behaviors like oscillations. These are closely related to biological architectures and provide an in vitro model of in vivo information processing. Nucleic acid circuits have already been used to handle various processes for technological or biotechnological purposes. Future applications of these chemical smart systems will benefit from the rapidly growing ability to design, construct, and model nucleic acid circuits of increasing size. Copyright © 2012 Elsevier Ltd. All rights reserved.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Effect of the nand p-type Si(100) substrates with a SiC buffer layer on the growth mechanism and structure of epitaxial layers of semipolar AlN and GaN

NASA Astrophysics Data System (ADS)

Bessolov, V. N.; Grashchenko, A. S.; Konenkova, E. V.; Myasoedov, A. V.; Osipov, A. V.; Red'kov, A. V.; Rodin, S. N.; Rubets, V. P.; Kukushkin, S. A.

2015-10-01

A new effect of the n-and p-type doping of the Si(100) substrate with a SiC film on the growth mechanism and structure of AlN and GaN epitaxial layers has been revealed. It has been experimentally shown that the mechanism of AlN and GaN layer growth on the surface of a SiC layer synthesized by substituting atoms on n- and p-Si substrates is fundamentally different. It has been found that semipolar AlN and GaN layers on the SiC/Si(100) surface grow in the epitaxial and polycrystalline structures on p-Si and n-Si substrates, respectively. A new method for synthesizing epitaxial semipolar AlN and GaN layers by chloride-hydride epitaxy on silicon substrates has been proposed.

Sequential circuit design for radiation hardened multiple voltage integrated circuits

DOEpatents

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Piezoelectric drive circuit

DOEpatents

Treu, Jr., Charles A.

1999-08-31

A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.

30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-07-01

... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

A neural command circuit for grooming movement control.

PubMed

Hampel, Stefanie; Franconville, Romain; Simpson, Julie H; Seeds, Andrew M

2015-09-07

Animals perform many stereotyped movements, but how nervous systems are organized for controlling specific movements remains unclear. Here we use anatomical, optogenetic, behavioral, and physiological techniques to identify a circuit in Drosophila melanogaster that can elicit stereotyped leg movements that groom the antennae. Mechanosensory chordotonal neurons detect displacements of the antennae and excite three different classes of functionally connected interneurons, which include two classes of brain interneurons and different parallel descending neurons. This multilayered circuit is organized such that neurons within each layer are sufficient to specifically elicit antennal grooming. However, we find differences in the durations of antennal grooming elicited by neurons in the different layers, suggesting that the circuit is organized to both command antennal grooming and control its duration. As similar features underlie stimulus-induced movements in other animals, we infer the possibility of a common circuit organization for movement control that can be dissected in Drosophila.

Selection of airgap layers for circuit timing optimization

NASA Astrophysics Data System (ADS)

Hyun, Daijoon; Shin, Youngsoo

2017-03-01

Airgap refers to a void formed in place of some inter metal dielectric (IMD). It brings about the reduction in coupling capacitance, which may contribute to improvement in circuit performance. We introduce two problems in this context. First is to choose the layers, where airgap should be applied, in such a way that total negative slack (TNS) is minimized for a given circuit. This has been motivated by the fact that best choice of airgap layers is different for different circuits. An algorithm is proposed to solve the problem, and is assessed against a naive approach in which airgap layers are simply fixed; additional 8% TNS reduction, on average of a few test circuits, is demonstrated. In the second problem, some wires of critical paths that are on non-airgap layers are reassigned to airgap layers such that TNS is further reduced; additional 3 to 14% of TNS reduction is observed.

Variability-aware double-patterning layout optimization for analog circuits

NASA Astrophysics Data System (ADS)

Li, Yongfu; Perez, Valerio; Tripathi, Vikas; Lee, Zhao Chuan; Tseng, I.-Lun; Ong, Jonathan Yoong Seang

2018-03-01

The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit's mismatch. To overcome the problem and improve the turn-around time, we proposed our smart "anchoring" placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

A Common Function of Basal Ganglia-Cortical Circuits Subserving Speed in Both Motor and Cognitive Domains.

PubMed

Hanakawa, Takashi; Goldfine, Andrew M; Hallett, Mark

2017-01-01

Distinct regions of the frontal cortex connect with their basal ganglia and thalamic counterparts, constituting largely segregated basal ganglia-thalamo-cortical (BTC) circuits. However, any common role of the BTC circuits in different behavioral domains remains unclear. Indeed, whether dysfunctional motor and cognitive BTC circuits are responsible for motor slowing and cognitive slowing, respectively, in Parkinson's disease (PD) is a matter of debate. Here, we used an effortful behavioral paradigm in which the effects of task rate on accuracy were tested in movement, imagery, and calculation tasks in humans. Using nonlinear fitting, we separated baseline accuracy ( A base ) and "agility" (ability to function quickly) components of performance in healthy participants and then confirmed reduced agility and preserved A base for the three tasks in PD. Using functional magnetic resonance imaging (fMRI) and diffusion tractography, we explored the neural substrates underlying speeded performance of the three tasks in healthy participants, suggesting the involvement of distinct BTC circuits in cognitive and motor agility. Language and motor BTC circuits were specifically active during speeded performance of the calculation and movement tasks, respectively, whereas premotor BTC circuits revealed activity for speeded performance of all tasks. Finally, PD showed reduced task rate-correlated activity in the language BTC circuits for speeded calculation, in the premotor BTC circuit for speeded imagery, and in the motor BTC circuits for speeded movement, as compared with controls. The present study casts light on the anatomo-functional organization of the BTC circuits and their parallel roles in invigorating movement and cognition through a function of dopamine.

A Common Function of Basal Ganglia-Cortical Circuits Subserving Speed in Both Motor and Cognitive Domains

PubMed Central

2017-01-01

Abstract Distinct regions of the frontal cortex connect with their basal ganglia and thalamic counterparts, constituting largely segregated basal ganglia-thalamo-cortical (BTC) circuits. However, any common role of the BTC circuits in different behavioral domains remains unclear. Indeed, whether dysfunctional motor and cognitive BTC circuits are responsible for motor slowing and cognitive slowing, respectively, in Parkinson’s disease (PD) is a matter of debate. Here, we used an effortful behavioral paradigm in which the effects of task rate on accuracy were tested in movement, imagery, and calculation tasks in humans. Using nonlinear fitting, we separated baseline accuracy (Abase) and “agility” (ability to function quickly) components of performance in healthy participants and then confirmed reduced agility and preserved Abase for the three tasks in PD. Using functional magnetic resonance imaging (fMRI) and diffusion tractography, we explored the neural substrates underlying speeded performance of the three tasks in healthy participants, suggesting the involvement of distinct BTC circuits in cognitive and motor agility. Language and motor BTC circuits were specifically active during speeded performance of the calculation and movement tasks, respectively, whereas premotor BTC circuits revealed activity for speeded performance of all tasks. Finally, PD showed reduced task rate-correlated activity in the language BTC circuits for speeded calculation, in the premotor BTC circuit for speeded imagery, and in the motor BTC circuits for speeded movement, as compared with controls. The present study casts light on the anatomo-functional organization of the BTC circuits and their parallel roles in invigorating movement and cognition through a function of dopamine. PMID:29379873

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

GATING CIRCUITS

DOEpatents

Merrill, L.C.

1958-10-14

Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

Flexible Circuits

NASA Technical Reports Server (NTRS)

1986-01-01

Adflex Solutions, Inc.'s flexible circuits may be molded to the shape of a chassis for bulk reduction. Particularly valuable when circuitry must be moved. They are produced by combining a plastic film, a metallic conductor and an adhesive. One adhesive, LARC-TPI, developed by the Langley Research Center, is a thermoplastic polyimide resin used to produce laminates by Rogers Corporation. It can be processed at a lower temperature, has good moisture resistance and excellent adherence. It is used to bond film to copper foil conductor materials in flexible circuits. The circuits have both aerospace and commercial applications.

Piezoelectric drive circuit

DOEpatents

Treu, C.A. Jr.

1999-08-31

A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

Targeting circuits

PubMed Central

Rajasethupathy, Priyamvada; Ferenczi, Emily; Deisseroth, Karl

2017-01-01

Current optogenetic methodology enables precise inhibition or excitation of neural circuits, spanning timescales as needed from the acute (milliseconds) to the chronic (many days or more), for experimental modulation of network activity and animal behavior. Such broad temporal versatility, unique to optogenetic control, is particularly powerful when combined with brain activity measurements that span both acute and chronic timescales as well. This enables, for instance, the study of adaptive circuit dynamics across the intact brain, and tuning interventions to match activity patterns naturally observed during behavior in the same individual. Although the impact of this approach has been greater on basic research than on clinical translation, it is natural to ask if specific neural circuit activity patterns discovered to be involved in controlling adaptive or maladaptive behaviors could become targets for treatment of neuropsychiatric diseases. Here we consider the landscape of such ideas related to therapeutic targeting of circuit dynamics, taking note of developments not only in optical but also in ultrasonic, magnetic, and thermal methods. We note the recent emergence of first-in-kind optogenetically-guided clinical outcomes, as well as opportunities related to the integration of interventions and readouts spanning diverse circuit-physiology, molecular, and behavioral modalities. PMID:27104976

Reconfigurable electro-optical directed-logic circuit using carrier-depletion micro-ring resonators.

PubMed

Qiu, Ciyuan; Gao, Weilu; Soref, Richard; Robinson, Jacob T; Xu, Qianfan

2014-12-15

Here we demonstrate a reconfigurable electro-optical directed-logic circuit based on a regular array of integrated optical switches. Each 1×1 optical switch consists of a micro-ring resonator with an embedded lateral p-n junction and a micro-heater. We achieve high-speed on-off switching by applying electrical logic signals to the p-n junction. We can configure the operation mode of each switch by thermal tuning the resonance wavelength. The result is an integrated optical circuit that can be reconfigured to perform any combinational logic operation. As a proof-of-principle, we fabricated a multi-spectral directed-logic circuit based on a fourfold array of switches and showed that this circuit can be reconfigured to perform arbitrary two-input logic functions with speeds up to 3  GB/s.

Glass Fibers for Printed Circuit Boards

NASA Astrophysics Data System (ADS)

Longobardo, Anthony V.

Fiberglass imparts numerous positive benefits to modern printed circuit boards. Reinforced laminate composites have an excellent cost-performance relationship that makes sense for most applications. At the leading edge of the technology, new glass fibers with improved properties, in combination with the best resin systems available, are able to meet very challenging performance, cost, and regulatory demands while remaining manufacturable.

Applying analog integrated circuits for HERO protection

NASA Technical Reports Server (NTRS)

Willis, Kenneth E.; Blachowski, Thomas J.

1994-01-01

One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

Monolithically integrated bacteriorhodopsin/semiconductor opto-electronic integrated circuit for a bio-photoreceiver.

PubMed

Xu, J; Bhattacharya, P; Váró, G

2004-03-15

The light-sensitive protein, bacteriorhodopsin (BR), is monolithically integrated with an InP-based amplifier circuit to realize a novel opto-electronic integrated circuit (OEIC) which performs as a high-speed photoreceiver. The circuit is realized by epitaxial growth of the field-effect transistors, currently used semiconductor device and circuit fabrication techniques, and selective area BR electro-deposition. The integrated photoreceiver has a responsivity of 175 V/W and linear photoresponse, with a dynamic range of 16 dB, with 594 nm photoexcitation. The dynamics of the photochemical cycle of BR has also been modeled and a proposed equivalent circuit simulates the measured BR photoresponse with good agreement.

General purpose computer programs for numerically analyzing linear ac electrical and electronic circuits for steady-state conditions

NASA Technical Reports Server (NTRS)

Egebrecht, R. A.; Thorbjornsen, A. R.

1967-01-01

Digital computer programs determine steady-state performance characteristics of active and passive linear circuits. The ac analysis program solves the basic circuit parameters. The compiler program solves these circuit parameters and in addition provides a more versatile program by allowing the user to perform mathematical and logical operations.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks.

PubMed

Chen, Huan-Yuan; Chen, Chih-Chang; Hwang, Wen-Jyi

2017-09-28

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

PubMed Central

Chen, Huan-Yuan; Chen, Chih-Chang

2017-01-01

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

[Shunt and short circuit].

PubMed

Rangel-Abundis, Alberto

2006-01-01

Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

Characteristic and intermingled neocortical circuits encode different visual object discriminations.

PubMed

Zhang, Guo-Rong; Zhao, Hua; Cook, Nathan; Svestka, Michael; Choi, Eui M; Jan, Mary; Cook, Robert G; Geller, Alfred I

2017-07-28

Synaptic plasticity and neural network theories hypothesize that the essential information for advanced cognitive tasks is encoded in specific circuits and neurons within distributed neocortical networks. However, these circuits are incompletely characterized, and we do not know if a specific discrimination is encoded in characteristic circuits among multiple animals. Here, we determined the spatial distribution of active neurons for a circuit that encodes some of the essential information for a cognitive task. We genetically activated protein kinase C pathways in several hundred spatially-grouped glutamatergic and GABAergic neurons in rat postrhinal cortex, a multimodal associative area that is part of a distributed circuit that encodes visual object discriminations. We previously established that this intervention enhances accuracy for specific discriminations. Moreover, the genetically-modified, local circuit in POR cortex encodes some of the essential information, and this local circuit is preferentially activated during performance, as shown by activity-dependent gene imaging. Here, we mapped the positions of the active neurons, which revealed that two image sets are encoded in characteristic and different circuits. While characteristic circuits are known to process sensory information, in sensory areas, this is the first demonstration that characteristic circuits encode specific discriminations, in a multimodal associative area. Further, the circuits encoding the two image sets are intermingled, and likely overlapping, enabling efficient encoding. Consistent with reconsolidation theories, intermingled and overlapping encoding could facilitate formation of associations between related discriminations, including visually similar discriminations or discriminations learned at the same time or place. Copyright © 2017 Elsevier B.V. All rights reserved.

Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

49 CFR 236.5 - Design of control circuits on closed circuit principle.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Design of control circuits on closed circuit... THE INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on...

Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

NASA Astrophysics Data System (ADS)

Bahl, Inder J.

Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

Single-server blind quantum computation with quantum circuit model

NASA Astrophysics Data System (ADS)

Zhang, Xiaoqian; Weng, Jian; Li, Xiaochun; Luo, Weiqi; Tan, Xiaoqing; Song, Tingting

2018-06-01

Blind quantum computation (BQC) enables the client, who has few quantum technologies, to delegate her quantum computation to a server, who has strong quantum computabilities and learns nothing about the client's quantum inputs, outputs and algorithms. In this article, we propose a single-server BQC protocol with quantum circuit model by replacing any quantum gate with the combination of rotation operators. The trap quantum circuits are introduced, together with the combination of rotation operators, such that the server is unknown about quantum algorithms. The client only needs to perform operations X and Z, while the server honestly performs rotation operators.

MULTIPLIER CIRCUIT

DOEpatents

Thomas, R.E.

1959-01-20

An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Remote reset circuit

DOEpatents

Gritzo, Russell E.

1987-01-01

A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

NASA Astrophysics Data System (ADS)

Mallick, S.; Kar, R.; Mandal, D.; Ghoshal, S. P.

2016-07-01

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors' sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.

Dynamic performance of maximum power point tracking circuits using sinusoidal extremum seeking control for photovoltaic generation

NASA Astrophysics Data System (ADS)

Leyva, R.; Artillan, P.; Cabal, C.; Estibals, B.; Alonso, C.

2011-04-01

The article studies the dynamic performance of a family of maximum power point tracking circuits used for photovoltaic generation. It revisits the sinusoidal extremum seeking control (ESC) technique which can be considered as a particular subgroup of the Perturb and Observe algorithms. The sinusoidal ESC technique consists of adding a small sinusoidal disturbance to the input and processing the perturbed output to drive the operating point at its maximum. The output processing involves a synchronous multiplication and a filtering stage. The filter instance determines the dynamic performance of the MPPT based on sinusoidal ESC principle. The approach uses the well-known root-locus method to give insight about damping degree and settlement time of maximum-seeking waveforms. This article shows the transient waveforms in three different filter instances to illustrate the approach. Finally, an experimental prototype corroborates the dynamic analysis.

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

Comparison of modified driver circuit and capacitor-transfer circuit in longitudinally excited N2 laser.

PubMed

Uno, Kazuyuki; Akitsu, Tetsuya; Nakamura, Kenshi; Jitsuno, Takahisa

2013-04-01

We developed a modified driver circuit composed of a capacitance and a spark gap, called a direct-drive circuit, for a longitudinally excited gas laser. The direct-drive circuit uses a large discharge impedance caused by a long discharge length of the longitudinal excitation scheme and eliminates the buffer capacitance used in the traditional capacitor-transfer circuit. We compared the direct-drive circuit and the capacitor-transfer circuit in a longitudinally excited N2 laser (wavelength: 337 nm). Producing high output energy with the capacitor-transfer circuit requires a large storage capacitance and a discharge tube with optimum dimensions (an inner diameter of 4 mm and a length of 10 cm in this work); in contrast, the direct-drive circuit requires a high breakdown voltage, achieved with a small storage capacitance and a large discharge tube. Additionally, for the same input energy of 792 mJ, the maximum output energy of the capacitor-transfer circuit was 174.2 μJ, and that of the direct-drive circuit was 344.7 μJ.

Separating OR, SUM, and XOR Circuits.

PubMed

Find, Magnus; Göös, Mika; Järvisalo, Matti; Kaski, Petteri; Koivisto, Mikko; Korhonen, Janne H

2016-08-01

Given a boolean n × n matrix A we consider arithmetic circuits for computing the transformation x ↦ Ax over different semirings. Namely, we study three circuit models: monotone OR-circuits, monotone SUM-circuits (addition of non-negative integers), and non-monotone XOR-circuits (addition modulo 2). Our focus is on separating OR-circuits from the two other models in terms of circuit complexity: We show how to obtain matrices that admit OR-circuits of size O ( n ), but require SUM-circuits of size Ω( n 3/2 /log 2 n ).We consider the task of rewriting a given OR-circuit as a XOR-circuit and prove that any subquadratic-time algorithm for this task violates the strong exponential time hypothesis.

CIRCUITS FOR CURRENT MEASUREMENTS

DOEpatents

Cox, R.J.

1958-11-01

Circuits are presented for measurement of a logarithmic scale of current flowing in a high impedance. In one form of the invention the disclosed circuit is in combination with an ionization chamber to measure lonization current. The particular circuit arrangement lncludes a vacuum tube having at least one grid, an ionization chamber connected in series with a high voltage source and the grid of the vacuum tube, and a d-c amplifier feedback circuit. As the ionization chamber current passes between the grid and cathode of the tube, the feedback circuit acts to stabilize the anode current, and the feedback voltage is a measure of the logaritbm of the ionization current.

Method of determining the open circuit voltage of a battery in a closed circuit

DOEpatents

Brown, William E.

1980-01-01

The open circuit voltage of a battery which is connected in a closed circuit is determined without breaking the circuit or causing voltage upsets therein. The closed circuit voltage across the battery and the current flowing through it are determined under normal load and then a fractional change is made in the load and the new current and voltage values determined. The open circuit voltage is then calculated, according to known principles, from the two sets of values.

Selective Manipulation of Neural Circuits.

PubMed

Park, Hong Geun; Carmel, Jason B

2016-04-01

Unraveling the complex network of neural circuits that form the nervous system demands tools that can manipulate specific circuits. The recent evolution of genetic tools to target neural circuits allows an unprecedented precision in elucidating their function. Here we describe two general approaches for achieving circuit specificity. The first uses the genetic identity of a cell, such as a transcription factor unique to a circuit, to drive expression of a molecule that can manipulate cell function. The second uses the spatial connectivity of a circuit to achieve specificity: one genetic element is introduced at the origin of a circuit and the other at its termination. When the two genetic elements combine within a neuron, they can alter its function. These two general approaches can be combined to allow manipulation of neurons with a specific genetic identity by introducing a regulatory gene into the origin or termination of the circuit. We consider the advantages and disadvantages of both these general approaches with regard to specificity and efficacy of the manipulations. We also review the genetic techniques that allow gain- and loss-of-function within specific neural circuits. These approaches introduce light-sensitive channels (optogenetic) or drug sensitive channels (chemogenetic) into neurons that form specific circuits. We compare these tools with others developed for circuit-specific manipulation and describe the advantages of each. Finally, we discuss how these tools might be applied for identification of the neural circuits that mediate behavior and for repair of neural connections.

Synthetic analog and digital circuits for cellular computation and memory.

PubMed

Purcell, Oliver; Lu, Timothy K

2014-10-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene networks that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. Copyright © 2014 The Authors. Published by Elsevier Ltd.. All rights reserved.

Paper-based silver-nanowire electronic circuits with outstanding electrical conductivity and extreme bending stability.

PubMed

Huang, Gui-Wen; Xiao, Hong-Mei; Fu, Shao-Yun

2014-08-07

Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Remote reset circuit

DOEpatents

Gritzo, R.E.

1985-09-12

A remote reset circuit acts as a stand-along monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients. 4 figs.

Bridging ultrahigh-Q devices and photonic circuits

NASA Astrophysics Data System (ADS)

Yang, Ki Youl; Oh, Dong Yoon; Lee, Seung Hoon; Yang, Qi-Fan; Yi, Xu; Shen, Boqiang; Wang, Heming; Vahala, Kerry

2018-05-01

Optical microresonators are essential to a broad range of technologies and scientific disciplines. However, many of their applications rely on discrete devices to attain challenging combinations of ultra-low-loss performance (ultrahigh Q) and resonator design requirements. This prevents access to scalable fabrication methods for photonic integration and lithographic feature control. Indeed, finding a microfabrication bridge that connects ultrahigh-Q device functions with photonic circuits is a priority of the microcavity field. Here, an integrated resonator having a record Q factor over 200 million is presented. Its ultra-low-loss and flexible cavity design brings performance to integrated systems that has been the exclusive domain of discrete silica and crystalline microcavity devices. Two distinctly different devices are demonstrated: soliton sources with electronic repetition rates and high-coherence/low-threshold Brillouin lasers. This multi-device capability and performance from a single integrated cavity platform represents a critical advance for future photonic circuits and systems.

A Circuit to Demonstrate Phase Relationships in "RLC" Circuits

ERIC Educational Resources Information Center

Sokol, P. E.; Warren, G.; Zheng, B.; Smith, P.

2013-01-01

We have developed a circuit to demonstrate the phase relationships between resistive and reactive elements in series "RLC" circuits. We utilize a differential amplifier to allow the phases of the three elements and the current to be simultaneously displayed on an inexpensive four channel oscilloscope. We have included a novel circuit…

Design and Characterization of DNA Strand-Displacement Circuits in Serum-Supplemented Cell Medium.

PubMed

Fern, Joshua; Schulman, Rebecca

2017-09-15

The functional stability and lifetimes of synthetic molecular circuits in biological environments are important for long-term, stable sensors or controllers of cell or tissue behavior. DNA-based molecular circuits, in particular DNA strand-displacement circuits, provide simple and effective biocompatible control mechanisms and sensors, but are vulnerable to digestion by nucleases present in living tissues and serum-supplemented cell culture. The stability of double-stranded and single-stranded DNA circuit components in serum-supplemented cell medium and the corresponding effect of nuclease-mediated degradation on circuit performance were characterized to determine the major routes of degradation and DNA strand-displacement circuit failure. Simple circuit design choices, such as the use of 5' toeholds within the DNA complexes used as reactants in the strand-displacement reactions and the termination of single-stranded components with DNA hairpin domains at the 3' termini, significantly increase the functional lifetime of the circuit components in the presence of nucleases. Simulations of multireaction circuits, guided by the experimentally measured operation of single-reaction circuits, enable predictive realization of multilayer and competitive-reaction circuit behavior. Together, these results provide a basic route to increased DNA circuit stability in cell culture environments.

Method and Circuit for Injecting a Precise Amount of Charge onto a Circuit Node

NASA Technical Reports Server (NTRS)

Hancock, Bruce R. (Inventor)

2016-01-01

A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

NASA Astrophysics Data System (ADS)

Maity, Subir Kr.; Pandit, Soumya

2017-11-01

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain-frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.

Multiplier Architecture for Coding Circuits

NASA Technical Reports Server (NTRS)

Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.

Perspective on Flipping Circuits I

ERIC Educational Resources Information Center

Kim, Gloria J.; Patrick, Erin E.; Srivastava, Ramakant; Law, Mark E.

2014-01-01

A flipped-classroom approach was implemented in a Circuits I class for electrical and computer engineering majors to lower its high attrition and failure rate. Students were asked to watch online lectures and then come to class prepared to work problems in small groups of four. The attitude, retention, and performance of students in the flipped…

Electrical short circuit and current overload tests on aircraft wiring

NASA Technical Reports Server (NTRS)

Cahill, Patricia

1995-01-01

The findings of electrical short circuit and current overload tests performed on commercial aircraft wiring are presented. A series of bench-scale tests were conducted to evaluate circuit breaker response to overcurrent and to determine if the wire showed any visible signs of thermal degradation due to overcurrent. Three types of wire used in commercial aircraft were evaluated: MIL-W-22759/34 (150 C rated), MIL-W-81381/12 (200 C rated), and BMS 1360 (260 C rated). A second series of tests evaluated circuit breaker response to short circuits and ticking faults. These tests were also meant to determine if the three test wires behaved differently under these conditions and if a short circuit or ticking fault could start a fire. It is concluded that circuit breakers provided reliable overcurrent protection. Circuit breakers may not protect wire from ticking faults but can protect wire from direct shorts. These tests indicated that the appearance of a wire subjected to a current that totally degrades the insulation looks identical to a wire subjected to a fire; however the 'fire exposed' conductor was more brittle than the conductor degraded by overcurrent. Preliminary testing indicates that direct short circuits are not likely to start a fire. Preliminary testing indicated that direct short circuits do not erode insulation and conductor to the extent that ticking faults did. Circuit breakers may not safeguard against the ignition of flammable materials by ticking faults. The flammability of materials near ticking faults is far more important than the rating of the wire insulation material.

Multi-Layer E-Textile Circuits

NASA Technical Reports Server (NTRS)

Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

2012-01-01

Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

X-ray effects on pacemaker type circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blamires, N.G.; Myatt, J.

1982-03-01

Queries have been raised concerning the potential hazards of X-ray irradiation on patients using the new generation of heart pacemakers based on digital circuitry. The present study was undertaken to provide some answers to these queries. The work was conducted in two parts. First, a literature search was done and, second, circuits using current state of the art digital technology were irradiated with X-rays. Watch circuits were chosen because of their availability and built-in facilities by which their function could be tested. Doses up to 330 rads were administered to them using energies of 46, 114, and 141 KeV. Themore » conclusion drawn from both parts of the study was that X-rays used for diagnostic purposes were unlikely to affect the performance of this type of circuit in any way. It was accepted that for therapeutic purposes doses far in excess of this are administered and circuit malfunctions are likely to occur. To assess the probability of a digital pacemaker malfunctioning, samples of that particular type would have to be irradiated at the relevant dose.« less

Automatic circuit interrupter

NASA Technical Reports Server (NTRS)

Dwinell, W. S.

1979-01-01

In technique, voice circuits connecting crew's cabin to launch station through umbilical connector disconnect automatically unused, or deadened portion of circuits immediately after vehicle is launched, eliminating possibility that unused wiring interferes with voice communications inside vehicle or need for manual cutoff switch and its associated wiring. Technique is applied to other types of electrical actuation circuits, also launch of mapped vehicles, such as balloons, submarines, test sleds, and test chambers-all requiring assistance of ground crew.

Silica-on-silicon waveguide quantum circuits.

PubMed

Politi, Alberto; Cryan, Martin J; Rarity, John G; Yu, Siyuan; O'Brien, Jeremy L

2008-05-02

Quantum technologies based on photons will likely require an integrated optics architecture for improved performance, miniaturization, and scalability. We demonstrate high-fidelity silica-on-silicon integrated optical realizations of key quantum photonic circuits, including two-photon quantum interference with a visibility of 94.8 +/- 0.5%; a controlled-NOT gate with an average logical basis fidelity of 94.3 +/- 0.2%; and a path-entangled state of two photons with fidelity of >92%. These results show that it is possible to directly "write" sophisticated photonic quantum circuits onto a silicon chip, which will be of benefit to future quantum technologies based on photons, including information processing, communication, metrology, and lithography, as well as the fundamental science of quantum optics.

Proposal of ultra-compact NAND/NOR/XNOR all-optical logic gates based on a nonlinear 3x1 multimode interference

NASA Astrophysics Data System (ADS)

Tajaldini, Mehdi; Mat Jafri, M. Z.

2014-05-01

We present a highly miniaturized multimode interference (MMI) coupler based on nonlinear modal propagation analysis (NMPA) method as a novel design method and potential application for optical NAND, NOR and XNOR logic gates for Boolean logic signal processing devices. Crystalline polydiacetylene is used to allow the appearances of nonlinear effects in low input intensities and ultra- short length to control the MMI coupler as an active device to access light switching due to its high nonlinear susceptibility. We consider a 10x33 μm2 MMI structure with three inputs and one output. Notably, the access facets are single-mode waveguides with sub-micron width. The center input contributes to control the induced light propagation in MMI by intensity variation whereas others could be launched by particular intensity when they are ON and 0 in OFF. Output intensity is analyzed in various sets of inputs to show the capability of Boolean logic gates, the contrast between ON and OFF is calculated on mentioned gates to present the efficiency. Good operation in low intensity and highly miniaturized MMI coupler is observed. Furthermore, nonlinear effects could be realized through the modal interferences. The issue of high insertion loss is addressed with a 3×3 upgraded coupler. Furthermore, the main significant aspect of this paper is simulating an MMI coupler that is launched by three nonlinear inputs, simultaneously, whereas last presents have never studied more than one input in nonlinear regimes.

Exchange circuits for FASTBUS slaves

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bratskii, A.A.; Matseev, M.Y.; Rybakov, V.G.

1985-09-01

This paper describes general-purpose circuits for FASTBUS interfacing of the functional part of a slave device. The circuits contain buffered receivers and transmitters, addressrecognition and data-transfer logic, and the required control/status registers. The described circuits are implemented with series-K500 integrated circuits.

On Polymorphic Circuits and Their Design Using Evolutionary Algorithms

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo; Keymeulen, Didier; Lohn, Jason; Clancy, Daniel (Technical Monitor)

2002-01-01

This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.

A novel prediction method about single components of analog circuits based on complex field modeling.

PubMed

Zhou, Jingyu; Tian, Shulin; Yang, Chenglin

2014-01-01

Few researches pay attention to prediction about analog circuits. The few methods lack the correlation with circuit analysis during extracting and calculating features so that FI (fault indicator) calculation often lack rationality, thus affecting prognostic performance. To solve the above problem, this paper proposes a novel prediction method about single components of analog circuits based on complex field modeling. Aiming at the feature that faults of single components hold the largest number in analog circuits, the method starts with circuit structure, analyzes transfer function of circuits, and implements complex field modeling. Then, by an established parameter scanning model related to complex field, it analyzes the relationship between parameter variation and degeneration of single components in the model in order to obtain a more reasonable FI feature set via calculation. According to the obtained FI feature set, it establishes a novel model about degeneration trend of analog circuits' single components. At last, it uses particle filter (PF) to update parameters for the model and predicts remaining useful performance (RUP) of analog circuits' single components. Since calculation about the FI feature set is more reasonable, accuracy of prediction is improved to some extent. Finally, the foregoing conclusions are verified by experiments.

Design of Arithmetic Circuits for Complex Binary Number System

NASA Astrophysics Data System (ADS)

Jamil, Tariq

2011-08-01

Complex numbers play important role in various engineering applications. To represent these numbers efficiently for storage and manipulation, a (-1+j)-base complex binary number system (CBNS) has been proposed in the literature. In this paper, designs of nibble-size arithmetic circuits (adder, subtractor, multiplier, divider) have been presented. These circuits can be incorporated within von Neumann and associative dataflow processors to achieve higher performance in both sequential and parallel computing paradigms.

Latest Trends of Vacuum Circuit Breaker and Related Technologies

NASA Astrophysics Data System (ADS)

Kozono, Hideaki; Tanimizu, Toru

Vacuum Circuit Breakers (VCBs) have been widely used for medium voltage level, because of their performance: compact size, light weight, maintenance free operations and environment-friendly characteristics. They become most comfortable breakers for our needs from other breakers: oil, air, magnetic blast and gas. In this paper the history of vacuum, and latest trends of circuit breakers and related technologies are described, as well as merits or demerits of using vacuum technologies.

Superconducting flux flow digital circuits

DOEpatents

Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

1995-01-01

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

State-variable analysis of non-linear circuits with a desk computer

NASA Technical Reports Server (NTRS)

Cohen, E.

1981-01-01

State variable analysis was used to analyze the transient performance of non-linear circuits on a desk top computer. The non-linearities considered were not restricted to any circuit element. All that is required for analysis is the relationship defining each non-linearity be known in terms of points on a curve.

Weddings, Electric Circuits, and the Corner Grocery Store

NASA Astrophysics Data System (ADS)

Fischer, Mark

2001-10-01

When discussing electric circuits in most physics and physical science courses, students often struggle with the rules for adding resistors wired in series and in parallel. Traditionally, these rules are motivated by analogies to water pumped through pipes, analogies that are at least as unfamiliar to most students as electricity itself. The activities presented here model the behavior of series and parallel electric circuits by wedding receiving lines and grocery store checkout lanes respectively, two circumstances with which most students have had experience. The activity is easy to perform and can be done qualitatively or quantitatively, and can even be augmented to model more sophisticated circuits. Thus, the activity described is appropriate for basic physical science courses as well as majors courses and will engage students from middle school through college.

[Modeling and analysis of volume conduction based on field-circuit coupling].

PubMed

Tang, Zhide; Liu, Hailong; Xie, Xiaohui; Chen, Xiufa; Hou, Deming

2012-08-01

Numerical simulations of volume conduction can be used to analyze the process of energy transfer and explore the effects of some physical factors on energy transfer efficiency. We analyzed the 3D quasi-static electric field by the finite element method, and developed A 3D coupled field-circuit model of volume conduction basing on the coupling between the circuit and the electric field. The model includes a circuit simulation of the volume conduction to provide direct theoretical guidance for energy transfer optimization design. A field-circuit coupling model with circular cylinder electrodes was established on the platform of the software FEM3.5. Based on this, the effects of electrode cross section area, electrode distance and circuit parameters on the performance of volume conduction system were obtained, which provided a basis for optimized design of energy transfer efficiency.

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

NASA Technical Reports Server (NTRS)

Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

2000-01-01

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

Design and Characterization of DNA Strand-Displacement Circuits in Serum-Supplemented Cell Medium

DOE PAGES

Fern, Joshua; Schulman, Rebecca

2017-05-30

The functional stability and lifetimes of synthetic molecular circuits in biological environments are important for long-term, stable sensors or controllers of cell or tissue behavior. DNA-based molecular circuits, particularly DNA strand-displacement circuits, provide simple and effective biocompatible control mechanisms and sensors, but are vulnerable to digestion by nucleases present in living tissues and serum-supplemented cell culture. The stability of double-stranded and single-stranded DNA circuit components in serum-supplemented cell medium and the corresponding effect of nuclease-mediated degradation on circuit performance were characterized to determine the major routes of degradation and DNA strand-displacement circuit failure. Simple circuit design choices, such as themore » use of 5' toeholds within the DNA complexes used as reactants in the strand-displacement reactions and the termination of single-stranded components with DNA hairpin domains at the 3' termini, significantly increase the functional lifetime of the circuit components in the presence of nucleases. Furthermore, simulations of multireaction circuits, guided by the experimentally measured operation of single-reaction circuits, enable predictive realization of multilayer and competitive-reaction circuit behavior. Altogether, these results provide a basic route to increased DNA circuit stability in cell culture environments.« less

Design and Characterization of DNA Strand-Displacement Circuits in Serum-Supplemented Cell Medium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fern, Joshua; Schulman, Rebecca

The functional stability and lifetimes of synthetic molecular circuits in biological environments are important for long-term, stable sensors or controllers of cell or tissue behavior. DNA-based molecular circuits, particularly DNA strand-displacement circuits, provide simple and effective biocompatible control mechanisms and sensors, but are vulnerable to digestion by nucleases present in living tissues and serum-supplemented cell culture. The stability of double-stranded and single-stranded DNA circuit components in serum-supplemented cell medium and the corresponding effect of nuclease-mediated degradation on circuit performance were characterized to determine the major routes of degradation and DNA strand-displacement circuit failure. Simple circuit design choices, such as themore » use of 5' toeholds within the DNA complexes used as reactants in the strand-displacement reactions and the termination of single-stranded components with DNA hairpin domains at the 3' termini, significantly increase the functional lifetime of the circuit components in the presence of nucleases. Furthermore, simulations of multireaction circuits, guided by the experimentally measured operation of single-reaction circuits, enable predictive realization of multilayer and competitive-reaction circuit behavior. Altogether, these results provide a basic route to increased DNA circuit stability in cell culture environments.« less

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

2008-01-01

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

PRECISION TIME-DELAY CIRCUIT

DOEpatents

Creveling, R.

1959-03-17

A tine-delay circuit which produces a delay time in d. The circuit a capacitor, an te back resistance, connected serially with the anode of the diode going to ground. At the start of the time delay a negative stepfunction is applied to the series circuit and initiates a half-cycle transient oscillatory voltage terminated by a transient oscillatory voltage of substantially higher frequency. The output of the delay circuit is taken at the junction of the inductor and diode where a sudden voltage rise appears after the initiation of the higher frequency transient oscillations.

Superconducting flux flow digital circuits

DOEpatents

Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

1995-02-14

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

Auto-programmable impulse neural circuits

NASA Technical Reports Server (NTRS)

Watula, D.; Meador, J.

1990-01-01

Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.

Anomalous neural circuit function in schizophrenia during a virtual Morris water task.

PubMed

Folley, Bradley S; Astur, Robert; Jagannathan, Kanchana; Calhoun, Vince D; Pearlson, Godfrey D

2010-02-15

Previous studies have reported learning and navigation impairments in schizophrenia patients during virtual reality allocentric learning tasks. The neural bases of these deficits have not been explored using functional MRI despite well-explored anatomic characterization of these paradigms in non-human animals. Our objective was to characterize the differential distributed neural circuits involved in virtual Morris water task performance using independent component analysis (ICA) in schizophrenia patients and controls. Additionally, we present behavioral data in order to derive relationships between brain function and performance, and we have included a general linear model-based analysis in order to exemplify the incremental and differential results afforded by ICA. Thirty-four individuals with schizophrenia and twenty-eight healthy controls underwent fMRI scanning during a block design virtual Morris water task using hidden and visible platform conditions. Independent components analysis was used to deconstruct neural contributions to hidden and visible platform conditions for patients and controls. We also examined performance variables, voxel-based morphometry and hippocampal subparcellation, and regional BOLD signal variation. Independent component analysis identified five neural circuits. Mesial temporal lobe regions, including the hippocampus, were consistently task-related across conditions and groups. Frontal, striatal, and parietal circuits were recruited preferentially during the visible condition for patients, while frontal and temporal lobe regions were more saliently recruited by controls during the hidden platform condition. Gray matter concentrations and BOLD signal in hippocampal subregions were associated with task performance in controls but not patients. Patients exhibited impaired performance on the hidden and visible conditions of the task, related to negative symptom severity. While controls showed coupling between neural circuits, regional

Apparatus for and method of testing an electrical ground fault circuit interrupt device

DOEpatents

Andrews, L.B.

1998-08-18

An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

Apparatus for and method of testing an electrical ground fault circuit interrupt device

DOEpatents

Andrews, Lowell B.

1998-01-01

An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

The practical operational-amplifier gyrator circuit for inductorless filter synthesis

NASA Technical Reports Server (NTRS)

Sutherland, W. C.

1976-01-01

A literature is reported for gyrator circuits utilizing operational amplifiers as the active device. A gyrator is a two port nonreciprocal device with the property that the input impedance is proportional to the reciprocal of the load impedance. Following an experimental study, the gyrator circuit with optimum properties was selected for additional testing. A theoretical analysis was performed and compared to the experimental results for excellent agreement.

Engine Tune-Up Service. Unit 3: Primary Circuit. Review Exercise Book. Automotive Mechanics Curriculum.

ERIC Educational Resources Information Center

Bacon, E. Miles

This book of pretests and review exercises is designed to accompany the Engine Tune-Up Service Student Guide for Unit 3, Primary Circuit, available separately as CE 031 211. Focus of the exercises and pretests is testing the primary ignition circuit. Pretests and performance checklists are provided for each of the eight performance objectives…

Electronic Circuit Analysis Language (ECAL)

NASA Astrophysics Data System (ADS)

Chenghang, C.

1983-03-01

The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

Diode-quad bridge circuit means

NASA Technical Reports Server (NTRS)

Harrison, D. R.; Dimeff, J. (Inventor)

1975-01-01

Diode-quad bridge circuit means is described for use as a transducer circuit or as a discriminator circuit. It includes: (1) a diode bridge having first, second, third, and fourth bridge terminals consecutively coupled together by four diodes polarized in circulating relationship; (2) a first impedance connected between the second bridge terminal and a circuit ground; (3) a second impedance connected between the fourth bridge terminal and the circuit ground; (4) a signal source having a first source terminal capacitively coupled to the first and third bridge terminals, and a second source terminal connected to the circuit ground; and (5) an output terminal coupled to the first bridge terminal and at which an output signal may be taken.

Charge regulation circuit

DOEpatents

Ball, Don G.

1992-01-01

A charge regulation circuit provides regulation of an unregulated voltage supply in the range of 0.01%. The charge regulation circuit is utilized in a preferred embodiment in providing regulated voltage for controlling the operation of a laser.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Closed circuit TV system automatically guides welding arc

NASA Technical Reports Server (NTRS)

Stephans, D. L.; Wall, W. A., Jr.

1968-01-01

Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.

An Electronics Course Emphasizing Circuit Design

ERIC Educational Resources Information Center

Bergeson, Haven E.

1975-01-01

Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

Evaluation of an enhanced gravity-based fine-coal circuit for high-sulfur coal

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mohanty, M.K.; Samal, A.R.; Palit, A.

One of the main objectives of this study was to evaluate a fine-coal cleaning circuit using an enhanced gravity separator specifically for a high sulfur coal application. The evaluation not only included testing of individual unit operations used for fine-coal classification, cleaning and dewatering, but also included testing of the complete circuit simultaneously. At a scale of nearly 2 t/h, two alternative circuits were evaluated to clean a minus 0.6-mm coal stream utilizing a 150-mm-diameter classifying cyclone, a linear screen having a projected surface area of 0.5 m{sup 2}, an enhanced gravity separator having a bowl diameter of 250 mmmore » and a screen-bowl centrifuge having a bowl diameter of 500 mm. The cleaning and dewatering components of both circuits were the same; however, one circuit used a classifying cyclone whereas the other used a linear screen as the classification device. An industrial size coal spiral was used to clean the 2- x 0.6-mm coal size fraction for each circuit to estimate the performance of a complete fine-coal circuit cleaning a minus 2-mm particle size coal stream. The 'linear screen + enhanced gravity separator + screen-bowl circuit' provided superior sulfur and ash-cleaning performance to the alternative circuit that used a classifying cyclone in place of the linear screen. Based on these test data, it was estimated that the use of the recommended circuit to treat 50 t/h of minus 2-mm size coal having feed ash and sulfur contents of 33.9% and 3.28%, respectively, may produce nearly 28.3 t/h of clean coal with product ash and sulfur contents of 9.15% and 1.61 %, respectively.« less

SNDR Limits of Oscillator-Based Sensor Readout Circuits.

PubMed

Cardes, Fernando; Quintero, Andres; Gutierrez, Eric; Buffa, Cesare; Wiesbauer, Andreas; Hernandez, Luis

2018-02-03

This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.

SNDR Limits of Oscillator-Based Sensor Readout Circuits

PubMed Central

Buffa, Cesare; Wiesbauer, Andreas; Hernandez, Luis

2018-01-01

This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms. PMID:29401646

Electrical Circuits and Water Analogies

ERIC Educational Resources Information Center

Smith, Frederick A.; Wilson, Jerry D.

1974-01-01

Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

Soldering Tool for Integrated Circuits

NASA Technical Reports Server (NTRS)

Takahashi, Ted H.

1987-01-01

Many connections soldered simultaneously in confined spaces. Improved soldering tool bonds integrated circuits onto printed-circuit boards. Intended especially for use with so-called "leadless-carrier" integrated circuits.

Quantum-Circuit Refrigerator

NASA Astrophysics Data System (ADS)

MöTtöNen, Mikko; Tan, Kuan Y.; Masuda, Shumpei; Partanen, Matti; Lake, Russell E.; Govenius, Joonas; Silveri, Matti; Grabert, Hermann

Quantum technology holds great potential in providing revolutionizing practical applications. However, fast and precise cooling of the functional quantum degrees of freedom on demand remains a major challenge in many solid-state implementations, such as superconducting circuits. We demonstrate direct cooling of a superconducting resonator mode using voltage-controllable quantum tunneling of electrons in a nanoscale refrigerator. In our first experiments on this type of a quantum-circuit refrigerator, we measure the drop in the mode temperature by electron thermometry at a resistor which is coupled to the resonator mode through ohmic losses. To eliminate unwanted dissipation, we remove the probe resistor and directly observe the power spectrum of the resonator output in agreement with the so-called P(E) theory. We also demonstrate in microwave reflection experiments that the internal quality factor of the resonator can be tuned by orders of magnitude. In the future, our refrigerator can be integrated with different quantum electric devices, potentially enhancing their performance. For example, it may prove useful in the initialization of superconducting quantum bits and in dissipation-assisted quantum annealing. We acknowledge European Research Council Grant SINGLEOUT (278117) and QUESS (681311) for funding.

Ladder-Type Circuits Revisited

ERIC Educational Resources Information Center

Yoon, Sung Hyun

2007-01-01

Ladder-type circuits where a given unit is repeated infinitely many times are dealt with in many textbooks on electromagnetism as examples of filter circuits. Determining the impedance of such circuits seems to be regarded as simple, which may be due to the fact that the invariance of the infinite system under the operation of adding one more unit…

An evaluation of the Intel 2920 digital signal processing integrated circuit

NASA Technical Reports Server (NTRS)

Heller, J.

1981-01-01

The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.

Maximum Acceleration Recording Circuit

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1995-01-01

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Four-junction superconducting circuit

PubMed Central

Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

2016-01-01

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

Logarithmic current measurement circuit with improved accuracy and temperature stability and associated method

DOEpatents

Ericson, M. Nance; Rochelle, James M.

1994-01-01

A logarithmic current measurement circuit for operating upon an input electric signal utilizes a quad, dielectrically isolated, well-matched, monolithic bipolar transistor array. One group of circuit components within the circuit cooperate with two transistors of the array to convert the input signal logarithmically to provide a first output signal which is temperature-dependant, and another group of circuit components cooperate with the other two transistors of the array to provide a second output signal which is temperature-dependant. A divider ratios the first and second output signals to provide a resultant output signal which is independent of temperature. The method of the invention includes the operating steps performed by the measurement circuit.

Improving Design Efficiency for Large-Scale Heterogeneous Circuits

NASA Astrophysics Data System (ADS)

Gregerson, Anthony

Despite increases in logic density, many Big Data applications must still be partitioned across multiple computing devices in order to meet their strict performance requirements. Among the most demanding of these applications is high-energy physics (HEP), which uses complex computing systems consisting of thousands of FPGAs and ASICs to process the sensor data created by experiments at particles accelerators such as the Large Hadron Collider (LHC). Designing such computing systems is challenging due to the scale of the systems, the exceptionally high-throughput and low-latency performance constraints that necessitate application-specific hardware implementations, the requirement that algorithms are efficiently partitioned across many devices, and the possible need to update the implemented algorithms during the lifetime of the system. In this work, we describe our research to develop flexible architectures for implementing such large-scale circuits on FPGAs. In particular, this work is motivated by (but not limited in scope to) high-energy physics algorithms for the Compact Muon Solenoid (CMS) experiment at the LHC. To make efficient use of logic resources in multi-FPGA systems, we introduce Multi-Personality Partitioning, a novel form of the graph partitioning problem, and present partitioning algorithms that can significantly improve resource utilization on heterogeneous devices while also reducing inter-chip connections. To reduce the high communication costs of Big Data applications, we also introduce Information-Aware Partitioning, a partitioning method that analyzes the data content of application-specific circuits, characterizes their entropy, and selects circuit partitions that enable efficient compression of data between chips. We employ our information-aware partitioning method to improve the performance of the hardware validation platform for evaluating new algorithms for the CMS experiment. Together, these research efforts help to improve the efficiency

Solid state remote circuit selector switch

NASA Technical Reports Server (NTRS)

Peterson, V. S.

1970-01-01

Remote switching circuit utilizes voltage logic to switch on desired circuit. Circuit controls rotating multi-range pressure transducers in jet engine testing and can be used in coded remote circuit activator where sequence of switching has to occur in defined length of time to prevent false or undesired circuit activation.

Vibration Damping Circuit Card Assembly

NASA Technical Reports Server (NTRS)

Hunt, Ronald Allen (Inventor)

2016-01-01

A vibration damping circuit card assembly includes a populated circuit card having a mass M. A closed metal container is coupled to a surface of the populated circuit card at approximately a geometric center of the populated circuit card. Tungsten balls fill approximately 90% of the metal container with a collective mass of the tungsten balls being approximately (0.07) M.

30 CFR 75.900 - Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit...

Code of Federal Regulations, 2011 CFR

2011-07-01

...-phase alternating current equipment; circuit breakers. 75.900 Section 75.900 Mineral Resources MINE... Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit breakers. [Statutory Provisions] Low- and medium-voltage power circuits serving three-phase alternating current...

Noise Expands the Response Range of the Bacillus subtilis Competence Circuit

PubMed Central

Hayden, Luke; Liu, Jintao; Wiggins, Chris H.; Süel, Gürol M.; Walczak, Aleksandra M.

2016-01-01

Gene regulatory circuits must contend with intrinsic noise that arises due to finite numbers of proteins. While some circuits act to reduce this noise, others appear to exploit it. A striking example is the competence circuit in Bacillus subtilis, which exhibits much larger noise in the duration of its competence events than a synthetically constructed analog that performs the same function. Here, using stochastic modeling and fluorescence microscopy, we show that this larger noise allows cells to exit terminal phenotypic states, which expands the range of stress levels to which cells are responsive and leads to phenotypic heterogeneity at the population level. This is an important example of how noise confers a functional benefit in a genetic decision-making circuit. PMID:27003682

A Novel Prediction Method about Single Components of Analog Circuits Based on Complex Field Modeling

PubMed Central

Tian, Shulin; Yang, Chenglin

2014-01-01

Few researches pay attention to prediction about analog circuits. The few methods lack the correlation with circuit analysis during extracting and calculating features so that FI (fault indicator) calculation often lack rationality, thus affecting prognostic performance. To solve the above problem, this paper proposes a novel prediction method about single components of analog circuits based on complex field modeling. Aiming at the feature that faults of single components hold the largest number in analog circuits, the method starts with circuit structure, analyzes transfer function of circuits, and implements complex field modeling. Then, by an established parameter scanning model related to complex field, it analyzes the relationship between parameter variation and degeneration of single components in the model in order to obtain a more reasonable FI feature set via calculation. According to the obtained FI feature set, it establishes a novel model about degeneration trend of analog circuits' single components. At last, it uses particle filter (PF) to update parameters for the model and predicts remaining useful performance (RUP) of analog circuits' single components. Since calculation about the FI feature set is more reasonable, accuracy of prediction is improved to some extent. Finally, the foregoing conclusions are verified by experiments. PMID:25147853

Modeling and Experiments with Carbon Nanotubes for Applications in High Performance Circuits

DTIC Science & Technology

2017-04-06

purchased and installed for experimental characterization of atomic layer deposited graphene on different substrates for radiation-hardened studies...72 3.6 Experimental Research in Graphene for Radiation Hardened Devices……………..73 4 Recommendations...physics for analysis and design of integrated circuits. The developed model is verified from published experimental data. Basic logic gates in

TRIPPING CIRCUIT

DOEpatents

Lees, G.W.; McCormick, E.D.

1962-05-22

A tripping circuit employing a magnetic amplifier for tripping a reactor in response to power level, period, or instrument failure is described. A reference winding and signal winding are wound in opposite directions on the core. Current from an ion chamber passes through both windings. If the current increases at too fast a rate, a shunt circuit bypasses one or the windings and the amplifier output reverses polarity. (AEC)

Integrated coherent matter wave circuits

DOE PAGES

Ryu, C.; Boshier, M. G.

2015-09-21

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Neural circuits and motivational processes for hunger

PubMed Central

Sternson, Scott M; Betley, J Nicholas; Huang Cao, Zhen Fang

2014-01-01

How does an organism’s internal state direct its actions? At one moment an animal forages for food with acrobatic feats such as tree climbing and jumping between branches. At another time, it travels along the ground to find water or a mate, exposing itself to predators along the way. These behaviors are costly in terms of energy or physical risk, and the likelihood of performing one set of actions relative to another is strongly modulated by internal state. For example, an animal in energy deficit searches for food and a dehydrated animal looks for water. The crosstalk between physiological state and motivational processes influences behavioral intensity and intent, but the underlying neural circuits are poorly understood. Molecular genetics along with optogenetic and pharmacogenetic tools for perturbing neuron function have enabled cell type-selective dissection of circuits that mediate behavioral responses to physiological state changes. Here, we review recent progress into neural circuit analysis of hunger in the mouse by focusing on a starvation-sensitive neuron population in the hypothalamus that is sufficient to promote voracious eating. We also consider research into the motivational processes that are thought to underlie hunger in order to outline considerations for bridging the gap between homeostatic and motivational neural circuits. PMID:23648085

Liquid detection circuit

DOEpatents

Regan, Thomas O.

1987-01-01

Herein is a circuit which is capable of detecting the presence of liquids, especially cryogenic liquids, and whose sensor will not overheat in a vacuum. The circuit parameters, however, can be adjusted to work with any liquid over a wide range of temperatures.

Q-band 4-state phase shifter in planar technology: Circuit design and performance analysis.

PubMed

Villa, E; Cagigas, J; Aja, B; de la Fuente, L; Artal, E

2016-09-01

A 30% bandwidth phase shifter with four phase states is designed to be integrated in a radio astronomy receiver. The circuit has two 90° out-of-phase microwave phase-shifting branches which are combined by Wilkinson power dividers. Each branch is composed of a 180° phase shifter and a band-pass filter. The 180° phase shifter is made of cascaded hybrid rings with microwave PIN diodes as switching devices. The 90° phase shift is achieved with the two band-pass filters. Experimental characterization has shown significant results, with average phase shift values of -90.7°, -181.7°, and 88.5° within the operation band, 35-47 GHz, and mean insertion loss of 7.4 dB. The performance of its integration in a polarimetric receiver for radio astronomy is analyzed, which validates the use of the presented phase shifter in such type of receiver.

30 CFR 77.506-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Code of Federal Regulations, 2010 CFR

2010-07-01

... short circuit protection; minimum requirements. 77.506-1 Section 77.506-1 Mineral Resources MINE SAFETY...-1 Electric equipment and circuits; overload and short circuit protection; minimum requirements. Devices providing either short circuit protection or protection against overload shall conform to the...

Interrogating the topological robustness of gene regulatory circuits by randomization

PubMed Central

Levine, Herbert; Onuchic, Jose N.

2017-01-01

One of the most important roles of cells is performing their cellular tasks properly for survival. Cells usually achieve robust functionality, for example, cell-fate decision-making and signal transduction, through multiple layers of regulation involving many genes. Despite the combinatorial complexity of gene regulation, its quantitative behavior has been typically studied on the basis of experimentally verified core gene regulatory circuitry, composed of a small set of important elements. It is still unclear how such a core circuit operates in the presence of many other regulatory molecules and in a crowded and noisy cellular environment. Here we report a new computational method, named random circuit perturbation (RACIPE), for interrogating the robust dynamical behavior of a gene regulatory circuit even without accurate measurements of circuit kinetic parameters. RACIPE generates an ensemble of random kinetic models corresponding to a fixed circuit topology, and utilizes statistical tools to identify generic properties of the circuit. By applying RACIPE to simple toggle-switch-like motifs, we observed that the stable states of all models converge to experimentally observed gene state clusters even when the parameters are strongly perturbed. RACIPE was further applied to a proposed 22-gene network of the Epithelial-to-Mesenchymal Transition (EMT), from which we identified four experimentally observed gene states, including the states that are associated with two different types of hybrid Epithelial/Mesenchymal phenotypes. Our results suggest that dynamics of a gene circuit is mainly determined by its topology, not by detailed circuit parameters. Our work provides a theoretical foundation for circuit-based systems biology modeling. We anticipate RACIPE to be a powerful tool to predict and decode circuit design principles in an unbiased manner, and to quantitatively evaluate the robustness and heterogeneity of gene expression. PMID:28362798

Resolving photon number states in a superconducting circuit.

PubMed

Schuster, D I; Houck, A A; Schreier, J A; Wallraff, A; Gambetta, J M; Blais, A; Frunzio, L; Majer, J; Johnson, B; Devoret, M H; Girvin, S M; Schoelkopf, R J

2007-02-01

Electromagnetic signals are always composed of photons, although in the circuit domain those signals are carried as voltages and currents on wires, and the discreteness of the photon's energy is usually not evident. However, by coupling a superconducting quantum bit (qubit) to signals on a microwave transmission line, it is possible to construct an integrated circuit in which the presence or absence of even a single photon can have a dramatic effect. Such a system can be described by circuit quantum electrodynamics (QED)-the circuit equivalent of cavity QED, where photons interact with atoms or quantum dots. Previously, circuit QED devices were shown to reach the resonant strong coupling regime, where a single qubit could absorb and re-emit a single photon many times. Here we report a circuit QED experiment in the strong dispersive limit, a new regime where a single photon has a large effect on the qubit without ever being absorbed. The hallmark of this strong dispersive regime is that the qubit transition energy can be resolved into a separate spectral line for each photon number state of the microwave field. The strength of each line is a measure of the probability of finding the corresponding photon number in the cavity. This effect is used to distinguish between coherent and thermal fields, and could be used to create a photon statistics analyser. As no photons are absorbed by this process, it should be possible to generate non-classical states of light by measurement and perform qubit-photon conditional logic, the basis of a logic bus for a quantum computer.

Design of a biochemical circuit motif for learning linear functions

PubMed Central

Lakin, Matthew R.; Minnich, Amanda; Lane, Terran; Stefanovic, Darko

2014-01-01

Learning and adaptive behaviour are fundamental biological processes. A key goal in the field of bioengineering is to develop biochemical circuit architectures with the ability to adapt to dynamic chemical environments. Here, we present a novel design for a biomolecular circuit capable of supervised learning of linear functions, using a model based on chemical reactions catalysed by DNAzymes. To achieve this, we propose a novel mechanism of maintaining and modifying internal state in biochemical systems, thereby advancing the state of the art in biomolecular circuit architecture. We use simulations to demonstrate that the circuit is capable of learning behaviour and assess its asymptotic learning performance, scalability and robustness to noise. Such circuits show great potential for building autonomous in vivo nanomedical devices. While such a biochemical system can tell us a great deal about the fundamentals of learning in living systems and may have broad applications in biomedicine (e.g. autonomous and adaptive drugs), it also offers some intriguing challenges and surprising behaviours from a machine learning perspective. PMID:25401175

Design of a biochemical circuit motif for learning linear functions.

PubMed

Lakin, Matthew R; Minnich, Amanda; Lane, Terran; Stefanovic, Darko

2014-12-06

Learning and adaptive behaviour are fundamental biological processes. A key goal in the field of bioengineering is to develop biochemical circuit architectures with the ability to adapt to dynamic chemical environments. Here, we present a novel design for a biomolecular circuit capable of supervised learning of linear functions, using a model based on chemical reactions catalysed by DNAzymes. To achieve this, we propose a novel mechanism of maintaining and modifying internal state in biochemical systems, thereby advancing the state of the art in biomolecular circuit architecture. We use simulations to demonstrate that the circuit is capable of learning behaviour and assess its asymptotic learning performance, scalability and robustness to noise. Such circuits show great potential for building autonomous in vivo nanomedical devices. While such a biochemical system can tell us a great deal about the fundamentals of learning in living systems and may have broad applications in biomedicine (e.g. autonomous and adaptive drugs), it also offers some intriguing challenges and surprising behaviours from a machine learning perspective.

Modifications to the Fission Surface Power Primary Test Circuit (FSP-PTC)

NASA Technical Reports Server (NTRS)

Garber, Anne E.

2008-01-01

An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Modifications are now complete and testing has resumed. Performance of the ALIp, provided by Idaho National Laboratory (INL), is the subject of the first round ofexperimentation. This paper provides a summary of the tests conducted on the original circuit, details the physical changes that have since been made to it, and describes the current test program.

The gravitational potential energy regeneration system with closed-circuit of boom of hydraulic excavator

NASA Astrophysics Data System (ADS)

Chen, Mingdong; Zhao, Dingxuan

2017-01-01

Considering the disadvantage of higher throttling loss for the open-circuit hydrostatic transmission at present, a novel gravitational potential energy regeneration system (GPERS) of the boom of hydraulic excavator, namely the closed-circuit GPERS, is proposed in this paper. The closed-circuit GPERS is based on a closed-circuit hydrostatic transmission and adopts a hydraulic accumulator as main energy storage element fabricated in novel configuration to recover the entire gravitational potential energy of the boom of hydraulic excavator. The matching parameter and control system design are carried out for the proposed system, and the system is modeled based on its physical attributes. Simulation and experiments are performed to validate the employed mathematical models, and then, the velocity and the pressure performance of system are analyzed. It is observed that the closed-circuit GPERS shows better velocity control of the boom and response characteristics. After that, the average working efficiency of the closed-circuit GPERS of boom is estimated under different load conditions. The results indicate that the proposed system is highly effective and that the average working efficiency in different load conditions varied from 60% to 68.2% for the experiment platform.

30 CFR 75.518-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Electric equipment and circuits; overload and short circuit protection; minimum requirements. 75.518-1 Section 75.518-1 Mineral Resources MINE SAFETY... short circuit protection; minimum requirements. A device to provide either short circuit protection or...

30 CFR 75.900 - Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit...

Code of Federal Regulations, 2012 CFR

2012-07-01

... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Low- and medium-voltage circuits serving three... STANDARDS-UNDERGROUND COAL MINES Underground Low- and Medium-Voltage Alternating Current Circuits § 75.900 Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit breakers...

30 CFR 75.900 - Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit...

Code of Federal Regulations, 2014 CFR

2014-07-01

... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Low- and medium-voltage circuits serving three... STANDARDS-UNDERGROUND COAL MINES Underground Low- and Medium-Voltage Alternating Current Circuits § 75.900 Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit breakers...

30 CFR 75.900 - Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit...

Code of Federal Regulations, 2010 CFR

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Low- and medium-voltage circuits serving three... STANDARDS-UNDERGROUND COAL MINES Underground Low- and Medium-Voltage Alternating Current Circuits § 75.900 Low- and medium-voltage circuits serving three-phase alternating current equipment; circuit breakers...

Reconfigurable Optical Directed-Logic Circuits

DTIC Science & Technology

2015-11-20

AFRL-AFOSR-VA-TR-2016-0053 Reconfigurable Optical Directed-Logic Circuits Jacob Robinson WILLIAM MARSH RICE UNIV HOUSTON TX Final Report 11/20/2015...2015 Reconfigurable Optical Directed-Logic Circuits FA9550-12-1-0261 FA9550-12-1-0261 Robinson, Jacob Rice University 6100 Main Street Houston...Optical Directed-Logic Circuits Jacob T. Robinson and Qianfan Xu Rice University 1. Motivation for Directed-Logic Circuits Directed-logic is

Power-Switching Circuit

NASA Technical Reports Server (NTRS)

Praver, Gerald A.; Theisinger, Peter C.; Genofsky, John

1987-01-01

Functions of circuit breakers, meters, and switches combined. Circuit that includes power field-effect transistors (PFET's) provides on/off switching, soft starting, current monitoring, current tripping, and protection against overcurrent for 30-Vdc power supply at normal load currents up to 2 A. Has no moving parts.

A miniature microcontroller curve tracing circuit for space flight testing transistors.

PubMed

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

High temperature superconducting thin film microwave circuits: Fabrication, characterization, and applications

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Warner, J. D.; Romanofsky, R. R.; Heinen, V. O.; Chorey, C. M.

1990-01-01

Epitaxial YBa2Cu3O7 films were grown on several microwave substrates. Surface resistance and penetration depth measurements were performed to determine the quality of these films. Here the properties of these films on key microwave substrates are described. The fabrication and characterization of a microwave ring resonator circuit to determine transmission line losses are presented. Lower losses than those observed in gold resonator circuits were observed at temperatures lower than critical transition temperature. Based on these results, potential applications of microwave superconducting circuits such as filters, resonators, oscillators, phase shifters, and antenna elements in space communication systems are identified.

High temperature superconducting thin film microwave circuits - Fabrication, characterization, and applications

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Warner, J. D.; Romanofsky, R. R.; Heinen, V. O.; Chorey, C. M.

1990-01-01

Epitaxial YBa2Cu3O7 films were grown on several microwave substrates. Surface resistance and penetration depth measurements were performed to determine the quality of these films. Here, the properties of these films on key microwave substrates are described. The fabrication and characterization of a microwave ring resonator circuit to determine transmission line losses are presented. Lower losses than those observed in gold resonator circuits were observed at temperatures lower than critical transition temperature. Based on these results, potential applications of microwave superconducting circuits such as filters, resonators, oscillators, phase shifters, and antenna elements in space communication systems are identified.

Micromachined Integrated Quantum Circuit Containing a Superconducting Qubit

NASA Astrophysics Data System (ADS)

Brecht, T.; Chu, Y.; Axline, C.; Pfaff, W.; Blumoff, J. Z.; Chou, K.; Krayzman, L.; Frunzio, L.; Schoelkopf, R. J.

2017-04-01

We present a device demonstrating a lithographically patterned transmon integrated with a micromachined cavity resonator. Our two-cavity, one-qubit device is a multilayer microwave-integrated quantum circuit (MMIQC), comprising a basic unit capable of performing circuit-QED operations. We describe the qubit-cavity coupling mechanism of a specialized geometry using an electric-field picture and a circuit model, and obtain specific system parameters using simulations. Fabrication of the MMIQC includes lithography, etching, and metallic bonding of silicon wafers. Superconducting wafer bonding is a critical capability that is demonstrated by a micromachined storage-cavity lifetime of 34.3 μ s , corresponding to a quality factor of 2 ×106 at single-photon energies. The transmon coherence times are T1=6.4 μ s , and T2echo=11.7 μ s . We measure qubit-cavity dispersive coupling with a rate χq μ/2 π =-1.17 MHz , constituting a Jaynes-Cummings system with an interaction strength g /2 π =49 MHz . With these parameters we are able to demonstrate circuit-QED operations in the strong dispersive regime with ease. Finally, we highlight several improvements and anticipated extensions of the technology to complex MMIQCs.

Protective Socket For Integrated Circuits

NASA Technical Reports Server (NTRS)

Wilkinson, Chris; Henegar, Greg

1988-01-01

Socket for intergrated circuits (IC's) protects from excessive voltages and currents or from application of voltages and currents in wrong sequence during insertion or removal. Contains built-in switch that opens as IC removed, disconnecting leads from signals and power. Also protects other components on circuit board from transients produced by insertion and removal of IC. Makes unnecessary to turn off power to entire circuit board so other circuits on board continue to function.

Engine Tune-Up Service. Unit 4: Secondary Circuit. Posttests. Automotive Mechanics Curriculum.

ERIC Educational Resources Information Center

Morse, David T.

This book of posttests is designed to accompany the Engine Tune-Up Service Student Guide for Unit 4, Secondary Circuit, available separately as CE 031 214. Focus of the posttests is testing and servicing the secondary ignition circuit. One multiple choice posttest is provided that covers the seven performance objectives contained in the unit. (No…

Engine Tune-Up Service. Unit 3: Primary Circuit. Posttests. Automotive Mechanics Curriculum.

ERIC Educational Resources Information Center

Morse, David T.

This book of posttests is designed to accompany the Engine Tune-Up Service Student Guide for Unit 3, Primary Circuit, available separately as CE 031 211. Focus of the posttests is setting the primary ignition circuit. One multiple choice posttest is provided, covering the eight performance objectives contained in the unit. (No answer key is…

Electroshock protection circuit

NASA Technical Reports Server (NTRS)

Heskett, H.; Meincer, J.; Inglis, A. L.

1973-01-01

Circuit was developed to prevent accidental shock through electrodes used to test subjects as part of Skylab program. This circuit is placed between electrical apparatus and electrode that is attached to patient's body. Thus, patient is effectively protected from dangerous electrical shock that might be caused by failure in electrical apparatus.

Design and application of cotranscriptional non-enzymatic RNA circuits and signal transducers

PubMed Central

Bhadra, Sanchita; Ellington, Andrew D.

2014-01-01

Nucleic acid circuits are finding increasing real-life applications in diagnostics and synthetic biology. Although DNA has been the main operator in most nucleic acid circuits, transcriptionally produced RNA circuits could provide powerful alternatives for reagent production and their use in cells. Towards these goals, we have implemented a particular nucleic acid circuit, catalytic hairpin assembly, using RNA for both information storage and processing. Our results demonstrated that the design principles developed for DNA circuits could be readily translated to engineering RNA circuits that operated with similar kinetics and sensitivities of detection. Not only could purified RNA hairpins perform amplification reactions but RNA hairpins transcribed in vitro also mediated amplification, even without purification. Moreover, we could read the results of the non-enzymatic amplification reactions using a fluorescent RNA aptamer ‘Spinach’ that was engineered to undergo sequence-specific conformational changes. These advances were applied to the end-point and real-time detection of the isothermal strand displacement amplification reaction that produces single-stranded DNAs as part of its amplification cycle. We were also able to readily engineer gate structures with RNA similar to those that have previously formed the basis of DNA circuit computations. Taken together, these results validate an entirely new chemistry for the implementation of nucleic acid circuits. PMID:24493736

Methods of fabricating applique circuits

DOEpatents

Dimos, Duane B.; Garino, Terry J.

1999-09-14

Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Comparing SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout

NASA Astrophysics Data System (ADS)

England, Troy; Curry, Matthew; Carr, Stephen; Mounce, Andrew; Jock, Ryan; Sharma, Peter; Bureau-Oxton, Chloe; Rudolph, Martin; Hardin, Terry; Carroll, Malcolm

Fast, low-power quantum state readout is one of many challenges facing quantum information processing. Single electron transistors (SETs) are potentially fast, sensitive detectors for performing spin readout. From a circuit perspective, however, their output impedance and nonlinear conductance are ill suited to drive the parasitic capacitance of coaxial conductors used in cryogenic environments, necessitating a cryogenic amplification stage. We will compare two amplifiers based on single-transistor circuits implemented with silicon germanium heterojunction bipolar transistors. Both amplifiers provide gain at low power levels, but the dynamics of each circuit vary significantly. We will explore the gain mechanisms, linearity, and noise of each circuit and explain the situations in which each amplifier is best used. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

Integrated circuit cooled turbine blade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.

A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channelmore » connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.« less

Verification of the predictive capabilities of the 4C code cryogenic circuit model

NASA Astrophysics Data System (ADS)

Zanino, R.; Bonifetto, R.; Hoa, C.; Richard, L. Savoldi

2014-01-01

The 4C code was developed to model thermal-hydraulics in superconducting magnet systems and related cryogenic circuits. It consists of three coupled modules: a quasi-3D thermal-hydraulic model of the winding; a quasi-3D model of heat conduction in the magnet structures; an object-oriented a-causal model of the cryogenic circuit. In the last couple of years the code and its different modules have undergone a series of validation exercises against experimental data, including also data coming from the supercritical He loop HELIOS at CEA Grenoble. However, all this analysis work was done each time after the experiments had been performed. In this paper a first demonstration is given of the predictive capabilities of the 4C code cryogenic circuit module. To do that, a set of ad-hoc experimental scenarios have been designed, including different heating and control strategies. Simulations with the cryogenic circuit module of 4C have then been performed before the experiment. The comparison presented here between the code predictions and the results of the HELIOS measurements gives the first proof of the excellent predictive capability of the 4C code cryogenic circuit module.

Capillarics: pre-programmed, self-powered microfluidic circuits built from capillary elements.

PubMed

Safavieh, Roozbeh; Juncker, David

2013-11-07

Microfluidic capillary systems employ surface tension effects to manipulate liquids, and are thus self-powered and self-regulated as liquid handling is structurally and chemically encoded in microscale conduits. However, capillary systems have been limited to perform simple fluidic operations. Here, we introduce complex capillary flow circuits that encode sequential flow of multiple liquids with distinct flow rates and flow reversal. We first introduce two novel microfluidic capillary elements including (i) retention burst valves and (ii) robust low aspect ratio trigger valves. These elements are combined with flow resistors, capillary retention valves, capillary pumps, and open and closed reservoirs to build a capillary circuit that, following sample addition, autonomously delivers a defined sequence of multiple chemicals according to a preprogrammed and predetermined flow rate and time. Such a circuit was used to measure the concentration of C-reactive protein. This work illustrates that as in electronics, complex capillary circuits may be built by combining simple capillary elements. We define such circuits as "capillarics", and introduce symbolic representations. We believe that more complex circuits will become possible by expanding the library of building elements and formulating abstract design rules.

Universal discrete Fourier optics RF photonic integrated circuit architecture.

PubMed

Hall, Trevor J; Hasan, Mehedi

2016-04-04

This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO_3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

NASA Astrophysics Data System (ADS)

Smith, Michael John Sebastian

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

Digital model of a vacuum circuit breaker for the analysis of switching waveforms in electrical circuits

NASA Astrophysics Data System (ADS)

Budzisz, Joanna; Wróblewski, Zbigniew

2016-03-01

The article presents a method of modelling a vaccum circuit breaker in the ATP/EMTP package, the results of the verification of the correctness of the developed digital circuit breaker model operation and its practical usefulness for analysis of overvoltages and overcurrents occurring in commutated capacitive electrical circuits and also examples of digital simulations of overvoltages and overcurrents in selected electrical circuits.

High-precision buffer circuit for suppression of regenerative oscillation

NASA Technical Reports Server (NTRS)

Tripp, John S.; Hare, David A.; Tcheng, Ping

1995-01-01

Precision analog signal conditioning electronics have been developed for wind tunnel model attitude inertial sensors. This application requires low-noise, stable, microvolt-level DC performance and a high-precision buffered output. Capacitive loading of the operational amplifier output stages due to the wind tunnel analog signal distribution facilities caused regenerative oscillation and consequent rectification bias errors. Oscillation suppression techniques commonly used in audio applications were inadequate to maintain the performance requirements for the measurement of attitude for wind tunnel models. Feedback control theory is applied to develop a suppression technique based on a known compensation (snubber) circuit, which provides superior oscillation suppression with high output isolation and preserves the low-noise low-offset performance of the signal conditioning electronics. A practical design technique is developed to select the parameters for the compensation circuit to suppress regenerative oscillation occurring when typical shielded cable loads are driven.

49 CFR 236.303 - Control circuits for signals, selection through circuit controller operated by switch points or...

Code of Federal Regulations, 2010 CFR

2010-10-01

... circuit controller operated by switch points or by switch locking mechanism. 236.303 Section 236.303... § 236.303 Control circuits for signals, selection through circuit controller operated by switch points or by switch locking mechanism. The control circuit for each aspect with indication more favorable...

49 CFR 236.303 - Control circuits for signals, selection through circuit controller operated by switch points or...

Code of Federal Regulations, 2012 CFR

2012-10-01

... circuit controller operated by switch points or by switch locking mechanism. 236.303 Section 236.303... § 236.303 Control circuits for signals, selection through circuit controller operated by switch points or by switch locking mechanism. The control circuit for each aspect with indication more favorable...

49 CFR 236.303 - Control circuits for signals, selection through circuit controller operated by switch points or...

Code of Federal Regulations, 2013 CFR

2013-10-01

... circuit controller operated by switch points or by switch locking mechanism. 236.303 Section 236.303... § 236.303 Control circuits for signals, selection through circuit controller operated by switch points or by switch locking mechanism. The control circuit for each aspect with indication more favorable...

49 CFR 236.303 - Control circuits for signals, selection through circuit controller operated by switch points or...

Code of Federal Regulations, 2014 CFR

2014-10-01

... circuit controller operated by switch points or by switch locking mechanism. 236.303 Section 236.303... § 236.303 Control circuits for signals, selection through circuit controller operated by switch points or by switch locking mechanism. The control circuit for each aspect with indication more favorable...

49 CFR 236.303 - Control circuits for signals, selection through circuit controller operated by switch points or...

Code of Federal Regulations, 2011 CFR

2011-10-01

... circuit controller operated by switch points or by switch locking mechanism. 236.303 Section 236.303... § 236.303 Control circuits for signals, selection through circuit controller operated by switch points or by switch locking mechanism. The control circuit for each aspect with indication more favorable...

Microfluidic Serial Dilution Circuit

PubMed Central

Paegel, Brian M.; Grover, William H.; Skelley, Alison M.; Mathies, Richard A.; Joyce, Gerald F.

2008-01-01

In vitro evolution of RNA molecules requires a method for executing many consecutive serial dilutions. To solve this problem, a microfluidic circuit has been fabricated in a three-layer glass-PDMS-glass device. The 400-nL serial dilution circuit contains five integrated membrane valves: three two-way valves arranged in a loop to drive cyclic mixing of the diluent and carryover, and two bus valves to control fluidic access to the circuit through input and output channels. By varying the valve placement in the circuit, carryover fractions from 0.04 to 0.2 were obtained. Each dilution process, which is comprised of a diluent flush cycle followed by a mixing cycle, is carried out with no pipeting, and a sample volume of 400 nL is sufficient for conducting an arbitrary number of serial dilutions. Mixing is precisely controlled by changing the cyclic pumping rate, with a minimum mixing time of 22 s. This microfluidic circuit is generally applicable for integrating automated serial dilution and sample preparation in almost any microfluidic architecture. PMID:17073422

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Input-output Transfer Function Analysis of a Photometer Circuit Based on an Operational Amplifier.

PubMed

Hernandez, Wilmar

2008-01-09

In this paper an input-output transfer function analysis based on the frequencyresponse of a photometer circuit based on operational amplifier (op amp) is carried out. Opamps are universally used in monitoring photodetectors and there are a variety of amplifierconnections for this purpose. However, the electronic circuits that are usually used to carryout the signal treatment in photometer circuits introduce some limitations in theperformance of the photometers that influence the selection of the op amps and otherelectronic devices. For example, the bandwidth, slew-rate, noise, input impedance and gain,among other characteristics of the op amp, are often the performance limiting factors ofphotometer circuits. For this reason, in this paper a comparative analysis between twophotodiode amplifier circuits is carried out. One circuit is based on a conventional currentto-voltage converter connection and the other circuit is based on a robust current-to-voltageconverter connection. The results are satisfactory and show that the photodiode amplifierperformance can be improved by using robust control techniques.

46 CFR 169.670 - Circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... Gross Tons § 169.670 Circuit breakers. Each circuit breaker must be of the manually reset type designed for— (a) Inverse time delay; (b) Instantaneous short circuit protection; and (c) Repeated opening of... 46 Shipping 7 2010-10-01 2010-10-01 false Circuit breakers. 169.670 Section 169.670 Shipping COAST...

Integrated circuits, and design and manufacture thereof

DOEpatents

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Solving search problems by strongly simulating quantum circuits

PubMed Central

Johnson, T. H.; Biamonte, J. D.; Clark, S. R.; Jaksch, D.

2013-01-01

Simulating quantum circuits using classical computers lets us analyse the inner workings of quantum algorithms. The most complete type of simulation, strong simulation, is believed to be generally inefficient. Nevertheless, several efficient strong simulation techniques are known for restricted families of quantum circuits and we develop an additional technique in this article. Further, we show that strong simulation algorithms perform another fundamental task: solving search problems. Efficient strong simulation techniques allow solutions to a class of search problems to be counted and found efficiently. This enhances the utility of strong simulation methods, known or yet to be discovered, and extends the class of search problems known to be efficiently simulable. Relating strong simulation to search problems also bounds the computational power of efficiently strongly simulable circuits; if they could solve all problems in P this would imply that all problems in NP and #P could be solved in polynomial time. PMID:23390585

Integrated-Circuit Controller For Brushless dc Motor

NASA Technical Reports Server (NTRS)

Le, Dong Tuan

1994-01-01

Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

Equivalent circuit-based analysis of CMUT cell dynamics in arrays.

PubMed

Oguz, H K; Atalar, Abdullah; Köymen, Hayrettin

2013-05-01

Capacitive micromachined ultrasonic transducers (CMUTs) are usually composed of large arrays of closely packed cells. In this work, we use an equivalent circuit model to analyze CMUT arrays with multiple cells. We study the effects of mutual acoustic interactions through the immersion medium caused by the pressure field generated by each cell acting upon the others. To do this, all the cells in the array are coupled through a radiation impedance matrix at their acoustic terminals. An accurate approximation for the mutual radiation impedance is defined between two circular cells, which can be used in large arrays to reduce computational complexity. Hence, a performance analysis of CMUT arrays can be accurately done with a circuit simulator. By using the proposed model, one can very rapidly obtain the linear frequency and nonlinear transient responses of arrays with an arbitrary number of CMUT cells. We performed several finite element method (FEM) simulations for arrays with small numbers of cells and showed that the results are very similar to those obtained by the equivalent circuit model.

Magnetic compression laser driving circuit

DOEpatents

Ball, D.G.; Birx, D.; Cook, E.G.

1993-01-05

A magnetic compression laser driving circuit is disclosed. The magnetic compression laser driving circuit compresses voltage pulses in the range of 1.5 microseconds at 20 kilovolts of amplitude to pulses in the range of 40 nanoseconds and 60 kilovolts of amplitude. The magnetic compression laser driving circuit includes a multi-stage magnetic switch where the last stage includes a switch having at least two turns which has larger saturated inductance with less core material so that the efficiency of the circuit and hence the laser is increased.

Magnetic compression laser driving circuit

DOEpatents

Ball, Don G.; Birx, Dan; Cook, Edward G.

1993-01-01

A magnetic compression laser driving circuit is disclosed. The magnetic compression laser driving circuit compresses voltage pulses in the range of 1.5 microseconds at 20 Kilovolts of amplitude to pulses in the range of 40 nanoseconds and 60 Kilovolts of amplitude. The magnetic compression laser driving circuit includes a multi-stage magnetic switch where the last stage includes a switch having at least two turns which has larger saturated inductance with less core material so that the efficiency of the circuit and hence the laser is increased.

Measuring User Similarity Using Electric Circuit Analysis: Application to Collaborative Filtering

PubMed Central

Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

2012-01-01

We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user–item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems PMID:23145095

Measuring user similarity using electric circuit analysis: application to collaborative filtering.

PubMed

Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

2012-01-01

We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user-item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems.

Dynamics, Analysis and Implementation of a Multiscroll Memristor-Based Chaotic Circuit

NASA Astrophysics Data System (ADS)

Alombah, N. Henry; Fotsin, Hilaire; Ngouonkadi, E. B. Megam; Nguazon, Tekou

This article introduces a novel four-dimensional autonomous multiscroll chaotic circuit which is derived from the actual simplest memristor-based chaotic circuit. A fourth circuit element — another inductor — is introduced to generate the complex behavior observed. A systematic study of the chaotic behavior is performed with the help of some nonlinear tools such as Lyapunov exponents, phase portraits, and bifurcation diagrams. Multiple scroll attractors are observed in Matlab, Pspice environments and also experimentally. We also observe the phenomenon of antimonotonicity, periodic and chaotic bubbles, multiple periodic-doubling bifurcations, Hopf bifurcations, crises and the phenomenon of intermittency. The chaotic dynamics of this circuit is realized by laboratory experiments, Pspice simulations, numerical and analytical investigations. It is observed that the results from the three environments agree to a great extent. This topology is likely convenient to be used to intentionally generate chaos in memristor-based chaotic circuit applications, given the fact that multiscroll chaotic systems have found important applications as broadband signal generators, pseudorandom number generators for communication engineering and also in biometric authentication.

High voltage MOSFET switching circuit

DOEpatents

McEwan, Thomas E.

1994-01-01

The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

Thermometry and thermal management of carbon nanotube circuits

NASA Astrophysics Data System (ADS)

Mayle, Scott; Gupta, Tanuj; Davis, Sam; Chandrasekhar, Venkat; Shafraniuk, Serhii

2015-05-01

Monitoring of the intrinsic temperature and the thermal management is discussed for the carbon nanotube nano-circuits. The experimental results concerning fabricating and testing of a thermometer able to monitor the intrinsic temperature on nanoscale are reported. We also suggest a model which describes a bi-metal multilayer system able to filter the heat flow, based on separating the electron and phonon components one from another. The bi-metal multilayer structure minimizes the phonon component of the heat flow, while retaining the electronic part. The method allows one to improve the overall performance of the electronic nano-circuits due to minimizing the energy dissipation.

Difference-Equation/Flow-Graph Circuit Analysis

NASA Technical Reports Server (NTRS)

Mcvey, I. M.

1988-01-01

Numerical technique enables rapid, approximate analyses of electronic circuits containing linear and nonlinear elements. Practiced in variety of computer languages on large and small computers; for circuits simple enough, programmable hand calculators used. Although some combinations of circuit elements make numerical solutions diverge, enables quick identification of divergence and correction of circuit models to make solutions converge.

Bypassing An Open-Circuit Power Cell

NASA Technical Reports Server (NTRS)

Wannemacher, Harry E.

1994-01-01

Collection of bypass circuits enables battery consisting series string of cells to continue to function when one of its cells fails in open-circuit (high-resistance) condition. Basic idea simply to shunt current around defective cell to prevent open circuit from turning off battery altogether. Bypass circuits dissipate little power and are nearly immune to false activation.

Monostable circuit with tunnel diode has fast recovery

NASA Technical Reports Server (NTRS)

Heffner, P.

1964-01-01

A monostable multivibrator circuit using a tunnel diode makes it possible for the MSMV to exceed the performance of present multivibrators in two respects. The rise time of the output voltage is faster and the duty cycle is raised to approximately 95 percent.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

Systematic use of closed-circuit television in a general practice teaching unit

PubMed Central

Irwin, W. George; Perrott, Jon S.

1981-01-01

We describe use of closed-circuit television in teaching general practice consulting skills in a new central teaching unit of a department of general practice. We explain how the system works, present a simple analysis of student performance in communicating with real and simulated patients and discuss the value of teaching from the consultation with closed-circuit television and video. PMID:7328539

Comparing the Robustness of High-Frequency Traveling-Wave Tube Slow-Wave Circuits

NASA Technical Reports Server (NTRS)

Chevalier, Christine T.; Wilson, Jeffrey D.; Kory, Carol L.

2007-01-01

A three-dimensional electromagnetic field simulation software package was used to compute the cold-test parameters, phase velocity, on-axis interaction impedance, and attenuation, for several high-frequency traveling-wave tube slow-wave circuit geometries. This research effort determined the effects of variations in circuit dimensions on cold-test performance. The parameter variations were based on the tolerances of conventional micromachining techniques.

MULTIPLIER CIRCUIT

DOEpatents

Chase, R.L.

1963-05-01

An electronic fast multiplier circuit utilizing a transistor controlled voltage divider network is presented. The multiplier includes a stepped potentiometer in which solid state or transistor switches are substituted for mechanical wipers in order to obtain electronic switching that is extremely fast as compared to the usual servo-driven mechanical wipers. While this multiplier circuit operates as an approximation and in steps to obtain a voltage that is the product of two input voltages, any desired degree of accuracy can be obtained with the proper number of increments and adjustment of parameters. (AEC)

Trigger Circuit.

DTIC Science & Technology

A wire of Nitinol can be stretched up to a given amount and will remain in this stretched state until heated to a critical temperature. When heated...circuit of this invention provides a current pulse for the required time period to heat the Nitinol wire to its critical temperature to thereby restore the...wire to its original length. The circuit includes a high power transistor which is gated on for a controlled time to provide the required power to heat the Nitinol wire to its critical temperature. (Author)

High voltage MOSFET switching circuit

DOEpatents

McEwan, T.E.

1994-07-26

The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET. 2 figs.

Millimeter-wave and terahertz integrated circuit antennas

NASA Technical Reports Server (NTRS)

Rebeiz, Gabriel M.

1992-01-01

This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

Genetic dissection of GABAergic neural circuits in mouse neocortex

PubMed Central

Taniguchi, Hiroki

2014-01-01

Diverse and flexible cortical functions rely on the ability of neural circuits to perform multiple types of neuronal computations. GABAergic inhibitory interneurons significantly contribute to this task by regulating the balance of activity, synaptic integration, spiking, synchrony, and oscillation in a neural ensemble. GABAergic interneurons display a high degree of cellular diversity in morphology, physiology, connectivity, and gene expression. A considerable number of subtypes of GABAergic interneurons diversify modes of cortical inhibition, enabling various types of information processing in the cortex. Thus, comprehensively understanding fate specification, circuit assembly, and physiological function of GABAergic interneurons is a key to elucidate the principles of cortical wiring and function. Recent advances in genetically encoded molecular tools have made a breakthrough to systematically study cortical circuitry at the molecular, cellular, circuit, and whole animal levels. However, the biggest obstacle to fully applying the power of these to analysis of GABAergic circuits was that there were no efficient and reliable methods to express them in subtypes of GABAergic interneurons. Here, I first summarize cortical interneuron diversity and current understanding of mechanisms, by which distinct classes of GABAergic interneurons are generated. I then review recent development in genetically encoded molecular tools for neural circuit research, and genetic targeting of GABAergic interneuron subtypes, particularly focusing on our recent effort to develop and characterize Cre/CreER knockin lines. Finally, I highlight recent success in genetic targeting of chandelier cells, the most unique and distinct GABAergic interneuron subtype, and discuss what kind of questions need to be addressed to understand development and function of cortical inhibitory circuits. PMID:24478631

Coexistence of multiple bifurcation modes in memristive diode-bridge-based canonical Chua's circuit

NASA Astrophysics Data System (ADS)

Bao, Bocheng; Xu, Li; Wu, Zhimin; Chen, Mo; Wu, Huagan