A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

NASA Astrophysics Data System (ADS)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each

Effect of wafer geometry on lithography chucking processes

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Sinha, Jaydeep K.

2015-03-01

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

High throughput wafer defect monitor for integrated metrology applications in photolithography

NASA Astrophysics Data System (ADS)

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-03-01

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

Mask-to-wafer alignment system

DOEpatents

Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

2003-11-04

A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

Nanoscale patterning of Si surface using SPM scratching

NASA Astrophysics Data System (ADS)

Ogino, T.; Nishimura, S.; Shirakashi, J.

2008-03-01

Nanolithography of Si surface using scanning probe microscopy (SPM) scratching with a diamond-coated tip was systematically investigated at a low force regime below 9 μN. The groove patterns with controlled width and depth could be achieved by adjusting the applied force, scan direction and the number of scan cycles. There was no effect of scan speed on the groove size. The minimum groove width of 10 nm was obtained on Si surfaces. Furthermore, more complex nanostructures such as line and space patterns of 30 nm pith and dot arrays of 2.6×1010 cm-2 density were realized. SPM scratching with a diamond-coated tip allows nanoscale patterning of Si surfaces to be performed simply.

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

PubMed

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

Wafer hot spot identification through advanced photomask characterization techniques

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2016-10-01

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

Transfer molding processes for nanoscale patterning of poly-L-lactic acid (PLLA) films

NASA Astrophysics Data System (ADS)

Dhakal, Rabin; Peer, Akshit; Biswas, Rana; Kim, Jaeyoun

2016-03-01

Nanoscale patterned structures composed of biomaterials exhibit great potential for the fabrication of functional biostructures. In this paper, we report cost-effective, rapid, and highly reproducible soft lithographic transfer-molding techniques for creating periodic micro- and nano-scale textures on poly (L-lactic acid) (PLLA) surface. These artificial textures can increase the overall surface area and change the release dynamics of the therapeutic agents coated on it. Specifically, we use the double replication technique in which the master pattern is first transferred to the PDMS mold and the pattern on PDMS is then transferred to the PLLA films through drop-casting as well as nano-imprinting. The ensuing comparison studies reveal that the drop-cast PLLA allows pattern transfer at higher levels of fidelity, enabling the realization of nano-hole and nano-cone arrays with pitch down to ~700 nm. The nano-patterned PLLA film was then coated with rapamycin to make it drug-eluting.

Wafer screening device and methods for wafer screening

DOEpatents

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Heating device for semiconductor wafers

DOEpatents

Vosen, Steven R.

1999-01-01

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems

NASA Astrophysics Data System (ADS)

Braeuer, J.; Gessner, T.

2014-11-01

This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5 µm to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5 m s-1 for bond frames with lateral dimensions as low as 20 µm. Furthermore, the feasibility of silicon (Si)-Si, Si-glass as well as Si-ceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235 MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Heating device for semiconductor wafers

DOEpatents

Vosen, S.R.

1999-07-27

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Line roughness improvements on self-aligned quadruple patterning by wafer stress engineering

NASA Astrophysics Data System (ADS)

Liu, Eric; Ko, Akiteru; Biolsi, Peter; Chae, Soo Doo; Hsieh, Chia-Yun; Kagaya, Munehito; Lee, Choongman; Moriya, Tsuyoshi; Tsujikawa, Shimpei; Suzuki, Yusuke; Okubo, Kazuya; Imai, Kiyotaka

2018-04-01

In integrated circuit and memory devices, size shrinkage has been the most effective method to reduce production cost and enable the steady increment of the number of transistors per unit area over the past few decades. In order to reduce the die size and feature size, it is necessary to minimize pattern formation in the advance node development. In the node of sub-10nm, extreme ultra violet lithography (EUV) and multi-patterning solutions based on 193nm immersionlithography are the two most common options to achieve the size requirement. In such small features of line and space pattern, line width roughness (LWR) and line edge roughness (LER) contribute significant amount of process variation that impacts both physical and electrical performances. In this paper, we focus on optimizing the line roughness performance by using wafer stress engineering on 30nm pitch line and space pattern. This pattern is generated by a self-aligned quadruple patterning (SAQP) technique for the potential application of fin formation. Our investigation starts by comparing film materials and stress levels in various processing steps and material selection on SAQP integration scheme. From the cross-matrix comparison, we are able to determine the best stack of film selection and stress combination in order to achieve the lowest line roughness performance while obtaining pattern validity after fin etch. This stack is also used to study the step-by-step line roughness performance from SAQP to fin etch. Finally, we will show a successful patterning of 30nm pitch line and space pattern SAQP scheme with 1nm line roughness performance.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers.

PubMed

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-03-04

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers

PubMed Central

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-01-01

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications. PMID:26940260

Fabrication of a highly oriented line structure on an aluminum surface and the nanoscale patterning on the nanoscale structure using highly functional molecules

DOE Office of Scientific and Technical Information (OSTI.GOV)

Watanabe, Y.; Kato, H.; Takemura, S.

2009-07-15

The surface of an Al plate was treated with a combination of chemical and electrochemical processes for fabrication of surface nanoscale structures on Al plates. Chemical treatments by using acetone and pure water under supersonic waves were conducted on an Al surface. Additional electrochemical process in H{sub 2}SO{sub 4} solution created a finer and oriented nanoscale structure on the Al surface. Dynamic force microscopy (DFM) measurement clarified that the nanoscale highly oriented line structure was successfully created on the Al surface. The line distance was estimated approximately 30-40 nm. At the next stage, molecular patterning on the highly oriented linemore » structure by functional molecules such as copper phthalocyanine (CuPc) and fullerene C{sub 60} was also conducted. CuPc or C{sub 60} molecules were deposited on the highly oriented line structure on Al. A toluene droplet containing CuPc molecules was cast on the nanostructured Al plate and was extended on the surface. CuPc or C{sub 60} deposition on the nanostructured Al surface proceeded by evaporation of toluene. DFM and x-ray photoemission spectroscopy measurements demonstrated that a unique molecular pattern was fabricated so that the highly oriented groove channels were filled with the functional molecules.« less

Nanoscale patterning controls inorganic-membrane interface structure

NASA Astrophysics Data System (ADS)

Almquist, Benjamin D.; Verma, Piyush; Cai, Wei; Melosh, Nicholas A.

2011-02-01

The ability to non-destructively integrate inorganic structures into or through biological membranes is essential to realizing full bio-inorganic integration, including arrayed on-chip patch-clamps, drug delivery, and biosensors. Here we explore the role of nanoscale patterning on the strength of biomembrane-inorganic interfaces. AFM measurements show that inorganic probes functionalized with hydrophobic bands with thicknesses complimentary to the hydrophobic lipid bilayer core exhibit strong attachment in the bilayer. As hydrophobic band thickness increases to 2-3 times the bilayer core the interfacial strength decreases, comparable to homogeneously hydrophobic probes. Analytical calculations and molecular dynamics simulations predict a transition between a `fused' interface and a `T-junction' that matches the experimental results, showing lipid disorder and defect formation for thicker bands. These results show that matching biological length scales leads to more intimate bio-inorganic junctions, enabling rational design of non-destructive membrane interfaces.The ability to non-destructively integrate inorganic structures into or through biological membranes is essential to realizing full bio-inorganic integration, including arrayed on-chip patch-clamps, drug delivery, and biosensors. Here we explore the role of nanoscale patterning on the strength of biomembrane-inorganic interfaces. AFM measurements show that inorganic probes functionalized with hydrophobic bands with thicknesses complimentary to the hydrophobic lipid bilayer core exhibit strong attachment in the bilayer. As hydrophobic band thickness increases to 2-3 times the bilayer core the interfacial strength decreases, comparable to homogeneously hydrophobic probes. Analytical calculations and molecular dynamics simulations predict a transition between a `fused' interface and a `T-junction' that matches the experimental results, showing lipid disorder and defect formation for thicker bands. These results

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Phototropic growth control of nanoscale pattern formation in photoelectrodeposited Se–Te films

PubMed Central

Sadtler, Bryce; Burgos, Stanley P.; Batara, Nicolas A.; Beardslee, Joseph A.; Atwater, Harry A.; Lewis, Nathan S.

2013-01-01

Photoresponsive materials that adapt their morphologies, growth directions, and growth rates dynamically in response to the local incident electromagnetic field would provide a remarkable route to the synthesis of complex 3D mesostructures via feedback between illumination and the structure that develops under optical excitation. We report the spontaneous development of ordered, nanoscale lamellar patterns in electrodeposited selenium–tellurium (Se–Te) alloy films grown under noncoherent, uniform illumination on unpatterned substrates in an isotropic electrolyte solution. These inorganic nanostructures exhibited phototropic growth in which lamellar stripes grew toward the incident light source, adopted an orientation parallel to the light polarization direction with a period controlled by the illumination wavelength, and showed an increased growth rate with increasing light intensity. Furthermore, the patterns responded dynamically to changes during growth in the polarization, wavelength, and angle of the incident light, enabling the template-free and pattern-free synthesis, on a variety of substrates, of woodpile, spiral, branched, or zigzag structures, along with dynamically directed growth toward a noncoherent, uniform intensity light source. Full-wave electromagnetic simulations in combination with Monte Carlo growth simulations were used to model light–matter interactions in the Se–Te films and produced a model for the morphological evolution of the lamellar structures under phototropic growth conditions. The experiments and simulations are consistent with a phototropic growth mechanism in which the optical near-field intensity profile selects and reinforces the dominant morphological mode in the emergent nanoscale patterns. PMID:24218617

Phototropic growth control of nanoscale pattern formation in photoelectrodeposited Se-Te films.

PubMed

Sadtler, Bryce; Burgos, Stanley P; Batara, Nicolas A; Beardslee, Joseph A; Atwater, Harry A; Lewis, Nathan S

2013-12-03

Photoresponsive materials that adapt their morphologies, growth directions, and growth rates dynamically in response to the local incident electromagnetic field would provide a remarkable route to the synthesis of complex 3D mesostructures via feedback between illumination and the structure that develops under optical excitation. We report the spontaneous development of ordered, nanoscale lamellar patterns in electrodeposited selenium-tellurium (Se-Te) alloy films grown under noncoherent, uniform illumination on unpatterned substrates in an isotropic electrolyte solution. These inorganic nanostructures exhibited phototropic growth in which lamellar stripes grew toward the incident light source, adopted an orientation parallel to the light polarization direction with a period controlled by the illumination wavelength, and showed an increased growth rate with increasing light intensity. Furthermore, the patterns responded dynamically to changes during growth in the polarization, wavelength, and angle of the incident light, enabling the template-free and pattern-free synthesis, on a variety of substrates, of woodpile, spiral, branched, or zigzag structures, along with dynamically directed growth toward a noncoherent, uniform intensity light source. Full-wave electromagnetic simulations in combination with Monte Carlo growth simulations were used to model light-matter interactions in the Se-Te films and produced a model for the morphological evolution of the lamellar structures under phototropic growth conditions. The experiments and simulations are consistent with a phototropic growth mechanism in which the optical near-field intensity profile selects and reinforces the dominant morphological mode in the emergent nanoscale patterns.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on

Inspection of imprint lithography patterns for semiconductor and patterned media

NASA Astrophysics Data System (ADS)

Resnick, Douglas J.; Haase, Gaddi; Singh, Lovejeet; Curran, David; Schmid, Gerard M.; Luo, Kang; Brooks, Cindy; Selinidis, Kosta; Fretwell, John; Sreenivasan, S. V.

2010-03-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology

Stable wafer-carrier system

DOEpatents

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

NASA Technical Reports Server (NTRS)

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Quantum mechanical modeling the emission pattern and polarization of nanoscale light emitting diodes.

PubMed

Wang, Rulin; Zhang, Yu; Bi, Fuzhen; Frauenheim, Thomas; Chen, GuanHua; Yam, ChiYung

2016-07-21

Understanding of the electroluminescence (EL) mechanism in optoelectronic devices is imperative for further optimization of their efficiency and effectiveness. Here, a quantum mechanical approach is formulated for modeling the EL processes in nanoscale light emitting diodes (LED). Based on non-equilibrium Green's function quantum transport equations, interactions with the electromagnetic vacuum environment are included to describe electrically driven light emission in the devices. The presented framework is illustrated by numerical simulations of a silicon nanowire LED device. EL spectra of the nanowire device under different bias voltages are obtained and, more importantly, the radiation pattern and polarization of optical emission can be determined using the current approach. This work is an important step forward towards atomistic quantum mechanical modeling of the electrically induced optical response in nanoscale systems.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

Enhancement of Water Evaporation on Solid Surfaces with Nanoscale Hydrophobic-Hydrophilic Patterns.

PubMed

Wan, Rongzheng; Wang, Chunlei; Lei, Xiaoling; Zhou, Guoquan; Fang, Haiping

2015-11-06

Using molecular dynamics simulations, we show that the evaporation of nanoscale water on hydrophobic-hydrophilic patterned surfaces is unexpectedly faster than that on any surfaces with uniform wettability. The key to this phenomenon is that, on the patterned surface, the evaporation rate from the hydrophilic region only slightly decreases due to the correspondingly increased water thickness; meanwhile, a considerable number of water molecules evaporate from the hydrophobic region despite the lack of water film. Most of the evaporated water from the hydrophobic region originates from the hydrophilic region by diffusing across the contact lines. Further analysis shows that the evaporation rate from the hydrophobic region is approximately proportional to the total length of the contact lines.

Biomimetic patterned surfaces for controllable friction in micro- and nanoscale devices

NASA Astrophysics Data System (ADS)

Singh, Arvind; Suh, Kahp-Yang

2013-12-01

Biomimetics is the study and simulation of biological systems for desired functional properties. It involves the transformation of underlying principles discovered in nature into man-made technologies. In this context, natural surfaces have significantly inspired and motivated new solutions for micro- and nano-scale devices (e.g., Micro/Nano-Electro-Mechanical Systems, MEMS/NEMS) towards controllable friction, during their operation. As a generic solution to reduce friction at small scale, various thin films/coatings have been employed in the last few decades. In recent years, inspiration from `Lotus Effect' has initiated a new research direction for controllable friction with biomimetic patterned surfaces. By exploiting the intrinsic hydrophobicity and ability to reduce contact area, such micro- or nano-patterned surfaces have demonstrated great strength and potential for applications in MEMS/NEMS devices. This review highlights recent advancements on the design, development and performance of these biomimetic patterned surfaces. Also, we present some hybrid approaches to tackle current challenges in biomimetic tribological applications for MEMS/NEMS devices.

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

NASA Astrophysics Data System (ADS)

Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

2016-03-01

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

Sharp Morphological Transitions from Nanoscale Mixed-Anchoring Patterns in Confined Nematic Liquid Crystals

DOE Office of Scientific and Technical Information (OSTI.GOV)

Armas-Pérez, Julio C.; Li, Xiao; Martínez-González, José A.

Liquid crystals are known to be particularly sensitive to orientational cues provided at surfaces or interfaces. In this work, we explore theoretically, computationally, and experimentally the behavior of liquid crystals on isolated nanoscale patterns with controlled anchoring characteristics at small length scales. The orientation of the liquid crystal is controlled through the use of chemically patterned polymer brushes that are tethered to a surface. This system can be engineered with remarkable precision, and the central question addressed here is whether a characteristic length scale exists at which information encoded on a surface is no longer registered by a liquid crystal.more » To do so, we adopt a tensorial description of the free energy of the hybrid liquidcrystal surface system, and we investigate its morphology in a systematic manner. For long and narrow surface stripes, it is found that the liquid crystal follows the instructions provided by the pattern down to 100 nm widths. This is accomplished through the creation of line defects that travel along the sides of the stripes. We show that a "sharp" morphological transition occurs from a uniform undistorted alignment to a dual uniform/splay-bend morphology. The theoretical and numerical predictions advanced here are confirmed by experimental observations. Our combined analysis suggests that nanoscale patterns can be used to manipulate the orientation of liquid crystals at a fraction of the energetic cost that is involved in traditional liquid crystal-based devices. The insights presented in this work have the potential to provide a new fabrication platform to assemble low power bistable devices, which could be reconfigured upon application of small external fields.« less

Nanoscale patterning of two metals on silicon surfaces using an ABC triblock copolymer template.

PubMed

Aizawa, Masato; Buriak, Jillian M

2006-05-03

Patterning technologically important semiconductor interfaces with nanoscale metal films is important for applications such as metallic interconnects and sensing applications. Self-assembling block copolymer templates are utilized to pattern an aqueous metal reduction reaction, galvanic displacement, on silicon surfaces. Utilization of a triblock copolymer monolayer film, polystyrene-block-poly(2-vinylpyridine)-block-poly(ethylene oxide) (PS-b-P2VP-b-PEO), with two blocks capable of selective transport of different metal complexes to the surface (PEO and P2VP), allows for chemical discrimination and nanoscale patterning. Different regions of the self-assembled structure discriminate between metal complexes at the silicon surface, at which time they undergo the spontaneous reaction at the interface. Gold deposition from gold(III) compounds such as HAuCl4(aq) in the presence of hydrofluoric acid mirrors the parent block copolymer core structure, whereas silver deposition from Ag(I) salts such as AgNO3(aq) does the opposite, localizing exclusively under the corona. By carrying out gold deposition first and silver second, sub-100-nm gold features surrounded by silver films can be produced. The chemical selectivity was extended to other metals, including copper, palladium, and platinum. The interfaces were characterized by a variety of methods, including scanning electron microscopy, scanning Auger microscopy, X-ray photoelectron spectroscopy, and atomic force microscopy.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Cracking-assisted fabrication of nanoscale patterns for micro/nanotechnological applications

NASA Astrophysics Data System (ADS)

Kim, Minseok; Kim, Dong-Joo; Ha, Dogyeong; Kim, Taesung

2016-05-01

Cracks are frequently observed in daily life, but they are rarely welcome and are considered as a material failure mode. Interestingly, cracks cause critical problems in various micro/nanofabrication processes such as colloidal assembly, thin film deposition, and even standard photolithography because they are hard to avoid or control. However, increasing attention has been given recently to control and use cracks as a facile, low-cost strategy for producing highly ordered nanopatterns. Specifically, cracking is the breakage of molecular bonds and occurs simultaneously over a large area, enabling fabrication of nanoscale patterns at both high resolution and high throughput, which are difficult to obtain simultaneously using conventional nanofabrication techniques. In this review, we discuss various cracking-assisted nanofabrication techniques, referred to as crack lithography, and summarize the fabrication principles, procedures, and characteristics of the crack patterns such as their position, direction, and dimensions. First, we categorize crack lithography techniques into three technical development levels according to the directional freedom of the crack patterns: randomly oriented, unidirectional, or multidirectional. Then, we describe a wide range of novel practical devices fabricated by crack lithography, including bioassay platforms, nanofluidic devices, nanowire sensors, and even biomimetic mechanosensors.

Printable Single-Crystal Silicon Micro/Nanoscale Ribbons, Platelets and Bars Generated from Bulk Wafers

DTIC Science & Technology

2007-08-28

enables high yield integration onto wafers, glass plates, plastic sheets, rubber slabs or other surfaces. As one application example, bottom gate thin... EPDMS 1m2Si ESi 1m2PDMS 23 is the critical strain for buck- ling, epre is the degree of prestrain, k0 and A0 are...Young’s modulus of Si and PDMS. The following values were used to yield the calcualted value of it (i.e., 84 lm): ESi = 160 GPa, EPDMS = 2 MPa, mPDMS

Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

NASA Astrophysics Data System (ADS)

Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

2018-01-01

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

Roughness and uniformity improvements on self-aligned quadruple patterning technique for 10nm node and beyond by wafer stress engineering

NASA Astrophysics Data System (ADS)

Liu, Eric; Ko, Akiteru; O'Meara, David; Mohanty, Nihar; Franke, Elliott; Pillai, Karthik; Biolsi, Peter

2017-05-01

Dimension shrinkage has been a major driving force in the development of integrated circuit processing over a number of decades. The Self-Aligned Quadruple Patterning (SAQP) technique is widely adapted for sub-10nm node in order to achieve the desired feature dimensions. This technique provides theoretical feasibility of multiple pitch-halving from 193nm immersion lithography by using various pattern transferring steps. The major concept of this approach is to a create spacer defined self-aligned pattern by using single lithography print. By repeating the process steps, double, quadruple, or octuple are possible to be achieved theoretically. In these small architectures, line roughness control becomes extremely important since it may contribute to a significant portion of process and device performance variations. In addition, the complexity of SAQP in terms of processing flow makes the roughness improvement indirective and ineffective. It is necessary to discover a new approach in order to improve the roughness in the current SAQP technique. In this presentation, we demonstrate a novel method to improve line roughness performances on 30nm pitch SAQP flow. We discover that the line roughness performance is strongly related to stress management. By selecting different stress level of film to be deposited onto the substrate, we can manipulate the roughness performance in line and space patterns. In addition, the impact of curvature change by applied film stress to SAQP line roughness performance is also studied. No significant correlation is found between wafer curvature and line roughness performance. We will discuss in details the step-by-step physical performances for each processing step in terms of critical dimension (CD)/ critical dimension uniformity (CDU)/line width roughness (LWR)/line edge roughness (LER). Finally, we summarize the process needed to reach the full wafer performance targets of LWR/LER in 1.07nm/1.13nm on 30nm pitch line and space pattern.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Wafer-size free-standing single-crystalline graphene device arrays

NASA Astrophysics Data System (ADS)

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Periodic nanoscale patterning of polyelectrolytes over square centimeter areas using block copolymer templates

DOE PAGES

Oded, Meirav; Kelly, Stephen T.; Gilles, Mary K.; ...

2016-04-07

Nano-patterned materials are beneficial for applications such as solar cells, opto-electronics, and sensing owing to their periodic structure and high interfacial area. We present a non-lithographic approach for assembling polyelectrolytes into periodic nanoscale patterns over cm 2 -scale areas. We used chemically modified block copolymer thin films featuring alternating charged and neutral domains as patterned substrates for electrostatic self-assembly. In-depth characterization of the deposition process using spectroscopy and microscopy techniques, including the state-of-the-art scanning transmission X-ray microscopy (STXM), reveals both the selective deposition of the polyelectrolyte on the charged copolymer domains as well as gradual changes in the film topographymore » that arise from further penetration of the solvent molecules and possibly also the polyelectrolyte into these domains. Our results demonstrate the feasibility of creating nano-patterned polyelectrolyte layers, which opens up new opportunities for structured functional coating fabrication.« less

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

NASA Astrophysics Data System (ADS)

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

PubMed

Carey, Benjamin J; Ou, Jian Zhen; Clark, Rhiannon M; Berean, Kyle J; Zavabeti, Ali; Chesman, Anthony S R; Russo, Salvy P; Lau, Desmond W M; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C; Dickey, Michael D; Kaner, Richard B; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-17

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

PubMed Central

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-01-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, Wing C.

1994-01-01

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible.

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, W.C.

1994-02-15

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible. 63 figures.

Comparison of line shortening assessed by aerial image and wafer measurements

NASA Astrophysics Data System (ADS)

Ziegler, Wolfram; Pforr, Rainer; Thiele, Joerg; Maurer, Wilhelm

1997-02-01

Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.

Submicron patterned metal hole etching

DOEpatents

McCarthy, Anthony M.; Contolini, Robert J.; Liberman, Vladimir; Morse, Jeffrey

2000-01-01

A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.

Fabrication of large-area nano-scale patterned sapphire substrate with laser interference lithography

NASA Astrophysics Data System (ADS)

Xuan, Ming-dong; Dai, Long-gui; Jia, Hai-qiang; Chen, Hong

2014-01-01

Periodic triangle truncated pyramid arrays are successfully fabricated on the sapphire substrate by a low-cost and high-efficiency laser interference lithography (LIL) system. Through the combination of dry etching and wet etching techniques, the nano-scale patterned sapphire substrate (NPSS) with uniform size is prepared. The period of the patterns is 460 nm as designed to match the wavelength of blue light emitting diode (LED). By improving the stability of the LIL system and optimizing the process parameters, well-defined triangle truncated pyramid arrays can be achieved on the sapphire substrate with diameter of 50.8 mm. The deviation of the bottom width of the triangle truncated pyramid arrays is 6.8%, which is close to the industrial production level of 3%.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Fabrication of nano-scale Cu bond pads with seal design in 3D integration applications.

PubMed

Chen, K N; Tsang, C K; Wu, W W; Lee, S H; Lu, J Q

2011-04-01

A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

Fabrication of Single, Vertically Aligned Carbon Nanotubes in 3D Nanoscale Architectures

NASA Technical Reports Server (NTRS)

Kaul, Anupama B.; Megerian, Krikor G.; Von Allmen, Paul A.; Baron, Richard L.

2010-01-01

Plasma-enhanced chemical vapor deposition (PECVD) and high-throughput manufacturing techniques for integrating single, aligned carbon nanotubes (CNTs) into novel 3D nanoscale architectures have been developed. First, the PECVD growth technique ensures excellent alignment of the tubes, since the tubes align in the direction of the electric field in the plasma as they are growing. Second, the tubes generated with this technique are all metallic, so their chirality is predetermined, which is important for electronic applications. Third, a wafer-scale manufacturing process was developed that is high-throughput and low-cost, and yet enables the integration of just single, aligned tubes with nanoscale 3D architectures with unprecedented placement accuracy and does not rely on e-beam lithography. Such techniques should lend themselves to the integration of PECVD grown tubes for applications ranging from interconnects, nanoelectromechanical systems (NEMS), sensors, bioprobes, or other 3D electronic devices. Chemically amplified polyhydroxystyrene-resin-based deep UV resists were used in conjunction with excimer laser-based (lambda = 248 nm) step-and-repeat lithography to form Ni catalyst dots = 300 nm in diameter that nucleated single, vertically aligned tubes with high yield using dc PECVD growth. This is the first time such chemically amplified resists have been used, resulting in the nucleation of single, vertically aligned tubes. In addition, novel 3D nanoscale architectures have been created using topdown techniques that integrate single, vertically aligned tubes. These were enabled by implementing techniques that use deep-UV chemically amplified resists for small-feature-size resolution; optical lithography units that allow unprecedented control over layer-to-layer registration; and ICP (inductively coupled plasma) etching techniques that result in near-vertical, high-aspect-ratio, 3D nanoscale architectures, in conjunction with the use of materials that are

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Wafer characteristics via reflectometry

DOEpatents

Sopori, Bhushan L.

2010-10-19

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

Wafer scale oblique angle plasma etching

DOEpatents

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Wafer-scale aluminum nano-plasmonics

NASA Astrophysics Data System (ADS)

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

Characterization and mechanism of He plasma pretreatment of nanoscale polymer masks for improved pattern transfer fidelity

DOE Office of Scientific and Technical Information (OSTI.GOV)

Weilnboeck, F.; Metzler, D.; Kumar, N.

2011-12-26

Roughening of nanoscale polymer masks during plasma etching (PE) limits feature critical dimensions in current and future lithographic technologies. Roughness formation of 193 nm photoresist (PR) is mechanistically explained by plasma-induced changes in mechanical properties introduced at the PR surface ({approx}2 nm) by ions and in parallel in the material bulk ({approx}200 nm) by ultraviolet (UV) plasma radiation. Synergistic roughening of polymer masks can be prevented by pretreating PR patterns with a high dose of He plasma UV exposure to saturate bulk material modifications. During subsequent PE, PR patterns are stabilized and exhibit improved etch resistance and reduced surface/line-edge roughness.

Methane production using resin-wafer electrodeionization

DOEpatents

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Optical and electrical properties of GaN-based light emitting diodes grown on micro- and nano-scale patterned Si substrate

NASA Astrophysics Data System (ADS)

Chiu, Ching-Hsueh; Lin, Chien-Chung; Deng, Dongmei; Kuo, Hao-Chung; Lau, Kei-May

2011-10-01

We investigate the optical and electrical characteristics of the GaN-based light emitting diodes (LEDs) grown on Micro and Nano-scale Patterned silicon substrate (MPLEDs and NPLEDs). The transmission electron microscopy (TEM) images reveal the suppression of threading dislocation density in InGaN/GaN structure on nano-pattern substrate due to nanoscale epitaxial lateral overgrowth (NELOG). The plan-view and cross-section cathodoluminescence (CL) mappings show less defective and more homogeneous active quantum well region growth on nano-porous substrates. From temperature dependent photoluminescence (PL) and low temperature time-resolved photoluminescence (TRPL) measurement, NPLEDs has better carrier confinement and higher radiative recombination rate than MPLEDs. In terms of device performance, NPLEDs exhibits smaller electroluminescence (EL) peak wavelength blue shift, lower reverse leakage current and decreases efficiency droop compared with the MPLEDs. These results suggest the feasibility of using NPSi for the growth of high quality and power LEDs on Si substrates.

Morphological transitions in nanoscale patterns produced by concurrent ion sputtering and impurity co-deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bradley, R. Mark

2016-04-07

We modify the theory of nanoscale patterns produced by ion bombardment with concurrent impurity deposition to take into account the effect that the near-surface impurities have on the collision cascades. As the impurity concentration is increased, the resulting theory successively yields a flat surface, a rippled surface with its wavevector along the projected direction of ion incidence, and a rippled surface with its wavevector rotated by 90°. Exactly the same morphological transitions were observed in recent experiments in which silicon was bombarded with an argon ion beam and gold was co-deposited [Moon et al., e-print arXiv:1601.02534].

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Temperature Dependent Electrical Properties of PZT Wafer

NASA Astrophysics Data System (ADS)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Porous solid ion exchange wafer for immobilizing biomolecules

DOEpatents

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Nanoscale charge distribution and energy band modification in defect-patterned graphene.

PubMed

Wang, Shengnan; Wang, Rui; Wang, Xiaowei; Zhang, Dongdong; Qiu, Xiaohui

2012-04-21

Defects were introduced precisely to exfoliated graphene (G) sheets on a SiO(2)/n(+) Si substrate to modulate the local energy band structure and the electron pathway using solution-phase oxidation followed by thermal reduction. The resulting nanoscale charge distribution and band gap modification were investigated by electrostatic force microscopy and spectroscopy. A transition phase with coexisting submicron-sized metallic and insulating regions in the moderately oxidized monolayer graphene were visualized and measured directly. It was determined that the delocalization of electrons/holes in a graphene "island" is confined by the surrounding defective C-O matrix, which acts as an energy barrier for mobile charge carriers. In contrast to the irreversible structural variations caused by the oxidation process, the electrical properties of graphene can be restored by annealing. The defect-patterned graphene and graphene oxide heterojunctions were further characterized by electrical transport measurement.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

PubMed

Nativ, Amit; Feldman, Haim; Shaked, Natan T

2018-05-01

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

NASA Astrophysics Data System (ADS)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Wafer-fused semiconductor radiation detector

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

The possibility of multi-layer nanofabrication via atomic force microscope-based pulse electrochemical nanopatterning

NASA Astrophysics Data System (ADS)

Kim, Uk Su; Morita, Noboru; Lee, Deug Woo; Jun, Martin; Park, Jeong Woo

2017-05-01

Pulse electrochemical nanopatterning, a non-contact scanning probe lithography process using ultrashort voltage pulses, is based primarily on an electrochemical machining process using localized electrochemical oxidation between a sharp tool tip and the sample surface. In this study, nanoscale oxide patterns were formed on silicon Si (100) wafer surfaces via electrochemical surface nanopatterning, by supplying external pulsed currents through non-contact atomic force microscopy. Nanoscale oxide width and height were controlled by modulating the applied pulse duration. Additionally, protruding nanoscale oxides were removed completely by simple chemical etching, showing a depressed pattern on the sample substrate surface. Nanoscale two-dimensional oxides, prepared by a localized electrochemical reaction, can be defined easily by controlling physical and electrical variables, before proceeding further to a layer-by-layer nanofabrication process.

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

Lithographically Patterned Nanoscale Electrodeposition of Plasmonic, Bimetallic, Semiconductor, Magnetic, and Polymer Nanoring Arrays

PubMed Central

2015-01-01

Large area arrays of magnetic, semiconducting, and insulating nanorings were created by coupling colloidal lithography with nanoscale electrodeposition. This versatile nanoscale fabrication process allows for the independent tuning of the spacing, diameter, and width of the nanorings with typical values of 1.0 μm, 750 nm, and 100 nm, respectively, and was used to form nanorings from a host of materials: Ni, Co, bimetallic Ni/Au, CdSe, and polydopamine. These nanoring arrays have potential applications in memory storage, optical materials, and biosensing. A modified version of this nanoscale electrodeposition process was also used to create arrays of split gold nanorings. The size of the split nanoring opening was controlled by the angle of photoresist exposure during the fabrication process and could be varied from 50% down to 10% of the ring circumference. The large area (cm2 scale) gold split nanoring array surfaces exhibited strong polarization-dependent plasmonic absorption bands for wavelengths from 1 to 5 μm. Plasmonic nanoscale split ring arrays are potentially useful as tunable dichroic materials throughout the infrared and near-infrared spectral regions. PMID:25553204

Improving scanner wafer alignment performance by target optimization

NASA Astrophysics Data System (ADS)

Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

2016-03-01

In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

Surface-pattern geometry, topography, and chemical modifications during KrF excimer laser micro-drilling of p-type Si (111) wafers in ambient environment of HCl fumes in air

NASA Astrophysics Data System (ADS)

Zakria Butt, Muhammad; Saher, Sobia; Waqas Khaliq, Muhammad; Siraj, Khurram

2016-11-01

Eight mirror-like polished p-type Si (111) wafers were irradiated with 100, 200, 300, 400, 800, 1200, 1600, and 2000 KrF excimer laser pulses in ambient environment of HCl fumes in air. The laser parameters were: wavelength = 248 nm, pulse width = 20 ns, pulse energy = 20 mJ, and repetition rate = 20 Hz. For each set of laser pulses, characterization of the rectangular etched patterns formed on target surface was done by optical/scanning electron microscopy, XRD, and EDX techniques. The average etched depth increased with the increase in number of laser pulses from 100 to 2000 in accord with Sigmoidal (Boltzmann) function, whereas the average etch rate followed an exponential decay with the increase in number of laser pulses. However, the etched area, maximum etched depth, and maximum etch rate were found to increase linearly with the number of laser pulses, but the rate of increase was faster for 100-400 laser pulses (region I) than that for 800-2000 laser pulses (region II). The elemental composition for each etched-pattern determined by EDX shows that both O and Cl contents increase progressively with the increase in the number of laser shots in region I. However, in region II both O and Cl contents attain saturation values of about 39.33 wt.% and 0.14 wt.%, respectively. Perforation of Si wafers was achieved on irradiation with 1200-2000 laser pulses. XRD analysis confirmed the formation of SiO2, SiCl2 and SiCl4 phases in Si (111) wafers due to chemical reaction of silicon with both HCl fumes and oxygen in air.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

New getter configuration at wafer level for assuring long term stability of MEMs

NASA Astrophysics Data System (ADS)

Moraja, Marco; Amiotti, Marco; Kullberg, Richard C.

2003-01-01

The evolution from ceramic packages to wafer to wafer hermetic sealing poses tremendous technical challenges to integrate a proper getter inside the MEMs to assure a long term stability and reliability of the devices. The state of the art solution to integrate a getter inside the MEMs of the last generation consists in patterning the getter material with a specific geometry onto the Si cap wafer. The practical implementation of this solution consists in a 4" or 6" Si wafers with grooves or particular incisures, where the getter material is placed in form of a thick film. The typical thickness of these thick films is in the range of few microns, depending on the gas load to be handled during the lifetime of the device. The structure of the thick getter film is highly porous in order to improve sorption performances, but at the same time there are no loose particles thanks to a proprietary manufacturing method. The getter thick film is composed of a Zr special alloy with a proper composition to optimize the sorption performances. The getter thick film can be placed selectively into grooves without affecting the lateral regions, surrounding the grooves where the hermetic sealing is performed.

CDU improvement technology of etching pattern using photo lithography

NASA Astrophysics Data System (ADS)

Tadokoro, Masahide; Shinozuka, Shinichi; Jyousaka, Megumi; Ogata, Kunie; Morimoto, Tamotsu; Konishi, Yoshitaka

2008-03-01

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving Resist Pattern CDU is to control post-exposure bake (PEB) temperature. When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. Resist Pattern CDU improvement contributes to Etching Pattern CDU improvement to a certain degree. To further improve Etching Pattern CDU, etcher-specific CD variation needs to be controlled. In this evaluation, 1. We verified whether etcher-specific CD variation can be controlled and consequently Etching Pattern CDU can be further improved by controlling resist patterns through PEB control. 2. Verifying whether Etching Pattern CDU improvement through has any effect on the reduction in wiring resistance variation. The evaluation procedure is as follows.1. Wafers with base film of Doped Poly-Si (D-Poly) were prepared. 2. Resist patterns were created on them. 3. To determine etcher-specific characteristics, the first etching was performed, and after cleaning off the resist and BARC, CD of etched D-Poly was measured. 4. Using the obtained within-wafer CD distribution of the etching patterns, within-wafer temperature distribution in the PEB process was modified. 5. Resist patterns were created again, followed by the second etching and cleaning, which was followed by CD measurement. We used Optical CD Measurement (OCD) for measurement of resist patterns and etching patterns as OCD is minimally affected by Line Edge Roughness (LER). As a result, 1. We confirmed the effect of Resist Pattern CD control through PEB control on the reduction in etcher-specific CD variation and the improvement in Etching Pattern CDU. 2. The improvement in Etching

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

Design Study of Wafer Seals for Future Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Nanoscale electrochemical patterning reveals the active sites for catechol oxidation at graphite surfaces.

PubMed

Patel, Anisha N; McKelvey, Kim; Unwin, Patrick R

2012-12-19

Graphite-based electrodes (graphite, graphene, and nanotubes) are used widely in electrochemistry, and there is a long-standing view that graphite step edges are needed to catalyze many reactions, with the basal surface considered to be inert. In the present work, this model was tested directly for the first time using scanning electrochemical cell microscopy reactive patterning and shown to be incorrect. For the electro-oxidation of dopamine as a model process, the reaction rate was measured at high spatial resolution across a surface of highly oriented pyrolytic graphite. Oxidation products left behind in a pattern defined by the scanned electrochemical cell served as surface-site markers, allowing the electrochemical activity to be correlated directly with the graphite structure on the nanoscale. This process produced tens of thousands of electrochemical measurements at different locations across the basal surface, unambiguously revealing it to be highly electrochemically active, with step edges providing no enhanced activity. This new model of graphite electrodes has significant implications for the design of carbon-based biosensors, and the results are additionally important for understanding electrochemical processes on related sp(2)-hybridized materials such as pristine graphene and nanotubes.

Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

NASA Astrophysics Data System (ADS)

Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

2004-08-01

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

Wafer-level packaging with compression-controlled seal ring bonding

DOEpatents

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

NASA Astrophysics Data System (ADS)

Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Klie, Robert F.; Kim, Moon J.

2013-12-01

The single twin boundary with crystallographic orientation relationship (1¯1¯1¯)//(111) [01¯1]//[011¯] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Novel wafer stepper with violet LED light source

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Nanoscale wicking methods and devices

NASA Technical Reports Server (NTRS)

Zhou, Jijie (Inventor); Bronikowski, Michael (Inventor); Noca, Flavio (Inventor); Sansom, Elijah B. (Inventor)

2011-01-01

A fluid transport method and fluid transport device are disclosed. Nanoscale fibers disposed in a patterned configuration allow transport of a fluid in absence of an external power source. The device may include two or more fluid transport components having different fluid transport efficiencies. The components may be separated by additional fluid transport components, to control fluid flow.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

NASA Technical Reports Server (NTRS)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Automated mask and wafer defect classification using a novel method for generalized CD variation measurements

NASA Astrophysics Data System (ADS)

Verechagin, V.; Kris, R.; Schwarzband, I.; Milstein, A.; Cohen, B.; Shkalim, A.; Levy, S.; Price, D.; Bal, E.

2018-03-01

Over the years, mask and wafers defects dispositioning has become an increasingly challenging and time consuming task. With design rules getting smaller, OPC getting complex and scanner illumination taking on free-form shapes - the probability of a user to perform accurate and repeatable classification of defects detected by mask inspection tools into pass/fail bins is reducing. The critical challenging of mask defect metrology for small nodes ( < 30 nm) was reviewed in [1]. While Critical Dimension (CD) variation measurement is still the method of choice for determining a mask defect future impact on wafer, the high complexity of OPCs combined with high variability in pattern shapes poses a challenge for any automated CD variation measurement method. In this study, a novel approach for measurement generalization is presented. CD variation assessment performance is evaluated on multiple different complex shape patterns, and is benchmarked against an existing qualified measurement methodology.

Thermal analysis of continuous and patterned multilayer films in the presence of a nanoscale hot spot

NASA Astrophysics Data System (ADS)

Juang, Jia-Yang; Zheng, Jinglin

2016-10-01

Thermal responses of multilayer films play essential roles in state-of-the-art electronic systems, such as photo/micro-electronic devices, data storage systems, and silicon-on-insulator transistors. In this paper, we focus on the thermal aspects of multilayer films in the presence of a nanoscale hot spot induced by near field laser heating. The problem is set up in the scenario of heat assisted magnetic recording (HAMR), the next-generation technology to overcome the data storage density limit imposed by superparamagnetism. We characterized thermal responses of both continuous and patterned multilayer media films using transient thermal modeling. We observed that material configurations, in particular, the thermal barriers at the material layer interfaces crucially impact the temperature field hence play a key role in determining the hot spot geometry, transient response and power consumption. With a representative generic media model, we further explored the possibility of optimizing thermal performances by designing layers of heat sink and thermal barrier. The modeling approach demonstrates an effective way to characterize thermal behaviors of micro and nano-scale electronic devices with multilayer thin film structures. The insights into the thermal transport scheme will be critical for design and operations of such electronic devices.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

NASA Astrophysics Data System (ADS)

Biyikli, Necmi; Haider, Ali

2017-09-01

In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Modelling deformation and fracture in confectionery wafers

NASA Astrophysics Data System (ADS)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Enhancement of the light output power of InGaN/GaN light-emitting diodes grown on pyramidal patterned sapphire substrates in the micro- and nanoscale

NASA Astrophysics Data System (ADS)

Gao, Haiyong; Yan, Fawang; Zhang, Yang; Li, Jinmin; Zeng, Yiping; Wang, Guohong

2008-01-01

Sapphire substrates were patterned by a chemical wet etching technique in the micro- and nanoscale to enhance the light output power of InGaN/GaN light-emitting diodes (LEDs). InGaN/GaN LEDs on a pyramidal patterned sapphire substrate in the microscale (MPSS) and pyramidal patterned sapphire substrate in the nanoscale (NPSS) were grown by metalorganic chemical vapor deposition. The characteristics of the LEDs fabricated on the MPSS and NPSS prepared by wet etching were studied and the light output powers of the LEDs fabricated on the MPSS and NPSS increased compared with that of the conventional LEDs fabricated on planar sapphire substrates. In comparison with the planar sapphire substrate, an enhancement in output power of about 29% and 48% is achieved with the MPSS and NPSS at an injection current of 20 mA, respectively. This significant enhancement is attributable to the improvement of the epitaxial quality of GaN-based epilayers and the improvement of the light extraction efficiency by patterned sapphire substrates. Additionally, the NPSS is more effective to enhance the light output power than the MPSS.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

NASA Astrophysics Data System (ADS)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Nanoscale topographic pattern formation on Kr{sup +}-bombarded germanium surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Perkinson, Joy C.; Madi, Charbel S.; Aziz, Michael J.

2013-03-15

The nanoscale pattern formation of Ge surfaces uniformly irradiated by Kr{sup +} ions was studied in a low-contamination environment at ion energies of 250 and 500 eV and at angles of 0 Degree-Sign through 80 Degree-Sign . The authors present a phase diagram of domains of pattern formation occurring as these two control parameters are varied. The results are insensitive to ion energy over the range covered by the experiments. Flat surfaces are stable from normal incidence up to an incidence angle of {theta} = 55 Degree-Sign from normal. At higher angles, the surface is linearly unstable to the formationmore » of parallel-mode ripples, in which the wave vector is parallel to the projection of the ion beam on the surface. For {theta} {>=} 75 Degree-Sign the authors observe perpendicular-mode ripples, in which the wave vector is perpendicular to the ion beam. This behavior is qualitatively similar to those of Madi et al. for Ar{sup +}-irradiated Si but is inconsistent with those of Ziberi et al. for Kr{sup +}-irradiated Ge. The existence of a window of stability is qualitatively inconsistent with a theory based on sputter erosion [R. M. Bradley and J. M. Harper, J. Vac. Sci. Technol. A 6, 2390 (1988)] and qualitatively consistent with a model of ion impact-induced mass redistribution [G. Carter and V. Vishnyakov, Phys. Rev. B 54, 17647 (1996)] as well as a crater function theory incorporating both effects [S. A. Norris et al., Nat. Commun. 2, 276 (2011)]. The critical transition angle between stable and rippled surfaces occurs 10 Degree-Sign -15 Degree-Sign above the value of 45 Degree-Sign predicted by the mass redistribution model.« less

Simulation of the light emission properties of patterned metal-based nanostructures for ultra-high density optical storage

NASA Astrophysics Data System (ADS)

Li, Weijun; Zhu, Yaping; Luo, Jun; Peng, Sha; Lei, Yu; Tong, Qing; Zhang, Xinyu; Xie, Changsheng

2015-10-01

Current researches show that the surface plasmon-polariton modes (SPPMs) in metallic nanostructures can lead to a powerful localization of guided light signals, which is generally as small as a few nanometers and thus far beyond the diffraction limit of electromagnetic waves in dielectric media. In this paper, our attention is paid to the modeling and simulation of particular kinds of patterned metal-based nanostructure fabricated over several common wafers such as typical silicon dioxide. The nanostructures are designed for concentrating and delivering incident light energy into nanoscale regions. In our research, the factors, for instance, optical materials, patterned nano-structures, the distance arrangement between adjacent single nanopattern, and the frequency of incident electromagnetic wave, are taken as variables, and further the CST microwave studio is used to simulate optical behaviors of the devices developed by us. By comparing the transmittance and electric field intensity distribution in small area, the nano-light-emission effects are analyzed, and the conditions for obtaining near-field nanospots have been chosen.

Modelling deformation and fracture in confectionery wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon

2015-01-22

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which wasmore » then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.« less

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Wafering economies for industrialization from a wafer manufacturer's viewpoint

NASA Technical Reports Server (NTRS)

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Design of surface modifications for nanoscale sensor applications.

PubMed

Reimhult, Erik; Höök, Fredrik

2015-01-14

Nanoscale biosensors provide the possibility to miniaturize optic, acoustic and electric sensors to the dimensions of biomolecules. This enables approaching single-molecule detection and new sensing modalities that probe molecular conformation. Nanoscale sensors are predominantly surface-based and label-free to exploit inherent advantages of physical phenomena allowing high sensitivity without distortive labeling. There are three main criteria to be optimized in the design of surface-based and label-free biosensors: (i) the biomolecules of interest must bind with high affinity and selectively to the sensitive area; (ii) the biomolecules must be efficiently transported from the bulk solution to the sensor; and (iii) the transducer concept must be sufficiently sensitive to detect low coverage of captured biomolecules within reasonable time scales. The majority of literature on nanoscale biosensors deals with the third criterion while implicitly assuming that solutions developed for macroscale biosensors to the first two, equally important, criteria are applicable also to nanoscale sensors. We focus on providing an introduction to and perspectives on the advanced concepts for surface functionalization of biosensors with nanosized sensor elements that have been developed over the past decades (criterion (iii)). We review in detail how patterning of molecular films designed to control interactions of biomolecules with nanoscale biosensor surfaces creates new possibilities as well as new challenges.

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

PubMed Central

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

NASA Astrophysics Data System (ADS)

Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

2006-03-01

The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

Full wafer size investigation of N+ and P+ co-implanted layers in 4H-SiC

NASA Astrophysics Data System (ADS)

Blanqué, S.; Lyonnet, J.; Pérez, R.; Terziyska, P.; Contreras, S.; Godignon, P.; Mestres, N.; Pascual, J.; Camassel, J.

2005-03-01

We report a full wafer size investigation of the homogeneity of electrical properties in the case of co-implanted nitrogen and phosphorus ions in 4H-SiC semi-insulating wafers. To match standard industrial requirements, implantation was done at room temperature. To achieve a detailed electrical knowledge, we worked on a 35 mm wafer on which 77 different reticules have been processed. Every reticule includes one Hall cross, one Van der Pauw test structure and different TLM patterns. Hall measurements have been made on all 77 different reticules, using an Accent HL5500 Hall System® from BioRad fitted with an home-made support to collect data from room temperature down to about 150 K. At room temperature, we find that the sheet carrier concentration is only 1/4 of the total implanted dose while the average mobility is 80.6 cm2/Vs. The standard deviation is, typically, 1.5 cm2/Vs.

ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

NASA Astrophysics Data System (ADS)

Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

2016-05-01

printability of defects at wafer level and automates the process of defect dispositioning from images captured using high resolution inspection machine. It first eliminates false defects due to registration, focus errors, image capture errors and random noise caused during inspection. For the remaining real defects, actual mask-like contours are generated using the Calibre® ILT solution [1][2], which is enhanced to predict the actual mask contours from high resolution defect images. It enables accurate prediction of defect contours, which is not possible from images captured using inspection machine because some information is already lost due to optical effects. Calibre's simulation engine is used to generate images at wafer level using scanner optical conditions and mask-like contours as input. The tool then analyses simulated images and predicts defect printability. It automatically calculates maximum CD variation and decides which defects are severe to affect patterns on wafer. In this paper, we assess the printability of defects for the mask of advanced technology nodes. In particular, we will compare the recovered mask contours with contours extracted from SEM image of the mask and compare simulation results with AIMSTM for a variety of defects and patterns. The results of printability assessment and the accuracy of comparison are presented in this paper. We also suggest how this method can be extended to predict printability of defects identified on EUV photomasks.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Propagation of resist heating mask error to wafer level

NASA Astrophysics Data System (ADS)

Babin, S. V.; Karklin, Linard

2006-10-01

As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Lead zirconate titanate nanoscale patterning by ultraviolet-based lithography lift-off technique for nano-electromechanical system applications.

PubMed

Guillon, Samuel; Saya, Daisuke; Mazenq, Laurent; Costecalde, Jean; Rèmiens, Denis; Soyer, Caroline; Nicu, Liviu

2012-09-01

The advantage of using lead zirconate titanate (PbZr(0.54)Ti(0.46)O(3)) ceramics as an active material in nanoelectromechanical systems (NEMS) comes from its relatively high piezoelectric coefficients. However, its integration within a technological process is limited by the difficulty of structuring this material with submicrometer resolution at the wafer scale. In this work, we develop a specific patterning method based on optical lithography coupled with a dual-layer resist process. The main objective is to obtain sub-micrometer features by lifting off a 100-nm-thick PZT layer while preserving the material's piezoelectric properties. A subsequent result of the developed method is the ability to stack several layers with a lateral resolution of few tens of nanometers, which is mandatory for the fabrication of NEMS with integrated actuation and read-out capabilities.

Formation of coffee-stain patterns at the nanoscale: The role of nanoparticle solubility and solvent evaporation rate.

PubMed

Zhang, Jianguo; Milzetti, Jasmin; Leroy, Frédéric; Müller-Plathe, Florian

2017-03-21

When droplets of nanoparticle suspension evaporate from surfaces, they leave behind a deposit of nanoparticles. The mechanism of evaporation-induced pattern formation in the deposit is studied by molecular dynamics simulations for sessile nanodroplets. The influence of the interaction between nanoparticles and liquid molecules and the influence of the evaporation rate on the final deposition pattern are addressed. When the nanoparticle-liquid interaction is weaker than the liquid-liquid interaction, an interaction-driven or evaporation-induced layer of nanoparticles appears at the liquid-vapor interface and eventually collapses onto the solid surface to form a uniform deposit independently of the evaporation rate. When the nanoparticle-liquid and liquid-liquid interactions are comparable, the nanoparticles are dispersed inside the droplet and evaporation takes place with the contact line pinned at a surface defect. In such a case, a pattern with an approximate ring-like shape is found with fast evaporation, while a more uniform distribution is observed with slower evaporation. When the liquid-nanoparticle interaction is stronger than the liquid-liquid interaction, evaporation always occurs with receding contact line. The final deposition pattern changes from volcano-like to pancake-like with decreasing evaporation rate. These findings might help to design nanoscale structures like nanopatterns or nanowires on surface through controlled solvent evaporation.

Formation of coffee-stain patterns at the nanoscale: The role of nanoparticle solubility and solvent evaporation rate

NASA Astrophysics Data System (ADS)

Zhang, Jianguo; Milzetti, Jasmin; Leroy, Frédéric; Müller-Plathe, Florian

2017-03-01

When droplets of nanoparticle suspension evaporate from surfaces, they leave behind a deposit of nanoparticles. The mechanism of evaporation-induced pattern formation in the deposit is studied by molecular dynamics simulations for sessile nanodroplets. The influence of the interaction between nanoparticles and liquid molecules and the influence of the evaporation rate on the final deposition pattern are addressed. When the nanoparticle-liquid interaction is weaker than the liquid-liquid interaction, an interaction-driven or evaporation-induced layer of nanoparticles appears at the liquid-vapor interface and eventually collapses onto the solid surface to form a uniform deposit independently of the evaporation rate. When the nanoparticle-liquid and liquid-liquid interactions are comparable, the nanoparticles are dispersed inside the droplet and evaporation takes place with the contact line pinned at a surface defect. In such a case, a pattern with an approximate ring-like shape is found with fast evaporation, while a more uniform distribution is observed with slower evaporation. When the liquid-nanoparticle interaction is stronger than the liquid-liquid interaction, evaporation always occurs with receding contact line. The final deposition pattern changes from volcano-like to pancake-like with decreasing evaporation rate. These findings might help to design nanoscale structures like nanopatterns or nanowires on surface through controlled solvent evaporation.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Fabrication of meso- and nano-scale structures on surfaces of chalcogenide semiconductors by surface hydrodynamic interference patterning

NASA Astrophysics Data System (ADS)

Bilanych, V.; Komanicky, V.; Lacková, M.; Feher, A.; Kuzma, V.; Rizak, V.

2015-10-01

We observe the change of surface relief on amorphous Ge-As-Se thin films after irradiation with an electron beam. The beam softens the glass and induces various topological surface changes in the irradiated area. The film relief change depends on the film thickness, deposited charge, and film composition. Various structures are formed: Gausian-like cones, extremely sharp Taylor cones, deep craters, and craters with large spires grown on the side. Our investigation shows that these effects can be at least partially a result of electro-hydrodynamic material flow, but the observed phenomena are likely more complex. When we irradiated structural patterns formed by the electron beam with a red laser beam, we could not only fully relax the produced patterns, but also form very complex and intricate superstructures. These organized meso- and nano-scale structures are formed by a combination of photo-induced structural relaxation, light interference on structures fabricated by the e-beam, and photo-induced material flow.

From magic to technology: materials integration by wafer bonding

NASA Astrophysics Data System (ADS)

Dragoi, Viorel

2006-02-01

Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

WaferOptics® mass volume production and reliability

NASA Astrophysics Data System (ADS)

Wolterink, E.; Demeyer, K.

2010-05-01

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

Design of Surface Modifications for Nanoscale Sensor Applications

PubMed Central

Reimhult, Erik; Höök, Fredrik

2015-01-01

Nanoscale biosensors provide the possibility to miniaturize optic, acoustic and electric sensors to the dimensions of biomolecules. This enables approaching single-molecule detection and new sensing modalities that probe molecular conformation. Nanoscale sensors are predominantly surface-based and label-free to exploit inherent advantages of physical phenomena allowing high sensitivity without distortive labeling. There are three main criteria to be optimized in the design of surface-based and label-free biosensors: (i) the biomolecules of interest must bind with high affinity and selectively to the sensitive area; (ii) the biomolecules must be efficiently transported from the bulk solution to the sensor; and (iii) the transducer concept must be sufficiently sensitive to detect low coverage of captured biomolecules within reasonable time scales. The majority of literature on nanoscale biosensors deals with the third criterion while implicitly assuming that solutions developed for macroscale biosensors to the first two, equally important, criteria are applicable also to nanoscale sensors. We focus on providing an introduction to and perspectives on the advanced concepts for surface functionalization of biosensors with nanosized sensor elements that have been developed over the past decades (criterion (iii)). We review in detail how patterning of molecular films designed to control interactions of biomolecules with nanoscale biosensor surfaces creates new possibilities as well as new challenges. PMID:25594599

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

NASA Astrophysics Data System (ADS)

Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

2018-01-01

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

PubMed

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Environmentally benign processing of YAG transparent wafers

NASA Astrophysics Data System (ADS)

Yang, Yan; Wu, Yiquan

2015-12-01

Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

P/N InP solar cells on Ge wafers

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

Strategies for Controlled Placement of Nanoscale Building Blocks

PubMed Central

2007-01-01

The capability of placing individual nanoscale building blocks on exact substrate locations in a controlled manner is one of the key requirements to realize future electronic, optical, and magnetic devices and sensors that are composed of such blocks. This article reviews some important advances in the strategies for controlled placement of nanoscale building blocks. In particular, we will overview template assisted placement that utilizes physical, molecular, or electrostatic templates, DNA-programmed assembly, placement using dielectrophoresis, approaches for non-close-packed assembly of spherical particles, and recent development of focused placement schemes including electrostatic funneling, focused placement via molecular gradient patterns, electrodynamic focusing of charged aerosols, and others. PMID:21794185

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

Wafer level reliability testing: An idea whose time has come

NASA Technical Reports Server (NTRS)

Trapp, O. D.

1987-01-01

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Dynamic Control of the Vortex Pinning Potential in a Superconductor Using Current Injection through Nanoscale Patterns.

PubMed

Kalcheim, Yoav; Katzir, Eran; Zeides, Felix; Katz, Nadav; Paltiel, Yossi; Millo, Oded

2017-05-10

Control over the vortex potential at the nanoscale in a superconductor is a subject of great interest for both fundamental and technological reasons. Many methods for achieving artificial pinning centers have been demonstrated, for example, with magnetic nanostructures or engineered imperfections, yielding many intriguing effects. However, these pinning mechanisms do not offer dynamic control over the strength of the patterned vortex potential because they involve static nanostructures created in or near the superconductor. Dynamic control has been achieved with scanning probe methods on the single vortex level but these are difficult so scale up. Here, we show that by applying controllable nanopatterned current injection, the superconductor can be locally driven out of equilibrium, creating an artificial vortex potential that can be tuned by the magnitude of the injected current, yielding a unique vortex channeling effect.

A general lithography-free method of microscale/nanoscale fabrication and patterning on Si and Ge surfaces

PubMed Central

2012-01-01

Here, we introduce and give an overview of a general lithography-free method to fabricate silicide and germanide micro-/nanostructures on Si and Ge surfaces through metal-vapor-initiated endoepitaxial growth. Excellent controls on shape and orientation are achieved by adjusting the substrate orientation and growth parameters. Furthermore, micro-/nanoscale pits with controlled morphologies can also be successfully fabricated on Si and Ge surfaces by taking advantage of the sublimation of silicides/germanides. The aim of this brief report is to illustrate the concept of lithography-free synthesis and patterning on surfaces of elemental semiconductors, and the differences and the challenges associated with the Si and the Ge surfaces will be discussed. Our results suggest that this low-cost bottom-up approach is promising for applications in functional nanodevices. PMID:22315969

Wafer-scale micro-optics fabrication

NASA Astrophysics Data System (ADS)

Voelkel, Reinhard

2012-07-01

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Wafer-Fused Orientation-Patterned GaAs

DTIC Science & Technology

2008-02-13

frequencies utilizing existing industrial foundries. 15. SUBJECT TERMS Orientation-patterned Gallium Arsenide, hydride vapor phase epitaxy, quasi-phase... Gallium Arsenide, hydride vapor phase epitaxy, quasi-phase-matching, nonlinear frequency conversion 1. INTRODUCTION Quasi-phase-matching (QPM)1...and E. Lallier, “Second harmonic generation of CO2 laser using thick quasi-phase-matched GaAs layer grown by hydride vapour phase epitaxy

Nanoscale functionalization and characterization of surfaces with hydrogel patterns and biomolecules

NASA Astrophysics Data System (ADS)

Dinakar, Hariharasudhan Chirra

The advent of numerous tools, ease of techniques, and concepts related to nanotechnology, in combination with functionalization via simple chemistry has made gold important for various biomedical applications. In this dissertation, the development and characterization of planar gold surfaces with responsive hydrogel patterns for rapid point of care sensing and the functionalization of gold nanoparticles for drug delivery are highlighted. Biomedical micro- and nanoscale devices that are spatially functionalized with intelligent hydrogels are typically fabricated using conventional UV-lithography. Herein, precise 3-D hydrogel patterns made up of temperature responsive crosslinked poly(N-isopropylacrylamide) over gold were synthesized. The XY control of the hydrogel was achieved using microcontact printing, while thickness control was achieved using atom transfer radical polymerization (ATRP). Atomic force microscopy analysis showed that to the ATRP reaction time governed the pattern growth. The temperature dependent swelling ratio was tailored by tuning the mesh size of the hydrogel. While nanopatterns exhibited a broad lower critical solution temperature (LCST) transition, surface roughness showed a sharp LCST transition. Quartz crystal microbalance with dissipation showed rapid response behavior of the thin films, which makes them applicable as functional components in biomedical devices. The easy synthesis, relative biocompatibility, inertness, and easy functionalization of gold nanoparticles (GNPs) have made them useful for various biomedical applications. Although ATRP can be successfully carried out over GNPs, the yield of stable solution based GNPs for biomedical applications prove to be low. As an alternative approach, a novel method of ISOlating, FUnctionalizing, and REleasing nanoparticles (ISOFURE) was proposed. Biodegradable poly(beta-amino ester) hydrogels were used to synthesize ISOFURE-GNP composites. ATRP was performed inside the composite, and the

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

CD-measurement technique for hole patterns on stencil mask

NASA Astrophysics Data System (ADS)

Ishikawa, Mikio; Yusa, Satoshi; Takikawa, Tadahiko; Fujita, Hiroshi; Sano, Hisatake; Hoga, Morihisa; Hayashi, Naoya

2004-12-01

EB lithography has a potential to successfully form hole patterns as small as 80 nm with a stencil mask. In a previous paper we proposed a technique using a HOLON dual-mode critical dimension (CD) SEM ESPA-75S in the transmission mode for CD measurement of line-and-space patterns on a stencil mask. In this paper we extend our effort of developing a CD measurement technique to contact hole features and determine it in comparison of measured values between features on mask and those printed on wafer. We have evaluated the width method and the area methods using designed 80-500 nm wide contact hole patterns on a large area membrane mask and their resist images on wafer printed by a LEEPL3000. We find that 1) the width method and the area methods show an excellent mask-wafer correlation for holes over 110 nm, and 2) the area methods show a better mask-wafer correlation than the width method does for holes below 110 nm. We conclude that the area calculated from the transmission SEM image is more suitable in defining the hole dimensions than the width for contact holes on a stencil mask.

Shielded piezoresistive cantilever probes for nanoscale topography and electrical imaging

NASA Astrophysics Data System (ADS)

Yang, Yongliang; Ma, Eric Yue; Cui, Yong-Tao; Haemmerli, Alexandre; Lai, Keji; Kundhikanjana, Worasom; Harjee, Nahid; Pruitt, Beth L.; Kelly, Michael; Shen, Zhi-Xun

2014-04-01

This paper presents the design and fabrication of piezoresistive cantilever probes for microwave impedance microscopy (MIM) to enable simultaneous topographic and electrical imaging. Plasma enhanced chemical vapor deposited Si3N4 cantilevers with a shielded center conductor line and nanoscale conductive tip apex are batch fabricated on silicon-on-insulator wafers. Doped silicon piezoresistors are integrated at the root of the cantilevers to sense their deformation. The piezoresistive sensitivity is 2 nm for a bandwidth of 10 kHz, enabling topographical imaging with reasonable speed. The aluminum center conductor has a low resistance (less than 5 Ω) and small capacitance (˜1.7 pF) to ground; these parameters are critical for high sensitivity MIM imaging. High quality piezoresistive topography and MIM images are simultaneously obtained with the fabricated probes at ambient and cryogenic temperatures. These new piezoresistive probes remarkably broaden the horizon of MIM for scientific applications by operating with an integrated feedback mechanism at low temperature and for photosensitive samples.

Massively parallel E-beam inspection: enabling next-generation patterned defect inspection for wafer and mask manufacturing

NASA Astrophysics Data System (ADS)

Malloy, Matt; Thiel, Brad; Bunday, Benjamin D.; Wurm, Stefan; Mukhtar, Maseeh; Quoi, Kathy; Kemen, Thomas; Zeidler, Dirk; Eberle, Anna Lena; Garbowski, Tomasz; Dellemann, Gregor; Peters, Jan Hendrik

2015-03-01

SEMATECH aims to identify and enable disruptive technologies to meet the ever-increasing demands of semiconductor high volume manufacturing (HVM). As such, a program was initiated in 2012 focused on high-speed e-beam defect inspection as a complement, and eventual successor, to bright field optical patterned defect inspection [1]. The primary goal is to enable a new technology to overcome the key gaps that are limiting modern day inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. The program specifically targets revolutionary solutions based on massively parallel e-beam technologies, as opposed to incremental improvements to existing e-beam and optical inspection platforms. Wafer inspection is the primary target, but attention is also being paid to next generation mask inspection. During the first phase of the multi-year program multiple technologies were reviewed, a down-selection was made to the top candidates, and evaluations began on proof of concept systems. A champion technology has been selected and as of late 2014 the program has begun to move into the core technology maturation phase in order to enable eventual commercialization of an HVM system. Performance data from early proof of concept systems will be shown along with roadmaps to achieving HVM performance. SEMATECH's vision for moving from early-stage development to commercialization will be shown, including plans for development with industry leading technology providers.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

2001-06-01

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Wafer plane inspection for advanced reticle defects

NASA Astrophysics Data System (ADS)

Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

2008-05-01

Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

GaN-Based Light-Emitting Diodes Grown on Nanoscale Patterned Sapphire Substrates with Void-Embedded Cortex-Like Nanostructures

NASA Astrophysics Data System (ADS)

Lin, Yu-Sheng; Yeh, J. Andrew

2011-09-01

High-efficiency GaN-based light-emitting diodes (LEDs) with an emitting wavelength of 438 nm were demonstrated utilizing nanoscale patterned sapphire substrates with void-embedded cortex-like nanostructures (NPSS-VECN). Unlike the previous nanopatterned sapphire substrates, the presented substrate has a new morphology that can not only improve the crystalline quality of GaN epilayers but also generate a void-embedded nanostructural layer to enhance light extraction. Under a driving current of 20 mA, the external quantum efficiency of an LED with NPSS-VECN is enhanced by 2.4-fold compared with that of the conventional LED. Moreover, the output powers of two devices respectively are 33.1 and 13.9 mW.

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Wafer-shape metrics based foundry lithography

NASA Astrophysics Data System (ADS)

Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

2017-03-01

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

NASA Astrophysics Data System (ADS)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

New approach for pattern collapse problem by increasing contact area at sub-100nm patterning

NASA Astrophysics Data System (ADS)

Lee, Sung-Koo; Jung, Jae Chang; Lee, Min Suk; Lee, Sung K.; Kim, Sam Young; Hwang, Young-Sun; Bok, Cheol K.; Moon, Seung-Chan; Shin, Ki S.; Kim, Sang-Jung

2003-06-01

To accomplish minimizing feature size to sub 100nm, new light sources for photolithography are emerging, such as ArF(193nm), F2(157nm), and EUV(13nm). However as the pattern size decreases to sub 100nm, a new obstacle, that is pattern collapse problem, becomes most serious bottleneck to the road for the sub 100 nm lithography. The main reason for this pattern collapse problem is capillary force that is increased as the pattern size decreases. As a result there were some trials to decrease this capillary force by changing developer or rinse materials that had low surface tension. On the other hands, there were other efforts to increase adhesion between resists and sub materials (organic BARC). In this study, we will propose a novel approach to solve pattern collapse problems by increasing contact area between sub material (organic BARC) and resist pattern. The basic concept of this approach is that if nano-scale topology is made at the sub material, the contact area between sub materials and resist will be increased. The process scheme was like this. First after coating and baking of organic BARC material, the nano-scale topology (3~10nm) was made by etching at this organic BARC material. On this nano-scale topology, resist was coated and exposed. Finally after develop, the contact area between organic BARC and resist could be increased. Though nano-scale topology was made by etching technology, this 20nm topology variation induced large substrate reflectivity of 4.2% and as a result the pattern fidelity was not so good at 100nm 1:1 island pattern. So we needed a new method to improve pattern fidelity problem. This pattern fidelity problem could be solved by introducing a sacrificial BARC layer. The process scheme was like this. First organic BARC was coated of which k value was about 0.64 and then sacrificial BARC layers was coated of which k value was about 0.18 on the organic BARC. The nano-scale topology (1~4nm) was made by etching of this sacrificial BARC layer

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Electron beam patterning for writing of positively charged gold colloidal nanoparticles

NASA Astrophysics Data System (ADS)

Zafri, Hadar; Azougi, Jonathan; Girshevitz, Olga; Zalevsky, Zeev; Zitoun, David

2018-02-01

Synthesis at the nanoscale has progressed at a very fast pace during the last decades. The main challenge today lies in precise localization to achieve efficient nanofabrication of devices. In the present work, we report on a novel method for the patterning of gold metallic nanoparticles into nanostructures on a silicon-on-insulator (SOI) wafer. The fabrication makes use of relatively accessible equipment, a scanning electron microscope (SEM), and wet chemical synthesis. The electron beam implants electrons into the insulating material, which further anchors the positively charged Au nanoparticles by electrostatic attraction. The novel fabrication method was applied to several substrates useful in microelectronics to add plasmonic particles. The resolution and surface density of the deposition were tuned, respectively, by the electron energy (acceleration voltage) and the dose of electronic irradiation. We easily achieved the smallest written feature of 68 ± 18 nm on SOI, and the technique can be extended to any positively charged nanoparticles, while the resolution is in principle limited by the particle size distribution and the scattering of the electrons in the substrate. [Figure not available: see fulltext.

Wafer chamber having a gas curtain for extreme-UV lithography

DOEpatents

Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

2001-01-01

An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

Patterned self-assembled monolayers for nanoscale lithography and the control of catalytically produced electroosmosis

NASA Astrophysics Data System (ADS)

Subramanian, Shyamala

different end-group functionality impart different surface zeta potential to the gold surface. Zeta-potential engineering via patterning various end-group functionalized SAMs on gold surface to control direction of catalytically induced electroosmotic fluid flow is demonstrated for the first time. This work also describes the application of catalytic power to produce controlled rotational motion. Gold gears-like structures made using conventional microfabrication techniques and propelled by catalytic power are shown to rotate at speeds of 1 rotation/sec in a dilute solution of hydrogen peroxide. Fabrication of a force sensor for detection and measurement of catalytic forces is also introduced. The force sensor, with sensitivity in the piconewton range, consists of a microcantilever with a catalytically active silver post patterned on the tip. Changes in cantilever displacement and resonance frequency due to the catalytic force were monitored as a function of concentration of hydrogen peroxide. Overall, this thesis integrates SAM deposition and patterning techniques with conventional fabrication methods to engineer and control nanoscale structures and devices. Possible future device designs are described including CMOS devices having channel width defined using molecular ruler lithography with sacrificial hosts, drug delivery device based on AFM force sensor and channeless pumps powered by catalytic reactions with SAM controlled electroosmotic fluid flow.

An anti-bacterial approach to nanoscale roughening of biomimetic rice-like pattern PP by thermal annealing

NASA Astrophysics Data System (ADS)

Jafari Nodoushan, Emad; Ebrahimi, Nadereh Golshan; Ayazi, Masoumeh

2017-11-01

In this paper, we introduced thermal annealing treatment as an effective way of increasing the nanoscale roughness of a semi-crystalline polymer surface. Annealing treatment applied to a biomimetic microscale pattern of rice leaf to achieve a superhydrophobic surface with a hierarchical roughness. Resulted surfaces was characterized by XRD, AFM and FE-SEM instruments and showed an increase of roughness and cristallinity within both time and temperature of treatment. These two parameters also impact on measured static contact angle up to 158°. Bacterial attachment potency has an inverse relationship with the similarity of surface pattern dimensions and bacterial size and due to that, thermal annealing could be an effective way to create anti-bacterial surface beyond its effect on water repellency. Point in case, the anti-bacterial properties of produced water-repellence surfaces of PP were measured and counted colonies of both gram-negative (E. coli) and gram-positive (S. aureus) bacteria reduced with the nature of PP and hierarchical pattern on that. Anti-bacterial characterization of the resulted surface reveals a stunning reduction in adhesion of gram-positive bacteria to the surface. S. aureus reduction rates equaled to 95% and 66% when compared to control blank plate and smooth surface of PP. Moreover, it also could affect the other type of bacteria, gram-negative (E. coli). In the latter case, adhesion reduction rates calculated 66% and 53% when against to the same controls, respectively.

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

DOE Office of Scientific and Technical Information (OSTI.GOV)

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In thismore » manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented« less

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

PubMed Central

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Controlling high-throughput manufacturing at the nano-scale

NASA Astrophysics Data System (ADS)

Cooper, Khershed P.

2013-09-01

Interest in nano-scale manufacturing research and development is growing. The reason is to accelerate the translation of discoveries and inventions of nanoscience and nanotechnology into products that would benefit industry, economy and society. Ongoing research in nanomanufacturing is focused primarily on developing novel nanofabrication techniques for a variety of applications—materials, energy, electronics, photonics, biomedical, etc. Our goal is to foster the development of high-throughput methods of fabricating nano-enabled products. Large-area parallel processing and highspeed continuous processing are high-throughput means for mass production. An example of large-area processing is step-and-repeat nanoimprinting, by which nanostructures are reproduced again and again over a large area, such as a 12 in wafer. Roll-to-roll processing is an example of continuous processing, by which it is possible to print and imprint multi-level nanostructures and nanodevices on a moving flexible substrate. The big pay-off is high-volume production and low unit cost. However, the anticipated cost benefits can only be realized if the increased production rate is accompanied by high yields of high quality products. To ensure product quality, we need to design and construct manufacturing systems such that the processes can be closely monitored and controlled. One approach is to bring cyber-physical systems (CPS) concepts to nanomanufacturing. CPS involves the control of a physical system such as manufacturing through modeling, computation, communication and control. Such a closely coupled system will involve in-situ metrology and closed-loop control of the physical processes guided by physics-based models and driven by appropriate instrumentation, sensing and actuation. This paper will discuss these ideas in the context of controlling high-throughput manufacturing at the nano-scale.

A novel approach: high resolution inspection with wafer plane defect detection

NASA Astrophysics Data System (ADS)

Hess, Carl; Wihl, Mark; Shi, Rui-fang; Xiong, Yalin; Pang, Song

2008-05-01

High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects on wafers. WPI is a new inspection mode that has been developed by KLA-Tencor and is currently under test with multiple customers. It employs the same transmitted and reflected-light high-resolution images as the industry-standard high-resolution inspections, but with much more sophisticated processing involved. A rigorous mask pattern recovery algorithm is used to convert the transmitted and reflected light images into a modeled representation of the reticle. Lithographic modeling of the scanner is then used to generate an aerial image of the mask. This is followed by resist modeling to determine the exposure of the photoresist. The defect detectors are then applied on this photoresist plane so that only printing defects are detected. Note that no hardware modifications to the inspection system are required to enable this detector. The same tool will be able to perform both our standard High Resolution inspections and the Wafer Plane Inspection detector. This approach has several important features. The ability to ignore non

Shaping nanoscale magnetic domain memory in exchange-coupled ferromagnets by field cooling.

PubMed

Chesnel, Karine; Safsten, Alex; Rytting, Matthew; Fullerton, Eric E

2016-06-01

The advance of magnetic nanotechnologies relies on detailed understanding of nanoscale magnetic mechanisms in materials. Magnetic domain memory (MDM), that is, the tendency for magnetic domains to repeat the same pattern during field cycling, is important for magnetic recording technologies. Here we demonstrate MDM in [Co/Pd]/IrMn films, using coherent X-ray scattering. Under illumination, the magnetic domains in [Co/Pd] produce a speckle pattern, a unique fingerprint of their nanoscale configuration. We measure MDM by cross-correlating speckle patterns throughout magnetization processes. When cooled below its blocking temperature, the film exhibits up to 100% MDM, induced by exchange-coupling with the underlying IrMn layer. The degree of MDM drastically depends on cooling conditions. If the film is cooled under moderate fields, MDM is high throughout the entire magnetization loop. If the film is cooled under nearly saturating field, MDM vanishes, except at nucleation and saturation. Our findings show how to fully control the occurrence of MDM by field cooling.

Shaping nanoscale magnetic domain memory in exchange-coupled ferromagnets by field cooling

PubMed Central

Chesnel, Karine; Safsten, Alex; Rytting, Matthew; Fullerton, Eric E.

2016-01-01

The advance of magnetic nanotechnologies relies on detailed understanding of nanoscale magnetic mechanisms in materials. Magnetic domain memory (MDM), that is, the tendency for magnetic domains to repeat the same pattern during field cycling, is important for magnetic recording technologies. Here we demonstrate MDM in [Co/Pd]/IrMn films, using coherent X-ray scattering. Under illumination, the magnetic domains in [Co/Pd] produce a speckle pattern, a unique fingerprint of their nanoscale configuration. We measure MDM by cross-correlating speckle patterns throughout magnetization processes. When cooled below its blocking temperature, the film exhibits up to 100% MDM, induced by exchange-coupling with the underlying IrMn layer. The degree of MDM drastically depends on cooling conditions. If the film is cooled under moderate fields, MDM is high throughout the entire magnetization loop. If the film is cooled under nearly saturating field, MDM vanishes, except at nucleation and saturation. Our findings show how to fully control the occurrence of MDM by field cooling. PMID:27248368

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Micro to Nanoscale Engineering of Surface Precipitates Using Reconfigurable Contact Lines.

PubMed

Kabi, Prasenjit; Chaudhuri, Swetaprovo; Basu, Saptarshi

2018-02-06

Nanoscale engineering has traditionally adopted the chemical route of synthesis or optochemical techniques such as lithography requiring large process times, expensive equipment, and an inert environment. Directed self-assembly using evaporation of nanocolloidal droplet can be a potential low-cost alternative across various industries ranging from semiconductors to biomedical systems. It is relatively simple to scale and reorient the evaporation-driven internal flow field in an evaporating droplet which can direct dispersed matter into functional agglomerates. The resulting functional precipitates not only exhibit macroscopically discernible changes but also nanoscopic variations in the particulate assembly. Thus, the evaporating droplet forms an autonomous system for nanoscale engineering without the need for external resources. In this article, an indigenous technique of interfacial re-engineering, which is both simple and inexpensive to implement, is developed. Such re-engineering widens the horizon for surface patterning previously limited by the fixed nature of the droplet interface. It involves handprinting hydrophobic lines on a hydrophilic substrate to form a confinement of any selected geometry using a simple document stamp. Droplets cast into such confinements get modulated into a variety of shapes. The droplet shapes control the contact line behavior, evaporation dynamics, and complex internal flow pattern. By exploiting the dynamic interplay among these variables, we could control the deposit's macro- as well as nanoscale assembly not possible with simple circular droplets. We provide a detailed mechanism of the coupling at various length scales enabling a predictive capability in custom engineering, particularly useful in nanoscale applications such as photonic crystals.

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

PubMed

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

2008-10-01

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

High frequency guided wave propagation in monocrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

A front-end wafer-level microsystem packaging technique with micro-cap array

NASA Astrophysics Data System (ADS)

Chiang, Yuh-Min

2002-09-01

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

Wafer-level colinearity monitoring for TFH applications

NASA Astrophysics Data System (ADS)

Moore, Patrick; Newman, Gary; Abreau, Kelly J.

2000-06-01

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines

Wafer-scale plasmonic and photonic crystal sensors

NASA Astrophysics Data System (ADS)

George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

2015-08-01

200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

Silk protein nanowires patterned using electron beam lithography.

PubMed

Pal, Ramendra K; Yadavalli, Vamsi K

2018-08-17

Nanofabrication approaches to pattern proteins at the nanoscale are useful in applications ranging from organic bioelectronics to cellular engineering. Specifically, functional materials based on natural polymers offer sustainable and environment-friendly substitutes to synthetic polymers. Silk proteins (fibroin and sericin) have emerged as an important class of biomaterials for next generation applications owing to excellent optical and mechanical properties, inherent biocompatibility, and biodegradability. However, the ability to precisely control their spatial positioning at the nanoscale via high throughput tools continues to remain a challenge. In this study electron beam lithography (EBL) is used to provide nanoscale patterning using methacrylate conjugated silk proteins that are photoreactive 'photoresists' materials. Very low energy electron beam radiation can be used to pattern silk proteins at the nanoscale and over large areas, whereby such nanostructure fabrication can be performed without specialized EBL tools. Significantly, using conducting polymers in conjunction with these silk proteins, the formation of protein nanowires down to 100 nm is shown. These wires can be easily degraded using enzymatic degradation. Thus, proteins can be precisely and scalably patterned and doped with conducting polymers and enzymes to form degradable, organic bioelectronic devices.

Lamb wave propagation in monocrystalline silicon wafers.

PubMed

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

Reduction of Defects in AlGaN Grown on Nanoscale-Patterned Sapphire Substrates by Hydride Vapor Phase Epitaxy

PubMed Central

Tasi, Chi-Tsung; Wang, Wei-Kai; Tsai, Tsung-Yen; Huang, Shih-Yung; Horng, Ray-Hua; Wuu, Dong-Sing

2017-01-01

In this study, a 3-μm-thick AlGaN film with an Al mole fraction of 10% was grown on a nanoscale-patterned sapphire substrate (NPSS) using hydride vapor phase epitaxy (HVPE). The growth mechanism, crystallization, and surface morphology of the epilayers were examined using X-ray diffraction, transmission electron microscopy (TEM), and scanning electron microscopy at various times in the growth process. The screw threading dislocation (TD) density of AlGaN-on-NPSS can improve to 1–2 × 109 cm−2, which is significantly lower than that of the sample grown on a conventional planar sapphire substrate (7 × 109 cm−2). TEM analysis indicated that these TDs do not subsequently propagate to the surface of the overgrown AlGaN layer, but bend or change directions in the region above the voids within the side faces of the patterned substrates, possibly because of the internal stress-relaxed morphologies of the AlGaN film. Hence, the laterally overgrown AlGaN films were obtained by HVPE, which can serve as a template for the growth of ultraviolet III-nitride optoelectronic devices. PMID:28772961

Reduction of Defects in AlGaN Grown on Nanoscale-Patterned Sapphire Substrates by Hydride Vapor Phase Epitaxy.

PubMed

Tasi, Chi-Tsung; Wang, Wei-Kai; Tsai, Tsung-Yen; Huang, Shih-Yung; Horng, Ray-Hua; Wuu, Dong-Sing

2017-05-31

In this study, a 3-μm-thick AlGaN film with an Al mole fraction of 10% was grown on a nanoscale-patterned sapphire substrate (NPSS) using hydride vapor phase epitaxy (HVPE). The growth mechanism, crystallization, and surface morphology of the epilayers were examined using X-ray diffraction, transmission electron microscopy (TEM), and scanning electron microscopy at various times in the growth process. The screw threading dislocation (TD) density of AlGaN-on-NPSS can improve to 1-2 × 10⁸ cm -2 , which is significantly lower than that of the sample grown on a conventional planar sapphire substrate (7 × 10⁸ cm -2 ). TEM analysis indicated that these TDs do not subsequently propagate to the surface of the overgrown AlGaN layer, but bend or change directions in the region above the voids within the side faces of the patterned substrates, possibly because of the internal stress-relaxed morphologies of the AlGaN film. Hence, the laterally overgrown AlGaN films were obtained by HVPE, which can serve as a template for the growth of ultraviolet III-nitride optoelectronic devices.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Nanoscale Probing of Thermal, Stress, and Optical Fields under Near-Field Laser Heating

PubMed Central

Tang, Xiaoduan; Xu, Shen; Wang, Xinwei

2013-01-01

Micro/nanoparticle induced near-field laser ultra-focusing and heating has been widely used in laser-assisted nanopatterning and nanolithography to pattern nanoscale features on a large-area substrate. Knowledge of the temperature and stress in the nanoscale near-field heating region is critical for process control and optimization. At present, probing of the nanoscale temperature, stress, and optical fields remains a great challenge since the heating area is very small (∼100 nm or less) and not immediately accessible for sensing. In this work, we report the first experimental study on nanoscale mapping of particle-induced thermal, stress, and optical fields by using a single laser for both near-field excitation and Raman probing. The mapping results based on Raman intensity variation, wavenumber shift, and linewidth broadening all give consistent conjugated thermal, stress, and near-field focusing effects at a 20 nm resolution (<λ/26, λ = 32 nm). Nanoscale mapping of near-field effects of particles from 1210 down to 160 nm demonstrates the strong capacity of such a technique. By developing a new strategy for physical analysis, we have de-conjugated the effects of temperature, stress, and near-field focusing from the Raman mapping. The temperature rise and stress in the nanoscale heating region is evaluated at different energy levels. High-fidelity electromagnetic and temperature field simulation is conducted to accurately interpret the experimental results. PMID:23555566

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Warpage Measurement of Thin Wafers by Reflectometry

NASA Astrophysics Data System (ADS)

Ng, Chi Seng; Asundi, Anand Krishna

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Shaping nanoscale magnetic domain memory in exchange-coupled ferromagnets by field cooling

DOE PAGES

Chesnel, Karine; Safsten, Alex; Rytting, Matthew; ...

2016-06-01

The advance of magnetic nanotechnologies relies on detailed understanding of nanoscale magnetic mechanisms in materials. Magnetic domain memory (MDM), that is, the tendency for magnetic domains to repeat the same pattern during field cycling, is important for magnetic recording technologies. Here we demonstrate MDM in [Co/Pd]/IrMn films, using coherent X-ray scattering. Under illumination, the magnetic domains in [Co/Pd] produce a speckle pattern, a unique fingerprint of their nanoscale configuration. We measure MDM by cross-correlating speckle patterns throughout magnetization processes. When cooled below its blocking temperature, the film exhibits up to 100% MDM, induced by exchange-coupling with the underlying IrMn layer.more » The degree of MDM drastically depends on cooling conditions. If the film is cooled under moderate fields, MDM is high throughout the entire magnetization loop. Lastly, if the film is cooled under nearly saturating field, MDM vanishes, except at nucleation and saturation. Our findings show how to fully control the occurrence of MDM by field cooling.« less

Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

Enhanced capture rate for haze defects in production wafer inspection

NASA Astrophysics Data System (ADS)

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure

Controlling the Nanoscale Patterning of AuNPs on Silicon Surfaces

PubMed Central

Williams, Sophie E.; Davies, Philip R.; Bowen, Jenna L.; Allender, Chris J.

2013-01-01

This study evaluates the effectiveness of vapour-phase deposition for creating sub-monolayer coverage of aminopropyl triethoxysilane (APTES) on silicon in order to exert control over subsequent gold nanoparticle deposition. Surface coverage was evaluated indirectly by observing the extent to which gold nanoparticles (AuNPs) deposited onto the modified silicon surface. By varying the distance of the silicon wafer from the APTES source and concentration of APTES in the evaporating media, control over subsequent gold nanoparticle deposition was achievable to an extent. Fine control over AuNP deposition (AuNPs/μm2) however, was best achieved by adjusting the ionic concentration of the AuNP-depositing solution. Furthermore it was demonstrated that although APTES was fully removed from the silicon surface following four hours incubation in water, the gold nanoparticle-amino surface complex was stable under the same conditions. Atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) were used to study these affects. PMID:28348330

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Effects of Bias Pulsing on Etching of SiO2 Pattern in Capacitively-Coupled Plasmas for Nano-Scale Patterning of Multi-Level Hard Masks.

PubMed

Kim, Sechan; Choi, Gyuhyun; Chae, Heeyeop; Lee, Nae-Eung

2016-05-01

In order to study the effects of bias pulsing on the etching characteristics of a silicon dioxide (SiO2) layer using multi-level hard mask (MLHM) structures of ArF photoresist/bottom anti-reflected coating/SiO2/amorphous carbon layer (ACL)/SiO2, the effects of bias pulsing conditions on the etch characteristics of a SiO2 layer with an ACL mask pattern in C4F8/CH2F2/O2/Ar etch chemistries were investigated in a dual-frequency capacitively-coupled plasma (CCP) etcher. The effects of the pulse frequency, duty ratio, and pulse-bias power in the 2 MHz low-frequency (LF) power source were investigated in plasmas generated by a 27.12 MHz high-frequency (HF) power source. The etch rates of ACL and SiO2 decreased, but the etch selectivity of SiO2/ACL increased with decreasing duty ratio. When the ACL and SiO2 layers were etched with increasing pulse frequency, no significant change was observed in the etch rates and etch selectivity. With increasing LF pulse-bias power, the etch rate of ACL and SiO2 slightly increased, but the etch selectivity of SiO2/ACL decreased. Also, the precise control of the critical dimension (CD) values with decreasing duty ratio can be explained by the protection of sidewall etching of SiO2 by increased passivation. Pulse-biased etching was successfully applied to the patterning of the nano-scale line and space of SiO2 using an ACL pattern.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Rocket Science at the Nanoscale.

PubMed

Li, Jinxing; Rozen, Isaac; Wang, Joseph

2016-06-28

Autonomous propulsion at the nanoscale represents one of the most challenging and demanding goals in nanotechnology. Over the past decade, numerous important advances in nanotechnology and material science have contributed to the creation of powerful self-propelled micro/nanomotors. In particular, micro- and nanoscale rockets (MNRs) offer impressive capabilities, including remarkable speeds, large cargo-towing forces, precise motion controls, and dynamic self-assembly, which have paved the way for designing multifunctional and intelligent nanoscale machines. These multipurpose nanoscale shuttles can propel and function in complex real-life media, actively transporting and releasing therapeutic payloads and remediation agents for diverse biomedical and environmental applications. This review discusses the challenges of designing efficient MNRs and presents an overview of their propulsion behavior, fabrication methods, potential rocket fuels, navigation strategies, practical applications, and the future prospects of rocket science and technology at the nanoscale.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Electrostatic bonding of thin (approximately 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (approximately 2 mil) silicon wafers and solar cells

NASA Technical Reports Server (NTRS)

Egelkrout, D. W.; Horne, W. E.

1980-01-01

Electrostatic bonding (ESB) of thin (3 mil) Corning 7070 cover glasses to Ta2O5 AR-coated thin (2 mil) silicon wafers and solar cells is investigated. An experimental program was conducted to establish the effects of variations in pressure, voltage, temperature, time, Ta2O5 thickness, and various prebond glass treatments. Flat wafers without contact grids were used to study the basic effects for bonding to semiconductor surfaces typical of solar cells. Solar cells with three different grid patterns were used to determine additional requirements caused by the raised metallic contacts.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Advanced FTIR technology for the chemical characterization of product wafers

NASA Astrophysics Data System (ADS)

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

High extraction efficiency GaN-based light-emitting diodes on embedded SiO2 nanorod array and nanoscale patterned sapphire substrate

NASA Astrophysics Data System (ADS)

Huang, Hung-Wen; Huang, Jhi-Kai; Kuo, Shou-Yi; Lee, Kang-Yuan; Kuo, Hao-Chung

2010-06-01

In this paper, GaN-based LEDs with a nanoscale patterned sapphire substrate (NPSS) and a SiO2 photonic quasicrystal (PQC) structure on an n-GaN layer using nanoimprint lithography are fabricated and investigated. The light output power of LED with a NPSS and a SiO2 PQC structure on an n-GaN layer was 48% greater than that of conventional LED. Strong enhancement in output power is attributed to better epitaxial quality and higher reflectance resulted from NPSS and PQC structures. Transmission electron microscopy images reveal that threading dislocations are blocked or bended in the vicinities of NPSS layer. These results provide promising potential to increase output power for commercial light emitting devices.

Geometry-based across wafer process control in a dual damascene scenario

NASA Astrophysics Data System (ADS)

Krause, Gerd; Hofmann, Detlef; Habets, Boris; Buhl, Stefan; Gutsch, Manuela; Lopez-Gomez, Alberto; Thrun, Xaver

2018-03-01

Dual damascene is an established patterning process for back-end-of-line to generate copper interconnects and lines. One of the critical output parameters is the electrical resistance of the metal lines. In our 200 mm line, this is currently being controlled by a feed-forward control from the etch process to the final step in the CMP process. In this paper, we investigate the impact of alternative feed-forward control using a calibrated physical model that estimates the impact on electrical resistance of the metal lines* . This is done by simulation on a large set of wafers. Three different approaches are evaluated, one of which uses different feed-forward settings for different radial zones in the CMP process.

Wafer integrated micro-scale concentrating photovoltaics

NASA Astrophysics Data System (ADS)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Mechanics of wafer bonding: Effect of clamping

NASA Astrophysics Data System (ADS)

Turner, K. T.; Thouless, M. D.; Spearing, S. M.

2004-01-01

A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Template-guided highly aligned, nano-scale wrinkle structure on a large-area

NASA Astrophysics Data System (ADS)

Lim, Jongcheon; Kim, Pilnam

This study presents a novel technique to induce aligned, nano-scale wrinkle on a polysiloxane-based UV curable resin. There have been studies on generating randomized sub-micron wrinkle using oxygen plasma treatment which causes equibiaxial compressive stress on the film surface. Few works have been reported on how to control the surface wrinkle orientation. Currently available approaches for regulating the wrinkle pattern typically require polydimethylsiloxane (PDMS)-based bilayer system under uniaxial stress condition which hampers various technological applications. Here, we demonstrate a method to generate aligned wrinkle with UV curable polymers. Highly regular array of nanoscale wrinkles were formed by elastic buckling of bilayered UV curable resin, resulting from a combination of confinement effect and anchor-guided propagation of structure. The wrinkle tends to align uniformly lateral to the template pattern as the resin filled in the pattern forms more convex meniscus. The wavelength of the wrinkle was controlled by UV exposure time yielding as small as 170nm. From our results, we suggest the confinement provided by the template pattern may have affected the direction of thin film's expansion yielding unidirectional compressive stress. This work was supported by Samsung Research Funding Center of Samsung Electronics under Project Number SRFC-IT1402-02.

Mask pattern generator employing EPL technology

NASA Astrophysics Data System (ADS)

Yoshioka, Nobuyuki; Yamabe, Masaki; Wakamiya, Wataru; Endo, Nobuhiro

2003-08-01

Mask cost is one of crucial issues in device fabrication, especially in SoC (System on a Chip) with small-volume production. The cost mainly depends on productivity of mask manufacturing tools such as mask writers and defect inspection tools. EPL (Electron Projection Lithography) has been developing as a high-throughput electron beam exposure technology that will succeed optical lithography. The application of EPL technology to mask writing will result in high productivity and contribute to decrease the mask cost. The concept of a mask pattern generator employing EPL technology is proposed in this paper. It is very similar to EPL technology used for pattern printing on a wafer. The mask patterns on the glass substrate are exposed by projecting the basic circuit patterns formed on the mother EPL mask. One example of the mother EPL mask is a stencil type made with 200-mm Si wafer. The basic circuit patterns are IP patterns and logical primitive patterns such as cell libraries (AND, OR, Inverter, Flip-Flop and etc.) to express the SoC device patterns. Since the SoC patterns are exposed with its collective units such as IP and logical primitive patterns by using this method, the high throughput will be expected comparing with conventional mask E-beam writers. In this paper, the mask pattern generator with the EPL technology is proposed. The concept, its advantages and issues to be solved are discussed.

Nanoscale Ionic Liquids

DTIC Science & Technology

2006-11-01

Technical Report 11 December 2005 - 30 November 2006 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Nanoscale Ionic Liquids 5b. GRANT NUMBER FA9550-06-1-0012...Title: Nanoscale Ionic Liquids Principal Investigator: Emmanuel P. Giannelis Address: Materials Science and Engineering, Bard Hall, Cornell University...based fluids exhibit high ionic conductivity. The NFs are typically synthesized by grafting a charged, oligomeric corona onto the nanoparticle cores

Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

NASA Astrophysics Data System (ADS)

Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

2018-02-01

Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

Accurate characterization of wafer bond toughness with the double cantilever specimen

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Spearing, S. Mark

2008-01-01

The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

Multiscale modeling for SiO2 atomic layer deposition for high-aspect-ratio hole patterns

NASA Astrophysics Data System (ADS)

Miyano, Yumiko; Narasaki, Ryota; Ichikawa, Takashi; Fukumoto, Atsushi; Aiso, Fumiki; Tamaoki, Naoki

2018-06-01

A multiscale simulation model is developed for optimizing the parameters of SiO2 plasma-enhanced atomic layer deposition of high-aspect-ratio hole patterns in three-dimensional (3D) stacked memory. This model takes into account the diffusion of a precursor in a reactor, that in holes, and the adsorption onto the wafer. It is found that the change in the aperture ratio of the holes on the wafer affects the concentration of the precursor near the top of the wafer surface, hence the deposition profile in the hole. The simulation results reproduced well the experimental results of the deposition thickness for the various hole aperture ratios. By this multiscale simulation, we can predict the deposition profile in a high-aspect-ratio hole pattern in 3D stacked memory. The atomic layer deposition parameters for conformal deposition such as precursor feeding time and partial pressure of precursor for wafers with various hole aperture ratios can be estimated.

Scatterometry on pelliclized masks: an option for wafer fabs

NASA Astrophysics Data System (ADS)

Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

2007-03-01

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Wafer plane inspection with soft resist thresholding

NASA Astrophysics Data System (ADS)

Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

2008-10-01

Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

Friction laws at the nanoscale.

PubMed

Mo, Yifei; Turner, Kevin T; Szlufarska, Izabela

2009-02-26

Macroscopic laws of friction do not generally apply to nanoscale contacts. Although continuum mechanics models have been predicted to break down at the nanoscale, they continue to be applied for lack of a better theory. An understanding of how friction force depends on applied load and contact area at these scales is essential for the design of miniaturized devices with optimal mechanical performance. Here we use large-scale molecular dynamics simulations with realistic force fields to establish friction laws in dry nanoscale contacts. We show that friction force depends linearly on the number of atoms that chemically interact across the contact. By defining the contact area as being proportional to this number of interacting atoms, we show that the macroscopically observed linear relationship between friction force and contact area can be extended to the nanoscale. Our model predicts that as the adhesion between the contacting surfaces is reduced, a transition takes place from nonlinear to linear dependence of friction force on load. This transition is consistent with the results of several nanoscale friction experiments. We demonstrate that the breakdown of continuum mechanics can be understood as a result of the rough (multi-asperity) nature of the contact, and show that roughness theories of friction can be applied at the nanoscale.

MiRNA-181d Expression Significantly Affects Treatment Responses to Carmustine Wafer Implantation.

PubMed

Sippl, Christoph; Ketter, Ralf; Bohr, Lisa; Kim, Yoo Jin; List, Markus; Oertel, Joachim; Urbschat, Steffi

2018-05-26

Standard therapeutic protocols for glioblastoma, the most aggressive type of brain cancer, include surgery followed by chemoradiotherapy. Additionally, carmustine-eluting wafers can be implanted locally into the resection cavity. To evaluate microRNA (miRNA)-181d as a prognostic marker of responses to carmustine wafer implantation. A total of 80 glioblastoma patients (40/group) were included in a matched pair analysis. One group (carmustine wafer group) received concomitant chemoradiotherapy with carmustine wafer implantation (Stupp protocol). The second group (control group) received only concomitant chemoradiotherapy. All tumor specimens were subjected to evaluations of miRNA-181d expression, results were correlated with further individual clinical data. The Cancer Genome Atlas (TCGA) dataset of 149 patients was used as an independent cohort to validate the results. Patients in the carmustine wafer group with low miRNA-181d expression had significantly longer overall (hazard ratio [HR], 35.03, [95% confidence interval (CI): 3.50-350.23], P = .002) and progression-free survival (HR, 20.23, [95% CI: 2.19-186.86], P = .008) than patients of the same group with a high miRNA-181d expression. These correlations were not observed in the control group. The nonsignificance in the control group was confirmed in the independent TCGA dataset. The carmustine wafer group patients with low miRNA-181d expression also had a significantly longer progression-free (P = .049) and overall survival (OS) (P = .034), compared with control group patients. Gross total resection correlated significantly with longer OS (P = .023). MiRNA-181d expression significantly affects treatment responses to carmustine wafer implantation.

Grain-boundary type and distribution in silicon carbide coatings and wafers

NASA Astrophysics Data System (ADS)

Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

2018-03-01

Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

PubMed

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

Smoother Scribing of Silicon Wafers

NASA Technical Reports Server (NTRS)

Danyluk, S.

1986-01-01

Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

Commercial production of QWIP wafers by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Fastenau, J. M.; Liu, W. K.; Fang, X. M.; Lubyshev, D. I.; Pelzel, R. I.; Yurasits, T. R.; Stewart, T. R.; Lee, J. H.; Li, S. S.; Tidrow, M. Z.

2001-06-01

As the performance of quantum well infrared photodetectors (QWIPs) and QWIP-based imaging systems continues to improve, their demand will undoubtedly grow. This points to the importance of a reliable commercial supplier of semiconductor QWIP material on three inch and, in the near future, four-inch substrates. Molecular beam epitaxy (MBE) is the preferred technique for growing the demanding QWIP structure, as tight control is required over the material composition and layer thickness. We report the current status of MBE-grown GaAs-based QWIP structures in a commercial production environment at IQE. Uniformity data and run-to-run reproducibility on both three-inch and four-inch GaAs substrates are quantified using alloy composition and QW thickness. Initial results on growth technology transfer to a multi-wafer MBE reactor are also presented. High-resolution X-ray diffraction measurements demonstrate GaAs QW thickness variations and AlGaAs barrier compositions changes to be less than 4% and 1% Al, respectively, across four-inch QWIP wafers from both single- and multiple-wafer MBE platforms.

Design, modeling, and fabrication of crab-shape capacitive microphone using silicon-on-isolator wafer

NASA Astrophysics Data System (ADS)

Ganji, Bahram Azizollah; Sedaghat, Sedighe Babaei; Roncaglia, Alberto; Belsito, Luca; Ansari, Reza

2018-01-01

This paper presents design, modeling, and fabrication of a crab-shape microphone using silicon-on-isolator (SOI) wafer. SOI wafer is used to prevent the additional deposition of sacrificial and diaphragm layers. The holes have been made on diaphragm to prevent back plate etching. Dry etching is used for removing the sacrificial layer, because wet etching causes adhesion between the diaphragm and the back plate. Crab legs around the perforated diaphragm allow for improving the microphone performance and reducing the mechanical stiffness and air damping of the microphone. In this structure, the supply voltage is decreased due to the uniform deflection of the diaphragm due to the designed low-K (spring constant) structure. An analytical model of the structure for description of microphone behavior is presented. The proposed method for estimating the basic parameters of the microphone is based on the calculation of the spring constant using the energy method. The microphone is fabricated using only one mask to pattern the crab-shape diaphragm, resulting in a low-cost and easy fabrication process. The diaphragm size is 0.3 mm×0.3 mm, which is smaller than the conventional microelectromechanical systems capacitive microphone. The results show that the analytical equations have a good agreement with measurement results. The device has the pull-in voltage of 14.3 V, a resonant frequency of 90 kHz, an open-circuit sensitivity of 1.33 mV/Pa under bias voltage of 5 V. Comparing with previous works, this microphone has several advantages: SOI wafer decreases the fabrication process steps, the microphone is smaller than the previous works, and crab-shape diaphragm improves the microphone performances.

Bio-Organic Nanotechnology: Using Proteins and Synthetic Polymers for Nanoscale Devices

NASA Technical Reports Server (NTRS)

Molnar, Linda K.; Xu, Ting; Trent, Jonathan D.; Russell, Thomas P.

2003-01-01

While the ability of proteins to self-assemble makes them powerful tools in nanotechnology, in biological systems protein-based structures ultimately depend on the context in which they form. We combine the self-assembling properties of synthetic diblock copolymers and proteins to construct intricately ordered, three-dimensional polymer protein structures with the ultimate goal of forming nano-scale devices. This hybrid approach takes advantage of the capabilities of organic polymer chemistry to build ordered structures and the capabilities of genetic engineering to create proteins that are selective for inorganic or organic substrates. Here, microphase-separated block copolymers coupled with genetically engineered heat shock proteins are used to produce nano-scale patterning that maximizes the potential for both increased structural complexity and integrity.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

Highly repeatable nanoscale phase coexistence in vanadium dioxide films

NASA Astrophysics Data System (ADS)

Huffman, T. J.; Lahneman, D. J.; Wang, S. L.; Slusar, T.; Kim, Bong-Jun; Kim, Hyun-Tak; Qazilbash, M. M.

2018-02-01

It is generally believed that in first-order phase transitions in materials with imperfections, the formation of phase domains must be affected to some extent by stochastic (probabilistic) processes. The stochasticity would lead to unreliable performance in nanoscale devices that have the potential to exploit the transformation of physical properties in a phase transition. Here we show that stochasticity at nanometer length scales is completely suppressed in the thermally driven metal-insulator transition (MIT) in sputtered vanadium dioxide (V O2 ) films. The nucleation and growth of domain patterns of metallic and insulating phases occur in a strikingly reproducible way. The completely deterministic nature of domain formation and growth in films with imperfections is a fundamental and unexpected finding about the kinetics of this material. Moreover, it opens the door for realizing reliable nanoscale devices based on the MIT in V O2 and similar phase-change materials.

Wafer-level radiometric performance testing of uncooled microbolometer arrays

NASA Astrophysics Data System (ADS)

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Epitaxial gallium arsenide wafers

NASA Technical Reports Server (NTRS)

Black, J. F.; Robinson, L. B.

1971-01-01

The preparation of GaAs epitaxial layers by a vapor transport process using AsCl3, Ga and H2 was pursued to provide epitaxial wafers suitable for the fabrication of transferred electron oscillators and amplifiers operating in the subcritical region. Both n-n(+) structures, and n(++)-n-n(+) sandwich structures were grown using n(+) (Si-doped) GaAs substrates. Process variables such as the input AsCl3 concentration, gallium temperature, and substrate temperature and temperature gradient and their effects on properties are presented and discussed.

Demonstration of lithography patterns using reflective e-beam direct write

NASA Astrophysics Data System (ADS)

Freed, Regina; Sun, Jeff; Brodie, Alan; Petric, Paul; McCord, Mark; Ronse, Kurt; Haspeslagh, Luc; Vereecke, Bart

2011-04-01

Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for high volume wafer processing. For this work, we report on the development and current status of a new maskless, direct write e-beam lithography tool which has the potential for high volume lithography at and below the 22 nm technology node. A Reflective Electron Beam Lithography (REBL) tool is being developed for high throughput electron beam direct write maskless lithography. The system is targeting critical patterning steps at the 22 nm node and beyond at a capital cost equivalent to conventional lithography. Reflective Electron Beam Lithography incorporates a number of novel technologies to generate and expose lithographic patterns with a throughput and footprint comparable to current 193 nm immersion lithography systems. A patented, reflective electron optic or Digital Pattern Generator (DPG) enables the unique approach. The Digital Pattern Generator is a CMOS ASIC chip with an array of small, independently controllable lens elements (lenslets), which act as an array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of

Advances in process overlay on 300-mm wafers

NASA Astrophysics Data System (ADS)

Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

2002-07-01

Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

NASA Astrophysics Data System (ADS)

Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

1998-06-01

Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

An evaluation method for nanoscale wrinkle

NASA Astrophysics Data System (ADS)

Liu, Y. P.; Wang, C. G.; Zhang, L. M.; Tan, H. F.

2016-06-01

In this paper, a spectrum-based wrinkling analysis method via two-dimensional Fourier transformation is proposed aiming to solve the difficulty of nanoscale wrinkle evaluation. It evaluates the wrinkle characteristics including wrinkling wavelength and direction simply using a single wrinkling image. Based on this method, the evaluation results of nanoscale wrinkle characteristics show agreement with the open experimental results within an error of 6%. It is also verified to be appropriate for the macro wrinkle evaluation without scale limitations. The spectrum-based wrinkling analysis is an effective method for nanoscale evaluation, which contributes to reveal the mechanism of nanoscale wrinkling.

Laser treatment of plasma-hydrogenated silicon wafers for thin layer exfoliation

NASA Astrophysics Data System (ADS)

Ghica, Corneliu; Nistor, Leona Cristina; Teodorescu, Valentin Serban; Maraloiu, Adrian; Vizireanu, Sorin; Scarisoreanu, Nae Doinel; Dinescu, Maria

2011-03-01

We have studied by transmission electron microscopy the microstructural effects induced by pulsed laser annealing in comparison with thermal treatments of RF plasma hydrogenated Si wafers aiming for further application in the smart-cut procedure. While thermal annealing mainly produces a slight decrease of the density of plasma-induced planar defects and an increase of the size and number of plasma-induced nanocavities in the Si matrix, pulsed laser annealing of RF plasma hydrogenated Si wafers with a 355 nm wavelength radiation results in both the healing of defects adjacent to the wafer surface and the formation of a well defined layer of nanometric cavities at a depth of 25-50 nm. In this way, a controlled fracture of single crystal layers of Si thinner than 50 nm is favored.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, C.M.; Hui, W.C.

1996-11-19

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, Conrad M.; Hui, Wing C.

1996-01-01

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Resonance ultrasonic diagnostics of defects in full-size silicon wafers

NASA Astrophysics Data System (ADS)

Belyaev, A.; Ostapenko, S.

2001-12-01

A resonance acoustic effect was observed recently in full-size 200 mm Cz-Si wafers and applied to characterize as-grown and process-induced defects. Ultrasonic vibrations can be excited into wafers using an external ultrasonic transducer and their amplitude is recorded using a scanning air-coupled acoustic probe operated in a non-contact mode. By sweeping driving frequency, f, of the transducer, we observed an amplification of a specific acoustic mode referred to as ‘whistle’. In this paper, we performed theoretical modeling of the whistle which allowed in attributing this mode to resonant flexural vibrations in a thin circular plate. We calculated normal frequencies of the flexural vibrations of a circular plate of radius ρ in the case of the free edge. The model gives an excellent fit to experimental data with regard to whistle spatial distribution. The results of calculation allow the evaluation of resonance acoustic effect in wafers of different geometries employed in the industry.

Endocytosis of Nanoscale Systems for Cancer Treatments.

PubMed

Chen, Kai; Li, Xue; Zhu, Hongyan; Gong, Qiyong; Luo, Kui

2017-04-28

Advances of nanoscale systems for cancer treatment have been involved in enabling highly regulated site-specific localization to sub cellular organelles hidden beneath cell membranes. Thus far, the cellular entry of these nanoscale systems has been not fully understood. Endocytosisis a form of active transport in which cell transports elected extracellular molecules (such as proteins, viruses, micro-organisms and nanoscale systems) are allowed into cell interiors by engulfing them in an energy-dependent process. This process appears at the plasma membrane surface and contains internalization of the cell membrane as well as the membrane proteins and lipids of cell. There are multiform pathways of endocytosis for nanoscale systems. Further comprehension for the mechanisms of endocytosis is achieved with a combination of efficient genetic manipulations, cell dynamic imaging, and chemical endocytosis inhibitors. This review provides an account of various endocytic pathways, itemizes current methods to study endocytosis of nanoscale systems, discusses some factors associated with cellular uptake for nanoscale systems and introduces the trafficking behavior for nanoscale systems with active targeting. An insight into the endocytosis mechanism is urgent and significant for developing safe and efficient nanoscale systems for cancer diagnosis and therapy. Copyright© Bentham Science Publishers; For any queries, please email at epub@benthamscience.org.

Controllable nanoscale inverted pyramids for highly efficient quasi-omnidirectional crystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Haiyuan, Xu; Sihua, Zhong; Yufeng, Zhuang; Wenzhong, Shen

2018-01-01

Nanoscale inverted pyramid structures (NIPs) have always been regarded as one of the paramount light management schemes to achieve extraordinary performance in various devices, especially in solar cells, due to their outstanding antireflection ability with relative lower surface enhancement ratio. However, current approaches to fabricating NIPs are complicated and not cost-effective for massive cell production in the photovoltaic industry. Here, controllable NIPs are fabricated on crystalline silicon (c-Si) wafers by Ag-catalyzed chemical etching and alkaline modification, which is a preferable all-solution-processed method. Through applying the NIPs to c-Si solar cells and optimizing the cell design, we have successfully achieved highly efficient textured solar cells with NIPs of a champion efficiency of 20.5%. Significantly, these NIPs are further demonstrated to possess a quasi-omnidirectional property over broad sunlight incident angles of approximately 0°-60°. Moreover, NIPs are theoretically revealed to offer light trapping advantages for ultrathin c-Si solar cells. Hence, NIPs formed by a controllable method exhibit great potential to be used in the future photovoltaic industry as surface texture.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Center for Nanoscale Science and Technology

National Institute of Standards and Technology Data Gateway

NIST Center for Nanoscale Science and Technology (Program website, free access)   Currently there is no database matching your keyword search, but the NIST Center for Nanoscale Science and Technology website may be of interest. The Center for Nanoscale Science and Technology enables science and industry by providing essential measurement methods, instrumentation, and standards to support all phases of nanotechnology development, from discovery to production.

Optical cavity furnace for semiconductor wafer processing

DOEpatents

Sopori, Bhushan L.

2014-08-05

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

"Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

NASA Astrophysics Data System (ADS)

van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

1987-01-01

An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Tip-enhanced ablation and ionization mass spectrometry for nanoscale chemical analysis

PubMed Central

Liang, Zhisen; Zhang, Shudi; Li, Xiaoping; Wang, Tongtong; Huang, Yaping; Hang, Wei; Yang, Zhilin; Li, Jianfeng; Tian, Zhongqun

2017-01-01

Spectroscopic methods with nanoscale lateral resolution are becoming essential in the fields of physics, chemistry, geology, biology, and materials science. However, the lateral resolution of laser-based mass spectrometry imaging (MSI) techniques has so far been limited to the microscale. This report presents the development of tip-enhanced ablation and ionization time-of-flight mass spectrometry (TEAI-TOFMS), using a shell-isolated apertureless silver tip. The TEAI-TOFMS results indicate the capability and reproducibility of the system for generating nanosized craters and for acquiring the corresponding mass spectral signals. Multi-elemental analysis of nine inorganic salt residues and MSI of a potassium salt residue pattern at a 50-nm lateral resolution were achieved. These results demonstrate the opportunity for the distribution of chemical compositions at the nanoscale to be visualized. PMID:29226250

Wafer-level manufacturing technology of glass microlenses

NASA Astrophysics Data System (ADS)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

NASA Astrophysics Data System (ADS)

Bakhshizadeh, N.; Sivoththaman, S.

2017-12-01

Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

Chemical method for producing smooth surfaces on silicon wafers

DOEpatents

Yu, Conrad

2003-01-01

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

PubMed

Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

2011-01-01

Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

Patterned growth of carbon nanotubes obtained by high density plasma chemical vapor deposition

NASA Astrophysics Data System (ADS)

Mousinho, A. P.; Mansano, R. D.

2015-03-01

Patterned growth of carbon nanotubes by chemical vapor deposition represents an assembly approach to place and orient nanotubes at a stage as early as when they are synthesized. In this work, the carbon nanotubes were obtained at room temperature by High Density Plasmas Chemical Vapor Deposition (HDPCVD) system. This CVD system uses a new concept of plasma generation, where a planar coil coupled to an RF system for plasma generation was used with an electrostatic shield for plasma densification. In this mode, high density plasmas are obtained. We also report the patterned growth of carbon nanotubes on full 4-in Si wafers, using pure methane plasmas and iron as precursor material (seed). Photolithography processes were used to pattern the regions on the silicon wafers. The carbon nanotubes were characterized by micro-Raman spectroscopy, the spectra showed very single-walled carbon nanotubes axial vibration modes around 1590 cm-1 and radial breathing modes (RBM) around 120-400 cm-1, confirming that high quality of the carbon nanotubes obtained in this work. The carbon nanotubes were analyzed by atomic force microscopy and scanning electron microscopy too. The results showed that is possible obtain high-aligned carbon nanotubes with patterned growth on a silicon wafer with high reproducibility and control.

Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

NASA Astrophysics Data System (ADS)

Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

2005-09-01

The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore

Wafer level reliability for high-performance VLSI design

NASA Technical Reports Server (NTRS)

Root, Bryan J.; Seefeldt, James D.

1987-01-01

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

SEM based overlay measurement between resist and buried patterns

NASA Astrophysics Data System (ADS)

Inoue, Osamu; Okagawa, Yutaka; Hasumi, Kazuhisa; Shao, Chuanyu; Leray, Philippe; Lorusso, Gian; Baudemprez, Bart

2016-03-01

With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.

Nanoscale potentiometry.

PubMed

Bakker, Eric; Pretsch, Ernö

2008-01-01

Potentiometric sensors share unique characteristics that set them apart from other electrochemical sensors. Potentiometric nanoelectrodes have been reported and successfully used for many decades, and we review these developments. Current research chiefly focuses on nanoscale films at the outer or the inner side of the membrane, with outer layers for increasing biocompatibility, expanding the sensor response, or improving the limit of detection (LOD). Inner layers are mainly used for stabilizing the response and eliminating inner aqueous contacts or undesired nanoscale layers of water. We also discuss the ultimate detectability of ions with such sensors and the power of coupling the ultra-low LODs of ion-selective electrodes with nanoparticle labels to give attractive bioassays that can compete with state-of-the-art electrochemical detection.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Local interstitial delivery of z-butylidenephthalide by polymer wafers against malignant human gliomas

PubMed Central

Harn, Horng-Jyh; Lin, Shinn-Zong; Lin, Po-Cheng; Liu, Cyong-Yue; Liu, Po-Yen; Chang, Li-Fu; Yen, Ssu-Yin; Hsieh, Dean-Kuo; Liu, Fu-Chen; Tai, Dar-Fu; Chiou, Tzyy-Wen

2011-01-01

We have shown that the natural compound z-butylidenephthalide (Bdph), isolated from the chloroform extract of Angelica sinensis, has antitumor effects. Because of the limitation of the blood-brain barrier, the Bdph dosage required for treatment of glioma is relatively high. To solve this problem, we developed a local-release system with Bdph incorporated into a biodegradable polyanhydride material, p(CPP-SA; Bdph-Wafer), and investigated its antitumor effects. On the basis of in vitro release kinetics, we demonstrated that the Bdph-Wafer released 50% of the available Bdph by the sixth day, and the release reached a plateau phase (90% of Bdph) by the 30th day. To investigate the in situ antitumor effects of the Bdph-Wafer on glioblastoma multiforme (GBM), we used 2 xenograft animal models—F344 rats (for rat GBM) and nude mice (for human GBM)—which were injected with RG2 and DBTRG-05MG cells, respectively, for tumor formation and subsequently treated subcutaneously with Bdph-Wafers. We observed a significant inhibitory effect on tumor growth, with no significant adverse effects on the rodents. Moreover, we demonstrated that the antitumor effect of Bdph on RG2 cells was via the PKC pathway, which upregulated Nurr77 and promoted its translocation from the nucleus to the cytoplasm. Finally, to study the effect of the interstitial administration of Bdph in cranial brain tumor, Bdph-Wafers were surgically placed in FGF-SV40 transgenic mice. Our Bdph-Wafer significantly reduced tumor size in a dose-dependent manner. In summary, our study showed that p(CPP-SA) containing Bdph delivered a sufficient concentration of Bdph to the tumor site and effectively inhibited the tumor growth in the glioma. PMID:21565841

Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

NASA Technical Reports Server (NTRS)

1979-01-01

Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

NASA Technical Reports Server (NTRS)

1978-01-01

Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

NASA Astrophysics Data System (ADS)

Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

2017-04-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

Wafer-scale pixelated detector system

DOEpatents

Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

2017-10-17

A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Nanoscale integration is the next frontier for nanotechnology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Picraux, Samuel T

2009-01-01

Nanoscale integration of materials and structures is the next critical step to exploit the promise of nanomaterials. Many novel and fascinating properties have been revealed for nanostructured materials. But if nanotechnology is to live up to its promise we must incorporate these nanoscale building blocks into functional systems that connect to the micro- and macroscale world. To do this we will inevitably need to understand and exploit the resulting combined unique properties of these integrated nanosystems. Much science waits to be discovered in the process. Nanoscale integration extends from the synthesis and fabrication of individual nanoscale building blocks, to themore » assembly of these building blocks into composite structures, and finally to the formation of complex functional systems. As illustrated in Figure 1, the building blocks may be homogeneous or heterogeneous, the composite materials may be nanocomposite or patterned structures, and the functional systems will involve additional combinations of materials. Nanoscale integration involves assembling diverse nanoscale materials across length scales to design and achieve new properties and functionality. At each stage size-dependent properties, the influence of surfaces in close proximity, and a multitude of interfaces all come into play. Whether the final system involves coherent electrons in a quantum computing approach, the combined flow of phonons and electrons for a high efficiency thermoelectric micro-generator, or a molecular recognition structure for bio-sensing, the combined effects of size, surface, and interface will be critical. In essence, one wants to combine the novel functions available through nanoscale science to achieve unique multi-functionalities not available in bulk materials. Perhaps the best-known example of integration is that of combining electronic components together into very large scale integrated circuits (VLSI). The integrated circuit has revolutionized electronics

Dynamic Control over the Optical Transmission of Nanoscale Dielectric Metasurface by Alkali Vapors.

PubMed

Bar-David, Jonathan; Stern, Liron; Levy, Uriel

2017-02-08

In recent years, dielectric and metallic nanoscale metasurfaces are attracting growing attention and are being used for variety of applications. Resulting from the ability to introduce abrupt changes in optical properties at nanoscale dimensions, metasurfaces enable unprecedented control over light's different degrees of freedom, in an essentially two-dimensional configuration. Yet, the dynamic control over metasurface properties still remains one of the ultimate goals of this field. Here, we demonstrate the optical resonant interaction between a form birefringent dielectric metasurface made of silicon and alkali atomic vapor to control and effectively tune the optical transmission pattern initially generated by the nanoscale dielectric metasurface. By doing so, we present a controllable metasurface system, the output of which may be altered by applying magnetic fields, changing input polarization, or shifting the optical frequency. Furthermore, we also demonstrate the nonlinear behavior of our system taking advantage of the saturation effect of atomic transition. The demonstrated approach paves the way for using metasurfaces in applications where dynamic tunability of the metasurface is in need, for example, for scanning systems, tunable focusing, real time displays, and more.

Non-Reciprocal on Wafer Microwave Devices

DTIC Science & Technology

2015-05-27

filter uses a barium hexagonal ferrite film incorporated into the dielectric layer of a microstrip transmission line. The zero-field operational...Fal,, Robert E. Camley. Millimeter wave phase shifter based on ferromagnetic resonancein a hexagonal barium ferrite thin film, Applied Physics...materials for on-wafer microwave devices concentrated on barium hexagonal ferrite (BaM) films grown on Si because these material is a good candidate

NANOSCALE BIOSENSORS IN ECOSYSTEM EXPOSURE RESEARCH

EPA Science Inventory

This powerpoint presentation presented information on nanoscale biosensors in ecosystem exposure research. The outline of the presentation is as follows: nanomaterials environmental exposure research; US agencies involved in nanosensor research; nanoscale LEDs in biosensors; nano...

Electrically controlled lens and prism using nanoscale polymer-dispersed and polymer-networked liquid crystals

NASA Astrophysics Data System (ADS)

Fan, Yun Hsing; Ren, Hongwen; Wu, Shin Tson

2004-05-01

Inhomogeneous nanoscale polymer-dispersed liquid crystal (PDLC) devices having gradient nanoscale droplet distribution were fabricated. This gradient refractive index nanoscale (GRIN) PDLC film was obtained by exposing the LC/ monomer with a uniform ultraviolet (UV) light through a patterned photomask. The monomer and LC were mixed at 70: 30 wt% ratio. The area exposed to a weaker UV intensity would produce a larger droplet size, and vice versa. Owing to the nanoscale LC droplets involved, the GRIN PDLC devices are highly transparent in the whole visible region. The gradient refractive index profile can be used as switchable prism gratings, Fresnel lens, and positive and negative lenses with tunable focal lengths. Such a GRIN PDLC device is a broadband device and independent of light polarization. The diffraction efficiency of the lens is controllable by the applied voltage. The major advantages of the GRIN PDLC devices are in simple fabrication process, polarization-independent, and fast switching speed, although the required driving voltage is higher than 100 Vrms. To lower the driving voltage, the technique of polymer-networked liquid crystal (PNLC) has been developed. The PNLC was also produced by exposing the LC/monomer mixture with a uniform UV light through a patterned photomask. However, the monomer concentration in PNLC is only around 2-5 wt%. The formed PNLC structure exhibits a gradient polymer network distribution. The LC in the regions stabilized by a higher polymer concentration exhibits a higher threshold voltage. By using this technique, prism grating, tunable electronic lens and Fresnel lens have been demonstrated. The driving voltage is around 10 Vrms. A drawback of this kind of device is polarization dependence. To overcome the polarization dependence, stacking two orthogonal homogeneous PNLC lens is considered.

Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

NASA Astrophysics Data System (ADS)

Lysaght, Patrick S.; Ybarra, Israel; Sax, Harry; Gupta, Gaurav; West, Michael; Doros, Theodore G.; Beach, James V.; Mello, Jim

2000-06-01

The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N2) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan IIITM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface

Low-Temperature Selective Growth of Tungsten Oxide Nanowires by Controlled Nanoscale Stress Induction

PubMed Central

Na, Hyungjoo; Eun, Youngkee; Kim, Min-Ook; Choi, Jungwook; Kim, Jongbaeg

2015-01-01

We report a unique approach for the patterned growth of single-crystalline tungsten oxide (WOx) nanowires based on localized stress-induction. Ions implanted into the desired growth area of WOx thin films lead to a local increase in the compressive stress, leading to the growth of nanowire at lower temperatures (600 °C vs. 750–900 °C) than for equivalent non-implanted samples. Nanowires were successfully grown on the microscale patterns using wafer-level ion implantation and on the nanometer scale patterns using a focused ion beam (FIB). Experimental results show that nanowire growth is influenced by a number of factors including the dose of the implanted ions and their atomic radius. The implanted-ion-assisted, stress-induced method proposed here for the patterned growth of WOx nanowires is simpler than alternative approaches and enhances the compatibility of the process by reducing the growth temperature. PMID:26666843

The CD control improvement by using CDSEM 2D measurement of complex OPC patterns

NASA Astrophysics Data System (ADS)

Chou, William; Cheng, Jeffrey; Lee, Adder; Cheng, James; Tzeng, Alex C.; Lu, Colbert; Yang, Ray; Lee, Hong Jen; Bandoh, Hideaki; Santo, Izumi; Zhang, Hao; Chen, Chien Kang

2016-10-01

As the process node becomes more advanced, the accuracy and precision in OPC pattern CD are required in mask manufacturing. CD SEM is an essential tool to confirm the mask quality such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in some cases of arbitrary enclosed patterns or aggressive OPC patterns, for instance, line with tiny jogs and curvilinear SRAF, CD variation depending on region of interest (ROI) is a very serious problem in mask CD control, even it decreases the wafer yield. For overcoming this situation, the 2-dimensional (2D) method by Holon is adopted. In this paper, we summarize the comparisons of error budget between conventional (1D) and 2D data using CD SEM and the CD performance between mask and wafer by complex OPC patterns including ILT features.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Electrical and structural investigations, and ferroelectric domains in nanoscale structures

NASA Astrophysics Data System (ADS)

Alexe, Marin

2005-03-01

Generally speaking material properties are expected to change as the characteristic dimension of a system approaches at the nanometer scale. In the case of ferroelectric materials fundamental problems such as the super-paraelectric limit, influence of the free surface and/or of the interface and bulk defects on ferroelectric switching, etc. arise when scaling the systems into the sub-100 nm range. In order to study these size effects, fabrication methods of high quality nanoscale ferroelectric crystals as well as AFM-based investigations methods have been developed in the last few years. The present talk will briefly review self-patterning and self- assembly fabrication methods, including chemical routes, morphological instability of ultrathin films, and self-assembly lift-off, employed up to the date to fabricate ferroelectric nanoscale structures with lateral size in the range of few tens of nanometers. Moreover, in depth structural and electrical investigations of interfaces performed to differentiate between intrinsic and extrinsic size effects will be also presented.

A review of nanoimprint lithography for high-volume semiconductor device manufacturing

NASA Astrophysics Data System (ADS)

Resnick, Douglas J.; Choi, Jin

2017-06-01

Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Emerging ferroelectric transistors with nanoscale channel materials: the possibilities, the limitations

NASA Astrophysics Data System (ADS)

Hong, Xia

2016-03-01

Combining the nonvolatile, locally switchable polarization field of a ferroelectric thin film with a nanoscale electronic material in a field effect transistor structure offers the opportunity to examine and control a rich variety of mesoscopic phenomena and interface coupling. It is also possible to introduce new phases and functionalities into these hybrid systems through rational design. This paper reviews two rapidly progressing branches in the field of ferroelectric transistors, which employ two distinct classes of nanoscale electronic materials as the conducting channel, the two-dimensional (2D) electron gas graphene and the strongly correlated transition metal oxide thin films. The topics covered include the basic device physics, novel phenomena emerging in the hybrid systems, critical mechanisms that control the magnitude and stability of the field effect modulation and the mobility of the channel material, potential device applications, and the performance limitations of these devices due to the complex interface interactions and challenges in achieving controlled materials properties. Possible future directions for this field are also outlined, including local ferroelectric gate control via nanoscale domain patterning and incorporating other emergent materials in this device concept, such as the simple binary ferroelectrics, layered 2D transition metal dichalcogenides, and the 4d and 5d heavy metal compounds with strong spin-orbit coupling.

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

NASA Astrophysics Data System (ADS)

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

DTIC Science & Technology

1989-12-01

perform Wafer Scale Integration on a routine basis is being vigorously pursued by a number of interests in military, academic , and commercial sectors...A iliciosi rip1 St -110 illic. (;11ptai / W. -a ;,tcd Ihat Ilesc hybhrid futl liods separiltely soI lie llixiiiul’upw~v~ ielts andl ~il (otii’ie thli

External self-gettering of nickel in float zone silicon wafers

NASA Astrophysics Data System (ADS)

Gay, N.; Martinuzzi, S.

1997-05-01

During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

Degradation of bare and silanized silicon wafer surfaces by constituents of biological fluids.

PubMed

Dekeyser, C M; Buron, C C; Derclaye, S R; Jonas, A M; Marchand-Brynaert, J; Rouxhet, P G

2012-07-15

The 24 h stability of bare silicon wafers as such or silanized with CH(3)O-(CH(2)-CH(2)-O)(n)-C(3)H(6)-trichlorosilane (n=6-9) was investigated in water, NaCl, phosphate and carbonate solutions, and in phosphate buffered saline (PBS) at 37 °C (close to biological conditions regarding temperature, high ionic strength, and pH). The resulting surfaces were analyzed using ellipsometry, X-ray Reflectometry (XRR), X-ray Photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM). Incubation of the silanized wafers in phosphate solution and PBS provokes a detachment of the silane layer. This is due to a hydrolysis of Si-O bonds which is favored by the action of phosphate, also responsible for a corrosion of non-silanized wafers. The surface alteration (detachment of silane layer and corrosion of the non-silanized wafer) is also important with carbonate solution, due to a higher pH (8.3). The protection of the silicon oxide layer brought by silane against the action of the salts is noticeable for phosphate but not for carbonate. Copyright © 2012 Elsevier Inc. All rights reserved.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Nanoscale chemical mapping of laser-solubilized silk

NASA Astrophysics Data System (ADS)

Ryu, Meguya; Kobayashi, Hanae; Balčytis, Armandas; Wang, Xuewen; Vongsvivut, Jitraporn; Li, Jingliang; Urayama, Norio; Mizeikis, Vygantas; Tobin, Mark; Juodkazis, Saulius; Morikawa, Junko

2017-11-01

A water soluble amorphous form of silk was made by ultra-short laser pulse irradiation and detected by nanoscale IR mapping. An optical absorption-induced nanoscale surface expansion was probed to yield the spectral response of silk at IR molecular fingerprinting wavelengths with a high  ˜ 20 nm spatial resolution defined by the tip of the probe. Silk microtomed sections of 1-5 μm in thickness were prepared for nanoscale spectroscopy and a laser was used to induce amorphisation. Comparison of silk absorbance measurements carried out by table-top and synchrotron Fourier transform IR spectroscopy proved that chemical imaging obtained at high spatial resolution and specificity (able to discriminate between amorphous and crystalline silk) is reliably achieved by nanoscale IR. Differences in absorbance and spectral line-shapes of the bands are related to the different sensitivity of the applied methods to real and imaginary parts of permittivity. A nanoscale material characterization by combining synchrotron IR radiation and nano-IR is discussed.

Nanoscale phase change memory materials.

PubMed

Caldwell, Marissa A; Jeyasingh, Rakesh Gnana David; Wong, H-S Philip; Milliron, Delia J

2012-08-07

Phase change memory materials store information through their reversible transitions between crystalline and amorphous states. For typical metal chalcogenide compounds, their phase transition properties directly impact critical memory characteristics and the manipulation of these is a major focus in the field. Here, we discuss recent work that explores the tuning of such properties by scaling the materials to nanoscale dimensions, including fabrication and synthetic strategies used to produce nanoscale phase change memory materials. The trends that emerge are relevant to understanding how such memory technologies will function as they scale to ever smaller dimensions and also suggest new approaches to designing materials for phase change applications. Finally, the challenges and opportunities raised by integrating nanoscale phase change materials into switching devices are discussed.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Proceedings of the Low-Cost Solar Array Wafering Workshop

NASA Technical Reports Server (NTRS)

Morrison, A. D.

1982-01-01

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Fabrication of complex nanoscale structures on various substrates

NASA Astrophysics Data System (ADS)

Han, Kang-Soo; Hong, Sung-Hoon; Lee, Heon

2007-09-01

Polymer based complex nanoscale structures were fabricated and transferred to various substrates using reverse nanoimprint lithography. To facilitate the fabrication and transference of the large area of the nanostructured layer to the substrates, a water-soluble polyvinyl alcohol mold was used. After generation and transference of the nanostructured layer, the polyvinyl alcohol mold was removed by dissolving in water. A residue-free, UV-curable, glue layer was formulated and used to bond the nanostructured layer onto the substrates. As a result, nanometer scale patterned polymer layers were bonded to various substrates and three-dimensional nanostructures were also fabricated by stacking of the layers.

Controllable Nanoscale Inverted Pyramids for High-Efficient Quasi-Omnidirectional Crystalline Silicon Solar Cells.

PubMed

Xu, Haiyuan; Zhong, Sihua; Zhuang, Yufeng; Shen, Wenzhong

2017-11-14

Nanoscale inverted pyramid structures (NIPs) have always been regarded as one of the most paramount light management schemes to achieve the extraordinary performance in various devices, especially in solar cells, due to their outstanding antireflection ability with relative lower surface enhancement ratio. However, the current approaches to fabricating the NIPs are complicated and not cost-effective for the massive cell production in the photovoltaic industry. Here, controllable NIPs are fabricated on crystalline silicon (c-Si) wafers by Ag catalyzed chemical etching and alkaline modification, which is a preferable all-solution-processed method. Through applying the NIPs to c-Si solar cells and optimizing the cell design, we have successfully achieved highly efficient NIPs textured solar cells with the champion efficiency of 20.5%. Importantly, the NIPs textured solar cells are further demonstrated to possess the quasi-omnidirectional property over the broad sunlight incident angles of approximately 0°-60°. Moreover, the NIPs are theoretically revealed to offer light trapping advantage for ultrathin c-Si solar cells. Hence, the NIPs formed by the controllable method exhibit a great potential to be used in the future photovoltaic industry as surface texture. © 2017 IOP Publishing Ltd.

Fundamentals of Nanoscale Polymer–Protein Interactions and Potential Contributions to Solid-State Nanobioarrays

PubMed Central

2015-01-01

Protein adsorption onto polymer surfaces is a very complex, ubiquitous, and integrated process, impacting essential areas of food processing and packaging, health devices, diagnostic tools, and medical products. The nature of protein–surface interactions is becoming much more complicated with continuous efforts toward miniaturization, especially for the development of highly compact protein detection and diagnostic devices. A large body of literature reports on protein adsorption from the perspective of ensemble-averaged behavior on macroscopic, chemically homogeneous, polymeric surfaces. However, protein–surface interactions governing the nanoscale size regime may not be effectively inferred from their macroscopic and microscopic characteristics. Recently, research efforts have been made to produce periodically arranged, nanoscopic protein patterns on diblock copolymer surfaces solely through self-assembly. Intriguing protein adsorption phenomena are directly probed on the individual biomolecule level for a fundamental understanding of protein adsorption on nanoscale surfaces exhibiting varying degrees of chemical heterogeneity. Insight gained from protein assembly on diblock copolymers can be effectively used to control the surface density, conformation, orientation, and biofunctionality of prebound proteins in highly miniaturized applications, now approaching the nanoscale. This feature article will highlight recent experimental and theoretical advances made on these fronts while focusing on single-biomolecule-level investigations of protein adsorption behavior combined with surface chemical heterogeneity on the length scale commensurate with a single protein. This article will also address advantages and challenges of the self-assembly-driven patterning technology used to produce protein nanoarrays and its implications for ultrahigh density, functional, and quantifiable protein detection in a highly miniaturized format. PMID:24456577

Fundamentals of nanoscale polymer-protein interactions and potential contributions to solid-state nanobioarrays.

PubMed

Hahm, Jong-in

2014-08-26

Protein adsorption onto polymer surfaces is a very complex, ubiquitous, and integrated process, impacting essential areas of food processing and packaging, health devices, diagnostic tools, and medical products. The nature of protein-surface interactions is becoming much more complicated with continuous efforts toward miniaturization, especially for the development of highly compact protein detection and diagnostic devices. A large body of literature reports on protein adsorption from the perspective of ensemble-averaged behavior on macroscopic, chemically homogeneous, polymeric surfaces. However, protein-surface interactions governing the nanoscale size regime may not be effectively inferred from their macroscopic and microscopic characteristics. Recently, research efforts have been made to produce periodically arranged, nanoscopic protein patterns on diblock copolymer surfaces solely through self-assembly. Intriguing protein adsorption phenomena are directly probed on the individual biomolecule level for a fundamental understanding of protein adsorption on nanoscale surfaces exhibiting varying degrees of chemical heterogeneity. Insight gained from protein assembly on diblock copolymers can be effectively used to control the surface density, conformation, orientation, and biofunctionality of prebound proteins in highly miniaturized applications, now approaching the nanoscale. This feature article will highlight recent experimental and theoretical advances made on these fronts while focusing on single-biomolecule-level investigations of protein adsorption behavior combined with surface chemical heterogeneity on the length scale commensurate with a single protein. This article will also address advantages and challenges of the self-assembly-driven patterning technology used to produce protein nanoarrays and its implications for ultrahigh density, functional, and quantifiable protein detection in a highly miniaturized format.

The analysis method of the DRAM cell pattern hotspot

NASA Astrophysics Data System (ADS)

Lee, Kyusun; Lee, Kweonjae; Chang, Jinman; Kim, Taeheon; Han, Daehan; Hong, Aeran; Kim, Yonghyeon; Kang, Jinyoung; Choi, Bumjin; Lee, Joosung; Lee, Jooyoung; Hong, Hyeongsun; Lee, Kyupil; Jin, Gyoyoung

2015-03-01

It is increasingly difficult to determine degree of completion of the patterning and the distribution at the DRAM Cell Patterns. When we research DRAM Device Cell Pattern, there are three big problems currently, it is as follows. First, due to etch loading, it is difficult to predict the potential defect. Second, due to under layer topology, it is impossible to demonstrate the influence of the hotspot. Finally, it is extremely difficult to predict final ACI pattern by the photo simulation, because current patterning process is double patterning technology which means photo pattern is completely different from final etch pattern. Therefore, if the hotspot occurs in wafer, it is very difficult to find it. CD-SEM is the most common pattern measurement tool in semiconductor fabrication site. CD-SEM is used to accurately measure small region of wafer pattern primarily. Therefore, there is no possibility of finding places where unpredictable defect occurs. Even though, "Current Defect detector" can measure a wide area, every chip has same pattern issue, the detector cannot detect critical hotspots. Because defect detecting algorithm of bright field machine is based on image processing, if same problems occur on compared and comparing chip, the machine cannot identify it. Moreover this instrument is not distinguished the difference of distribution about 1nm~3nm. So, "Defect detector" is difficult to handle the data for potential weak point far lower than target CD. In order to solve those problems, another method is needed. In this paper, we introduce the analysis method of the DRAM Cell Pattern Hotspot.

Fabrication of ordered arrays of micro- and nanoscale features with control over their shape and size via templated solid-state dewetting.

PubMed

Ye, Jongpil

2015-05-08

Templated solid-state dewetting of single-crystal films has been shown to be used to produce regular patterns of various shapes. However, the materials for which this patterning method is applicable, and the size range of the patterns produced are still limited. Here, it is shown that ordered arrays of micro- and nanoscale features can be produced with control over their shape and size via solid-state dewetting of patches patterned from single-crystal palladium and nickel films of different thicknesses and orientations. The shape and size characteristics of the patterns are found to be widely controllable with varying the shape, width, thickness, and orientation of the initial patches. The morphological evolution of the patches is also dependent on the film material, with different dewetting behaviors observed in palladium and nickel films. The mechanisms underlying the pattern formation are explained in terms of the influence on Rayleigh-like instability of the patch geometry and the surface energy anisotropy of the film material. This mechanistic understanding of pattern formation can be used to design patches for the precise fabrication of micro- and nanoscale structures with the desired shapes and feature sizes.

Fabrication of ordered arrays of micro- and nanoscale features with control over their shape and size via templated solid-state dewetting

PubMed Central

Ye, Jongpil

2015-01-01

Templated solid-state dewetting of single-crystal films has been shown to be used to produce regular patterns of various shapes. However, the materials for which this patterning method is applicable, and the size range of the patterns produced are still limited. Here, it is shown that ordered arrays of micro- and nanoscale features can be produced with control over their shape and size via solid-state dewetting of patches patterned from single-crystal palladium and nickel films of different thicknesses and orientations. The shape and size characteristics of the patterns are found to be widely controllable with varying the shape, width, thickness, and orientation of the initial patches. The morphological evolution of the patches is also dependent on the film material, with different dewetting behaviors observed in palladium and nickel films. The mechanisms underlying the pattern formation are explained in terms of the influence on Rayleigh-like instability of the patch geometry and the surface energy anisotropy of the film material. This mechanistic understanding of pattern formation can be used to design patches for the precise fabrication of micro- and nanoscale structures with the desired shapes and feature sizes. PMID:25951816

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Influence of Si wafer thinning processes on (sub)surface defects

NASA Astrophysics Data System (ADS)

Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira

2017-05-01

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5-2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

Nanoscale chemical imaging by photoinduced force microscopy

PubMed Central

Nowak, Derek; Morrison, William; Wickramasinghe, H. Kumar; Jahng, Junghoon; Potma, Eric; Wan, Lei; Ruiz, Ricardo; Albrecht, Thomas R.; Schmidt, Kristin; Frommer, Jane; Sanders, Daniel P.; Park, Sung

2016-01-01

Correlating spatial chemical information with the morphology of closely packed nanostructures remains a challenge for the scientific community. For example, supramolecular self-assembly, which provides a powerful and low-cost way to create nanoscale patterns and engineered nanostructures, is not easily interrogated in real space via existing nondestructive techniques based on optics or electrons. A novel scanning probe technique called infrared photoinduced force microscopy (IR PiFM) directly measures the photoinduced polarizability of the sample in the near field by detecting the time-integrated force between the tip and the sample. By imaging at multiple IR wavelengths corresponding to absorption peaks of different chemical species, PiFM has demonstrated the ability to spatially map nm-scale patterns of the individual chemical components of two different types of self-assembled block copolymer films. With chemical-specific nanometer-scale imaging, PiFM provides a powerful new analytical method for deepening our understanding of nanomaterials. PMID:27051870

Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

NASA Astrophysics Data System (ADS)

Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

2016-04-01

A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

Engineering nanoscale stem cell niche: direct stem cell behavior at cell-matrix interface.

PubMed

Zhang, Yan; Gordon, Andrew; Qian, Weiyi; Chen, Weiqiang

2015-09-16

Biophysical cues on the extracellular matrix (ECM) have proven to be significant regulators of stem cell behavior and evolution. Understanding the interplay of these cells and their extracellular microenvironment is critical to future tissue engineering and regenerative medicine, both of which require a means of controlled differentiation. Research suggests that nanotopography, which mimics the local, nanoscale, topographic cues within the stem cell niche, could be a way to achieve large-scale proliferation and control of stem cells in vitro. This Progress Report reviews the history and contemporary advancements of this technology, and pays special attention to nanotopographic fabrication methods and the effect of different nanoscale patterns on stem cell response. Finally, it outlines potential intracellular mechanisms behind this response. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

NASA Technical Reports Server (NTRS)

Anthony, Thomas R. (Inventor)

1983-01-01

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

1.3-microm optically-pumped semiconductor disk laser by wafer fusion.

PubMed

Lyytikäinen, Jari; Rautiainen, Jussi; Toikkanen, Lauri; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

2009-05-25

We report a wafer-fused high power optically-pumped semiconductor disk laser operating at 1.3 microm. An InP-based active medium was fused with a GaAs/AlGaAs distributed Bragg reflector, resulting in an integrated monolithic gain mirror. Over 2.7 W of output power, obtained at temperature of 15 degrees C, represents the best achievement reported to date for this type of lasers. The results reveal an essential advantage of the wafer fusing technique over both monolithically grown AlGaInAs/GaInAsP- and GaInNAs-based structures.

Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hegedus, Steven S.

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and

Wafer-scale growth of VO2 thin films using a combinatorial approach

PubMed Central

Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

2015-01-01

Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

Atomistic Design and Simulations of Nanoscale Machines and Assembly

NASA Technical Reports Server (NTRS)

Goddard, William A., III; Cagin, Tahir; Walch, Stephen P.

2000-01-01

Over the three years of this project, we made significant progress on critical theoretical and computational issues in nanoscale science and technology, particularly in:(1) Fullerenes and nanotubes, (2) Characterization of surfaces of diamond and silicon for NEMS applications, (3) Nanoscale machine and assemblies, (4) Organic nanostructures and dendrimers, (5) Nanoscale confinement and nanotribology, (6) Dynamic response of nanoscale structures nanowires (metals, tubes, fullerenes), (7) Thermal transport in nanostructures.

Methods and devices for fabricating three-dimensional nanoscale structures

DOEpatents

Rogers, John A.; Jeon, Seokwoo; Park, Jangung

2010-04-27

The present invention provides methods and devices for fabricating 3D structures and patterns of 3D structures on substrate surfaces, including symmetrical and asymmetrical patterns of 3D structures. Methods of the present invention provide a means of fabricating 3D structures having accurately selected physical dimensions, including lateral and vertical dimensions ranging from 10s of nanometers to 1000s of nanometers. In one aspect, methods are provided using a mask element comprising a conformable, elastomeric phase mask capable of establishing conformal contact with a radiation sensitive material undergoing photoprocessing. In another aspect, the temporal and/or spatial coherence of electromagnetic radiation using for photoprocessing is selected to fabricate complex structures having nanoscale features that do not extend entirely through the thickness of the structure fabricated.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

Differences between wafer and bake plate temperature uniformity in proximity bake: a theoretical and experimental study

NASA Astrophysics Data System (ADS)

Ramanan, Natarajan; Kozman, Austin; Sims, James B.

2000-06-01

As the lithography industry moves toward finer features, specifications on temperature uniformity of the bake plates are expected to become more stringent. Consequently, aggressive improvements are needed to conventional bake station designs to make them perform significantly better than current market requirements. To this end, we have conducted a rigorous study that combines state-of-the-art simulation tools and experimental methods to predict the impact of the parameters that influence the uniformity of the wafer in proximity bake. The key observation from this detailed study is that the temperature uniformity of the wafer in proximity mode depends on a number of parameters in addition to the uniformity of the bake plate itself. These parameters include the lid design, the air flow distribution around the bake chamber, bake plate design and flatness of the bake plate and wafer. By performing careful experimental studies that were guided by extensive numerical simulations, we were able to understand the relative importance of each of these parameters. In an orderly fashion, we made appropriate design changes to curtail or eliminate the nonuniformity caused by each of these parameters. After implementing all these changes, we have now been able to match or improve the temperature uniformity of the wafer in proximity with that of a contact measurement on the bake plate. The wafer temperature uniformity is also very close to the theoretically predicted uniformity of the wafer.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

NASA Astrophysics Data System (ADS)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

EDITORIAL: Nanoscale metrology Nanoscale metrology

NASA Astrophysics Data System (ADS)

Picotto, G. B.; Koenders, L.; Wilkening, G.

2009-08-01

Instrumentation and measurement techniques at the nanoscale play a crucial role not only in extending our knowledge of the properties of matter and processes in nanosciences, but also in addressing new measurement needs in process control and quality assurance in industry. Micro- and nanotechnologies are now facing a growing demand for quantitative measurements to support the reliability, safety and competitiveness of products and services. Quantitative measurements presuppose reliable and stable instruments and measurement procedures as well as suitable calibration artefacts to ensure the quality of measurements and traceability to standards. This special issue of Measurement Science and Technology presents selected contributions from the Nanoscale 2008 seminar held at the Istituto Nazionale di Ricerca Metrologica (INRIM), Torino, in September 2008. This was the 4th Seminar on Nanoscale Calibration Standards and Methods and the 8th Seminar on Quantitative Microscopy (the first being held in 1995). The seminar was jointly organized by the Nanometrology Group within EUROMET (The European Collaboration in Measurement Standards), the German Nanotechnology Competence Centre 'Ultraprecise Surface Figuring' (CC-UPOB), the Physikalisch-Technische Bundesanstalt (PTB) and INRIM. A special event during the seminar was the 'knighting' of Günter Wilkening from PTB, Braunschweig, Germany, as the 1st Knight of Dimensional Nanometrology. Günter Wilkening received the NanoKnight Award for his outstanding work in the field of dimensional nanometrology over the last 20 years. The contributions in this special issue deal with the developments and improvements of instrumentation and measurement methods for scanning force microscopy (SFM), electron and optical microscopy, high-resolution interferometry, calibration of instruments and new standards, new facilities and applications including critical dimension (CD) measurements on small and medium structures and nanoparticle

Wafer-Scale Integration of Systolic Arrays,

DTIC Science & Technology

1985-10-01

hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

Dynamics of systems on the nanoscale

NASA Astrophysics Data System (ADS)

Korol, Andrei V.; Solov'yov, Andrey V.

2017-12-01

Various aspects of the structure formation and dynamics of animate and inanimate matter on the nanoscale is a highly interdisciplinary field of rapidly emerging research interest by both experimentalists and theorists. The International Conference on Dynamics of Systems on the Nanoscale (DySoN) is the premier forum to present cutting-edge research in this field. It was established in 2010 and the most recent conference was held in Bad Ems, Germany in October of 2016. This Topical Issue presents original research results from some of the participants, who attended this conference. Contribution to the Topical Issue "Dynamics of Systems at the Nanoscale", edited by Andrey Solov'yov and Andrei Korol.

A statistical nanomechanism of biomolecular patterning actuated by surface potential

NASA Astrophysics Data System (ADS)

Lin, Chih-Ting; Lin, Chih-Hao

2011-02-01

Biomolecular patterning on a nanoscale/microscale on chip surfaces is one of the most important techniques used in vitro biochip technologies. Here, we report upon a stochastic mechanics model we have developed for biomolecular patterning controlled by surface potential. The probabilistic biomolecular surface adsorption behavior can be modeled by considering the potential difference between the binding and nonbinding states. To verify our model, we experimentally implemented a method of electroactivated biomolecular patterning technology and the resulting fluorescence intensity matched the prediction of the developed model quite well. Based on this result, we also experimentally demonstrated the creation of a bovine serum albumin pattern with a width of 200 nm in 5 min operations. This submicron noncovalent-binding biomolecular pattern can be maintained for hours after removing the applied electrical voltage. These stochastic understandings and experimental results not only prove the feasibility of submicron biomolecular patterns on chips but also pave the way for nanoscale interfacial-bioelectrical engineering.

Switchable static friction of piezoelectric composite—silicon wafer contacts

NASA Astrophysics Data System (ADS)

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

Sulfur passivation techniques for III-V wafer bonding

NASA Astrophysics Data System (ADS)

Jackson, Michael James

The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the

From Lab to Fab: Developing a Nanoscale Delivery Tool for Scalable Nanomanufacturing

NASA Astrophysics Data System (ADS)

Safi, Asmahan A.

The emergence of nanomaterials with unique properties at the nanoscale over the past two decades carries a capacity to impact society and transform or create new industries ranging from nanoelectronics to nanomedicine. However, a gap in nanomanufacturing technologies has prevented the translation of nanomaterial into real-world commercialized products. Bridging this gap requires a paradigm shift in methods for fabricating structured devices with a nanoscale resolution in a repeatable fashion. This thesis explores the new paradigms for fabricating nanoscale structures devices and systems for high throughput high registration applications. We present a robust and scalable nanoscale delivery platform, the Nanofountain Probe (NFP), for parallel direct-write of functional materials. The design and microfabrication of NFP is presented. The new generation addresses the challenges of throughput, resolution and ink replenishment characterizing tip-based nanomanufacturing. To achieve these goals, optimized probe geometry is integrated to the process along with channel sealing and cantilever bending. The capabilities of the newly fabricated probes are demonstrated through two type of delivery: protein nanopatterning and single cell nanoinjection. The broad applications of the NFP for single cell delivery are investigated. An external microfluidic packaging is developed to enable delivery in liquid environment. The system is integrated to a combined atomic force microscope and inverted fluorescence microscope. Intracellular delivery is demonstrated by injecting a fluorescent dextran into Hela cells in vitro while monitoring the injection forces. Such developments enable in vitro cellular delivery for single cell studies and high throughput gene expression. The nanomanufacturing capabilities of NFPs are explored. Nanofabrication of carbon nanotube-based electronics presents all the manufacturing challenges characterizing of assembling nanomaterials precisely onto devices. The

[Smart drug delivery systems based on nanoscale ZnO].

PubMed

Huang, Xiao; Chen, Chun; Yi, Caixia; Zheng, Xi

2018-04-01

In view of the excellent biocompatibility as well as the low cost, nanoscale ZnO shows great potential for drug delivery application. Moreover, The charming character enable nanoscale ZnO some excellent features (e.g. dissolution in acid, ultrasonic permeability, microwave absorbing, hydrophobic/hydrophilic transition). All of that make nanoscale ZnO reasonable choices for smart drug delivery. In the recent decade, more and more studies have focused on controlling the drug release behavior via smart drug delivery systems based on nanoscale ZnO responsive to some certain stimuli. Herein, we review the recent exciting progress on the pH-responsive, ultrasound-responsive, microwave-responsive and UV-responsive nanoscale ZnO-based drug delivery systems. A brief introduction of the drug controlled release behavior and its effect of the drug delivery systems is presented. The biocompatibility of nanoscale ZnO is also discussed. Moreover, its development prospect is looked forward.

An RNAi Screen for Genes Involved in Nanoscale Protrusion Formation on Corneal Lens in Drosophila melanogaster.

PubMed

Minami, Ryunosuke; Sato, Chiaki; Yamahama, Yumi; Kubo, Hideo; Hariyama, Takahiko; Kimura, Ken-Ichi

2016-12-01

The "moth-eye" structure, which is observed on the surface of corneal lens in several insects, supports anti-reflective and self-cleaning functions due to nanoscale protrusions known as corneal nipples. Although the morphology and function of the "moth-eye" structure, are relatively well studied, the mechanism of protrusion formation from cell-secreted substances is unknown. In Drosophila melanogaster, a compound eye consists of approximately 800 facets, the surface of which is formed by the corneal lens with nanoscale protrusions. In the present study, we sought to identify genes involved in "moth-eye" structure, formation in order to elucidate the developmental mechanism of the protrusions in Drosophila. We re-examined the aberrant patterns in classical glossy-eye mutants by scanning electron microscope and classified the aberrant patterns into groups. Next, we screened genes encoding putative structural cuticular proteins and genes involved in cuticular formation using eye specific RNAi silencing methods combined with the Gal4/UAS expression system. We identified 12 of 100 candidate genes, such as cuticular proteins family genes (Cuticular protein 23B and Cuticular protein 49Ah), cuticle secretion-related genes (Syntaxin 1A and Sec61 ββ subunit), ecdysone signaling and biosynthesis-related genes (Ecdysone receptor, Blimp-1, and shroud), and genes involved in cell polarity/cell architecture (Actin 5C, shotgun, armadillo, discs large1, and coracle). Although some of the genes we identified may affect corneal protrusion formation indirectly through general patterning defects in eye formation, these initial findings have encouraged us to more systematically explore the precise mechanisms underlying the formation of nanoscale protrusions in Drosophila.

Indium-tin-oxide nanowhiskers crystalline silicon photovoltaics combining micro- and nano-scale surface textures

NASA Astrophysics Data System (ADS)

Chang, C. H.; Hsu, M. H.; Chang, W. L.; Sun, W. C.; Yu, Peichen

2011-02-01

In this work, we present a solution that employs combined micro- and nano-scale surface textures to increase light harvesting in the near infrared for crystalline silicon photovoltaics, and discuss the associated antireflection and scattering mechanisms. The combined surface textures are achieved by uniformly depositing a layer of indium-tin-oxide nanowhiskers on passivated, micro-grooved silicon solar cells using electron-beam evaporation. The nanowhiskers facilitate optical transmission in the near-infrared, which is optically equivalent to a stack of two dielectric thin-films with step- and graded- refractive index profiles. The ITO nanowhiskers provide broadband anti-reflective properties (R<5%) in the wavelength range of 350-1100nm. In comparison with conventional Si solar cell, the combined surface texture solar cell shows higher external quantum efficiency (EQE) in the range of 700-1100nm. Moreover, the ITO nano-whisker coating Si solar cell shows a high total efficiency increase of 1.1% (from 16.08% to17.18%). Furthermore, the nano-whiskers also provide strong forward scattering for ultraviolet and visible light, favorable in thin-wafer silicon photovoltaics to increase the optical absorption path.

Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

PubMed Central

Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

2013-01-01

Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

NASA Astrophysics Data System (ADS)

Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

2003-09-01

The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

EDITORIAL: Nanoscale metrology Nanoscale metrology

NASA Astrophysics Data System (ADS)

Klapetek, P.; Koenders, L.

2011-09-01

This special issue of Measurement Science and Technology presents selected contributions from the NanoScale 2010 seminar held in Brno, Czech Republic. It was the 5th Seminar on Nanoscale Calibration Standards and Methods and the 9th Seminar on Quantitative Microscopy (the first being held in 1995). The seminar was jointly organized with the Czech Metrology Institute (CMI) and the Nanometrology Group of the Technical Committee-Length of EURAMET. There were two workshops that were integrated into NanoScale 2010: first a workshop presenting the results obtained in NANOTRACE, a European Metrology Research Project (EMRP) on displacement-measuring optical interferometers, and second a workshop about the European metrology landscape in nanometrology related to thin films, scanning probe microscopy and critical dimension. The aim of this workshop was to bring together developers, applicants and metrologists working in this field of nanometrology and to discuss future needs. For more information see www.co-nanomet.eu. The articles in this special issue of Measurement Science and Technology cover some novel scientific results. This issue can serve also as a representative selection of topics that are currently being investigated in the field of European and world-wide nanometrology. Besides traditional topics of dimensional metrology, like development of novel interferometers or laser stabilization techniques, some novel interesting trends in the field of nanometrology are observed. As metrology generally reflects the needs of scientific and industrial research, many research topics addressed refer to current trends in nanotechnology, too, focusing on traceability and improved measurement accuracy in this field. While historically the most studied standards in nanometrology were related to simple geometric structures like step heights or 1D or 2D gratings, now we are facing tasks to measure 3D structures and many unforeseen questions arising from interesting physical

Can amorphization take place in nanoscale interconnects?

PubMed

Kumar, S; Joshi, K L; van Duin, A C T; Haque, M A

2012-03-09

The trend of miniaturization has highlighted the problems of heat dissipation and electromigration in nanoelectronic device interconnects, but not amorphization. While amorphization is known to be a high pressure and/or temperature phenomenon, we argue that defect density is the key factor, while temperature and pressure are only the means. For nanoscale interconnects carrying modest current density, large vacancy concentrations may be generated without the necessity of high temperature or pressure due to the large fraction of grain boundaries and triple points. To investigate this hypothesis, we performed in situ transmission electron microscope (TEM) experiments on 200 nm thick (80 nm average grain size) aluminum specimens. Electron diffraction patterns indicate partial amorphization at modest current density of about 10(5) A cm(-2), which is too low to trigger electromigration. Since amorphization results in drastic decrease in mechanical ductility as well as electrical and thermal conductivity, further increase in current density to about 7 × 10(5) A cm(-2) resulted in brittle fracture failure. Our molecular dynamics (MD) simulations predict the formation of amorphous regions in response to large mechanical stresses (due to nanoscale grain size) and excess vacancies at the cathode side of the thin films. The findings of this study suggest that amorphization can precede electromigration and thereby play a vital role in the reliability of micro/nanoelectronic devices.

Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

NASA Astrophysics Data System (ADS)

Fan, Shu-Kai S.; Tsai, Du-Ming; Chuang, Wei-Che

2017-04-01

Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.

Low Dose X-Ray Speckle Visibility Spectroscopy Reveals Nanoscale Dynamics in Radiation Sensitive Ionic Liquids

NASA Astrophysics Data System (ADS)

Verwohlt, Jan; Reiser, Mario; Randolph, Lisa; Matic, Aleksandar; Medina, Luis Aguilera; Madsen, Anders; Sprung, Michael; Zozulya, Alexey; Gutt, Christian

2018-04-01

X-ray radiation damage provides a serious bottleneck for investigating microsecond to second dynamics on nanometer length scales employing x-ray photon correlation spectroscopy. This limitation hinders the investigation of real time dynamics in most soft matter and biological materials which can tolerate only x-ray doses of kGy and below. Here, we show that this bottleneck can be overcome by low dose x-ray speckle visibility spectroscopy. Employing x-ray doses of 22-438 kGy and analyzing the sparse speckle pattern of count rates as low as 6.7 ×10-3 per pixel, we follow the slow nanoscale dynamics of an ionic liquid (IL) at the glass transition. At the prepeak of nanoscale order in the IL, we observe complex dynamics upon approaching the glass transition temperature TG with a freezing in of the alpha relaxation and a multitude of millisecond local relaxations existing well below TG . We identify this fast relaxation as being responsible for the increasing development of nanoscale order observed in ILs at temperatures below TG .

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

NASA Astrophysics Data System (ADS)

Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

2006-11-01

In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

New directions for nanoscale thermoelectric materials research

NASA Technical Reports Server (NTRS)

Dresselhaus, M. S.; Chen, G.; Tang, M. Y.; Yang, R. G.; Lee, H.; Wang, D. Z.; Ren, F.; Fleurial, J. P.; Gogna, P.

2005-01-01

Many of the recent advances in enhancing the thermoelectric figure of merit are linked to nanoscale phenomena with both bulk samples containing nanoscale constituents and nanoscale materials exhibiting enhanced thermoelectric performance in their own right. Prior theoretical and experimental proof of principle studies on isolated quantum well and quantum wire samples have now evolved into studies on bulk samples containing nanostructured constituents. In this review, nanostructural composites are shown to exhibit nanostructures and properties that show promise for thermoelectric applications. A review of some of the results obtained to date are presented.

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

A method for determining average damage depth of sawn crystalline silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B.; Devayajanam, S.; Basnyat, P.

2016-04-01

The depth of surface damage (or simply, damage) in crystalline silicon wafers, caused by wire sawing of ingots, is determined by performing a series of minority carrier lifetime (MCLT) measurements. Samples are sequentially etched to remove thin layers from each surface and MCLT is measured after each etch step. The thickness-removed (..delta..t) at which the lifetime reaches a peak value corresponds to the damage depth. This technique also allows the damage to be quantified in terms of effective surface recombination velocity (Seff). To accomplish this, the MCLT data are converted into an Seff vs ..delta..t plot, which represents a quantitativemore » distribution of the degree of damage within the surface layer. We describe a wafer preparation procedure to attain reproducible etching and MCLT measurement results. We also describe important characteristics of an etchant used for controllably removing thin layers from the wafer surfaces. Some typical results showing changes in the MCLT vs ..delta..t plots for different cutting parameters are given.« less

Optimization of corn, rice and buckwheat formulations for gluten-free wafer production.

PubMed

Dogan, Ismail Sait; Yildiz, Onder; Meral, Raciye

2016-07-01

Gluten-free baked products for celiac sufferers are essential for healthy living. Cereals having gluten such as wheat and rye must be removed from the diet for the clinical and histological improvement. The variety of gluten-free foods should be offered for the sufferers. In the study, gluten-free wafer formulas were optimized using corn, rice and buckwheat flours, xanthan and guar gum blend as an alternative product for celiac sufferers. Wafer sheet attributes and textural properties were investigated. Considering all wafer sheet properties in gluten-free formulas, better results were obtained by using 163.5% water, 0.5% guar and 0.1% xanthan in corn formula; 173.3% water, 0.45% guar and 0.15% xanthan gum in rice formula; 176% water, 0.1% guar and 0.5% xanthan gum in buckwheat formula. Average desirability values in gluten-free formulas were between 0.86 and 0.91 indicating they had similar visual and textural profiles to control sheet made with wheat flour. © The Author(s) 2015.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Influence of different aspect ratios on the structural and electrical properties of GaN thin films grown on nanoscale-patterned sapphire substrates

NASA Astrophysics Data System (ADS)

Lee, Fang-Wei; Ke, Wen-Cheng; Cheng, Chun-Hong; Liao, Bo-Wei; Chen, Wei-Kuo

2016-07-01

This study presents GaN thin films grown on nanoscale-patterned sapphire substrates (NPSSs) with different aspect ratios (ARs) using a homemade metal-organic chemical vapor deposition system. The anodic aluminum oxide (AAO) technique is used to prepare the dry etching mask. The cross-sectional view of the scanning electron microscope image shows that voids exist between the interface of the GaN thin film and the high-AR (i.e. ∼2) NPSS. In contrast, patterns on the low-AR (∼0.7) NPSS are filled full of GaN. The formation of voids on the high-AR NPSS is believed to be due to the enhancement of the lateral growth in the initial growth stage, and the quick-merging GaN thin film blocks the precursors from continuing to supply the bottom of the pattern. The atomic force microscopy images of GaN on bare sapphire show a layer-by-layer surface morphology, which becomes a step-flow surface morphology for GaN on a high-AR NPSS. The edge-type threading dislocation density can be reduced from 7.1 × 108 cm-2 for GaN on bare sapphire to 4.9 × 108 cm-2 for GaN on a high-AR NPSS. In addition, the carrier mobility increases from 85 cm2/Vs for GaN on bare sapphire to 199 cm2/Vs for GaN on a high-AR NPSS. However, the increased screw-type threading dislocation density for GaN on a low-AR NPSS is due to the competition of lateral growth on the flat-top patterns and vertical growth on the bottom of the patterns that causes the material quality of the GaN thin film to degenerate. Thus, the experimental results indicate that the AR of the particular patterning of a NPSS plays a crucial role in achieving GaN thin film with a high crystalline quality.

Plastic deformation in nanoscale gold single crystals and open-celled nanoporous gold

NASA Astrophysics Data System (ADS)

Lee, Dongyun; Wei, Xiaoding; Zhao, Manhong; Chen, Xi; Jun, Seong C.; Hone, James; Kysar, Jeffrey W.

2007-01-01

The results of two sets of experiments to measure the elastic-plastic behaviour of gold at the nanometre length scale are reported. One set of experiments was on free-standing nanoscale single crystals of gold, and the other was on free-standing nanoscale specimens of open-celled nanoporous gold. Both types of specimens were fabricated from commercially available leaf which was either pure Au or a Au/Ag alloy following by dealloying of the Ag. Mechanical testing specimens of a 'dog-bone' shape were fabricated from the leaf using standard lithographic procedures after the leaf had been glued onto a silicon wafer. The thickness of the gauge portion of the specimens was about 100 nm, the width between 250 nm and 300 nm and the length 7 µm. The specimens were mechanically loaded with a nanoindenter (MTS) at the approximate midpoint of the gauge length. The resulting force-displacement curve of the single crystal gold was serrated and it was evident that slip localization occurred on individual slip systems; however, the early stages of the plastic deformation occurred in a non-localized manner. The results of detailed finite element analyses of the specimen suggest that the critical resolved shear stress of the gold single crystal was as high as 135 MPa which would lead to a maximum uniaxial stress of about 500 MPa after several per cent strain. The behaviour of the nanoporous gold was substantially different. It exhibited an apparent elastic behaviour until the point where it failed in an apparently brittle manner, although it is assumed that plastic deformation occurred in the ligaments prior to failure. The average elastic stiffness of three specimens was measured to be Enp = 8.8 GPa and the stress at ultimate failure averaged 190 MPa for the three specimens tested. Scaling arguments suggest that the stress in the individual ligaments could approach the theoretical shear strength. Presented at the IUTAM Symposium on Plasticity at the Micron Scale, Technical

The patterning center of excellence (CoE): an evolving lithographic enablement model

NASA Astrophysics Data System (ADS)

Montgomery, Warren; Chun, Jun Sung; Liehr, Michael; Tittnich, Michael

2015-03-01

As EUV lithography moves toward high-volume manufacturing (HVM), a key need for the lithography materials makers is access to EUV photons and imaging. The SEMATECH Resist Materials Development Center (RMDC) provided a solution path by enabling the Resist and Materials companies to work together (using SUNY Polytechnic Institute's Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE) -based exposure systems), in a consortium fashion, in order to address the need for EUV photons. Thousands of wafers have been processed by the RMDC (leveraging the SUNY Poly CNSE/SEMATECH MET, SUNY Poly CNSE Alpha Demo Tool (ADT) and the SEMATECH Lawrence Berkeley MET) allowing many of the questions associated with EUV materials development to be answered. In this regard the activities associated with the RMDC are continuing. As the major Integrated Device Manufacturers (IDMs) have continued to purchase EUV scanners, Materials companies must now provide scanner based test data that characterizes the lithography materials they are producing. SUNY Poly CNSE and SEMATECH have partnered to evolve the RMDC into "The Patterning Center of Excellence (CoE)". The new CoE leverages the capability of the SUNY Poly CNSE-based full field ASML 3300 EUV scanner and combines that capability with EUV Microexposure (MET) systems resident in the SEMATECH RMDC to create an integrated lithography model which will allow materials companies to advance materials development in ways not previously possible.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Detection and characterization of microdefects and microprecipitates in Si wafers by Brewster angle illumination using an optical fiber system

NASA Astrophysics Data System (ADS)

Taijing, Lu; Toyoda, Koichi; Nango, Nobuhito; Ogawa, Tomoya

1991-10-01

Microdefects and microprecipitates were non-destructively detected in bulk and near surface of a Si wafer by Brewster angle illumination using an optical fiber system, because the p-component of the illumination enters completely into the wafer and then makes scattering from the defects while the other s-component reflects on the wafer surface so as to deviate from an objective lens for the detection of the scattering. Some results of observations and discussions will be done here about the scatterers in epitaxially grown Si layers, denuded zones of Si wafers, annealed amorphous SiC films, SIMOX specimens and slip bands in Si crystals.

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

NASA Technical Reports Server (NTRS)

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.;

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 {mu}m wide (111) sidewalls was fabricated using a 220 {mu}m thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

PubMed

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Creating nanoscale emulsions using condensation.

PubMed

Guha, Ingrid F; Anand, Sushant; Varanasi, Kripa K

2017-11-08

Nanoscale emulsions are essential components in numerous products, ranging from processed foods to novel drug delivery systems. Existing emulsification methods rely either on the breakup of larger droplets or solvent exchange/inversion. Here we report a simple, scalable method of creating nanoscale water-in-oil emulsions by condensing water vapor onto a subcooled oil-surfactant solution. Our technique enables a bottom-up approach to forming small-scale emulsions. Nanoscale water droplets nucleate at the oil/air interface and spontaneously disperse within the oil, due to the spreading dynamics of oil on water. Oil-soluble surfactants stabilize the resulting emulsions. We find that the oil-surfactant concentration controls the spreading behavior of oil on water, as well as the peak size, polydispersity, and stability of the resulting emulsions. Using condensation, we form emulsions with peak radii around 100 nm and polydispersities around 10%. This emulsion formation technique may open different routes to creating emulsions, colloidal systems, and emulsion-based materials.

Deconvoluting the mechanism of microwave annealing of block copolymer thin films.

PubMed

Jin, Cong; Murphy, Jeffrey N; Harris, Kenneth D; Buriak, Jillian M

2014-04-22

The self-assembly of block copolymer (BCP) thin films is a versatile method for producing periodic nanoscale patterns with a variety of shapes. The key to attaining a desired pattern or structure is the annealing step undertaken to facilitate the reorganization of nanoscale phase-segregated domains of the BCP on a surface. Annealing BCPs on silicon substrates using a microwave oven has been shown to be very fast (seconds to minutes), both with and without contributions from solvent vapor. The mechanism of the microwave annealing process remains, however, unclear. This work endeavors to uncover the key steps that take place during microwave annealing, which enable the self-assembly process to proceed. Through the use of in situ temperature monitoring with a fiber optic temperature probe in direct contact with the sample, we have demonstrated that the silicon substrate on which the BCP film is cast is the dominant source of heating if the doping of the silicon wafer is sufficiently low. Surface temperatures as high as 240 °C are reached in under 1 min for lightly doped, high resistivity silicon wafers (n- or p-type). The influence of doping, sample size, and BCP composition was analyzed to rule out other possible mechanisms. In situ temperature monitoring of various polymer samples (PS, P2VP, PMMA, and the BCPs used here) showed that the polymers do not heat to any significant extent on their own with microwave irradiation of this frequency (2.45 GHz) and power (∼600 W). It was demonstrated that BCP annealing can be effectively carried out in 60 s on non-microwave-responsive substrates, such as highly doped silicon, indium tin oxide (ITO)-coated glass, glass, and Kapton, by placing a piece of high resistivity silicon wafer in contact with the sample-in this configuration, the silicon wafer is termed the heating element. Annealing and self-assembly of polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) and polystyrene-block-poly(methyl methacrylate) (PS

Nanoscale-driven crystal growth of hexaferrite heterostructures for magnetoelectric tuning of microwave semiconductor integrated devices.

PubMed

Hu, Bolin; Chen, Zhaohui; Su, Zhijuan; Wang, Xian; Daigle, Andrew; Andalib, Parisa; Wolf, Jason; McHenry, Michael E; Chen, Yajie; Harris, Vincent G

2014-11-25

A nanoscale-driven crystal growth of magnetic hexaferrites was successfully demonstrated at low growth temperatures (25-40% lower than the temperatures required often for crystal growth). This outcome exhibits thermodynamic processes of crystal growth, allowing ease in fabrication of advanced multifunctional materials. Most importantly, the crystal growth technique is considered theoretically and experimentally to be universal and suitable for the growth of a wide range of diverse crystals. In the present experiment, the conical spin structure of Co2Y ferrite crystals was found to give rise to an intrinsic magnetoelectric effect. Our experiment reveals a remarkable increase in the conical phase transition temperature by ∼150 K for Co2Y ferrite, compared to 5-10 K of Zn2Y ferrites recently reported. The high quality Co2Y ferrite crystals, having low microwave loss and magnetoelectricity, were successfully grown on a wide bandgap semiconductor GaN. The demonstration of the nanostructure materials-based "system on a wafer" architecture is a critical milestone to next generation microwave integrated systems. It is also practical that future microwave integrated systems and their magnetic performances could be tuned by an electric field because of the magnetoelectricity of hexaferrites.

Formation of Au nano-patterns on various substrates using simplified nano-transfer printing method

NASA Astrophysics Data System (ADS)

Kim, Jong-Woo; Yang, Ki-Yeon; Hong, Sung-Hoon; Lee, Heon

2008-06-01

For future device applications, fabrication of the metal nano-patterns on various substrates, such as Si wafer, non-planar glass lens and flexible plastic films become important. Among various nano-patterning technologies, nano-transfer print method is one of the simplest techniques to fabricate metal nano-patterns. In nano-transfer printing process, thin Au layer is deposited on flexible PDMS mold, containing surface protrusion patterns, and the Au layer is transferred from PDMS mold to various substrates due to the difference of bonding strength of Au layer to PDMS mold and to the substrate. For effective transfer of Au layer, self-assembled monolayer, which has strong bonding to Au, is deposited on the substrate as a glue layer. In this study, complicated SAM layer coating process was replaced to simple UV/ozone treatment, which can activates the surface and form the -OH radicals. Using simple UV/ozone treatments on both Au and substrate, Au nano-pattern can be successfully transferred to as large as 6 in. diameter Si wafer, without SAM coating process. High fidelity transfer of Au nano-patterns to non-planar glass lens and flexible PET film was also demonstrated.

Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

NASA Astrophysics Data System (ADS)

Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

2003-09-01

As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

NASA Astrophysics Data System (ADS)

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Nanoscale thermal transport: Theoretical method and application

NASA Astrophysics Data System (ADS)

Zeng, Yu-Jia; Liu, Yue-Yang; Zhou, Wu-Xing; Chen, Ke-Qiu

2018-03-01

With the size reduction of nanoscale electronic devices, the heat generated by the unit area in integrated circuits will be increasing exponentially, and consequently the thermal management in these devices is a very important issue. In addition, the heat generated by the electronic devices mostly diffuses to the air in the form of waste heat, which makes the thermoelectric energy conversion also an important issue for nowadays. In recent years, the thermal transport properties in nanoscale systems have attracted increasing attention in both experiments and theoretical calculations. In this review, we will discuss various theoretical simulation methods for investigating thermal transport properties and take a glance at several interesting thermal transport phenomena in nanoscale systems. Our emphasizes will lie on the advantage and limitation of calculational method, and the application of nanoscale thermal transport and thermoelectric property. Project supported by the Nation Key Research and Development Program of China (Grant No. 2017YFB0701602) and the National Natural Science Foundation of China (Grant No. 11674092).

Generating atomically sharp p -n junctions in graphene and testing quantum electron optics on the nanoscale

NASA Astrophysics Data System (ADS)

Bai, Ke-Ke; Zhou, Jiao-Jiao; Wei, Yi-Cong; Qiao, Jia-Bin; Liu, Yi-Wen; Liu, Hai-Wen; Jiang, Hua; He, Lin

2018-01-01

Creation of high-quality p -n junctions in graphene monolayer is vital in studying many exotic phenomena of massless Dirac fermions. However, even with the fast progress of graphene technology for more than ten years, it remains conspicuously difficult to generate nanoscale and atomically sharp p -n junctions in graphene. Here, we realized nanoscale p -n junctions with atomically sharp boundaries in graphene monolayer by using monolayer vacancy island of Cu surface. The generated sharp p -n junctions with the height as high as 660 meV isolate the graphene above the Cu monolayer vacancy island as nanoscale graphene quantum dots (GQDs) in a continuous graphene sheet. Massless Dirac fermions are confined by the p -n junctions for a finite time to form quasibound states in the GQDs. By using scanning tunneling microscopy, we observe resonances of quasibound states in the GQDs with various sizes and directly visualize effects of geometries of the GQDs on the quantum interference patterns of the quasibound states, which allow us to test the quantum electron optics based on graphene in atomic scale.

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Reliable four-point flexion test and model for die-to-wafer direct bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.

2015-07-07

For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, bothmore » D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.« less

Nanoscale assembly of lanthanum silica with dense and porous interfacial structures.

PubMed

Ballinger, Benjamin; Motuzas, Julius; Miller, Christopher R; Smart, Simon; Diniz da Costa, João C

2015-02-03

This work reports on the nanoscale assembly of hybrid lanthanum oxide and silica structures, which form patterns of interfacial dense and porous networks. It was found that increasing the molar ratio of lanthanum nitrate to tetraethyl orthosilicate (TEOS) in an acid catalysed sol-gel process alters the expected microporous metal oxide silica structure to a predominantly mesoporous structure above a critical lanthanum concentration. This change manifests itself by the formation of a lanthanum silicate phase, which results from the reaction of lanthanum oxide nanoparticles with the silica matrix. This process converts the microporous silica into the denser silicate phase. Above a lanthanum to silica ratio of 0.15, the combination of growth and microporous silica consumption results in the formation of nanoscale hybrid lanthanum oxides, with the inter-nano-domain spacing forming mesoporous volume. As the size of these nano-domains increases with concentration, so does the mesoporous volume. The absence of lanthanum hydroxide (La(OH)3) suggests the formation of La2O3 surrounded by lanthanum silicate.

Through-wafer interrogation of microstructure motion for MEMS feedback control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

1999-09-01

Closed-loop MEMS control enables mechanical microsystems to adapt to the demands of the environment which they are actuating opening a new window of opportunity for future MEMS applications. Planar diffractive optical microsystems have the potential to enable the integrated optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation which is central to realization of feedback control. This paper presents the results of initial research evaluating through-wafer optical microsystems for MEMS integrated optical monitoring. Positional monitoring results obtained from a 1.3 micrometer wavelength through- wafer free-space optical probe of a lateral comb resonator fabricated using the Multi-User MEMS Process Service (MUMPS) are presented. Given the availability of positional information via probe signal feedback, a simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure.

Nano-Encrypted Morse Code: A Versatile Approach to Programmable and Reversible Nanoscale Assembly and Disassembly

PubMed Central

Wong, Ngo Yin; Xing, Hang; Tan, Li Huey; Lu, Yi

2013-01-01

While much work has been devoted to nanoscale assembly of functional materials, selective reversible assembly of components in the nanoscale pattern at selective sites has received much less attention. Exerting such a reversible control of the assembly process will make it possible to fine-tune the functional properties of the assembly and to realize more complex designs. Herein, by taking advantage of different binding affinities of biotin and desthiobiotin toward streptavidin, we demonstrate selective and reversible decoration of DNA origami tiles with streptavidin, including revealing an encrypted Morse code “NANO” and reversible exchange of uppercase letter “I” with lowercase “i”. The yields of the conjugations are high (> 90%) and the process is reversible. We expect this versatile conjugation technique to be widely applicable with different nanomaterials and templates. PMID:23373425

Nano-encrypted Morse code: a versatile approach to programmable and reversible nanoscale assembly and disassembly.

PubMed

Wong, Ngo Yin; Xing, Hang; Tan, Li Huey; Lu, Yi

2013-02-27

While much work has been devoted to nanoscale assembly of functional materials, selective reversible assembly of components in the nanoscale pattern at selective sites has received much less attention. Exerting such a reversible control of the assembly process will make it possible to fine-tune the functional properties of the assembly and to realize more complex designs. Herein, by taking advantage of different binding affinities of biotin and desthiobiotin toward streptavidin, we demonstrate selective and reversible decoration of DNA origami tiles with streptavidin, including revealing an encrypted Morse code "NANO" and reversible exchange of uppercase letter "I" with lowercase "i". The yields of the conjugations are high (>90%), and the process is reversible. We expect this versatile conjugation technique to be widely applicable with different nanomaterials and templates.

Nanoscale tissue engineering: spatial control over cell-materials interactions

PubMed Central

Wheeldon, Ian; Farhadi, Arash; Bick, Alexander G.; Jabbari, Esmaiel; Khademhosseini, Ali

2011-01-01

Cells interact with the surrounding environment by making tens to hundreds of thousands of nanoscale interactions with extracellular signals and features. The goal of nanoscale tissue engineering is to harness the interactions through nanoscale biomaterials engineering in order to study and direct cellular behaviors. Here, we review the nanoscale tissue engineering technologies for both two- and three-dimensional studies (2- and 3D), and provide a holistic overview of the field. Techniques that can control the average spacing and clustering of cell adhesion ligands are well established and have been highly successful in describing cell adhesion and migration in 2D. Extension of these engineering tools to 3D biomaterials has created many new hydrogel and nanofiber scaffolds technologies that are being used to design in vitro experiments with more physiologically relevant conditions. Researchers are beginning to study complex cell functions in 3D, however, there is a need for biomaterials systems that provide fine control over the nanoscale presentation of bioactive ligands in 3D. Additionally, there is a need for 2- and 3D techniques that can control the nanoscale presentation of multiple bioactive ligands and the temporal changes in cellular microenvironment. PMID:21451238

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

NASA Astrophysics Data System (ADS)

Kulshreshtha, Prashant Kumar

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

X-Ray Diffraction Wafer Mapping Method for Rhombohedral Super-Hetero-Epitaxy

NASA Technical Reports Server (NTRS)

Park, Yoonjoon; Choi, Sang Hyouk; King, Glen C.; Elliott, James R.; Dimarcantonio, Albert L.

2010-01-01

A new X-ray diffraction (XRD) method is provided to acquire XY mapping of the distribution of single crystals, poly-crystals, and twin defects across an entire wafer of rhombohedral super-hetero-epitaxial semiconductor material. In one embodiment, the method is performed with a point or line X-ray source with an X-ray incidence angle approximating a normal angle close to 90 deg, and in which the beam mask is preferably replaced with a crossed slit. While the wafer moves in the X and Y direction, a narrowly defined X-ray source illuminates the sample and the diffracted X-ray beam is monitored by the detector at a predefined angle. Preferably, the untilted, asymmetric scans are of {440} peaks, for twin defect characterization.

Traceable nanoscale measurement at NML-SIRIM

NASA Astrophysics Data System (ADS)

Dahlan, Ahmad M.; Abdul Hapip, A. I.

2012-06-01

The role of national metrology institute (NMI) has always been very crucial in national technology development. One of the key activities of the NMI is to provide traceable measurement in all parameters under the International System of Units (SI). Dimensional measurement where size and shape are two important features investigated, is one of the important area covered by NMIs. To support the national technology development, particularly in manufacturing sectors and emerging technology such nanotechnology, the National Metrology Laboratory, SIRIM Berhad (NML-SIRIM), has embarked on a project to equip Malaysia with state-of-the-art nanoscale measurement facility with the aims of providing traceability of measurement at nanoscale. This paper will look into some of the results from current activities at NML-SIRIM related to measurement at nanoscale particularly on application of atomic force microscope (AFM) and laser based sensor in dimensional measurement. Step height standards of different sizes were measured using AFM and laser-based sensors. These probes are integrated into a long-range nanoscale measuring machine traceable to the international definition of the meter thus ensuring their traceability. Consistency of results obtained by these two methods will be discussed and presented. Factors affecting their measurements as well as their related uncertainty of measurements will also be presented.

Neuromorphic computing with nanoscale spintronic oscillators.

PubMed

Torrejon, Jacob; Riou, Mathieu; Araujo, Flavio Abreu; Tsunegi, Sumito; Khalsa, Guru; Querlioz, Damien; Bortolotti, Paolo; Cros, Vincent; Yakushiji, Kay; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Stiles, Mark D; Grollier, Julie

2017-07-26

Neurons in the brain behave as nonlinear oscillators, which develop rhythmic activity and interact to process information. Taking inspiration from this behaviour to realize high-density, low-power neuromorphic computing will require very large numbers of nanoscale nonlinear oscillators. A simple estimation indicates that to fit 10 8 oscillators organized in a two-dimensional array inside a chip the size of a thumb, the lateral dimension of each oscillator must be smaller than one micrometre. However, nanoscale devices tend to be noisy and to lack the stability that is required to process data in a reliable way. For this reason, despite multiple theoretical proposals and several candidates, including memristive and superconducting oscillators, a proof of concept of neuromorphic computing using nanoscale oscillators has yet to be demonstrated. Here we show experimentally that a nanoscale spintronic oscillator (a magnetic tunnel junction) can be used to achieve spoken-digit recognition with an accuracy similar to that of state-of-the-art neural networks. We also determine the regime of magnetization dynamics that leads to the greatest performance. These results, combined with the ability of the spintronic oscillators to interact with each other, and their long lifetime and low energy consumption, open up a path to fast, parallel, on-chip computation based on networks of oscillators.

Bench-scale synthesis of nanoscale materials

NASA Technical Reports Server (NTRS)

Buehler, M. F.; Darab, J. G.; Matson, D. W.; Linehan, J. C.

1994-01-01

A novel flow-through hydrothermal method used to synthesize nanoscale powders is introduced by Pacific Northwest Laboratory. The process, Rapid Thermal Decomposition of precursors in Solution (RTDS), uniquely combines high-pressure and high-temperature conditions to rapidly form nanoscale particles. The RTDS process was initially demonstrated on a laboratory scale and was subsequently scaled up to accommodate production rates attractive to industry. The process is able to produce a wide variety of metal oxides and oxyhydroxides. The powders are characterized by scanning and transmission electron microscopic methods, surface-area measurements, and x-ray diffraction. Typical crystallite sizes are less than 20 nanometers, with BET surface areas ranging from 100 to 400 sq m/g. A description of the RTDS process is presented along with powder characterization results. In addition, data on the sintering of nanoscale ZrO2 produced by RTDS are included.

Roll-to-roll continuous patterning and transfer of graphene via dispersive adhesion

NASA Astrophysics Data System (ADS)

Choi, Taejun; Kim, Sang Jin; Park, Subeom; Hwang, Taek Yong; Jeon, Youngro; Hong, Byung Hee

2015-04-01

We present a roll-to-roll, continuous patterning and transfer of graphene sheets capable of residue-free and fast patterning. The graphene sheet is supported with dispersive adhesion. Graphene is continuously patterned by the difference in adhesion forces with a pre-defined embossed roller. The patterned graphene sheet adheres to the polyethylene terephthalate (PET)/silicone with very low strength and can be easily transferred to various substrates without the aid of any heating mechanism. The width of the patterned film was 120 mm and a production rate of 15 m min-1 for patterning was achieved. Large-area uniformity was confirmed by observing the optical images on 4 inch Si wafer and Raman mapping spectra for 50 × 50 mm2.We present a roll-to-roll, continuous patterning and transfer of graphene sheets capable of residue-free and fast patterning. The graphene sheet is supported with dispersive adhesion. Graphene is continuously patterned by the difference in adhesion forces with a pre-defined embossed roller. The patterned graphene sheet adheres to the polyethylene terephthalate (PET)/silicone with very low strength and can be easily transferred to various substrates without the aid of any heating mechanism. The width of the patterned film was 120 mm and a production rate of 15 m min-1 for patterning was achieved. Large-area uniformity was confirmed by observing the optical images on 4 inch Si wafer and Raman mapping spectra for 50 × 50 mm2. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr06991a

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

DOEpatents

Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

2011-07-12

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Production of Optical Quality Free Standing Diamond Wafer

DTIC Science & Technology

2008-05-19

Title : Production of Optical Quality Free Standing Diamond Wafer Prime Contractor : Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568...www.onyxoptics.com Program Manager : Helmuth Meissner Onyx Optics, Inc. 6551 Sierra Lane Dublin, CA 94568 Email: hmeissner@onyxoptics.com Ph: 925...PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING

Simplified nonplanar wafer bonding for heterogeneous device integration

NASA Astrophysics Data System (ADS)

Geske, Jon; Bowers, John E.; Riley, Anton

2004-07-01

We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

Hybrid strategies for nanolithography and chemical patterning

NASA Astrophysics Data System (ADS)

Srinivasan, Charan

Remarkable technological advances in photolithography have extended patterning to the sub-50-nm regime. However, because photolithography is a top-down approach, it faces substantial technological and economic challenges in maintaining the downward scaling trends of feature sizes below 30 nm. Concurrently, fundamental research on chemical self-assembly has enabled the path to access molecular length scales. The key to the success of photolithography is its inherent economies of scale, which justify the large capital investment for its implementation. In this thesis research, top-down and bottom-up approaches have been combined synergistically, and these hybrid strategies have been employed in applications that do not have the economies of scale found in semiconductor chip manufacturing. The specific instances of techniques developed here include molecular-ruler lithography and a series of nanoscale chemical patterning methods. Molecular-ruler lithography utilizes self-assembled multilayered films as a sidewall spacer on initial photolithographically patterned gold features (parent) to place a second-generation feature (daughter) in precise proximity to the parent. The parent-daughter separation, which is on the nanometer length scale, is defined by the thickness of the molecular-ruler resist. Analogous to protocols followed in industry to evaluate lithographic performance, electrical test-pad structures were designed to interrogate the nanostructures patterned by molecular-ruler nanolithography, failure modes creating electrical shorts were mapped to each lithographic step, and subsequent lithographic optimization was performed to pattern nanoscale devices with excellent electrical performance. The optimized lithographic processes were applied to generate nanoscale devices such as nanowires and thin-film transistors (TFTs). Metallic nanowires were patterned by depositing a tertiary generation material in the nanogap and surrounding micron-scale regions, and then

Nanoscale electrode arrays produced with microscale lithographic techniques for use in biomedical sensing applications.

PubMed

Terry, Jonathan G; Schmüser, Ilka; Underwood, Ian; Corrigan, Damion K; Freeman, Neville J; Bunting, Andrew S; Mount, Andrew R; Walton, Anthony J

2013-12-01

A novel technique for the production of nanoscale electrode arrays that uses standard microfabrication processes and micron-scale photolithography is reported here in detail. These microsquare nanoband edge electrode (MNEE) arrays have been fabricated with highly reproducible control of the key array dimensions, including the size and pitch of the individual elements and, most importantly, the width of the nanoband electrodes. The definition of lateral features to nanoscale dimensions typically requires expensive patterning techniques that are complex and low-throughput. However, the fabrication methodology used here relies on the fact that vertical dimensions (i.e. layer thicknesses) have long been manufacturable at the nanoscale using thin film deposition techniques that are well established in mainstream microelectronics. The authors report for the first time two aspects that highlight the particular suitability of these MNEE array systems for probe monolayer biosensing. The first is simulation, which shows the enhanced sensitivity to the redox reaction of the solution redox couple. The second is the enhancement of probe film functionalisation observed for the probe film model molecule, 6-mercapto-1-hexanol compared with microsquare electrodes. Such surface modification for specific probe layer biosensing and detection is of significance for a wide range of biomedical and other sensing and analytical applications.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Development for 2D pattern quantification method on mask and wafer

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Toyoda, Yasutaka; Wang, Zhigang

2010-03-01

We have developed the effective method of mask and silicon 2-dimensional metrology. The aim of this method is evaluating the performance of the silicon corresponding to Hotspot on a mask. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. 2-dimensional Shape quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. On the other hand, there is roughness in the silicon shape made from a mass-production line. Moreover, there is variation in the silicon shape. For this reason, quantification of silicon shape is important, in order to estimate the performance of a pattern. In order to quantify, the same shape is equalized in two dimensions. And the method of evaluating based on the shape is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. It is possible to analyze variability of the edge of the same position with high precision. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and

Control of cavitation using dissolved carbon dioxide for damage-free megasonic cleaning of wafers

NASA Astrophysics Data System (ADS)

Kumari, Sangita

equilibria revealed that the loss of released CO2(aq) upon increase in pH can be compensated by moderate increase in added NH4HCO3. Using this method, simultaneous control of SL and solution pH was demonstrated in two systems, NH4HCO3/HCl and NH4OH/CO2, at two nominal pH values; 5.7 and 7.0. Damage studies were performed on wafer samples with line/space patterns donated by IMEC and FSI International bearing Si/metal/a-Si gate stacks of thickness ~36 nm and Si/Poly-Si gate stacks of thickness ~67 nm, respectively. A single wafer spin cleaning tool MegPieRTM was used for the generation of megasonic energy for inducing damage to the structures. It was demonstrated that CO2 dissolution in DI water suppresses damage to the gate stacks in a dose-dependent manner. Together, these studies establish a systematic and strong correlation between CO2(aq) concentration, SL suppression and damage suppression. Significant damage reduction (~50 % to ~90 %) was observed at [CO2(aq)] > ~300 ppm. It was also demonstrated that CO2(aq) suppresses damage under alkaline pH condition too. This demonstration was made possible by the successful design of two new cleaning systems NH4HCO3/NH4OH and CO2/NH 4OH that could generate CO2(aq) under alkaline conditions. Damage suppressing ability of the newly designed cleaning systems were compared to the standard cleaning system NH4OH at pH 8.2 and it was found that NH4HCO3/NH4OH and CO2/NH 4OH systems were 80 % more efficient in suppressing damage compared to the standard NH4OH cleaning system. Finally, megasonic cleaning studies were conducted in the same single wafer spin cleaning tool MegPieRTM, using SiO2 particles (size 185 nm) deposited on 200 mm oxide Si wafers, as the contaminant. It was found that the standard cleaning chemical, NH4OH, pH 8.2, was effective in achieving > 95 % particle removal for 2 min irradiation of megasonic energy at power densities > 0.7 W/cm2. Based on these results, a new system, NH4HCO3/NH4OH, was designed with an aim to

Epitaxy of GaN in high aspect ratio nanoscale holes over silicon substrate

NASA Astrophysics Data System (ADS)

Wang, Kejia; Wang, Anqi; Ji, Qingbin; Hu, Xiaodong; Xie, Yahong; Sun, Ying; Cheng, Zhiyuan

2017-12-01

Dislocation filtering in gallium nitride (GaN) by epitaxial growth through patterned nanoscale holes is studied. GaN grown from extremely high aspect ratio holes by metalorganic chemical vapor deposition is examined by transmission electron microscopy and high-resolution transmission electron microscopy. This selective area epitaxial growth method with a reduced epitaxy area and an increased depth to width ratio of holes leads to effective filtering of dislocations within the hole and improves the quality of GaN significantly.

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Multiproject wafers: not just for million-dollar mask sets

NASA Astrophysics Data System (ADS)

Morse, Richard D.

2003-06-01

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

Laser pattern generator challenges in airborne molecular contamination protection

NASA Astrophysics Data System (ADS)

Ekberg, Mats; Skotte, Per-Uno; Utterback, Tomas; Paul, Swaraj; Kishkovich, Oleg P.; Hudzik, James S.

2003-08-01

The introduction of photomask laser pattern generators presents new challenges to system designers and manufacturers. One of the laser pattern generator's environmental operating challenges is Airborne Molecular Contamination (AMC), which affects both chemically amplified resists (CAResist) and laser optics. Similar challenges in CAResist protection have already been addressed in semiconductor wafer lithography with reasonable solutions and experience gained by all those involved. However, photomask and photomask equipment manufacturers have not previously had a comparable experience, and some photomask AMC issues differ from those seen in semiconductor wafer lithography. Culminating years of AMC experience, the authors discuss specific requirements of Photomask AMC. Air sampling and material of construction analysis were performed to understand these particular AMC challenges and used to develop an appropriate filtration specification for different classes of contaminates. The authors portray the importance of cooperation between tool designers and AMC experts early in the design stage to assure goal attainment to maximize both process stability and machine productivity in advanced mask making. In conclusion, the authors provide valuable recommendations to both laser tool users and other equipment manufacturers.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Astrophysics Data System (ADS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

2016-08-01

Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Technical Reports Server (NTRS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.;

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

2009-01-01

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muir, R.; Heebner, J.

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE PAGES

Muir, R.; Heebner, J.

2017-10-24

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Nanoscale platforms for messenger RNA delivery.

PubMed

Li, Bin; Zhang, Xinfu; Dong, Yizhou

2018-05-04

Messenger RNA (mRNA) has become a promising class of drugs for diverse therapeutic applications in the past few years. A series of clinical trials are ongoing or will be initiated in the near future for the treatment of a variety of diseases. Currently, mRNA-based therapeutics mainly focuses on ex vivo transfection and local administration in clinical studies. Efficient and safe delivery of therapeutically relevant mRNAs remains one of the major challenges for their broad applications in humans. Thus, effective delivery systems are urgently needed to overcome this limitation. In recent years, numerous nanoscale biomaterials have been constructed for mRNA delivery in order to protect mRNA from extracellular degradation and facilitate endosomal escape after cellular uptake. Nanoscale platforms have expanded the feasibility of mRNA-based therapeutics, and enabled its potential applications to protein replacement therapy, cancer immunotherapy, therapeutic vaccines, regenerative medicine, and genome editing. This review focuses on recent advances, challenges, and future directions in nanoscale platforms designed for mRNA delivery, including lipid and lipid-derived nanoparticles, polymer-based nanoparticles, protein derivatives mRNA complexes, and other types of nanomaterials. This article is categorized under: Nanotechnology Approaches to Biology > Nanoscale Systems in Biology Biology-Inspired Nanomaterials > Lipid-Based Structures Biology-Inspired Nanomaterials > Nucleic Acid-Based Structures. © 2018 Wiley Periodicals, Inc.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

NASA Astrophysics Data System (ADS)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

Modeling collective behavior of molecules in nanoscale direct deposition processes

NASA Astrophysics Data System (ADS)

Lee, Nam-Kyung; Hong, Seunghun

2006-03-01

We present a theoretical model describing the collective behavior of molecules in nanoscale direct deposition processes such as dip-pen nanolithography. We show that strong intermolecular interactions combined with nonuniform substrate-molecule interactions can produce various shapes of molecular patterns including fractal-like structures. Computer simulations reveal circular and starlike patterns at low and intermediate densities of preferentially attractive surface sites, respectively. At large density of such surface sites, the molecules form a two-dimensional invasion percolation cluster. Previous experimental results showing anisotropic patterns of various chemical and biological molecules correspond to the starlike regime [P. Manandhar et al., Phys. Rev. Lett. 90, 115505 (2003); J.-H. Lim and C. A. Mirkin, Adv. Mater. (Weinheim, Ger.) 14, 1474 (2002); D. L. Wilson et al., Proc. Natl. Acad. Sci. U.S.A. 98, 13660 (2001); M. Su et al., Appl. Phys. Lett. 84, 4200 (2004); R. McKendry et al., Nano Lett. 2, 713 (2002); H. Zhou et al., Appl. Surf. Sci. 236, 18 (2004); G. Agarwal et al., J. Am. Chem. Soc. 125, 580 (2003)].

Scalable maskless patterning of nanostructures using high-speed scanning probe arrays

NASA Astrophysics Data System (ADS)

Chen, Chen; Akella, Meghana; Du, Zhidong; Pan, Liang

2017-08-01

Nanoscale patterning is the key process to manufacture important products such as semiconductor microprocessors and data storage devices. Many studies have shown that it has the potential to revolutionize the functions of a broad range of products for a wide variety of applications in energy, healthcare, civil, defense and security. However, tools for mass production of these devices usually cost tens of million dollars each and are only affordable to the established semiconductor industry. A new method, nominally known as "pattern-on-the- y", that involves scanning an array of optical or electrical probes at high speed to form nanostructures and offers a new low-cost approach for nanoscale additive patterning. In this paper, we report some progress on using this method to pattern self-assembled monolayers (SAMs) on silicon substrate. We also functionalize the substrate with gold nanoparticle based on the SAM to show the feasibility of preparing amphiphilic and multi-functional surfaces.

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

High-wafer-yield, high-performance vertical cavity surface-emitting lasers

NASA Astrophysics Data System (ADS)

Li, Gabriel S.; Yuen, Wupen; Lim, Sui F.; Chang-Hasnain, Constance J.

1996-04-01

Vertical cavity surface emitting lasers (VCSELs) with very low threshold current and voltage of 340 (mu) A and 1.5 V is achieved. The molecular beam epitaxially grown wafers are grown with a highly accurate, low cost and versatile pre-growth calibration technique. One- hundred percent VCSEL wafer yield is obtained. Low threshold current is achieved with a native oxide confined structure with excellent current confinement. Single transverse mode with stable, predetermined polarization direction up to 18 times threshold is also achieved, due to stable index guiding provided by the structure. This is the highest value reported to data for VCSELs. We have established that p-contact annealing in these devices is crucial for low voltage operation, contrary to the general belief. Uniform doping in the mirrors also appears not to be inferior to complicated doping engineering. With these design rules, very low threshold voltage VCSELs are achieved with very simple growth and fabrication steps.

Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

NASA Astrophysics Data System (ADS)

Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

2001-07-01

The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

NASA Astrophysics Data System (ADS)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

NASA Astrophysics Data System (ADS)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

Nanoscale imaging of photocurrent enhancement by resonator array photovoltaic coatings.

PubMed

Ha, Dongheon; Yoon, Yohan; Zhitenev, Nikolai B

2018-04-06

Nanoscale surface patterning commonly used to increase absorption of solar cells can adversely impact the open-circuit voltage due to increased surface area and recombination. Here, we demonstrate absorptivity and photocurrent enhancement using silicon dioxide (SiO 2 ) nanosphere arrays on a gallium arsenide (GaAs) solar cell that do not require direct surface patterning. Due to the combined effects of thin-film interference and whispering gallery-like resonances within nanosphere arrays, there is more than 20% enhancement in both absorptivity and photocurrent. To determine the effect of the resonance coupling between nanospheres, we perform a scanning photocurrent microscopy based on a near-field scanning optical microscopy measurement and find a substantial local photocurrent enhancement. The nanosphere-based antireflection coating (ARC), made by the Meyer rod rolling technique, is a scalable and a room-temperature process; and, can replace the conventional thin-film-based ARCs requiring expensive high-temperature vacuum deposition.

Nanoscale imaging of photocurrent enhancement by resonator array photovoltaic coatings

NASA Astrophysics Data System (ADS)

Ha, Dongheon; Yoon, Yohan; Zhitenev, Nikolai B.

2018-04-01

Nanoscale surface patterning commonly used to increase absorption of solar cells can adversely impact the open-circuit voltage due to increased surface area and recombination. Here, we demonstrate absorptivity and photocurrent enhancement using silicon dioxide (SiO2) nanosphere arrays on a gallium arsenide (GaAs) solar cell that do not require direct surface patterning. Due to the combined effects of thin-film interference and whispering gallery-like resonances within nanosphere arrays, there is more than 20% enhancement in both absorptivity and photocurrent. To determine the effect of the resonance coupling between nanospheres, we perform a scanning photocurrent microscopy based on a near-field scanning optical microscopy measurement and find a substantial local photocurrent enhancement. The nanosphere-based antireflection coating (ARC), made by the Meyer rod rolling technique, is a scalable and a room-temperature process; and, can replace the conventional thin-film-based ARCs requiring expensive high-temperature vacuum deposition.

Reverse micelle synthesis of nanoscale metal containing catalysts

DOE Office of Scientific and Technical Information (OSTI.GOV)

Darab, J.G.; Fulton, J.L.; Linehan, J.C.

1993-03-01

The need for morphological control during the synthesis of catalyst precursor powders is generally accepted to be important. In the liquefaction of coal, for example, iron-bearing catalyst precursor particles containing individual crystallites with diameters in the 1-100 nanometer range are believed to achieve good dispersion through out the coal-solvent slurry during liquefaction 2 runs and to undergo chemical transformations to catalytically active iron sulfide phases. The production of the nanoscale powders described here employs the confining spherical microdomains comprising the aqueous phase of a modified reverse micelle (MRM) microemulsion system as nanoscale reaction vessels in which polymerization, electrochemical reduction andmore » precipitation of solvated salts can occur. The goal is to take advantage of the confining nature of micelles to kinetically hinder transformation processes which readily occur in bulk aqueous solution in order to control the morphology and phase of the resulting powder. We have prepared a variety of metal, alloy, and metal- and mixed metal-oxide nanoscale powders from appropriate MRM systems. Examples of nanoscale powders produced include Co, Mo-Co, Ni{sub 3}Fe, Ni, and various oxides and oxyhydroxides of iron. Here, we discuss the preparation and characterization of nickel metal (with a nickel oxide surface layer) and iron oxyhydroxide MRM nanoscale powders. We have used extended x-ray absorption fine structure (EXAFS) spectroscopy to study the chemical polymerization process in situ, x-ray diffraction (XRD), scanning and transmission electron microcroscopies (SEM and TEM), elemental analysis and structural modelling to characterize the nanoscale powders produced. The catalytic activity of these powders is currently being studied.« less

Electrode-stress-induced nanoscale disorder in Si quantum electronic devices

DOE PAGES

Park, J.; Ahn, Y.; Tilka, J. A.; ...

2016-06-20

Disorder in the potential-energy landscape presents a major obstacle to the more rapid development of semiconductor quantum device technologies. We report a large-magnitude source of disorder, beyond commonly considered unintentional background doping or fixed charge in oxide layers: nanoscale strain fields induced by residual stresses in nanopatterned metal gates. Quantitative analysis of synchrotron coherent hard x-ray nanobeam diffraction patterns reveals gate-induced curvature and strains up to 0.03% in a buried Si quantum well within a Si/SiGe heterostructure. Furthermore, electrode stress presents both challenges to the design of devices and opportunities associated with the lateral manipulation of electronic energy levels.

Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

PubMed Central

Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

2015-01-01

Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

PREFACE: Superconductivity in ultrathin films and nanoscale systems Superconductivity in ultrathin films and nanoscale systems

NASA Astrophysics Data System (ADS)