Science.gov

Sample records for nonvolatile memory devices

  1. Nonvolatile memory devices based on self-assembled nanocrystals

    NASA Astrophysics Data System (ADS)

    Lee, Jang-Sik

    2013-06-01

    Nonvolatile memory devices are one of the most important components in modern electronic devices. Many efforts have been made to fabricate high-density, low-cost, nonvolatile solid-state memory devices for use in portable/mobile electronic devices such as laptop computers, tablet devices, smart phones, etc. Among the many available nonvolatile memory devices, flash memory devices are of great interest to the electronics industry owing to their simple device structure, enabling high-density memory applications. Flash memory devices in which nanoparticles or nanocrystals are used as the charge-trapping elements have advantages over conventional flash memory devices because the charge-trapping layer and memory performance of the former can be readily optimized. Active research has recently been conducted to fabricate and characterize self-assembled-nanocrystal-based nonvolatile memory devices. We reviewed various strategies for fabricating nanocrystal-based nonvolatile memory devices and discussed the programmable memory properties and the device reliability characteristics of nanocrystal-based memory devices to possibly apply nanocrystal-based memory devices to those used in portable/mobile electronic devices. Finally, novel device applications such as printed/flexible/transparent electronic devices were explored based on nanocrystal-based memory devices.

  2. Sericin for resistance switching device with multilevel nonvolatile memory.

    PubMed

    Wang, Hong; Meng, Fanben; Cai, Yurong; Zheng, Liyan; Li, Yuangang; Liu, Yuanjun; Jiang, Yueyue; Wang, Xiaotian; Chen, Xiaodong

    2013-10-11

    Resistance switching characteristics of natural sericin protein film is demonstrated for nonvolatile memory application for the first time. Excellent memory characteristics with a resistance OFF/ON ratio larger than 10(6) have been obtained and a multilevel memory based on sericin has been achieved. The environmentally friendly high performance biomaterial based memory devices may hold a place in the future of electronic device development. PMID:23893500

  3. Bioorganic nanodots for non-volatile memory devices

    SciTech Connect

    Amdursky, Nadav; Shalev, Gil; Handelman, Amir; Natan, Amir; Rosenwaks, Yossi; Litsyn, Simon; Szwarcman, Daniel; Rosenman, Gil; Roizin, Yakov

    2013-12-01

    In recent years we are witnessing an intensive integration of bio-organic nanomaterials in electronic devices. Here we show that the diphenylalanine bio-molecule can self-assemble into tiny peptide nanodots (PNDs) of ∼2 nm size, and can be embedded into metal-oxide-semiconductor devices as charge storage nanounits in non-volatile memory. For that purpose, we first directly observe the crystallinity of a single PND by electron microscopy. We use these nanocrystalline PNDs units for the formation of a dense monolayer on SiO{sub 2} surface, and study the electron/hole trapping mechanisms and charge retention ability of the monolayer, followed by fabrication of PND-based memory cell device.

  4. Bioorganic nanodots for non-volatile memory devices

    NASA Astrophysics Data System (ADS)

    Amdursky, Nadav; Shalev, Gil; Handelman, Amir; Litsyn, Simon; Natan, Amir; Roizin, Yakov; Rosenwaks, Yossi; Szwarcman, Daniel; Rosenman, Gil

    2013-12-01

    In recent years we are witnessing an intensive integration of bio-organic nanomaterials in electronic devices. Here we show that the diphenylalanine bio-molecule can self-assemble into tiny peptide nanodots (PNDs) of ˜2 nm size, and can be embedded into metal-oxide-semiconductor devices as charge storage nanounits in non-volatile memory. For that purpose, we first directly observe the crystallinity of a single PND by electron microscopy. We use these nanocrystalline PNDs units for the formation of a dense monolayer on SiO2 surface, and study the electron/hole trapping mechanisms and charge retention ability of the monolayer, followed by fabrication of PND-based memory cell device.

  5. Total ionizing dose effects and reliability of graphene-based non-volatile memory devices

    NASA Astrophysics Data System (ADS)

    Zhang, Cher Xuan; Zhang, En Xia; Fleetwood, Daniel M.; Alles, Michael L.; Schrimpf, Ronald D.; Song, Emil B.; Galatsis, Kosmas; Newaz, A. K. M.; Bolotin, K. I.

    We discuss total ionizing dose effects and reliability of graphene-based electronics and non-volatile memory devices. The degradation after radiation exposure of these structures derives primarily from surface oxygen adsorption. Excellent stability and memory retention are observed for ionizing radiation exposure or constant-voltage stress. Cycling of the memory state leads to a significant degradation of the performance.

  6. Flexible non-volatile memory devices based on organic semiconductors

    NASA Astrophysics Data System (ADS)

    Cosseddu, Piero; Casula, Giulia; Lai, Stefano; Bonfiglio, Annalisa

    2015-09-01

    The possibility of developing fully organic electronic circuits is critically dependent on the ability to realize a full set of electronic functionalities based on organic devices. In order to complete the scene, a fundamental element is still missing, i.e. reliable data storage. Over the past few years, a considerable effort has been spent on the development and optimization of organic polymer based memory elements. Among several possible solutions, transistor-based memories and resistive switching-based memories are attracting a great interest in the scientific community. In this paper, a route for the fabrication of organic semiconductor-based memory devices with performances beyond the state of the art is reported. Both the families of organic memories will be considered. A flexible resistive memory based on a novel combination of materials is presented. In particular, high retention time in ambient conditions are reported. Complementary, a low voltage transistor-based memory is presented. Low voltage operation is allowed by an hybrid, nano-sized dielectric, which is also responsible for the memory effect in the device. Thanks to the possibility of reproducibly fabricating such device on ultra-thin substrates, high mechanical stability is reported.

  7. Improving Memory Characteristics of Hydrogenated Nanocrystalline Silicon Germanium Nonvolatile Memory Devices by Controlling Germanium Contents.

    PubMed

    Kim, Jiwoong; Jang, Kyungsoo; Phu, Nguyen Thi Cam; Trinh, Thanh Thuy; Raja, Jayapal; Kim, Taeyong; Cho, Jaehyun; Kim, Sangho; Park, Jinjoo; Jung, Junhee; Lee, Youn-Jung; Yi, Junsin

    2016-05-01

    Nonvolatile memory (NVM) with silicon dioxide/silicon nitride/silicon oxynitride (ONO(n)) charge trap structure is a promising flash memory technology duo that will fulfill process compatibility for system-on-panel displays, down-scaling cell size and low operation voltage. In this research, charge trap flash devices were fabricated with ONO(n) stack gate insulators and an active layer using hydrogenated nanocrystalline silicon germanium (nc-SiGe:H) films at a low temperature. In this study, the effect of the interface trap density on the performance of devices, including memory window and retention, was investigated. The electrical characteristics of NVM devices were studied controlling Ge content from 0% to 28% in the nc-SiGe:H channel layer. The optimal Ge content in the channel layer was found to be around 16%. For nc-SiGe:H NVM with 16% Ge content, the memory window was 3.13 V and the retention data exceeded 77% after 10 years under the programming condition of 15 V for 1 msec. This showed that the memory window increased by 42% and the retention increased by 12% compared to the nc-Si:H NVM that does not contain Ge. However, when the Ge content was more than 16%, the memory window and retention property decreased. Finally, this research showed that the Ge content has an effect on the interface trap density and this enabled us to determine the optimal Ge content. PMID:27483856

  8. Integration of Flexible and Microscale Organic Nonvolatile Resistive Memory Devices Using Orthogonal Photolithography.

    PubMed

    Song, Younggul; Jang, Jingon; Yoo, Daekyoung; Jung, Seok-Heon; Jeong, Hyunhak; Hong, Seunghun; Lee, Jin-Kyun; Lee, Takhee

    2016-06-01

    We present the integration of flexible and microscale organic nonvolatile resistive memory devices fabricated in a cross-bar array structure on plastic substrates. This microscale integration was made via orthogonal photolithography method using fluorinated photoresist and solvents and was achieved without causing damage to the underlying organic memory materials. Our flexible microscale organic devices exhibited high ON/OFF ratio (I(ON/I(OFF) > 10(4)) under bending conditions. In addition, the ON and OFF states of our flexible and microscale memory devices were maintained for 10,000 seconds without any serious degradation. PMID:27427716

  9. Metal-organic molecular device for non-volatile memory storage

    NASA Astrophysics Data System (ADS)

    Radha, B.; Sagade, Abhay A.; Kulkarni, G. U.

    2014-08-01

    Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

  10. Metal-organic molecular device for non-volatile memory storage

    SciTech Connect

    Radha, B. E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U. E-mail: kulkarni@jncasr.ac.in

    2014-08-25

    Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

  11. Nonvolatile organic thin film transistor memory devices based on hybrid nanocomposites of semiconducting polymers: gold nanoparticles.

    PubMed

    Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

    2013-12-26

    We report the facile fabrication and characteristics of organic thin film transistor (OTFT)-based nonvolatile memory devices using the hybrid nanocomposites of semiconducting poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and ligand-capped Au nanoparticles (NPs), thereby serving as a charge storage medium. Electrical bias sweep/excitation effectively modulates the current response of hybrid memory devices through the charge transfer between F8T2 channel and functionalized Au NPs trapping sites. The electrical performance of the hybrid memory devices can be effectively controlled though the loading concentrations (0-9 %) of Au NPs and organic thiolate ligands on Au NP surfaces with different carbon chain lengths (Au-L6, Au-L10, and Au-L18). The memory window induced by voltage sweep is considerably increased by the high content of Au NPs or short carbon chain on the ligand. The hybrid nanocomposite of F8T2:9% Au-L6 provides the OTFT memories with a memory window of ~41 V operated at ± 30 V and memory ratio of ~1 × 10(3) maintained for 1 × 10(4) s. The experimental results suggest that the hybrid materials of the functionalized Au NPs in F8T2 matrix have the potential applications for low voltage-driven high performance nonvolatile memory devices. PMID:24224739

  12. A fast and low-power microelectromechanical system-based non-volatile memory device

    PubMed Central

    Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

    2011-01-01

    Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

  13. A fast and low-power microelectromechanical system-based non-volatile memory device.

    PubMed

    Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E B; Park, Yung Woo

    2011-01-01

    Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

  14. High performance nonvolatile memory devices based on Cu2-xSe nanowires

    NASA Astrophysics Data System (ADS)

    Wu, Chun-Yan; Wu, Yi-Liang; Wang, Wen-Jian; Mao, Dun; Yu, Yong-Qiang; Wang, Li; Xu, Jun; Hu, Ji-Gang; Luo, Lin-Bao

    2013-11-01

    We report on the rational synthesis of one-dimensional Cu2-xSe nanowires (NWs) via a solution method. Electrical analysis of Cu2-xSe NWs based memory device exhibits a stable and reproducible bipolar resistive switching behavior with a low set voltage (0.3-0.6 V), which can enable the device to write and erase data efficiently. Remarkably, the memory device has a record conductance switching ratio of 108, much higher than other devices ever reported. At last, a conducting filaments model is introduced to account for the resistive switching behavior. The totality of this study suggests that the Cu2-xSe NWs are promising building blocks for fabricating high-performance and low-consumption nonvolatile memory devices.

  15. Non-volatile resistive memory devices based on solution-processed ultrathin two-dimensional nanomaterials.

    PubMed

    Tan, Chaoliang; Liu, Zhengdong; Huang, Wei; Zhang, Hua

    2015-05-01

    Ultrathin two-dimensional (2D) nanomaterials, such as graphene and MoS2, hold great promise for electronics and optoelectronics due to their distinctive physical and electronic properties. Recent progress in high-yield, massive production of ultrathin 2D nanomaterials via various solution-based methods allows them to be easily integrated into electronic devices via solution processing techniques. Non-volatile resistive memory devices based on ultrathin 2D nanomaterials have been emerging as promising alternatives for the next-generation data storage devices due to their high flexibility, three-dimensional-stacking capability, simple structure, transparency, easy fabrication and low cost. In this tutorial review, we will summarize the recent progress in the utilization of solution-processed ultrathin 2D nanomaterials for fabrication of non-volatile resistive memory devices. Moreover, we demonstrate how to achieve excellent device performance by engineering the active layers, electrodes and/or device structure of resistive memory devices. On the basis of current status, the discussion is concluded with some personal insights into the challenges and opportunities in future research directions. PMID:25877687

  16. An upconverted photonic nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Zhou, Ye; Han, Su-Ting; Chen, Xian; Wang, Feng; Tang, Yong-Bing; Roy, V. A. L.

    2014-08-01

    Conventional flash memory devices are voltage driven and found to be unsafe for confidential data storage. To ensure the security of the stored data, there is a strong demand for developing novel nonvolatile memory technology for data encryption. Here we show a photonic flash memory device, based on upconversion nanocrystals, which is light driven with a particular narrow width of wavelength in addition to voltage bias. With the help of near-infrared light, we successfully manipulate the multilevel data storage of the flash memory device. These upconverted photonic flash memory devices exhibit high ON/OFF ratio, long retention time and excellent rewritable characteristics.

  17. High speed switching in quantum Dot/Ti-TiOx nonvolatile memory device

    NASA Astrophysics Data System (ADS)

    Kannan, V.; Kim, Hyun-Seok; Park, Hyun-Chang

    2016-03-01

    We report a Ti-TiOx/CdSe-ZnS core-shell quantum dot based bipolar nonvolatile resistive memory device. The device exhibits an ON/OFF ratio of 100 and is reproducible. The memory device showed good retention characteristics under stress and excellent stability even after 100,000 cycles of switching operation. The switching speed measured was around 15 ns. The devices are solution processed at room temperature in ambient atmosphere. The operating mechanism is discussed based on charge trapping in quantum dots resulting in the Coulomb blockade effect with a ZnS shell layer and metal-oxide layer acting as the barrier to confine the trapped charges. The proposed mechanism is validated by a three terminal device designed exclusively for this purpose. [Figure not available: see fulltext.

  18. Non-volatile memory devices with redox-active diruthenium molecular compound

    NASA Astrophysics Data System (ADS)

    Pookpanratana, S.; Zhu, H.; Bittle, E. G.; Natoli, S. N.; Ren, T.; Richter, C. A.; Li, Q.; Hacker, C. A.

    2016-03-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al2O3/molecule/SiO2/Si structure. The bulky ruthenium redox molecule is attached to the surface by using a ‘click’ reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The ‘click’ reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices.

  19. Non-volatile memory devices with redox-active diruthenium molecular compound.

    PubMed

    Pookpanratana, S; Zhu, H; Bittle, E G; Natoli, S N; Ren, T; Richter, C A; Li, Q; Hacker, C A

    2016-03-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al2O3/molecule/SiO2/Si structure. The bulky ruthenium redox molecule is attached to the surface by using a 'click' reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The 'click' reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices. PMID:26871549

  20. Resistive switching behavior of reduced graphene oxide memory cells for low power nonvolatile device application

    PubMed Central

    Pradhan, Sangram K.; Xiao, Bo; Mishra, Saswat; Killam, Alex; Pradhan, Aswini K.

    2016-01-01

    Graphene Oxide (GO) based low cost flexible electronics and memory cell have recently attracted more attention for the fabrication of emerging electronic devices. As a suitable candidate for resistive random access memory technology, reduced graphene oxide (RGO) can be widely used for non-volatile switching memory applications because of its large surface area, excellent scalability, retention, and endurance properties. We demonstrated that the fabricated metal/RGO/metal memory device exhibited excellent switching characteristics, with on/off ratio of two orders of magnitude and operated threshold switching voltage of less than 1 V. The studies on different cell diameter, thickness, scan voltages and period of time corroborate the reliability of the device as resistive random access memory. The microscopic origin of switching operation is governed by the establishment of conducting filaments due to the interface amorphous layer rupturing and the movement of oxygen in the GO layer. This interesting experimental finding indicates that device made up of thermally reduced GO shows more reliability for its use in next generation electronics devices. PMID:27240537

  1. Resistive switching behavior of reduced graphene oxide memory cells for low power nonvolatile device application

    NASA Astrophysics Data System (ADS)

    Pradhan, Sangram K.; Xiao, Bo; Mishra, Saswat; Killam, Alex; Pradhan, Aswini K.

    2016-05-01

    Graphene Oxide (GO) based low cost flexible electronics and memory cell have recently attracted more attention for the fabrication of emerging electronic devices. As a suitable candidate for resistive random access memory technology, reduced graphene oxide (RGO) can be widely used for non-volatile switching memory applications because of its large surface area, excellent scalability, retention, and endurance properties. We demonstrated that the fabricated metal/RGO/metal memory device exhibited excellent switching characteristics, with on/off ratio of two orders of magnitude and operated threshold switching voltage of less than 1 V. The studies on different cell diameter, thickness, scan voltages and period of time corroborate the reliability of the device as resistive random access memory. The microscopic origin of switching operation is governed by the establishment of conducting filaments due to the interface amorphous layer rupturing and the movement of oxygen in the GO layer. This interesting experimental finding indicates that device made up of thermally reduced GO shows more reliability for its use in next generation electronics devices.

  2. Resistive switching behavior of reduced graphene oxide memory cells for low power nonvolatile device application.

    PubMed

    Pradhan, Sangram K; Xiao, Bo; Mishra, Saswat; Killam, Alex; Pradhan, Aswini K

    2016-01-01

    Graphene Oxide (GO) based low cost flexible electronics and memory cell have recently attracted more attention for the fabrication of emerging electronic devices. As a suitable candidate for resistive random access memory technology, reduced graphene oxide (RGO) can be widely used for non-volatile switching memory applications because of its large surface area, excellent scalability, retention, and endurance properties. We demonstrated that the fabricated metal/RGO/metal memory device exhibited excellent switching characteristics, with on/off ratio of two orders of magnitude and operated threshold switching voltage of less than 1 V. The studies on different cell diameter, thickness, scan voltages and period of time corroborate the reliability of the device as resistive random access memory. The microscopic origin of switching operation is governed by the establishment of conducting filaments due to the interface amorphous layer rupturing and the movement of oxygen in the GO layer. This interesting experimental finding indicates that device made up of thermally reduced GO shows more reliability for its use in next generation electronics devices. PMID:27240537

  3. Wearable non-volatile memory devices based on topological insulator Bi2Se3/Pt fibers

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaoyan; Wen, Fusheng; Xiang, Jianyong; Wang, Xiaochen; Wang, Limin; Hu, Wentao; Liu, Zhongyuan

    2015-09-01

    Pt fibers (15 μm) were coated with topological insulator Bi2Se3 nanoplates via a single mode microwave-assisted synthesis technique. With the Bi2Se3/Pt fibers, flexible memory devices were facilely assembled, and they were demonstrated to exhibit rewritable nonvolatile resistive switching characteristics of low switching voltage (-1.2 V and +0.7 V), high ON/OFF current ratio (106), and good retention (4500 s), showing the potential application in data storage. The resistive switching mechanism was analyzed on the bases of formation and rupture of conductive filaments.

  4. Vertically Stackable Novel One-Time Programmable Nonvolatile Memory Devices Based on Dielectric Breakdown Mechanism

    NASA Astrophysics Data System (ADS)

    Cho, Seongjae; Lee, Jung Hoon; Ryoo, Kyung-Chang; Jung, Sunghun; Lee, Jong-Ho; Park, Byung-Gook

    2011-12-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array structures based on silicon technology are proposed. There have been many features of OTP NVM devices utilizing various combinations of channel, breakdown region, barrier, and contact materials. However, this invention can be realized by simple materials and fabrication methods: it is silicon-based materials and fully compatible with the conventional CMOS process. An individual memory cell is a silicon diode vertically integrated. Historically, OTP memories were widely used for read-only-memory (ROM) in the central processing unit (CPU) of the computer systems. By implanting the nanoscale fabrication technology into the concept of OTP memory, innovative high-density NVM appliances for massive storage media becomes very promising. The program operation is performed by breaking down the thin oxide layer between pn doped structure and wordline (WL) and its state can be sensed by the leakage current through the broken oxide. Since this invention is based on neither transistor structure nor charge-based mechanism, it is highly reliable and functional for the ultra-large scale integration. The feasibility of its stacked array will be also checked.

  5. Nonvolatile memory devices based on poly(vinyl alcohol) + graphene oxide hybrid composites.

    PubMed

    Sun, Yanmei; Lu, Junguo; Ai, Chunpeng; Wen, Dianzhong

    2016-04-20

    Nonvolatile memory devices based on active layers of poly(vinyl alcohol) (PVA) + graphene oxide (GO) hybrid composites have been fabricated. The performance of the ITO/PVA + GO/Al device was compared with that of the ITO/PVA/Al device. The ITO/PVA + GO/Al device showed excellent performance compared to the ITO/PVA/Al device (an ON/OFF resistance ratio of 1.2 × 10(2) at 1 V, VSET ∼ -1.45 V and VRESET ∼ 3.6 V), with a higher ON/OFF resistance ratio of 3 × 10(4) at 1 V and lower operating voltages of VSET ∼ -0.75 V and VRESET ∼ 3.0 V. Furthermore, endurance performance and write-read-erase-reread (WRER) cycle tests manifest that the presence of GO in ITO/PVA + GO/Al devices makes them have better stability and repeatability. The results show that the performance of hybrid devices can be effectively enhanced by the introduction of GO into the PVA matrix. PMID:27056548

  6. Vacancy associates-rich ultrathin nanosheets for high performance and flexible nonvolatile memory device.

    PubMed

    Liang, Lin; Li, Kun; Xiao, Chong; Fan, Shaojuan; Liu, Jiao; Zhang, Wenshuai; Xu, Wenhui; Tong, Wei; Liao, Jiaying; Zhou, Yingying; Ye, Bangjiao; Xie, Yi

    2015-03-01

    On the road of innovation in modern information technology, resistive switching random access memory (RRAM) has been considered to be the best potential candidate to replace the conventional Si-based technologies. In fact, the key prerequisite of high storage density and low power consumption as well as flexibility for the tangible next generation of nonvolatile memories has stimulated extensive research into RRAM. Herein, we highlight an inorganic graphene analogue, ultrathin WO3·H2O nanosheets with only 2-3 nm thickness, as a promising material to construct a high performance and flexible RRAM device. The abundant vacancy associates in the ultrathin nanosheets, revealed by the positron annihilation spectra, act not only carrier reservoir to provide carriers but also capture center to trap the actived Cu(2+) for the formation of conductive filaments, which synergistically realize the resistive switching memory with low operating voltage (+1.0 V/-1.14 V) and large resistance ON/OFF ratio (>10(5)). This ultrathin-nanosheets-based RRAM device also shows long retention time (>10(5) s), good endurance (>5000 cycles), and excellent flexibility. The finding of the existence of distinct defects in ultrathin nanosheets undoubtedly leads to an atomic level deep understanding of the underlying nature of the resistive switching behavior, which may serve as a guide to improve the performances and promote the rapid development of RRAM. PMID:25668153

  7. All-solution-processed nonvolatile flexible nano-floating gate memory devices

    NASA Astrophysics Data System (ADS)

    Kim, Chaewon; Song, Ji-Min; Lee, Jang-Sik; Lee, Mi Jung

    2014-01-01

    Organic semiconductors have great potential for future electronic applications owing to their inherent flexibility, low cost, light weight and ability to easily cover large areas. However, all of these advantageous material properties can only be harnessed if simple, cheap and low-temperature fabrication processes, which exclude the need for vacuum deposition and are compatible with flexible plastic substrates, are employed. There are a few solution-based techniques such as spin-coating and inkjet printing that meet the above criteria. In this paper, we describe a novel all-solution-processed nonvolatile memory device fabricated on a flexible plastic substrate. The source, drain and gate electrodes were printed using an inkjet printer with a conducting organic solution, while the semiconducting layer was spin-coated with an n-type polymer. The charge-trapping layer was composed of spin-coated reduced graphene oxide (rGO), which was prepared in the form of a solution using Hummer’s method. The fabricated device was characterized in order to confirm the memory characteristics. Device parameters such as threshold voltage shift, retention/endurance characteristics, mechanical robustness and reliability upon bending were also analyzed.

  8. A Nonvolatile MOSFET Memory Device Based on Mobile Protons in SiO(2) Thin Films

    SciTech Connect

    Vanheusden, K.; Warren, W.L.; Devine, R.A.B.; Fleetwood, D.M.; Draper, B.L.; Schwank, J.R.

    1999-03-02

    It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protons are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).

  9. Nonvolatile Analog Memory

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C. (Inventor)

    2007-01-01

    A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and the second FFET has a storage voltage applied thereto that is indicative of the analog value. The saturation and storage voltages decay over time in accordance with a known decay function that is used to recover the original analog value when the pair of FFETs is read.

  10. Nonvolatile memory devices prepared from sol-gel derived niobium pentoxide films.

    PubMed

    Baek, Hyunhee; Lee, Chanwoo; Choi, Jungkyu; Cho, Jinhan

    2013-01-01

    We report on the resistive switching nonvolatile memory (RSNM) properties of niobium pentoxide (Nb(2)O(5)) films prepared using sol-gel chemistry. A sol-gel derived solution of niobium ethoxide, a precursor to Nb(2)O(5), was spin-coated on to a platinum (Pt)-coated silicon substrate, and was then annealed at approximately 620 and 450 °C to form a Nb(2)O(5) film of polycrystalline and amorphous structure, respectively. A top electrode consisting of Ag, W, Au, or Pt was then coated onto the Nb(2)O(5) films to complete the fabrication. After a forming process of limited current compliance up to 10 mA, known as "electroforming", a resistive switching phenomenon, independent of voltage polarity (unipolar switching), was observed at low operating voltages (0.59 ± 0.05 V(RESET) and 1.03 ± 0.06 V(SET)) with a high ON/OFF current ratio above 10(8). The reported approach offers opportunities for preparing Nb(2)O(5)-based resistive switching memory devices from solution process. PMID:23210494

  11. Scalability of Phase Change Materials in Non-Volatile Memory Devices

    NASA Astrophysics Data System (ADS)

    Jackson, Biyun Li

    This dissertation presents a study of the scaling limit of Phase Change Materials (PCM) for non-volatile memory device application. The approach is to obtain isolated true nano size Phase Change Materials through controllable deposition of PCM onto a template - nano pitted substrate. The fabrication of nano pitted substrate started from a di-block copolymer (DBC) film in hexagonal nano arrangement coated on thin SiO2 on Si (100) substrate. Then the DBC pattern was transferred to SiO2 - Si substrate by anisotropic dry oxide etch. Subsequently, a wet KOH etch with high crystallographic selectivity changed the circular pattern into an inverted pyramidal pit substrate. Thus, the dimension of the pits are controlled by the hole size of DBC, and the density of the pits are controlled by the interspacing between holes. Characterization tools such as SEM and TEM are intensively used to analyze the morphology, crystallographic, atomic ratio and phase transformation of the PCM. The dissertation discusses the critical fabrication tricks to produce high yield nano pitted substrate, illustrating the size effect of phase change materials upon crystallization and melting as well as the scaling limit of PCM. A proposal is also discussed for extending the study to device fabrication level and branch out the nano pitted substrate for the study of other materials in size and pressure effect.

  12. Analog Nonvolatile Computer Memory Circuits

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd

    2007-01-01

    In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value

  13. Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

    NASA Astrophysics Data System (ADS)

    Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

    2016-02-01

    We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

  14. Resistive Switching in Al/Al2O3/TiO2/Al/PES Flexible Device for Nonvolatile Memory Application.

    PubMed

    Lin, Chun-Chieh; Lee, Wang-Ying; Lee, Han-Tang

    2016-05-01

    Resistive switching memory devices with superior properties are possibly used in next-generation nonvolatile memory to replace the flash memory. In addition, flexible electronics has also attracted much attention because of its light-weight and flexibility. Therefore, an Al/Al2O3/TiO2/Al/PES flexible resistive switching memory is employed in this study. The resistive switching characteristics and stability of the flexible device are improved by inserting the Al2O3 film. The resistive switching of the flexible device can be repeated over hundreds of times after the bending test. A possible resistive switching model of the flexible device is also proposed. In addition, the non-volatility of the flexible device is demonstrated. Based on our research results, the proposed Al2O3/TiO2-based resistive switching memory is possibly used in next-generation flexible electronics and nonvolatile memory applications. PMID:27483828

  15. Towards the development of flexible non-volatile memories.

    PubMed

    Han, Su-Ting; Zhou, Ye; Roy, V A L

    2013-10-11

    Flexible non-volatile memories have attracted tremendous attentions for data storage for future electronics application. From device perspective, the advantages of flexible memory devices include thin, lightweight, printable, foldable and stretchable. The flash memories, resistive random access memories (RRAM) and ferroelectric random access memory/ferroelectric field-effect transistor memories (FeRAM/FeFET) are considered as promising candidates for next generation non-volatile memory device. Here, we review the general background knowledge on device structure, working principle, materials, challenges and recent progress with the emphasis on the flexibility of above three categories of non-volatile memories. PMID:24038631

  16. GaAs metal-oxide-semiconductor based nonvolatile memory devices embedded with ZnO quantum dots

    NASA Astrophysics Data System (ADS)

    Kundu, Souvik; Rao Gollu, Sankara; Sharma, Ramakant; Halder, Nripendra. N.; Biswas, Pranab; Banerji, P.; Gupta, D.

    2013-08-01

    Ultrathin InP passivated GaAs non-volatile memory devices were fabricated with chemically synthesized 5 nm ZnO quantum dots embedded into ZrO2 high-k oxide matrix deposited through metal organic chemical vapor deposition. In these memory devices, the memory window was found to be 6.10 V and the obtained charge loss was only 15.20% after 105 s. The superior retention characteristics and a wide memory window are achieved due to presence of ZnO quantum dots between tunneling and control oxide layers. Room temperature Coulomb blockade effect was found in these devices and it was ascertained to be the main reason for low leakage. Electronic band diagram with program and erase operations were described on the basis of electrical characterizations.

  17. A nonvolatile memory device made of a ferroelectric polymer gate nanodot and a single-walled carbon nanotube.

    PubMed

    Son, Jong Yeog; Ryu, Sangwoo; Park, Yoon-Cheol; Lim, Yun-Tak; Shin, Yun-Sok; Shin, Young-Han; Jang, Hyun Myung

    2010-12-28

    We demonstrate a field-effect nonvolatile memory device made of a ferroelectric copolymer gate nanodot and a single-walled carbon nanotube (SW-CNT). A position-controlled dip-pen nanolithography was performed to deposit a poly(vinylidene fluoride-ran-trifluoroethylene) (PVDF-TrFE) nanodot onto the SW-CNT channel with both a source and drain for field-effect transistor (FET) function. PVDF-TrFE was chosen as a gate dielectric nanodot in order to efficiently exploit its bipolar chemical nature. A piezoelectric force microscopy study confirmed the canonical ferroelectric responses of the PVDF-TrFE nanodot fabricated at the center of the SW-CNT channel. The two distinct ferroelectric polarization states with the stable current retention and fatigue-resistant characteristics make the present PVDF-TrFE-based FET suitable for nonvolatile memory applications. PMID:21050014

  18. Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices.

    PubMed

    Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

    2016-01-21

    Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. PMID:26695561

  19. Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

    NASA Astrophysics Data System (ADS)

    Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

    2016-01-01

    Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

  20. Nonvolatile random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1994-01-01

    A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

  1. Non-volatile memory for checkpoint storage

    SciTech Connect

    Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.; Coteus, Paul W.; Gara, Alan; Heidelberger, Philip; Jeanson, Mark J.; Kopcsay, Gerard V.; Ohmacht, Martin; Takken, Todd E.

    2014-07-22

    A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

  2. Nonvolatile Memory Technology for Space Applications

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

    2010-01-01

    This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

  3. Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

    PubMed Central

    Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

    2014-01-01

    Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

  4. Functionalized graphitic carbon nitride for metal-free, flexible and rewritable nonvolatile memory device via direct laser-writing.

    PubMed

    Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

    2014-01-01

    Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 10(5), which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

  5. Overview of emerging nonvolatile memory technologies

    PubMed Central

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  6. Overview of emerging nonvolatile memory technologies.

    PubMed

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  7. Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Roy, V. A. L.

    2013-01-01

    The capability of storing multi-bit information is one of the most important challenges in memory technologies. An ambipolar polymer which intrinsically has the ability to transport electrons and holes as a semiconducting layer provides an opportunity for the charge trapping layer to trap both electrons and holes efficiently. Here, we achieved large memory window and distinct multilevel data storage by utilizing the phenomena of ambipolar charge trapping mechanism. As fabricated flexible memory devices display five well-defined data levels with good endurance and retention properties showing potential application in printed electronics. PMID:23900459

  8. Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism.

    PubMed

    Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Roy, V A L

    2013-01-01

    The capability of storing multi-bit information is one of the most important challenges in memory technologies. An ambipolar polymer which intrinsically has the ability to transport electrons and holes as a semiconducting layer provides an opportunity for the charge trapping layer to trap both electrons and holes efficiently. Here, we achieved large memory window and distinct multilevel data storage by utilizing the phenomena of ambipolar charge trapping mechanism. As fabricated flexible memory devices display five well-defined data levels with good endurance and retention properties showing potential application in printed electronics. PMID:23900459

  9. Nonvolatile Memory Based on Nonlinear Magnetoelectric Effects

    NASA Astrophysics Data System (ADS)

    Shen, Jianxin; Cong, Junzhuang; Chai, Yisheng; Shang, Dashan; Shen, Shipeng; Zhai, Kun; Tian, Ying; Sun, Young

    2016-08-01

    The magnetoelectric effects in multiferroics have a great potential in creating next-generation memory devices. We use an alternative concept of nonvolatile memory based, on a type of nonlinear magnetoelectric effects showing a butterfly-shaped hysteresis loop. The principle is to utilize the states of the magnetoelectric coefficient, instead of magnetization, electric polarization, or resistance, to store binary information. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure clearly demonstrate that the sign of the magnetoelectric coefficient can be repeatedly switched between positive and negative by applying electric fields, confirming the feasibility of this principle. This kind of nonvolatile memory has outstanding practical virtues such as simple structure, easy operation in writing and reading, low power, fast speed, and diverse materials available.

  10. Non-volatile transistor memory devices using charge storage cross-linked core-shell nanoparticles.

    PubMed

    Lo, Chen-Tsyr; Watanabe, Yu; Oya, Hiroshi; Nakabayashi, Kazuhiro; Mori, Hideharu; Chen, Wen-Chang

    2016-06-01

    Solution processable cross-linked core-shell poly[poly(ethylene glycol)methylether methacrylate]-block-poly(2,5-dibromo-3-vinylthiophene) (poly(PEGMA)m-b-poly(DB3VT)n) nanoparticles are firstly explored as charge storage materials for transistor-type memory devices owing to their efficient and controllable ability in electric charge transfer and trapping. PMID:27180874

  11. Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

    SciTech Connect

    Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra

    2014-04-07

    In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attained with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.

  12. Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

    NASA Astrophysics Data System (ADS)

    Jin, Zhiwen; Liu, Guo; Wang, Jizheng

    2013-05-01

    Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

  13. The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices.

    PubMed

    Lee, Meng Chuan; Wong, Hin Yong

    2014-02-01

    This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper. PMID:24749438

  14. Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

    NASA Astrophysics Data System (ADS)

    Yu, Jie; Chen, Kunji; Ma, Zhongyuan; Zhang, Xinxin; Jiang, Xiaofan; Huang, Xinfan; Zhang, Yongxing; Wang, Lingling

    2016-01-01

    The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

  15. Nonpolar resistive switching in Cu/SiC/Au non-volatile resistive memory devices

    NASA Astrophysics Data System (ADS)

    Zhong, L.; Jiang, L.; Huang, R.; de Groot, C. H.

    2014-03-01

    Amorphous silicon carbide (a-SiC) based resistive memory (RM) Cu/a-SiC/Au devices were fabricated and their resistive switching characteristics investigated. All four possible modes of nonpolar resistive switching were achieved with ON/OFF ratio in the range 106-108. Detailed current-voltage I-V characteristics analysis suggests that the conduction mechanism in low resistance state is due to the formation of metallic filaments. Schottky emission is proven to be the dominant conduction mechanism in high resistance state which results from the Schottky contacts between the metal electrodes and SiC. ON/OFF ratios exceeding 107 over 10 years were also predicted from state retention characterizations. These results suggest promising application potentials for Cu/a-SiC/Au RMs.

  16. Cellulose Nanofiber Paper as an Ultra Flexible Nonvolatile Memory

    PubMed Central

    Nagashima, Kazuki; Koga, Hirotaka; Celano, Umberto; Zhuge, Fuwei; Kanai, Masaki; Rahong, Sakon; Meng, Gang; He, Yong; De Boeck, Jo; Jurczak, Malgorzata; Vandervorst, Wilfried; Kitaoka, Takuya; Nogi, Masaya; Yanagida, Takeshi

    2014-01-01

    On the development of flexible electronics, a highly flexible nonvolatile memory, which is an important circuit component for the portability, is necessary. However, the flexibility of existing nonvolatile memory has been limited, e.g. the smallest radius into which can be bent has been millimeters range, due to the difficulty in maintaining memory properties while bending. Here we propose the ultra flexible resistive nonvolatile memory using Ag-decorated cellulose nanofiber paper (CNP). The Ag-decorated CNP devices showed the stable nonvolatile memory effects with 6 orders of ON/OFF resistance ratio and the small standard deviation of switching voltage distribution. The memory performance of CNP devices can be maintained without any degradation when being bent down to the radius of 350 μm, which is the smallest value compared to those of existing any flexible nonvolatile memories. Thus the present device using abundant and mechanically flexible CNP offers a highly flexible nonvolatile memory for portable flexible electronics. PMID:24985164

  17. Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

    SciTech Connect

    Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

    2014-12-08

    Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.

  18. Black phosphorus nonvolatile transistor memory.

    PubMed

    Lee, Dain; Choi, Yongsuk; Hwang, Euyheon; Kang, Moon Sung; Lee, Seungwoo; Cho, Jeong Ho

    2016-04-28

    We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (10(4) s), and cyclic endurance (1000 cycles). PMID:27074903

  19. Black phosphorus nonvolatile transistor memory

    NASA Astrophysics Data System (ADS)

    Lee, Dain; Choi, Yongsuk; Hwang, Euyheon; Kang, Moon Sung; Lee, Seungwoo; Cho, Jeong Ho

    2016-04-01

    We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (104 s), and cyclic endurance (1000 cycles).We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (104 s), and cyclic endurance (1000 cycles). Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02078j

  20. Securing non-volatile memory regions

    SciTech Connect

    Faraboschi, Paolo; Ranganathan, Parthasarathy; Muralimanohar, Naveen

    2013-08-20

    Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

  1. Nonvolatile electrical bistability and operating mechanism of memory devices based on CdSe/ZnS nanoparticle/polymer hybrid composites

    NASA Astrophysics Data System (ADS)

    Li, Fushan; Son, Dong Ick; Kim, Bong Jun; Kim, Tae Whan

    2008-07-01

    Current-voltage (I-V) measurements on Al/(core/shell-type CdSe /ZnS nanoparticles embedded in polymer/indium tin oxide)/glass devices showed a nonvolatile electrical bistability behavior. Capacitance-voltage (C-V) measurements on the devices showed a counterclockwise hysteresis with a flatband voltage shift due to the existence of the CdSe /ZnS nanoparticles. The on/off ratio of the electrical bistability for memory devices with a hybrid [poly-N-vinylcarbazole (PVK) and polystyrene (PS)] matrix layer was larger than those for memory devices with a PVK or a PS layer. Possible operating mechanisms for the devices are described on the basis of the I-V and the C-V results.

  2. Colossal resistance switching effect in Pt/spinel-MgZnO/Pt devices for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Chen, Xinman; Wu, Guangheng; Jiang, Peng; Liu, Weifang; Bao, Dinghua

    2009-01-01

    We reported the discovery of colossal resistance switching effect in polycrystalline spinel-like structure MgZnO thin films with high Mg contents sandwiched by Pt electrodes. The ultrahigh resistance ratio of high resistance state to low resistance state of about seven to nine orders of magnitude with a low reset voltage of less than 1 V was obtained in this thin film system. The resistance ratio shows an increase of several orders of magnitude compared with those of previously reported resistance switching material systems including metal oxides, semiconductors, and organic molecules. This colossal resistance switching effect will greatly improve the signal-to-noise ratio and simplify the process of reading memory state for nonvolatile memory applications. Our study also provides a material base for studying the origin of resistance switching phenomenon.

  3. Investigation of charge trapping mechanism for nanocrystal-based organic nonvolatile floating gate memory devices by band structure analysis

    NASA Astrophysics Data System (ADS)

    Lee, Dong-Hoon; Lim, Ki-Tae; Park, Eung-Kyu; Shin, Ha-Chul; Kim, Chung Soo; Park, Kee-Chan; Ahn, Joung-Real; Bang, Jin Ho; Kim, Yong-Sang

    2016-05-01

    This paper investigates the charge trapping mechanism and electrical performance of CdSe nanocrystals, such as nanoparticles and nanowires in organic floating gate memory devices. Despite of same chemical component, each nanocrystals show different electrical performances with distinct trapping mechanism. CdSe nanoparticles trap holes in the memory device; on the contrary, nanowires trap electrons. This phenomenon is mainly due to the difference of energy band structures between nanoparticles and nanowires, measured by the ultraviolet photoelectron spectroscopy. Also, we investigated the memory performance with C- V characteristics, charging and discharging phenomena, and retention time. The nanoparticle based hole trapping memory device has large memory window while the nanowire based electron trapping memory shows a narrow memory window. In spite of narrow memory window, the nanowire based memory device shows better retention performance of about 55% of the charge even after 104 sec of charging. The contrasting performance of nanoparticle and nanowire is attributed to the difference in their energy band and the morphology of thin layer in the device. [Figure not available: see fulltext.

  4. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend.

    PubMed

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices. PMID:27323302

  5. 2K nonvolatile shadow RAM and 265K EEPROM SONOS nonvolatile memory development

    SciTech Connect

    Nasby, R.D.; Murray, J.R.; Habermehl, S.D.; Bennett, R.S.; Tafoya-Porras, B.C.; Mahl, P.R.; Rodriguez, J.L.; Jones, R.V.; Knoll, M.G.

    1998-07-01

    This paper describes Silicon Oxide Nitride Oxide Semiconductor (SONOS) nonvolatile memory development at Sandia National Laboratories. A 256K EEPROM nonvolatile memory and a 2K nonvolatile shadow RAM are under development using an n-channel SONOS memory technology. The technology has 1.2 {micro}m minimum features in a twin well design using shallow trench isolation.

  6. Non-volatile memory based on the ferroelectric photovoltaic effect

    PubMed Central

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-01-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

  7. Nonvolatile Rad-Hard Holographic Memory

    NASA Technical Reports Server (NTRS)

    Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

    2001-01-01

    We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

  8. GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

    SciTech Connect

    Islam, Sk Masiul Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P.; Chakraborty, S.

    2015-06-24

    Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

  9. GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

    NASA Astrophysics Data System (ADS)

    Islam, Sk Masiul; Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P.; Chakraborty, S.; Mukherjee, Rabibrata

    2015-06-01

    Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO2 and ZrO2, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×1011 cm-2, respectively. The device with a structure Metal/ZrO2/InAs QDs/HfO2/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10-6 A/cm2 and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO2 deposition.

  10. Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

    NASA Astrophysics Data System (ADS)

    Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

    2016-03-01

    In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

  11. A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory.

    PubMed

    Lee, Myoung-Jae; Ahn, Seung-Eon; Lee, Chang Bum; Kim, Chang-Jung; Jeon, Sanghun; Chung, U-In; Yoo, In-Kyeong; Park, Gyeong-Su; Han, Seungwu; Hwang, In Rok; Park, Bae-Ho

    2011-11-01

    Present charge-based silicon memories are unlikely to reach terabit densities because of scaling limits. As the feature size of memory shrinks to just tens of nanometers, there is insufficient volume available to store charge. Also, process temperatures higher than 800 °C make silicon incompatible with three-dimensional (3D) stacking structures. Here we present a device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory using resistance switching. It is demonstrated that NiO films are scalable to around 30 nm and compatible with multilevel cell technology. The device unit can be a building block for 3D stacking structure because of its simple structure and constituent, high performance, and process temperature lower than 300 °C. Memory resistance switching of NiO storage element is accompanied by an increase in density of grain boundary while threshold resistance switching of NiO switch element is controlled by current flowing through NiO film. PMID:21988144

  12. Resistive switching characteristics of ZnO thin film grown on stainless steel for flexible nonvolatile memory devices

    SciTech Connect

    Lee, Seunghyup; Kim, Heejin; Yong, Kijung; Yun, Dong-Jin; Rhee, Shi-Woo

    2009-12-28

    This paper reports a resistive switching device of Au/ZnO/stainless steel (SS) and its applicability as a flexible resistive random access memory (ReRAM). The Au/ZnO/SS structure was fabricated by radio frequency sputtering deposition of a ZnO thin film on the SS substrate. The fabricated device showed stable unipolar and bipolar resistive switching behaviors with reliable switching responses over 100 cycles. The device performance was not degraded upon bending, which indicates high potential for flexible ReRAM applications.

  13. SONOS Nonvolatile Memory Cell Programming Characteristics

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2010-01-01

    Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

  14. EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

    NASA Astrophysics Data System (ADS)

    Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

    2011-06-01

    Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

  15. Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

    NASA Astrophysics Data System (ADS)

    Oh, Se Woong; Park, Sang Su; Kim, Dong Hun; Kim, Hyun Woo; Kim, Tae Whan

    2009-06-01

    Not-and (NAND)-type silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices with a separated double-gate (SDG) Fin field effect transistor structure were proposed to reduce the unit cell size of such memory devices and increase their memory density in comparison with that of conventional NVM devices. The proposed memory device consisted of a pair of control gates separated along the length of the Fin channel direction. Each SDG had a different thickness of the tunneling oxide to operate the proposed memory device as a two-bit/cell device. A technology computer-aided design simulation was performed to investigate the program/erase and two-bit characteristics. The simulation results show that the proposed devices can be used to increase the scaling down capability and charge storage density of NAND-type SONOS NVM devices.

  16. EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

    NASA Astrophysics Data System (ADS)

    Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

    2011-06-01

    Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

  17. Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

    NASA Technical Reports Server (NTRS)

    John, Caroline S.; MacLeod, Todd C.; Evans, Joe; Ho, Fat D.

    2011-01-01

    We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

  18. Nonvolatile semiconductor memory having three dimension charge confinement

    DOEpatents

    Dawson, L. Ralph; Osbourn, Gordon C.; Peercy, Paul S.; Weaver, Harry T.; Zipperian, Thomas E.

    1991-01-01

    A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

  19. Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

    PubMed

    Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

    2016-05-01

    We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays. PMID:27483835

  20. Non-volatile magnetic random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

  1. Novel nonvolatile memory with multibit storage based on a ZnO nanowire transistor.

    PubMed

    Sohn, Jung Inn; Choi, Su Seok; Morris, Stephen M; Bendall, James S; Coles, Harry J; Hong, Woong-Ki; Jo, Gunho; Lee, Takhee; Welland, Mark E

    2010-11-10

    We demonstrate a room temperature processed ferroelectric (FE) nonvolatile memory based on a ZnO nanowire (NW) FET where the NW channel is coated with FE nanoparticles. A single device exhibits excellent memory characteristics with the large modulation in channel conductance between ON and OFF states exceeding 10(4), a long retention time of over 4 × 10(4) s, and multibit memory storage ability. Our findings provide a viable way to create new functional high-density nonvolatile memory devices compatible with simple processing techniques at low temperature for flexible devices made on plastic substrates. PMID:20945844

  2. Ultra-flexible nonvolatile memory based on donor-acceptor diketopyrrolopyrrole polymer blends

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Zhou, Li; Huang, Long-Biao; Zhuang, Jiaqing; Sonar, Prashant; Roy, V. A. L.

    2015-01-01

    Flexible memory cell array based on high mobility donor-acceptor diketopyrrolopyrrole polymer has been demonstrated. The memory cell exhibits low read voltage, high cell-to-cell uniformity and good mechanical flexibility, and has reliable retention and endurance memory performance. The electrical properties of the memory devices are systematically investigated and modeled. Our results suggest that the polymer blends provide an important step towards high-density flexible nonvolatile memory devices. PMID:26029856

  3. Active Flash: Performance-Energy Tradeoffs for Out-of-Core Processing on Non-Volatile Memory Devices

    SciTech Connect

    Boboila, Simona; Kim, Youngjae; Vazhkudai, Sudharshan S; Desnoyers, Peter; Shipman, Galen M

    2012-01-01

    In this abstract, we study the performance and energy tradeoffs involved in migrating data analysis into the flash device, a process we refer to as Active Flash. The Active Flash paradigm is similar to 'active disks', which has received considerable attention. Active Flash allows us to move processing closer to data, thereby minimizing data movement costs and reducing power consumption. It enables true out-of-core computation. The conventional definition of out-of-core solvers refers to an approach to process data that is too large to fit in the main memory and, consequently, requires access to disk. However, in Active Flash, processing outside the host CPU literally frees the core and achieves real 'out-of-core' analysis. Moving analysis to data has long been desirable, not just at this level, but at all levels of the system hierarchy. However, this requires a detailed study on the tradeoffs involved in achieving analysis turnaround under an acceptable energy envelope. To this end, we first need to evaluate if there is enough computing power on the flash device to warrant such an exploration. Flash processors require decent computing power to run the internal logic pertaining to the Flash Translation Layer (FTL), which is responsible for operations such as address translation, garbage collection (GC) and wear-leveling. Modern SSDs are composed of multiple packages and several flash chips within a package. The packages are connected using multiple I/O channels to offer high I/O bandwidth. SSD computing power is also expected to be high enough to exploit such inherent internal parallelism within the drive to increase the bandwidth and to handle fast I/O requests. More recently, SSD devices are being equipped with powerful processing units and are even embedded with multicore CPUs (e.g. ARM Cortex-A9 embedded processor is advertised to reach 2GHz frequency and deliver 5000 DMIPS; OCZ RevoDrive X2 SSD has 4 SandForce controllers, each with 780MHz max frequency

  4. Enhanced Memory Behavior in Phase-Change Nonvolatile-Memory Devices Using Multilayered Structure of Compositionally Modified Ge-Sb-Te Films

    NASA Astrophysics Data System (ADS)

    Yoon, Sung-Min; Lee, Seung-Yun; Jung, Soon-Won; Park, Young-Sam; Yu, Byoung-Gon

    2009-04-01

    A unique and novel phase-change memory device employing multilayered chalcogenide films was proposed and fabricated. In this structure, Ge18Sb39Te43, which corresponds to a 22 at. % Sb-excessive phase of typical stoichiometric Ge2Sb2Te5 (GST), was located in the middle and acted as the main operating region to exploit its superior properties, thus ensuring reliable memory operations. Thinner GST layers were inserted to above and below the middle layer. The introduction of a bottom GST layer promotes the temperature rise and the thermal insulation within the device operating volume owing to its lower thermal conductivity. The top GST layer effectively suppresses the undesirable interdiffusion between the top electrode of W and the Sb added to excess. Moreover, the upper and lower GST supplementary layers promote the initial crystallization stage during set operations owing to their higher crystallization rate compared with that of the Sb-rich phase of GST. As a result, the required current for reset, the required time for set, and the number of rewritable cycles of the proposed device with an active pore size of 0.5 ×0.5 µm2 were 6.1 mA, 80 ns, and 6.4 ×106, respectively, which are superior values compared with those for the device using a single layer of Ge18Sb39Te43. We can conclude that the proposed multilayered structure of compositionally modified GST films provides a very promising approach to enhancing all types of the memory behaviors required for the phase-change memory devices.

  5. An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

    NASA Technical Reports Server (NTRS)

    Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

    2001-01-01

    Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

  6. Thermally reliable clocked non-volatile spin wave logic device

    NASA Astrophysics Data System (ADS)

    Dutta, Sourav; Nikonov, Dmitri; Manipatruni, Sasikanth; Young, Ian; Naeemi, Azad

    The possibility of utilizing spin waves for information transmission and computation has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits. Here, we present a comprehensive scheme for building a thermally reliable clocked non-volatile spin wave logic device (SWLD) by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, exploiting the magneto-electric effect for spin wave transmission, detection and non-volatile memory, utilizing the phase of the spin wave as information token, ensuring phase-dependent deterministic switching of the magnetoelectric spin wave detector in the presence of thermal noise via compensation of demagnetization and a novel clocking scheme that ensures sequential transmission of information in a cascaded SWLD and non- reciprocity

  7. Radiation and Reliability Concerns for Modern Nonvolatile Memory Technology

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Friendlich, Mark R.; Kim, Hak S.; Berg, Melanie D.; LaBel, Kenneth A.; Buchner, S. P.; McMorrow, D.; Mavis, D. G.; Eaton, P. H.; Castillo, J.

    2011-01-01

    Commercial nonvolatile memory technology is attractive for space applications, but radiation issues are serious concerns. In addition, we discuss combined radiation/reliability concerns which are only beginning to be addressed.

  8. Non-Volatile Memory Technology Symposium 2000: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh (Editor)

    2000-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.

  9. Single-crystal C60 needle/CuPc nanoparticle double floating-gate for low-voltage organic transistors based non-volatile memory devices.

    PubMed

    Chang, Hsuan-Chun; Lu, Chien; Liu, Cheng-Liang; Chen, Wen-Chang

    2015-01-01

    Low-voltage organic field-effect transistor memory devices exhibiting a wide memory window, low power consumption, acceptable retention, endurance properties, and tunable memory performance are fabricated. The performance is achieved by employing single-crystal C60 needles and copper phthalocyanine nanoparticles to produce an ambipolar (hole/electron) trapping effect in a double floating-gate architecture. PMID:25358891

  10. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    SciTech Connect

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  11. Non-volatile memory based on transition metal perovskite oxide resistance switching

    NASA Astrophysics Data System (ADS)

    Nian, Yibo

    Driven by the non-volatile memory market looking for new advanced materials, this dissertation focuses on the study of non-volatile resistive random access memory (RRAM) based on transition metal perovskite oxides. Pr0.7Ca0.3MnO3 (PCMO), one of the representative materials in this family, has demonstrated a large range of resistance change when short electrical pulses with different polarity are applied. Such electrical-pulse-induced resistance (EPIR), with attractive features such as fast response, low power, high-density and non-volatility, makes PCMO and related materials promising candidates for non-volatile RRAM application. The objective of this work is to investigate, optimize and understand the properties of this universal EPIR behavior in transition metal perovskite oxide, represented by PCMO thin film devices. The research work includes fabrication of PCMO thin film devices, characterization of these EPIR devices as non-volatile memories, and investigation of their resistive switching mechanisms. The functionality of this perovskite oxide RRAM, including pulse magnitude/width dependence, power consumption, retention, endurance and radiation-hardness has been investigated. By studying the "shuttle tail" in hysteresis switching loops of oxygen deficient devices, a diffusion model with oxygen ions/vacancies as active agents at the metal/oxide interface is proposed for the non-volatile resistance switching effect in transition metal perovskite oxide thin films. The change of EPIR switching behavior after oxygen/argon ion implantation also shows experiment support for the proposed model. Furthermore, the universality, scalability and comparison with other non-volatile memories are discussed for future application.

  12. Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

    NASA Astrophysics Data System (ADS)

    Valentini, L.; Cardinali, M.; Fortunati, E.; Kenny, J. M.

    2014-10-01

    With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

  13. Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

    SciTech Connect

    Valentini, L. Cardinali, M.; Fortunati, E.; Kenny, J. M.

    2014-10-13

    With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

  14. Method for refreshing a non-volatile memory

    DOEpatents

    Riekels, James E.; Schlesinger, Samuel

    2008-11-04

    A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

  15. Analytical Model of Nano-Electromechanical (NEM) Nonvolatile Memory Cells

    NASA Astrophysics Data System (ADS)

    Han, Boram; Choi, Woo Young

    The fringe field effects of nano-electromechanical (NEM) nonvolatile memory cells have been investigated analytically for the accurate evaluation of NEM memory cells. As the beam width is scaled down, fringe field effect becomes more severe. It has been observed that pull-in, release and hysteresis voltage decrease more than our prediction. Also, the fringe field on cell characteristics has been discussed.

  16. Endurance-write-speed tradeoffs in nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Strukov, Dmitri B.

    2016-04-01

    We derive phenomenological model for endurance-write time switching tradeoff for nonvolatile memories with thermally activated switching mechanisms. The model predicts linear to cubic dependence of endurance on write time for metal oxide memristors and flash memories, which is partially supported by experimental data for the breakdown of metal oxide thin films.

  17. Development of non-volatile semiconductor memory

    NASA Technical Reports Server (NTRS)

    Heikkila, W. W.

    1979-01-01

    A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

  18. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  19. Physical principles and current status of emerging non-volatile solid state memories

    NASA Astrophysics Data System (ADS)

    Wang, L.; Yang, C.-H.; Wen, J.

    2015-07-01

    Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

  20. Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

    NASA Astrophysics Data System (ADS)

    Zhao-wen, Yan; Jiao, Wang; Jian-li, Qiao; Wen-jie, Chen; Pan, Yang; Tong, Xiao; Jian-hong, Yang

    2016-06-01

    A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated, in which polysilicon is sandwiched between oxide layers as a floating gate. Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed. The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing (P/E) operations at various P/E voltages are discussed. The simulated results show that present memory exhibits a large memory window of 57.5 V, and a high read current on/off ratio of ≈ 103. Compared with the reported experimental results, these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects, which shows great promise in device designing and practical application.

  1. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

    PubMed

    Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-01-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

  2. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

    PubMed Central

    Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-01-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

  3. Non-Volatile Memory Technology Symposium 2001: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Daud, Taher; Strauss, Karl

    2001-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

  4. Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Kim, Young Rae; Jo, Yong Eun; Shin, Yong Seon; Kang, Won Tae; Sung, Yeo Hyun; Won, Ui Yeon; Lee, Young Hee; Yu, Woo Jong

    2015-03-01

    In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO2 gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

  5. Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

    SciTech Connect

    Kim, Young Rae; Jo, Yong Eun; Sung, Yeo Hyun; Won, Ui Yeon; Shin, Yong Seon; Kang, Won Tae; Yu, Woo Jong E-mail: micco21@skku.edu; Lee, Young Hee E-mail: micco21@skku.edu

    2015-03-09

    In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO{sub 2} gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

  6. A graphene-based non-volatile memory

    NASA Astrophysics Data System (ADS)

    Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

    2015-09-01

    We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET < VRESET , where SET is the process decreasing the resistance and RESET the process increasing the resistance. We achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

  7. Wafer-scale arrays of nonvolatile polymer memories with microprinted semiconducting small molecule/polymer blends.

    PubMed

    Bae, Insung; Hwang, Sun Kak; Kim, Richard Hahnkee; Kang, Seok Ju; Park, Cheolmin

    2013-11-13

    Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropatterns of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate/bottom-contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropatterns of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface. PMID:24070419

  8. Integrated photonics with programmable non-volatile memory

    PubMed Central

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-01-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications. PMID:26941113

  9. Integrated photonics with programmable non-volatile memory.

    PubMed

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-01-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications. PMID:26941113

  10. Integrated photonics with programmable non-volatile memory

    NASA Astrophysics Data System (ADS)

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-03-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications.

  11. Flexible Nonvolatile Polymer Memory Array on Plastic Substrate via Initiated Chemical Vapor Deposition.

    PubMed

    Jang, Byung Chul; Seong, Hyejeong; Kim, Sung Kyu; Kim, Jong Yun; Koo, Beom Jun; Choi, Junhwan; Yang, Sang Yoon; Im, Sung Gap; Choi, Sung-Yool

    2016-05-25

    Resistive random access memory based on polymer thin films has been developed as a promising flexible nonvolatile memory for flexible electronic systems. Memory plays an important role in all modern electronic systems for data storage, processing, and communication; thus, the development of flexible memory is essential for the realization of flexible electronics. However, the existing solution-processed, polymer-based RRAMs have exhibited serious drawbacks in terms of the uniformity, electrical stability, and long-term stability of the polymer thin films. Here, we present poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based RRAM arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) process for flexible memory application. Because of the outstanding chemical stability of pV3D3 films, the pV3D3-RRAM arrays can be fabricated by a conventional photolithography process. The pV3D3-RRAM on flexible substrates showed unipolar resistive switching memory with an on/off ratio of over 10(7), stable retention time for 10(5) s, excellent cycling endurance over 10(5) cycles, and robust immunity to mechanical stress. In addition, pV3D3-RRAMs showed good uniformity in terms of device-to-device distribution. The pV3D3-RRAM will pave the way for development of next-generation flexible nonvolatile memory devices. PMID:27142537

  12. Organic field-effect transistor nonvolatile memories based on hybrid nano-floating-gate

    NASA Astrophysics Data System (ADS)

    Gao, Xu; She, Xiao-Jian; Liu, Chang-Hai; Sun, Qi-Jun; Liu, Jie; Wang, Sui-Dong

    2013-01-01

    High performance organic field-effect transistor nonvolatile memory is achieved by integrating gold nanoparticles and graphene oxide sheets as the hybrid nano-floating-gate. The device shows a large memory window of about 40 V, high ON/OFF ratio of reading current over 104, excellent programming/erasing endurance, and retention ability. The hybrid nano-floating-gate can increase the density of charge trapping sites, which are electrically separate from each other and thus suppress the stored charge leakage. The memory window is increased under illumination, and the results indicate that the photon-generated carriers facilitate the electron trapping but have almost no effect on the hole trapping.

  13. Coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3/In memristive devices

    NASA Astrophysics Data System (ADS)

    Yang, M.; Bao, D. H.; Li, S. W.

    2013-12-01

    Memristive devices are triggering innovations in the fields of nonvolatile memory, digital logic, analogue circuits, neuromorphic engineering, and so on. Creating new memristive devices with unique characteristics would be significant for these emergent applications. Here we report the coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3 (NSTO)/In memristive devices. The Pt/NSTO interface contributes a nonvolatile resistive switching behaviour, whereas the NSTO/In interface displays a volatile hysteresis loop. Combining the two interfaces in the Pt/NSTO/In devices leads to the unique coexistence of nonvolatility and volatility. The results imply more opportunities to invent new memristive devices by engineering both interfaces in metal/insulator/metal structures.

  14. A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

    PubMed Central

    Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

    2016-01-01

    Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

  15. Nonvolatile GaAs Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

    1994-01-01

    Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

  16. Integrated all-photonic non-volatile multi-level memory

    NASA Astrophysics Data System (ADS)

    Ríos, Carlos; Stegmaier, Matthias; Hosseini, Peiman; Wang, Di; Scherer, Torsten; Wright, C. David; Bhaskaran, Harish; Pernice, Wolfram H. P.

    2015-11-01

    Implementing on-chip non-volatile photonic memories has been a long-term, yet elusive goal. Photonic data storage would dramatically improve performance in existing computing architectures by reducing the latencies associated with electrical memories and potentially eliminating optoelectronic conversions. Furthermore, multi-level photonic memories with random access would allow for leveraging even greater computational capability. However, photonic memories have thus far been volatile. Here, we demonstrate a robust, non-volatile, all-photonic memory based on phase-change materials. By using optical near-field effects, we realize bit storage of up to eight levels in a single device that readily switches between intermediate states. Our on-chip memory cells feature single-shot readout and switching energies as low as 13.4 pJ at speeds approaching 1 GHz. We show that individual memory elements can be addressed using a wavelength multiplexing scheme. Our multi-level, multi-bit devices provide a pathway towards eliminating the von Neumann bottleneck and portend a new paradigm in all-photonic memory and non-conventional computing.

  17. Nonvolatile memory characteristics of nickel-silicon-nitride nanocrystal

    SciTech Connect

    Chen, W.-R.; Chang, T.-C.; Liu, P.-T.; Yeh, J.-L.; Tu, C.-H.; Lou, J.-C.; Yeh, C.-F.; Chang, C.-Y.

    2007-08-20

    The formation of nickel-silicon-nitride nanocrystals by sputtering a comixed target in the argon and nitrogen environment is proposed in this letter. High resolution transmission electron microscope analysis clearly shows the nanocrystals embedded in the silicon nitride and x-ray photoelectron spectroscopy also shows the chemical material analysis of nanocrystals. The memory window of nickel-silicon-nitride nanocrystals enough to define 1 and 0 states is obviously observed, and a good data retention characteristic to get up to 10 years is exhibited for the nonvolatile memory application.

  18. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  19. Reactive ion etching of Si(x)Sb2Te in CF4/Ar plasma for nonvolatile phase-change memory device.

    PubMed

    Gu, Yifeng; Song, Sannian; Song, Zhitang; Cheng, Yan; Liu, Xuyan; Du, Xiaofeng; Liu, Bo; Feng, Songlin

    2013-02-01

    Si(x)Sb2Te material system is novel for phase-change random access memory applications. Its properties are more outstanding than the widely used material Ge2Sb2Te5. Etching process is one of the critical steps in the device fabrication. The etching characteristics of phase-change material Si(x)Sb2Te were studied with CF4/Ar gas mixture by a reactive ion etching system. The changes of etching rate, etching profile and surface root-mean-square roughness resulted from variation of the gas-mixing ratio were investigated under constant pressure (50 mTorr) and applying power (200 W). Si0.34Sb2Te is with the highest phase-change speed and the lowest power consumption in the PCRAM memory among these compositions, which means it is the most promising candidate for the PCRAM applications. So the most optimized CF4/Ar gas ratio for Si0.34Sb2Te was studied, the value is 25/25. The etching rate is 155 nm/min, and the selectivity of Si0.34Sb2Te to SiO2 is as high as 3.4 times. Furthermore, the smooth surface was achieved with this optimized gas ratio. PMID:23646688

  20. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics. PMID:26578160

  1. Highly scalable non-volatile and ultra-low-power phase-change nanowire memory.

    PubMed

    Lee, Se-Ho; Jung, Yeonwoong; Agarwal, Ritesh

    2007-10-01

    The search for a universal memory storage device that combines rapid read and write speeds, high storage density and non-volatility is driving the exploration of new materials in nanostructured form. Phase-change materials, which can be reversibly switched between amorphous and crystalline states, are promising in this respect, but top-down processing of these materials into nanostructures often damages their useful properties. Self-assembled nanowire-based phase-change material memory devices offer an attractive solution owing to their sub-lithographic sizes and unique geometry, coupled with the facile etch-free processes with which they can be fabricated. Here, we explore the effects of nanoscaling on the memory-storage capability of self-assembled Ge2Sb2Te5 nanowires, an important phase-change material. Our measurements of write-current amplitude, switching speed, endurance and data retention time in these devices show that such nanowires are promising building blocks for non-volatile scalable memory and may represent the ultimate size limit in exploring current-induced phase transition in nanoscale systems. PMID:18654387

  2. Ordered arrays of a defect-modified ferroelectric polymer for non-volatile memory with minimized energy consumption

    NASA Astrophysics Data System (ADS)

    Chen, Xiang-Zhong; Chen, Xin; Guo, Xu; Cui, Yu-Shuang; Shen, Qun-Dong; Ge, Hai-Xiong

    2014-10-01

    Ferroelectric polymers are among the most promising materials for flexible electronic devices. Highly ordered arrays of the defect-modified ferroelectric polymer P(VDF-TrFE-CFE) (poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene)) are fabricated by nanoimprint lithography for nonvolatile memory application. The defective CFE units reduce the coercive field to one-fifth of that of the un-modified P(VDF-TrFE), which can help minimize the energy consumption and extend the lifespan of the device. The nanoimprint process leads to preferable orientation of polymer chains and delicately controlled distribution of the defects, and thus a bi-stable polarization that makes the memory nonvolatile, as revealed by the pulsed polarization experiment.Ferroelectric polymers are among the most promising materials for flexible electronic devices. Highly ordered arrays of the defect-modified ferroelectric polymer P(VDF-TrFE-CFE) (poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene)) are fabricated by nanoimprint lithography for nonvolatile memory application. The defective CFE units reduce the coercive field to one-fifth of that of the un-modified P(VDF-TrFE), which can help minimize the energy consumption and extend the lifespan of the device. The nanoimprint process leads to preferable orientation of polymer chains and delicately controlled distribution of the defects, and thus a bi-stable polarization that makes the memory nonvolatile, as revealed by the pulsed polarization experiment. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr03866e

  3. Highly Stretchable Non-volatile Nylon Thread Memory

    PubMed Central

    Kang, Ting-Kuo

    2016-01-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications. PMID:27072786

  4. Highly Stretchable Non-volatile Nylon Thread Memory

    NASA Astrophysics Data System (ADS)

    Kang, Ting-Kuo

    2016-04-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

  5. Nonvolatile memory cells based on MoS2/graphene heterostructures.

    PubMed

    Bertolazzi, Simone; Krasnozhon, Daria; Kis, Andras

    2013-04-23

    Memory cells are an important building block of digital electronics. We combine here the unique electronic properties of semiconducting monolayer MoS2 with the high conductivity of graphene to build a 2D heterostructure capable of information storage. MoS2 acts as a channel in an intimate contact with graphene electrodes in a field-effect transistor geometry. Our prototypical all-2D transistor is further integrated with a multilayer graphene charge trapping layer into a device that can be operated as a nonvolatile memory cell. Because of its band gap and 2D nature, monolayer MoS2 is highly sensitive to the presence of charges in the charge trapping layer, resulting in a factor of 10(4) difference between memory program and erase states. The two-dimensional nature of both the contact and the channel can be harnessed for the fabrication of flexible nanoelectronic devices with large-scale integration. PMID:23510133

  6. Progress on a New Non-Volatile Memory for Space Based on Chalcogenide Glass

    SciTech Connect

    Maimon, J.; Hunt, K.; Rodgers, J.; Burcin, L.; Knowles, K.

    2004-02-04

    We report on the progress of a recent addition to non-volatile solid state memory technologies suited for space and other ionizing radiation environments. We summarize the material and processing science behind the current generation of chalcogenide phase-change memories fabricated on CMOS structures. The chalcogenide material used for phase-change applications in rewritable optical storage (Ge2Sb2Te5) has been integrated with a radiation hardened CMOS process to produce 64kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100ns programming and read speeds, and write currents as low as 1mA/bit. Devices functioned normally from - 55 deg. C to 125 deg. C. Write/read endurance has been demonstrated to 1 x 108 before first bit failure. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase-change material. Future applications of the technology are discussed.

  7. PREFACE: Emerging non-volatile memories: magnetic and resistive technologies Emerging non-volatile memories: magnetic and resistive technologies

    NASA Astrophysics Data System (ADS)

    Dieny, B.; Jagadish, Chennupati

    2013-02-01

    In 2010, the International Technology Roadmap for Semiconductors (ITRS) published an assessment of the potential and maturity of selected emerging research on memory technologies. Eight different technologies of non-volatile memories were compared (ferroelectric gate field-effect transistor, nano-electro-mechanical switch, spin-transfer torque random access memories (STTRAM), various types of resistive RAM, in particular redox RAM, nanothermal phase change RAM, electronic effects RAM, macromolecular memories and molecular RAM). In this report, spin-transfer torque MRAM and redox RRAM were identified as two emerging memory technologies recommended for accelerated research and development leading to scaling and commercialization of non-volatile RAM to and beyond the 16nm generation. Nowadays, there is an intense research and development effort in microelectronics on these two technologies, one based on spintronic phenomena (tunnel magnetoresistance and spin-transfer torque), the other based on migration of vacancies or ions in an insulating matrix driven by oxydo-reduction potentials. Both technologies could be used for standalone or embedded applications. In this context, it appeared timely to publish a cluster of review articles related to these two technologies. In this cluster, the first two articles introduce the general principles of spin-transfer torque RAM and of thermally assisted RAM. The third presents a broader range of applications for this integrated CMOS/magnetic tunnel junction technology for low-power electronics. The fourth paper presents more advanced research on voltage control of magnetization switching with the aim of dramatically reducing the write energy in MRAM. The last two papers deal with two categories of resistive RAM, one based on the migration of cations, the other one based on nanowires. We thank all the authors and reviewers for their contribution to this cluster issue. Our special thanks are due to Dr Olivia Roche, Publisher, and Dr

  8. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    SciTech Connect

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  9. Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

    PubMed

    Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

    2015-07-21

    Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use. PMID:26098677

  10. Electrically Variable Resistive Memory Devices

    NASA Technical Reports Server (NTRS)

    Liu, Shangqing; Wu, Nai-Juan; Ignatiev, Alex; Charlson, E. J.

    2010-01-01

    Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

  11. Single-Wall Carbon Nanotube Field Effect Transistors with Non-Volatile Memory Operation

    NASA Astrophysics Data System (ADS)

    Sakurai, Tatsuya; Yoshimura, Takeshi; Akita, Seiji; Fujimura, Norifumi; Nakayama, Yoshikazu

    2006-10-01

    We describe the fabrication and electrical characteristics of single-wall carbon-nanotubes field-effect transistors (CNT-FETs) with a non-volatile memory function using ferroelectric thin films as gate insulators. The ferroelectric-gate CNT-FETs were fabricated using single-wall CNTs synthesized from alcohol by catalytic chemical vapor deposition and sol-gel derived PbZr0.5Ti0.5O3 thin films. The ferroelectric-gate CNT-FETs showed modulation of the drain current with the gate voltage and the threshold voltage shift (memory window) on the drain current-gate voltage characteristics. Moreover, the memory window was saturated around 1.1 V as the gate voltage sweeping range increased. These results indicate that carriers in CNTs are controlled by spontaneous polarization of the ferroelectric films. Because ferroelectrics exhibit complex couplings between their electrical, structural, mechanical, thermal, and optical properties, and because CNTs have unique mechanical and electrical properties, ferroelectric-gate CNT-FETs offer promise as potentially useful nanoelectronics devices not only for non-volatile memory elements but also for high-sensitivity sensors.

  12. Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

    SciTech Connect

    Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung; Kang, Moon Sung

    2015-02-09

    Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

  13. Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

    NASA Astrophysics Data System (ADS)

    Yoon, Sung-Min; Yang, Shin-Hyuk; Park, Sang-Hee Ko; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

    2009-12-01

    Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al2O3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 107 on/off ratio, and a gate leakage current of 10-11 A.

  14. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Wang, Shun; Gao, Xu; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong

    2016-07-01

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  15. An embedded nonvolatile memory cell with spacer floating gate for power management integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Na, Kee-Yeol; Baek, Ki-Ju; Lee, Gun-Woong; Kim, Yeong-Seuk

    2013-08-01

    This paper describes a simple nonvolatile memory cell with a poly-Si spacer floating gate for power management integrated circuit applications. The proposed memory cell is fabricated using a 0.35 μm double-poly high-voltage CMOS process which includes PIP capacitor, LV (5 V), and HV (20 V) CMOS devices. The floating gates of the proposed cell are buried under a LDD spacer oxide; thus the unit cell can be scaled easily in the channel length direction. In addition, any extra photo masking step is not required for the proposed cell in the applied fabrication process. The proposed cell shows an acceptable threshold voltage window of up to 104 cycles and less than 2% threshold voltage shifts in an 85 °C retention test.

  16. Hot Carrier Trapping Induced Negative Photoconductance in InAs Nanowires toward Novel Nonvolatile Memory.

    PubMed

    Yang, Yiming; Peng, Xingyue; Kim, Hong-Seok; Kim, Taeho; Jeon, Sanghun; Kang, Hang Kyu; Choi, Wonjun; Song, Jindong; Doh, Yong-Joo; Yu, Dong

    2015-09-01

    We report a novel negative photoconductivity (NPC) mechanism in n-type indium arsenide nanowires (NWs). Photoexcitation significantly suppresses the conductivity with a gain up to 10(5). The origin of NPC is attributed to the depletion of conduction channels by light assisted hot electron trapping, supported by gate voltage threshold shift and wavelength-dependent photoconductance measurements. Scanning photocurrent microscopy excludes the possibility that NPC originates from the NW/metal contacts and reveals a competing positive photoconductivity. The conductivity recovery after illumination substantially slows down at low temperature, indicating a thermally activated detrapping mechanism. At 78 K, the spontaneous recovery of the conductance is completely quenched, resulting in a reversible memory device, which can be switched by light and gate voltage pulses. The novel NPC based optoelectronics may find exciting applications in photodetection and nonvolatile memory with low power consumption. PMID:26226506

  17. Nonvolatile memory characteristics of WSi2 nanocrystals embedded in SiO2 dielectrics.

    PubMed

    Seo, Ki Bong; Lee, Dong Uk; Han, Seung Jong; Kim, Seon Pil; Kim, Eun Kyu

    2011-01-01

    A nano-floating gate capacitor with WSi2 nanocrystals embedded in SiO2 dielectrics was fabricated. The WSi2 nanocrystals were created from ultrathin WSi2 film during rapid thermal annealing process and their average size and density were about 2.5 nm and 3.59 x 10(12) cm(-2), respectively. The flat-band voltage shift due to the carrier charging effect of WSi2 nanocrystals were measured up to 5.9 V when the gate voltage sweep in the range of +/- 9 V. The memory window was decreased from 3.7 V to 1.9 V after 1 h and remained about 3.7 V after 10(5) programming/erasing cycles. These results show that there is a possibility for the WSi2 nanocrystals to be applied to nonvolatile memory devices. PMID:21446472

  18. Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects

    NASA Astrophysics Data System (ADS)

    Zaka, A.; Singer, J.; Dornel, E.; Garetto, D.; Rideau, D.; Rafhay, Q.; Clerc, R.; Manceau, J.-P.; Degors, N.; Boccaccio, C.; Tavernier, C.; Jaouen, H.

    2011-09-01

    The impact of 3D device architecture in aggressively scaled embedded non-volatile memories has been investigated by means of experiments and 3D TCAD simulations. A complete 3D calibration methodology covering DC and transient operating regimes has been introduced and validated against measurements for different technological options. This approach has been employed to determine the key features for device optimization. In particular, shallow trench isolation corners around the active area have been identified as critical regions of the memory cell for program and erase operations, as well as for gate coupling ratio optimization.

  19. Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

    NASA Technical Reports Server (NTRS)

    Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

    2009-01-01

    We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

  20. Nonvolatile Memory Solution for Near-Term NASA Missions

    NASA Technical Reports Server (NTRS)

    Patel, J. U.; Blaes, B. R.; Mojarradi, M. M.

    2001-01-01

    Nonvolatile memory (NVM) system that could reliably function in extreme environments is one of the most critical components for many spacecrafts being developed for NASA missions to be launched in next four to seven years. NVM supports the computer system in saving and updating critical state data required for a warm restart after power cycling or in case of a power bus failure. It also provides a power independent mass storage capacity for the scientific data gathered by the instruments. In some cases the window for gathering such data is very small and occurs only once in a given mission. Commercially popular and fully developed Flash NVM technology is inappropriate for many reasons such as the limited read write cycles with slower access speeds, radiation intolerance, higher Single Event Upsets (SEU) rates, etc. It is desirable to have an NVM system based upon a robust cell technology making it immune to the SEUs and with sufficient radiation hardness. Availability of such NVM system seems to be still 5 to 10 years in the future. Meanwhile, it is possible to provide an interim hybrid solution by combining the existing rad-hard technologies. Additional information is contained in the original extended abstract.

  1. Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

    2004-01-01

    We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

  2. Reconfigurable magnetic logic combined with non-volatile memory in silicon

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.

  3. Biomolecule nanoparticle-induced nanocomposites with resistive switching nonvolatile memory properties

    NASA Astrophysics Data System (ADS)

    Ko, Yongmin; Ryu, Sook Won; Cho, Jinhan

    2016-04-01

    Resistive switching behavior-based memory devices are considered promising candidates for next-generation data storage because of their simple structure configuration, low power consumption, and rapid operating speed. Here, the resistive switching nonvolatile memory properties of Fe2O3 nanocomposite (NC) films prepared from the thermal calcination of layer-by-layer (LbL) assembled ferritin multilayers were successfully investigated. For this study, negatively charged ferritin nanoparticles were alternately deposited onto the Pt-coated Si substrate with positively charged poly(allylamine hydrochloride) (PAH) by solution-based electrostatic LbL assembly, and the formed multilayers were thermally calcinated to obtain a homogeneous transition metal oxide NC film through the elimination of organic components, including the protein shell of ferritin. The formed memory device exhibits a stable ON/OFF current ratio of approximately 103, with nanosecond switching times under an applied external bias. In addition, these reversible switching properties were kept stable during the repeated cycling tests of above 200 cycles and a test period of approximately 105 s under atmosphere. These solution-based approaches can provide a basis for large-area inorganic nanoparticle-based electric devices through the design of bio-nanomaterials at the molecular level.

  4. Determining the state of non-volatile memory cells with floating gate using scanning probe microscopy

    NASA Astrophysics Data System (ADS)

    Hanzii, D.; Kelm, E.; Luapunov, N.; Milovanov, R.; Molodcova, G.; Yanul, M.; Zubov, D.

    2013-01-01

    During a failure analysis of integrated circuits, containing non-volatile memory, it is often necessary to determine its contents while Standard memory reading procedures are not applicable. This article considers how the state of NVM cells with floating gate can be determined using scanning probe microscopy. Samples preparation and measuring procedure are described with the example of Microchip microcontrollers with the EPROM memory (PIC12C508) and flash-EEPROM memory (PIC16F876A).

  5. Printed dose-recording tag based on organic complementary circuits and ferroelectric nonvolatile memories

    PubMed Central

    Nga Ng, Tse; Schwartz, David E.; Mei, Ping; Krusor, Brent; Kor, Sivkheng; Veres, Janos; Bröms, Per; Eriksson, Torbjörn; Wang, Yong; Hagel, Olle; Karlsson, Christer

    2015-01-01

    We have demonstrated a printed electronic tag that monitors time-integrated sensor signals and writes to nonvolatile memories for later readout. The tag is additively fabricated on flexible plastic foil and comprises a thermistor divider, complementary organic circuits, and two nonvolatile memory cells. With a supply voltage below 30 V, the threshold temperatures can be tuned between 0 °C and 80 °C. The time-temperature dose measurement is calibrated for minute-scale integration. The two memory bits are sequentially written in a thermometer code to provide an accumulated dose record. PMID:26307438

  6. Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2010-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

  7. Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2011-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

  8. Design of a Photoactive Hybrid Bilayer Dielectric for Flexible Nonvolatile Organic Memory Transistors.

    PubMed

    Chen, Hongliang; Cheng, Nongyi; Ma, Wei; Li, Mingliang; Hu, Shuxin; Gu, Lin; Meng, Sheng; Guo, Xuefeng

    2016-01-26

    Organic field-effect transistors (OFETs) featuring a photoactive hybrid bilayer dielectric (PHBD) that comprises a self-assembled monolayer (SAM) of photochromic diarylethenes (DAEs) and an ultrathin solution-processed hafnium oxide layer are described here. We photoengineer the energy levels of DAE SAMs to facilitate the charging and discharging of the interface of the two dielectrics, thus yielding an OFET that functions as a nonvolatile memory device. The transistors use light signals for programming and electrical signals for erasing (≤3 V) to produce a large, reversible threshold-voltage shift with long retention times and good nondestructive signal processing ability. The memory effect can be exercised by more than 10(4) memory cycles. Furthermore, these memory cells have demonstrated the capacity to be arrayed into a photosensor matrix on flexible plastic substrates to detect the spatial distribution of a confined light and then store the analog sensor input as a two-dimensional image with high precision over a long period of time. PMID:26673624

  9. Epitaxial Growth of Thin Ferroelectric Polymer Films on Graphene Layer for Fully Transparent and Flexible Nonvolatile Memory.

    PubMed

    Kim, Kang Lib; Lee, Wonho; Hwang, Sun Kak; Joo, Se Hun; Cho, Suk Man; Song, Giyoung; Cho, Sung Hwan; Jeong, Beomjin; Hwang, Ihn; Ahn, Jong-Hyun; Yu, Young-Jun; Shin, Tae Joo; Kwak, Sang Kyu; Kang, Seok Ju; Park, Cheolmin

    2016-01-13

    Enhancing the device performance of organic memory devices while providing high optical transparency and mechanical flexibility requires an optimized combination of functional materials and smart device architecture design. However, it remains a great challenge to realize fully functional transparent and mechanically durable nonvolatile memory because of the limitations of conventional rigid, opaque metal electrodes. Here, we demonstrate ferroelectric nonvolatile memory devices that use graphene electrodes as the epitaxial growth substrate for crystalline poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) polymer. The strong crystallographic interaction between PVDF-TrFE and graphene results in the orientation of the crystals with distinct symmetry, which is favorable for polarization switching upon the electric field. The epitaxial growth of PVDF-TrFE on a graphene layer thus provides excellent ferroelectric performance with high remnant polarization in metal/ferroelectric polymer/metal devices. Furthermore, a fully transparent and flexible array of ferroelectric field effect transistors was successfully realized by adopting transparent poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] semiconducting polymer. PMID:26618802

  10. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    NASA Astrophysics Data System (ADS)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  11. Improvement of memory window and retention with low trap density in hydrogenated-amorphous-silicon-germanium nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Choi, Woojin; Jang, Kyungsoo; Raja, Jayapal; Cho, Jaehyun; Hanh Nguyen, Hong; Kim, Minbum; Kim, Jiwoong; Lee, YounJung; Nagarajan, Balaji; Yi, Junsin

    2013-03-01

    We report the SiO2/SiOX/SiOXNY (OOXON) stacked nonvolatile memory (NVM) using hydrogenated amorphous silicon germanium (a-SiXGe1-X:H) as an active channel layer. In NVMs, the reduction of interface trap density is one of the key issues to improve device performance including memory window and retention. The NVMs using a-SiGe:H as the active channel overcame the limitation of small memory window size and poor retention characteristics by controlling the interface trap density using different Ge contents in the surface SiGe layer. For a-Si:H NVM that does not contain Ge, the memory size is about 5.15 V, which is quite large, with a programming voltage of -7 V and an erasing voltage of +15 V. However, the retention time of over 10 years is almost impossible. For a-SiGe:H NVM with 20% Ge, the memory size is as large as 7.38 V and the retention data of ˜58% is possible even after 10 years due to the reduced trap density in OOXON and channel layers. When the Ge content is more than 20%, the memory size and retention property after 10 years decrease rapidly. When the contents of Ge in SiGe films reach a certain point, they act as defects lowering the properties. The results of NVM devices using a-SiGe:H (Ge 20%) as an active channel layer demonstrate that they have switching characteristics suitable for data storage such as a threshold voltage window.

  12. Multilevel resistive switching nonvolatile memory based on MoS2 nanosheet-embedded graphene oxide

    NASA Astrophysics Data System (ADS)

    Shin, Gwang Hyuk; Kim, Choong-Ki; Bang, Gyeong Sook; Kim, Jong Yun; Jang, Byung Chul; Koo, Beom Jun; Woo, Myung Hun; Choi, Yang-Kyu; Choi, Sung-Yool

    2016-09-01

    An increasing demand for nonvolatile memory has driven extensive research on resistive switching memory because it uses simple structures with high density, fast switching speed, and low power consumption. To improve the storage density, the application of multilevel cells is among the most promising solutions, including three-dimensional cross-point array architectures. Two-dimensional nanomaterials have several advantages as resistive switching media, including flexibility, low cost, and simple fabrication processes. However, few reports exist on multilevel nonvolatile memory and its switching mechanism. We herein present a multilevel resistive switching memory based on graphene oxide (GO) and MoS2 fabricated by a simple spin-coating process. Metallic 1T-MoS2 nanosheets, chemically exfoliated by Li intercalation, were successfully embedded between two GO layers as charge-trapping sites. The resulting stacks of GO/MoS2/GO exhibited excellent nonvolatile memory performance with at least four resistance states, >102 endurance cycles, and >104 s retention time. Furthermore, the charge transport mechanism was systematically investigated through the analysis of low-frequency 1/f noise in various resistance states, which could be modulated by the input voltage bias in the negative differential resistance region. Accordingly, we propose a strategy to achieve multilevel nonvolatile memory in which the stacked layers of two-dimensional nanosheets are utilized as resistive and charge-storage materials.

  13. The role of non-volatile memory from an application perspective

    SciTech Connect

    Kettering, Brett M; Nunez, James A

    2010-09-16

    Current, emerging, and future NVM (non-volatile memory) technologies give us hope that we will be able to architect HPC (high performance computing) systems that initially use them in a memory and storage hierarchy, and eventually use them as the memory and storage for the system, complete with ownership and protections as a HDD-based (hard-disk-drive-based) file system provides today.

  14. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    SciTech Connect

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  15. Silicon-based current-controlled reconfigurable magnetoresistance logic combined with non-volatile memory

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaozhong; Luo, Zhaochu

    2015-03-01

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success. However, the traditional development pathway is approaching its fundamental limits. Magnetoelectronics logic, especially magnetic-field-based logic, shows promise for surpassing the development limits of CMOS logic. Existing proposals of magnetic-field-based logic are based on exotic semiconductors and difficult for further technological implementation. We proposed a kind of diode-assisted geometry-enhanced low-magnetic-field magnetoresistance (MR) mechanism. It couples p-n junction's nonlinear transport characteristic and Lorentz force by geometry, and shows extremely large low-magnetic-field MR (>120% at 0.15 T) Further, it is applied to experimentally demonstrate current-controlled reconfigurable MR logic on the silicon platform at room temperature. This logic device could perform Boolean logic AND, OR, NAND and NOR in one device. Combined with non-volatile magnetic memory, this logic architecture has the advantages of current-controlled reconfiguration, zero refresh consumption, instant-on performance and would bridge the processor-memory gap.

  16. Low-Dimensional Polyoxometalate Molecules/Tantalum Oxide Hybrids for Non-Volatile Capacitive Memories.

    PubMed

    Balliou, Angelika; Papadimitropoulos, Giorgos; Skoulatakis, George; Kennou, Stella; Davazoglou, Dimitrios; Gardelis, Spiros; Glezos, Nikos

    2016-03-23

    Transition-metal-oxide hybrids composed of high surface-to-volume ratio Ta2O5 matrices and a molecular analogue of transition metal oxides, tungsten polyoxometalates ([PW12O40](3-)), are introduced herein as a charge storage medium in molecular nonvolatile capacitive memory cells. The polyoxometalate molecules are electrostatically self-assembled on a low-dimensional Ta2O5 matrix, functionalized with an aminosilane molecule with primary amines as the anchoring moiety. The charge trapping sites are located onto the metal framework of the electron-accepting molecular entities as well as on the molecule/oxide interfaces which can immobilize negatively charged mobile oxygen vacancies. The memory characteristics of this novel nanocomposite were tested using no blocking oxide for extraction of structure-specific characteristics. The film was formed on top of the 3.1 nm-thick SiO2/n-Si(001) substrates and has been found to serve as both SiO2/Si interface states' reducer (i.e., quality enhancer) and electron storage medium. The device with the polyoxometalates sandwiched between two Ta2O5 films results in enhanced internal scattering of carriers. Thanks to this, it exhibits a significantly larger memory window than the one containing the plain hybrid and comparable retention time, resulting in a memory window of 4.0 V for the write state and a retention time around 10(4) s without blocking medium. Differential distance of molecular trapping centers from the cell's gate and electronic coupling to the space charge region of the underlying Si substrate were identified as critical parameters for enhanced electron trapping for the first time in such devices. Implementing a numerical electrostatic model incorporating structural and electronic characteristics of the molecular nodes derived from scanning probe and spectroscopic characterization, we are able to interpret the hybrid's electrical response and gain some insight into the electrostatics of the trapping medium. PMID

  17. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    SciTech Connect

    Jovanović, B. E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L.

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  18. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    NASA Astrophysics Data System (ADS)

    Jovanović, B.; Brum, R. M.; Torres, L.

    2014-04-01

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  19. Development and characterization of a ferroelectric non-volatile memory for flexible electronics

    NASA Astrophysics Data System (ADS)

    Mao, Duo

    Flexible electronics have received significant attention recently because of the potential applications in displays, sensors, radio frequency identification (RFID) tags and other integrated circuits. Electrically addressable non-volatile memory is a key component for these applications. The major challenges are to fabricate the memory at a low temperature compatible with plastic substrates while maintaining good device reliability, by being compatible with process as needed to integrate with other electronic components for system-on-chip applications. In this work, ferroelectric capacitors fabricated at low temperature were developed. Based on that, a ferroelectric random access memory (FRAM) for flexible electronics was developed and characterized. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer was used as a ferroelectric material and a photolithographic process was developed to fabricate ferroelectric capacitors. Different characterization methods including atomic force microscopy, x-ray diffraction and Fourier-transform infrared reflection-absorption spectroscopy were used to study the material properties of the P(VDF-TrFE) film. The material properties were correlated with the electrical characteristics of the ferroelectric capacitors. To understand the polarization switching behavior of the P(VDF-TrFE) ferroelectric capacitors, a Nucleation-Limited-Switching (NLS) model was used to study the switching kinetics. The switching kinetics were characterized over the temperature range from -60 °C to 100 °C. Fatigue characteristics were studied at different electrical stress voltages and frequencies to evaluate the reliability of the ferroelectric capacitor. The degradation mechanism is attributed to the increase of the activation field and the suppression of the switchable polarization. To develop a FRAM circuit for flexible electronics, an n-channel thin film transistor (TFT) based on CdS as the semiconductor was integrated with a P

  20. Memory device using movement of protons

    DOEpatents

    Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

    1998-11-03

    An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

  1. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

    1998-01-01

    An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

  2. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

    2000-01-01

    An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

  3. Inkjet-printing of non-volatile organic resistive devices and crossbar array structures

    NASA Astrophysics Data System (ADS)

    Sax, Stefan; Nau, Sebastian; Popovic, Karl; Bluemel, Alexander; Klug, Andreas; List-Kratochvil, Emil J. W.

    2015-09-01

    Due to the increasing demand for storage capacity in various electronic gadgets like mobile phones or tablets, new types of non-volatile memory devices have gained a lot of attention over the last few years. Especially multilevel conductance switching elements based on organic semiconductors are of great interest due to their relatively simple device architecture and their small feature size. Since organic semiconductors combine the electronic properties of inorganic materials with the mechanical characteristics of polymers, this class of materials is suitable for solution based large area device preparation techniques. Consequently, inkjet based deposition techniques are highly capable of facing preparation related challenges. By gradually replacing the evaporated electrodes with inkjet printed silver, the preparation related influence onto device performance parameters such as the ON/OFF ratio was investigated with IV measurements and high resolution transmission electron microscopy. Due to the electrode surface roughness the solvent load during the printing of the top electrode as well as organic layer inhomogeneity's the utilization in array applications is hampered. As a prototypical example a 1diode-1resistor element and a 2×2 subarray from 5×5 array matrix were fully characterized demonstrating the versatility of inkjet printing for device preparation.

  4. A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

    NASA Technical Reports Server (NTRS)

    Liu, S. Q.; Wu, N. J.; Ignatiev, A.

    2001-01-01

    A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

  5. Bipolar resistive switching based on bis(8-hydroxyquinoline) cadmium complex: Mechanism and non-volatile memory application

    NASA Astrophysics Data System (ADS)

    Wang, Ying; Yang, Ting; Xie, Ji-Peng; Lü, Wen-Li; Fan, Guo-Ying; Liu, Su

    2013-07-01

    Stable and persistent bipolar resistive switching was observed in an organic diode with the structure of indium-tin oxide (ITO)/bis(8-hydroxyquinoline) cadmium (Cdq2)/Al. Aggregate formation and electric field driven trapping and de-trapping of charge carriers in the aggregate states that lie in the energy gap of the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) of the organic molecule were proposed as the mechanism of the observed bipolar resistive switching, and this was solidly supported by the results of AFM investigations. Repeatedly set, read, and reset measurements demonstrated that the device is potentially applicable in non-volatile memories.

  6. Review of Emerging New Solid-State Non-Volatile Memories

    NASA Astrophysics Data System (ADS)

    Fujisaki, Yoshihisa

    2013-04-01

    The integration limit of flash memories is approaching, and many new types of memory to replace conventional flash memories have been proposed. Unlike flash memories, new nonvolatile memories do not require storage of electric charges. The possibility of phase-change random-access memories (PCRAMs) or resistive-change RAMs (ReRAMs) replacing ultrahigh-density NAND flash memories has been investigated; however, many issues remain to be overcome, making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and magnetoresistive RAMs (MRAMs) are gradually penetrating into fields where the shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use inconvenient. For instance, FeRAMs are widely used in ICs that require low power consumption such as smart cards and wireless tags. MRAMs are used in many kinds of controllers in industrial equipment that require high speed and unlimited rewrite operations. For successful application of new non-volatile semiconductor memories, such memories must be practically utilized in new fields in which flash memories are not applicable, and their technologies must be further developed.

  7. Nonvolatile read/write memory element - A concept

    NASA Technical Reports Server (NTRS)

    Cricchi, J. R.; Lytle, W. J.

    1971-01-01

    Memory, with limited number of programming cycles, is achieved by using verticle, fusible links in series with oxide breakthrough elements. Memory elements are fabricated with integrated circuit technology and are ideal for low power digital computer application.

  8. Scaling Analysis of Nanoelectromechanical Memory Devices

    NASA Astrophysics Data System (ADS)

    Nagami, Tasuku; Tsuchiya, Yoshishige; Uchida, Ken; Mizuta, Hiroshi; Oda, Shunri

    2010-04-01

    Numerical simulation of electromechanical switching for bistable bridges in non-volatile nanoelectromechanical (NEM) memory devices suggests that performance of memory characteristics enhanced by decreasing suspended floating gate length. By conducting a two-dimensional finite element electromechanical simulation combined with a drift-diffusion analysis, we analyze the electromechanical switching operation of miniaturized structures. By shrinking the NEM floating gate length from 1000 to 100 nm, the switching (set/reset) voltage reduces from 7.2 to 2.8 V, switching time from 63 to 4.6 ns, power consumption from 16.9 to 0.13 fJ. This indicates the advantage of fast and low-power memory characteristics.

  9. Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions

    PubMed Central

    Yau, H. M.; Yan, Z. B.; Chan, N. Y.; Au, K.; Wong, C. M.; Leung, C. W.; Zhang, F.Y.; Gao, X. S.; Dai, J. Y.

    2015-01-01

    Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure. PMID:26239505

  10. Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions.

    PubMed

    Yau, H M; Yan, Z B; Chan, N Y; Au, K; Wong, C M; Leung, C W; Zhang, F Y; Gao, X S; Dai, J Y

    2015-01-01

    Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure. PMID:26239505

  11. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    SciTech Connect

    Han, Jinhua; Wang, Wei Ying, Jun; Xie, Wenfa

    2014-01-06

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

  12. Alloy perovskite oxide thin film as resistance switching non-volatile memory

    NASA Astrophysics Data System (ADS)

    Wang, Yudi

    Nonvolatile memory that permanently stores data is indispensable for computers and hand-held devices. In the last few years, resistance memory (RRAM) has emerged as an intriguing possibility that might replace flash memory one day, which is widely used in hand-held and portable-storage devices. The newest, rapidly growing interest in resistance switching is focused on semiconducting oxides and other related materials. In this dissertation, a novel material system for oxide RRAM that offers unique advantages over all the other existing oxide RRAM materials was designed and systematically investigated. The primary aim of these studies is to obtain a material system with the intrinsic property that allows electrically-induced metal-insulator transition, which is regulated by electron trapping and release at some interval sites. A series of alloy perovskite oxides thin film systems were designed by combining a wide band gap insulator (CaZrO3 or LaAlO3) and a conductor with a narrow bandwidth (SrRuO3 or LaNiO3 ), with the conductor concentration near the percolation threshold. These alloy perovskite oxides thin films are almost atomically flat without any defects, such as cracks or crosshatches, which is achieved using well controlled deposition conditions that favor domain-boundary relaxation of the large misfit strain. The bottom electrode is a single crystalline SrRuO 3 thin film, deposited on a single crystal substrate of SrTiO3 which exhibits high conductivity and ferromagnetic transition at ˜150K. The alloy thin films manifest an anisotropic percolation phenomenon: below a critical thickness a metallic conducting path always exists across the film thickness direction but not along the in-plane direction, which ensures electrical isolation between neighboring memory cells. These initially conducting films present excellent resistance switching properties: low switching voltages (1-3 V), high switching ratio (˜100), fast switching speed (50 ns), good switching

  13. Fabrication of nanostructure and formation of nanocrystal for non-volatile memory.

    PubMed

    Jung, Sungwook; Parm, I O; Jang, Kyung Soo; Park, Dae-Ho; Sohn, Byeong-Hyeok; Jung, Jin Chul; Zin, Wang Cheol; Choi, Suk-Ho; Dhungel, S K; Yi, J

    2006-11-01

    In this work, we have demonstrated that the nanocrystal created by combining the self-assembled block copolymer thin film with regular semiconductor processing can be applicable to non-volatile memory device with increased charge storage capacity over planar structures. Self-assembled block copolymer thin film for nanostructures with critical dimensions below photolithographic resolution limits has been used during all experiments. Nanoporous thin film from PS-b-PMMA diblock copolymer thin film with selective removal of PMMA domains was used to fabricate nanostructure and nanocrystal. We have also reported about surface morphologies and electrical properties of the nano-needle structure formed by RIE technique. The details of nanoscale pattern of the very uniform arrays using RIE are presented. We fabricated different surface structure of nanoscale using block copolymer. We also deposited Si-rich SiNx layer using ICP-CVD on the silicon surface of nanostructure. The deposited films were studied after annealing. PL studies demonstrated nanocrystal in Si-rich SiNx film on nanostructure of silicon. PMID:17252830

  14. Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

    NASA Technical Reports Server (NTRS)

    Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

    1991-01-01

    The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

  15. Non-volatile memory elements based on the intercalation of organic molecules inside carbon nanotubes

    SciTech Connect

    Meunier, Vincent; Kalinin, Sergei V; Sumpter, Bobby G

    2007-01-01

    We propose a novel class of non-volatile memory elements based on the modification of the transport properties of a conducting carbon nanotube by the presence of a guest molecule having multiple stable orientational states relative to the nanotube that correspond to conducting and non-conducting states. The mechanism, governed by a local gating effect of the molecule on the electronic properties of the nanotube host, is studied using density functional theory. The mechanisms of reversible reading and writing of information are illustrated with a F4 TCNQ molecule encap-sulated inside a metallic carbon nanotube. Our results suggest that this new type of non-volatile memory element is robust, fatigue-free, and can operate at room temperature.

  16. Investigation of metal oxide dielectrics for non-volatile floating gate and resistance switching memory applications

    NASA Astrophysics Data System (ADS)

    Chakrabarti, Bhaswar

    Floating gate transistor based flash memories have seen more than a decade of continuous growth as the prominent non-volatile memory technology. However, the recent trends indicate that the scaling of flash memory is expected to saturate in the near future. Several alternative technologies are being considered for the replacement of flash in the near future. The basic motivation for this work is to investigate the material properties of metal oxide based high-k dielectrics for potential applications in floating gate and resistance switching memory applications. This dissertation can be divided into two main sections. In the first section, the tunneling characteristics of the SiO2/HfO 2 stacks were investigated. Previous theoretical studies for thin SiO 2/ thick high-k stacks predict an increase in tunneling current in the high-bias regime (better programming) and a decrease in the low-bias regime (better retention) in comparison to pure SiO2 of same equivalent oxide thickness (EOT). However, our studies indicated that the performance improvement in SiO2/HfO2 stacks with thick HfO2 layer is difficult due to significant amount of charge traps in thick HfO2 layers. Oxygen anneal on the stacks did not improve the programming current and retention. X-ray photoelectron spectroscopy (XPS) studies indicated that this was due to formation of an interfacial oxide layer. The second part of the dissertation deals with the investigation of resistive switching in metal oxides. Although promising, practical applications of resistive random access memories (RRAM) require addressing several issues including high forming voltage, large operating currents and reliability. We first investigated resistive switching in HfTiOx nanolaminate with conventional TiN electrodes. The forming-free switching observed in the structures could be described by the quantum point contact model. The modelling results indicated that the forming-free characteristics can be due to a higher number of

  17. Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

    NASA Astrophysics Data System (ADS)

    Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

    2016-07-01

    Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

  18. A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

    NASA Technical Reports Server (NTRS)

    Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

  19. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

    2000-01-01

    An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

  20. Ferroelastic switching for nanoscale non-volatile magnetoelectric devices

    SciTech Connect

    Baek, S. H.; Jang, H. W.; Folkman, C. M.; Li, Yulan; Winchester, B.; Zhang, J. X.; He, Q.; Chu, Y. H.; Nelson, C. T.; Rzchowski, M. S.; Pan, X. Q.; Ramesh, R.; Chen , L.Q.; Eom, C.B.

    2010-04-01

    Multiferroics, where (anti-) ferromagnetic, ferroelectric, and ferroelastic order parameters coexist [1-5], enables manipulation of magnetic ordering by electric field through switching of the electric polarization [6-9]. It has been shown that realization of magnetoelectric coupling in single-phase multiferroic such as BiFeO3 requires ferroelastic (71o, 109o) rather than ferroelectric (180o) domain switching [6]. However, the control of such ferroleastic switching in a singlephase system has been a significant challenge as elastic interactions tend to destabilize small switched volumes, resulting in subsequent ferroelastic backswitching at zero electric field, thus disappearance of nonvolatile information storage [10, 11]. Guided by our phase-field simulations, we here report an approach to stabilize ferroelastic switching by eliminating the stress-induced instability responsible for back-switching using isolated monodomain BiFeO3islands. This work demonstrates a critical step to control and utilize nonvolatile magnetoelectric coupling at the nanoscale. Beyond magnetoelectric coupling, it provides a framework for exploring a route to control multiple order parameters coupled to ferroelastic order in other low-symmetry materials.

  1. Thin dielectric technology and memory devices

    NASA Astrophysics Data System (ADS)

    King, Ya-Chin

    With advances in technology and scaling, silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based VLSI circuits have remained dominant in data processing and memory applications. Perpetuated by the demand for high-performance and low-cost integrated circuits, the lateral dimensions of the MOSFETs are being aggressively scaled. This in turn demands scaling of the gate oxide thickness as well. Thin gate oxides present both challenges to the modeling and design device of the classical MOSFET and opportunities to explore new device designs and applications. This study investigates the effect of inversion layer quantization on the capacitance and current characteristics of thin-gate-oxide MOS transistors. In addition, this study explores the possibility of employing thin tunnel oxide for new quasi-nonvolatile memory devices. The performance limitation of a thin dielectric floating gate memory device as well as its potential for dynamic memory applications are discussed. An alternative device structure (i.e. charge-trap based memory cells) is examined by the single charge tunneling model governed by Coulomb Blockade theory. Two methods of forming charge storage nodes embedded in the gate dielectric are investigated. The resulting devices are then characterized. The first proposed device contains a charge trapping layer of silicon rich oxide (SRO) for dynamic/non-volatile memory application. This device has a similar structure as a MONOS device with SRO instead of silicon nitride for charge trapping on top of a very thin tunneling oxide (<2nm). Since it uses charge trapped in the oxide to create threshold voltage shift, the SRO memory cell is a non-destructive-read device. A new process of depositing SRO and high temperature oxide (HTO) in a single furnace step is developed to better top the control oxide thickness and improve data retention. This device achieved write and erase speeds comparable to that of a DRAM cell and longer data retention time than

  2. Nonvolatile Quantum Dot Gate Memory (NVQDM): Tunneling Rate from Quantum Well Channel to Quantum Dot Gate

    NASA Astrophysics Data System (ADS)

    Hasaneen, El-Sayed; Heller, Evan; Bansal, Rajeev; Jain, Faquir

    2003-10-01

    In this paper, we compute the tunneling of electrons in a nonvolatile quantum dot memory (NVQDM) cell during the WRITE operation. The transition rate of electrons from a quantum well channel to the quantum dots forming the floating gate is calculated using a recently reported method by Chuang et al.[1]. Tunneling current is computed based on transport of electrons from the channel to the floating quantum dots. The maximum number of electrons on a dot is calculated using surface electric field and break down voltage of the tunneling dielectric material. Comparison of tunneling for silicon oxide and high-k dielectric gate insulators is also described. Capacitance-Voltage characteristics of a NVQDM device are calculated by solving the Schrodinger and Poisson equations self-consistently. In addition, the READ operation of the memory has been investigated analytically. Results for 70 nm channel length Si NVQDMs are presented. Threshold voltage is calculated including the effect of the charge on nanocrystal quantum dots. Current-voltage characteristics are obtained using BSIM3v3 model [2-3]. This work is supported by Office of Navel Research (N00014210883, Dr. D. Purdy, Program Monitor), Connecticut Innovations Inc./TranSwitch (CII # 00Y17), and National Science Foundation (CCR-0210428) grants. [1] S. L. Chuang and N. Holonyak, Appl. Phys. Lett., 80, pp. 1270, 2002. [2] Y. Chen et. al., BSIM3v3 Manual, Elect. Eng. and Comp. Dept., U. California, Berkeley, CA, 1996. [3] W. Liu, MOSFET Models for SPICE Simulation, John Wiley & Sons, Inc., 2001.

  3. High-G testing of MEMS mechanical non-volatile memory and silicon re-entry switch.

    SciTech Connect

    Baker, Michael Sean; Pohl, Kenneth Roy

    2005-10-01

    Two different Sandia MEMS devices have been tested in a high-g environment to determine their performance and survivability. The first test was performed using a drop-table to produce a peak acceleration load of 1792 g's over a period of 1.5 ms. For the second test the MEMS devices were assembled in a gun-fired penetrator and shot into a cement target at the Army Waterways Experiment Station in Vicksburg Mississippi. This test resulted in a peak acceleration of 7191 g's for a duration of 5.5 ms. The MEMS devices were instrumented using the MEMS Diagnostic Extraction System (MDES), which is capable of driving the devices and recording the device output data during the high-g event, providing in-flight data to assess the device performance. A total of six devices were monitored during the experiments, four mechanical non-volatile memory devices (MNVM) and two Silicon Reentry Switches (SiRES). All six devices functioned properly before, during, and after each high-g test without a single failure. This is the first known test under flight conditions of an active, powered MEMS device at Sandia.

  4. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    SciTech Connect

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-30

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgO{sub x} and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgO{sub x} gate operates under low voltage write-erase (WR-ER) pulse of {+-}20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of {+-}70 V for WR and ER states. Both devices stably operated under visible illuminations.

  5. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    SciTech Connect

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin E-mail: chilf@suda.edu.cn Chi, Li-Feng E-mail: chilf@suda.edu.cn Wang, Sui-Dong E-mail: chilf@suda.edu.cn

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  6. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  7. A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

    NASA Astrophysics Data System (ADS)

    Wu, Ming-Chi; Jang, Wen-Yueh; Lin, Chen-Hsi; Tseng, Tseung-Yuen

    2012-06-01

    Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO2/Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO2/Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO2-based RRAM is a prospective alternative for nonvolatile multilevel memory device applications.

  8. Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

    NASA Astrophysics Data System (ADS)

    Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

    2015-09-01

    Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

  9. TOPICAL REVIEW Nanoscale memory devices

    NASA Astrophysics Data System (ADS)

    Chung, Andy; Deen, Jamal; Lee, Jeong-Soo; Meyyappan, M.

    2010-10-01

    This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO2.

  10. Multifunctional organic phototransistor-based nonvolatile memory achieved by UV/ozone treatment of the Ta₂O₅ gate dielectric.

    PubMed

    Liu, Xiaohui; Zhao, Haoyan; Dong, Guifang; Duan, Lian; Li, Dong; Wang, Liduo; Qiu, Yong

    2014-06-11

    An organic phototransistor (OPT) shows nonvolatile memory effect due to its novel optical writing and electrical erasing processes. In this work, we utilize an organic light-emitting diode (OLED) as the light source to investigate OPT-based memory (OPTM) performance. It is found that the OPTM can be used as either flash memory or write-once read-many-times memory by adjusting the properties of the Ta2O5 gate dielectric layer. UV/ozone treatment is applied to effectively change dielectric properties of the Ta2O5 film. The mechanisms for this are examined by X-ray photoelectron spectroscopy and capacitance-voltage measurement. It turns out that the densities of oxygen vacancies and defects in the first 1.8 nm Ta2O5 films near the Ta2O5/semiconductor interface are reduced. Furthermore, for the first time, we use this multifunctional OPTM, which unites the photosensitive and memory properties in one single device, as an optical feedback system to tune the brightness of the OLED. Our study suggests that these OPTMs have potential applications in tuning the brightness uniformity, improving the display quality and prolonging the lifetime of flat panel displays. PMID:24813352

  11. Non-Volatile Flash Memory Characteristics of Tetralayer Nickel-Germanide Nanocrystals Embedded Structure.

    PubMed

    Panda, D; Panda, M

    2016-01-01

    Formation of tetralayer memory structure having nickel-germanide nanocrystals using a Ge/Ni multilayers is proposed. X-ray diffraction study shows the NiGe (002) phase formation after proper annealing. Cross sectional HRTEM clearly shows the sharpness and the size (~4-6 nm) of the stacked nanocrystals embedded in the oxide matrix. A large anti-clockwise hysteresis memory win- dow of 13.4 Volt at ± 15 Volt is observed for the optimized samples. This large memory window indicates for the MLC applications. Frequency independent C-V curve confirms about the charge storage in the nanocrystals. A good charge retention and endurance characteristics are exhibited upto 125 °C for the nonvolatile memory application. PMID:27398590

  12. Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

    NASA Astrophysics Data System (ADS)

    Zhu, Xiaoxiao; Li, Qiliang; Ioannou, Dimitris E.; Gu, Diefeng; Bonevich, John E.; Baumgart, Helmut; Suehle, John S.; Richter, Curt A.

    2011-06-01

    We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO2 charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO2 increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO2 thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.

  13. 5 V driving organic non-volatile memory transistors with poly(vinyl alcohol) gate insulator and poly(3-hexylthiophene) channel layers

    NASA Astrophysics Data System (ADS)

    Nam, Sungho; Seo, Jooyeok; Kim, Hwajeong; Kim, Youngkyoo

    2015-10-01

    Organic non-volatile memory devices were fabricated by employing organic field-effect transistors (OFETs) with poly(vinyl alcohol) (PVA) and poly(3-hexylthiophene) as a gate insulating layer and a channel layer, respectively. The 10-nm-thick nickel layers were inserted for better charge injection between the channel layer and the top source/drain electrodes. The fabricated PVA-OFET memory devices could be operated at low voltages (≤5 V) and showed pronounced hysteresis characteristics in the transfer curves, even though very small hysteresis was measured from the output curves. The degree of hysteresis was considerably dependent on the ratio of channel width (W) to channel length (L). The PVA-OFET memory device with the smaller W/L ratio (25) exhibited better retention characteristics upon 700 cycles of writing-reading-erasing-reading operations, which was assigned to the stability of charged states in devices.

  14. Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag2S nanoparticles

    NASA Astrophysics Data System (ADS)

    Jang, Jaewon

    2016-07-01

    In this study, Ag2S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag2S films are successfully crystallized on plastic substrates with synthesized Ag2S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag2S/metal structures are fabricated and tested. The effect of the electrode material on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 103 cycles and 104 sec, respectively.

  15. Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Allen, Gregory R.

    2012-01-01

    The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

  16. A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory

    PubMed Central

    2014-01-01

    This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplicity of its use and the ease with which it can be embedded in Si wafer, glass, and flexible substrates. This device exhibits excellent retention, with a memory window maintained 2 V after 104 s. By extrapolation, 95% of the original charge can be stored for 10 years. In the future, this device will be applied to multi-layer Si ICs in fully functional systems on panels, active-matrix liquid-crystal displays, and three-dimensional (3D) stacked flash memory. PMID:25404873

  17. Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

    NASA Technical Reports Server (NTRS)

    Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2011-01-01

    The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

  18. Fully transparent nonvolatile memory employing amorphous oxides as charge trap and transistor's channel layer

    NASA Astrophysics Data System (ADS)

    Yin, Huaxiang; Kim, Sunil; Kim, Chang Jung; Song, Ihun; Park, Jaechul; Kim, Sangwook; Park, Youngsoo

    2008-10-01

    A fully transparent nonvolatile memory with the conventional sandwich gate insulator structure was demonstrated. Wide band gap amorphous GaInZnO (a-GIZO) thin films were employed as both the charge trap layer and the transistor channel layer. An excellent program window of 3.5 V with a stressing time of 100 ms was achieved through the well-known Fowler-Nordheim tunneling method. Due to the similar energy levels extracted from the experimental data, the asymmetrical program/erase characteristics are believed to be the result of the strong trapping of the injected negative charges in the shallow donor levels of the GIZO film.

  19. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    SciTech Connect

    Wang, Wei Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-22

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  20. Electrical Bistabilities and Conduction Mechanisms of Nonvolatile Memories Based on a Polymethylsilsesquioxane Insulating Layer Containing CdSe/ZnS Quantum Dots

    NASA Astrophysics Data System (ADS)

    Ma, Zehao; Ooi, Poh Choon; Li, Fushan; Yun, Dong Yeol; Kim, Tae Whan

    2015-10-01

    Nonvolatile memory (NVM) devices based on a metal-insulator-metal structure consisting of CdSe/ZnS quantum dots embedded in polymethylsilsesquioxane dielectric layers were fabricated. The current-voltage ( I- V) curves showed a bistable current behavior and the presence of hysteresis. The current-time ( I- t) curves showed that the fabricated NVM memory devices were stable up to 1 × 104 s with a distinct ON/OFF ratio of 104 and were reprogrammable when the endurance test was performed. The extrapolation of the I- t curve to 105 s with corresponding current ON/OFF ratio 1 × 105 indicated a long performance stability of the NVM devices. Schottky emission, Poole-Frenkel emission, trapped-charge limited-current and Child-Langmuir law were proposed as the dominant conduction mechanisms for the fabricated NVM devices based on the obtained I- V characteristics.

  1. Nonvolatile memories by using charge traps in silicon-rich oxides

    NASA Astrophysics Data System (ADS)

    Lim, Keun Yong; Kim, Min Choul; Hong, Seung Hui; Choi, Suk-Ho; Kim, Kyung Joong

    2010-08-01

    The nonvolatile memory characteristics of silicon-rich oxide (SRO, SiOx) grown at room temperature for charge-trapping layer are first reported and shown to exhibit a strong dependence on oxygen content (x). The memory window that is estimated by capacitance-voltage curves monotonically decreases with increasing x from 1.0 to 1.8, possibly resulting from the x-dependent variation in the Si suboxide states responsible for the charge traps, as evidenced by x-ray photoelectron spectroscopy. The density of the charge traps is estimated to be (3.9-8.8)×1012 cm-2 for x=1.0-1.4. The charge-loss rate sharply decreases at x=1.2, but by further increase in x above 1.2, it gradually increases, which can be explained by the lowered SRO/SiO2 barrier due to the increased optical band gap of SRO at larger x

  2. Reversible insulator-metal transition of LaAlO3/SrTiO3 interface for nonvolatile memory

    PubMed Central

    Lu, Hong-Liang; Liao, Zhi-Min; Zhang, Liang; Yuan, Wen-Tao; Wang, Yong; Ma, Xiu-Mei; Yu, Da-Peng

    2013-01-01

    We report a new type of memory device based on insulating LaAlO3/SrTiO3 (LAO/STO) hetero-interface. The microstructures of the LAO/STO interface are characterized by Cs-corrected scanning transmission electron microscopy, which reveals the element intermixing at the interface. The inhomogeneous element distribution may result in carrier localization, which is responsible for the insulating state. The insulating state of such interface can be converted to metallic state by light illumination and the metallic state maintains after light off due to giant persistent photoconductivity (PPC) effect. The on/off ratio between the PPC and the initial dark conductance is as large as 105. The metallic state also can be converted back to insulating state by applying gate voltage. Reversible and reproducible resistive switching makes LAO/STO interface promising as a nonvolatile memory. Our results deepen the understanding of PPC phenomenon in LAO/STO, and pave the way for the development of all-oxide electronics integrating information storage devices. PMID:24100438

  3. Reversible insulator-metal transition of LaAlO3/SrTiO3 interface for nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Lu, Hong-Liang; Liao, Zhi-Min; Zhang, Liang; Yuan, Wen-Tao; Wang, Yong; Ma, Xiu-Mei; Yu, Da-Peng

    2013-10-01

    We report a new type of memory device based on insulating LaAlO3/SrTiO3 (LAO/STO) hetero-interface. The microstructures of the LAO/STO interface are characterized by Cs-corrected scanning transmission electron microscopy, which reveals the element intermixing at the interface. The inhomogeneous element distribution may result in carrier localization, which is responsible for the insulating state. The insulating state of such interface can be converted to metallic state by light illumination and the metallic state maintains after light off due to giant persistent photoconductivity (PPC) effect. The on/off ratio between the PPC and the initial dark conductance is as large as 105. The metallic state also can be converted back to insulating state by applying gate voltage. Reversible and reproducible resistive switching makes LAO/STO interface promising as a nonvolatile memory. Our results deepen the understanding of PPC phenomenon in LAO/STO, and pave the way for the development of all-oxide electronics integrating information storage devices.

  4. Memory bistable mechanisms of organic memory devices

    NASA Astrophysics Data System (ADS)

    Lee, Ching-Ting; Yu, Li-Zhen; Chen, Hung-Chun

    2010-07-01

    To investigate the memory bistable mechanisms of organic memory devices, the structure of [top Au anode/9,10-di(2-naphthyl)anthracene (ADN) active layer/bottom Au cathode] was deposited using a thermal deposition system. The Au atoms migrated into the ADN active layer was observed from the secondary ion mass spectrometry. The density of 9.6×1016 cm-3 and energy level of 0.553 eV of the induced trapping centers caused by the migrated Au atoms in the ADN active layer were calculated. The induced trapping centers did not influence the carrier injection barrier height between Au and ADN active layer. Therefore, the memory bistable behaviors of the organic memory devices were attributed to the induced trapping centers. The energy diagram was established to verify the mechanisms.

  5. High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

    SciTech Connect

    Nedic, Stanko; Welland, Mark E-mail: mew10@cam.ac.uk; Tea Chun, Young; Chu, Daping E-mail: mew10@cam.ac.uk; Hong, Woong-Ki

    2014-01-20

    A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10{sup 5}, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10{sup 4} s.

  6. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    NASA Astrophysics Data System (ADS)

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  7. Graphene–ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    PubMed Central

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer. PMID:26813710

  8. Forced ion migration for chalcogenide phase change memory device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A. (Inventor)

    2011-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

  9. Forced ion migration for chalcogenide phase change memory device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A. (Inventor)

    2012-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

  10. Forced Ion Migration for Chalcogenide Phase Change Memory Device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A (Inventor)

    2013-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

  11. Redox-Active Molecular Nanowire Flash Memory for High-Endurance and High-Density Nonvolatile Memory Applications.

    PubMed

    Zhu, Hao; Pookpanratana, Sujitra J; Bonevich, John E; Natoli, Sean N; Hacker, Christina A; Ren, Tong; Suehle, John S; Richter, Curt A; Li, Qiliang

    2015-12-16

    In this work, high-performance top-gated nanowire molecular flash memory has been fabricated with redox-active molecules. Different molecules with one and two redox centers have been tested. The flash memory has clean solid/molecule and dielectric interfaces, due to the pristine molecular self-assembly and the nanowire device self-alignment fabrication process. The memory cells exhibit discrete charged states at small gate voltages. Such multi-bit memory in one cell is favorable for high-density storage. These memory devices exhibit fast speed, low power, long memory retention, and exceptionally good endurance (>10(9) cycles). The excellent characteristics are derived from the intrinsic charge-storage properties of the protected redox-active molecules. Such multi-bit molecular flash memory is very attractive for high-endurance and high-density on-chip memory applications in future portable electronics. PMID:26600234

  12. Investigation of Nonvolatile Memory Effect of Organic Thin-Film Transistors with Triple Dielectric Layers

    NASA Astrophysics Data System (ADS)

    Yu, Hsin-Chieh; Chen, Ying-Chih; Huang, Chun-Yuan; Su, Yan-Kuin

    2012-03-01

    Pentacene thin-film transistor (TFT) memory using poly(2-hydroxyethyl methacrylate) (PHEMA)-based polymer dielectric layers has been developed. The electric performance and memory behaviors of memory TFTs can be significantly improved by using triple polymer dielectric layers consisting of PHEMA/poly(methyl methacrylate) (PMMA)/PHEMA. This can be attributed to the improvement of the channel/dielectric interface. This memory effect is due to the charge storage of the dipolar group or molecules in the dielectric. The devices exhibit a wide memory window (ΔVth, >20 V), switchable channel current, and long retention time.

  13. Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

    SciTech Connect

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

    2013-12-16

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

  14. Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H2Pc heterojunction

    NASA Astrophysics Data System (ADS)

    Khasan, S. Karimov; Zubair, Ahmad; Farid, Touati; Mahroof-Tahir, M.; M. Muqeet, Rehman; S. Zameer, Abbas

    2015-11-01

    A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H2Pc are fabricated by vacuum deposition of the CuPc and H2Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 30-40 μm. For the current-voltage (I-V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120-150. Under the switching condition, the electric current increases ˜ 80-100 times. A comparison between the forward and reverse I-V characteristics shows the presence of rectifying behavior. Project supported by the GIK Institute of Engineering Science and Technology, Pakistan and Physical Technical Institute of Academy of Sciences of Tajikistan.

  15. A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

    SciTech Connect

    De, Arup

    2014-01-01

    Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

  16. High performance non-volatile memory with the control of charge trapping states in an amorphous InSnZnO active channel

    NASA Astrophysics Data System (ADS)

    Phu Thi Nguyen, Cam; Thuy Trinh, Thanh; Raja, Jayapal; Le, Anh Huy Tuan; Jang, Kyungsoo; Lee, Youn-Jung; Yi, Junsin

    2015-07-01

    In this study, the influence of interface states between an indium tin zinc oxide (ITZO) active layer and a gate insulator on memory characteristics was examined as a function of annealing temperature. The annealing nonvolatile memory (NVM) devices have shown the best electrical characteristics such as high field effect mobility (27.22 cm2 V-1 s-1), low threshold voltage (0.15 V), low subthreshold slope (0.17 V dec-1), and high on/off current ratio (7.57 × 107) in comparison with as-deposited devices. By annealing at 250 °C, the number of ITZO/insulator interface trap densities was reduced. The effect of the remaining trap states on the retention characteristic of memory devices is negligible. The performance of NVM devices using different annealing temperatures of ITZO and a multi-stack gate insulator SiO2/SiOx/SiOxNy with Si-rich SiOx for the charge storage layer was also reported. The 250 °C annealed ITZO-based NVM device showed a retention exceeding ˜94% of the threshold voltage shift after 104 s and greater than ˜90% after 10 years with a low operating voltage of +11 V at only 1 μs programming duration time. Therefore, the NVM devices, which were fabricated by the low ITZO/insulator interface trap densities, were highly suitable for potential application in memory systems.

  17. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-01

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively. PMID:25679117

  18. Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

    PubMed

    Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

    2015-10-27

    Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%. PMID:26370537

  19. Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

    SciTech Connect

    Chang, Yu-Chi; Wang, Yeong-Her

    2015-03-23

    Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect of Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.

  20. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

    NASA Astrophysics Data System (ADS)

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-06-01

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

  1. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires.

    PubMed

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-01-01

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques. PMID:27279431

  2. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

    PubMed Central

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-01-01

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques. PMID:27279431

  3. New memory devices based on the proton transfer process.

    PubMed

    Wierzbowska, Małgorzata

    2016-01-01

    Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing  information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge-saturated with oxygen or the hydroxy group-and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices. PMID:26596910

  4. New memory devices based on the proton transfer process

    NASA Astrophysics Data System (ADS)

    Wierzbowska, Małgorzata

    2016-01-01

    Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices.

  5. Three-terminal resistive switching memory in a transparent vertical-configuration device

    SciTech Connect

    Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

    2014-01-06

    The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

  6. Magnetic tunnel junction based spintronic logic and memory devices

    NASA Astrophysics Data System (ADS)

    Yao, Xiaofeng

    2011-12-01

    The development of semiconductor devices is limited by the high power consumption and further physical dimension reduction. Spintronic devices, especially the magnetic tunnel junction (MTJ) based devices, have advantages of non-volatility, reconfigurable capability, fast-switching speed, small-dimension, and compatibility to semiconductor devices, which is a promising candidate for future logic and memory devices. However, the previously proposed MTJ logic devices have been operated independently and therefore are limited to only basic logic operations. Consequently, the MTJ device has only been used as ancillary device in the circuit, rather than the main computation component. In this thesis, study has been done on both spintronic logic and memory devices. In the first part, systematic study has been performed on MTJ based logic devices in order to expand the functionalities and properties of MTJ devices. Basic logic cell with three-input has been designed and simulated. Nano-magnetic-channel has been proposed, which is the first design to realize the communication between the MTJ logic cells. With basic logic unit as a building block, a spintronic logic circuit has been designed with MTJ as the dominant component. HSPICE simulation has been done for this spintronic logic circuit, which acts as an Arithmetic Logic Unit. In the spintronic memory device part, study has been focused on the fundamental study on the current induced switching in MTJ devices with hybrid free layer. With hybrid free layer, magnetic non-uniformity is introduced along the current direction, which induces extra spin torque component. Unique current-induced switching has been observed and studied in the hybrid free layer MTJ. Adiabatic spin torque, which is introduced by spatial non-uniform magnetization in the hybrid free layer, plays an important role for the unique switching. By tuning the bias field, single-polar current switching was achieved in this hybrid MTJ device, which gives the

  7. Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

    NASA Astrophysics Data System (ADS)

    Huh, In; Cheon, Woo Young; Choi, Woo Young

    2016-04-01

    A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

  8. A Synthetic Multicellular Memory Device.

    PubMed

    Urrios, Arturo; Macia, Javier; Manzoni, Romilde; Conde, Núria; Bonforti, Adriano; de Nadal, Eulàlia; Posas, Francesc; Solé, Ricard

    2016-08-19

    Changing environments pose a challenge to living organisms. Cells need to gather and process incoming information, adapting to changes in predictable ways. This requires in particular the presence of memory, which allows different internal states to be stored. Biological memory can be stored by switches that retain information on past and present events. Synthetic biologists have implemented a number of memory devices for biological applications, mostly in single cells. It has been shown that the use of multicellular consortia provides interesting advantages to implement biological circuits. Here we show how to build a synthetic biological memory switch using an eukaryotic consortium. We engineered yeast cells that can communicate and retain memory of changes in the extracellular environment. These cells were able to produce and secrete a pheromone and sense a different pheromone following NOT logic. When the two strains were cocultured, they behaved as a double-negative-feedback motif with memory. In addition, we showed that memory can be effectively changed by the use of external inputs. Further optimization of these modules and addition of other cells could lead to new multicellular circuits that exhibit memory over a broad range of biological inputs. PMID:27439436

  9. Nonvolatile resistive switching memory properties of thermally annealed titania precursor/polyelectrolyte multilayers.

    PubMed

    Lee, Chanwoo; Kim, Inpyo; Shin, Hyunjung; Kim, Sanghyo; Cho, Jinhan

    2009-10-01

    We describe a novel and versatile approach for preparing resistive switching memory devices based on transition metal oxides. A titania precursor and poly(allyamine hydrochloride) (PAH) layers were deposited alternately onto platinum (Pt)-coated silicon substrates using electrostatic interactions. The multilayers were then converted to TiO2 nanocomposite (TiO2 NC) films after thermal annealing. A top electrode was coated on the TiO2 NC films to complete device fabrication. When an external bias was applied to the devices, a switching phenomenon independent of the voltage polarity (i.e., unipolar switching) was observed at low operating voltages (approximately 0.4 VRESET and 1.3 VSET), which is comparable to that observed in conventional devices fabricated by sputtering or metal organic chemical vapor deposition processes. The reported approach offers new opportunities for preparing inorganic material-based resistive switching memory devices with tailored electronic properties, allowing facile solution processing. PMID:19725555

  10. Fast, Capacious Disk Memory Device

    NASA Technical Reports Server (NTRS)

    Muller, Ronald M.

    1990-01-01

    Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

  11. Metal-oxide-semiconductor diodes containing C60 fullerenes for non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Beckmeier, Daniel; Baumgärtner, Hermann

    2013-01-01

    For non-volatile memories, silicon-oxide-nitride-oxide-silicon or floating gate structures are used to store information by charging and discharging electronic states reversibly. In this article, we propose to replace the floating gate by C60 molecules. This would allow more defined programming voltages because of the discrete molecular energy levels and a higher resistance to tunneling oxide defects because of the weak electrical connection between the single molecules. Such C60 MOS diode structures are produced and their electrical properties are analyzed regarding current transport and charging mechanism of the molecules. To create the MOS structures, C60 molecules (5% of a monolayer) are evaporated onto a part of a clean silicon wafer and covered by amorphous silicon in situ in an ultra high vacuum system. Then the wafer is oxidized in wet atmosphere at just 710 °C through the C60 layer. The goal is to produce a clean oxide above and under the molecules without destroying them. Aluminum gate contacts are defined on top of these layers to perform complementary capacitance voltage (CV) and current voltage (IV) measurements. First, the gate voltage is swept to analyze the injection current, then CV measurements are performed after each sweep to analyze the charge state of the C60 layer and the oxide quality. Reference diodes without C60 on the same wafer show an identical Fowler-Nordheim (FN) tunneling behavior for currents injected from silicon or from aluminum, respectively. In the CV curves, no pronounced flatband voltage shift is observable. In diodes with C60, for negative gate voltages, a classical FN tunneling is observed and compared to theory. The electron injection from silicon shows a different tunneling current behavior. It starts at a lower electric field and has a smaller slope then a FN current would have. It is identified as a trap-assisted tunneling (TAT) current caused by oxidation-induced traps under the C60 layer. It is modeled by an

  12. Bipolar tri-state resistive switching characteristics in Ti/CeOx/Pt memory device

    NASA Astrophysics Data System (ADS)

    Ismail, M.; W. Abbas, M.; M. Rana, A.; Talib, I.; E., Ahmed; Y. Nadeem, M.; L. Tsai, T.; U., Chand; A. Shah, N.; Hussain, M.; Aziz, A.; T. Bhatti, M.

    2014-12-01

    Highly repeatable multilevel bipolar resistive switching in Ti/CeOx/Pt nonvolatile memory device has been demonstrated. X-ray diffraction studies of CeO2 films reveal the formation of weak polycrystalline structure. The observed good memory performance, including stable cycling endurance and long data retention times (> 104 s) with an acceptable resistance ratio (~102), enables the device for its applications in future non-volatile resistive random access memories (RRAMs). Based on the unique distribution characteristics of oxygen vacancies in CeOx films, the possible mechanism of multilevel resistive switching in CeOx RRAM devices has been discussed. The conduction mechanism in low resistance state is found to be Ohmic due to conductive filamentary paths, while that in the high resistance state was identified as Ohmic for low applied voltages and a space-charge-limited conduction dominated by Schottky emission at high applied voltages.

  13. Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

    SciTech Connect

    Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

    2015-11-28

    Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10{sup 17 }m{sup −2}. We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching.

  14. High Performance Nonvolatile Transistor Memories Utilizing Functional Polyimide-Based Supramolecular Electrets.

    PubMed

    Tung, Wei-Yao; Li, Meng-Hsien; Wu, Hung-Chin; Liu, Hsin-Yu; Hsieh, Yun-Ting; Chen, Wen-Chang

    2016-05-20

    We report pentacene-based organic field-effect transistor memory devices utilizing supramolecular electrets, consisting of a polyimide, PI(6FOH-ODPA), containing hydroxyl groups for hydrogen bonding with amine functionalized aromatic rings (AM) of 1-aniline (AM1), 2-naphthylamine (AM2), 2-aminoanthracene (AM3), and 1-aminopyrene (AM4). The effect of the phenyl ring size and composition of AM1-AM4 on the hole-trapping capability of the fabricated devices was investigated systematically. Under an operating voltage under ±40 V, the prepared devices using the electrets of 100 % AM1-AM4/PI ratios exhibited a memory window of 0, 8.59, 25.97, and 29.95 V, respectively, suggesting that the hole-trapping capability increased with enhancing phenyl ring size. The memory window was enhanced as the amount of AM in PI increased. Furthermore, the devices showed a long charge-retention time of 10(4)  s with an ON/OFF current ratio of around 10(3) -10(4) and multiple switching stability over 100 cycles. This study demonstrated that the electrical characteristics of the OFET memory devices could be manipulated through the chemical compositions of the supramolecular electrets. PMID:27061212

  15. All organic memory devices utilizing fullerene molecules and insulating polymers

    NASA Astrophysics Data System (ADS)

    Kanwal, Alokik Paul

    memory operation is proposed based on the I-V fits. These devices exhibit the characteristics needed to satisfy the new demands for memory application and have the potential of becoming the first universal memory technology. They possess the high speed, non-volatility, thermal stability, and potentially high memory densities to make them ideal for use in laptops, iPhones, mp3 players, portable video players, GPS systems, and other mobile devices.

  16. Flexible and stackable non-volatile resistive memory for high integration

    NASA Astrophysics Data System (ADS)

    Ali, Shawkat; Bae, Jinho; Lee, Chong Hyun

    2015-08-01

    We propose a novel flexible and stackable resistive random access memory (ReRAM) array with multi-layered crossbar structures fabricated on a PET flexible substrate through EHD system. The basic memory block of the proposed device is based on one resistor and multi-layered column memristors (1R-MCM) structure, which can be easily extended to 3 dimensional columns for a high integration. To fabricate the device, the materials Ag for top and bottom electrodes, PVP for memristor, and (MEH:PPV and PMMA in acetonitrile) for pull-up resistors are used. Memory single cell is consisted of a high OFF/ON ratio (~4663) memristor and a pull-up resistor (20 MΩ) that operate on the principles of voltage divider circuit. Memory logic data is retrieve in the form of voltage levels instead of sensing current the of crossbar array. Two memory crossbar arrays are stacked vertically and they are sharing column bars, each column's memristors are with a single pull-up resistor. A 3x3 stacked memory with two layers that can store 18 bits of data is demonstrated to realize on a small area for a high integration.

  17. Development of a Tritium Cleanup System for a Large Helical Device Using Nonvolatile Getter Materials

    SciTech Connect

    Kawano, Takao; Sakuma, Yoichi; Kabutomori, Toshiki; Shibuya, Mamoru

    2000-01-15

    A tritium cleanup system has been conceptually developed for the large helical device (LHD) at the National Institute for Fusion Science. The system is a processing device employed to remove tritium from exhaust gas. In the exhaust gas discharged from the LHD in normal operation, the major part of tritium constituents should be in a form of hydrogen molecules because the fuel used in plasma experiments with the LHD is hydrogen molecules. From this viewpoint, we have designed a tritium cleanup system, which is characterized by tritium being removed and stored in a form of hydrogen molecules with less impurities, like oxygen and carbon, and its decomposition and the separation processes are introduced to convert various tritiated compounds into a form of hydrogen molecules of high purity. Besides these, there is another aspect in that getter materials are applied in both decomposition of tritiated compounds and storage of hydrogen molecules containing tritium.The system design is composed of three essential component parts: a hydrogen separator, a hydrogen absorbing vessel, and a decomposition process vessel. The hydrogen separator and the decomposition process vessel make a process loop repeat to remove hydrogen into a form of hydrogen molecules with less impurities. It is important that 'less impurities' means having a less bad influence on hydrogen-absorbing materials used in the storage vessel.We think that the hydrogen separator will be manufactured by employing a palladium hydrogen purifier system, which is available in the marketplace, and the hydrogen storage vessel will also be manufactured by using hydrogen-absorbing alloys like titanium. Thus, the serious problem imposed on us is how to realize the decomposition process vessel. To develop the decomposition process vessel, we thought nonvolatile getter materials were promising and carried out performance tests of methane decomposition by the nonvolatile getter materials, where methane was used because it is

  18. Control over variability in nonvolatile hafnium-oxide resistive-switching memory based on modeling of the switching processes

    NASA Astrophysics Data System (ADS)

    Butcher, Brian Jerad

    Resistive random access memory (ReRAM) technology presents an attractive option for embedded non-volatile (NV) memory systems if its variability (cycle-to-cycle and device-to-device) can be controlled. This dissertation has focused on investigations to identify key mechanisms and parameters which dominate ReRAM variability, and the development of subsequent experimental and simulation-based tools to address this variability. The first component of these efforts entailed identification of the modern-day non-volatile memory technological gaps that have driven the operational requirements and challenges for resistive memory as an emerging NV memory. Initial research confirmed the critical requirement of a sub-stoichiometric (HfO2-x) dielectric regarding the enablement of stable switching and suggested a defect-driven mechanism, which is discussed in detail. Preliminary experimental work was focused on the fabrication of a durable current-limiting (1T1R) testing structure; which was utilized to enable ReRAM device characterization, reduce unwanted parasitic capacitances, and overshoot-current. Initial electrical and physical characterization confirmed a filamentary based (defect-driven) mechanism based on ReRAM scalability-trends (in device sizes ranging from 50x50nm2 to 7x7microm2). Physical analysis (AFM, TEM and EELS) verified a `dominant-filament mechanism' in transmission-metal-oxide (specifically HfO2-x) based ReRAM. A novel characterization and analysis protocol for key electrical parameters affecting filament formation for HfO2-x-based ReRAMs was developed, focusing on the roles of current, voltage, and temperature. This protocol included characterization of the high-resistive-state (HRS) dependence on the maximum FORMING current (seen during 1st RESET Imax) and the characterization of low-power endurance. This characterization protocol was employed to investigate and develop an approach for ReRAM filament formation at elevated temperatures (hot FORMING) to

  19. Design of a Multi-Level/Analog Ferroelectric Memory Device

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2006-01-01

    Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  20. A triple quantum dot based nano-electromechanical memory device

    SciTech Connect

    Pozner, R.; Lifshitz, E.; Peskin, U.

    2015-09-14

    Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, “ON” and “OFF” states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Considering realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.

  1. A triple quantum dot based nano-electromechanical memory device

    NASA Astrophysics Data System (ADS)

    Pozner, R.; Lifshitz, E.; Peskin, U.

    2015-09-01

    Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, "ON" and "OFF" states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Considering realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.

  2. Ferroelectric memory

    NASA Astrophysics Data System (ADS)

    Vorotilov, K. A.; Sigov, A. S.

    2012-05-01

    The current status of developments in the field of ferroelectric memory devices has been considered. The rapidly growing market of non-volatile memory devices has been analyzed, and the current state of the art and prospects for the scaling of parameters of non-volatile memory devices of different types have been considered. The basic constructive and technological solutions in the field of the design of ferroelectric memory devices, as well as the "roadmaps" of the development of this technology, have been discussed.

  3. Oxygen plasma immersion ion implantation treatment to enhance data retention of tungsten nanocrystal nonvolatile memory

    SciTech Connect

    Wang, Jer-Chyi Chang, Wei-Cheng; Lai, Chao-Sung; Chang, Li-Chun; Ai, Chi-Fong; Tsai, Wen-Fa

    2014-03-15

    Data retention characteristics of tungsten nanocrystal (W-NC) memory devices using an oxygen plasma immersion ion implantation (PIII) treatment are investigated. With an increase of oxygen PIII bias voltage and treatment time, the capacitance–voltage hysteresis memory window is increased but the data retention characteristics become degraded. High-resolution transmission electron microscopy images show that this poor data retention is a result of plasma damage on the tunneling oxide layer, which can be prevented by lowering the bias voltage to 7 kV. In addition, by using the elevated temperature retention measurement technique, the effective charge trapping level of the WO{sub 3} film surrounding the W-NCs can be extracted. This measurement reveals that a higher oxygen PIII bias voltage and treatment time induces more shallow traps within the WO{sub 3} film, degrading the retention behavior of the W-NC memory.

  4. Resistive Switching Memory Devices Based on Proteins.

    PubMed

    Wang, Hong; Meng, Fanben; Zhu, Bowen; Leow, Wan Ru; Liu, Yaqing; Chen, Xiaodong

    2015-12-01

    Resistive switching memory constitutes a prospective candidate for next-generation data storage devices. Meanwhile, naturally occurring biomaterials are promising building blocks for a new generation of environmentally friendly, biocompatible, and biodegradable electronic devices. Recent progress in using proteins to construct resistive switching memory devices is highlighted. The protein materials selection, device engineering, and mechanism of such protein-based resistive switching memory are discussed in detail. Finally, the critical challenges associated with protein-based resistive switching memory devices are presented, as well as insights into the future development of resistive switching memory based on natural biomaterials. PMID:25753764

  5. Improved Retention Characteristic in Polycrystalline Silicon-Oxide-Hafnium Oxide-Oxide-Silicon-Type Nonvolatile Memory with Robust Tunnel Oxynitride

    NASA Astrophysics Data System (ADS)

    Hsieh, Chih Ren; Lai, Chiung Hui; Lin, Bo Chun; Zheng, Yuan Kai; Chung Lou, Jen; Lin, Gray

    2011-03-01

    In this paper, we present a simple novel process for forming a robust and reliable oxynitride dielectric with a high nitrogen content. It is highly suitable for n-channel metal-oxide-semiconductor field-effect transistor (nMOSFETs) and polycrystalline silicon-oxide-hafnium oxide-oxide-silicon (SOHOS)-type memory applications. The proposed approach is realized by using chemical oxide with ammonia (NH3) nitridation followed by reoxidation with oxygen (O2). The novel oxynitride process is not only compatible with the standard complementary metal-oxide-semiconductor (CMOS) process, but also can ensure the improvement of flash memory with low-cost manufacturing. The characteristics of nMOSFETs and SOHOS-type nonvolatile memories (NVMs) with a robust oxynitride as a gate oxide or tunnel oxide are studied to demonstrate their advantages such as the retardation of the stress-induced trap generation during constant-voltage stress (CVS), the program/erase behaviors, cycling endurance, and data retention. The results indicate that the proposed robust oxynitride is suitable for future nonvolatile flash memory technology application.

  6. Shape memory actuated release devices

    NASA Astrophysics Data System (ADS)

    Carpenter, Bernie F.; Clark, Cary R.; Weems, Weyman

    1996-05-01

    Spacecraft require a variety of separation and release devices to accomplish mission related functions. Current off-the-shelf devices such as pyrotechnics, gas-discharge systems, paraffin wax actuators, and other electro-mechanical devices may not be able to meet future design needs. The use of pyrotechnics on advanced lightweight spacecraft, for example, will expose fragile sensors and electronics to high shock levels and sensitive optics might be subject to contamination. Other areas of consideration include reliability, safety, and cost reduction. Shape memory alloys (SMA) are one class of actuator material that provides a solution to these design problems. SMA's utilize a thermally activated reversible phase transformation to recover their original heat treated shape (up to 8% strain) or to generate high recovery stresses (> 700 Mpa) when heated above a critical transition temperature. NiTiCu alloy actuators have been fabricated to provide synchronized, shockless separation within release mechanisms. In addition, a shape memory damper has been incorporated to absorb the elastic energy of the preload bolt and to electrically reset the device during ground testing. Direct resistive heating of the SMA actuators was accomplished using a programmable electric control system. Release times less than 40 msec have been determined using 90 watt-sec of power. Accelerometer data indicate less than 500 g's of shock were generated using a bolt preload of 1350 kgs.

  7. Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications.

    PubMed

    Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N; Hudait, Mantu K; Banerji, Pallab; Priya, Shashank

    2015-01-01

    We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~10(6) s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

  8. Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

    PubMed Central

    Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

    2015-01-01

    We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

  9. Colossal Electroresistive Properties Of CSD Grown Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3} Films For Nonvolatile Memory Applications

    SciTech Connect

    Bhavsar, K. H.; Joshi, U. S.

    2010-12-01

    Colossal electroresistance effects upon application of electric field in perovskite oxide Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3}(PCMO) thin films, which is a promising candidate for resistance random access memory (RRAM) device have been investigated. Nanocrystalline PCMO films were grown on SiO{sub 2} substrates by chemical solution deposition and crystallized at 700 deg. C under different gas atmospheres. Four terminal current voltage characteristics of Ag/PCMO/Ag planar geometry exhibited a sharp transition from a low resistance state (LRS) to a high resistance state (HRS) with a resistance switching ratio of as high as 1100% at room temperature. Nonvolatility and high retention was confirmed by electric pulse induced resistive switching measurements. The resistance switching ratios were found to depend on the annealing conditions, suggesting an interaction between the nonlattice oxygen and oxygen vacancies and/or the cationic vacancy.

  10. MOSFET nonvolatile memory with a high-density tungsten nanodot floating gate formed by self-assembled nanodot deposition

    NASA Astrophysics Data System (ADS)

    Pei, Y.; Yin, C.; Bea, J. C.; Kino, H.; Fukushima, T.; Tanaka, T.; Koyanagi, M.

    2009-04-01

    Metal-oxide-semiconductor field-effect transistor (MOSFET) nonvolatile memories with high-density tungsten nanodots (W-NDs) dispersed in silicon nitride as a floating gate were fabricated and characterized. The W-NDs with a high density of ~5 × 1012 cm-2 and small sizes of 2-3 nm were formed by self-assembled nanodot deposition (SAND). A large memory window of ~1.7 V was observed with bi-directional gate voltage sweeping between -10 and +10 V. Considering that there is no hysteresis memory window for the reference sample without W-NDs, this result indicates the charge trapping in W-NDs or related defects. Finally, the program/erase speed and retention characteristics were investigated and discussed in this paper.