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Sample records for oxide semiconductor field-effect

  1. GaN Metal Oxide Semiconductor Field Effect Transistors

    SciTech Connect

    Ren, F.; Pearton, S.J.; Abernathy, C.R.; Baca, A.; Cheng, P.; Shul, R.J.; Chu, S.N.G.; Hong, M.; Lothian, J.R.; Schurman, M.J.

    1999-03-02

    A GaN based depletion mode metal oxide semiconductor field effect transistor (MOSFET) was demonstrated using Ga{sub 2}O{sub 3}(Gd{sub 2}O{sub 3}) as the gate dielectric. The MOS gate reverse breakdown voltage was > 35V which was significantly improved from 17V of Pt Schottky gate on the same material. A maximum extrinsic transconductance of 15 mS/mm was obtained at V{sub ds} = 30 V and device performance was limited by the contact resistance. A unity current gain cut-off frequency, f{sub {tau}}, and maximum frequency of oscillation, f{sub max} of 3.1 and 10.3 GHz, respectively, were measured at V{sub ds} = 25 V and V{sub gs} = {minus}20 V.

  2. Metal-oxide-semiconductor field effect transistor humidity sensor using surface conductance

    NASA Astrophysics Data System (ADS)

    Song, Seok-Ho; Yang, Hyun-Ho; Han, Chang-Hoon; Ko, Seung-Deok; Lee, Seok-Hee; Yoon, Jun-Bo

    2012-03-01

    This letter presents a metal-oxide-semiconductor field effect transistor based humidity sensor which does not use any specific materials to sense the relative humidity. We simply make use of the low pressure chemical vapor deposited (LPCVD) silicon dioxide's surface conductance change. When the gate is biased and then floated, the electrical charge in the gate is dissipated through the LPCVD silicon dioxide's surface to the surrounding ground with a time constant depending on the surface conductance which, in turn, varies with humidity. With this method, extremely high sensitivity was achieved—the charge dissipation speed increased thousand times as the relative humidity increased.

  3. Effect of Temperature on GaGdO/GaN Metal Oxide Semiconductor Field Effect Transistors

    SciTech Connect

    Abernathy, C.R.; Baca, A.; Chu, S.N.G.; Hong, M.; Lothian, J.R.; Marcus, M.A.; Pearton, S.J.; Ren, F.; Schurman, M.J.

    1998-10-14

    GaGdO was deposited on GaN for use as a gate dielectric in order to fabricate a depletion metal oxide semiconductor field effect transistor (MOSFET). This is the fmt demonstration of such a device in the III-Nitride system. Analysis of the effect of temperature on the device shows that gate leakage is significantly reduced at elevated temperature relative to a conventional metal semiconductor field effeet transistor (MESFET) fabricated on the same GaN layer. MOSFET device operation in fact improved upon heating to 400 C. Modeling of the effeet of temperature on contact resistance suggests that the improvement is due to a reduction in the parasitic resistances present in the device.

  4. Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics

    PubMed Central

    Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

    2016-01-01

    We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm2/Vs, respectively, at room temperature. PMID:27545201

  5. Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

    PubMed

    Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

    2016-01-01

    We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature. PMID:27545201

  6. Optimal design of an electret microphone metal-oxide-semiconductor field-effect transistor preamplifier.

    PubMed

    van der Donk, A G; Bergveld, P

    1992-04-01

    A theoretical noise analysis of the combination of a capacitive microphone and a preamplifier containing a metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-value resistive bias element is given. It is found that the output signal-to-noise ratio for a source follower and for a common-source circuit is almost the same. It is also shown that the output noise can be reduced by making the microphone capacitance as well as the bias resistor as large as possible, and furthermore by keeping the parasitic gate capacitances as low as possible and finally by using an optimum value for the gate area of the MOSFET. The main noise source is the thermal noise of the gate leakage resistance of the MOSFET. It is also shown that short-channel MOSFETs produce more thermal channel noise than longer channel devices. PMID:1597614

  7. Drift-diffusion equation for ballistic transport in nanoscale metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Rhew, Jung-Hoon; Lundstrom, Mark S.

    2002-11-01

    We develop a drift-diffusion equation that describes ballistic transport in a nanoscale metal-oxide-semiconductor field effect transistor (MOSFET). We treat injection from different contacts separately, and describe each injection with a set of extended McKelvey one-flux equations [Phys. Rev. 123, 51 (1961); 125, 1570 (1962)] that include hierarchy closure approximations appropriate for high-field ballistic transport and degenerate carrier statistics. We then reexpress the extended one-flux equations in a drift-diffusion form with a properly defined Einstein relationship. The results obtained for a nanoscale MOSFET show excellent agreement with the solution of the ballistic Boltzmann transport equation with no fitting parameters. These results show that a macroscopic transport model based on the moments of the Boltzmann transport equation can describe ballistic transport.

  8. Modeling of quasi-ballistic transport in nanowire metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Lee, Yeonghun; Kakushima, Kuniyuki; Natori, Kenji; Iwai, Hiroshi

    2015-10-01

    We developed a semi-analytical quasi-ballistic transport model for the nanowire metal-oxide-semiconductor field-effect transistors, dealing with finite lengths of source, channel, and drain. For the modeling, we used a combination of one-flux scattering matrices and analytical solutions of Boltzmann transport equations. The developed model was in quantitatively good agreement with numerical results, and well represented intermediate-scaled devices. In addition, we illustrated that the finite source seriously affect the distribution function of the carriers injected from the source, and the finite drain does for the backscattering into the channel from the drain. Finally, our model and results would help to understand physical aspects regarding quasi-ballistic transport in nanoscale devices.

  9. Experimental characterization of a metal-oxide-semiconductor field-effect transistor-based Coulter counter.

    PubMed

    Sridhar, Manoj; Xu, Dongyan; Kang, Yuejun; Hmelo, Anthony B; Feldman, Leonard C; Li, Dongqing; Li, Deyu

    2008-05-15

    We report the detailed characterization of an ultrasensitive microfluidic device used to detect the translocation of small particles through a sensing microchannel. The device connects a fluidic circuit to the gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) and detects particles by monitoring the MOSFET drain current modulation instead of the modulation in the ionic current through the sensing channel. The minimum volume ratio of the particle to the sensing channel detected is 0.006%, which is about ten times smaller than the lowest detected volume ratio previously reported in the literature. This volume ratio is detected at a noise level of about 0.6% of the baseline MOSFET drain current, clearly showing the amplification effects from the fluidic circuits and the MOSFETs. We characterize the device sensitivity as a function of the MOSFET gate potential and show that its sensitivity is higher when the MOSFET is operating below its threshold gate voltage than when it is operating above the threshold voltage. In addition, we demonstrate that the device sensitivity linearly increases with the applied electrical bias across the fluidic circuit. Finally, we show that polystyrene beads and glass beads with similar sizes can be distinguished from each other based on their different translocation times, and the size distribution of microbeads can be obtained with accuracy comparable to that of direct scanning electron microscopy measurements. PMID:19479001

  10. Origin of microwave noise from an n-channel metal-oxide-semiconductor field effect transistor

    NASA Astrophysics Data System (ADS)

    Pantisano, Luigi; Cheung, K. P.

    2002-12-01

    The physics of noise is a complex subject. It is often difficult to clearly identify the physical origin of the observed noise. Electronic noise at microwave frequencies is technologically very important and has been extensively studied. While it is well known that many physical phenomena give rise to output current fluctuations (i.e., noise) in a metal-oxide-semiconductor field effect transistor (MOSFET), few physical phenomena have a time constant that can contribute in the microwave range. Current physical models of MOSFET microwave noise are all based on thermal agitation of electrons (thermal noise). However, what is the correct temperature (lattice or electron) to use in the noise calculation is an ongoing debate in the literature. All the modeling efforts have been using noise measured from pristine devices as a test for validity. In this work, we studied the n-MOSFET microwave noise as a function of electrical stress induced degradation. Our experiments thus introduced a new dimension in the noise behavior study. The results of our experiments cannot be explained by any of the current existing models. All existing models discounted flicker noise as being too small at microwave frequency. Our experimental results compel us to reexamine the validity of this common assumption. While we are not quite able to prove conclusively, our evidences are clearly leaning toward defect-induced fluctuation (flicker noise) as the origin of microwave noise in a n-MOSFET

  11. New Performance Indicators of Metal-Oxide-Semiconductor Field-Effect Transistors for High-Frequency Power-Conscious Design

    NASA Astrophysics Data System (ADS)

    Katayama, Kosuke; Fujishima, Minoru

    2012-02-01

    With the progress of complementary metal-oxide-semiconductor (CMOS) process technology, it is possible to apply CMOS devices to millimeter-wave amplifier design. However, the power consumption of the system becomes higher in proportion to its target frequency. Moreover, CMOS devices are biased at a point where the device achieves the highest gain and consumes much power. In order to reduce the power consumption without any compromise, we introduce two types of indicator. One works towards achieving the highest gain with the lowest power consumption. The other works towards achieving the highest linearity with consideration of the power consumption. In this work, we have shown the effectiveness of those indicators by applying measured data of the fabricated metal-oxide-semiconductor field-effect transistors (MOSFETs) to cascade common-source amplifiers.

  12. Growth and metal-oxide-semiconductor field-effect transistors of corundum-structured alpha indium oxide semiconductors

    NASA Astrophysics Data System (ADS)

    Kaneko, Kentaro; Ito, Yoshito; Uchida, Takayuki; Fujita, Shizuo

    2015-09-01

    The growth of corundum-structured α-In2O3, showing an X-ray diffraction (0006) rocking curve full-width at half maximum of 185 arcsec and electron Hall mobility of 130 cm2 V-1 s-1, was demonstrated on a sapphire substrate with an α-Ga2O3 buffer layer. An MOSFET of α-In2O3 exhibited pinch-off characteristics and an on-off ratio of drain current of 106. The use of mist chemical vapor deposition for the insulator-semiconductor structure was advantageous for low-cost devices.

  13. Metal-oxide-semiconductor field-effect-transistors on indium phosphide using HfO2 and silicon passivation layer with equivalent oxide thickness of 18 A˚

    NASA Astrophysics Data System (ADS)

    Chen, Yen-Ting; Zhao, Han; Yum, Jung Hwan; Wang, Yanzhen; Lee, Jack C.

    2009-05-01

    In this letter, we demonstrate the electrical properties of metal-oxide-semiconductor capacitors and metal-oxide-semiconductor field-effect transistors (MOSFETs) on InP using atomic layer deposited HfO2 gate dielectric and a thin silicon interface passivation layer (Si IPL). Compared with single HfO2, the use of Si IPL results in better interface quality with InP substrate, as illustrated by smaller frequency dispersion and reduced hysteresis. MOSFETs with Si IPL show much higher drive current and transconductance, improved subthreshold swing, interface-trap density and gate leakage current with equivalent oxide thickness scaling down to 18 Å.

  14. Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

    PubMed

    Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

    2014-10-20

    In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication. PMID:25607316

  15. Model for the field effect from layers of biological macromolecules on the gates of metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Landheer, D.; Aers, G.; McKinnon, W. R.; Deen, M. J.; Ranuarez, J. C.

    2005-08-01

    The potential diagram for field-effect transistors used to detect charged biological macromolecules in an electrolyte is presented for the case where an insulating cover layer is used over a conventional eletrolyte-insulator metal-oxide-semiconductor (EIMOS) structure to tether or bind the biological molecules to a floating gate. The layer of macromolecules is modeled using the Poisson-Boltzmann equation for an ion-permeable membrane. Expressions are derived for the charges and potentials in the EIMOS and electrolyte-insulator-semiconductor structures, including the membrane and electrolyte. Exact solutions for the potentials and charges are calculated using numerical algorithms. Simple expressions for the response are presented for low solution potentials when the Donnan potential is approached in the bulk of the membrane. The implications of the model for the small-signal equivalent circuit and the noise analysis of these structures are discussed.

  16. Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

    NASA Technical Reports Server (NTRS)

    Benumof, Reuben; Zoutendyk, John

    1987-01-01

    A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

  17. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    NASA Astrophysics Data System (ADS)

    Inaba, Masafumi; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-01

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al2O3. Using Al2O3 as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  18. Probing Electronic, Structural, and Charge Transfer Properties of Organic Semiconductor/Inorganic Oxide Interfaces Using Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Spalenka, Josef Wade

    Interfaces between organic semiconductors and inorganic oxides provide the functionality for devices including field-effect transistors (FETs) and organic photovoltaics. Organic FETs are sensitive to the physical structure and electronic properties of the few molecular layers of material at the interface between the semiconducting channel and the gate dielectric, and provide quantitative information such as the field-effect mobility of charge carriers and the concentration of trapped charge. In this thesis, FET interfaces between organic small-molecule semiconductors and SiO2, and donor/acceptor interfaces between organic small-molecules and the wide bandgap semiconductor ZnO are studied using electrical measurements of field-effect transistor devices. Monolayer-scale films of dihexyl sexithiophene are shown to have higher hole mobility than other monolayer organic semiconductors, and the origin of the high mobility is discussed. Studies of the crystal structure of the monolayer using X-ray structural probes and atomic force microscopy reveal the crystal structure is different in the monolayer regime compared to thicker films and bulk crystals. Progress and remaining challenges are discussed for in situ X-ray diffraction studies of the dynamic changes in the local crystal structure in organic monolayers due to charge carriers generated during the application of electric fields from the gate electrode in working FETs. Studies were conducted of light sensitive organic/inorganic interfaces that are modified with organic molecules grafted to the surface of ZnO nanoparticles and thin films. These interfaces are models for donor/acceptor interfaces in photovoltaics. The process of exciton dissociation at the donor/acceptor interface was sensitive to the insulating or semiconducting molecules grafted to the ZnO, and the photoinduced charge transfer process is measured by the threshold voltage shift of FETs during illumination. Charge transfer between light sensitive donor

  19. A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

    NASA Astrophysics Data System (ADS)

    Ren, Min; Li, Ze-Hong; Liu, Xiao-Long; Xie, Jia-Xiong; Deng, Guang-Min; Zhang, Bo

    2011-12-01

    A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its Ron,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated, and the optimized results with BV of 83 V and Ron,sp of 54 mΩ·mm2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior “Ron,sp/BV" trade-off to the conventional VDMOS (a 38% reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of Ron,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.

  20. SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting.

    PubMed

    Du, Wei; Inokawa, Hiroshi; Satoh, Hiroaki; Ono, Atsushi

    2011-08-01

    In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved. PMID:21808317

  1. Anomalous degradation of low-field mobility in short-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Natori, Kenji; Iwai, Hiroshi; Kakushima, Kuniyuki

    2015-12-01

    The anomalous degradation of the low-field mobility observed in short-channel metal-oxide-semiconductor field-effect transistors is analyzed by collating various reported data in experiments and simulations. It is inferred that the degradation is not caused by the channel scattering of the carriers. The origin is proposed to be the backscattering of channel carriers on injection into the drain. The expression of the low-field mobility, including the backscattering effect, is derived. The inverse of the low-field mobility is a linear function of the inverse of channel length, the expression of which reproduces that empirically derived by Bidal's group. By fitting the expression to simulated as well as experimental data, we can estimate the value of parameters related to the channel scattering and also to the backscattering from the drain. We find that these values are in reasonable magnitude.

  2. Extraction of Channel Length Independent Series Resistance for Deeply Scaled Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Ma, Li-Juan; Ji, Xiao-Li; Chen, Yuan-Cong; Xia, Hao-Guang; Zhu, Chen-Xin; Guo, Qiang; Yan, Feng

    2014-09-01

    The recently developed four Rsd extraction methods from a single device, involving the constant-mobility method, the direct Id—Vgs method, the conductance method and the Y-function method, are evaluated on 32 nm n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs). It is found that Rsd achieved from the constant-mobility method exhibits the channel length independent characteristics. The L-dependent Rsd extracted from the other three methods is proven to be associated with the gate-voltage-induced mobility degradation in the extraction procedures. Based on L-dependent behaviors of Rsd, a new method is proposed for accurate series resistance extraction on deeply scaled MOSFETs.

  3. Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Spathis, C. Birbas, A.; Georgakopoulou, K.

    2015-08-15

    Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

  4. GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

    NASA Astrophysics Data System (ADS)

    Zhao, Lian-Feng; Tan, Zhen; Wang, Jing; Xu, Jun

    2015-01-01

    GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the underlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given. Project supported by the National Basic Research Program of China (Grant No. 2011CBA00602) and the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2011ZX02708-002).

  5. A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu

    2014-11-07

    A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

  6. GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

    NASA Astrophysics Data System (ADS)

    Kodama, Masahito; Sugimoto, Masahiro; Hayashi, Eiko; Soejima, Narumasa; Ishiguro, Osamu; Kanechika, Masakazu; Itoh, Kenji; Ueda, Hiroyuki; Uesugi, Tsutomu; Kachi, Tetsu

    2008-02-01

    A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current-gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

  7. Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Shima, Akio; Sugii, Nobuyuki; Mise, Nobuyuki; Hisamoto, Digh; Takeda, Ken-ichi; Torii, Kazuyoshi

    2011-04-01

    This paper reports novel, non-epitaxial raised source/drain (S/D) approaches to decrease the parasitic external resistance in complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) fabricated on ultrathin silicon on insulator (UTSOI). This technique utilizes a metal Schottky S/D process with dopant segregation. Selectively formed NiSi2 with dopant segregation fabricated by laser-spike annealing (LSA) significantly lowered effective Shottky-barrier height and, thereby, lowered contact resistance (ρc). Satisfying the requirements of UTSOI MOSFETs in the 32-nm node for low stand-by power (LSTP) application, external parasitic resistance was reduced to 140 (NMOS) and 350 (PMOS) Ω µm. Our results show that ρc is an important component of parasitic resistance in terms of improving device performance of UTSOI MOSFETs.

  8. Experimental study on vertical scaling of InAs-on-insulator metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Yokoyama, Masafumi; Nakane, Ryosho; Takenaka, Mitsuru; Takagi, Shinichi; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko

    2014-06-30

    We have investigated effects of the vertical scaling on electrical properties in extremely thin-body InAs-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs). It is found that the body thickness (T{sub body}) scaling provides better short channel effect (SCE) control, whereas the T{sub body} scaling also causes the reduction of the mobility limited by channel thickness fluctuation (δT{sub body}) scattering (μ{sub fluctuation}). Also, in order to achieve better SCEs control, the thickness of InAs channel layer (T{sub channel}) scaling is more favorable than the thickness of MOS interface buffer layer (T{sub buffer}) scaling from a viewpoint of a balance between SCEs control and μ{sub fluctuation} reduction. These results indicate necessity of quantum well channel structure in InAs-OI MOSFETs and these should be considered in future transistor design.

  9. Evaluation of a dual bias dual metal oxide-silicon semiconductor field effect transistor detector as radiation dosimeter.

    PubMed

    Soubra, M; Cygler, J; Mackay, G

    1994-04-01

    A new type of direct reading semiconductor dosimeter has been investigated as a radiation detector for photon and electron therapy beams of various energies. The operation of this device is based on the measurement of the threshold voltage shift in a custom-built metal oxide-silicon semiconductor field effect transistor (MOSFET). This voltage is a linear function of absorbed dose. The extent of the linearity region is dependent on the voltage controlled operation during irradiation. Operating two MOSFETS at two different biases simultaneously during irradiation will result in sensitivity (V/Gy) reproducibility better than +/- 3% over a range in dose of 100 Gy and at a dose per fraction greater than 20 x 10(-2) Gy. The modes of operation give this device many advantages, such as continuous monitoring during irradiation, immediate reading, and permanent storage of total dose after irradiation. The availability and ease of use of these MOSFET detectors make them very promising in clinical dosimetry. PMID:8058024

  10. A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Hsieh, E. R.; Chung, Steve S.

    2016-05-01

    A gate current variation measurement method is proposed to examine the surface roughness of metal oxide semiconductor field effect transistors (MOSFETs). This gate current variation is demonstrated on the trigate structure MOSFETs. It was found that the standard deviation of oxide-thickness is proportional to the inverse of square-root of device areas, and its slope is defined as the effective surface roughness variation. In particular, for the transistors with varying fin height, this surface roughness effect aggravates with the increasing fin height. More importantly, the gate leakage at off-state, i.e., Vg = 0 V, is strongly dependent on the gate dielectric surface roughness and dominates the drain current variations. This gate leakage may serve as a quality measure of a low power and energy efficient integrated circuit, especially for the transistor with 3-dimensional gate structure. The present results provide us better understandings on an additional source of Vth fluctuations, i.e., the surface roughness variation, in addition to the random dopant fluctuation, that we are usually not noticed. In particular, this study also provides us a simple easy-to-use method for the monitoring of oxide quality in the volume production of trigate MOSFETs.

  11. Single Event Effects (SEE) for Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)

    NASA Technical Reports Server (NTRS)

    Lauenstein, Jean-Marie

    2011-01-01

    Single-event gate rupture (SEGR) continues to be a key failure mode in power MOSFETs. (1) SEGR is complex, making rate prediction difficult SEGR mechanism has two main components: (1) Oxide damage-- Reduces field required for rupture (2) Epilayer response -- Creates transient high field across the oxide.

  12. Quantum Mechanical Effects on the Threshold Voltage of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Liu, Ran; Qiu, Zhi-Jun; Wang, Ling-Li; Tang, Ting-Ao

    2010-03-01

    A model for a metal-oxide-semiconductor field-effect transistor (MOSFET) with a double gate (DG) is developed. Quantum mechanical effects on the threshold voltage (VTH) are modeled and investigated analytically. The analytic model shows how VTH is increased with quantum mechanical effect. The model is applicable to both symmetric DG (SDG) and asymmetric DG (ADG) nMOSFETs, and is also applicable to both doped and undoped DG nMOSFETs. The analytic results are verified by comparing with the results obtained from simulations using Schred, and good agreement is observed. The VTH of an ADG nMOSFET will shift more than that of an SDG nMOSFET, and the VTH of a DG transistor with (110)-silicon (Si) orientation will shift more than that of a DG transistor with (100)-Si orientation. When the silicon thickness tsi < 3 nm, the VTH shift will be significant, and one should be careful in the use of an extremely thin silicon body. When the body doping density (NA) is not high (<1018 cm-3), the VTH shift is almost the same for different NA. When NA > 1018 cm-3, the higher the NA, the more the VTH shift.

  13. Channel Strain in Advanced Complementary Metal-Oxide-Semiconductor Field Effect Transistors Measured Using Nano-Beam Electron Diffraction

    NASA Astrophysics Data System (ADS)

    Toda, Akio; Nakamura, Hidetatsu; Fukai, Toshinori; Ikarashi, Nobuyuki

    2008-04-01

    Using high-precision nano-beam electron diffraction (NBD), we clarified the influences of stress liner and the stress of shallow trench isolation on channel strain in advanced metal-oxide-semiconductor field effect transistors (MOSFETs). For systematic strain measurements, we improved the precision of NBD by observing large reciprocal lattice vectors under appropriate diffraction conditions. The absolute value of the channel strain increases by stress liner as gate length decreases, although the drive current increase due to stress liner saturates at a shorter channel length. The normal strain in the gate length direction is inversely proportional to the distance from the gate electrode to the shallow trench isolation (STI). Furthermore, the relationship between measured channel strain induced by STI and drive current change was shown. The drive current of n- and p-MOSFET changes about 5% with 2×10-3 channel strain variation. This result suggests that reducing the shallow trench isolation stress is effective for controlling the drive current change, depending on the active region layout. We conclude that the experimental measurement of channel strain is necessary for device and circuit design.

  14. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors. PMID:27077327

  15. Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

    NASA Astrophysics Data System (ADS)

    Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

    2015-10-01

    Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

  16. Possible unified model for the Hooge parameter in inversion-layer-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Omura, Yasuhisa

    2013-06-01

    This paper proposes a possible unified model for the Hooge parameter by considering the impact of transport dimensionality on the Hooge parameter behavior of various inversion-layer-channel metal-oxide-semiconductor field-effect transistors. Past experiments show that the Hooge parameter has a couple of peculiar behaviors. Based on a phenomenological consideration, the original mobility-based model for the Hooge parameter is shown to provide only a partial understanding of the results. It is also observed that, in contrast to past models, the interpretation of some aspects of the Hooge parameter strongly depends on how the two fluctuation modes, the carrier-density fluctuation and the mobility fluctuation, correlate. The phenomenological model proposed here gives a fundamental physical basis that allows important aspects of the Hooge parameter to be interpreted; the model also introduces three basic parameters (the Hooge parameter elements for the carrier-density fluctuation, the mobility fluctuation, and the cross-correlation component). Theoretical expressions for the three basic Hooge parameters are given by merging the fundamental Hooge model, Handel's theory, statistical physics, and quantum-mechanical transport physics. The gate voltage dependence of the Hooge parameter can be explained reasonably well by stating that the screening length rules the dielectric function and that the mobility fluctuation and carrier density fluctuation are correlated. Finally, the theoretical models are examined against the results of past experiments.

  17. Analytic Circuit Model of Ballistic Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor for Transient Analysis

    NASA Astrophysics Data System (ADS)

    Numata, Tatsuhiro; Uno, Shigeyasu; Kamakura, Yoshinari; Mori, Nobuya; Nakazato, Kazuo

    2013-04-01

    A fully analytic and explicit model of device properties in the ballistic transport in gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed, which enables circuit simulations. The electrostatic potential distribution in the wire cross section is approximated by a parabolic function. Using the applied potential, the energy levels of electrons are analytically obtained in terms of a single unknown parameter by perturbation theory. Ballistic current is obtained in terms of an unknown parameter using the analytic expression of the electron energy level and the current equation for ballistic transport. We analytically derive the parameter with a one-of-a-kind approximate methodology. With the obtained parameter, the fully analytic and explicit model of device properties such as energy levels, ballistic current, and effective capacitance is derived with satisfactory accuracy compared with the numerical simulation results. Finally, we perform a transient simulation using a circuit simulator, introducing our model to it as a Verilog-A script.

  18. A silicon metal-oxide-semiconductor field-effect transistor Hall bar for scanning Hall probe microscopy.

    PubMed

    Yamaguchi, Akinobu; Saito, Hiromasa; Shimizu, Masayoshi; Miyajima, Hideki; Matsumoto, Satoru; Nakamura, Yoshiharu; Hirohata, Atsufumi

    2008-08-01

    We demonstrate successful operation of a scanning Hall probe microscope with a few micron-size resolution by using a silicon metal-oxide semiconductor field-effect transistor (Si-MOSFET) Hall bar, which is designed to improve not only the mechanical strength but also the temperature stability. The Si-MOSFET micro-Hall probe is cheaper than the current micro-Hall probes and is found to be as sensitive as a micro-Hall probe with GaAs/AlGaAs heterostructure or an epitaxial InSb two-dimensional electron gas. This was used to magnetically image the surface of a Sm(2)Co(17) permanent magnet during the magnetization reversal process as a function of an external magnetic field below 1.5 T. This revealed firm evidence of the presence of the inverse magnetic seed as theoretically predicted earlier. Magnetically pinned centers, with a typical size 80 mum, are observed to persist even under a high magnetic field, clearly indicating the robustness of the Si Hall probe against the field application as well as the repetition of the measurement. PMID:19044353

  19. Characteristics of drain-modulated generation current in n-type metal-oxide-semiconductor field-effect transistor

    NASA Astrophysics Data System (ADS)

    Chen, Hai-Feng; Guo, Li-Xin; Zheng, Pu-Yang; Dong, Zhao; Zhang, Qian

    2015-07-01

    Drain-modulated generation current IDMG induced by interface traps in an n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) is investigated. The formation of IDMG ascribes to the change of the Si surface potential φ s. This change makes the channel suffer transformation from the inversion state, depletion I state to depletion II state. The simulation result agrees with the experiment in the inversion and depletion I states. In the depletion II state, the theoretical curve goes into saturation, while the experimental curve drops quickly as VD increases. The reason for this unconformity is that the drain-to-gate voltage VDG lessens φ s around the drain corner and controls the falling edge of the IDMG curve. The experiments of gate-modulated generation and recombination currents are also applied to verify the reasonability of the mechanism. Based on this mechanism, a theoretical model of the IDMG falling edge is set up in which IDMG has an exponential attenuation relation with VDG. Finally, the critical fitting coefficient t of the experimental curves is extracted. It is found that t = 80 mV = 3kT/q. This result fully shows the accuracy of the above mechanism. Project supported by the National Natural Science Foundation of China (Grant No. 61306131) and the Research Project of Education Department of Shaanxi Province, China (Grant No. 2013JK1095).

  20. Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Si, Mengwei; Gu, Jiangjiang J.; Wang, Xinwei; Shao, Jiayi; Li, Xuefei; Manfra, Michael J.; Gordon, Roy G.; Ye, Peide D.

    2013-03-01

    InGaAs gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) with 6 nm nanowire thickness have been experimentally demonstrated at sub-80 nm channel length. The effects of forming gas anneal (FGA) on the performance of these devices have been systematically studied. The 30 min 400 °C FGA (4% H2/96% N2) is found to improve the quality of the Al2O3/InGaAs interface, resulting in a subthreshold slope reduction over 20 mV/dec (from 117 mV/dec in average to 93 mV/dec). Moreover, the improvement of interface quality also has positive impact on the on-state device performance. A scaling metrics study has been carried out for FGA treated devices with channel lengths down to 20 nm, indicating excellent gate electrostatic control. With the FGA passivation and the ultra-thin nanowire structure, InGaAs MOSFETs are promising for future logic applications.

  1. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Lee, Minjoo L.; Fitzgerald, Eugene A.; Bulsara, Mayank T.; Currie, Matthew T.; Lochtefeld, Anthony

    2005-01-01

    This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980's and 1990's to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1-xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the literature on short-channel device performance and process integration of strained Si. The review concludes with a global summary of the mobility enhancements available in the SiGe materials system and a discussion of implications for future technology generations.

  2. Ballistic graphene nanoribbon metal-oxide-semiconductor field-effect transistors: A full real-space quantum transport simulation

    NASA Astrophysics Data System (ADS)

    Liang, Gengchiau; Neophytou, Neophytos; Lundstrom, Mark S.; Nikonov, Dmitri E.

    2007-09-01

    A real-space quantum transport simulator for graphene nanoribbon (GNR) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been developed and used to examine the ballistic performance of GNR MOSFETs. This study focuses on the impact of quantum effects on these devices and on the effect of different type of contacts. We found that two-dimensional (2D) semi-infinite graphene contacts produce metal-induced-gap states (MIGS) in the GNR channel. These states enhance quantum tunneling, particularly in short channel devices, they cause Fermi level pinning and degrade the device performance in both the ON-state and OFF-state. Devices with infinitely long contacts having the same width as the channel do not indicate MIGS. Even without MIGS quantum tunneling effects such as band-to-band tunneling still play an important role in the device characteristics and dominate the OFF-state current. This is accurately captured in our nonequilibrium Greens' function quantum simulations. We show that both narrow (1.4 nm width) and wider (1.8 nm width) GNRs with 12.5 nm channel length have the potential to outperform ultrascaled Si devices in terms of drive current capabilities and electrostatic control. Although their subthreshold swings under forward bias are better than in Si transistors, tunneling currents are important and prevent the achievement of the theoretical limit of 60 mV/dec.

  3. Effects of Hot Carriers on DC and RF Performances of Deep Submicron p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Various Oxide Layer Thicknesses

    NASA Astrophysics Data System (ADS)

    Tang, Mao-Chyuan; Fang, Yean-Kuen; Liao, Wen-Shiang; Chen, David C.; Yeh, Chune-Sin; Chien, Shan-Chieh

    2008-04-01

    In this work, the effects of hot carriers on the DC and RF performances of 45 nm p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) with various oxide layer thicknesses were investigated in detail by RF automatic measurements. It was found that a PMOSFET with a thinner oxide layer suffers more serious damage from hot carriers than that with a thicker oxide layer. Also, the greatest degradation occurs at the bias condition when gate stress voltage Vgstr is equal to drain stress voltage Vdstr, and it was found that the degradation of the cutoff frequency fT is dependent on transconductance gm only. This is different from conventional long-channel devices, in which the greatest degradation takes place at Vgstr = Vdstr/2 and when fT is dependent on both gm and the total gate capacitance Cgg (=Cgs+Cgd).

  4. Trap Profiling Based on Frequency Varied Charge Pumping Method for Hot Carrier Stressed Thin Gate Oxide Metal Oxide Semiconductors Field Effect Transistors.

    PubMed

    Choi, Pyungho; Kim, Hyunjin; Kim, Sangsub; Kim, Soonkon; Javadi, Reza; Park, Hyoungsun; Choi, Byoungdeog

    2016-05-01

    In this study, pulse frequency and reverse bias voltage is modified in charge pumping and advanced technique is presented to extract oxide trap profile in hot carrier stressed thin gate oxide metal oxide semiconductor field effect transistors (MOSFETs). Carrier trapping-detrapping in a gate oxide was analyzed after hot carrier stress and the relationship between trapping depth and frequency was investigated. Hot carrier induced interface traps appears in whole channel area but induced border traps mainly appears in above pinch-off region near drain and gradually decreases toward center of the channel. Thus, hot carrier stress causes interface trap generation in whole channel area while most border trap generation occurs in the drain region under the gate. Ultimately, modified charge pumping method was performed to get trap density distribution of hot carrier stressed MOSFET devices, and the trapping-detrapping mechanism is also analyzed. PMID:27483833

  5. A Unified Functional Reliability Model for N-channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide

    NASA Astrophysics Data System (ADS)

    Lee, Hai-Ming; Du, Long-Jye; Liang, Mong-Song; King, Ya-Ching; Hsu, Charles Ching-Hsiang

    2002-09-01

    Reliability tests of N-channel metal-oxide-semiconductor field-effect transistors (NMOSFET’s) with oxide thickness ranging from 3.3 nm to 1.7 nm are performed and analyzed in this work. New device failure mechanism due to gate-to-drain leakage path formation is observed, and it severely degrades the off-state performance of devices with sub 2 nm gate oxides. Among the device parameters monitored, on-state conduction current and off-state drain leakage are the two most decisive parameters which dominate NMOSFET’s functional reliability. A new unified functional reliability model is proposed, and lifetime predictions due to respective device parameters can be achieved.

  6. Verification of the plan dosimetry for high dose rate brachytherapy using metal-oxide-semiconductor field effect transistor detectors

    SciTech Connect

    Qi Zhenyu; Deng Xiaowu; Huang Shaomin; Lu Jie; Lerch, Michael; Cutajar, Dean; Rosenfeld, Anatoly

    2007-06-15

    The feasibility of a recently designed metal-oxide-semiconductor field effect transistor (MOSFET) dosimetry system for dose verification of high dose rate (HDR) brachytherapy treatment planning was investigated. MOSFET detectors were calibrated with a 0.6 cm{sup 3} NE-2571 Farmer-type ionization chamber in water. Key characteristics of the MOSFET detectors, such as the energy dependence, that will affect phantom measurements with HDR {sup 192}Ir sources were measured. The MOSFET detector was then applied to verify the dosimetric accuracy of HDR brachytherapy treatments in a custom-made water phantom. Three MOSFET detectors were calibrated independently, with the calibration factors ranging from 0.187 to 0.215 cGy/mV. A distance dependent energy response was observed, significant within 2 cm from the source. The new MOSFET detector has a good reproducibility (<3%), small angular effect (<2%), and good dose linearity (R{sup 2}=1). It was observed that the MOSFET detectors had a linear response to dose until the threshold voltage reached approximately 24 V for {sup 192}Ir source measurements. Further comparison of phantom measurements using MOSFET detectors with dose calculations by a commercial treatment planning system for computed tomography-based brachytherapy treatment plans showed that the mean relative deviation was 2.2{+-}0.2% for dose points 1 cm away from the source and 2.0{+-}0.1% for dose points located 2 cm away. The percentage deviations between the measured doses and the planned doses were below 5% for all the measurements. The MOSFET detector, with its advantages of small physical size and ease of use, is a reliable tool for quality assurance of HDR brachytherapy. The phantom verification method described here is universal and can be applied to other HDR brachytherapy treatments.

  7. Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Amakawa, Shuhei; Toda, Asato; Ohyama, Katsuroh; Higashiguchi, Naoya; Hori, Daisuke; Shintaku, Yasuhiro; Miyake, Masataka; Miura-Mattausch, Mitiko

    2011-04-01

    This paper presents an experimentally found device-size-independent universal relationship between the settling time of floating-body silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) and the substrate current in body-tied devices. Such a relationship could enable one to characterize dynamic properties of SOI MOSFETs through DC measurements and would be useful for physical compact modeling of history effects.

  8. An electrically detected magnetic resonance study of performance limiting defects in SiC metal oxide semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Cochrane, C. J.; Lenahan, P. M.; Lelis, A. J.

    2011-01-01

    In this study, we utilize electrically detected magnetic resonance (EDMR) techniques and electrical measurements to study defects in SiC based metal oxide semiconductor field effect transistors (MOSFETs). We compare results on a series of SiC MOSFETs prepared with significantly different processing parameters. The EDMR is detected through spin dependent recombination (SDR) in most cases. However, in some devices at a fairly high negative bias, the EDMR likely also involves spin dependent trap-assisted tunneling (SDT) between defects on both sides of the SiC/SiO2 interface. At least three different defects have been detected in the magnetic resonance measurements. The defects observed include two at the SiC/SiO2 interface or on the SiC side of the SiC/SiO2 interface: one is very likely a vacancy center with a distribution which extends into the bulk of the SiC and the other is likely a "dangling bond" defect. A third defect, located on the SiO2 side of the SiC/SiO2 interface, has a spectrum very similar to that previously reported for an oxygen deficient silicon coupled to a hydrogen atom. In nearly all cases, we observe a strong dominating single line EDMR spectrum with an isotropic g≈2.0027. In some samples, this strong central line is accompanied by two pairs of considerably weaker side peaks which we link to hyperfine interactions with nearby Si and C atoms. The pattern is physically reasonable for a silicon vacancy in SiC. We therefore tentatively assign it to a silicon vacancy or silicon vacancy associated defect in the SiC. In one set of devices with very high interface trap density we observe another dominating spectrum with g∥=2.0026 and g⊥=2.0010 with the symmetry axis coincident with the [0001] and nearly the SiC/SiO2 interface normal. We ascribe this EDMR spectrum to a "dangling bond" defect. A third EDMR spectrum shows up in some devices at a fairly large negative gate bias. The phase of this spectrum is quite consistently opposite to that of the

  9. Experimental Study on Improving Unclamped Inductive Switching Characteristics of the New Power Metal Oxide Semiconductor Field Effect Transistor Employing Deep Body Contact

    NASA Astrophysics Data System (ADS)

    Ji, In‑Hwan; Choi, Young‑Hwan; Kim, Soo‑Seong; Choi, Yearn‑Ik; Han, Min‑Koo

    2006-04-01

    A new power metal oxide semiconductor field effect transistor (MOSFET) with deep body contact (DBC), which improves the avalanche energy capability, is proposed and verified by experimental results. For the experiment, a 60 V, 1 A power MOSFET employing DBC has been fabricated using a complementary metal oxide semiconductor (CMOS) compatible deep Si trench process. Previous simulations show that DBC alters the direction of the current flow from the edge to the bottom of the p-body under unclamped inductive switching (UIS) conditions. DBC also suppresses the activation of the parasitic bipolar transistor due to the reduction of the current density beneath the n+ source. Experimental results show that the ruggedness of the proposed power MOSFET is improved without sacrificing any other electrical characteristics and increasing device area.

  10. Impact of Reducing Shallow Trench Isolation Mechanical Stress on Active Length for 40 nm n-Type Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Huang, Yao-Tsung; Wu, San-Lein; Lin, Hau-Yu; Kuo, Cheng-Wen; Chang, Shoou-Jinn; Hong, De-Gong; Wu, Chung-Yi; Huang, Cheng-Tung; Cheng, Osbert

    2011-04-01

    We report an improved densification annealing process for sub atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) performance for 40 nm node and beyond. Experimental results show that this improved STI densification process leads to lower compressive stress in the small active area compared with the standard STI process. This is beneficial to electron mobility and leads to an enhancement of on-current (ION). Moreover, comparable drain induced barrier lowering (DIBL) and subthreshold swing (SS) characteristics for both devices indicate that the improved densification process would no significant influences on process variations or dopant diffusions. Hence, the improved STI process can be adopted in 40 nm complementary metal-oxide-semiconductor (CMOS) technology and beyond.

  11. Comparison between chemical vapor deposited and physical vapor deposited WSi2 metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-01

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi2 metal gate process for In0.53Ga0.47As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al2O3 as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al2O3 shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  12. Stress Characterization of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) using Raman Spectroscopy and the Finite Element Method.

    PubMed

    Yoshikawa, Masanobu; Kosaka, Kenichi; Seki, Hirohumi; Kimoto, Tsunenobu

    2016-07-01

    We measured the depolarized and polarized Raman spectra of a 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and found that compressive stress of approximately 20 MPa occurs under the source and gate electrodes and tensile stress of approximately 10 MPa occurs between the source and gate electrodes. The experimental result was in close agreement with the result obtained by calculation using the finite element method (FEM). A combination of Raman spectroscopy and FEM provides much data on the stresses in 4H-SiC MOSFET. PMID:27165155

  13. Ballistic performance comparison of monolayer transition metal dichalcogenide MX2 (M = Mo, W; X = S, Se, Te) metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Chang, Jiwon; Register, Leonard F.; Banerjee, Sanjay K.

    2014-02-01

    We study the transport properties of monolayer MX2 (M = Mo, W; X = S, Se, Te) n- and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Green's function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX2 MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics of nanoscale monolayer MX2 MOSFETs.

  14. Detailed investigation of InSb p-channel metal-oxide-semiconductor field effect transistor prepared by photo-enhanced chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Liu, Biing-Der; Lee, Si-Chen; Sun, Tai-Ping; Yang, Sheng-Jenn

    1995-05-01

    The InSb metal-oxide-semiconductor field effect transistor (MOSFET) with three different channel lengths 5, 15, and 30 micron were fabricated successfully. The SiO2 prepared by photo-enhanced chemical vapor deposition was used both as the gate insulator and the source/drain passivation layer to reduce the source/drain pn junction surface leakage current. The common-source current-voltage characteristics show a breakdown voltage exceeding 2 V indicating an excellent pn junction reverse characteristics. The capacitance-voltage and the transferred current versus gate voltage characteristics are discussed in detail to explain the geometry effect on the device performance.

  15. Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

    NASA Astrophysics Data System (ADS)

    Lim, Ji-Song; Yang, Xiaodong; Nishida, Toshikazu; Thompson, Scott E.

    2006-08-01

    An experimental method to determine both the hydrostatic and shear deformation potential constants is introduced. The technique is based on the change in the gate tunneling currents of Si-metal oxide semiconductor field effect transistors (MOSFETs) under externally applied mechanical stress and has been applied to industrial n-type MOSFETs. The conduction band hydrostatic and shear deformation potential constants (Ξd and Ξu) are extracted to be 1.0±0.1 and 9.6±1.0eV, respectively, which is consistent with recent theoretical works.

  16. Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

    SciTech Connect

    Kanaki, Toshiki Asahara, Hirokatsu; Ohya, Shinobu Tanaka, Masaaki

    2015-12-14

    We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I{sub DS} by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I{sub DS} by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

  17. GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

    NASA Astrophysics Data System (ADS)

    Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

    2015-04-01

    GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

  18. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    NASA Astrophysics Data System (ADS)

    Liu, Hsi-Wen; Chang, Ting-Chang; Tsai, Jyun-Yu; Chen, Ching-En; Liu, Kuan-Ju; Lu, Ying-Hsin; Lin, Chien-Yu; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-04-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  19. Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

    SciTech Connect

    Held, Martin; Schießl, Stefan P.; Gannott, Florentina; Miehler, Dominik; Zaumseil, Jana

    2015-08-24

    Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

  20. Vox/Eox-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress

    NASA Astrophysics Data System (ADS)

    Tsujikawa, Shimpei; Shiga, Katsuya; Umeda, Hiroshi; Yugami, Jiro

    2007-01-01

    The breakdown mechanism of ultrathin SiON gate dielectrics in p-type metal oxide semiconductor field effect transistors having p+gates (p+gate-pMOSFETs) has been studied. Systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFET in inversion mode, gate dielectric breakdown under stress voltage lower than -4 V is driven by oxide voltage (Vox) or oxide field (Eox), while the breakdown under stress voltage higher than -4 V is driven by gate voltage (Vg). The Vox/Eox-driven breakdown observed under low stress voltage is quite important to the reliability of low-voltage complementary metal oxide semiconductor (CMOS). By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to same mechanism as the negative bias temperature instability (NBTI), namely the interfacial hydrogen release driven by Eox, has been shown to be possible. However, direct tunneling of holes driven by Vox has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be Vox or Eox.

  1. A high performance In0.53Ga0.47As metal-oxide-semiconductor field effect transistor with silicon interface passivation layer

    NASA Astrophysics Data System (ADS)

    Zhu, Feng; Zhao, Han; Ok, I.; Kim, H. S.; Yum, J.; Lee, Jack C.; Goel, Niti; Tsai, W.; Gaspe, C. K.; Santos, M. B.

    2009-01-01

    In this letter, we demonstrate a high performance In0.53Ga0.47As channel n-type metal-oxide-semiconductor field effect transistor with silicon interface passivation layer (IPL) and HfO2 gate oxide. Owing to the effectiveness of Si IPL on improving the interface quality, good device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm and Vd=50 mV), drive current of 158 mA/mm (Lg=5 μm, Vgs=Vth+2 V, and Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V s. As an important factor on device design, the impact of silicon IPL thickness on the transistor characteristics has been investigated.

  2. INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

    2010-10-01

    As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

  3. The empirical dependence of radiation-induced charge neutralization on negative bias in dosimeters based on the metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Benson, Chris; Albadri, Abdulrahman; Joyce, Malcolm J.; Price, Robert A.

    2006-08-15

    The dependence of radiation-induced charge neutralization (RICN) has been studied in metal-oxide-semiconductor field-effect transistor (MOSFET) dosimeters. These devices were first exposed to x rays under positive bias and then to further dose increments at a selection of reverse bias levels. A nonlinear empirical trend has been established that is consistent with that identified in the data obtained in this work. Estimates for the reverse bias level corresponding to the maximum rate of RICN have been extracted from the data. These optimum bias levels appear to be independent of the level of initial absorbed dose under positive bias. The established models for threshold voltage change have been considered and indicate a related nonlinear trend for neutralization cross section {sigma}{sub N} as a function of oxide field. These data are discussed in the context of dose measurement with MOSFETs and within the framework of statistical mechanics associated with neutral traps and their field dependence.

  4. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    NASA Astrophysics Data System (ADS)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  5. HfO2-based InP n-channel metal-oxide-semiconductor field-effect transistors and metal-oxide-semiconductor capacitors using a germanium interfacial passivation layer

    NASA Astrophysics Data System (ADS)

    Kim, Hyoung-Sub; Ok, I.; Zhang, M.; Zhu, F.; Park, S.; Yum, J.; Zhao, H.; Lee, Jack C.; Majhi, Prashant

    2008-09-01

    In this letter, we present our experimental results of HfO2-based n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and metal-oxide-semiconductor capacitors (MOSCAPs) on indium phosphide (InP) substrates using a thin germanium (Ge) interfacial passivation layer (IPL). We found that MOSCAPs on n-InP substrates showed good C-V characteristics such as a small capacitance equivalent thickness (14Å ), a small frequency dispersion (<10% and <200mV), and a low dielectric leakage current (˜5×10-4A/cm2 at Vg=1.5V), whereas MOSCAPs on p-InP exhibited poor characteristics, implying severe Fermi level pinning. It was also found that InP was more vulnerable to a high temperature process such that C-V curves showed a characteristic "bump" and inversion capacitance at relatively high frequencies. From n-channel MOSFETs on a semi-insulating InP substrate using Ge IPL, HfO2, and TaN gate electrodes, excellent electrical characteristics such as a large transconductance (9.3mS /mm) and large drain currents (12.3mA/mm at Vd=2V and Vg=Vth+2V) were achieved, which are comparable to other works.

  6. Fabrication and characterization of the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Qing-Wen, Song; Xiao-Yan, Tang; Yan-Jing, He; Guan-Nan, Tang; Yue-Hu, Wang; Yi-Meng, Zhang; Hui, Guo; Ren-Xu, Jia; Hong-Liang, Lv; Yi-Men, Zhang; Yu-Ming, Zhang

    2016-03-01

    In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFFETs) have been fabricated and characterized. A sandwich- (nitridation-oxidation-nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF I-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 × 1011 eV-1·cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field-effect mobility is about 32.5 cm2·V-1·s-1, and the maximum peak field-effect mobility of 38 cm2·V-1·s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs. Projcet supported by the National Natural Science Foundation of China (Grant Nos. 61404098, 61176070, and 61274079), the Doctoral Fund of Ministry of Education of China (Grant Nos. 20110203110010 and 20130203120017), the National Key Basic Research Program of China (Grant No. 2015CB759600), and the Key Specific Projects of Ministry of Education of China (Grant No. 625010101).

  7. Analysis of Channel Stress Induced by NiPt-Silicide in Metal-Oxide-Semiconductor Field-Effect Transistor and Its Generation Mechanism

    NASA Astrophysics Data System (ADS)

    Mizuo, Mariko; Yamaguchi, Tadashi; Kudo, Shuichi; Hirose, Yukinori; Kimura, Hiroshi; Tsuchimoto, Jun-ichi; Hattori, Nobuyoshi

    2013-09-01

    Channel stress induced by NiPt-silicide films in metal-oxide-semiconductor field-effect transistors (MOSFETs) was demonstrated using UV-Raman spectroscopy, and its generation mechanism was revealed. It was possible to accurately measure the channel stress with the Raman test structure. The channel stress depends on the source/drain doping type and the second silicide annealing method. In order to discuss the channel stress generation mechanism, NiPt-silicide microstructure analyses were performed using X-ray diffraction analysis and scanning transmission electron microscopy. The channel stress generation mechanism can be elucidated by the following two factors: the change in the NiSi lattice spacing, which depends on the annealing temperature, and the NiSi crystal orientation. The analyses of these factors are important for controlling channel stress in stress engineering for high-performance transistors.

  8. Performance enhancement of multiple-gate ZnO metal-oxide-semiconductor field-effect transistors fabricated using self-aligned and laser interference photolithography techniques

    PubMed Central

    2014-01-01

    The simple self-aligned photolithography technique and laser interference photolithography technique were proposed and utilized to fabricate multiple-gate ZnO metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the multiple-gate structure could improve the electrical field distribution along the ZnO channel, the performance of the ZnO MOSFETs could be enhanced. The performance of the multiple-gate ZnO MOSFETs was better than that of the conventional single-gate ZnO MOSFETs. The higher the drain-source saturation current (12.41 mA/mm), the higher the transconductance (5.35 mS/mm) and the lower the anomalous off-current (5.7 μA/mm) for the multiple-gate ZnO MOSFETs were obtained. PMID:24948884

  9. Simulation Study of Intrinsic Parameter Fluctuations in Variable-Body-Factor Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Yang, Yunxiang; Du, Gang; Han, Ruqi; Liu, Xiaoyan

    2011-04-01

    The effects of intrinsic parameter fluctuations, including line-edge-roughness (LER), silicon-body thickness variation (STV) and work-function variation (WFV), in 20-nm-gate variable-γ silicon-on-thin-box (SOTB) metal oxide semiconductor field effect transistors (MOSFETs) have been investigated and compared with those of the conventional SOTB. Results show that the variable-γ SOTB offers not only an enhanced Ion but also a reduced Ion fluctuation with a small increase in the active-state Ioff fluctuation. The Vth-roll-off value in the variable-γ SOTB can be reduced by adopting a reverse-biased side gate to optimize the short channel effect, but the variability of the DIBL effect is enlarged. It is expected that a thinner silicon body can be used to reduce the dominant variability sources.

  10. P-Channel InGaN/GaN heterostructure metal-oxide-semiconductor field effect transistor based on polarization-induced two-dimensional hole gas

    NASA Astrophysics Data System (ADS)

    Zhang, Kexiong; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Sang, Liwen

    2016-03-01

    The concept of p-channel InGaN/GaN heterostructure field effect transistor (FET) using a two-dimensional hole gas (2DHG) induced by polarization effect is demonstrated. The existence of 2DHG near the lower interface of InGaN/GaN heterostructure is verified by theoretical simulation and capacitance-voltage profiling. The metal-oxide-semiconductor FET (MOSFET) with Al2O3 gate dielectric shows a drain-source current density of 0.51 mA/mm at the gate voltage of ‑2 V and drain bias of ‑15 V, an ON/OFF ratio of two orders of magnitude and effective hole mobility of 10 cm2/Vs at room temperature. The normal operation of MOSFET without freeze-out at 8 K further proves that the p-channel behavior is originated from the polarization-induced 2DHG.

  11. Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

    NASA Astrophysics Data System (ADS)

    Yan-Wen, Chen; Zhen, Tan; Lian-Feng, Zhao; Jing, Wang; Yi-Zhou, Liu; Chen, Si; Fang, Yuan; Wen-Hui, Duan; Jun, Xu

    2016-03-01

    Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally and theoretically investigated. The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V·s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxial compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands. Project supported by the National Basic Research Program of China (Grant No. 2011CBA00602) and the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2011ZX02708-002).

  12. P-Channel InGaN/GaN heterostructure metal-oxide-semiconductor field effect transistor based on polarization-induced two-dimensional hole gas.

    PubMed

    Zhang, Kexiong; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Sang, Liwen

    2016-01-01

    The concept of p-channel InGaN/GaN heterostructure field effect transistor (FET) using a two-dimensional hole gas (2DHG) induced by polarization effect is demonstrated. The existence of 2DHG near the lower interface of InGaN/GaN heterostructure is verified by theoretical simulation and capacitance-voltage profiling. The metal-oxide-semiconductor FET (MOSFET) with Al2O3 gate dielectric shows a drain-source current density of 0.51 mA/mm at the gate voltage of -2 V and drain bias of -15 V, an ON/OFF ratio of two orders of magnitude and effective hole mobility of 10 cm(2)/Vs at room temperature. The normal operation of MOSFET without freeze-out at 8 K further proves that the p-channel behavior is originated from the polarization-induced 2DHG. PMID:27021054

  13. Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

    NASA Astrophysics Data System (ADS)

    Lu, Anh Khoa Augustin; Pourtois, Geoffrey; Agarwal, Tarun; Afzalian, Aryan; Radu, Iuliana P.; Houssa, Michel

    2016-01-01

    The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs.

  14. Room-temperature detection of spin accumulation in silicon across Schottky tunnel barriers using a metal-oxide-semiconductor field effect transistor structure (invited)

    NASA Astrophysics Data System (ADS)

    Hamaya, K.; Ando, Y.; Masaki, K.; Maeda, Y.; Fujita, Y.; Yamada, S.; Sawano, K.; Miyao, M.

    2013-05-01

    Using a metal-oxide-semiconductor field effect transistor structure with a high-quality CoFe/n+-Si contact, we systematically study spin injection and spin accumulation in a nondegenerated Si channel with a doping density of ˜4.5 × 1015 cm-3 at room temperature. By applying the gate voltage (VG) to the channel, we obtain sufficient bias currents (IBias) for creating spin accumulation in the channel and observe clear spin-accumulation signals even at room temperature. Whereas the magnitude of the spin signals is enhanced by increasing IBias, it is reduced by increasing VG interestingly. These features can be understood within the framework of the conventional spin diffusion model. As a result, a room-temperature spin injection technique for the nondegenerated Si channel without using insulating tunnel barriers is established, which indicates a technological progress for Si-based spintronic applications with gate electrodes.

  15. Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

    PubMed

    Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

    2007-05-01

    Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important. PMID:17388638

  16. Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Arai, Yukiko; Aoki, Hitoshi; Abe, Fumitaka; Todoroki, Shunichiro; Khatami, Ramin; Kazumi, Masaki; Totsuka, Takuya; Wang, Taifeng; Kobayashi, Haruo

    2015-04-01

    1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.

  17. A new third-level charge pumping method for accurate determination of interface-trap parameters in metal-oxide-semiconductor field-effect-transistors

    NASA Astrophysics Data System (ADS)

    Autran, Jean-Luc; Balland, Bernard

    1994-06-01

    We propose a new implementation of the third-level charge pumping technique for a precise determination of the energy distributions of electron and hole cross sections and interface state density in metal-oxide-semiconductor field-effect transistors (MOSFETs). Using an arbitrary function generator with a high clock rate and a sufficient storage memory length, it is possible to evaluate interface trap emission times and interface state densities in small geometry MOSFETs with a high-enegy resolution. The accuracy of the technique has been greatly increased owing to the high stability and the weak distortion of the signal applied to the gate of the device (numerically generating via a high-speed digital-to-analog converter) and the development of a new acquisition procedure. To illustrate the performance of this method, we present the first results concerning the characterization of 0.6 μm N-channel MOSFETs.

  18. Magnetoresistance of a Spin Metal-Oxide-Semiconductor Field-Effect Transistor with Ferromagnetic MnAs Source and Drain Contacts

    NASA Astrophysics Data System (ADS)

    Nakane, Ryosho; Harada, Tomoyuki; Sugiura, Kuniaki; Tanaka, Masaaki

    2010-11-01

    Transport characteristics were investigated in a spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) with ferromagnetic MnAs source and drain (S/D) contacts. A bottom-gate type spin MOSFET was fabricated by photolithography using an epitaxial MnAs film grown on a silicon-on-insulator (SOI) substrate. In-plane magnetoresistance showed a square like hysteretic behavior, when measurements were performed with constant source-drain and source-gate biases. From the comparison with the magnetization-related resistance change resulting from the MnAs contacts, a highly possible origin of the feature obtained for the spin MOSFET is the spin-valve effect originating from the spin-dependent transport in the Si channel.

  19. Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Djara, V.; Cherkaoui, K.; Negara, M. A.; Hurley, P. K.

    2015-11-28

    An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N{sub inv}) from the trapped charge density in high-k/InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I{sub d}-V{sub g} measurements enabled an accurate effective mobility vs N{sub inv} extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs.

  20. Tensile-Strained GeSn Metal-Oxide-Semiconductor Field-Effect Transistor Devices on Si(111) Using Solid Phase Epitaxy

    NASA Astrophysics Data System (ADS)

    Lieten, Ruben R.; Maeda, Tatsuro; Jevasuwan, Wipakorn; Hattori, Hiroyuki; Uchida, Noriyuki; Miura, Shu; Tanaka, Masatoshi; Locquet, Jean-Pierre

    2013-10-01

    We demonstrate tensile-strained GeSn metal-oxide-semiconductor field-effect transistor (MOSFET) devices on Si(111) substrates using solid phase epitaxy of amorphous GeSn layers. Amorphous GeSn layers are obtained by limiting the adatom surface mobility during deposition. Subsequent annealing transforms the amorphous layer into single-crystalline GeSn by solid phase epitaxy. Single-crystalline GeSn layers with 4.5% Sn and 0.33% tensile strain are fabricated on Si(111) substrates. To verify the structural quality of thin-film GeSn as a channel material, we fabricate ultrathin GeSn p-channel MOSFETs (pMOSFETs) on Si(111). We demonstrate junctionless depletion-mode operation of tensile-strained GeSn(111) pMOSFETs on Si substrates.

  1. Strained germanium-tin (GeSn) p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with ammonium sulfide passivation

    NASA Astrophysics Data System (ADS)

    Wang, Lanxiang; Su, Shaojian; Wang, Wei; Gong, Xiao; Yang, Yue; Guo, Pengfei; Zhang, Guangze; Xue, Chunlai; Cheng, Buwen; Han, Genquan; Yeo, Yee-Chia

    2013-05-01

    High-mobility strained Ge0.958Sn0.042 p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with ammonium sulfide [(NH4)2S] surface passivation were demonstrated. A ˜10 nm thick fully-strained single crystalline GeSn layer was epitaxially grown on Ge (1 0 0) substrate as the channel layer. (NH4)2S surface passivation was performed for the GeSn surface, followed by gate stack formation. Ge0.958Sn0.042 p-MOSFETs with (NH4)2S passivation show decent electrical characteristics and a peak effective mobility of 509 cm2/V s, which is the highest reported peak mobility obtained for GeSn channel p-MOSFETs so far.

  2. Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

    SciTech Connect

    Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Oktyabrsky, Serge; Veksler, Dmitry; Hill, Richard

    2014-03-31

    In this work, we are using a gated Hall method for measurement of free carrier density and electron mobility in buried InGaAs quantum well metal-oxide-semiconductor field-effect-transistor channels. At room temperature, mobility over 8000 cm{sup 2}/Vs is observed at ∼1.4 × 10{sup 12} cm{sup −2}. Temperature dependence of the electron mobility gives the evidence that remote Coulomb scattering dominates at electron density <2 × 10{sup 11} cm{sup −2}. Spectrum of the interface/border traps is quantified from comparison of Hall data with capacitance-voltage measurements or electrostatic modeling. Above the threshold voltage, gate control is strongly limited by fast traps that cannot be distinguished from free channel carriers just by capacitance-based methods and can be the reason for significant overestimation of channel density and underestimation of carrier mobility from transistor measurements.

  3. The n-type metal-oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

    NASA Astrophysics Data System (ADS)

    Touhami, A.; Bouhdada, A.

    2002-12-01

    The band-to-band tunnelling (BBT) effect in an n-type metal-oxide semiconductor field-effect transistor (n-MOSFET) is attributed not only to the transverse electric field ET but also to the lateral electric field EL in the gate-to-drain overlap region. The main sources of these electric fields are the gate-source (Vgs) and drain-source (Vds) voltages. The modelling of the gate-induced drain leakage current, Igidl, associated with BBT remains always dependent on the drain-gate voltage, Vdg, whatever the applied values of Vgs and Vds, which cannot describe accurately the evolution of the Igidl current according to biases. Therefore, it is necessary to clarify the impact of Vgs and Vds separately. In this paper, we propose a new model of the Igidl current, which can describe the BBT effect in n-MOSFETs under various Vgs and Vds biases.

  4. Operation of the GaSb p-channel metal-oxide-semiconductor field-effect transistors fabricated on (111)A surfaces

    SciTech Connect

    Nishi, K. Takenaka, M.; Takagi, S.; Yokoyama, M.; Yokoyama, H.; Hoshi, T.; Sugiyama, H.

    2014-12-08

    We demonstrate the operation of GaSb p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on (111)A surfaces with Al{sub 2}O{sub 3} gate dielectrics formed by atomic-layer deposition at 150 °C. The p-MOSFETs on (111)A surfaces exhibit higher drain current and lower subthreshold swing than those on (100) surfaces. We find that the interface-state density (D{sub it}) values at the Al{sub 2}O{sub 3}/GaSb MOS interfaces on the (111)A surfaces are lower than those on the (100) surfaces, which can lead to performance enhancement of the GaSb p-MOSFETs on (111)A surfaces. The mobility of the GaSb p-MOSFETs on (111)A surfaces is 80% higher than that on (100) surfaces.

  5. Electron detrapping characteristics in positive bias temperature stressed n-channel metal-oxide-semiconductor field-effect transistors with ultrathin HfSiON gate dielectrics

    NASA Astrophysics Data System (ADS)

    Zhu, Shiyang; Nakajima, Anri

    2007-07-01

    Electrons trapped in the HfSiON gate dielectrics of n-channel metal-oxide-semiconductor field-effect transistors induced by positive bias temperature stress start to decay when the stress is interrupted or an opposite (recovery) voltage is applied. The decay begins with a quick detrapping within tens of nanoseconds followed by a slow detrapping. The quick detrapping depends on the recovery voltage and the trapping history, whereas the slow detrapping obeys approximately a logarithmic dependence on time with an almost identical slope before saturation. The observed detrapping behavior can be explained by a spatial and/or energetic distribution of trapped electrons in the HfSiON film. The device degradation under various dynamic stresses is found to be almost independent of frequency ranging from 0.001to1MHz, while it is slightly enhanced at 10MHz, probably due to insufficient recovery at the recovering half cycle.

  6. Characteristics of flexographic printed indium-zinc-oxide thin films as an active semiconductor layer in thin film field-effect transistors

    NASA Astrophysics Data System (ADS)

    Dilfer, Stefan; Hoffmann, Rudolf C.; Dörsam, Edgar

    2014-11-01

    Characteristics of oxide semiconductor thin film transistors prepared by flexographic printing technique have been studied. The device was a field-effect transistor substrate (15 mm × 15 mm, n-doped silicon, 90 nm SiO2 layer) with pre-structured gold electrodes and a printed active layer. The active layer was printed with a indium-zinc-oxide precursor solution and then annealed at 450 °C for 4 min on a hotplate. Influences of typographical parameters, i.e. printing pressure, anilox roller pressure, ink supply rate, printing velocity and printing plate (cliché) properties were studied. Reference active layers were produced by spin coating. The printed IZO ceramic layer with a dry film thickness between 3 and 8 nm, deposited onto the substrate for field-effect transistors provided a good performance with charge carrier mobilities (μ) up to 2.4 cm2 V-1 s-1, on/off current ratios (Ion/off ratio) up to 5.2 × 107 and mean threshold voltages (Vth) of +4 V. The characterization of the printed and annealed IZO layer by AFM revealed the amorphous nature of the printed active layer films with a root-mean square roughness of 0.8 nm.

  7. A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process

    NASA Astrophysics Data System (ADS)

    Lee, Te Liang; Tsang Tsai, Ming; King, Ya Chin; Lin, Chrong Jung

    2013-04-01

    In this paper, a novel sub-20 V device which is called contact gate MOSFET (CGMOS) with fully CMOS logic compatible process is proposed and demonstrated. Comparing with lateral double diffusion MOSFET (LDMOS), CGMOS uses P substrate instead of N minus layer as drift region in logic process, and a contact on resistance protection oxide (RPO) layers to form an extra gate on the drain side of the channel region to provide a better gate control and reduce the surface field. This new device significantly rises up the breakdown voltage to 18 V with specific on-resistance 8.8 mΩ.mm2 in a small high voltage (HV) MOSFET area. Since there is no extra mask for creating the drift region or additional step for the wire bonding, CGMOS makes the integration of high voltage and logic circuits much simpler and area-saving.

  8. Design and Analysis of Power Low-Temperature Polysilicon Lateral Double-Diffusion Metal Oxide Semiconductor Field Effect Transistors with Shielding-Trench Structure

    NASA Astrophysics Data System (ADS)

    Lin, Jyh-Ling; Lin, Cang-Ting

    2013-08-01

    A new polycrystalline silicon (poly-Si) lateral double-diffusion metal oxide semiconductor field-effect transistor power device combining super-lateral-growth technology and shielding-trench oxide structures (STO-LDMOSFET) is introduced. The trench oxide offers a platform for amorphous silicon lateral growth through excimer laser annealing; this not only enables stable control of the crystallization of poly-Si but also promotes the blocking ability of devices. The breakdown voltages of the manufactured devices with and without trench oxide are 460 and 387 V, respectively, increasing by approximately 73 V. The characteristics of poly-Si treated with an excimer laser were obtained by low-temperature poly-Si LDMOSFET (LTPS-LDMOSFET) measurement and simulation. Then, STO-LDMOSFETs were studied by simulation. The results showed that the STO-LDMOSFET with a 150 cm2 V-1 s-1 mobility had a breakdown voltage and a specific on-resistance of approximately 450 V and 16 Ω cm2, respectively, at a 40 µm drift region length.

  9. Microwave assisted synthesis and characterisation of a zinc oxide/tobacco mosaic virus hybrid material. An active hybrid semiconductor in a field-effect transistor device

    PubMed Central

    Sanctis, Shawn; Hoffmann, Rudolf C; Eiben, Sabine

    2015-01-01

    Summary Tobacco mosaic virus (TMV) has been employed as a robust functional template for the fabrication of a TMV/zinc oxide field effect transistor (FET). A microwave based approach, under mild conditions was employed to synthesize stable zinc oxide (ZnO) nanoparticles, employing a molecular precursor. Insightful studies of the decomposition of the precursor were done using NMR spectroscopy and material characterization of the hybrid material derived from the decomposition was achieved using dynamic light scattering (DLS), transmission electron microscopy (TEM), grazing incidence X-ray diffractometry (GI-XRD) and atomic force microscopy (AFM). TEM and DLS data confirm the formation of crystalline ZnO nanoparticles tethered on top of the virus template. GI-XRD investigations exhibit an orientated nature of the deposited ZnO film along the c-axis. FET devices fabricated using the zinc oxide mineralized virus template material demonstrates an operational transistor performance which was achieved without any high-temperature post-processing steps. Moreover, a further improvement in FET performance was observed by adjusting an optimal layer thickness of the deposited ZnO on top of the TMV. Such a bio-inorganic nanocomposite semiconductor material accessible using a mild and straightforward microwave processing technique could open up new future avenues within the field of bio-electronics. PMID:25977849

  10. New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides

    NASA Astrophysics Data System (ADS)

    Lee, Hai-Ming; Liu, Cheng-Jye; Hsu, Chih-Wei; Liang, Mong-Song; King, Ya-Chin; Hsu, Charles Ching-Hsiang

    2001-03-01

    A new trap-assisted band-to-band tunneling (TAB) gate current model is proposed to describe the new observed band-to-band tunneling (BBT) induced gate current characteristics of p-channel metal-oxide-semiconductor field effect transistors (PMOSFET’s) with ultra-thin gate oxide. Based on this new TAB gate current model, the off-state gate currents of PMOSFET’s with various sub-3 nm gate oxides can be well characterized, while the conventional BBT current model is no longer applicable in this regime.

  11. Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2014-11-24

    Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility of exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.

  12. A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Chiang, Te-Kuang; Chen, Mei-Li

    2007-06-01

    Based on resultant solution of a two-dimensional (2D) Poisson’s equation in the silicon region, a new analytical model for short-channel fully depleted, symmetrical dual-material double-gate (SDMDG) metal-oxide-semiconductor field effect transistors (MOSFETs) has been developed. The SDMDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical double-gate (SDG) MOSFET due to the step potential profile at the interface between different gate materials. It is found that the threshold voltage roll-off can be effectively reduced using both the thin Si film and thin gate oxide. A considerable portion of the large workfunction of metal gate 1 (M1) when laterally merged with the small workfunction of metal gate 2 (M2) can efficiently suppress drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. In this work, not only a precise 2D analytical model of the surface potential and threshold voltage is presented, but also the minimum surface potential in M1 of the shorter channel device that brings about subthreshold swing degradation for the SDMDG MOSFET is discussed. The new model is verified to be in good agreement with numerical simulation results over a wide range of device parameters.

  13. P-Channel InGaN/GaN heterostructure metal-oxide-semiconductor field effect transistor based on polarization-induced two-dimensional hole gas

    PubMed Central

    Zhang, Kexiong; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Sang, Liwen

    2016-01-01

    The concept of p-channel InGaN/GaN heterostructure field effect transistor (FET) using a two-dimensional hole gas (2DHG) induced by polarization effect is demonstrated. The existence of 2DHG near the lower interface of InGaN/GaN heterostructure is verified by theoretical simulation and capacitance-voltage profiling. The metal-oxide-semiconductor FET (MOSFET) with Al2O3 gate dielectric shows a drain-source current density of 0.51 mA/mm at the gate voltage of −2 V and drain bias of −15 V, an ON/OFF ratio of two orders of magnitude and effective hole mobility of 10 cm2/Vs at room temperature. The normal operation of MOSFET without freeze-out at 8 K further proves that the p-channel behavior is originated from the polarization-induced 2DHG. PMID:27021054

  14. Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

    SciTech Connect

    Akhavan, N. D. Jolley, G.; Umana-Membreno, G. A.; Antoszewski, J.; Faraone, L.

    2014-08-28

    Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs based on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.

  15. Characteristics and Modeling of a Nonplanar Nonrectangular Metal Oxide Semiconductor Field Effect Transistor for Charge Sensing in the Si Micro-Fluidic Channel

    NASA Astrophysics Data System (ADS)

    Lim, Geunbae; Kim, Dong-Sun; Lyu, Hong-Kun; Park, Hey-Jung; Shin, Jang-Kyoo; Choi, Pyung; Lee, Jong-Hyun; Lee, Minho

    2004-06-01

    In this work, a nonplanar, nonrectangular metal-oxide-semiconductor field effect transistor (MOSFET) with an asymmetrical channel structure for sensing charge in the Si micro-fluidic channel was fabricated, and the electrical characteristics of the fabricated three-dimensional (3-D) MOSFET were measured. The device was formed in the convex corner of a Si micro-fluidic channel using tetramethyl ammonium hydroxide (TMAH) anistropic etching solution, so that it would be suitable for combination with a micro-fluidic system. We approximated the nonplanar, nonrectangular 3-D MOSFET to a two-dimensional rectangular structure using the Schwartz-Christoffel transformation. The LEVEL1 device parameters of the 3-D MOSFET were extracted from the measured electrical device characteristics and were used in a simulation program with integrated circuit emphasis (SPICE) simulation. The measured and simulated results for the 3-D MOSFET were compared and found to show good agreement. We also investigated the feasibility of the proposed 3-D MOSFET as a charge sensor for detecting charged biomolecules.

  16. Fabrication of 3-Dimensional Structure of Metal Oxide Semiconductor Field Effect Transistor Embodied in the Convex Corner of the Silicon Micro-Fluidic Channel

    NASA Astrophysics Data System (ADS)

    Lim, Geunbae; Park, Chin-Sung; Lyu, Hong-Kun; Kim, Dong-Sun; Jeong, Yong-Taek; Park, Hey-Jung; Kim, Hyoung Sik; Shin, Jang-Kyoo; Choi, Pyung; Lee, Jong-Hyun

    2003-06-01

    As micro-fluidic systems and biochemical detection systems are scaled to smaller dimensions, the realization of small and portable biochemical detection systems has become increasingly important. In this paper, we propose a 3-dimensional structure of a metal oxide semiconductor field-effect transistor(3-D MOSFET) using tetramethyl ammonium hydroxide (TMAH) anisotropic etching, which is a suitable device for combining with a micro-fluidic system. After fabricating a trapezoidal micro-fluidic channel, the 3-D MOSFET embodied in the convex corner of the micro-fluidic channel was fabricated. The length of the gate is about 20 μm and the width is about 9 μm. The depth and top width of the trapezoidal micro-fluidic channel are about 8 μm and 60 μm, respectively. The measured drain saturation current of the 3-D MOSFET was about -22 μA at VGS=-5 V and VDS=-5 V, and the device characteristics exhibit a typical MOSFET behavior. Moreover, a gold layer was used for the MOSFET’s gate metal to detect charged biochemical samples using the affinity between gold and thiol.

  17. Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

    PubMed

    Putranto, Dedy Septono Catur; Priambodo, Purnomo Sidi; Hartanto, Djoko; Du, Wei; Satoh, Hiroaki; Ono, Atsushi; Inokawa, Hiroshi

    2014-09-01

    Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation. PMID:25321581

  18. Radiofrequency current source (RFCS) drive and decoupling technique for parallel transmit arrays using a high-power metal oxide semiconductor field-effect transistor (MOSFET).

    PubMed

    Lee, Wonje; Boskamp, Eddy; Grist, Thomas; Kurpad, Krishna

    2009-07-01

    A radiofrequency current source (RFCS) design using a high-power metal oxide semiconductor field effect transistor (MOSFET) that enables independent current control for parallel transmit applications is presented. The design of an RFCS integrated with a series tuned transmitting loop and its associated control circuitry is described. The current source is operated in a gated class AB push-pull configuration for linear operation at high efficiency. The pulsed RF current amplitude driven into the low impedance transmitting loop was found to be relatively insensitive to the various loaded loop impedances ranging from 0.4 to 10.3 ohms, confirming current mode operation. The suppression of current induced by a neighboring loop was quantified as a function of center-to-center loop distance, and was measured to be 17 dB for nonoverlapping, adjacent loops. Deterministic manipulation of the B(1) field pattern was demonstrated by the independent control of RF phase and amplitude in a head-sized two-channel volume transmit array. It was found that a high-voltage rated RF power MOSFET with a minimum load resistance, exhibits current source behavior, which aids in transmit array design. PMID:19353658

  19. Characterization of high-sensitivity metal oxide semiconductor field effect transistor dosimeters system and LiF:Mg,Cu,P thermoluminescence dosimeters for use in diagnostic radiology.

    PubMed

    Dong, S L; Chu, T C; Lan, G Y; Wu, T H; Lin, Y C; Lee, J S

    2002-12-01

    Monitoring radiation exposure during diagnostic radiographic procedures has recently become an area of interest. In recent years, the LiF:Mg,Cu,P thermoluminescence dosimeter (TLD-100H) and the highly sensitive metal oxide semiconductor field effect transistor (MOSFET) dosimeter were introduced as good candidates for entrance skin dose measurements in diagnostic radiology. In the present study, the TLD-100H and the MOSFET dosimeters were evaluated for sensitivity, linearity, energy, angular dependence, and post-exposure response. Our results indicate that the TLD-100H dosimeter has excellent linearity within diagnostic energy ranges and its sensitivity variations were under 3% at tube potentials from 40Vp to 125kVp. Good linearity was also observed with the MOSFET dosimeter, but in low-dose regions the values are less reliable and were found to be a function of the tube potentials. Both dosimeters also presented predictable angular dependence in this study. Our findings suggest that the TLD-100H dosimeter is more appropriate for low-dose diagnostic procedures such as chest and skull projections. The MOSFET dosimeter system is valuable for entrance skin dose measurement with lumbar spine projections and certain fluoroscopic procedures. PMID:12406633

  20. Ultrathin body GaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

    SciTech Connect

    Yokoyama, Masafumi Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Haruki

    2015-02-16

    We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al{sub 2}O{sub 3} and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ∼76 cm{sup 2}/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al{sub 2}O{sub 3} ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm{sup 2}/V s for GaSb-OI p-MOSFETs with the 20-nm-thick GaSb layer.

  1. Strained Germanium-Tin (GeSn) P-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Featuring High Effective Hole Mobility

    NASA Astrophysics Data System (ADS)

    Liu, Yan; Yan, Jing; Wang, Hongjuan; Cheng, Buwen; Han, Genquan

    2015-06-01

    Compressively strained and p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated with low-temperature surface passivation. High crystallinity GeSn films epitaxially grown on a Ge(001) substrate are used for the device fabrication. The impacts of the Sn composition on the subthreshold swing , threshold voltage , on-state current , and effective hole mobility of the devices are investigated. GeSn pMOSFETs with different Sn compositions show a similar , indicating almost the same midgap density of interface states . A positive shift of with an increase of the Sn composition is observed. A pMOSFET exhibits a significant improvement in as compared to a device with a lower Sn composition, which is due to the superior hole mobility in a device with a higher Sn composition. pMOSFETs achieve a peak effective hole mobility of , which is much higher than that of devices. The enhancement of the compressive strain and chemical effect in the channel region with increased Sn composition leads to an improvement of.

  2. Electron power loss in the (100) n channel of a Si metal-oxide-semiconductor field-effect transistor. I. Intrasubband phonon scattering

    NASA Astrophysics Data System (ADS)

    Krowne, Clifford M.

    1983-05-01

    The electron energy relaxation is studied as a function of the ``electron temperature'' Te in the n channel of a (100) surface silicon MOSFET (metal-oxide-semiconductor field-effect transistor) device by inspecting the phenomenological energy relaxation time τɛ(Te) at 4.2 °K, 77 °K, and 300 °K lattice temperatures. τɛ is theoretically calculated in order to determine the relative contributions of shear horizontal (SH), pressure-shear vertical (P-SV), shear vertical-pressure (SV-P), total reflection shear vertical pressure (TR), and Rayleigh (R) surface acoustic phonon modes to the electron energy relaxation at the interface. Two-dimensional electron transport is assumed and the effects of subbanding near the interface are included. Only electron scatter events within subbands are studied (intrasubband). This exhaustive study finds that surface modes do not dominate the electron energy relaxation at the Si-SiO2 interface at TL =4.2 °K. Some other mechanism(s) must predominate at TL =4.2 °K.

  3. Modeling of anisotropic two-dimensional materials monolayer HfS{sub 2} and phosphorene metal-oxide semiconductor field effect transistors

    SciTech Connect

    Chang, Jiwon

    2015-06-07

    Ballistic transport characteristics of metal-oxide semiconductor field effect transistors (MOSFETs) based on anisotropic two-dimensional materials monolayer HfS{sub 2} and phosphorene are explored through quantum transport simulations. We focus on the effects of the channel crystal orientation and the channel length scaling on device performances. Especially, the role of degenerate conduction band (CB) valleys in monolayer HfS{sub 2} is comprehensively analyzed. Benchmarking monolayer HfS{sub 2} with phosphorene MOSFETs, we predict that the effect of channel orientation on device performances is much weaker in monolayer HfS{sub 2} than in phosphorene due to the degenerate CB valleys of monolayer HfS{sub 2}. Our simulations also reveal that at 10 nm channel length scale, phosphorene MOSFETs outperform monolayer HfS{sub 2} MOSFETs in terms of the on-state current. However, it is observed that monolayer HfS{sub 2} MOSFETs may offer comparable, but a little bit degraded, device performances as compared with phosphorene MOSFETs at 5 nm channel length.

  4. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    PubMed

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-01

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

  5. Metal-Oxide-Semiconductor Field-Effect-Transistors Possessing Step Functional I-V Curves Caused by the Punch Through between Drain and Inversion Layer of the Gate

    NASA Astrophysics Data System (ADS)

    Karasawa, Shinji; Yamanouchi, Kazuhiko; Tachibana, Yukio

    1992-02-01

    Through measurements of an Al gate p-channel Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) with a gap between the gate and drain, the behavior of the minority carrier in the depletion layer is clarified. The turn-on drain voltage depends upon the length and the density of impurity on the punch-through area. That is, Vd{=}-4 V for Lgap{=}0.5 μm in 3˜5 Ω\\cdotcm n-Si wafer and Vd{=}-3 V for Lgap{=}2.0 μm in 120˜200 Ω\\cdotcm n-Si wafer. The abrupt step functional I-V curve is revealed under the condition of low gate voltage. There are surface effects by which the higher the gate voltage, the lower the turn-on voltage of the drain becomes. The hole mobility in the depletion layer made from lightly doped < 111> wafer abruptly decreases when the temperature is lowered to below 20 K and the turn-on voltage on the step function MOSFET increases remarkably at 4.2 K.

  6. CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

    NASA Astrophysics Data System (ADS)

    Yang, Yuan; Gao, Yong; Gong, Peng-Liang

    2008-08-01

    A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured.

  7. Hole Confinement and 1/ f Noise Characteristics of SiGe Double-Quantum-Well p-Type Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Lin, Yu Min; Wu, San Lein; Chang, Shoou Jinn; Chen, Pang Shiu; Liu, Chee Wee

    2006-05-01

    A working p-type SiGe double-quantum-well metal-oxide-semiconductor field effect transistor (DQW-pMOSFETs) has been fabricated and characterized. The upper quantum well with 15%-Ge acts as an induced-carrier buffer to slow holes into the Si surface channel and increases the number of high-mobility holes in the 30%-Ge well at the bottom under high gate voltage by improving carrier confinement. DQW devices with a thinner Si-spacer layer between the two SiGe quantum wells exhibit an improved effective hole mobility and wider gate voltage swings but also reduced 1/ f noise levels than Si-controlled pMOSFETs. The DQW has an enhanced carrier confinement compared to a single quantum-well (SQW) device; however, the degradation of mobility and transconductance observed in a sample DQW indicates that this poor transport mechanism may result from an additional hole scattering effect at the Si/SiGe interface.

  8. The Impacts of Contact Etch Stop Layer Thickness and Gate Height on Channel Stress in Strained N-Metal Oxide Semiconductor Field Effect Transistors.

    PubMed

    Lin, K C; Twu, M J; Deng, R H; Liu, C H

    2015-04-01

    The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET. PMID:26353480

  9. Sample size requirements for estimating effective dose from computed tomography using solid-state metal-oxide-semiconductor field-effect transistor dosimetry

    SciTech Connect

    Trattner, Sigal; Cheng, Bin; Pieniazek, Radoslaw L.; Hoffmann, Udo; Douglas, Pamela S.; Einstein, Andrew J.

    2014-04-15

    Purpose: Effective dose (ED) is a widely used metric for comparing ionizing radiation burden between different imaging modalities, scanners, and scan protocols. In computed tomography (CT), ED can be estimated by performing scans on an anthropomorphic phantom in which metal-oxide-semiconductor field-effect transistor (MOSFET) solid-state dosimeters have been placed to enable organ dose measurements. Here a statistical framework is established to determine the sample size (number of scans) needed for estimating ED to a desired precision and confidence, for a particular scanner and scan protocol, subject to practical limitations. Methods: The statistical scheme involves solving equations which minimize the sample size required for estimating ED to desired precision and confidence. It is subject to a constrained variation of the estimated ED and solved using the Lagrange multiplier method. The scheme incorporates measurement variation introduced both by MOSFET calibration, and by variation in MOSFET readings between repeated CT scans. Sample size requirements are illustrated on cardiac, chest, and abdomen–pelvis CT scans performed on a 320-row scanner and chest CT performed on a 16-row scanner. Results: Sample sizes for estimating ED vary considerably between scanners and protocols. Sample size increases as the required precision or confidence is higher and also as the anticipated ED is lower. For example, for a helical chest protocol, for 95% confidence and 5% precision for the ED, 30 measurements are required on the 320-row scanner and 11 on the 16-row scanner when the anticipated ED is 4 mSv; these sample sizes are 5 and 2, respectively, when the anticipated ED is 10 mSv. Conclusions: Applying the suggested scheme, it was found that even at modest sample sizes, it is feasible to estimate ED with high precision and a high degree of confidence. As CT technology develops enabling ED to be lowered, more MOSFET measurements are needed to estimate ED with the same

  10. A methodology to identify and quantify mobility-reducing defects in 4H-silicon carbide power metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ettisserry, D. P.; Goldsman, N.; Lelis, A.

    2014-03-01

    In this paper, we present a methodology for the identification and quantification of defects responsible for low channel mobility in 4H-Silicon Carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs). To achieve this, we use an algorithm based on 2D-device simulations of a power MOSFET, density functional simulations, and measurement data. Using physical modeling of carrier mobility and interface traps, we reproduce the experimental I-V characteristics of a 4H-SiC doubly implanted MOSFET through drift-diffusion simulation. We extract the position of Fermi level and the occupied trap density as a function of applied bias and temperature. Using these inputs, our algorithm estimates the number of possible trap types, their energy levels, and concentrations at 4H-SiC/SiO2 interface. Subsequently, we use density functional theory (DFT)-based ab initio simulations to identify the atomic make-up of defects causing these trap levels. We study silicon vacancy and carbon di-interstitial defects in the SiC side of the interface. Our algorithm indicates that the Dit spectrum near the conduction band edge (3.25 eV) is composed of three trap types located at 2.8-2.85 eV, 3.05 eV, and 3.1-3.2 eV, and also calculates their densities. Based on DFT simulations, this work attributes the trap levels very close to the conduction band edge to the C di-interstitial defect.

  11. Sample size requirements for estimating effective dose from computed tomography using solid-state metal-oxide-semiconductor field-effect transistor dosimetry

    PubMed Central

    Trattner, Sigal; Cheng, Bin; Pieniazek, Radoslaw L.; Hoffmann, Udo; Douglas, Pamela S.; Einstein, Andrew J.

    2014-01-01

    Purpose: Effective dose (ED) is a widely used metric for comparing ionizing radiation burden between different imaging modalities, scanners, and scan protocols. In computed tomography (CT), ED can be estimated by performing scans on an anthropomorphic phantom in which metal-oxide-semiconductor field-effect transistor (MOSFET) solid-state dosimeters have been placed to enable organ dose measurements. Here a statistical framework is established to determine the sample size (number of scans) needed for estimating ED to a desired precision and confidence, for a particular scanner and scan protocol, subject to practical limitations. Methods: The statistical scheme involves solving equations which minimize the sample size required for estimating ED to desired precision and confidence. It is subject to a constrained variation of the estimated ED and solved using the Lagrange multiplier method. The scheme incorporates measurement variation introduced both by MOSFET calibration, and by variation in MOSFET readings between repeated CT scans. Sample size requirements are illustrated on cardiac, chest, and abdomen–pelvis CT scans performed on a 320-row scanner and chest CT performed on a 16-row scanner. Results: Sample sizes for estimating ED vary considerably between scanners and protocols. Sample size increases as the required precision or confidence is higher and also as the anticipated ED is lower. For example, for a helical chest protocol, for 95% confidence and 5% precision for the ED, 30 measurements are required on the 320-row scanner and 11 on the 16-row scanner when the anticipated ED is 4 mSv; these sample sizes are 5 and 2, respectively, when the anticipated ED is 10 mSv. Conclusions: Applying the suggested scheme, it was found that even at modest sample sizes, it is feasible to estimate ED with high precision and a high degree of confidence. As CT technology develops enabling ED to be lowered, more MOSFET measurements are needed to estimate ED with the same

  12. Electron power loss in the (100) n channel of a Si metal-oxide-semiconductor field-effect transistor. II. Intersubband phonon scattering

    NASA Astrophysics Data System (ADS)

    Krowne, Clifford M.

    1983-05-01

    A simple matrix element is used to approximate electron-acoustic phonon scattering between different electron subbands i in the n channel of a (100) surface silicon MOSFET (metal-oxide-semiconductor field-effect transistor) device. This matrix element is used to determine the form of the electron power loss Pij in a i→j intersubband transition. P10 is calculated for TL =4.2 °K lattice temperature and electron temperatures Te between 4.4 °K and 18 °K when the electron inversion density Ninv =(3.76-10.0)×1011 cm-2 and an acceptor density NA =1014/cm3, and compared to Fang and Fowler's experimental data (which is put into the form of an experimental power loss Pexp). This is justified since the total power loss P due to intrasubband scattering as well as other Pij terms besides P10 is small. It is found that good to excellent fits between P10 and Pexp occur by adjusting the separation Δɛ10 between the lowest two circular subband edges. Δɛ10 is between 5.2 and 9.4 meV, and the electron-phonon deformation coupling constant D≊3.5 eV. The values of Δɛ10 obtained in such a manner roughly agree with Stern's theoretical self-consistent results. P10 is very sensitive to both Δɛ10 and to the effective mass for motion parallel to the surface m1 with the results implying that m1≊0.19m0 (m0=free electron rest mass). If one wants to find the contribution of intersubband scattering to P at higher TL, the formalism should still be applicable, although the approach could be much more complicated due to the addition of new Pij terms coming from both higher subbands and new scattering agents such as optical modes.

  13. A methodology to identify and quantify mobility-reducing defects in 4H-silicon carbide power metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ettisserry, D. P. Goldsman, N.; Lelis, A.

    2014-03-14

    In this paper, we present a methodology for the identification and quantification of defects responsible for low channel mobility in 4H-Silicon Carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs). To achieve this, we use an algorithm based on 2D-device simulations of a power MOSFET, density functional simulations, and measurement data. Using physical modeling of carrier mobility and interface traps, we reproduce the experimental I-V characteristics of a 4H-SiC doubly implanted MOSFET through drift-diffusion simulation. We extract the position of Fermi level and the occupied trap density as a function of applied bias and temperature. Using these inputs, our algorithm estimates the number of possible trap types, their energy levels, and concentrations at 4H-SiC/SiO{sub 2} interface. Subsequently, we use density functional theory (DFT)-based ab initio simulations to identify the atomic make-up of defects causing these trap levels. We study silicon vacancy and carbon di-interstitial defects in the SiC side of the interface. Our algorithm indicates that the D{sub it} spectrum near the conduction band edge (3.25 eV) is composed of three trap types located at 2.8–2.85 eV, 3.05 eV, and 3.1–3.2 eV, and also calculates their densities. Based on DFT simulations, this work attributes the trap levels very close to the conduction band edge to the C di-interstitial defect.

  14. A Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for Deep Sub-0.1-μm Channel Regime

    NASA Astrophysics Data System (ADS)

    Yanagi, Shin-ichiro; Nakakubo, Atsushi; Omura, Yasuhisa

    2001-04-01

    Silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) offers a number of advantages over conventional bulk silicon transistors. In this paper, we present a new SOI device structure called a “partial-ground-plane” SOI MOSFET down to 50 nm channel length. This new device shows good suppression of short-channel effect together with a small subthreshold swing and has a good driveability with a low leakage current.

  15. High-performance GaAs-based metal-oxide-semiconductor heterostructure field-effect transistors with atomic-layer-deposited Al2O3 gate oxide and in situ AlN passivation by metalorganic chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2014-10-01

    GaAs-based metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al2O3 gate oxide and in situ AlN passivation were investigated. Passivation with AlN improved the quality of the MOS interfaces, leading to good control of the gate. The devices had a sufficiently small subthreshold swing of 84 mV decade-1 in the drain current vs gate voltage curves, as well as negligible frequency dispersions and nearly zero hysteresis in the gate capacitance vs gate voltage curves. A maximum drain current of 630 mA/mm and a peak effective mobility of 6720 cm2 V-1 s-1 at a sheet carrier density of 3 × 1012 cm-2 were achieved.

  16. Impact of additional Pt and NiSi crystal orientation on channel stress induced by Ni silicide film in metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Mizuo, Mariko; Yamaguchi, Tadashi; Kudo, Shuichi; Hirose, Yukinori; Kimura, Hiroshi; Tsuchimoto, Jun-ichi; Hattori, Nobuyoshi

    2014-01-01

    The impact of additional Pt and Ni monosilicide (NiSi) crystal orientation on channel stress from Ni silicide in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been demonstrated. The channel stress generation mechanism can be explained by the NiSi crystal orientation. In pure Ni silicide films, the channel stress in the p-type substrate is much larger than that in the n-type one, since the NiSi a-axis parallel to the channel direction is strongly aligned on the p-type substrate compared with on the n-type one. On the other hand, in NiPt silicide films, the difference in the channel stress between the p- and n-type substrates is small, because the NiSi crystal orientation on the p-type substrate is similar to that on the n-type one. These results can be explained by the Pt segregation at the interface between the NiSi film and the Si surface. Segregated Pt atoms cause the NiSi b-axis to align normal to the Si(001) surface in the nucleation step owing to the expansion of the NiSi lattice spacing at the NiSi/Si interface. Furthermore, the Pt segregation mechanism is considered to be caused by the grain boundary diffusion in the Ni2Si film during NiSi formation. We confirmed that the grains of Ni2Si on the p-type substrate are smaller than those on the n-type one. The Ni2Si film on the p-type substrate has more grain boundary diffusion paths than that on the n-type one. Therefore, the amount of Pt segregation at the NiSi/Si interface on the p-type substrate is larger than that on the n-type one. Consequently, the number of NiSi grains with the b-axis aligned normal to the Si(001) in the p-type substrate is larger than that in the n-type one. As a result, the channel stress induced by NiPt silicide in PMOS is larger than that in NMOS. According to this mechanism, controlling the Pt concentration at the NiSi/Si interface is one of the key factors for channel stress engineering.

  17. Effective dose assessment in the maxillofacial region using thermoluminescent (TLD) and metal oxide semiconductor field-effect transistor (MOSFET) dosemeters: a comparative study

    PubMed Central

    Schulze, D; Wolff, J; Rottke, D

    2014-01-01

    Objectives: The objective of this study was to compare the performance of metal oxide semiconductor field-effect transistor (MOSFET) technology dosemeters with thermoluminescent dosemeters (TLDs) (TLD 100; Thermo Fisher Scientific, Waltham, MA) in the maxillofacial area. Methods: Organ and effective dose measurements were performed using 40 TLD and 20 MOSFET dosemeters that were alternately placed in 20 different locations in 1 anthropomorphic RANDO® head phantom (the Phantom Laboratory, Salem, NY). The phantom was exposed to four different CBCT default maxillofacial protocols using small (4 × 5 cm) to full face (20 × 17 cm) fields of view (FOVs). Results: The TLD effective doses ranged between 7.0 and 158.0 µSv and the MOSFET doses between 6.1 and 175.0 µSv. The MOSFET and TLD effective doses acquired using four different (FOV) protocols were as follows: face maxillofacial (FOV 20 × 17 cm) (MOSFET, 83.4 µSv; TLD, 87.6 µSv; −5%); teeth, upper jaw (FOV, 8.5 × 5.0 cm) (MOSFET, 6.1 µSv; TLD, 7.0 µSv; −14%); tooth, mandible and left molar (FOV, 4 × 5 cm) (MOSFET, 10.3 µSv; TLD, 12.3 µSv; −16%) and teeth, both jaws (FOV, 10 × 10 cm) (MOSFET, 175 µSv; TLD, 158 µSv; +11%). The largest variation in organ and effective dose was recorded in the small FOV protocols. Conclusions: Taking into account the uncertainties of both measurement methods and the results of the statistical analysis, the effective doses acquired using MOSFET dosemeters were found to be in good agreement with those obtained using TLD dosemeters. The MOSFET dosemeters constitute a feasible alternative for TLDs for the effective dose assessment of CBCT devices in the maxillofacial region. PMID:25143020

  18. Interfacial band configuration and electrical properties of LaAlO3/Al2O3/hydrogenated-diamond metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Liu, J. W.; Liao, M. Y.; Imura, M.; Oosato, H.; Watanabe, E.; Tanaka, A.; Iwai, H.; Koide, Y.

    2013-08-01

    In order to search a gate dielectric with high permittivity on hydrogenated-diamond (H-diamond), LaAlO3 films with thin Al2O3 buffer layers are fabricated on the H-diamond epilayers by sputtering-deposition (SD) and atomic layer deposition (ALD) techniques, respectively. Interfacial band configuration and electrical properties of the SD-LaAlO3/ALD-Al2O3/H-diamond metal-oxide-semiconductor field effect transistors (MOSFETs) with gate lengths of 10, 20, and 30 μm have been investigated. The valence and conduction band offsets of the SD-LaAlO3/ALD-Al2O3 structure are measured by X-ray photoelectron spectroscopy to be 1.1 ± 0.2 and 1.6 ± 0.2 eV, respectively. The valence band discontinuity between H-diamond and LaAlO3 is evaluated to be 4.0 ± 0.2 eV, showing that the MOS structure acts as the gate which controls a hole carrier density. The leakage current density of the SD-LaAlO3/ALD-Al2O3/H-diamond MOS diode is smaller than 10-8 A cm-2 at gate bias from -4 to 2 V. The capacitance-voltage curve in the depletion mode shows sharp dependence, small flat band voltage, and small hysteresis shift, which implies low positive and trapped charge densities. The MOSFETs show p-type channel and complete normally off characteristics with threshold voltages changing from -3.6 ± 0.1 to -5.0 ± 0.1 V dependent on the gate length. The drain current maximum and the extrinsic transconductance of the MOSFET with gate length of 10 μm are -7.5 mA mm-1 and 2.3 ± 0.1 mS mm-1, respectively. The enhancement mode SD-LaAlO3/ALD-Al2O3/H-diamond MOSFET is concluded to be suitable for the applications of high power and high frequency electrical devices.

  19. Effect of temperature on Ga{sub 2}O{sub 3}(Gd{sub 2}O{sub 3})/GaN metal{endash}oxide{endash}semiconductor field-effect transistors

    SciTech Connect

    Ren, F.; Hong, M.; Chu, S.N.; Marcus, M.A.; Schurman, M.J.; Baca, A.; Pearton, S.J.; Abernathy, C.R.

    1998-12-01

    Ga{sub 2}O{sub 3}(Gd{sub 2}O{sub 3}) was deposited on GaN for use as a gate dielectric in order to fabricate a depletion metal{endash}oxide{endash}semiconductor field-effect transistor (MOSFET). Analysis of the effect of temperature on the device shows that gate leakage is significantly reduced at elevated temperature relative to a conventional metal{endash}semiconductor field-effect transistor fabricated on the same GaN layer. MOSFET device operation in fact improved upon heating to 400 {degree}C. Modeling of the effect of temperature on contact resistance suggests that the improvement is due to a reduction in the parasitic resistances present in the device. {copyright} {ital 1998 American Institute of Physics.}

  20. Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

    NASA Astrophysics Data System (ADS)

    El Kazzi, M.; Czornomaz, L.; Rossel, C.; Gerl, C.; Caimi, D.; Siegwart, H.; Fompeyrine, J.; Marchiori, C.

    2012-02-01

    Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001) substrates. Thanks to the presence of the Al2O3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 1011 eV-1 cm-2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO2/1 nm Al2O3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm2 V-1 s-1 and 740 cm2 V-1 s-1 at carrier density of 6.5 × 1012 cm-2) for a 1.3 nm EOT.

  1. Impact of acceptor concentration on electrical properties and density of interface states of 4H-SiC n-metal-oxide-semiconductor field effect transistors studied by Hall effect

    NASA Astrophysics Data System (ADS)

    Ortiz, G.; Strenger, C.; Uhnevionak, V.; Burenkov, A.; Bauer, A. J.; Pichler, P.; Cristiano, F.; Bedel-Pereira, E.; Mortet, V.

    2015-02-01

    Silicon carbide n-type metal-oxide-semiconductor field effect transistors (MOSFETs) with different p-body acceptor concentrations were characterized by Hall effect. Normally OFF MOSFETs with good transfer characteristics and low threshold voltage were obtained with a peak mobility of ˜145 cm2 V-1 s-1 for the lowest acceptor concentration. The results are explained in terms of an increase of Coulomb scattering centers when increasing the background doping. These scattering centers are associated to fixed oxide and trapped interface charges. Additionally, the observed mobility improvement is not related to a decrease of the interface states density as a function of background doping.

  2. Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage Stress

    NASA Astrophysics Data System (ADS)

    Zheng, Qi-Wen; Cui, Jiang-Wei; Yu, Xue-Feng; Guo, Qi; Zhou, Hang; Ren, Di-Yuan

    2014-12-01

    The larger back-gate voltage stress is applied on 130 nm partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors isolated by shallow trench isolation. The experimental results show that the back-gate sub-threshold hump of the device is eliminated by stress. This observed behavior is caused by the high electric field in the oxide near the bottom corner of the silicon island. The total ionizing dose hardness of devices with pre back-gate stress is enhanced by the interface states induced by stress.

  3. Modulation of flat-band voltage on H-terminated silicon-on-insulator pseudo-metal-oxide-semiconductor field effect transistors by adsorption and reaction events

    NASA Astrophysics Data System (ADS)

    Dubey, Girjesh; Rosei, Federico; Lopinski, Gregory P.

    2011-05-01

    Accumulation mode pseudo-MOSFETs formed on hydrogen terminated silicon-on-insulator (SOI-H) were used to probe molecular adsorption and reaction events. Current-voltage characteristics of such n-channel devices are found to be sensitive to the environment, with the accumulation threshold voltage, or flat-band voltage, exhibiting large reversible changes upon cycling between ambient atmosphere, high vacuum (<10-5 Torr), and exposure to water and pyridine vapor at pressures in the Torr range. The field-effect mobility is found to be comparatively less affected through these transitions. Oxidation of the H-terminated surface in ambient conditions leads to irreversible shifts in both the flat-band voltage and the field-effect mobility. A photochemical gas phase reaction with decene is used to form a decyl monolayer on the SOI(100)-H surface. Formation of this monolayer is found to result in a relatively small shift of the threshold voltage and only a slight degradation of the field effect mobility, suggesting that alkyl monolayer dielectrics formed in this way could function as good passivating dielectrics in field effect sensing applications.

  4. Comparison between chemical vapor deposited and physical vapor deposited WSi{sub 2} metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-02

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi{sub 2} metal gate process for In{sub 0.53}Ga{sub 0.47}As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al{sub 2}O{sub 3} as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al{sub 2}O{sub 3} shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  5. Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

    NASA Astrophysics Data System (ADS)

    Dib, E.; Carrillo-Nuñez, H.; Cavassilas, N.; Bescond, M.

    2016-01-01

    Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

  6. Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-field-effect-transistors under hot carrier stress

    NASA Astrophysics Data System (ADS)

    Lo, Wen-Hung; Chang, Ting-Chang; Tsai, Jyun-Yu; Dai, Chih-Hao; Chen, Ching-En; Ho, Szu-Han; Chen, Hua-Mao; Cheng, Osbert; Huang, Cheng-Tung

    2012-04-01

    This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in Gm decrease and positive Vth shift. However, Vth under saturation region shows an insignificant degradation during stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vth between linear and saturation region. The devices with different channel length are used to evidence the trapping-induced DIBL behavior.

  7. The Impact of Shallow-Trench-Isolation Mechanical Stress on the Hysteresis Effect of Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effects

    NASA Astrophysics Data System (ADS)

    Luo, Jie-Xin; Chen, Jing; Chai, Zhan; Lü, Kai; He, Wei-Wei; Yang, Yan; Wang, Xi

    2014-12-01

    The impact of shallow trench isolation (STI) mechanical stress on the hysteresis effect in the output characteristics is measured in partially depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). We develop ID hysteresis, which is defined as the difference between ID versus VD forward sweep and reverse sweep. The fabricated devices show positive and negative peaks in ID hysteresis. The experimental results show that ID hysteresis declined as the STI mechanical stress increases. We also elaborate on the impact of STI mechanical stress on the ID hysteresis of PD SOI n-type MOSFETs.

  8. Design and control of Ge-based metal-oxide-semiconductor interfaces for high-mobility field-effect transistors with ultrathin oxynitride gate dielectrics

    NASA Astrophysics Data System (ADS)

    Minoura, Yuya; Kasuya, Atsushi; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2013-07-01

    High-quality Ge-based metal-oxide-semiconductor (MOS) stacks were achieved with ultrathin oxynitride (GeON) gate dielectrics. An in situ process based on plasma nitridation of the base germanium oxide (GeO2) surface and subsequent metal electrode deposition was proven to be effective for suppressing electrical deterioration induced by the reaction at the metal/insulator interface. The electrical properties of the bottom GeON/Ge interface were further improved by both low-temperature oxidation for base GeO2 formation and high-temperature in situ vacuum annealing after plasma nitridation of the base oxide. Based on the optimized in situ gate stack fabrication process, very high inversion carrier mobility (μhole: 445 cm2/Vs, μelectron: 1114 cm2/Vs) was demonstrated for p- and n-channel Ge MOSFETs with Al/GeON/Ge gate stacks at scaled equivalent oxide thickness down to 1.4 nm.

  9. Metal-semiconductor hybrid thin films in field-effect transistors

    SciTech Connect

    Okamura, Koshi Dehm, Simone; Hahn, Horst

    2013-12-16

    Metal-semiconductor hybrid thin films consisting of an amorphous oxide semiconductor and a number of aluminum dots in different diameters and arrangements are formed by electron beam lithography and employed for thin-film transistors (TFTs). Experimental and computational demonstrations systematically reveal that the field-effect mobility of the TFTs enhances but levels off as the dot density increases, which originates from variations of the effective channel length that strongly depends on the electric field distribution in a transistor channel.

  10. Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

    SciTech Connect

    Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo; Higashi, Seiichiro

    2013-12-02

    A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobility of 609 cm{sup 2} V{sup −1} s{sup −1}.

  11. Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    NASA Astrophysics Data System (ADS)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-01

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in "gate-controlled-diode" configuration. The measurements revealed an anomalous non-steady conduction under negative bias (VG > |20 V|) through the SiO2/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (Ntrap ˜ 2 × 1011 cm-2).

  12. Temperature-independent switching rates for a random telegraph signal in a silicon metal-oxide-semiconductor field-effect transistor at low temperatures

    SciTech Connect

    Scofield, John H.; Borland, Nick; Fleetwood, D. M.

    2000-05-29

    We have observed discrete random telegraph signals (RTSs) in the drain voltages of three, nominally 1.25 {mu}mx1.25 {mu}m, enhancement-mode p-channel metal-oxide-semiconductor transistors operated in strong inversion in their linear regimes with constant drain-current and gate-voltage bias, for temperatures ranging from 4.2 to 300 K. The switching rates for all RTSs observed above 30 K were thermally activated. The switching rate for the only RTS observed below 30 K was thermally activated above 30 K but temperature independent below 10 K. This response is consistent with a crossover from thermal activation to tunneling at low temperatures. Implications are discussed for models of change exchange between the Si and the near-interfacial SiO{sub 2}. (c) 2000 American Institute of Physics.

  13. Impact of SF{sub 6} plasma treatment on performance of TaN-HfO{sub 2}-InP metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Wang Yanzhen; Chen Yenting; Zhao Han; Xue Fei; Zhou Fei; Lee, Jack C.

    2011-01-24

    In this work, the experimental impact of SF{sub 6} plasma treatment on the performance of InP metal-oxide-semiconductor field-effect transistors is presented. S and F are incorporated into atomic layer deposited HfO{sub 2} via postgate SF{sub 6} plasma treatment. The decreased subthreshold swing, gate leakage (I{sub g}), and increased effective channel mobility ({mu}{sub eff}) indicate that better interface and bulk oxide quality have been achieved with SF{sub 6} plasma treatment due to the formation of stronger Hf-F bonds. Drive current (I{sub d}), transconductance (G{sub m}), and effective channel mobility ({mu}{sub eff}) are improved by 22.3%, 35%, and 35%, respectively, compared with those of control devices.

  14. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  15. SiO2/InP Structure Prepared by Direct Photo-Chemical Vapor Deposition Using Deuterium Lamp and Its Applications to Metal-Oxide-Semiconductor Field-Effect Transistor

    NASA Astrophysics Data System (ADS)

    Shei, Shih-Chang; Su, Yan-Kuin; Hwang, Chih-Jen; Yokoyama, Meiso

    1995-02-01

    Silicon dioxide ( SiO2) films have been successfully deposited on indium phosphide (InP) substrate at low temperature and low pressure by direct photo-enhanced chemical vapor deposition (photo-CVD) under irradiation by a deuterium lamp. Silane ( SiH4) and oxygen ( O2) are used as reactant sources. The measurements of Fourier transform infrared (FTIR), Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS) show that the dominant components of the oxide are silicon and oxygen and the film is SiO2. Metal-oxide-semiconductor (MOS) capacitors show sharp interfaces with densities of states in the range of 1.2×1011 cm-2 eV-1. N-channel depletion-mode InP metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated with a transconductance of 63 mS/mm for 2 µ m gate length and an effective channel mobility as high as 1140 cm2 V-1 s-1. High-frequency S-parameter measurements of microwave characteristics for the devices indicate a current-gain cutoff frequency f t=6.3 GHz.

  16. Performance enhancement of n-channel inversion type In{sub x}Ga{sub 1-x}As metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer

    SciTech Connect

    Sonnet, A. M.; Hinkle, C. L.; Jivani, M. N.; Chapman, R. A.; Pollack, G. P.; Wallace, R. M.; Vogel, E. M.

    2008-09-22

    Significant enhancement in metal-oxide-semiconductor field effect transistor (MOSFET) transport characteristics is achieved with In{sub x}Ga{sub 1-x}As (x=0.53, x=0.20) channel material using ex situ plasma enhanced chemical vapor deposited amorphous Si layer. In{sub x}Ga{sub 1-x}As MOSFETs (L=2 {mu}m, V{sub gs}-V{sub t}=2.0 V) with Si interlayer show a maximum drain current of 290 mA/mm (x=0.53) and 2 {mu}A/mm (x=0.20), which are much higher compared to devices without a Si interlayer. However, charge pumping measurements show a lower average interface state density near the intrinsic Fermi level for devices without the silicon interlayer indicating that a reduction in the midgap interface state density is not responsible for the improved transport characteristics.

  17. Anomalous negative bias temperature instability behavior in p-channel metal-oxide-semiconductor field-effect transistors with HfSiON /SiO2 gate stack

    NASA Astrophysics Data System (ADS)

    Chen, Shih-Chang; Chien, Chao-Hsin; Lou, Jen-Chung

    2007-06-01

    In this letter, the authors systematically investigated the behavior of negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with HfSiON /SiO2 gate stack. They found that typical linear extrapolation does not work well for the lifetime extraction at the normal operation conditions since the polarities of the net trapped charge inside the high-κ dielectrics are not the same at lower and higher stress voltage regimes. In other words, as ∣Vg∣<2.5V electron trapping dominated while hole trapping dominated when ∣Vg∣>2.5V. This phenomenon obviously contradicts the essence of the linear prediction in which the same degradation mechanism is assumed through the entire stress voltage range.

  18. Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

    SciTech Connect

    Kao, Tsung-Hsien; Chang, Shoou-Jinn Fang, Yean-Kuen; Huang, Po-Chin; Wu, Chung-Yi; Wu, San-Lein

    2014-08-11

    In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

  19. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    SciTech Connect

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-10-06

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  20. Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

    NASA Technical Reports Server (NTRS)

    Duen Ho, Fat; Macleod, Todd C.

    1998-01-01

    The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFET's drain current. This is different from the model proposed by Chen et. al. and that by Wu.

  1. Depletion-mode Ga2O3 metal-oxide-semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics

    NASA Astrophysics Data System (ADS)

    Higashiwaki, Masataka; Sasaki, Kohei; Kamimura, Takafumi; Hoi Wong, Man; Krishnamurthy, Daivasigamani; Kuramata, Akito; Masui, Takekazu; Yamakoshi, Shigenobu

    2013-09-01

    Single-crystal gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors were fabricated on a semi-insulating β-Ga2O3 (010) substrate. A Sn-doped n-Ga2O3 channel layer was grown by molecular-beam epitaxy. Si-ion implantation doping was performed to source and drain electrode regions for obtaining low-resistance ohmic contacts. An Al2O3 gate dielectric film formed by atomic layer deposition passivated the device surface and significantly reduced gate leakage. The device with a gate length of 2 μm showed effective gate modulation of the drain current with an extremely low off-state drain leakage of less than a few pA/mm, leading to a high drain current on/off ratio of over ten orders of magnitude. A three-terminal off-state breakdown voltage of 370 V was achieved. Stable transistor operation was sustained at temperatures up to 250 °C.

  2. Negative bias-and-temperature stress-assisted activation of oxygen-vacancy hole traps in 4H-silicon carbide metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ettisserry, D. P.; Goldsman, N.; Akturk, A.; Lelis, A. J.

    2015-07-01

    We use hybrid-functional density functional theory-based Charge Transition Levels (CTLs) to study the electrical activity of near-interfacial oxygen vacancies located in the oxide side of 4H-Silicon Carbide (4H-SiC) power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Based on the "amorphousness" of their local atomic environment, oxygen vacancies are shown to introduce their CTLs either within (permanently electrically active) or outside of (electrically inactive) the 4H-SiC bandgap. The "permanently electrically active" centers are likely to cause threshold voltage (Vth) instability at room temperature. On the other hand, we show that the "electrically inactive" defects could be transformed into various "electrically active" configurations under simultaneous application of negative bias and high temperature stresses. Based on this observation, we present a model for plausible oxygen vacancy defects that could be responsible for the recently observed excessive worsening of Vth instability in 4H-SiC power MOSFETs under high temperature-and-gate bias stress. This model could also explain the recent electrically detected magnetic resonance observations in 4H-SiC MOSFETs.

  3. Negative bias-and-temperature stress-assisted activation of oxygen-vacancy hole traps in 4H-silicon carbide metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ettisserry, D. P. E-mail: neil@umd.edu; Goldsman, N. E-mail: neil@umd.edu; Akturk, A.; Lelis, A. J.

    2015-07-28

    We use hybrid-functional density functional theory-based Charge Transition Levels (CTLs) to study the electrical activity of near-interfacial oxygen vacancies located in the oxide side of 4H-Silicon Carbide (4H-SiC) power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Based on the “amorphousness” of their local atomic environment, oxygen vacancies are shown to introduce their CTLs either within (permanently electrically active) or outside of (electrically inactive) the 4H-SiC bandgap. The “permanently electrically active” centers are likely to cause threshold voltage (V{sub th}) instability at room temperature. On the other hand, we show that the “electrically inactive” defects could be transformed into various “electrically active” configurations under simultaneous application of negative bias and high temperature stresses. Based on this observation, we present a model for plausible oxygen vacancy defects that could be responsible for the recently observed excessive worsening of V{sub th} instability in 4H-SiC power MOSFETs under high temperature-and-gate bias stress. This model could also explain the recent electrically detected magnetic resonance observations in 4H-SiC MOSFETs.

  4. Charge Pumping Profiling Technique for the Evaluation of Plasma-Charging-Enhanced Hot-Carrier Effect in Short-N-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Chen, Shang-Jr; Chung, Steve Shao-Shiun; Lin, Horng-Chih

    2002-07-01

    Plasma etching of poly-silicon in a metal-oxide-semiconductor field-effect transistor (MOSFET) during the gate definition process induces edge damage at the gate-drain overlap edge. This edge damage will be further enhanced by the antenna effect and cause a more serious hot-carrier (HC) effect, particularly in short-channel devices. We call this phenomenon the plasma-charging-enhanced HC effect. In this paper, this plasma-charging-enhanced HC effect is evaluated by the charge pumping (CP) profiling technique, in which the enhanced damage at the gate-drain overlap gate oxide region can be identified. A three-phase plasma damage mechanism is then proposed to explain the observed effect. According to experimental results, it was shown that the interface traps generated at the gate-drain overlap edge are mainly attributed to the plasma-charging-enhanced HC effect. These interface traps (Nit) become the dominant mechanism of the drain current (ID) degradation, which increases with a reducing channel length (L). Again, the enhanced HC-effect-induced-degradation will dominate the device reliability under long-term operations.

  5. Performance of GaN Metal-Oxide-Semiconductor Field-Effect Transistor with Regrown n+-Source/Drain on a Selectively Etched GaN

    NASA Astrophysics Data System (ADS)

    Kim, Do-Kywn; Kim, Dong-Seok; Chang, Sung-Jae; Lee, Chang-Ju; Bae, Youngho; Cristoloveanu, Sorin; Lee, Jung-Hee; Hahm, Sung-Ho

    2013-06-01

    We proposed and fabricated normally off GaN MOSFETs with an epitaxially regrown n+ GaN source/drain after a short period of dry etching on a sapphire substrate. The regrown S/D MOSFET after dry etching (MOSFET A) exhibited enhanced performance in terms of current drivability and access resistance compared with the same MOSFET without the surface etching before the regrowth (MOSFET B). While MOSFET A has a saturation drain current of 10 mA/mm at VG = 8 V, a field-effect mobility of 22 cm2 V-1 s-1, and a series resistance RSD of 0.57 kΩ, MOSFET B has 3 mA/mm, 12 cm2 V-1 s-1, and 0.93 kΩ, respectively. The electrical characteristic of MOSFET A was also much more improved than that of MOSFET B at low temperatures. Mobility degradation at low temperatures was related to the effect of impurity scattering caused by crystal defects generated during the metal organic chemical vapor deposition (MOCVD) growth.

  6. Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors

    SciTech Connect

    Shin, H. S.; Yum, J. H.; Johnson, D. W.; Harris, H. R.; Hudnall, Todd W.; Oh, J.; Kirsch, P.; Wang, W.-E.; Bielawski, C. W.; Banerjee, S. K.; Lee, J. C.; Lee, H. D.

    2013-11-25

    In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

  7. High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors by in-situ atomic-layer-deposited HfO2

    NASA Astrophysics Data System (ADS)

    Lin, T. D.; Chang, W. H.; Chu, R. L.; Chang, Y. C.; Chang, Y. H.; Lee, M. Y.; Hong, P. F.; Chen, Min-Cheng; Kwo, J.; Hong, M.

    2013-12-01

    Self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) have been fabricated using the gate dielectrics of in-situ directly atomic-layer-deposited (ALD) HfO2 followed by ALD-Al2O3. There were no surface pretreatments and no interfacial passivation/barrier layers prior to the ALD. TiN/Al2O3 (4 nm)/HfO2 (1 nm)/In0.53Ga0.47As/InP MOS capacitors exhibited well-behaved capacitance-voltage characteristics with true inversion behavior, low leakage current densities of ˜10-8 A/cm2 at ±1 MV/cm, and thermodynamic stability at high temperatures. Al2O3 (3 nm)/HfO2 (1 nm)/In0.53Ga0.47As MOSFETs of 1 μm gate length, with 700 °C-800 °C rapid thermal annealing in source/drain activation, have exhibited high extrinsic drain current (ID) of 1.5 mA/μm, transconductance (Gm) of 0.84 mS/μm, ION/IOFF of ˜104, low sub-threshold swing of 103 mV/decade, and field-effect electron mobility of 1100 cm2/V . s. The devices have also achieved very high intrinsic ID and Gm of 2 mA/μm and 1.2 mS/μm, respectively.

  8. Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Han, Ru; Li, Cong

    2013-02-01

    In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

  9. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    SciTech Connect

    Han, Bin Takamizawa, Hisashi Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  10. Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal-oxide-semiconductor field-effect transistor with low on-state resistance

    NASA Astrophysics Data System (ADS)

    Yu-Ru, Wang; Yi-He, Liu; Zhao-Jiang, Lin; Dong, Fang; Cheng-Zhou, Li; Ming, Qiao; Bo, Zhang

    2016-02-01

    An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer. Project supported by the National Natural Science Foundation of China (Grant No. 61376080), the Natural Science Foundation of Guangdong Province, China (Grant No. 2014A030313736), and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2013J030).

  11. Trade-Off Relationship between Si Recess and Defect Density Formed by Plasma-Induced Damage in Planar Metal-Oxide-Semiconductor Field-Effect Transistors and the Optimization Methodology

    NASA Astrophysics Data System (ADS)

    Eriguchi, Koji; Nakakubo, Yoshinori; Matsuda, Asahiko; Kamei, Masayuki; Takao, Yoshinori; Ono, Kouichi

    2011-08-01

    Physical damage induced by high-energy ion bombardment during plasma processing is characterized from the viewpoint of the relationship between surface-damaged layer (silicon loss) and defect site underneath the surface. Parameters for plasma-induced damage (PID), Si recess depth (dR) and residual (areal) defect density after wet-etch treatment (Ndam), are calculated on the basis of a modified range theory, and the trade-off relationship between dR and Ndam is presented. We also model their effects on device parameters such as off-state leakage (Ioff) and drain saturation current (Ion) of n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Based on the models, we clarify the relationship among plasma process parameters (ion energy and ion flux), dR, Ndam, Ioff, and Ion. Then we propose a methodology optimizing ion energy and ion flux under the constraints defined by device specifications Ioff and Ion, via dR and Ndam. This procedure is regarded as so-called optimization problems. The proposed methodology is applicable to optimizing plasma parameters that minimize degradation of MOSFET performance by PID.

  12. Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal-oxide-semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Taur, Y.; Yu, E. T.

    2002-11-01

    We have directly measured nanoscale electronic features associated with a 120 nm physical gate length p-channel silicon metal-oxide-semiconductor field-effect transistor device structure including n+ superhalo implants using cross-sectional scanning capacitance microscopy (SCM). A dc bias-dependent voltage series of SCM images representing nine bias conditions from 2 to -2 V in 0.5 V steps was obtained. The SCM contrast observed varies with the ac and dc bias applied to the sample and allows delineation of the device features, including the p+ source and drain contacts, p+ source and drain extensions, p+ polycrystalline silicon gate, electrical p-n junction, n-well, and n+ superhalo implants. It is demonstrated that the superhalo implant features are imaged only under specific SCM bias conditions. Detailed analysis of the resulting SCM contrast indicates an apparent channel length of 73±11 nm, and reveals clear asymmetry in the individual lobes of the n+ superhalo implant features.

  13. Oxidation and crystal field effects in uranium

    NASA Astrophysics Data System (ADS)

    Tobin, J. G.; Yu, S.-W.; Booth, C. H.; Tyliszczak, T.; Shuh, D. K.; van der Laan, G.; Sokaras, D.; Nordlund, D.; Weng, T.-C.; Bagus, P. S.

    2015-07-01

    An extensive investigation of oxidation in uranium has been pursued. This includes the utilization of soft x-ray absorption spectroscopy, hard x-ray absorption near-edge structure, resonant (hard) x-ray emission spectroscopy, cluster calculations, and a branching ratio analysis founded on atomic theory. The samples utilized were uranium dioxide (U O2) , uranium trioxide (U O3) , and uranium tetrafluoride (U F4) . A discussion of the role of nonspherical perturbations, i.e., crystal or ligand field effects, will be presented.

  14. Oxidation and crystal field effects in uranium

    SciTech Connect

    Tobin, J. G.; Booth, C. H.; Shuh, D. K.; van der Laan, G.; Sokaras, D.; Weng, T. -C.; Yu, S. W.; Bagus, P. S.; Tyliszczak, T.; Nordlund, D.

    2015-07-06

    An extensive investigation of oxidation in uranium has been pursued. This includes the utilization of soft x-ray absorption spectroscopy, hard x-ray absorption near-edge structure, resonant (hard) x-ray emission spectroscopy, cluster calculations, and a branching ratio analysis founded on atomic theory. The samples utilized were uranium dioxide (UO2), uranium trioxide (UO3), and uranium tetrafluoride (UF4). As a result, a discussion of the role of non-spherical perturbations, i.e., crystal or ligand field effects, will be presented.

  15. Reduction in the interface-states density of metal-oxide-semiconductor field-effect transistors fabricated on high-index Si (114) surfaces by using an external magnetic field

    SciTech Connect

    Molina, J. De La Hidalga, J.; Gutierrez, E.

    2014-08-14

    After fabrication of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices on high-index silicon (114) surfaces, their threshold voltage (Vth) and interface-states density (Dit) characteristics were measured under the influence of an externally applied magnetic field of B = 6 μT at room temperature. The electron flow of the MOSFET's channel presents high anisotropy on Si (114), and this effect is enhanced by using an external magnetic field B, applied parallel to the Si (114) surface but perpendicular to the electron flow direction. This special configuration results in the channel electrons experiencing a Lorentzian force which pushes the electrons closer to the Si (114)-SiO{sub 2} interface and therefore to the special morphology of the Si (114) surface. Interestingly, Dit evaluation of n-type MOSFETs fabricated on Si (114) surfaces shows that the Si (114)-SiO{sub 2} interface is of high quality so that Dit as low as ∼10{sup 10 }cm{sup −2}·eV{sup −1} are obtained for MOSFETs with channels aligned at specific orientations. Additionally, using both a small positive Vds ≤ 100 mV and B = 6 μT, the former Dit is reduced by 35% in MOSFETs whose channels are aligned parallel to row-like nanostructures formed atop Si (114) surfaces (channels having a 90° rotation), whereas Dit is increased by 25% in MOSFETs whose channels are aligned perpendicular to these nanostructures (channels having a 0° rotation). From these results, the special morphology of a high-index Si (114) plane having nanochannels on its surface opens the possibility to reduce the electron-trapping characteristics of MOSFET devices having deep-submicron features and operating at very high frequencies.

  16. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Azzah Bte Suleiman, Sumarlina; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal-oxide-semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel-Poole emission at high electric field. This Frenkel-Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3×1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel-Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley-Read-Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id∝T-0.37 observed for passivated device, in comparison to Id∝T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  17. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal--Oxide--Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Suleiman, Sumarlina Azzah Bte; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal--oxide--semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel--Poole emission at high electric field. This Frenkel--Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3× 1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel--Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley--Read--Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id\\propto T-0.37 observed for passivated device, in comparison to Id\\propto T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  18. EDITORIAL: Oxide semiconductors

    NASA Astrophysics Data System (ADS)

    Kawasaki, M.; Makino, T.

    2005-04-01

    growth of p-type layers, ferromagnetic behaviour in transition-metal doped oxide is also fuelling renewed interest from the spintronic point of view. Since some of the related reports remain controversial, a critical discussion of the magnetic properties of these doped oxides is made by Fukumura et al. Before the observation of electro-luminescence from the ZnO p-n homojunction reported by Tsukazaki et al (2005 Nature Mater. 4 42), the afore-mentioned advantages have been explored and exploited by alternative methods, such as heteroepitaxy in which p-n heterostructures can be obtained by depositing n-type ZnO films on other p-type oxides while still utilizing ZnO as their active layer. Researchers in Hosono's group observed the high-intensity band-edge emission from such heterostructures for the first time (Ohta H et al 2000 Appl. Phys. Lett. 77 475). They have also successfully extended their research fields to the development of a transparent oxide transistor based on homologous compounds, which is reviewed by Kamiya and Hosono in this special issue. As can be seen from these demonstrations, the advantage of oxides is, of course, based on the fact that many elements in the periodic table can form compounds with oxygen. Since the discovery of high-temperature superconductors, these multi-component oxides have exploited the new field known as the science of strongly correlated-electron materials, whose recent progress is reviewed by Inoue. Although the collection of papers included in this special issue covers a good cross-section of the development of oxide semiconductors and correlated-electron oxides to date, this is not meant to be exhaustive. There are a number of unavoidable omissions, such as theoretical studies except for some theoretical predictions on the room-temperature Bose-Einstein condensation of exciton-polaritons found in the article by Chichibu et al. We hope this issue promotes further development of this exciting field. The guest editors would like to

  19. Electrical characteristics of gadolinium gallium oxide/gallium oxide insulators on GaAs and In0.53Ga0.47As in metal-oxide-semiconductor field effect transistors - admittance and subthreshold characteristics

    NASA Astrophysics Data System (ADS)

    Paterson, G. W.; Bentley, S. J.; Holland, M. C.; Thayne, I. G.; Long, A. R.

    2011-09-01

    The admittances and subthreshold characteristics of capacitors and MOSFETs on buried InxGa1-xAs channel wafers with a dielectric stack of Gd0.25Ga0.15O0.6/Ga2O3 deposited on GaAs and In0.53Ga0.47As are reported. Both the GaAs and InGaAs interface samples show admittance characteristics indicative of the presence of defect states within the oxide, in agreement with previously reported data from the same oxides on n+ substrates. The interface state model is applied to the admittance data to extract an apparent interface state density (Dit) that includes interface and oxide states. The Dit profiles are very different and have pronounced effects on the device performance. The device subthreshold swings (SS) at low source-drain voltages are also used to extract an apparent Dit. A simple method is used to estimate the Fermi-level position within the bandgap (Et) at threshold, and the resulting Dit(Et) are found to be in good agreement with the admittance data. The importance of proper interpretation of SS and Dit in general and in GaAs interface devices in particular is emphasized. A model that accounts for the logarithmic sweep rate dependence of the extracted Dit due to the presence of oxide states is reported and used to estimate their density from SS measurements. The implications of the band parameters of an oxide with defect states within it for the comparison of different oxides on the same substrate and the issues around the comparison of results in general are discussed.

  20. Interfacial band configuration and electrical properties of LaAlO{sub 3}/Al{sub 2}O{sub 3}/hydrogenated-diamond metal-oxide-semiconductor field effect transistors

    SciTech Connect

    Liu, J. W.; Liao, M. Y.; Imura, M.; Oosato, H.; Watanabe, E.; Tanaka, A.; Iwai, H.; Koide, Y.

    2013-08-28

    In order to search a gate dielectric with high permittivity on hydrogenated-diamond (H-diamond), LaAlO{sub 3} films with thin Al{sub 2}O{sub 3} buffer layers are fabricated on the H-diamond epilayers by sputtering-deposition (SD) and atomic layer deposition (ALD) techniques, respectively. Interfacial band configuration and electrical properties of the SD-LaAlO{sub 3}/ALD-Al{sub 2}O{sub 3}/H-diamond metal-oxide-semiconductor field effect transistors (MOSFETs) with gate lengths of 10, 20, and 30 μm have been investigated. The valence and conduction band offsets of the SD-LaAlO{sub 3}/ALD-Al{sub 2}O{sub 3} structure are measured by X-ray photoelectron spectroscopy to be 1.1 ± 0.2 and 1.6 ± 0.2 eV, respectively. The valence band discontinuity between H-diamond and LaAlO{sub 3} is evaluated to be 4.0 ± 0.2 eV, showing that the MOS structure acts as the gate which controls a hole carrier density. The leakage current density of the SD-LaAlO{sub 3}/ALD-Al{sub 2}O{sub 3}/H-diamond MOS diode is smaller than 10{sup −8} A cm{sup −2} at gate bias from −4 to 2 V. The capacitance-voltage curve in the depletion mode shows sharp dependence, small flat band voltage, and small hysteresis shift, which implies low positive and trapped charge densities. The MOSFETs show p-type channel and complete normally off characteristics with threshold voltages changing from −3.6 ± 0.1 to −5.0 ± 0.1 V dependent on the gate length. The drain current maximum and the extrinsic transconductance of the MOSFET with gate length of 10 μm are −7.5 mA mm{sup −1} and 2.3 ± 0.1 mS mm{sup −1}, respectively. The enhancement mode SD-LaAlO{sub 3}/ALD-Al{sub 2}O{sub 3}/H-diamond MOSFET is concluded to be suitable for the applications of high power and high frequency electrical devices.

  1. Metal oxide semiconductor structure using oxygen-terminated diamond

    NASA Astrophysics Data System (ADS)

    Chicot, G.; Maréchal, A.; Motte, R.; Muret, P.; Gheeraert, E.; Pernot, J.

    2013-06-01

    Metal-oxide-semiconductor structures with aluminum oxide as insulator and p-type (100) mono-crystalline diamond as semiconductor have been fabricated and investigated by capacitance versus voltage and current versus voltage measurements. The aluminum oxide dielectric was deposited using low temperature atomic layer deposition on an oxygenated diamond surface. The capacitance voltage measurements demonstrate that accumulation, depletion, and deep depletion regimes can be controlled by the bias voltage, opening the route for diamond metal-oxide-semiconductor field effect transistor. A band diagram is proposed and discussed.

  2. High temperature behavior of multi-region direct current current-voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal-oxide-semiconductor field-effect-transistors reliability

    NASA Astrophysics Data System (ADS)

    He, Yandong; Zhang, Ganggang; Zhang, Xing

    2014-01-01

    With the process compatibility with the mainstream standard complementary metal-oxide-semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular for its better tradeoff between breakdown voltage and performance, especially for smart power applications. A multi-region direct current current-voltage (MR-DCIV) technique with spectroscopic features was demonstrated to map the interface state generation in the channel, accumulation and STI drift regions. High temperature behavior of MR-DCIV spectroscopy was analyzed and a physical model was verified. Degradation of STI-based LDMOS transistors under high temperature reverse bias (HTRB) stress is experimentally studied by MR-DCIV spectroscopy. The impact of interface state location on device electrical characteristics was investigated. Our results show that the major contribution to HTRB degradation, in term of the on-resistance degradation, was attributed to interface state generation under STI drift region.

  3. Exploring graphene field effect transistor devices to improve spectral resolution of semiconductor radiation detectors

    SciTech Connect

    Harrison, Richard Karl; Howell, Stephen Wayne; Martin, Jeffrey B.; Hamilton, Allister B.

    2013-12-01

    Graphene, a planar, atomically thin form of carbon, has unique electrical and material properties that could enable new high performance semiconductor devices. Graphene could be of specific interest in the development of room-temperature, high-resolution semiconductor radiation spectrometers. Incorporating graphene into a field-effect transistor architecture could provide an extremely high sensitivity readout mechanism for sensing charge carriers in a semiconductor detector, thus enabling the fabrication of a sensitive radiation sensor. In addition, the field effect transistor architecture allows us to sense only a single charge carrier type, such as electrons. This is an advantage for room-temperature semiconductor radiation detectors, which often suffer from significant hole trapping. Here we report on initial efforts towards device fabrication and proof-of-concept testing. This work investigates the use of graphene transferred onto silicon and silicon carbide, and the response of these fabricated graphene field effect transistor devices to stimuli such as light and alpha radiation.

  4. Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors by a Novel Direct Current Current-Voltage Technique

    NASA Astrophysics Data System (ADS)

    He, Yandong; Zhang, Ganggang

    2012-04-01

    Shallow trench isolation (STI) based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. A novel direct current current-voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum Isub stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

  5. Polyfluorenes as organic semiconductors for polymeric field effect transistors

    NASA Astrophysics Data System (ADS)

    Brennan, David J.; Townsend, Paul H., III; Welsh, Dean M.; Dibbs, Mitchell G.; Shaw, Jeff M.; Miklovich, Jessica L.; Boeke, Robyn B.; Arias, Ana Claudia; Creswell, Lisa; MacKenzie, J. D.; Ramsdale, Catherine; Menon, Anoop; Sirringhaus, Henning

    2003-11-01

    Well-characterized F8T2 polyfluorene (Dow Chemical) has been prepared with weight average molecular weights (Mw) ranging from about 20,000 to 120,000. This semiconducting polymer has been used by Plastic Logic to fabricate arrays of 4,800 thin film transistors (TFTs) with 50 dpi, to be used as backplanes for active matrix displays. In this paper, the effects that molecular weight and thermal treatment have on the electrical characteristics of F8T2-based TFTs are reported. First, transistor performance improves with increasing molecular weight, with maximum values of TFT mobility approaching 1x 10-2 cm2 /V-s. Consistently higher mobilities are obtained when the F8T2 semiconductor makes contact with PEDOT/PSS versus gold electrodes. Alignment of F8T2 on a rubbed polyimide substrate is maintained after quenching, as determined by measurement of the dichroic ratios. Early-stage results on the development of inks based on F8T2 polyfluorene are also reported.

  6. New Material Transistor with Record-High Field-Effect Mobility among Wide-Band-Gap Semiconductors.

    PubMed

    Shih, Cheng Wei; Chin, Albert

    2016-08-01

    At an ultrathin 5 nm, we report a new high-mobility tin oxide (SnO2) metal-oxide-semiconductor field-effect transistor (MOSFET) exhibiting extremely high field-effect mobility values of 279 and 255 cm(2)/V-s at 145 and 205 °C, respectively. These values are the highest reported mobility values among all wide-band-gap semiconductors of GaN, SiC, and metal-oxide MOSFETs, and they also exceed those of silicon devices at the aforementioned elevated temperatures. For the first time among existing semiconductor transistors, a new device physical phenomenon of a higher mobility value was measured at 45-205 °C than at 25 °C, which is due to the lower optical phonon scattering by the large SnO2 phonon energy. Moreover, the high on-current/off-current of 4 × 10(6) and the positive threshold voltage of 0.14 V at 25 °C are significantly better than those of a graphene transistor. This wide-band-gap SnO2 MOSFET exhibits high mobility in a 25-205 °C temperature range, a wide operating voltage of 1.5-20 V, and the ability to form on an amorphous substrate, rendering it an ideal candidate for multifunctional low-power integrated circuit (IC), display, and brain-mimicking three-dimensional IC applications. PMID:27454211

  7. L{sub g} = 100 nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

    SciTech Connect

    Koh, D. E-mail: Taewoo.Kim@sematech.org; Kwon, H. M.; Kim, T.-W. E-mail: Taewoo.Kim@sematech.org; Veksler, D.; Gilmer, D.; Kirsch, P. D.; Kim, D.-H.; Hudnall, Todd W.; Bielawski, Christopher W.; Maszara, W.; Banerjee, S. K.

    2014-04-21

    In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/μm, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7 nm technology node and/or beyond.

  8. Investigation of abnormal negative threshold voltage shift under positive bias stress in input/output n-channel metal-oxide-semiconductor field-effect transistors with TiN/HfO{sub 2} structure using fast I-V measurement

    SciTech Connect

    Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen; Chang, Ting-Chang Lu, Ying-Hsin; Tsai, Jyun-Yu; Liu, Kuan-Ju; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-03-17

    This letter investigates abnormal negative threshold voltage shifts under positive bias stress in input/output (I/O) TiN/HfO{sub 2} n-channel metal-oxide-semiconductor field-effect transistors using fast I-V measurement. This phenomenon is attributed to a reversible charge/discharge effect in pre-existing bulk traps. Moreover, in standard performance devices, threshold-voltage (V{sub t}) shifts positively during fast I-V double sweep measurement. However, in I/O devices, V{sub t} shifts negatively since electrons escape from bulk traps to metal gate rather than channel electrons injecting to bulk traps. Consequently, decreasing pre-existing bulk traps in I/O devices, which can be achieved by adopting Hf{sub x}Zr{sub 1−x}O{sub 2} as gate oxide, can reduce the charge/discharge effect.

  9. All-electric all-semiconductor spin field-effect transistors

    NASA Astrophysics Data System (ADS)

    Chuang, Pojen; Ho, Sheng-Chin; Smith, L. W.; Sfigakis, F.; Pepper, M.; Chen, Chin-Hung; Fan, Ju-Chun; Griffiths, J. P.; Farrer, I.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Chen, Tse-Ming

    2015-01-01

    The spin field-effect transistor envisioned by Datta and Das opens a gateway to spin information processing. Although the coherent manipulation of electron spins in semiconductors is now possible, the realization of a functional spin field-effect transistor for information processing has yet to be achieved, owing to several fundamental challenges such as the low spin-injection efficiency due to resistance mismatch, spin relaxation and the spread of spin precession angles. Alternative spin transistor designs have therefore been proposed, but these differ from the field-effect transistor concept and require the use of optical or magnetic elements, which pose difficulties for incorporation into integrated circuits. Here, we present an all-electric and all-semiconductor spin field-effect transistor in which these obstacles are overcome by using two quantum point contacts as spin injectors and detectors. Distinct engineering architectures of spin-orbit coupling are exploited for the quantum point contacts and the central semiconductor channel to achieve complete control of the electron spins (spin injection, manipulation and detection) in a purely electrical manner. Such a device is compatible with large-scale integration and holds promise for future spintronic devices for information processing.

  10. P-Channel Lateral Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance

    NASA Astrophysics Data System (ADS)

    Liaw, Chorng-Wei; Chang, Ching-Hung; Lin, Ming-Jang; King, Ya-Ching; Hsu, Charles Ching-Hsiang; Lin, Chrong Jung

    2007-07-01

    Many high voltage complementary metal-oxide-semiconductor (HV-CMOS) processes are modified from a standard 5 V CMOS process by adding an N-type heavily doped layer under the P-well of a HV-PMOS drain terminal to isolate a high voltage P-well from a grounded P-substrate. The limitation of breakdown voltage is dominated by P-well concentration and junction depth. For designing a certain breakdown voltage (\\mathit{BV}dss) for a HV-PMOS, the original 5 V CMOS P-well concentration should be decreased, which could degrade 5 V CMOS characteristics, such as NMOS punch through and latch-up immunity. In this study, we demonstrate a novel HV-PMOS based on a split N-type buried layer (NBL), which provides a high \\mathit{BV}dss in a HV-CMOS process. The newly proposed device with NBL split under the P-well of a drain electrode increases \\mathit{BV}dss without degrading specific on-resistance (Ron,sp) and any added process complexity. From this result, P-well concentration could be increased to improve both 5 V NMOS characteristics and HV-PMOS Ron,sp.

  11. Frontier of transparent oxide semiconductors

    NASA Astrophysics Data System (ADS)

    Ohta, Hiromichi; Nomura, Kenji; Hiramatsu, Hidenori; Ueda, Kazushige; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

    2003-12-01

    Recent advancements of transparent oxide semiconductors (TOS) toward new frontiers of "oxide electronics" are reviewed based on our efforts, categorized as "novel functional materials", "heteroepitaxial growth techniques", and "device fabrications". Topics focused in this paper are: (1) highly conductive ITO thin film with atomically flat surface, (2) p-type TOS material ZnRh 2O 4, (3) deep-ultraviolet (DUV) transparent conductive oxide β-Ga 2O 3 thin film, (4) electrochromic oxyfuolide NbO 2F, (5) single-crystalline films of InGaO 3(ZnO) m grown by reactive solid-phase epitaxy, (6) p-type semiconductor LaCuOS/Se epitaxial films capable of emitting UV- and purple-light, (7) p-n homojunction based on bipolar CuInO 2, (8) transparent FET based on single-crystalline InGaO 3(ZnO) 5 films, and (9) UV-light emitting diode based on p-n heterojunction.

  12. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    NASA Astrophysics Data System (ADS)

    Besleaga, C.; Stan, G. E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

    2016-08-01

    The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium-gallium-zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium-gallium-zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  13. Conductivity in transparent oxide semiconductors

    NASA Astrophysics Data System (ADS)

    King, P. D. C.; Veal, T. D.

    2011-08-01

    Despite an extensive research effort for over 60 years, an understanding of the origins of conductivity in wide band gap transparent conducting oxide (TCO) semiconductors remains elusive. While TCOs have already found widespread use in device applications requiring a transparent contact, there are currently enormous efforts to (i) increase the conductivity of existing materials, (ii) identify suitable alternatives, and (iii) attempt to gain semiconductor-engineering levels of control over their carrier density, essential for the incorporation of TCOs into a new generation of multifunctional transparent electronic devices. These efforts, however, are dependent on a microscopic identification of the defects and impurities leading to the high unintentional carrier densities present in these materials. Here, we review recent developments towards such an understanding. While oxygen vacancies are commonly assumed to be the source of the conductivity, there is increasing evidence that this is not a sufficient mechanism to explain the total measured carrier concentrations. In fact, many studies suggest that oxygen vacancies are deep, rather than shallow, donors, and their abundance in as-grown material is also debated. We discuss other potential contributions to the conductivity in TCOs, including other native defects, their complexes, and in particular hydrogen impurities. Convincing theoretical and experimental evidence is presented for the donor nature of hydrogen across a range of TCO materials, and while its stability and the role of interstitial versus substitutional species are still somewhat open questions, it is one of the leading contenders for yielding unintentional conductivity in TCOs. We also review recent work indicating that the surfaces of TCOs can support very high carrier densities, opposite to the case for conventional semiconductors. In thin-film materials/devices and, in particular, nanostructures, the surface can have a large impact on the total

  14. All-Graphene Planar Self-Switching MISFEDs, Metal-Insulator-Semiconductor Field-Effect Diodes

    PubMed Central

    Al-Dirini, Feras; Hossain, Faruque M.; Nirmalathas, Ampalavanapillai; Skafidas, Efstratios

    2014-01-01

    Graphene normally behaves as a semimetal because it lacks a bandgap, but when it is patterned into nanoribbons a bandgap can be introduced. By varying the width of these nanoribbons this band gap can be tuned from semiconducting to metallic. This property allows metallic and semiconducting regions within a single Graphene monolayer, which can be used in realising two-dimensional (2D) planar Metal-Insulator-Semiconductor field effect devices. Based on this concept, we present a new class of nano-scale planar devices named Graphene Self-Switching MISFEDs (Metal-Insulator-Semiconductor Field-Effect Diodes), in which Graphene is used as the metal and the semiconductor concurrently. The presented devices exhibit excellent current-voltage characteristics while occupying an ultra-small area with sub-10 nm dimensions and an ultimate thinness of a single atom. Quantum mechanical simulation results, based on the Extended Huckel method and Nonequilibrium Green's Function Formalism, show that a Graphene Self-Switching MISFED with a channel as short as 5 nm can achieve forward-to-reverse current rectification ratios exceeding 5000. PMID:24496307

  15. Method for manufacturing compound semiconductor field-effect transistors with improved DC and high frequency performance

    DOEpatents

    Zolper, John C.; Sherwin, Marc E.; Baca, Albert G.

    2000-01-01

    A method for making compound semiconductor devices including the use of a p-type dopant is disclosed wherein the dopant is co-implanted with an n-type donor species at the time the n-channel is formed and a single anneal at moderate temperature is then performed. Also disclosed are devices manufactured using the method. In the preferred embodiment n-MESFETs and other similar field effect transistor devices are manufactured using C ions co-implanted with Si atoms in GaAs to form an n-channel. C exhibits a unique characteristic in the context of the invention in that it exhibits a low activation efficiency (typically, 50% or less) as a p-type dopant, and consequently, it acts to sharpen the Si n-channel by compensating Si donors in the region of the Si-channel tail, but does not contribute substantially to the acceptor concentration in the buried p region. As a result, the invention provides for improved field effect semiconductor and related devices with enhancement of both DC and high-frequency performance.

  16. Stability of In-Ga-Zn-O metal-semiconductor field-effect-transistors under bias, illumination, and temperature stress

    NASA Astrophysics Data System (ADS)

    Dang, Giang T.; Kawaharamura, Toshiyuki; Furuta, Mamoru; Saxena, Saurabh; Allen, Martin W.

    2015-10-01

    The stability of metal-semiconductor field-effect-transistors (MESFETs) with silver oxide Schottky gates on In-Ga-Zn-O (IGZO) channels, grown by mist chemical-vapor-deposition, was examined under different combinations of positive and negative bias, illumination, and temperature stress. These devices were remarkably stable, even under the most severe condition of negative-bias-illumination-temperature-stress (NBITS), where the threshold voltage shift after 10 h NBITS was only +0.12 V and was mainly attributed to a decrease in the carrier density of the channel. The stability of these IGZO MESFETs is associated with the use of a conducting Schottky gate that significantly reduces charge trapping at the gate-channel interface.

  17. Performance Comparison of InAs, InSb, and GaSb n-Channel Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors in the Ballistic Transport Limit

    NASA Astrophysics Data System (ADS)

    Shimoida, Kenta; Tsuchiya, Hideaki; Kamakura, Yoshinari; Mori, Nobuya; Ogawa, Matsuto

    2013-03-01

    Ballistic performances of InAs, InSb, and GaSb nanowire field-effect transistors (NWFETs) were theoretically investigated. We found that InAs and InSb NWFETs exhibit similar device performances due to 1D band structure effects. Furthermore, although these In-based NWFETs suffer from the density-of-states (DOS) bottleneck, a lower power switching is expected. On the other hand, GaSb NWs have multiple energy subbands at conduction band minima, as a result of the projection of L-valleys which thus improves the DOS. In particular, a <110>-oriented GaSb NW has an improved DOS and a high electron velocity simultaneously, and thus, it could be a strong competitor to In-based NWFETs.

  18. Controlled deposition or organic semiconductor single crystals and its application in field-effect transistors

    NASA Astrophysics Data System (ADS)

    Liu, Shuhong

    The search for low-cost, large area, flexible devices has led to a remarkable increase in the research and development of organic semiconductors. Single-crystal organic field-effect transistors (OFETs) are ideal device structures for studying fundamental science associated with charge transport in organic materials and have demonstrated high mobility and outstanding electrical characteristics. For example, an exceptionally high carrier mobility of 20 cm2/Vs has been demonstrated for rubrene single crystal field effect transistors. However, it remains a technical challenge to integrate single-crystal devices into practical electronic applications. A key difficulty is that organic single-crystal devices are usually fabricated one device at a time by handpicking a single crystal and placing it onto the device substrate. This makes it impossible to mass-produce at high density with reasonable throughput. Therefore, there is a great need for a high-throughput method for depositing large arrays of organic semiconductor single crystals directly onto device structures. In this dissertation, I develop several approaches towards realizing this goal. The first approach is a solution-processing technique, which relies on solvent wetting and de-wetting on substrates with patterned wettability to selectively direct the deposition or removal of organic crystals. The assembly of different organic crystals over centimeter-squared areas on Au, SiO 2 and flexible plastic substrates is demonstrated. By designing line features on the substrate, alignment of needle-like crystals is also achieved. As a demonstration of the potential application of this approach, arrays of organic single crystal FETs are fabricated by patterning organic single crystals directly onto and between transistor source and drain electrodes. Besides organic single crystals, this self-assembly strategy is also applicable for patterning other objects such as metallic nanowires. In the second technique, organic

  19. Surface enhanced Raman spectroscopic studies of the metal-semiconductor interface in organic field effect transistors

    NASA Astrophysics Data System (ADS)

    Adil, Danish; Guha, Suchi

    2012-02-01

    The performance of organic field-effect transistors (FETs) largely depends on the nature of interfaces of dissimilar materials. Metal-semiconductor interfaces, in particular, play a critical role in the charge injection process. Here, Raman spectroscopy is used to investigate the nature of the Au-semiconductor interface in pentacene based FETs. A large enhancement in the Raman intensity (SERS) is observed from the pentacene film under the Au layer. The enhancement is evidence of a nano-scale roughness in the morphology of the interface, which is further confirmed by electron microscopy images. The morphology of the interface is investigated by SERS as a function of the pentacene layer thickness and the Au layer thickness. The Raman spectra are found to be extremely sensitive in detecting small changes in the morphology of the interface in the sub-nanometer range. Changes in the Raman spectra are further tracked after biasing and ageing the devices. Evolution of these Raman spectra is correlated with degradation in device performance. Finally, FETs based on other donor-acceptor semiconductors are probed by Raman scattering and contrasted with those of the pentacene-based devices.

  20. Admittance and subthreshold characteristics of atomic-layer-deposition Al2O3 on In0.53Ga0.47As in surface and buried channel flatband metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Paterson, G. W.; Bentley, S. J.; Holland, M. C.; Thayne, I. G.; Ahn, J.; Long, R. D.; McIntyre, P. C.; Long, A. R.

    2012-05-01

    The admittances and subthreshold characteristics of capacitors and MOSFETs on buried and surface In0.53Ga0.47As channel flatband wafers, with a dielectric of Al2O3 deposited on In0.53Ga0.47As, are reported. The admittance characteristics of both wafers indicate the presence of defect states within the oxide, in common with a number of other oxides on In0.53Ga0.47As. The two wafers studied have not been hydrogen annealed, but do show some similar features to FGA treated oxides on n+ substrates. We discuss how the possible presence of residual hydroxyl ions in as-grown Al2O3 may explain these similarities and also account for many of the changes in the properties of FGA treated n+ samples. The issues around the comparison of subthreshold swing (SS) results and the impact of transistor design parameters on the energy portion of the defect state distribution affecting efficient device switching are discussed. The interface state model is applied to low source-drain voltage SS data to extract an effective interface state density (Dit) that includes interface and oxide traps. The logarithmic gate voltage sweep rate dependence of the SS Dit is used to extract an oxide trap density (Dot) and a simple method is used to estimate the Fermi level position within the band gap, Et. The Al2O3 Dit(Et) and Dot(Et) distributions are found to be similar to each other and to the results of our analysis of Gd0.25Ga0.15O0.6/Ga2O3 and HfO2/Al2O3 on In0.53Ga0.47As, adding weight to the suggestion of there being a common defect state distribution and perhaps a common cause of defects states for a number of oxides on In0.53Ga0.47As.

  1. Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling

    NASA Astrophysics Data System (ADS)

    Van Den Daele, W.; Malaquin, C.; Baumel, N.; Kononchuk, O.; Cristoloveanu, S.

    2013-10-01

    This paper revisits and adapts of the pseudo-MOSFET (Ψ-MOSFET) characterization technique for advanced fully depleted silicon on insulator (FDSOI) wafers. We review the current challenges for standard Ψ-MOSFET set-up on ultra-thin body (12 nm) over ultra-thin buried oxide (25 nm BOX) and propose a novel set-up enabling the technique on FDSOI structures. This novel configuration embeds 4 probes with large tip radius (100-200 μm) and low pressure to avoid oxide damage. Compared with previous 4-point probe measurements, we introduce a simplified and faster methodology together with an adapted Y-function. The models for parameters extraction are revisited and calibrated through systematic measurements of SOI wafers with variable film thickness. We propose an in-depth analysis of the FDSOI structure through comparison of experimental data, TCAD (Technology Computed Aided Design) simulations, and analytical modeling. TCAD simulations are used to unify previously reported thickness-dependent analytical models by analyzing the BOX/substrate potential and the electrical field in ultrathin films. Our updated analytical models are used to explain the results and to extract correct electrical parameters such as low-field electron and hole mobility, subthreshold slope, and film/BOX interface traps density.

  2. A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

    2004-01-01

    The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

  3. Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

    SciTech Connect

    Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei; Wu, Yung-Hsien

    2015-02-02

    ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.

  4. Recent progress on ZnO-based metal-semiconductor field-effect transistors and their application in transparent integrated circuits.

    PubMed

    Frenzel, Heiko; Lajn, Alexander; von Wenckstern, Holger; Lorenz, Michael; Schein, Friedrich; Zhang, Zhipeng; Grundmann, Marius

    2010-12-14

    Metal-semiconductor field-effect transistors (MESFETs) are widely known from opaque high-speed GaAs or high-power SiC and GaN technology. For the emerging field of transparent electronics, only metal-insulator-semiconductor field-effect transistors (MISFETs) were considered so far. This article reviews the progress of high-performance MESFETs in oxide electronics and reflects the recent advances of this technique towards transparent MESFET circuitry. We discuss design prospects as well as limitations regarding device performance, reliability and stability. The presented ZnO-based MESFETs and inverters have superior properties compared to MISFETs, i.e., high channel mobilities and on/off-ratios, high gain, and low uncertainty level at comparatively low operating voltages. This makes them a promising approach for future low-cost transparent electronics. PMID:20878625

  5. Systematic structural and chemical characterization of the transition layer at the interface of NO-annealed 4H-SiC/SiO2 metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Taillon, Joshua A.; Hyuk Yang, Joon; Ahyi, Claude A.; Rozen, John; Williams, John R.; Feldman, Leonard C.; Zheleva, Tsvetanka S.; Lelis, Aivars J.; Salamanca-Riba, Lourdes G.

    2013-01-01

    We present a systematic characterization of the transition layer at the 4H-SiC/SiO2 interface as a function of nitric oxide (NO) post-annealing time, using high-resolution transmission electron microscopy for structural characterization and spatially resolved electron energy-loss spectroscopy for chemical analysis. We propose a systematic method for determining transition layer width by measuring the monotonic chemical shift of the Si-L2,3 edge across the interface, and compare its efficacy to traditional measures from the literature, revealing the proposed method to be most reliable. A gradual shift in the Si-L2,3 edge onset energy suggests mixed Si-C/Si-O bonding in the transition layer. We confirm an inverse relationship between NO-anneal time and transition layer width, which correlates with improved channel mobility, enhanced N density at the interface, and decreased interface trap density. No excess C was noted in the interfacial region.

  6. Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

    NASA Astrophysics Data System (ADS)

    Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

    2015-09-01

    We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10-2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost.

  7. Interface effects on the characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

    NASA Astrophysics Data System (ADS)

    Sun, Jing; Zheng, Xue Jun; Cao, Juan; Li, Wen

    2011-09-01

    The interface effects on the electrical characteristics of metal-ferroelectric-insulator- semiconductor field-effect transistor (MFIS-FET) are studied using an improved model in which the expressions for interface and the mobility model are incorporated into Lue model. The interface layer between the ferroelectric and the electrode and the SiO2 layer between the insulator and the semiconductor have been investigated. Capacitance-gate voltage (C-VG) and drain current-gate voltage (ID-VGS) characteristics are modeled with fixed interface layer and SiO2 layer thicknesses and show good agreement with the experiments, verifying the validity of the improved model and the existence of the interface in the transistor. The characteristics, such as C-VG, ID-VGS and drain current-drain voltage (ID-VDS), are modeled respectively with various interface layer and SiO2 layer thicknesses. The thicker the interface layer and SiO2 layer are, the worse the transistor characteristics become. Similar characteristics can be observed at the specific thickness of the two layers, indicating that both interface layer and SiO2 layer should be considered when the characteristics of MFIS-FETs degrade. In addition, the type of the interfaces can be distinguished by comparing the capacitance in the accumulation region. It is expected that this work can offer some useful guidance to the design and performance improvement of MFIS structure devices.

  8. Vacuum-and-solvent-free fabrication of organic semiconductor layers for field-effect transistors

    PubMed Central

    Matsushima, Toshinori; Sandanayaka, Atula S. D.; Esaki, Yu; Adachi, Chihaya

    2015-01-01

    We demonstrate that cold and hot isostatic pressing (CIP and HIP) is a novel, alternative method for organic semiconductor layer fabrication, where organic powder is compressed into a layer shape directly on a substrate with 200 MPa pressure. Spatial gaps between powder particles and the other particles, substrates, or electrodes are crushed after CIP and HIP, making it possible to operate organic field-effect transistors (OFETs) containing the compressed powder as the semiconductor. The CIP-compressed powder of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) had a hole mobility of (1.6 ± 0.4) × 10–2 cm2/Vs. HIP of C8-BTBT powder increased the hole mobility to an amorphous silicon-like value (0.22 ± 0.07 cm2/Vs) because of the growth of the C8-BTBT crystallites and the improved continuity between the powder particles. The vacuum and solution processes are not involved in our CIP and HIP techniques, offering a possibility of manufacturing OFETs at low cost. PMID:26416434

  9. Room-temperature terahertz detectors based on semiconductor nanowire field-effect transistors.

    PubMed

    Vitiello, Miriam S; Coquillat, Dominique; Viti, Leonardo; Ercolani, Daniele; Teppe, Frederic; Pitanti, Alessandro; Beltram, Fabio; Sorba, Lucia; Knap, Wojciech; Tredicucci, Alessandro

    2012-01-11

    The growth of semiconductor nanowires (NWs) has recently opened new paths to silicon integration of device families such as light-emitting diodes, high-efficiency photovoltaics, or high-responsivity photodetectors. It is also offering a wealth of new approaches for the development of a future generation of nanoelectronic devices. Here we demonstrate that semiconductor nanowires can also be used as building blocks for the realization of high-sensitivity terahertz detectors based on a 1D field-effect transistor configuration. In order to take advantage of the low effective mass and high mobilities achievable in III-V compounds, we have used InAs nanowires, grown by vapor-phase epitaxy, and properly doped with selenium to control the charge density and to optimize source-drain and contact resistance. The detection mechanism exploits the nonlinearity of the transfer characteristics: the terahertz radiation field is fed at the gate-source electrodes with wide band antennas, and the rectified signal is then read at the output in the form of a DC drain voltage. Significant responsivity values (>1 V/W) at 0.3 THz have been obtained with noise equivalent powers (NEP) < 2 × 10(-9) W/(Hz)(1/2) at room temperature. The large existing margins for technology improvements, the scalability to higher frequencies, and the possibility of realizing multipixel arrays, make these devices highly competitive as a future solution for terahertz detection. PMID:22149118

  10. Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

    NASA Astrophysics Data System (ADS)

    Ukah, Ndubuisi Benjamin

    This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

  11. Compound semiconductor field-effect transistors with improved dc and high frequency performance

    SciTech Connect

    Zolper, J.C.; Sherwin, M.E.; Baca, A.G.

    1995-12-31

    A method for making compound semiconductor devices including the use of a p-type dopant is disclosed wherein the dopant is co-implanted with an n-type donor species at the time the n-channel is deposited. Also disclosed are devices manufactured using the method. In the preferred embodiment n-MESFETs and other similar field effect transistor devices are manufactured using C ions implanted with Si atoms in GaAs to form an n-channel. C exhibits a unique characteristic in the context of the invention in that it exhibits a low activation efficiency (typically, 50% or less) as a p-type dopant, and consequently, it acts to sharpen the Si n-channel by compensating Si donors in the region the Si-channel tail, but does not contribute substantially to the acceptor concentration in the region of the buried p-implant. As a result, the invention provides for improved field effect transistor devices with enhancement of both DC and high-frequency performance.

  12. Electrospun Polyaniline/Polyethylene Oxide Nanofiber Field Effect Transistor

    NASA Technical Reports Server (NTRS)

    Pinto, N. J.; Johnson, A. T.; MacDiarmid, A. G.; Mueller, C. H.; Theofylaktos, N.; Robinson, D. C.; Miranda, F. A.

    2003-01-01

    We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.

  13. Solution-Processed Donor-Acceptor Polymer Nanowire Network Semiconductors For High-Performance Field-Effect Transistors

    PubMed Central

    Lei, Yanlian; Deng, Ping; Li, Jun; Lin, Ming; Zhu, Furong; Ng, Tsz-Wai; Lee, Chun-Sing; Ong, Beng S.

    2016-01-01

    Organic field-effect transistors (OFETs) represent a low-cost transistor technology for creating next-generation large-area, flexible and ultra-low-cost electronics. Conjugated electron donor-acceptor (D-A) polymers have surfaced as ideal channel semiconductor candidates for OFETs. However, high-molecular weight (MW) D-A polymer semiconductors, which offer high field-effect mobility, generally suffer from processing complications due to limited solubility. Conversely, the readily soluble, low-MW D-A polymers give low mobility. We report herein a facile solution process which transformed a lower-MW, low-mobility diketopyrrolopyrrole-dithienylthieno[3,2-b]thiophene (I) into a high crystalline order and high-mobility semiconductor for OFETs applications. The process involved solution fabrication of a channel semiconductor film from a lower-MW (I) and polystyrene blends. With the help of cooperative shifting motion of polystyrene chain segments, (I) readily self-assembled and crystallized out in the polystyrene matrix as an interpenetrating, nanowire semiconductor network, providing significantly enhanced mobility (over 8 cm2V−1s−1), on/off ratio (107), and other desirable field-effect properties that meet impactful OFET application requirements. PMID:27091315

  14. Solution-Processed Donor-Acceptor Polymer Nanowire Network Semiconductors For High-Performance Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Lei, Yanlian; Deng, Ping; Li, Jun; Lin, Ming; Zhu, Furong; Ng, Tsz-Wai; Lee, Chun-Sing; Ong, Beng S.

    2016-04-01

    Organic field-effect transistors (OFETs) represent a low-cost transistor technology for creating next-generation large-area, flexible and ultra-low-cost electronics. Conjugated electron donor-acceptor (D-A) polymers have surfaced as ideal channel semiconductor candidates for OFETs. However, high-molecular weight (MW) D-A polymer semiconductors, which offer high field-effect mobility, generally suffer from processing complications due to limited solubility. Conversely, the readily soluble, low-MW D-A polymers give low mobility. We report herein a facile solution process which transformed a lower-MW, low-mobility diketopyrrolopyrrole-dithienylthieno[3,2-b]thiophene (I) into a high crystalline order and high-mobility semiconductor for OFETs applications. The process involved solution fabrication of a channel semiconductor film from a lower-MW (I) and polystyrene blends. With the help of cooperative shifting motion of polystyrene chain segments, (I) readily self-assembled and crystallized out in the polystyrene matrix as an interpenetrating, nanowire semiconductor network, providing significantly enhanced mobility (over 8 cm2V‑1s‑1), on/off ratio (107), and other desirable field-effect properties that meet impactful OFET application requirements.

  15. Solution-Processed Donor-Acceptor Polymer Nanowire Network Semiconductors For High-Performance Field-Effect Transistors.

    PubMed

    Lei, Yanlian; Deng, Ping; Li, Jun; Lin, Ming; Zhu, Furong; Ng, Tsz-Wai; Lee, Chun-Sing; Ong, Beng S

    2016-01-01

    Organic field-effect transistors (OFETs) represent a low-cost transistor technology for creating next-generation large-area, flexible and ultra-low-cost electronics. Conjugated electron donor-acceptor (D-A) polymers have surfaced as ideal channel semiconductor candidates for OFETs. However, high-molecular weight (MW) D-A polymer semiconductors, which offer high field-effect mobility, generally suffer from processing complications due to limited solubility. Conversely, the readily soluble, low-MW D-A polymers give low mobility. We report herein a facile solution process which transformed a lower-MW, low-mobility diketopyrrolopyrrole-dithienylthieno[3,2-b]thiophene (I) into a high crystalline order and high-mobility semiconductor for OFETs applications. The process involved solution fabrication of a channel semiconductor film from a lower-MW (I) and polystyrene blends. With the help of cooperative shifting motion of polystyrene chain segments, (I) readily self-assembled and crystallized out in the polystyrene matrix as an interpenetrating, nanowire semiconductor network, providing significantly enhanced mobility (over 8 cm(2)V(-1)s(-1)), on/off ratio (10(7)), and other desirable field-effect properties that meet impactful OFET application requirements. PMID:27091315

  16. Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Ho, Fat Duen

    1999-01-01

    The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

  17. Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

    2005-01-01

    Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

  18. Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

    2006-01-01

    Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

  19. Photoionization spectroscopy of traps in GaN metal-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Klein, P. B.; Binari, S. C.; Freitas, J. A.; Wickenden, A. E.

    2000-09-01

    Measurements of the spectral and intensity dependences of the optically-induced reversal of current collapse in a GaN metal-semiconductor field-effect transistor (MESFET) have been compared to calculated results. The model assumes a net transfer of charge from the conducting channel to trapping states in the high-resistivity region of the device. The reversal, a light-induced increase in the trap-limited drain current, results from the photoionization of trapped carriers and their return to the channel under the influence of the built-in electric field associated with the trapped charge distribution. For a MESFET in which two distinct trapping centers have been spectrally resolved, the experimentally measured dependence upon light intensity was fitted using this model. The two traps were found to have very different photoionization cross-sections but comparable concentrations (4×1011 cm-2 and 6×1011 cm-2), suggesting that both traps contribute comparably to the observed current collapse.

  20. Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor

    SciTech Connect

    Liu, J. W.; Liao, M. Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

    2014-08-25

    A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO{sub 3} layer and a thin atomic-layer-deposited Al{sub 2}O{sub 3} buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be −40.7 mA·mm{sup −1}, 13.2 ± 0.1 mS·mm{sup −1}, and −3.1 ± 0.1 V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to −10.0 V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages.

  1. A Pt-Ti-O gate Si-metal-insulator-semiconductor field-effect transistor hydrogen gas sensor

    NASA Astrophysics Data System (ADS)

    Usagawa, Toshiyuki; Kikuchi, Yota

    2010-10-01

    A hydrogen gas sensor based on platinum-titanium-oxygen (Pt-Ti-O) gate silicon-metal-insulator-semiconductor field-effect transistors (Si-MISFETs) was developed. The sensor has a unique gate structure composed of titanium and oxygen accumulated around platinum grains on top of a novel mixed layer of nanocrystalline TiOx and superheavily oxygen-doped amorphous titanium formed on SiO2/Si substrates. The FET hydrogen sensor shows high reliability and high sensing amplitude (Δ Vg) defined by the magnitude of the threshold voltage shift. Δ Vg is well fitted by a linear function of the logarithm of air-diluted hydrogen concentration C (ppm), i.e., Δ Vg(V) =0.355 log C(ppm ) -0.610 , between 100 ppm and 1%. This high gradient coefficient of Δ Vg for the wide sensing range demonstrates that the sensor is suitable for most hydrogen-safety-monitoring sensor systems. The Pt-Ti-O structures of the sensor are typically realized by annealing Pt (15 nm)/Ti (5 nm)-gate Si-metal-oxide-semiconductor structures in air at 400 °C for 2 h. The Pt-Ti-O gate MIS structures were analyzed by transmission electron microscope (TEM), x-ray diffraction, Auger electron spectroscopy, and TEM energy dispersive x-ray spectroscopy. From the viewpoint of practical sensing applications, hydrogen postannealing of the Pt-Ti-O gate Si-MISFETs is necessary to reduce the residual sensing amplitudes with long tailing profiles.

  2. Influence of Temperature Variation on Field Effect Transistor Properties Using a Solution-Processed Liquid Crystalline Semiconductor, 8TNAT8.

    PubMed

    Monobe, Hirosato; Kimoto, Masaomi; Shimizu, Yo

    2016-04-01

    In this study, we used a liquid crystalline (LC) semiconductor, 8TNAT8, solution (e.g., 0.1 wt% in toluene) for forming an organic semiconductor layer by solution casting method, and fabricated bottom-gate/bottom-contact type field effect transistors (FETs). These LC semiconductors show FET characteristic properties and have high carrier mobility of 0.01 cm2 V-1 s-1. We have investigated the surface morphology and the influence of temperature variation on LC FET properties across the phase transition from crystal to mesophase of a LC semiconductor, 8TNAT8. In the most cases, FET mobility was irreversibly decreased after. temperature heat stress above the melting point of 8TNAT8, owing to the morphological change of LC layer. PMID:27451617

  3. Automated semiconductor diffusion and oxidation facility

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A semiconductor diffusion and oxidation facility (totally automated) was developed. Wafers arrived on an air track, automatically loaded into a furnace tube, processed, returned to track, and sent on to the next process. The entire process was controlled by a computer.

  4. Compound semiconductor oxide antireflection coatings

    NASA Astrophysics Data System (ADS)

    Knopp, K. J.; Mirin, R. P.; Bertness, K. A.; Silverman, K. L.; Christensen, D. H.

    2000-05-01

    We report the development of high quality, broad-bandwidth, antireflection (AR) coatings using the low index provided by wet thermally oxidized Al0.98Ga0.02As. We address the design criteria, fabrication, and characterizations of AR coatings composed of surface and buried oxide layers on GaAs. We show, using native-oxide dispersion data, that surface oxide coatings can be designed to offer a nearly zero minimum of reflectance and a reflectance of <1% over bandwidths as large as 500 nm. Surface coatings having a reflectance minimum of 0.4% and a reflectance of <1% over >250 nm have been experimentally demonstrated at a design wavelength of 1 micrometer. Additionally, buried oxide coatings can be designed with an AlxGa1-xAs matching layer of any composition to exactly match the admittance of any substrate with effective index between 2.5 and 3.5. We have demonstrated buried oxide coatings, also designed for 1 micrometer, having a reflectance minimum of 0.4% and a reflectance of <1% over 21 nm. The calculated optical scattering loss from measured roughness data indicates that reflectance minima as low as 10-4 % are ultimately achievable with native-oxide antireflection coatings.

  5. Investigating Organic Field Effect Transistors with Reduced Graphene Oxide Electrodes of Different Reduction Efficiency

    NASA Astrophysics Data System (ADS)

    Kang, Narae; Khondaker, Saiful I.

    2014-03-01

    Organic field-effect transistors (OFETs) have received much attention owing to their flexibility, transparency, and low-cost of fabrication. One of the major limiting factors in fabricating high-performance OFET is the large injection barrier at metal electrodes/organic semiconductor interface, which results in low charge injection from metal electrodes to organic semiconductor. Graphene has been suggested as an alternative electrode material due to its high work function, extraordinary electronic properties and strong π- π interaction with organic molecule; all of which can reduce the injection barrier at the electrode/organic interface. In particular, due to its solubility, large scale production, and its chemical functionality, reduced graphene oxide (RGO) has been introduced as a promising electrode for OFETs. Its tunability of electrical and optical properties can make RGO a highly desired electrode material because the work function match is essential for better charge injection at electrode/organic interface. In this talk, we will discuss the fabrication of OFETs with RGO of different reduction efficiency as an electrode material. We will also present the electrical transport properties fabricated devices.

  6. Semiconductor-oxide heterostructured nanowires using postgrowth oxidation.

    PubMed

    Wallentin, Jesper; Ek, Martin; Vainorious, Neimantas; Mergenthaler, Kilian; Samuelson, Lars; Pistol, Mats-Erik; Reine Wallenberg, L; Borgström, Magnus T

    2013-01-01

    Semiconductor-oxide heterointerfaces have several electron volts high-charge carrier potential barriers, which may enable devices utilizing quantum confinement at room temperature. While a single heterointerface is easily formed by oxide deposition on a crystalline semiconductor, as in MOS transistors, the amorphous structure of most oxides inhibits epitaxy of a second semiconductor layer. Here, we overcome this limitation by separating epitaxy from oxidation, using postgrowth oxidation of AlP segments to create axial and core-shell semiconductor-oxide heterostructured nanowires. Complete epitaxial AlP-InP nanowire structures were first grown in an oxygen-free environment. Subsequent exposure to air converted the AlP segments into amorphous aluminum oxide segments, leaving isolated InP segments in an oxide matrix. InP quantum dots formed on the nanowire sidewalls exhibit room temperature photoluminescence with small line widths (down to 15 meV) and high intensity. This optical performance, together with the control of heterostructure segment length, diameter, and position, opens up for optoelectrical applications at room temperature. PMID:24195687

  7. Study of Ferromagnetic and Field Effect Properties of Zinc Oxide Thin Films

    NASA Astrophysics Data System (ADS)

    Xia, Daxue

    Spintronics (spin transport electronics), in which both spm and charge of carriers are utilized for information processing, is perceived to be a candidate to extend and possibly to become the next-generation electronics. Its advantages include nonvolatility (data retention without electrical power), lower energy consumption, faster processing speed, and higher integration densities in comparison with the current semiconductor devices relying solely on electron charge. To realize a spin-field effect transistor, two respects are prerequisite. On the one hand, the mechanism of ferromagnetism should be addressed before one could prepare magnetic semiconductor films in a controllable way. On the other hand, excellent field effect properties should be sought through a convenient and low-cost strategy for manufacturing future nano-scale spintronic devices. This thesis is comprised of two parts. Firstly, it deals with the synthesis, characterization, and magnetism of transition-metal-doped or un-doped zinc oxide (ZnO) thin films. Secondly, it focuses on the field effect properties of solution processable ZnO thin films, which are not only of great interest for current charge-carrier based thin film transistors, but also of fundamental importance in future spin-based transistors. A facile spin-coating technique has been developed to fabricate ZnO thin films. Even without magnetic element doping, the film is found to show room temperature ferromagnetism. A broad series of advanced microscopic and spectroscopic techniques are utilized to characterize the thin films properties. Oxygen vacancy defects are tentatively attributed to the observed ferromagnetism. Following the similar method, Ga doped or Ga, Co co-doped ZnO thin films are prepared. The ferromagnetism is enhanced with Ga doping, providing more carriers. It is discovered that room temperature ferromagnetism can exist in both highly conductive regime and the less conductive or near insulating regime. Transition metal

  8. Finite size and intrinsic field effect on the polar-active properties of the ferroelectric-semiconductor heterostructures

    SciTech Connect

    Morozovska, A. N.; Eliseev, E. A.; Svechnikov, S. V.; Shur, V.Y.; Borisevich, Albina Y; Maksymovych, Petro; Kalinin, Sergei V

    2010-01-01

    Using Landau-Ginzburg-Devonshire approach we calculated the equilibrium distributions of electric field, polarization and space charge in the ferroelectric-semiconductor heterostructures containing proper or incipient ferroelectric thin films. The role of the polarization gradient and intrinsic surface energy, interface dipoles and free charges on polarization dynamics are specifically explored. The intrinsic field effects, which originated at the ferroelectric-semiconductor interface, lead to the surface band bending and result into the formation of depletion space-charge layer near the semiconductor surface. During the local polarization reversal (caused by the electric field of the nanosized tip of the Scanning Probe Microscope) the thickness and charge of the interface layer drastically changes, in particular the sign of the screening carriers is determined by the polarization direction. Obtained analytical solutions could be extended to analyze polarization-mediated electronic transport.

  9. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    SciTech Connect

    Liang, Shibo; Zhang, Zhiyong Si, Jia; Zhong, Donglai; Peng, Lian-Mao

    2014-08-11

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  10. Theory aided design and analysis of dielectric and semiconductor components for organic field-effect transistors

    NASA Astrophysics Data System (ADS)

    Dibenedetto, Sara Arlene

    Perfluoroacyl/acyl-derivatized quaterthiophens are developed and synthesized. The frontier molecular orbital energies of these compounds are studied by optical spectroscopy and electrochemistry while solid-state/film properties are investigated by thermal analysis, x-ray diffraction, and scanning electron microscopy. Organic thin film transistors (OTFTs) performance parameters are discussed in terms of the interplay between semiconductor molecular energetics and film morphologies/microstructures. The majority charge carrier type and mobility exhibit a strong correlation with the regiochemistry of perfluoroarene incorporation. In quaterthiophene-based semiconductors, carbonyl-functionalization allows tuning of the majority carrier type from p-type to ambipolar and to n-type. In situ conversion of a p-type semiconducting film to n-type film is also demonstrated. The design of chemical and film microstructural alternative hybrid organic-inorganic gate dielectrics is described using the classic Clausius-Mossotti relation. The Maxwell-Wagner effective medium model is used to compute the effective dielectric permittivity of two types of dielectrics self-assembled nanodielectrics (SANDs) and crosslinked polymer blends (CPBs). In these calculations showing good agreement between theory and experiment, it is found that greater capacitances should be achievable with mixed composites than with layered composites. With this insight, a series of mixed metal oxide-polyolefin nanocomposites is synthesized via in-situ olefin polymerization using the single-site metallocene catalysts. By integrating organic and inorganic constituents, the resulting hybrid material exhibit high permittivity (from the inorganic inclusions) and high breakdown strength, mechanical flexibility, and facile processability (from the polymer matrices). In order to better optimize the capacitance and leakage current of hybrid organic-inorganic dielectrics, the capacitance, leakage current and OFET gate

  11. Method of physical vapor deposition of metal oxides on semiconductors

    DOEpatents

    Norton, David P.

    2001-01-01

    A process for growing a metal oxide thin film upon a semiconductor surface with a physical vapor deposition technique in a high-vacuum environment and a structure formed with the process involves the steps of heating the semiconductor surface and introducing hydrogen gas into the high-vacuum environment to develop conditions at the semiconductor surface which are favorable for growing the desired metal oxide upon the semiconductor surface yet is unfavorable for the formation of any native oxides upon the semiconductor. More specifically, the temperature of the semiconductor surface and the ratio of hydrogen partial pressure to water pressure within the vacuum environment are high enough to render the formation of native oxides on the semiconductor surface thermodynamically unstable yet are not so high that the formation of the desired metal oxide on the semiconductor surface is thermodynamically unstable. Having established these conditions, constituent atoms of the metal oxide to be deposited upon the semiconductor surface are directed toward the surface of the semiconductor by a physical vapor deposition technique so that the atoms come to rest upon the semiconductor surface as a thin film of metal oxide with no native oxide at the semiconductor surface/thin film interface. An example of a structure formed by this method includes an epitaxial thin film of (001)-oriented CeO.sub.2 overlying a substrate of (001) Ge.

  12. Metal oxide semiconductors for solar energy harvesting

    NASA Astrophysics Data System (ADS)

    Thimsen, Elijah James

    The correlation between energy consumption and human development illustrates the importance of this societal resource. We will consume more energy in the future. In light of issues with the status quo, such as climate change, long-term supply and security, solar energy is an attractive source. It is plentiful, virtually inexhaustible, and can provide more than enough energy to power society. However, the issue with producing electricity and fuels from solar energy is that it is expensive, primarily from the materials (silicon) used in building the cells. Metal oxide semiconductors are an attractive class of materials that are extremely low cost and can be produced at the scale needed to meet widespread demand. An industrially attractive thin film synthesis process based on aerosol deposition was developed that relies on self-assembly to afford rational control over critical materials parameters such as film morphology and nanostructure. The film morphology and nanostructure were found to have dramatic effects on the performance of TiO2-based photovoltaic dye-sensitized solar cells. Taking a cue from nature, to overcome the spatial and temporal mismatch between the supply of sunlight and demand for energy consumption, it is desirable to produce solar fuels such as hydrogen from photoelectrochemical water splitting. The source of water is important---seawater is attractive. The fundamental reaction mechanism for TiO2-based cells is discussed in the context of seawater splitting. There are two primary issues with producing hydrogen by photoelectrochemical water splitting using metal-oxide semiconductors: visible light activity and spontaneous activity. To address the light absorption issue, a combined theory-experiment approach was taken to understand the fundamental role of chemical composition in determining the visible light absorption properties of mixed metal-oxide semiconductors. To address the spontaneous activity issue, self-biasing all oxide p/n bulk

  13. Standard CMOS Fabrication of a Sensitive Fully Depleted Electrolyte-Insulator-Semiconductor Field Effect Transistor for Biosensor Applications

    PubMed Central

    Shalev, Gil; Cohen, Ariel; Doron, Amihood; Machauf, Andrew; Horesh, Moran; Virobnik, Udi; Ullien, Daniela; Levy, Ilan

    2009-01-01

    Microfabricated semiconductor devices are becoming increasingly relevant for detection of biological and chemical components. The integration of active biological materials together with sensitive transducers offers the possibility of generating highly sensitive, specific, selective and reliable biosensors. This paper presents the fabrication of a sensitive, fully depleted (FD), electrolyte-insulator-semiconductor field-effect transistor (EISFET) made with a silicon-on-insulator (SOI) wafer of a thin 10-30 nm active SOI layer. Initial results are presented for device operation in solutions and for bio-sensing. Here we report the first step towards a high volume manufacturing of a CMOS-based biosensor that will enable various types of applications including medical and environmental sensing. PMID:22408530

  14. High-performance GaAs metal-insulator-semiconductor field-effect transistors enabled by self-assembled nanodielectrics

    NASA Astrophysics Data System (ADS)

    Lin, H. C.; Ye, P. D.; Xuan, Y.; Lu, G.; Facchetti, A.; Marks, T. J.

    2006-10-01

    High-performance GaAs metal-insulator-semiconductor field-effect-transistors (MISFETs) fabricated with very thin self-assembled organic nanodielectrics (SANDs), deposited from solution at room temperature, are demonstrated. A submicron gate-length depletion-mode n-channel GaAs MISFET with SAND thicknesses ranging from 5.5to16.5nm exhibit a gate leakage current density <10-5A/cm2 at a gate bias smaller than 3V, a maximum drain current of 370mA/mm at a forward gate bias of 2V, and a maximum intrinsic transconductance of 170mS/mm. The importance of appropriate GaAs surface chemistry treatments on SAND/GaAs interface properties is also presented. Application of SANDs to III-V compound semiconductors affords more opportunities to manipulate the complex III-V surface chemistry with broad materials options.

  15. Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor.

    PubMed

    Nomura, Kenji; Ohta, Hiromichi; Ueda, Kazushige; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

    2003-05-23

    We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO3(ZnO)5, as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of approximately 106 and a field-effect mobility of approximately 80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics. PMID:12764192

  16. Interface chemistry between complex oxides and semiconductors: where chemistry and physics meet

    NASA Astrophysics Data System (ADS)

    Marchiori, Chiara

    2010-03-01

    Even though heavily based on semiconductors, microelectronics CMOS technology would not exist without the integration of thin oxide films which enable the exploitation of the semiconductor properties. Indeed, working principle of the metal-oxide-semiconductor field-effect transistor, the main building block of such a technology, is the modulation of charges at the oxide/semiconductor interface. The quality of this interface is of fundamental importance for device performance. For over four decades, SiO2 was the gate dielectric of choice and device scaling meant improving performance while lowering production costs. However, as scaling is approaching fundamental limits, direct tunneling across the dielectric becomes unacceptable. At this point, the integration of more complex and higher dielectric constant oxides - ``high-K dielectrics''- with Si or even more complex semiconductors (Ge, III-V) is the key enabler of performance gain. I will review critical issues related to the oxide/semiconductor interfaces, starting with SiO2/Si. Then, I will discuss how the level of complexity increases with the introduction of high-K dielectrics and other semiconductors in the stack. Among the issues to be addressed to fabricate high-performance devices, I will discuss the role played by: 1) interfacial chemistry and thermodynamical stability, 2) band alignment and surface band bending, 3) presence of defects at the interface and in the oxide bulk, 4) evolution of the gate stack properties upon post-deposition treatments. The impact of these parameters on electrical performance of devices will be discussed in detail. Finally, epitaxial oxide on Si will be explored as a promising approach for ultimate EOT scaling and the parameters governing the epitaxial growth of complex crystalline oxides on Si will be addressed. I will show that the development performed in this area might enable the integration of epitaxial oxides for monolithic integration, paving the way to technological

  17. Enhanced mobility in organic field-effect transistors due to semiconductor/dielectric interface control and very thin single crystal

    NASA Astrophysics Data System (ADS)

    Dong, Ji; Yu, Peng; Atika Arabi, Syeda; Wang, Jiawei; He, Jun; Jiang, Chao

    2016-07-01

    A perfect organic crystal while keeping high quality semiconductor/dielectric interface with minimal defects and disorder is crucial for the realization of high performance organic single crystal field-effect transistors (OSCFETs). However, in most reported OSCFET devices, the crystal transfer processes is extensively used. Therefore, the semiconductor/dielectric interface is inevitably damaged. Carrier traps and scattering centers are brought into the conduction channel, so that the intrinsic high mobility of OSCFET devices is entirely disguised. Here, very thin pentacene single crystal is grown directly on bare SiO2 by developing a ‘seed-controlled’ pentacene single crystal method. The interface quality is controlled by an in situ fabrication of OSCFETs. The interface is kept intact without any transfer process. Furthermore, we quantitatively analyze the influence of crystal thickness on device performance. With a pristine interface and very thin crystal, we have achieved the highest mobility: 5.7 cm2 V‑1 s‑1—more than twice the highest ever reported pentacene OSCFET mobility on bare SiO2. This study may provide a universal route for the use of small organic molecules to achieve high performance in lamellar single crystal field-effect devices.

  18. Time-resolved spin-dependent processes in magnetic field effects in organic semiconductors

    NASA Astrophysics Data System (ADS)

    Peng, Qiming; Li, Xianjie; Li, Feng

    2012-12-01

    We investigated the time-resolved magnetic field effects (MFEs) in tri-(8-hydroxyquinoline)-aluminum (Alq3) based organic light-emitting diodes (OLEDs) through the transient electroluminescence (EL) method. The values of magneto-electroluminescence (MEL) decrease with the time, and the decreasing slope is proportional to the driving voltage. Specifically, negative MELs are seen when the driving voltage is high enough (V > 11 V). We propose a model to elucidate the spin-dependent processes and theoretically simulate the time-resolved MELs. In particular, this dynamic analysis of time-resolved MELs reveals that the intersystem crossing between singlet and triplet electron-hole pairs and the triplet-triplet annihilation are responsible for the time-resolved MELs at the beginning and enduring periods of the pulse, respectively.

  19. Dielectric interface-dependent spatial charge distribution in ambipolar polymer semiconductors embedded in dual-gate field-effect transistors

    NASA Astrophysics Data System (ADS)

    Lee, Jiyoul; Roelofs, W. S. Christian; Janssen, Rene A. J.; Gelinck, Gerwin H.

    2016-07-01

    The spatial charge distribution in diketopyrrolopyrrole-containing ambipolar polymeric semiconductors embedded in dual-gate field-effect transistors (DGFETs) was investigated. The DGFETs have identical active channel layers but two different channel/gate interfaces, with a CYTOP™ organic dielectric layer for the top-gate and an octadecyltrichlorosilane (ODTS) self-assembled monolayer-treated inorganic SiO2 dielectric for the bottom-gate, respectively. Temperature-dependent transfer measurements of the DGFETs were conducted to examine the charge transport at each interface. By fitting the temperature-dependent measurement results to the modified Vissenberg-Matters model, it can be inferred that the top-channel interfacing with the fluorinated organic dielectric layers has confined charge transport to two-dimensions, whereas the bottom-channel interfacing with the ODTS-treated SiO2 dielectric layers has three-dimensional charge transport.

  20. A top-gate GaN nanowire metal-semiconductor field effect transistor with improved channel electrostatic control

    NASA Astrophysics Data System (ADS)

    Gačević, Ž.; López-Romero, D.; Juan Mangas, T.; Calleja, E.

    2016-01-01

    A uniformly n-type doped GaN:Si nanowire (NW), with a diameter of d = 90 nm and a length of 1.2 μm, is processed into a metal-semiconductor field effect transistor (MESFET) with a semi-cylindrical top Ti/Au Schottky gate. The FET is in a normally-ON mode, with the threshold at -0.7 V and transconductance of gm ˜ 2 μS (the transconductance normalized with NW diameter gm/d > 22 mS/mm). It enters the saturation mode at VDS ˜ 4.5 V, with the maximum measured drain current IDS = 5.0 μA and the current density exceeding JDS > 78 kA/cm2.

  1. RF Performance of Diamond Metel-Semiconductor Field-Effect Transistor at Elevated Temperatures and Analysis of its Equivalent Circuit

    NASA Astrophysics Data System (ADS)

    Ye, Haitao; Kasu, Makoto; Ueda, Kenji; Yamauchi, Yoshiharu; Maeda, Narihiko; Sasaki, Satoshi; Makimoto, Toshiki

    2006-04-01

    Temperature dependent DC and RF characteristics of p-type diamond metal-semiconductor field-effect transistors (MESFETs) on hydrogen-terminated surfaces are investigated. The device is thermally stable up to 100 °C, because it does not deteriorate at all at higher temperatures. Temperature coefficients of transconductance (gm), drain conductance (gds), gate-source capacitance (Cgs), gate-drain capacitance (Cgd), cut-off frequency ( fT), and maximum drain current (Ids) were obtained from small-signal equivalent circuit analysis. The cut-off frequency ( fT) is almost totally independent of temperature. Intrinsic gm, gds, and Cgs decrease with increasing temperature. Cgd is almost totally independent of temperature. The threshold voltage shifts to the negative side with increasing temperature. We propose a band model of an Al-gate contact/H-terminated diamond to explain the temperature dependence of these components.

  2. De-embedding parasitic elements of GaN nanowire metal semiconductor field effect transistors by use of microwave measurements

    NASA Astrophysics Data System (ADS)

    Gu, Dazhen; Wallis, T. M.; Blanchard, P.; Lim, Sang-Hyun; Imtiaz, A.; Bertness, K. A.; Sanford, N. A.; Kabos, P.

    2011-05-01

    We present a de-embedding roadmap for extracting parasitic elements of a nanowire (NW) metal semiconductor field effect transistor (MESFET) from full two-port scattering-parameter measurements in 0.1-25 GHz range. The NW MESFET is integrated in a microwave coplanar waveguide structure. A conventional MESFET circuit model is modified to include capacitors of small value that is non-negligible in NW devices. We follow a step-by-step removal of external elements and an iteration search for optimized model data. The fitted model indicates good agreement with experimental data. This letter reflects a significant step toward full circuit modeling of NW MESFETs under normal operating conditions.

  3. Electron Transport Behavior on Gate Length Scaling in Sub-50 nm GaAs Metal Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Han, Jaeheon

    2011-12-01

    Short channel GaAs Metal Semiconductor Field Effect Transistors (MESFETs) have been fabricated with gate length to 20 nm, in order to examine the characteristics of sub-50 nm MESFET scaling. Here the rise in the measured transconductance is mainly attributed to electron velocity overshoot. For gate lengths below 40 nm, however, the transconductance drops suddenly. The behavior of velocity overshoot and its degradation is investigated and simulated by using a transport model based on the retarded Langevin equation (RLE). This indicates the existence of a minimum acceleration length needed for the carriers to reach the overshoot velocity. The argument shows that the source resistance must be included as an internal element, or appropriate boundary condition, of relative importance in any model where the gate length is comparable to the inelastic mean free path of the carriers.

  4. C-band superconductor/semiconductor hybrid field-effect transistor amplifier on a LaAlO3 substrate

    NASA Technical Reports Server (NTRS)

    Nahra, J. J.; Bhasin, K. B.; Toncich, S. S.; Subramanyam, G.; Kapoor, V. J.

    1992-01-01

    A single-stage C-band superconductor/semiconductor hybrid field-effect transistor amplifier was designed, fabricated, and tested at 77 K. The large area (1 inch x 0.5 inches) high temperature superconducting Tl-Ba-Ca-Cu-O (TBCCO) thin film was rf magnetron sputtered onto a LaAlO3 substrate. The film had a transition temperature of about 92 K after it was patterned and etched. The amplifier showed a gain of 6 dB and a 3 dB bandwidth of 100 MHz centered at 7.9 GHz. An identical gold amplifier circuit was tested at 77 K, and these results are compared with those from the hybrid amplifier.

  5. Optically enhanced oxidation of III-V compound semiconductors

    NASA Astrophysics Data System (ADS)

    Fukuda, Mitsuo; Takahei, Kenichiro

    1985-01-01

    Oxidation of III-V compound semiconductor (110) cleaved surfaces under light irradiation is studied. The light irradiation enhanced the reaction rate of oxidation but the relationship between oxide growth and oxidation time under logarithmic law scarcely changed within this experimental range. The oxidation trend observed under light irradiation is similar to that of thermal oxidation for GaP, GaAs, InP, InAs, InGaAs, and InGaAsP. Semiconductors having As as the V element tend to be easily oxidized, while those of the above mentioned six kinds of materials having Ga as the III element are quickly oxidized in their initial stage. Ternary and quaternary compound semiconductors have less tendency to be oxidized compared to their constituent binary materials. off

  6. Characterization of silicon carbide metal oxide semiconductor capacitors

    NASA Astrophysics Data System (ADS)

    Marinella, Matthew J.

    Only a few years after the invention of the transistor, William Shockley considered silicon carbide (SiC) an excellent material for high temperature semiconductor devices. Over a half century later, SiC technology is nearly mature enough that it may be considered for use in commercial electronic devices. Furthermore, since SiC has the ability to grow thermal silicon dioxide, significant research has been directed toward the creation of a commercial SiC metal oxide semiconductor field effect transistor (MOSFET). However, a number of significant hurdles still must be overcome before SiC devices can become commercially competitive, including the relatively high cost and low quality of materials. Another significant problem is the lack of understanding of factors which limit the minority carrier lifetime. The primary purpose of this work was to use the pulsed metal oxide semiconductor capacitor (MOS-C) technique to measure generation lifetime in SiC materials. It was found that many nonidealities corrupt the results obtained by this technique. One very interesting nonideality was negative bias temperature instability (NBTI), which has also been widely studied by the silicon industry in recent years. Methods to understand and minimize the effect of these nonidealities were developed. Furthermore, these methods allowed for further study of the oxide properties, such as leakage current. Even after accounting for nonidealities, generation lifetimes showed several peculiarities, such as a variation of as much as a factor of 1000 within a square cm area. In addition, the ratio of generation to recombination lifetime is less than unity, which is not predicted by classic theory, nor typically observed in silicon devices. Possible explanations are put forth to explain these observations. In addition, to further investigate these abnormalities, Schottky diodes were fabricated and characterized. When applied to the SiC MOS capacitor, the pulsed MOS-C technique involves

  7. Optical investigations of nanostructured oxides and semiconductors

    NASA Astrophysics Data System (ADS)

    Irvin, Patrick Richard

    This work is motivated by the prospect of building a quantum computer: a device that would allow physicists to explore quantum mechanics more deeply, and allow everyone else to keep their credit card numbers safe on the Internet. In this thesis we explore two classes of materials that are relevant to a proposed quantum computer architecture: oxides and semiconductors. Systems with a ferroelectric to paraelectric transition in the vicinity of room temperature are useful for devices. We investigate strained-SrTiO 3, which is ferroelectric at room-temperature, and a composite material of (Ba,Sr)TiO3 and MgO. We present optical techniques to measure electron spin dynamics with GHz dynamical bandwidth, transform-limited spectral selectivity, and phase-sensitive detection. We demonstrate this technique by measuring GHz-spin precession in n-GaAs. We also describe our efforts to optically probe InAs/GaAs and GaAs/AlGaAs quantum dots. Nanoscale devices with photonic properties have been the subject of intense research over the past decade. Potential nanophotonic applications include communications, polarization-sensitive detectors, and solar power generation. Here we show photosensitivity of a nanoscale detector written at the interface between two oxides.

  8. Wide band gap ferromagnetic semiconductors and oxides

    NASA Astrophysics Data System (ADS)

    Pearton, S. J.; Abernathy, C. R.; Overberg, M. E.; Thaler, G. T.; Norton, D. P.; Theodoropoulou, N.; Hebard, A. F.; Park, Y. D.; Ren, F.; Kim, J.; Boatner, L. A.

    2003-01-01

    Recent advances in the theory and experimental realization of ferromagnetic semiconductors give hope that a new generation of microelectronic devices based on the spin degree of freedom of the electron can be developed. This review focuses primarily on promising candidate materials (such as GaN, GaP and ZnO) in which there is already a technology base and a fairly good understanding of the basic electrical and optical properties. The introduction of Mn into these and other materials under the right conditions is found to produce ferromagnetism near or above room temperature. There are a number of other potential dopant ions that could be employed (such as Fe, Ni, Co, Cr) as suggested by theory [see, for example, Sato and Katayama-Yoshida, Jpn. J. Appl. Phys., Part 2 39, L555 (2000)]. Growth of these ferromagnetic materials by thin film techniques, such as molecular beam epitaxy or pulsed laser deposition, provides excellent control of the dopant concentration and the ability to grow single-phase layers. The mechanism for the observed magnetic behavior is complex and appears to depend on a number of factors, including Mn-Mn spacing, and carrier density and type. For example, in a simple Ruderman-Kittel-Kasuya-Yosida carrier-mediated exchange mechanism, the free-carrier/Mn ion interaction can be either ferromagnetic or antiferromagnetic depending on the separation of the Mn ions. Potential applications for ferromagnetic semiconductors and oxides include electrically controlled magnetic sensors and actuators, high-density ultralow-power memory and logic, spin-polarized light emitters for optical encoding, advanced optical switches and modulators and devices with integrated magnetic, electronic and optical functionality.

  9. Field-induced activation of metal oxide semiconductor for low temperature flexible transparent electronic device applications

    NASA Astrophysics Data System (ADS)

    Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony; Haglund, Amada; Ward, Thomas Zac; Mandrus, David; Rack, Philip

    Amorphous metal-oxide semiconductors have been extensively studied as an active channel material in thin film transistors due to their high carrier mobility, and excellent large-area uniformity. Here, we report the athermal activation of amorphous indium gallium zinc oxide semiconductor channels by an electric field-induced oxygen migration via gating through an ionic liquid. Using field-induced activation, a transparent flexible thin film transistor is demonstrated on a polyamide substrate with transistor characteristics having a current ON-OFF ratio exceeding 108, and saturation field effect mobility of 8.32 cm2/(V.s) without a post-deposition thermal treatment. This study demonstrates the potential of field-induced activation as an athermal alternative to traditional post-deposition thermal annealing for metal oxide electronic devices suitable for transparent and flexible polymer substrates. Materials Science and Technology Division, ORBL, Oak Ridge, TN 37831, USA.

  10. Semiconductor neutron detectors using depleted uranium oxide

    NASA Astrophysics Data System (ADS)

    Kruschwitz, Craig A.; Mukhopadhyay, Sanjoy; Schwellenbach, David; Meek, Thomas; Shaver, Brandon; Cunningham, Taylor; Auxier, Jerrad Philip

    2014-09-01

    This paper reports on recent attempts to develop and test a new type of solid-state neutron detector fabricated from uranium compounds. It has been known for many years that uranium oxide (UO2), triuranium octoxide (U3O8) and other uranium compounds exhibit semiconducting characteristics with a broad range of electrical properties. We seek to exploit these characteristics to make a direct-conversion semiconductor neutron detector. In such a device a neutron interacts with a uranium nucleus, inducing fission. The fission products deposit energy-producing, detectable electron-hole pairs. The high energy released in the fission reaction indicates that noise discrimination in such a device has the potential to be excellent. Schottky devices were fabricated using a chemical deposition coating technique to deposit UO2 layers a few microns thick on a sapphire substrate. Schottky devices have also been made using a single crystal from UO2 samples approximately 500 microns thick. Neutron sensitivity simulations have been performed using GEANT4. Neutron sensitivity for the Schottky devices was tested experimentally using a 252Cf source.

  11. Nanoscale Metal Oxide Semiconductors for Gas Sensing

    NASA Technical Reports Server (NTRS)

    Hunter, Gary W.; Evans, Laura; Xu, Jennifer C.; VanderWal, Randy L.; Berger, Gordon M.; Kulis, Michael J.

    2011-01-01

    A report describes the fabrication and testing of nanoscale metal oxide semiconductors (MOSs) for gas and chemical sensing. This document examines the relationship between processing approaches and resulting sensor behavior. This is a core question related to a range of applications of nanotechnology and a number of different synthesis methods are discussed: thermal evaporation- condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed, providing a processing overview to developers of nanotechnology- based systems. The results of a significant amount of testing and comparison are also described. A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. The TECsynthesized single-crystal nanowires offer uniform crystal surfaces, resistance to sintering, and their synthesis may be done apart from the substrate. The TECproduced nanowire response is very low, even at the operating temperature of 200 C. In contrast, the electrospun polycrystalline nanofiber response is high, suggesting that junction potentials are superior to a continuous surface depletion layer as a transduction mechanism for chemisorption. Using a catalyst deposited upon the surface in the form of nanoparticles yields dramatic gains in sensitivity for both nanostructured, one-dimensional forms. For the nanowire materials, the response magnitude and response rate uniformly increase with increasing operating temperature. Such changes are interpreted in terms of accelerated surface diffusional processes, yielding greater access to chemisorbed oxygen species and faster dissociative chemisorption, respectively. Regardless of operating temperature, sensitivity of the nanofibers is a factor of 10 to 100 greater than that of nanowires with the same catalyst for the same test condition. In summary, nanostructure appears critical to governing the reactivity, as measured by electrical

  12. Use of nonpolar BaHfO3 gate oxide for field effect on the high mobility BaSnO3

    NASA Astrophysics Data System (ADS)

    Park, Chulkwon; Kim, Useong; Kim, Young Mo; Ju, Chanjong; Char, Kookrin

    2015-03-01

    Recently, BaSnO3 (BSO) has attracted attentions as a transparent conducting oxide and/or a transparent oxide semiconductor due to its novel properties: the excellent oxygen stability even at high temperature and the high electrical mobility at room temperature. We fabricated field effect transistors using La-doped BSO as the semiconducting channel on undoped BSO buffer layers on SrTiO3 substrates. A non-polar perovskite BaHfO3 was used as the gate insulator, and 4% La-doped BSO as the source, the drain, and the gate electrodes grown by pulsed laser deposition. We have measured the optical and the dielectric properties of the epitaxial BaHfO3 gate oxide layer, namely the optical band gap, the dielectric constant, and the breakdown field. Using such BaHfO3 gate oxide, we observed carrier modulation in the active layer by field effect. In this presentation, we will report on the performance of such field effect transistors: the output and the transfer characteristics, the field effect mobility, the Ion/Ioff ratio, and the subthreshold swing.

  13. Scalability of Schottky barrier metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Jang, Moongyu

    2016-05-01

    In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are estimated as 1.5 × 1013 traps/cm2, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by N2 annealing. Based on the diode characteristics, various sizes of erbium-silicided/platinum-silicided n/p-type SB-MOSFETs are manufactured and analyzed. The manufactured SB-MOSFETs show enhanced drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are comparable with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

  14. Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform

    SciTech Connect

    Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Hussain, Muhammad M.; Aljedaani, Abdulrahman B.

    2015-10-26

    Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal–oxide–semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

  15. CdSe Nanowire-Based Flexible Devices: Schottky Diodes, Metal-Semiconductor Field-Effect Transistors, and Inverters.

    PubMed

    Jin, Weifeng; Zhang, Kun; Gao, Zhiwei; Li, Yanping; Yao, Li; Wang, Yilun; Dai, Lun

    2015-06-24

    Novel CdSe nanowire (NW)-based flexible devices, including Schottky diodes, metal-semiconductor field-effect transistors (MESFETs), and inverters, have been fabricated and investigated. The turn-on voltage of a typical Schottky diode is about 0.7 V, and the rectification ratio is larger than 1 × 10(7). The threshold voltage, on/off current ratio, subthreshold swing, and peak transconductance of a typical MESFET are about -0.3 V, 4 × 10(5), 78 mV/dec, and 2.7 μS, respectively. The inverter, constructed with two MESFETs, exhibits clear inverting behavior with the gain to be about 28, 34, and 38, at the supply voltages (V(DD)) of 3, 5, and 7 V, respectively. The inverter also shows good dynamic behavior. The rising and falling times of the output signals are about 0.18 and 0.09 ms, respectively, under 1000 Hz square wave signals input. The performances of the flexible devices are stable and reliable under different bending conditions. Our work demonstrates these flexible NW-based Schottky diodes, MESFETs, and inverters are promising candidate components for future portable transparent nanoelectronic devices. PMID:26061530

  16. Pt–Ti–O gate silicon–metal–insulator–semiconductor field-effect transistor hydrogen gas sensors in harsh environments

    NASA Astrophysics Data System (ADS)

    Usagawa, Toshiyuki; Ueda, Kazuhiro; Nambu, Akira; Yoneyama, Akio; Kikuchi, Yota; Watanabe, Atsushi

    2016-06-01

    The influence of radiation damages to developed hydrogen gas sensor chips from γ-rays (60Co) and/or X-rays (synchrotron radiation) is manageably avoided for sensor operations even at extremely high integral doses such as 1.8 and/or 18 MGy. Platinum–titanium–oxygen (Pt–Ti–O) gate silicon–metal–insulator–semiconductor field-effect transistor (Si-MISFET) hydrogen gas sensors can work stably as hydrogen sensors up to about 270 °C and also show environmental hardness as follows: When nitrogen-diluted 10-ppm hexamethyldisiloxane (HMDS) was exposed to the sensor FETs for 40 min at a working temperature of 115 °C, large sensing amplitude (ΔV g) changed little within repetition errors before and after HMDS exposures. The variations of ΔV g among relative humidity of 20 and 80% are very small within ±4.4% around 50% under 40 °C atmosphere. The Pt–Ti–O sensors have been found to show large ΔV g of 624.4 mV with σΔV g of 7.27 mV for nine times repeated measurements under nitrogen-diluted 1.0%-hydrogen gas, which are nearly the same values of 654.5 mV with σΔV g of 3.77 mV under air-diluted 1.0%-hydrogen gas.

  17. Effect of charge on the ferroelectric field effect in strongly correlated oxides

    NASA Astrophysics Data System (ADS)

    Chen, Xuegang; Xiao, Zhiyong; Zhang, Xiaozhe; Zhang, Le; Zhao, Weiwei; Xu, Xiaoshan; Hong, Xia

    We present a systematic study of the effect of charge on the ferroelectric field effect modulation of various strongly correlated oxide materials. We have fabricated high quality epitaxial heterostructures composed of a ferroelectric Pb(Zr,Ti)O3 (PZT) gate and a correlated oxide channel, including Sm0.5Nd0.5NiO3 (SNNO), La0.7Sr0.3MnO3 (LSMO), SNNO/LSMO bilayers, and NiCo2O4 (NCO). The Hall effect measurements reveal a carrier density of ~4 holes/u.c. (0.4 cm2V-1s-1) for SNNO to ~2 holes/u.c. (27 cm2V-1s-1) for NCO. We find the magnitude of the field effect is closely related to both the intrinsic carrier density and carrier mobility of the channel material. For devices employing the SNNO/LSMO bilayer channel, we believe the charge transfer between the two correlated oxides play an important role in the observed resistance modulation. The screening capacitor of the channel materials and the interfacial defect states also have significant impact on the retention characteristics of the field effect. Our study reveals the critical role of charge in determining the interfacial coupling between ferroelectric and magnetic oxides, and has important implications in developing ferroelectric-controlled Mott memory devices.

  18. A Low-Leakage Epitaxial High-κ Gate Oxide for Germanium Metal-Oxide-Semiconductor Devices.

    PubMed

    Hu, Chengqing; McDaniel, Martin D; Jiang, Aiting; Posadas, Agham; Demkov, Alexander A; Ekerdt, John G; Yu, Edward T

    2016-03-01

    Germanium (Ge)-based metal-oxide-semiconductor field-effect transistors are a promising candidate for high performance, low power electronics at the 7 nm technology node and beyond. However, the availability of high quality gate oxide/Ge interfaces that provide low leakage current density and equivalent oxide thickness (EOT), robust scalability, and acceptable interface state density (Dit) has emerged as one of the most challenging hurdles in the development of such devices. Here we demonstrate and present detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge (001) by atomic layer deposition. Metal-oxide-Ge capacitor structures show extremely low gate leakage, small and scalable EOT, and good and reducible Dit. Detailed growth strategies and postgrowth annealing schemes are demonstrated to reduce Dit. The physical mechanisms behind these phenomena are studied and suggest approaches for further reduction of Dit. PMID:26859048

  19. DNA detection using a complementary metal-oxide semiconductor ring oscillator circuit

    NASA Astrophysics Data System (ADS)

    Kocanda, Martin; Abdel-Motaleb, Ibrahim

    2010-10-01

    A DNA detection scheme has been implemented that utilizes a simple complementary metal-oxide semiconductor (CMOS) ring oscillator circuit. The detector oscillates at a fundamental frequency when using a nonhybridized single-strand DNA probe layer. Upon hybridization with a complimentary DNA strand, the oscillator output exhibits an increased frequency shift, indicating a genetic match. The probe assembly consists of a p-GaAs substrate containing a pulsed laser deposition-applied barium strontium titanate layer and an overlying sodium dodecyl sulfate lipid layer that serves to anchor a functionalized oligonucleotide probe. The oscillator circuit consisting of cascaded discrete complimentary n-channel and p-channel metal-oxide-semiconductor field-effect transistors was implemented using passive components arranged in a T-network to provide the associated fundamental time constant.

  20. Low-frequency noise in AlTiO/AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors

    NASA Astrophysics Data System (ADS)

    Le, Son Phuong; Ui, Toshimasa; Nguyen, Tuan Quy; Shih, Hong-An; Suzuki, Toshi-kazu

    2016-05-01

    Using aluminum titanium oxide (AlTiO, an alloy of Al2O3 and TiO2) as a high-k gate insulator, we fabricated and investigated AlTiO/AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors. From current low-frequency noise (LFN) characterization, we find Lorentzian spectra near the threshold voltage, in addition to 1/f spectra for the well-above-threshold regime. The Lorentzian spectra are attributed to electron trapping/detrapping with two specific time constants, ˜25 ms and ˜3 ms, which are independent of the gate length and the gate voltage, corresponding to two trap level depths of 0.5-0.7 eV with a 0.06 eV difference in the AlTiO insulator. In addition, gate leakage currents are analyzed and attributed to the Poole-Frenkel mechanism due to traps in the AlTiO insulator, where the extracted trap level depth is consistent with the Lorentzian LFN.

  1. Graphene oxide-zinc oxide nanocomposite as channel layer for field effect transistors: effect of ZnO loading on field effect transport.

    PubMed

    Jilani, S Mahaboob; Banerji, Pallab

    2014-10-01

    The effects of ZnO on graphene oxide (GO)-ZnO nanocomposites are investigated to tune the conductivity in GO under field effect regime. Zinc oxides with different concentrations from 5 wt % to 25 wt % are used in a GO matrix to increase the conductivity in the composite. Six sets of field effect transistors with pristine GO and GO-ZnO as the channel layer at varying ZnO concentrations were fabricated. From the transfer characteristics, it is observed that GO exhibited an insulating behavior and the transistors with low ZnO (5 wt %) concentration initially showed p-type conductivity that changes to n-type with increases in ZnO loading. This n-type dominance in conductivity is a consequence of the transfer of electrons from ZnO to the GO matrix. From X-ray photoelectron spectroscopic measurements, it is observed that the progressive reduction in the C-OH oxygen group took place with increases in ZnO loading. Thus, from insulating GO to p- and then n-type, conductivity in GO could be achieved with reduction in the C-OH oxygen group by photocatalytic reduction of GO with varying degrees of ZnO. The restoration of sp(2) electron network in the GO matrix with the anchoring of ZnO nanostructures was observed from Raman spectra. From UV-visible spectra, the band gap in pristine GO was found to be 3.98 eV and reduced to 2.8 eV with increase in ZnO attachment. PMID:25199448

  2. Epitaxial Electronic Oxides on Semiconductors Using Pulsed-Laser Deposition

    SciTech Connect

    Norton, D.P.; Budai, J.D.; Chisholm, M.F.

    1999-12-01

    We describe the growth and properties of epitaxial (OO1) CeO{sub 2} on a (001) Ge surface using a hydrogen-assisted pulsed-laser deposition method. Hydrogen gas is introduced during film growth to eliminate the presence of the GeOs from the semiconductor surface during the initial nucleation of the metal oxide film. The hydrogen partial pressure and substrate temperature are selected to be sufficiently high such that the germanium native oxides are thermodynamically unstable. The Gibbs free energy of CeO{sub 2} is larger in magnitude than that of the Ge native oxides, making it more favorable for the metal oxide to reside at the interface in comparison to the native Ge oxides. By satisfying these criteria. the metal oxide/semiconductor interface is shown to be atomically abrupt with no native oxide present. Preliminary structural and electrical properties are reported.

  3. Field-effect optical modulation based on epsilon-near-zero conductive oxide

    NASA Astrophysics Data System (ADS)

    Shi, Kaifeng; Lu, Zhaolin

    2016-07-01

    Epsilon-near-zero (ENZ, dielectric constant εr ≈ 0) materials have attracted significant research interest, however, their applications in the near-infrared regime are very limited. Conductive oxide (COx), owing to its moderate carrier concentration, is a candidate for ENZ material at telecom wavelengths based on the Drude model. Herein, we report an indium tin oxide (ITO) thin film as an ENZ material with cross-over wavelength, where real part of permittivity crosses zero, and enhanced light absorption at telecom wavelengths. We also report the investigation of electro-absorption modulation based on a metal-oxide-semiconductor (MOS)-like structure, more specifically a metal-oxide-ITO stack, where ITO works around ENZ. Based on the attenuated total reflectance (ATR) configuration, our test shows great promise for future electro-optical (EO) modulators. The operation speed of the MOS-like structure is limited mainly by RC delay.

  4. Large Lateral Photovoltaic Effect in Metal-(Oxide-) Semiconductor Structures

    PubMed Central

    Yu, Chongqi; Wang, Hui

    2010-01-01

    The lateral photovoltaic effect (LPE) can be used in position-sensitive detectors to detect very small displacements due to its output of lateral photovoltage changing linearly with light spot position. In this review, we will summarize some of our recent works regarding LPE in metal-semiconductor and metal-oxide-semiconductor structures, and give a theoretical model of LPE in these two structures. PMID:22163463

  5. Possible Deviation from the well-known Threshold Behavior of Field-Effect Doping Phenomenon in Extremely Thin Organic Semiconductor Layer

    NASA Astrophysics Data System (ADS)

    Ikegami, Keiichi

    2004-05-01

    Field-effect doping in a metal/insulator/semiconductor/metal four-layer model indicates that the well-known threshold behavior Q\\propto(VG-Vth), where Q is the induced charge and VG and Vth are the bias voltage and its threshold value, respectively, should be realized even when the thickness of the semiconductor layer (ds) is on the 10 nm scale. At the same time, however, this model suggests that the doping phenomenon deviates from this simple threshold behavior when the density of states is small and ds is on the 1 nm scale.

  6. Combined Jonker and Ioffe Analysis of Oxide Conductors and Semiconductors

    SciTech Connect

    Zhu, Q.M.; Hopper, E.M.; Ingram, B.J.; Mason, Thomas O.

    2010-09-27

    Jonker plots (Seebeck coefficient versus logarithm of conductivity) have been utilized to obtain the product of the density of states (DOS) and mobility (μ) in oxide semiconductors, from which the maximum electrical conductivity can be estimated for degenerate transparent conducting oxide (TCO) applications. In addition, the DOS–μ product can be utilized to predict the maximum achievable “power factor” (PF, Seebeck coefficient squared times conductivity) for oxide semiconductors. The PF is an important parameter governing the figure of merit for thermoelectric oxide (TEO) applications. The procedure employs an analysis developed by Ioffe, and provides an important screening tool for oxide (and other) thermoelectric materials, based upon data from polycrystalline ceramic specimens. Several oxides, including known transparent conductors, are considered as TCO and TEO case studies in the present work.

  7. Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

    NASA Technical Reports Server (NTRS)

    Kapoor, V. J.; Shokrani, M.

    1991-01-01

    A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

  8. Fabrication and characterization on reduced graphene oxide field effect transistor (RGOFET) based biosensor

    NASA Astrophysics Data System (ADS)

    Rashid, A. Diyana; Ruslinda, A. Rahim; Fatin, M. F.; Hashim, U.; Arshad, M. K.

    2016-07-01

    The fabrication and characterization on reduced graphene oxide field effect transistor (RGO-FET) were demonstrated using a spray deposition method for biological sensing device purpose. A spray method is a fast, low-cost and simple technique to deposit graphene and the most promising technology due to ideal coating on variety of substrates and high production speed. The fabrication method was demonstrated for developing a label free aptamer reduced graphene oxide field effect transistor biosensor. Reduced graphene oxide (RGO) was obtained by heating on hot plate fixed at various temperatures of 100, 200 and 300°C, respectively. The surface morphology of RGO were examined via atomic force microscopy to observed the temperature effect of produced RGO. The electrical measurement verify the performance of electrical conducting RGO-FET at temperature 300°C is better as compared to other temperature due to the removal of oxygen groups in GO. Thus, reduced graphene oxide was a promising material for biosensor application.

  9. Detection of a 2.8 THz quantum cascade laser with a semiconductor nanowire field-effect transistor coupled to a bow-tie antenna

    SciTech Connect

    Ravaro, M. Locatelli, M.; Consolino, L.; Bartalini, S.; De Natale, P.; Viti, L.; Ercolani, D.; Sorba, L.; Vitiello, M. S.

    2014-02-24

    The use of a high-electron mobility semiconductor nanowire as transistor channel has recently allowed the extension of the spectral coverage of THz field-effect transistor detectors up to 1.5 THz. In this report, we demonstrate efficient operation of a field-effect transistor detector based on a semiconductor nanowire at a much higher frequency, 2.8 THz, with a responsivity ≈5 V/W in a bandwidth ≈100 kHz, thus proving the full potential of such approach for the detection of THz quantum cascade lasers. Finally, such a THz sensing system is exploited to perform raster scan transmission imaging, with high spatial resolution, signal-to-noise ratio, and acquisition rate.

  10. Anisotropy-based crystalline oxide-on-semiconductor material

    DOEpatents

    McKee, Rodney Allen; Walker, Frederick Joseph

    2000-01-01

    A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation. For example, in the instance in which the crystalline oxide of the structure is a perovskite, a spinel or an oxide of similarly-related cubic structure, the structure can, within an appropriate semiconductor device, exhibit ferroelectric, piezoelectric, pyroelectric, electro-optic, ferromagnetic, antiferromagnetic, magneto-optic or large dielectric properties that synergistically couple to the underlying semiconductor substrate.