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Sample records for programmable logic devices

  1. Fuzzy logic and coarse coding using programmable logic devices

    NASA Astrophysics Data System (ADS)

    Brooks, Geoffrey

    2009-05-01

    Naturally-occurring sensory signal processing algorithms, such as those that inspired fuzzy-logic control, can be integrated into non-naturally-occurring high-performance technology, such as programmable logic devices, to realize novel bio-inspired designs. Research is underway concerning an investigation into using field programmable logic devices (FPLD's) to implement fuzzy logic sensory processing. A discussion is provided concerning the commonality between bio-inspired fuzzy logic algorithms and coarse coding that is prevalent in naturally-occurring sensory systems. Undergraduate design projects using fuzzy logic for an obstacle-avoidance robot has been accomplished at our institution and other places; numerous other successful fuzzy logic applications can be found as well. The long-term goal is to leverage such biomimetic algorithms for future applications. This paper outlines a design approach for implementing fuzzy-logic algorithms into reconfigurable computing devices. This paper is presented in an effort to connect with others who may be interested in collaboration as well as to establish a starting point for future research.

  2. Electronic systems miniaturization using programmable logic devices

    SciTech Connect

    Ashton, E.C.; Bergeson, G.C.

    1990-10-01

    This report describes the steps which were taken to miniaturize a target circuit using Erasable Programmable Logic Devices (EPLDs). The original objective of this project was to explore the miniaturization of a circuit using both Application Specific Integrated Circuits (ASICs) and EPLDs to meet the following goals: balance cost and circuit density; reduce fabrication time; improve quality control issues by keeping much of the design in-house; and eliminate security risks by partitioning the design into ASIC and PLD (EPLD) sections. Due to cost considerations, the target circuit was miniaturized using only PLDs. The results of this project indicate that PLDs are capable of realizing fairly dense circuitry, are considerably less expensive than ASICs (by a factor of 500--1000), and are able to eliminate security risks and reduce fabrication time by keeping the design completely in-house.

  3. Table-top mirror based parallel programmable optical logic device

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay

    2014-12-01

    Light rays can easily be reflected to different path by mechanical movement of mirrors. Using this basic operational principle we can design parallel programmable optical logic device (PPOLD) by arranging mirrors on a table. The ‘table-top mirror' models of this proposed circuit have been shown here. We can program it to design all the two input 16-Boolean logical expressions from a single design. The design is based on only plane mirrors. No active optical material is used in this design. Not only that the proposed circuit is optically reversible in nature. Moreover this design is very simple in sense. It can be fabricated in MEMS based optical switches.

  4. Preface of the "Symposium on Logic Synthesis for Programmable Logic Devices"

    NASA Astrophysics Data System (ADS)

    Kania, Dariusz

    2015-12-01

    Logic synthesis is an indirect link between design description and technology mapping. In the result of synthesis process an implementation in terms of an interconnection of logic gates, flip-flops, LUTs, etc. is generated. Typically, synthesis is performed for an objective function, such as minimizing the number of logic blocks (area), delay of interconnection, minimizing the power consumed, or making the implementation more testable. Logic synthesis is typically separated into two stages: technology-independent optimization, followed by a technology mapping. Technology mapping is the process of expressing a boolean network in terms of elements characteristic for a given technology (or device family). The aim of the symposium is to show all aspects of logic synthesis dedicated for Programmable Logic Devices.

  5. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm

  6. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

  7. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

  8. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.

  9. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.

  10. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    2000-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.

  11. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Day, John H. (Technical Monitor)

    2001-01-01

    This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

  12. A novel productivity-driven logic element for field-programmable devices

    NASA Astrophysics Data System (ADS)

    Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

    2014-06-01

    Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

  13. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1999-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.

  14. Flexible programmable logic module

    SciTech Connect

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  15. Programmable Logic Controllers.

    ERIC Educational Resources Information Center

    Insolia, Gerard; Anderson, Kathleen

    This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…

  16. A complex programmable logic device-based high-precision electrical capacitance tomography system

    NASA Astrophysics Data System (ADS)

    Zhou, Haili; Xu, Lijun; Cao, Zhang; Liu, XiaoLei; Liu, Shi

    2013-07-01

    In this paper, a high-precision measurement system for electrical capacitance tomography (ECT) is presented. A low-cost complex programmable logic device (CPLD) is employed to accomplish logic control, signal generation, data acquisition, digital demodulation and communication with the aid of external components. By adopting a simple digital demodulator recently developed by the authors, the demodulation to ac signals becomes rather simple and resource-saving. A double-T-switches configuration is developed to improve the precision and lower the limit of multi-channel capacitance measurement. A capacitance network is constructed for system calibration. A square ECT sensor with 16 electrodes is constructed to test the practical performance of the measurement system. With a data acquisition rate of 185 frame s-1, the signal-to-noise ratio and standard deviation of capacitance measurement can reach up to 70 dB and 0.09 fF, respectively. Image reconstruction experiment has validated the CPLD-based ECT system.

  17. Software Safety Assurance of Programmable Logic

    NASA Technical Reports Server (NTRS)

    Berens, Kalynnda

    2002-01-01

    Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

  18. Programmable Logic Controllers. Teacher Edition.

    ERIC Educational Resources Information Center

    Rauh, Bob; Kaltwasser, Stan

    These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…

  19. Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Darrin, Ann Garrison; Conde, Richard; Chern, Bobbie; Luers, Phil; Jurczyk, Steve; Mills, Carl; Day, John H. (Technical Monitor)

    2001-01-01

    The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of

  20. Implementation of field programmable logic arrays. Final report

    SciTech Connect

    Anderson, J.D.

    1981-03-01

    Field Programmable Logic Arrays (FPLAs) were incorporated into a fire set tester and a development tester used to test a signal generator's logic boards. Other circuits were designed using the FPLA in code conversion and sequential control applications. A Curtiss Electro Devices FPLA programmer was purchased to program Signetics 82S100 and 82S101 devices.

  1. Microelectromechanical reprogrammable logic device

    PubMed Central

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  2. Microelectromechanical reprogrammable logic device.

    PubMed

    Hafiz, M A A; Kosuru, L; Younis, M I

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  3. Microelectromechanical reprogrammable logic device

    NASA Astrophysics Data System (ADS)

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-03-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

  4. Benchmarking emerging logic devices

    NASA Astrophysics Data System (ADS)

    Nikonov, Dmitri

    2014-03-01

    As complementary metal-oxide-semiconductor field-effect transistors (CMOS FET) are being scaled to ever smaller sizes by the semiconductor industry, the demand is growing for emerging logic devices to supplement CMOS in various special functions. Research directions and concepts of such devices are overviewed. They include tunneling, graphene based, spintronic devices etc. The methodology to estimate future performance of emerging (beyond CMOS) devices and simple logic circuits based on them is explained. Results of benchmarking are used to identify more promising concepts and to map pathways for improvement of beyond CMOS computing.

  5. Universal programmable logic gate and routing method

    NASA Technical Reports Server (NTRS)

    Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

    2009-01-01

    An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

  6. Design of a Ferroelectric Programmable Logic Gate Array

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Ho, Fat Duen

    2003-01-01

    A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

  7. Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

    ERIC Educational Resources Information Center

    Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

    2009-01-01

    Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

  8. Implementing neural nets with programmable logic

    NASA Technical Reports Server (NTRS)

    Vidal, Jacques J.

    1988-01-01

    Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

  9. High-speed, cascaded optical logic operations using programmable optical logic gate arrays

    SciTech Connect

    Lu, B.; Lu, Y.C.; Cheng, J.; Hafich, M.J.; Klem, J.; Zolper, J.C.

    1996-01-01

    Programmable optical logic operations are demonstrated using arrays of nonlatching binary optical switches consisting of vertical-cavity surface-emitting lasers, p-i-n photodetectors and heterojunction bipolar transistors. Individual arrays can perform Boolean optical logic functions at 100 Mb/s using both optical and electrical logic inputs, while the routing and fan-out of the optical logic outputs can be controlled at the gate level. Cascaded optical logic operation is demonstrated using two programmable logic gate arrays.

  10. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  11. Reversible logic gate using adiabatic superconducting devices

    PubMed Central

    Takeuchi, N.; Yamanashi, Y.; Yoshikawa, N.

    2014-01-01

    Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage. PMID:25220698

  12. Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

    ERIC Educational Resources Information Center

    Debiec, P.; Byczuk, M.

    2011-01-01

    Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these laboratories.…

  13. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  14. Multifunction minimization for programmable logic arrays

    SciTech Connect

    Campbell, J.A.

    1984-01-01

    The problem of minimizing two-level AND/OR Boolean algebraic functions of n inputs and m outputs for implementation on programmable logic arrays (PLA) is examined. The theory of multiple-output functions as well as the historically alternative approaches to reckoning the cost of an equation implementation are reviewed. The PLA is shown to be a realization of the least product gate equation cost criterion. The multi-function minimization is dealt with in the context of a directed tree search algorithm developed in previous research. The PLA oriented minimization is shown to alter the nature of each of the basic tenets of multiple-output minimization used in earlier work. The concept of a non-prime but selectable implicant is introduced. A new cost criterion, the quantum cost, is discussed, and an approximation algorithm utilizing this criterion is developed. A timing analysis of a cyclic resolution algorithm for PLA based functions is presented. Lastly, the question of efficiency in automated minimization algorithms is examined. The application of the PLA cost criterion is shown to exhibit intrinsic increases in computational efficiency. A minterm classification algorithm is suggested and a PLA minimization algorithm is implemented in the FORTRAN language.

  15. Hybrid Programmable Logic Controller for Load Automation

    NASA Astrophysics Data System (ADS)

    Shahzad, Aamir; Farooq, Hashim; Abbar, Sofia; Yousaf, Mushtaq; Hafeez, Kamran; Hanif, M.

    The purpose of this study is to design a Programmable Logic Controller (PLC) to command 8-relays to control and automate ac loads via PC parallel port. In this project, the PLC is connected to the Personal Computer called hybrid PLC and this PC controls all the field ac loads via parallel printer port. Eight signals of different sequences are sent on parallel port via computer keyboard, which activate the microcontroller as inputs. Microcontroller responds according to these inputs and its user programming, which then commands 8-relays to control (on/off) different electronic appliances. Microcontroller memory makes easier to store its programming permanently. This hybrid PLC is applicable for controlling and monitoring industrial processes particularly of small to medium scale manufacturing processes and may be used for home automation as well. Parallel port is accessed by a program written in C++ language and microcontroller is programmed in assembly language. Ac load of any kind, whether resistive or inductive can be controlled with the help of this project.

  16. Logic and structured design for computer programmers

    SciTech Connect

    Rood, H.J.

    1985-01-01

    This text provides a language- and system-independent introduction to logical structures, and teaches logic plus the programming and data processing applications in which logic is used. The author has eliminated the need to cover basic program design at the beginning of every language course, and has used logic of sets, Boolean algebra, conditional statements, and truth tables to establish logic of structure flowchart, pseudocode, Warnier/Orr diagrams, and so on. After chapter three, the chapters are independent so that instructors can select the coverage of programming tools and techniques most relevant to their students.

  17. Programmable ubiquitous telerobotic devices

    NASA Astrophysics Data System (ADS)

    Doherty, Michael; Greene, Matthew; Keaton, David; Och, Christian; Seidl, Matthew L.; Waite, William; Zorn, Benjamin G.

    1997-12-01

    We are investigating a field of research that we call ubiquitous telepresence, which involves the design and implementation of low-cost robotic devices that can be programmed and operated from anywhere on the Internet. These devices, which we call ubots, can be used for academic purposes (e.g., a biologist could remote conduct a population survey), commercial purposes (e.g., a house could be shown remotely by a real-estate agent), and for recreation and education (e.g., someone could tour a museum remotely). We anticipate that such devices will become increasingly common due to recent changes in hardware and software technology. In particular, current hardware technology enables such devices to be constructed very cheaply (less than $500), and current software and network technology allows highly portable code to be written and downloaded across the Internet. In this paper, we present our prototype system architecture, and the ubot implementation we have constructed based on it. The hardware technology we use is the handy board, a 6811-based controller board with digital and analog inputs and outputs. Our software includes a network layer based on TCP/IP and software layers written in Java. Our software enables users across the Internet to program the behavior of the vehicle and to receive image feedback from a camera mounted on it.

  18. Magnetic tunnel junction based spintronic logic devices

    NASA Astrophysics Data System (ADS)

    Lyle, Andrew Paul

    The International Technology Roadmap for Semiconductors (ITRS) predicts that complimentary metal oxide semiconductor (CMOS) based technologies will hit their last generation on or near the 16 nm node, which we expect to reach by the year 2025. Thus future advances in computational power will not be realized from ever-shrinking device sizes, but rather by 'outside the box' designs and new physics, including molecular or DNA based computation, organics, magnonics, or spintronic. This dissertation investigates magnetic logic devices for post-CMOS computation. Three different architectures were studied, each relying on a different magnetic mechanism to compute logic functions. Each design has it benefits and challenges that must be overcome. This dissertation focuses on pushing each design from the drawing board to a realistic logic technology. The first logic architecture is based on electrically connected magnetic tunnel junctions (MTJs) that allow direct communication between elements without intermediate sensing amplifiers. Two and three input logic gates, which consist of two and three MTJs connected in parallel, respectively were fabricated and are compared. The direct communication is realized by electrically connecting the output in series with the input and applying voltage across the series connections. The logic gates rely on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin transfer torque switching the output. The change in resistance at the input resulted in a voltage margin of 50--200 mV and 250--300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three input logic function realizes the Majority, AND, NAND, NOR, and OR logic operations. The second logic architecture utilizes magnetostatically coupled nanomagnets to compute logic functions, which is the basis of

  19. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.; Paolini, W.; Sin, B.

    1998-01-01

    State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

  20. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, R.; Wang, J. J.; Koga, R.; LaBel, K. A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.; Paolini, W.; Sin, B.

    1998-01-01

    State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

  1. Pathway to the Piezoelectronic Transduction Logic Device

    NASA Astrophysics Data System (ADS)

    Solomon, P. M.; Bryce, B. A.; Kuroda, M. A.; Keech, R.; Shetty, S.; Shaw, T. M.; Copel, M.; Hung, L.-W.; Schrott, A. G.; Armstrong, C.; Gordon, M. S.; Reuter, K. B.; Theis, T. N.; Haensch, W.; Rossnagel, S. M.; Miyazoe, H.; Elmegreen, B. G.; Liu, X.-H.; Trolier-McKinstry, S.; Martyna, G. J.; Newns, D. M.

    2015-04-01

    The information age challenges computer technology to process an exponentially increasing computational load on a limited energy budget - a requirement that demands an exponential reduction in energy per operation. In digital logic circuits, the switching energy of present FET devices is intimately connected with the switching voltage, and can no longer be lowered sufficiently, limiting the ability of current technology to address the challenge. Quantum computing offers a leap forward in capability, but a clear advantage requires algorithms presently developed for only a small set of applications. Therefore, a new, general purpose, classical technology based on a different paradigm is needed to meet the ever increasing demand for data processing.

  2. Magnetic tunnel junction based spintronic logic and memory devices

    NASA Astrophysics Data System (ADS)

    Yao, Xiaofeng

    2011-12-01

    The development of semiconductor devices is limited by the high power consumption and further physical dimension reduction. Spintronic devices, especially the magnetic tunnel junction (MTJ) based devices, have advantages of non-volatility, reconfigurable capability, fast-switching speed, small-dimension, and compatibility to semiconductor devices, which is a promising candidate for future logic and memory devices. However, the previously proposed MTJ logic devices have been operated independently and therefore are limited to only basic logic operations. Consequently, the MTJ device has only been used as ancillary device in the circuit, rather than the main computation component. In this thesis, study has been done on both spintronic logic and memory devices. In the first part, systematic study has been performed on MTJ based logic devices in order to expand the functionalities and properties of MTJ devices. Basic logic cell with three-input has been designed and simulated. Nano-magnetic-channel has been proposed, which is the first design to realize the communication between the MTJ logic cells. With basic logic unit as a building block, a spintronic logic circuit has been designed with MTJ as the dominant component. HSPICE simulation has been done for this spintronic logic circuit, which acts as an Arithmetic Logic Unit. In the spintronic memory device part, study has been focused on the fundamental study on the current induced switching in MTJ devices with hybrid free layer. With hybrid free layer, magnetic non-uniformity is introduced along the current direction, which induces extra spin torque component. Unique current-induced switching has been observed and studied in the hybrid free layer MTJ. Adiabatic spin torque, which is introduced by spatial non-uniform magnetization in the hybrid free layer, plays an important role for the unique switching. By tuning the bias field, single-polar current switching was achieved in this hybrid MTJ device, which gives the

  3. Applying programmable logic controllers to safety-related systems

    SciTech Connect

    Ruether, J.C. )

    1992-01-01

    Northern States Power Company (NSP) recently installed programmable logic controllers (PLCs) in two safety-related systems at its Prairie Island nuclear generating plant. The lessons learned during these applications at the 19-yr old two-unit plant may benefit similar projects. Prairie Island responded to the station black out (SBO) issue by upgrading its electrical distribution system. This included installing additional safeguard diesel generators (DGs), new 4160-V buses, and new 480-V buses. As part of this upgrade, PLCs were commercially dedicated for use in two safety-related applications: (1) bus load sequencer project, (2) 480-V voltage regulator project.

  4. Building and using a highly parallel programmable logic array

    SciTech Connect

    Gokhale, M.; Holmes, W.; Kopser, A.; Lucas, S.; Minnich, R.; Sweely, D. ); Lopresti, D. )

    1991-01-01

    With a $13,000 two-slot addition called Splash, a Sun workstation can outperform a Cray-2 on certain applications. Several applications, most involving bit-stream computations, have been run on Splash, which received a 1989 Gordon Bell Prize honorable mention for timings on a problem that compared a new DNA sequence against a library of sequences to find the closest match. In essence, Splash is a programmable linear logic array that can be configured to suit the problem at hand; it bridges the gap between the traditional fixed-function VLSI systolic array and the more versatile programmable array. As originally conceived, a systolic array is a collection of simple processing elements, along with a one- or two-dimensional nearest-neighbor communication pattern. The local nature of the communication gives the systolic array a high communications bandwidth, and the simple, fixed function gives a high packing density for VLSI implementation.

  5. Development of ferrite logic devices for an arithmetic processor

    NASA Technical Reports Server (NTRS)

    Heckler, C. H., Jr.

    1972-01-01

    A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.

  6. Sandia ATM SONET Interface Logic

    Energy Science and Technology Software Center (ESTSC)

    1994-07-21

    SASIL is used to program the EPLD's (Erasable Programmable Logic Devices) and PAL's (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  7. The programmable (logic) controller: Adapting in an environment of change

    SciTech Connect

    Levine, P.S.

    1995-03-01

    Reports of the imminent death of the PLC (programmable logic controller) were greatly exaggerated, to paraphrase Mark Twain. In fact, the PLC is not only alive and working worldwide in thousands of applications, but it is also integrating well with related technologies. Long-term survival is a larger question - probably unanswerable given the pace of technological change. However, a few questions arise about the PLC today and in the immediate future: (1) What`s happening with programming languages? (2) Will there continue to be a {open_quotes}blurring of the lines{close_quotes} between the PLC and other technologies, and what role will software play in this integration? (3) How will the PLC`s cost and size affect the market?

  8. Improving immunization of programmable logic controllers using weighted median filters.

    PubMed

    Paredes, José L; Díaz, Dhionel

    2005-04-01

    This paper addresses the problem of improving immunization of programmable logic controllers (PLC's) to electromagnetic interference with impulsive characteristics. A filtering structure, based on weighted median filters, that does not require additional hardware and can be implemented in legacy PLC's is proposed. The filtering operation is implemented in the binary domain and removes the impulsive noise presented in the discrete input adding thus robustness to PLC's. By modifying the sampling clock structure, two variants of the filter are obtained. Both structures exploit the cyclic nature of the PLC to form an N-sample observation window of the discrete input, hence a status change on it is determined by the filter output taking into account all the N samples avoiding thus that a single impulse affects the PLC functionality. A comparative study, based on a statistical analysis, of the different filters' performances is presented. PMID:15868861

  9. Processing device with self-scrubbing logic

    DOEpatents

    Wojahn, Christopher K.

    2016-03-01

    An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

  10. Programmable logic controller optical fibre sensor interface module

    NASA Astrophysics Data System (ADS)

    Allwood, Gary; Wild, Graham; Hinckley, Steven

    2011-12-01

    Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

  11. Voltage controlled spintronic devices for logic applications

    DOEpatents

    You, Chun-Yeol; Bader, Samuel D.

    2001-01-01

    A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

  12. Programmable and Multiparameter DNA-Based Logic Platform For Cancer Recognition and Targeted Therapy

    PubMed Central

    2014-01-01

    The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

  13. Programmable and multiparameter DNA-based logic platform for cancer recognition and targeted therapy.

    PubMed

    You, Mingxu; Zhu, Guizhi; Chen, Tao; Donovan, Michael J; Tan, Weihong

    2015-01-21

    The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

  14. Ultrafast phase-change logic device driven by melting processes

    PubMed Central

    Loke, Desmond; Skelton, Jonathan M.; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R.

    2014-01-01

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change–based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change–based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change–based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates. PMID:25197044

  15. Ultrafast phase-change logic device driven by melting processes.

    PubMed

    Loke, Desmond; Skelton, Jonathan M; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R

    2014-09-16

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change-based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change-based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change-based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates. PMID:25197044

  16. SASIL. Sandia ATM SONET Interface Logic

    SciTech Connect

    Kitta, J.P.

    1994-07-01

    SASIL is used to program the EPLD`s (Erasable Programmable Logic Devices) and PAL`s (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  17. Compact programmable photonic variable delay devices

    NASA Technical Reports Server (NTRS)

    Yao, X. Steve (Inventor)

    1999-01-01

    Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

  18. Supramolecular photochemistry applied to artificial photosynthesis and molecular logic devices.

    PubMed

    Gust, Devens

    2015-01-01

    Supramolecular photochemical systems consist of photochemically active components such as chromophores, electron donors or electron acceptors that are associated via non-covalent or covalent interactions and that interact in some functional way. Examples of interactions are singlet-singlet energy transfer, triplet-triplet energy transfer, photoinduced electron transfer, quantum coherence and spin-spin magnetic interactions. Supramolecular photochemical "devices" may have applications in areas such as solar energy conversion, molecular logic, computation and data storage, biomedicine, sensing, imaging, and displays. This short review illustrates supramolecular photochemistry with examples drawn from artificial photosynthesis, molecular logic, analog photochemical devices and models for avian magnetic orientation. PMID:26515930

  19. Pathway to the piezoelectronic transduction logic device.

    PubMed

    Solomon, P M; Bryce, B A; Kuroda, M A; Keech, R; Shetty, S; Shaw, T M; Copel, M; Hung, L-W; Schrott, A G; Armstrong, C; Gordon, M S; Reuter, K B; Theis, T N; Haensch, W; Rossnagel, S M; Miyazoe, H; Elmegreen, B G; Liu, X-H; Trolier-McKinstry, S; Martyna, G J; Newns, D M

    2015-04-01

    The piezoelectronic transistor (PET) has been proposed as a transduction device not subject to the voltage limits of field-effect transistors. The PET transduces voltage to stress, activating a facile insulator-metal transition, thereby achieving multigigahertz switching speeds, as predicted by modeling, at lower power than the comparable generation field effect transistor (FET). Here, the fabrication and measurement of the first physical PET devices are reported, showing both on/off switching and cycling. The results demonstrate the realization of a stress-based transduction principle, representing the early steps on a developmental pathway to PET technology with potential to contribute to the IT industry. PMID:25793915

  20. Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

    PubMed

    Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

    2013-05-01

    A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors. PMID:23858841

  1. Cascade DNA logic device programmed ratiometric DNA analysis and logic devices based on a fluorescent dual-signal probe of a G-quadruplex DNAzyme.

    PubMed

    Fan, Daoqing; Zhu, Jinbo; Zhai, Qingfeng; Wang, Erkang; Dong, Shaojun

    2016-03-01

    Herein, two fluorescence sensitive substrates of G-quadruplex/hemin DNAzyme with inverse responses (Scopoletin and Amplex Red) were simultaneously used in one homogeneous system to construct a cascade advanced DNA logic device for the first time (a functional logic device (a three input based DNA calliper) cascade with an advanced non-arithmetic logic gate (1 to 2 decoder)). This cascade logic device was applied to label-free ratiometric target DNA detection and length measurement. PMID:26882417

  2. General purpose programmable accelerator board

    DOEpatents

    Robertson, Perry J.; Witzke, Edward L.

    2001-01-01

    A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

  3. Programme Costing - A Logical Step Toward Improved Management.

    ERIC Educational Resources Information Center

    McDougall, Ronald N.

    The analysis of costs of university activities from a functional or program point of view, rather than an organizational unit basis, is not only an imperative for the planning and management of universities, but also a logical method of examing the costs of university operations. A task force of the Committee of Finance Officers-Universities of…

  4. Energy Efficient Digital Logic Using Nanoscale Magnetic Devices

    NASA Astrophysics Data System (ADS)

    Lambson, Brian James

    Increasing demand for information processing in the last 50 years has been largely satisfied by the steadily declining price and improving performance of microelectronic devices. Much of this progress has been made by aggressively scaling the size of semiconductor transistors and metal interconnects that microprocessors are built from. As devices shrink to the size regime in which quantum effects pose significant challenges, new physics may be required in order to continue historical scaling trends. A variety of new devices and physics are currently under investigation throughout the scientific and engineering community to meet these challenges. One of the more drastic proposals on the table is to replace the electronic components of information processors with magnetic components. Magnetic components are already commonplace in computers for their information storage capability. Unlike most electronic devices, magnetic materials can store data in the absence of a power supply. Today's magnetic hard disk drives can routinely hold billions of bits of information and are in widespread commercial use. Their ability to function without a constant power source hints at an intrinsic energy efficiency. The question we investigate in this dissertation is whether or not this advantage can be extended from information storage to the notoriously energy intensive task of information processing. Several proof-of-concept magnetic logic devices were proposed and tested in the past decade. In this dissertation, we build on the prior work by answering fundamental questions about how magnetic devices achieve such high energy efficiency and how they can best function in digital logic applications. The results of this analysis are used to suggest and test improvements to nanomagnetic computing devices. Two of our results are seen as especially important to the field of nanomagnetic computing: (1) we show that it is possible to operate nanomagnetic computers at the fundamental

  5. Motor imaginary-based brain-machine interface design using programmable logic controllers for the disabled.

    PubMed

    Jeyabalan, Vickneswaran; Samraj, Andrews; Loo, Chu Kiong

    2010-10-01

    Aiming at the implementation of brain-machine interfaces (BMI) for the aid of disabled people, this paper presents a system design for real-time communication between the BMI and programmable logic controllers (PLCs) to control an electrical actuator that could be used in devices to help the disabled. Motor imaginary signals extracted from the brain’s motor cortex using an electroencephalogram (EEG) were used as a control signal. The EEG signals were pre-processed by means of adaptive recursive band-pass filtrations (ARBF) and classified using simplified fuzzy adaptive resonance theory mapping (ARTMAP) in which the classified signals are then translated into control signals used for machine control via the PLC. A real-time test system was designed using MATLAB for signal processing, KEP-Ware V4 OLE for process control (OPC), a wireless local area network router, an Omron Sysmac CPM1 PLC and a 5 V/0.3A motor. This paper explains the signal processing techniques, the PLC's hardware configuration, OPC configuration and real-time data exchange between MATLAB and PLC using the MATLAB OPC toolbox. The test results indicate that the function of exchanging real-time data can be attained between the BMI and PLC through OPC server and proves that it is an effective and feasible method to be applied to devices such as wheelchairs or electronic equipment. PMID:20336561

  6. Preliminary surface-emitting laser logic device evaluation

    NASA Astrophysics Data System (ADS)

    Libby, S. I.; Parker, M. A.; Olbright, G. R.; Swanson, P. D.

    1993-03-01

    This report discusses the evaluation of a monolithically integrated heterojunction phototransistor and vertical-cavity surface-emitting laser, designated the surface-Emitting Laser Logic device (CELL). Included is a discussion of the device structure and theory of operation, test procedures, results, and conclusions. Also presented is the CELL's opto-electronic input/output characteristics which includes spectral analysis, characteristic emitted light versus current and current versus voltage curves, input wavelength tolerance, output wavelength sensitivity to bias current, and insensitivity to input wavelength and power within a specified range.

  7. Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

    ERIC Educational Resources Information Center

    Todorovich, E.; Marone, J. A.; Vazquez, M.

    2012-01-01

    Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

  8. A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

    ERIC Educational Resources Information Center

    Kellett, C. M.

    2012-01-01

    This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

  9. Thermally reliable clocked non-volatile spin wave logic device

    NASA Astrophysics Data System (ADS)

    Dutta, Sourav; Nikonov, Dmitri; Manipatruni, Sasikanth; Young, Ian; Naeemi, Azad

    The possibility of utilizing spin waves for information transmission and computation has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits. Here, we present a comprehensive scheme for building a thermally reliable clocked non-volatile spin wave logic device (SWLD) by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, exploiting the magneto-electric effect for spin wave transmission, detection and non-volatile memory, utilizing the phase of the spin wave as information token, ensuring phase-dependent deterministic switching of the magnetoelectric spin wave detector in the presence of thermal noise via compensation of demagnetization and a novel clocking scheme that ensures sequential transmission of information in a cascaded SWLD and non- reciprocity

  10. Multifunctional devices and logic gates with undoped silicon nanowires.

    PubMed

    Mongillo, Massimo; Spathis, Panayotis; Katsaros, Georgios; Gentile, Pascal; De Franceschi, Silvano

    2012-06-13

    We report on the electronic transport properties of multiple-gate devices fabricated from undoped silicon nanowires. Understanding and control of the relevant transport mechanisms was achieved by means of local electrostatic gating and temperature-dependent measurements. The roles of the source/drain contacts and of the silicon channel could be independently evaluated and tuned. Wrap gates surrounding the silicide-silicon contact interfaces were proved to be effective in inducing a full suppression of the contact Schottky barriers, thereby enabling carrier injection down to liquid helium temperature. By independently tuning the effective Schottky barrier heights, a variety of reconfigurable device functionalities could be obtained. In particular, the same nanowire device could be configured to work as a Schottky barrier transistor, a Schottky diode, or a p-n diode with tunable polarities. This versatility was eventually exploited to realize a NAND logic gate with gain well above one. PMID:22594644

  11. Current-limiting challenges for all-spin logic devices

    NASA Astrophysics Data System (ADS)

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-10-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications.

  12. Current-limiting challenges for all-spin logic devices

    PubMed Central

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-01-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

  13. Current-limiting challenges for all-spin logic devices.

    PubMed

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-01-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

  14. Lateral Programmable Metallization Cell Devices And Applications

    NASA Astrophysics Data System (ADS)

    Ren, Minghan

    2011-12-01

    Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in situ, via the application of a bias on laterally placed electrodes, creates a large number of promising applications. A novel PMC-based lateral microwave switch was fabricated and characterized for use in microwave systems. It has demonstrated low insertion loss, high isolation, low voltage operation, low power and low energy consumption, and excellent linearity. Due to its non-volatile nature the switch operates with fewer biases and its simple planar geometry makes possible innovative device structures which can be potentially integrated into microwave power distribution circuits. PMC technology is also used to develop lateral dendritic metal electrodes. A lateral metallic dendritic network can be grown in a solid electrolyte (GeSe) or electrodeposited on SiO2 or Si using a water-mediated method. These dendritic electrodes grown in a solid electrolyte (GeSe) can be used to lower resistances for applications like self-healing interconnects despite its relatively low light transparency; while the dendritic electrodes grown using water-mediated method can be potentially integrated into solar cell applications, like replacing conventional Ag screen-printed top electrodes as they not only reduce resistances but also are highly transparent. This research effort also laid a solid foundation for developing dendritic plasmonic structures. A PMC-based lateral dendritic plasmonic structure is a device that has metallic dendritic networks grown electrochemically on SiO2 with a thin layer of surface metal nanoparticles in liquid electrolyte. These structures increase the distribution of particle sizes by connecting pre-deposited Ag

  15. Improved overlay metrology device correlation on 90-nm logic processes

    NASA Astrophysics Data System (ADS)

    Ueno, Atsushi; Tsujita, Kouichirou; Kurita, Hiroyuki; Iwata, Yasuhisa; Ghinovker, Mark; Poplawski, Jorge M.; Kassel, Elyakim; Adel, Mike E.

    2004-05-01

    Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

  16. Towards manufacturing of advanced logic devices by double-patterning

    NASA Astrophysics Data System (ADS)

    Koay, Chiew-seng; Halle, Scott; Holmes, Steven; Petrillo, Karen; Colburn, Matthew; van Dommelen, Youri; Jiang, Aiqin; Crouse, Michael; Dunn, Shannon; Hetzer, David; Kawakami, Shinichiro; Cantone, Jason; Huli, Lior; Rodgers, Martin; Martinick, Brian

    2011-04-01

    As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

  17. 46 CFR 62.25-25 - Programmable systems and devices.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 46 Shipping 2 2014-10-01 2014-10-01 false Programmable systems and devices. 62.25-25 Section 62.25-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM AUTOMATION General Requirements for All Automated Vital Systems § 62.25-25 Programmable systems and...

  18. Fabrication of stretchable single-walled carbon nanotube logic devices.

    PubMed

    Yoon, Jangyeol; Shin, Gunchul; Kim, Joonsung; Moon, Young Sun; Lee, Seung-Jung; Zi, Goangseup; Ha, Jeong Sook

    2014-07-23

    The fabrication of a stretchable single-walled carbon nanotube (SWCNT) complementary metal oxide semiconductor (CMOS) inverter array and ring oscillators is reported. The SWCNT CMOS inverter exhibits static voltage transfer characteristics with a maximum gain of 8.9 at a supply voltage of 5 V. The fabricated devices show stable electrical performance under the maximum strain of 30% via forming wavy configurations. In addition, the 3-stage ring oscillator demonstrates a stable oscillator frequency of ∼3.5 kHz at a supply voltage of 10 V and the oscillating waveforms are maintained without any distortion under cycles of pre-strain and release. The strains applied to the device upon deformation are also analyzed by using the classical lamination theory, estimating the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions which is small enough to keep the device performance stable under the pre-strain up to 30%. This work demonstrates the potential application of stretchable SWCNT logic circuit devices in future wearable electronics. PMID:24700788

  19. D0 General Support: The Use of Programmable Logic Controllers (PLCS) at D0

    SciTech Connect

    Hance, R.; /Fermilab

    2000-05-05

    With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

  20. Programmable logic controller performance enhancement by field programmable gate array based design.

    PubMed

    Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

    2015-01-01

    PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. PMID:25441219

  1. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  2. WeaselBoard : zero-day exploit detection for programmable logic controllers.

    SciTech Connect

    Mulder, John C.; Schwartz, Moses Daniel; Berg, Michael J.; Van Houten, Jonathan Roger; Urrea, Jorge Mario; King, Michael Aaron; Clements, Abraham Anthony; Jacob, Joshua A.

    2013-10-01

    Critical infrastructures, such as electrical power plants and oil refineries, rely on programmable logic controllers (PLCs) to control essential processes. State of the art security cannot detect attacks on PLCs at the hardware or firmware level. This renders critical infrastructure control systems vulnerable to costly and dangerous attacks. WeaselBoard is a PLC backplane analysis system that connects directly to the PLC backplane to capture backplane communications between modules. WeaselBoard forwards inter-module traffic to an external analysis system that detects changes to process control settings, sensor values, module configuration information, firmware updates, and process control program (logic) updates. WeaselBoard provides zero-day exploit detection for PLCs by detecting changes in the PLC and the process. This approach to PLC monitoring is protected under U.S. Patent Application 13/947,887.

  3. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  4. A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell

    NASA Astrophysics Data System (ADS)

    Yi-Hung Tsai,; Hsiao-Lan Yang,; Wun-Jie Lin,; Chrong Jung Lin,; Ya-Chin King,

    2010-04-01

    This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 Å for 90 nm complementary metal-oxide-semiconductor (CMOS) node and beyond.

  5. Programmable synaptic devices for electronic neural nets

    NASA Technical Reports Server (NTRS)

    Moopenn, A.; Thakoor, A. P.

    1990-01-01

    The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

  6. Improvement of photovoltaic pumping systems based on standard frequency converters by means of programmable logic controllers

    SciTech Connect

    Fernandez-Ramos, Jose; Narvarte-Fernandez, Luis; Poza-Saura, Fernando

    2010-01-15

    Photovoltaic pumping systems (PVPS) based on standard frequency converters (SFCs) are currently experiencing a growing interest in pumping programmes implemented in remote areas because of their high performance in terms of component reliability, low cost, high power range and good availability of components virtually anywhere in the world. However, in practical applications there have appeared a number of problems related to the adaptation of the SFCs to the requirements of the photovoltaic pumping systems (PVPS). Another disadvantage of dedicated PVPS is the difficulty in implementing maximum power point tracking (MPPT). This paper shows that these problems can be solved through the addition of a basic industrial programmable logic controller (PLC) to the system. This PLC does not increase the cost and complexity of the system, but improves the adaptation of the SFC to the photovoltaic pumping system, and increases the overall performance of the system. (author)

  7. The Programmable Logic Controller and its application in nuclear reactor systems

    SciTech Connect

    Palomar, J.; Wyman, R.

    1993-09-01

    This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

  8. The research and applications of programmable analog device

    NASA Astrophysics Data System (ADS)

    Yang, Xiaohui; Zhao, Qiudi; Yang, Yongjian

    2005-01-01

    This paper introduces the inner structure principle and signal adjusting applications of programmable analogy device ispPAC which was manufactured by Lattice semiconductor company.It expounds the chip functions of agility,diverse amplification,smoothing and deamplification at length and discusses the design method of every function.

  9. A logical molecular circuit for programmable and autonomous regulation of protein activity using DNA aptamer-protein interactions.

    PubMed

    Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R; Tan, Weihong

    2012-12-26

    Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo. (1) As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here, we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy. PMID:23194304

  10. A logical molecular circuit for programmable and autonomous regulation of protein activity using DNA aptamer-protein interactions

    PubMed Central

    Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R.; Tan, Weihong

    2013-01-01

    Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo.1 As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy. PMID:23194304

  11. All-optical logic devices with cascaded nonlinear couplers.

    PubMed

    Wang, Y; Wang, Z H; Bialkowski, M E

    2000-08-10

    The switching behaviors of cascaded nonlinear couplers were investigated. They have nearly ideal digital-switching characteristics, and their output power levels can be adjusted by means of varying the nonlinear coupling coefficient of the final coupler. The two-input excitation nonlinear cascaded couplers can perform not only switching operations but also a series of logic operations. The logic operations depend mainly on the coupling length of the two-input coupler and its initial inputs. The power corresponding to the rising and falling ridge of the logic operating waveforms can be shifted effectively by means of varying the switching power of the reshaper. Allowable ranges of three important parameters--coupling length of the two-input coupler L(1), bias optical power P(bia), and phase difference psi between the signal and bias beams for six fundamental logic operations--were calculated. Curves for design considerations and suggestions for the best choice of parameters for stable and reliable logic operations and, or, xor, nand, nor, and nxor are also presented individually. PMID:18349996

  12. Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

    SciTech Connect

    KOCH, M.R.

    1999-11-16

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309, Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  13. Programmable logic controller implementation of an auto-tuned predictive control based on minimal plant information.

    PubMed

    Valencia-Palomo, G; Rossiter, J A

    2011-01-01

    This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules. PMID:21056412

  14. Implementation of motor speed control using PID control in programmable logic controller

    NASA Astrophysics Data System (ADS)

    Samin, R. E.; Azmi, N. A.; Ahmad, M. A.; Ghazali, M. R.; Zawawi, M. A.

    2012-11-01

    This paper presents the implementation of motor speed control using Proportional Integral Derrivative (PID) controller using Programmable Logic Controller (PLC). Proportional Integral Derrivative (PID) controller is the technique used to actively control the speed of the motor. An AC motor is used in the research together with the PLC, encoder and Proface touch screen. The model of the PLC that has been used in this project is OMRON CJIG-CPU42P where this PLC has a build in loop control that can be made the ladder diagram quite simple using function block in CX-process tools. A complete experimental analysis of the technique in terms of system response is presented. Comparative assessment of the impact of Proportional, Integral and Derivative in the controller on the system performance is presented and discussed.

  15. Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

    SciTech Connect

    WHITE, K.A.

    2000-11-28

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309, Rev. 1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  16. Controlling High Power Devices with Computers or TTL Logic Circuits

    ERIC Educational Resources Information Center

    Carlton, Kevin

    2002-01-01

    Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…

  17. Electrically reconfigurable logic array

    NASA Technical Reports Server (NTRS)

    Agarwal, R. K.

    1982-01-01

    To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

  18. ``Spin inverter'' as building block of All Spin Logic devices

    NASA Astrophysics Data System (ADS)

    Sarkar, Angik; Srinivasan, Srikant; Datta, Supriyo

    2012-02-01

    All-spin logic (ASL) represents a new approach to information processing where the roles of charges and capacitors in charge based transistors are played by spins and magnets, without the need for repeated spin-charge conversion. In our past work, we have presented numerical simulations based on a coupled spin transport and Landau Lifshitz Gilbert model showing that ring oscillators and logic circuits with intrinsic directionality [IEEE Trans. Magn. 47,10, 4026, 2011; Proc. IEDM, 2011)] can be implemented by manipulation of spins in magnetic nanostructures. The aim of this talk is (1) to identify a basic ASL unit that can be interconnected to build up spin circuits analogous to the way transistors are interconnected to build conventional circuits and (2) to present a compact model for this basic unit that can be used to design and analyze large scale spin circuits. We will show that this basic ASL unit is a one-magnet ``spin inverter'' with gain that can be cascaded to accomplish a spin circuit implementation of almost any logic functionality

  19. Logic synthesis of cascade circuits

    NASA Astrophysics Data System (ADS)

    Zakrevskii, A. D.

    The work reviews aspects of the logic design of cascade circuits, particularly programmable logic matrices. Effective methods for solving various problems of the analysis and synthesis of these devices are examined; these methods are based on a matrix representation of the structure of these devices, and a vector-matrix interpretation of certain aspects of Boolean algebra. Particular consideration is given to the theory of elementary matrix circuits, methods for the minimization of Boolean functions, the synthesis of programmable logic matrices, multilevel combinational networks, and the development of automata with memory.

  20. Proposal for an all-spin logic device with built-in memory.

    PubMed

    Behin-Aein, Behtash; Datta, Deepanjan; Salahuddin, Sayeef; Datta, Supriyo

    2010-04-01

    The possible use of spin rather than charge as a state variable in devices for processing and storing information has been widely discussed, because it could allow low-power operation and might also have applications in quantum computing. However, spin-based experiments and proposals for logic applications typically use spin only as an internal variable, the terminal quantities for each individual logic gate still being charge-based. This requires repeated spin-to-charge conversion, using extra hardware that offsets any possible advantage. Here we propose a spintronic device that uses spin at every stage of its operation. Input and output information are represented by the magnetization of nanomagnets that communicate through spin-coherent channels. Based on simulations with an experimentally benchmarked model, we argue that the device is both feasible and shows the five essential characteristics for logic applications: concatenability, nonlinearity, feedback elimination, gain and a complete set of Boolean operations. PMID:20190748

  1. Designing the Expanded Programme on Immunisation (EPI) as a service: Prioritising patients over administrative logic.

    PubMed

    McKnight, Jacob; Holt, Douglas B

    2014-01-01

    Expanded Programme on Immunisation (EPI) vaccination rates remain well below herd immunity in regions of many countries despite huge international resources devoted to both financing and access. We draw upon service marketing theory, organisational sociology, development anthropology and cultural consumer research to conduct an ethnographic study of vaccination delivery in Jimma Zone, Ethiopia - one such region. We find that Western public health sector policies are dominated by an administrative logic. Critical failures in delivery are produced by a system that obfuscates the on-the-ground problems that mothers face in trying to vaccinate their children, while instead prioritising administrative processes. Our ethnographic analysis of 83 mothers who had not vaccinated their children reveals key barriers to vaccination from a 'customer' perspective. While mothers value vaccination, it is a 'low involvement' good compared to the acute daily needs of a subsistence life. The costs imposed by poor service - such as uncaring staff with class hostilities, unpredictable and missed schedules and long waits - are too much and so they forego the service. Our service design framework illuminates specific service problems from the mother's perspective and points towards simple service innovations that could improve vaccination rates in regions that have poor uptake. PMID:25363481

  2. The spatial and logical organization of devices in an advanced industrial robot system

    NASA Technical Reports Server (NTRS)

    Ruoff, C. F.

    1980-01-01

    This paper describes the geometrical and device organization of a robot system which is based in part upon transformations of Cartesian frames and exchangeable device tree structures. It discusses coordinate frame transformations, geometrical device representation and solution degeneracy along with the data structures which support the exchangeable logical-physical device assignments. The system, which has been implemented in a minicomputer, supports vision, force, and other sensors. It allows tasks to be instantiated with logically equivalent devices and it allows tasks to be defined relative to appropriate frames. Since these frames are, in turn, defined relative other frames this organization provides a significant simplification in task specification and a high degree of system modularity.

  3. Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

    NASA Astrophysics Data System (ADS)

    Wang, Jian-Ping

    An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

  4. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications

    NASA Astrophysics Data System (ADS)

    Khatami, Yasin; Kang, Jiahao; Banerjee, Kaustav

    2013-01-01

    Negative resistance devices offer opportunities in design of compact and fast analog and digital circuits. However, their implementation in logic applications has been limited due to their small ON current to OFF current ratios (peak to valley ratio). In this paper, a design for a 2-port negative resistance device based on arm-chair graphene nanoribbon is presented. The proposed structure takes advantage of electrostatic doping, and offers high ON current (˜700 μA/μm) as well as ON current to OFF current ratio of more than 105. The effects of several design parameters such as doping profile, gate workfunction, bandgap, and hetero-interface characteristics are investigated to improve the performance of the proposed devices. The proposed device offers high flexibility in terms of the design and optimization, and is suitable for digital logic applications. A complementary logic is developed based on the proposed device, which can be operated down to 200 mV of supply voltage. The complementary logic is used in design of an ultra-compact bi-stable switching static memory cell. Due to its compactness and high drive current, the proposed memory cell can outperform the conventional static random access memory cells in terms of switching speed and power consumption.

  5. Cellular signaling circuits interfaced with synthetic, post-translational, negating Boolean logic devices.

    PubMed

    Razavi, Shiva; Su, Steven; Inoue, Takanari

    2014-09-19

    A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top-down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers. PMID:25000210

  6. Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

    SciTech Connect

    Koga, R.; Crain, W.R.; Hansel, S.J.; Crawford, K.B.; Kirshman, J.F.; Pinkerton, S.D.; Penzin, S.H.; Moss, S.C.; Maher, M.

    1995-12-01

    This paper presents single event upset (SEU) and latchup test results for selected Emitter Coupled Logic (ECL) microcircuits, including several types of low capacity SRAMs and other memory devices. The high speed of ECL memory devices makes them attractive for use in space applications. However, the emitter coupled transistor design increases susceptibility to radiation induced functional errors, especially SEU, because the transistors are not saturated, unlike the transistors in a CMOS device. Charge collection at the sensitive nodes in ECL memory elements differs accordingly. These differences are responsible, in part, for the heightened SEU vulnerability of ECL memory devices relative to their CMOS counterparts.

  7. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

    1991-01-01

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

  8. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

    1991-07-09

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

  9. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    PubMed Central

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-min; Lu, Meng

    2016-01-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively. PMID:26925828

  10. A programmable nanoreplica molding for the fabrication of nanophotonic devices.

    PubMed

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-Min; Lu, Meng

    2016-01-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively. PMID:26925828

  11. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    NASA Astrophysics Data System (ADS)

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-Min; Lu, Meng

    2016-03-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively.

  12. Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices

    NASA Astrophysics Data System (ADS)

    Cricchio, Dario; Fiordilino, Emilio

    2016-01-01

    We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device.

  13. Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices.

    PubMed

    Cricchio, Dario; Fiordilino, Emilio

    2016-01-28

    We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device. PMID:26662194

  14. Micromagnetic simulation of exploratory magnetic logic device with missing corner defect

    NASA Astrophysics Data System (ADS)

    Yang, Xiaokuo; Cai, Li; Zhang, Bin; Cui, Huanqing; Zhang, Mingliang

    2015-11-01

    Magnetic film nanostructures are attractive components of nonvolatile magnetoresistive memories and nanomagnet logic circuits. Recently, we studied switching properties (i.e., null logic preserving) of rectangle shape nanomagnet subjected to fabrication imperfections. Specifically, we presented typical missing corner material-related imperfections and adopted an isosceles triangle to model this defect for nanomagnets. Micromagnetic simulation shows that this kind of imperfections modeling method agrees well with previous experimental observations. Using the proposed defect modeling scheme, we investigate in detail the switching characteristics of different defective stand-alone and coupled nanomagnets. The results suggest that the state transition of defective nanomagnet element highly depends on defect type and device's aspect ratio, and the defect type Bd needs the largest coercive field, while the defect type D requires the largest null field for switching. These findings can provide key technical parameters and guides for nanomagnet logic circuit design.

  15. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    NASA Technical Reports Server (NTRS)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  16. Analysis of an nn+ low-high junction and the application to integrated injection logic devices

    NASA Astrophysics Data System (ADS)

    Gannon, T. L.

    1980-12-01

    The literature on pnn+ devices is reviewed with an itemization of the assumptions typically made as well as a derivation of the most widely accepted theory. These assumptions are analyzed separately with the aid of sample calculations made using numerical analysis. The effects associated with heavy doping and Auger recombination are introduced with the associated theories described. A computational approach for the analysis of nn+ is developed that provides excellent agreement with the more complex and rigorous numerical analysis. The basic operation of integrated injection logic is described along with a development of a d.c. model. The a.c. or transient analysis of an integrated injection logic device using a charge control model is discussed. An extended Ebers-Moll model is described with a technique for calculating the model parameters for diffusion capacitance determination. The numerical techniques utilized in the derivations as well as determining how heavy doping and Auger effects can be incorporated into the algorithm are considered.

  17. Spin-wave logic devices based on isotropic forward volume magnetostatic waves

    SciTech Connect

    Klingler, S. Pirro, P.; Brächer, T.; Leven, B.; Hillebrands, B.; Chumak, A. V.

    2015-05-25

    We propose the utilization of isotropic forward volume magnetostatic spin waves in modern wave-based logic devices and suggest a concrete design for a spin-wave majority gate operating with these waves. We demonstrate by numerical simulations that the proposed out-of-plane magnetized majority gate overcomes the limitations of anisotropic in-plane magnetized majority gates due to the high spin-wave transmission through the gate, which enables a reduced energy consumption of these devices. Moreover, the functionality of the out-of-plane majority gate is increased due to the lack of parasitic generation of short-wavelength exchange spin waves.

  18. CAMAC modular programmable function generator

    SciTech Connect

    Turner, G.W.; Suehiro, S.; Hendricks, R.W.

    1980-12-01

    A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve.

  19. A novel design-based global CDU metrology for 1X nm node logic devices

    NASA Astrophysics Data System (ADS)

    Yoon, Young-Keun; Chung, Dong H.; Kim, Min-Ho; Seo, Jung-Uk; Kim, Byung-Gook; Jeon, Chan-Uk; Hur, JiUk; Cho, Wonil; Yamamoto, Tetsuya

    2013-09-01

    As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view (FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics. For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in order to maximize the coverage area on a mask. In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its fundamental performance such as accuracy, repeatability, and correlation with other CD metrology

  20. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    SciTech Connect

    Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-17

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  1. A Novel 2-D Programmable Photonic Time Delay Device for MM-Wave Signal Processing Applications

    NASA Technical Reports Server (NTRS)

    Yao, X.; Maleki, L.

    1994-01-01

    We describe a novel programmable photonic true time delay device that has the properties of low loss, inherent two dimensionality with a packing density exceeding 25 lines/cm super 2, virtually infinite bandwidth, and is easy to manufacture.

  2. Programmable hardware for reconfigurable computing systems

    NASA Astrophysics Data System (ADS)

    Smith, Stephen

    1996-10-01

    In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

  3. Topological frustration in graphene nanoflakes: magnetic order and spin logic devices.

    PubMed

    Wang, Wei L; Yazyev, Oleg V; Meng, Sheng; Kaxiras, Efthimios

    2009-04-17

    Magnetic order in graphene-related structures can arise from size effects or from topological frustration. We introduce a rigorous classification scheme for the types of finite graphene structures (nanoflakes) which lead to large net spin or to antiferromagnetic coupling between groups of electron spins. Based on this scheme, we propose specific examples of structures that can serve as the fundamental (NOR and NAND) logic gates for the design of high-density ultrafast spintronic devices. We demonstrate, using ab initio electronic structure calculations, that these gates can in principle operate at room temperature with very low and correctable error rates. PMID:19518670

  4. Quantum logical gates with four-level superconducting quantum interference devices coupled to a superconducting resonator

    SciTech Connect

    He Xiaoling; Luo Junyan; Yang Chuiping; Li Sheng; Han Siyuan

    2010-08-15

    We propose a way for realizing a two-qubit controlled phase gate with superconducting quantum interference devices (SQUIDs) coupled to a superconducting resonator. In this proposal, the two lowest levels of each SQUID serve as the logical states and two intermediate levels of each SQUID are used for the gate realization. We show that neither adjustment of SQUID level spacings during the gate operation nor uniformity in SQUID parameters is required by this proposal. In addition, this proposal does not require the adiabatic passage or a second-order detuning and thus the gate is much faster.

  5. Remote Control Laboratory Using EJS Applets and TwinCAT Programmable Logic Controllers

    ERIC Educational Resources Information Center

    Besada-Portas, E.; Lopez-Orozco, J. A.; de la Torre, L.; de la Cruz, J. M.

    2013-01-01

    This paper presents a new methodology to develop remote laboratories for systems engineering and automation control courses, based on the combined use of TwinCAT, a laboratory Java server application, and Easy Java Simulations (EJS). The TwinCAT system is used to close the control loop for the selected plants by means of programmable logic…

  6. Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

    NASA Astrophysics Data System (ADS)

    Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

    2015-02-01

    A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer,a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

  7. Top coat less resist process development for contact layer of 40nm node logic devices

    NASA Astrophysics Data System (ADS)

    Fujita, Masafumi; Uchiyama, Takayuki; Furusho, Tetsunari; Otsuka, Takahisa; Tsuchiya, Katsuhiro

    2010-04-01

    ArF immersion lithography has been introduced in mass production of 55nm node devices and beyond as the post ArF dry lithography. Due to the existence of water between the resist film and lens, we have many concerns such as leaching of PAG and quencher from resist film into immersion water, resist film swelling by water, keeping water in the immersion hood to avoid water droplets coming in contact with the wafer, and so on. We have applied to the ArF dry resist process an immersion topcoat (TC) process in order to ensure the hydrophobic property as well as one for protecting the surface. We investigate the TC-less resist process with an aim to improve CoO, the yield and productivity in mass production of immersion lithography. In this paper, we will report TC-less resist process development for the contact layer of 40nm node logic devices. It is important to control the resist surface condition to reduce pattern defects, in particular in the case of the contact layer. We evaluated defectivity and lithography performance of TC-less resist with changing hydrophobicity before and after development. Hydrophobicity of TC-less resist was controlled by changing additives with TC functions introduced into conventional ArF dry resist. However, the hydrophobicity control was not sufficient to reduce the number of Blob defects compared with the TC process. Therefore, we introduced Advanced Defect Reduction (ADR) rinse, which was a new developer rinse technique that is effective against hydrophobic surfaces. We have realized Blob defect reduction by hydrophobicity control and ADR rinse. Furthermore, we will report device performance, yield, and immersion defect data at 40nm node logic devices with TC-less resist process.

  8. Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews

    PubMed Central

    Kneale, Dylan; Thomas, James; Harris, Katherine

    2015-01-01

    Background Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to ‘think’ conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. Methods and Findings In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Conclusions Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions. PMID:26575182

  9. Magnetic dipolar coupling and collective effects for binary information codification in cost-effective logic devices

    NASA Astrophysics Data System (ADS)

    Chiolerio, Alessandro; Allia, Paolo; Graziano, Mariagrazia

    2012-09-01

    Physical limitations foreshadow the eventual end to traditional Complementary Metal Oxide Semiconductor (CMOS) scaling. Therefore, interest has turned to various materials and technologies aimed to succeed to traditional CMOS. Magnetic Quantum dot Cellular Automata (MQCA) are one of these technologies. Working MQCA arrays require very complex techniques and an excellent control on the geometry of the nanomagnets and on the quality of the magnetic thin film, thus limiting the possibility for MQCA of representing a definite solution to cost-effective, high density and low power consumption device demand. Counter-intuitively, moving towards bigger sizes and lighter technologies it is still possible to develop multi-state logic devices, as we demonstrated, whose main advantage is cost-effectiveness. Applications may be seen in low cost logic devices where integration and computational power are not the main issue, eventually using flexible substrates and taking advantage of the intrinsic mechanical toughness of systems where long range interactions do not need wirings. We realized cobalt micrometric MQCA arrays by means of Electron Beam Lithography, exploiting cost-effective processes such as lift-off and RF sputtering that usually are avoided due to their low control on array geometry and film roughness. Information relative to the magnetic configuration of MQCA elements including their eventual magnetic interactions was obtained from Magnetic Force Microscope (MFM) images, enhanced by means of a numerical procedure and presented in differential maps. We report the existence of bi-stable magnetic patterns, as detected by MFM while sampling the z-component of magnetic induction field, arising from dipolar inter-element magnetostatic coupling, able to store and propagate binary information. This is achieved despite the array quality and element magnetic state, which are low and multi-domain, respectively. We discuss in detail shape, inter-element spacing and dot profile

  10. Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

    NASA Technical Reports Server (NTRS)

    Taylor, B.

    1990-01-01

    The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

  11. Crystalline Direction Dependence of Spin Precession Angle and Its Application to Complementary Spin Logic Devices.

    PubMed

    Park, Youn Ho; Kim, Hyung-Jun; Chang, Joonyeon; Choi, Heon-Jin; Koo, Hyun Cheol

    2015-10-01

    In a semiconductor channel, spin-orbit interaction is divided into two terms, Rashba and Dresselhaus effects, which are key phenomena for modulating spin precession angles. The direction of Rashba field is always perpendicular to the wavevector but that of Dresselhaus field depends on the crystal orientation. Based on the individual Rashba and Dresselhaus strengths, we calculate spin precession angles for various crystal orientations in an InAs quantum well structure. When the channel length is 1 μm, the precession angle is 550° for the [110] direction and 460° for the [1-10] direction, respectively. Using the two spin transistors with different crystal directions, which play roles of n- and p-type transistors in conventional charge transistors, we propose a complementary logic device. PMID:26726362

  12. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGESBeta

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  13. The use of programmable logic controllers (PLC) for rocket engine component testing

    NASA Technical Reports Server (NTRS)

    Nail, William; Scheuermann, Patrick; Witcher, Kern

    1991-01-01

    Application of PLCs to the rocket engine component testing at a new Stennis Space Center Component Test Facility is suggested as an alternative to dedicated specialized computers. The PLC systems are characterized by rugged design, intuitive software, fault tolerance, flexibility, multiple end device options, networking capability, and built-in diagnostics. A distributed PLC-based system is projected to be used for testing LH2/LOx turbopumps required for the ALS/NLS rocket engines.

  14. Light programmable organic transistor memory device based on hybrid dielectric

    NASA Astrophysics Data System (ADS)

    Ren, Xiaochen; Chan, Paddy K. L.

    2013-09-01

    We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

  15. Automated hotspot analysis with aerial image CD metrology for advanced logic devices

    NASA Astrophysics Data System (ADS)

    Buttgereit, Ute; Trautzsch, Thomas; Kim, Min-ho; Seo, Jung-Uk; Yoon, Young-Keun; Han, Hak-Seung; Chung, Dong Hoon; Jeon, Chan-Uk; Meyers, Gary

    2014-09-01

    Continuously shrinking designs by further extension of 193nm technology lead to a much higher probability of hotspots especially for the manufacturing of advanced logic devices. The CD of these potential hotspots needs to be precisely controlled and measured on the mask. On top of that, the feature complexity increases due to high OPC load in the logic mask design which is an additional challenge for CD metrology. Therefore the hotspot measurements have been performed on WLCD from ZEISS, which provides the benefit of reduced complexity by measuring the CD in the aerial image and qualifying the printing relevant CD. This is especially of advantage for complex 2D feature measurements. Additionally, the data preparation for CD measurement becomes more critical due to the larger amount of CD measurements and the increasing feature diversity. For the data preparation this means to identify these hotspots and mark them automatically with the correct marker required to make the feature specific CD measurement successful. Currently available methods can address generic pattern but cannot deal with the pattern diversity of the hotspots. The paper will explore a method how to overcome those limitations and to enhance the time-to-result in the marking process dramatically. For the marking process the Synopsys WLCD Output Module was utilized, which is an interface between the CATS mask data prep software and the WLCD metrology tool. It translates the CATS marking directly into an executable WLCD measurement job including CD analysis. The paper will describe the utilized method and flow for the hotspot measurement. Additionally, the achieved results on hotspot measurements utilizing this method will be presented.

  16. On the Spot: Using Mobile Devices for Listening and Speaking Practice on a French Language Programme

    ERIC Educational Resources Information Center

    Demouy, Valerie; Kukulska-Hulme, Agnes

    2010-01-01

    This paper presents and discusses the initial findings of a mobile language learning project undertaken in the context of an undergraduate distance-learning French language programme at The Open University (UK). The overall objective of the project was to investigate students' experiences when using their own portable devices for additional…

  17. Biophotonic logic devices based on quantum dots and temporally-staggered Förster energy transfer relays

    NASA Astrophysics Data System (ADS)

    Claussen, Jonathan C.; Algar, W. Russ; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G.; Medintz, Igor L.

    2013-11-01

    Integrating photonic inputs/outputs into unimolecular logic devices can provide significantly increased functional complexity and the ability to expand the repertoire of available operations. Here, we build upon a system previously utilized for biosensing to assemble and prototype several increasingly sophisticated biophotonic logic devices that function based upon multistep Förster resonance energy transfer (FRET) relays. The core system combines a central semiconductor quantum dot (QD) nanoplatform with a long-lifetime Tb complex FRET donor and a near-IR organic fluorophore acceptor; the latter acts as two unique inputs for the QD-based device. The Tb complex allows for a form of temporal memory by providing unique access to a time-delayed modality as an alternate output which significantly increases the inherent computing options. Altering the device by controlling the configuration parameters with biologically based self-assembly provides input control while monitoring changes in emission output of all participants, in both a spectral and temporal-dependent manner, gives rise to two input, single output Boolean Logic operations including OR, AND, INHIBIT, XOR, NOR, NAND, along with the possibility of gate transitions. Incorporation of an enzymatic cleavage step provides for a set-reset function that can be implemented repeatedly with the same building blocks and is demonstrated with single input, single output YES and NOT gates. Potential applications for these devices are discussed in the context of their constituent parts and the richness of available signal.

  18. A study of source mask optimization for logic device through experiment and simulations

    NASA Astrophysics Data System (ADS)

    Kim, Hyo-chan; Lee, Jeong-Hoon; Shin, Jong-Chan; Bae, Yong-Kug; Choi, Siyoung; Kang, Ho-Kyu

    2011-04-01

    Source and Mask co-Optimization (SMO) plays an increasingly important role in the advanced RETs required to continue shrinking designs in the low-k1 lithography regime. Instead of costly double pattering patterning techniques, SMO has been explored as an enabling technology for low-k1 design node. It is clear that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. In this work, source and mask shape for logic device have been optimized in order to improve process window of critical layouts which include complex 2D shape and dense contact. Tachyon SMO solution developed by BRION was introduced to obtain the optimization. In order to improve the accuracy of SMO model, AI blur which represents resist effect on wafer was considered during optimization. Based on simulation results, improvement in terms of process window as well as Mask Error Enhancement Factor (MEEF) was approximately 20 % in comparison with reference conditions. However, the corresponding experimental results should be investigated as the evidence of the performance SMO. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

  19. The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

    SciTech Connect

    Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J.

    2015-05-07

    All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

  20. The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

    NASA Astrophysics Data System (ADS)

    Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J.

    2015-05-01

    All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau-Lifshitz-Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

  1. Reliability concerns with logical constants in Xilinx FPGA designs

    SciTech Connect

    Quinn, Heather M; Graham, Paul; Morgan, Keith; Ostler, Patrick; Allen, Greg; Swift, Gary; Tseng, Chen W

    2009-01-01

    In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

  2. High-frequency programmable acoustic wave device realized through ferroelectric domain engineering

    SciTech Connect

    Ivry, Yachin E-mail: cd229@eng.cam.ac.uk; Wang, Nan; Durkan, Colm E-mail: cd229@eng.cam.ac.uk

    2014-03-31

    Surface acoustic wave devices are extensively used in contemporary wireless communication devices. We used atomic force microscopy to form periodic macroscopic ferroelectric domains in sol-gel deposited lead zirconate titanate, where each ferroelectric domain is composed of many crystallites, each of which contains many microscopic ferroelastic domains. We examined the electro-acoustic characteristics of the apparatus and found a resonator behavior similar to that of an equivalent surface or bulk acoustic wave device. We show that the operational frequency of the device can be tailored by altering the periodicity of the engineered domains and demonstrate high-frequency filter behavior (>8 GHz), allowing low-cost programmable high-frequency resonators.

  3. Development and Validation of a Miniature Programmable tDCS Device.

    PubMed

    Kouzani, Abbas Z; Jaberzadeh, Shapour; Zoghi, Maryam; Usma, Clara; Parastarfeizabadi, Mahboubeh

    2016-01-01

    Research is being conducted on the use of transcranial direct current stimulation (tDCS) for therapeutic effects, and also on the mechanisms through which such therapeutic effects are mediated. A bottleneck in the progress of the research has been the large size of the existing tDCS systems which prevents subjects from performing their daily activities. To help research into the principles, mechanisms, and benefits of tDCS, reduction of size and weight, improvement in simplicity and user friendliness, portability, and programmability of tDCS systems are vital. This paper presents a design for a low-cost, light-weight, programmable, and portable tDCS device. The device is head-mountable and can be concealed in a hat and worn on the head by the subject while receiving the stimulation. The strength of the direct current stimulation can be selected through a simple user interface. The device is constructed and its performance evaluated through bench and in vivo tests. The tests validated the operation of the device in inducing neuromodulatory changes in primary motor cortex, M1, through measuring excitability of dominant M1 of resting right first dorsal interosseus muscle by transcranial magnetic stimulation induced motor evoked potentials. It was observed that the tDCS device induced comparable neuromodulatory effects in M1 as the existing bulky tDCS systems. PMID:26285208

  4. Logic gates and antisense DNA devices operating on a translator nucleic Acid scaffold.

    PubMed

    Shlyahovsky, Bella; Li, Yang; Lioubashevski, Oleg; Elbaz, Johann; Willner, Itamar

    2009-07-28

    A series of logic gates, "AND", "OR", and "XOR", are designed using a DNA scaffold that includes four "footholds" on which the logic operations are activated. Two of the footholds represent input-recognition strands, and these are blocked by complementary nucleic acids, whereas the other two footholds are blocked by nucleic acids that include the horseradish peroxidase (HRP)-mimicking DNAzyme sequence. The logic gates are activated by either nucleic acid inputs that hybridize to the respective "footholds", or by low-molecular-weight inputs (adenosine monophosphate or cocaine) that yield the respective aptamer-substrate complexes. This results in the respective translocation of the blocking nucleic acids to the footholds carrying the HRP-mimicking DNAzyme sequence, and the concomitant release of the respective DNAzyme. The released product-strands then self-assemble into the hemin/G-quadruplex-HRP-mimicking DNAzyme that biocatalyzes the formation of a colored product and provides an output signal for the different logic gates. The principle of the logic operation is, then, implemented as a possible paradigm for future nanomedicine. The nucleic acid inputs that bind to the blocked footholds result in the translocation of the blocking nucleic acids to the respective footholds carrying the antithrombin aptamer. The released aptamer inhibits, then, the hydrolytic activity of thrombin. The system demonstrates the regulation of a biocatalytic reaction by a translator system activated on a DNA scaffold. PMID:19507821

  5. Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices

    NASA Astrophysics Data System (ADS)

    Suzuki, Daisuke; Natsui, Masanori; Mochizuki, Akira; Hanyu, Takahiro

    2014-01-01

    A 6-input nonvolatile logic element (NV-LE) using domain-wall motion (DWM) devices is presented for low-power and real-time reconfigurable logic LSI applications. Because the write current path of a DWM device is separated from its read current path and the resistance value of the write current path is quite small, multiple DWM devices can be reprogrammed in parallel, thus affording real-time logic-function reconfiguration within a few nanoseconds. Moreover, by merging a circuit component between combinational and sequential logic functions, transistor counts can be minimized. As a result, 2-ns 64-bit-parallel circuit reconfiguration is realized by the proposed 6-input NV-LE with 67% lesser area than a conventional CMOS-based alternative, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS/MTJ technologies.

  6. Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

    NASA Astrophysics Data System (ADS)

    Roy, Debapriya; Biswas, Abhijit

    2016-09-01

    Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4-0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

  7. Project W-058 monitor and control system logic

    SciTech Connect

    ROBERTS, J.B.

    1999-05-12

    This supporting document contains the printout of the control logic for the Project W-058 Monitor and Control System, as developed by Programmable Control Services, Inc. The logic is arranged in five appendices, one for each programmable logic controller console.

  8. Programmable digital memory devices based on nanoscale thin films of a thermally dimensionally stable polyimide.

    PubMed

    Lee, Taek Joon; Chang, Cha-Wen; Hahm, Suk Gyu; Kim, Kyungtae; Park, Samdae; Kim, Dong Min; Kim, Jinchul; Kwon, Won-Sang; Liou, Guey-Sheng; Ree, Moonhor

    2009-04-01

    We have fabricated electrically programmable memory devices with thermally and dimensionally stable poly(N-(N',N'-diphenyl-N'-1,4-phenyl)-N,N-4,4'-diphenylene hexafluoroisopropylidene-diphthalimide) (6F-2TPA PI) films and investigated their switching characteristics and reliability. 6F-2TPA PI films were found to reveal a conductivity of 1.0 x 10(-13)-1.0 x 10(-14) S cm(-1). The 6F-2TPA PI films exhibit versatile memory characteristics that depend on the film thickness. All the PI films are initially present in the OFF state. The PI films with a thickness of >15 to <100 nm exhibit excellent write-once-read-many-times (WORM) (i.e. fuse-type) memory characteristics with and without polarity depending on the thickness. The WORM memory devices are electrically stable, even in air ambient, for a very long time. The devices' ON/OFF current ratio is high, up to 10(10). Therefore, these WORM memory devices can provide an efficient, low-cost means of permanent data storage. On the other hand, the 100 nm thick PI films exhibit excellent dynamic random access memory (DRAM) characteristics with polarity. The ON/OFF current ratio of the DRAM devices is as high as 10(11). The observed electrical switching behaviors were found to be governed by trap-limited space-charge-limited conduction and local filament formation and further dependent on the differences between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels of the PI film and the work functions of the top and bottom electrodes as well as the PI film thickness. In summary, the excellent memory properties of 6F-2TPA PI make it a promising candidate material for the low-cost mass production of high density and very stable digital nonvolatile WORM and volatile DRAM memory devices. PMID:19420490

  9. Molecular implementation of simple logic programs

    NASA Astrophysics Data System (ADS)

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-11-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

  10. Molecular implementation of simple logic programs.

    PubMed

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-10-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation. PMID:19809454

  11. Stem-directed growth of highly fluorescent silver nanoclusters for versatile logic devices.

    PubMed

    Li, Jing; Jia, Xiaofang; Li, Dongyue; Ren, Jiangtao; Han, Yanchao; Xia, Yong; Wang, Erkang

    2013-07-01

    This work described for the first time the stem-directed growth of silver nanoclusters (AgNCs) with high brightness using the well-chosen hairpin DNA structure. In comparison with the corresponding double-stranded (ds) DNA capped AgNCs, the fluorescence emission of hairpin DNA structure templated AgNCs were lighted up with 12.5-fold enhancement fluorescent intensity by sequence modification with T-loop. It provided a new prospect for precise placement of nanoscale optical elements onto DNA scaffolds. And these DNA protected AgNCs exhibited the base sequence, strand length and microenvironment-dependent fluorescent properties. Benefiting from these properties, versatile logic gates (or, not, inhibit, XNOR, implication) were constructed using different ions as inputs with AgNCs as signal transducer. PMID:23728712

  12. Programmable immersive peripheral environmental system (PIPES): a prototype control system for environmental feedback devices

    NASA Astrophysics Data System (ADS)

    Frend, Chauncey; Boyles, Michael

    2015-03-01

    This paper describes an environmental feedback device (EFD) control system aimed at simplifying the VR development cycle. Programmable Immersive Peripheral Environmental System (PIPES) affords VR developers a custom approach to programming and controlling EFD behaviors while relaxing the required knowledge and expertise of electronic systems. PIPES has been implemented for the Unity engine and features EFD control using the Arduino integrated development environment. PIPES was installed and tested on two VR systems, a large format CAVE system and an Oculus Rift HMD system. A photocell based end-to-end latency experiment was conducted to measure latency within the system. This work extends previously unpublished prototypes of a similar design. Development and experiments described in this paper are part of the VR community goal to understand and apply environment effects to VEs that ultimately add to users' perceived presence.

  13. Sensor sentinel computing device

    DOEpatents

    Damico, Joseph P.

    2016-08-02

    Technologies pertaining to authenticating data output by sensors in an industrial environment are described herein. A sensor sentinel computing device receives time-series data from a sensor by way of a wireline connection. The sensor sentinel computing device generates a validation signal that is a function of the time-series signal. The sensor sentinel computing device then transmits the validation signal to a programmable logic controller in the industrial environment.

  14. Stem-directed growth of highly fluorescent silver nanoclusters for versatile logic devices

    NASA Astrophysics Data System (ADS)

    Li, Jing; Jia, Xiaofang; Li, Dongyue; Ren, Jiangtao; Han, Yanchao; Xia, Yong; Wang, Erkang

    2013-06-01

    This work described for the first time the stem-directed growth of silver nanoclusters (AgNCs) with high brightness using the well-chosen hairpin DNA structure. In comparison with the corresponding double-stranded (ds) DNA capped AgNCs, the fluorescence emission of hairpin DNA structure templated AgNCs were lighted up with 12.5-fold enhancement fluorescent intensity by sequence modification with T-loop. It provided a new prospect for precise placement of nanoscale optical elements onto DNA scaffolds. And these DNA protected AgNCs exhibited the base sequence, strand length and microenvironment-dependent fluorescent properties. Benefiting from these properties, versatile logic gates (OR, NOT, INHIBIT, XNOR, IMPLICATION) were constructed using different ions as inputs with AgNCs as signal transducer.This work described for the first time the stem-directed growth of silver nanoclusters (AgNCs) with high brightness using the well-chosen hairpin DNA structure. In comparison with the corresponding double-stranded (ds) DNA capped AgNCs, the fluorescence emission of hairpin DNA structure templated AgNCs were lighted up with 12.5-fold enhancement fluorescent intensity by sequence modification with T-loop. It provided a new prospect for precise placement of nanoscale optical elements onto DNA scaffolds. And these DNA protected AgNCs exhibited the base sequence, strand length and microenvironment-dependent fluorescent properties. Benefiting from these properties, versatile logic gates (OR, NOT, INHIBIT, XNOR, IMPLICATION) were constructed using different ions as inputs with AgNCs as signal transducer. Electronic supplementary information (ESI) available: DNA sequences used, Tm curves and spectra data of the obtained AgNCs. See DOI: 10.1039/c3nr00998j

  15. Customizable 3D Printed ‘Plug and Play’ Millifluidic Devices for Programmable Fluidics

    PubMed Central

    Tsuda, Soichiro; Jaffery, Hussain; Doran, David; Hezwani, Mohammad; Robbins, Phillip J.; Yoshida, Mari; Cronin, Leroy

    2015-01-01

    Three dimensional (3D) printing is actively sought after in recent years as a promising novel technology to construct complex objects, which scope spans from nano- to over millimeter scale. Previously we utilized Fused deposition modeling (FDM)-based 3D printer to construct complex 3D chemical fluidic systems, and here we demonstrate the construction of 3D milli-fluidic structures for programmable liquid handling and control of biological samples. Basic fluidic operation devices, such as water-in-oil (W/O) droplet generators for producing compartmentalized mono-disperse droplets, sensor-integrated chamber for online monitoring of cellular growth, are presented. In addition, chemical surface treatment techniques are used to construct valve-based flow selector for liquid flow control and inter-connectable modular devices for networking fluidic parts. As such this work paves the way for complex operations, such as mixing, flow control, and monitoring of reaction / cell culture progress can be carried out by constructing both passive and active components in 3D printed structures, which designs can be shared online so that anyone with 3D printers can reproduce them by themselves. PMID:26558389

  16. Vertically Stackable Novel One-Time Programmable Nonvolatile Memory Devices Based on Dielectric Breakdown Mechanism

    NASA Astrophysics Data System (ADS)

    Cho, Seongjae; Lee, Jung Hoon; Ryoo, Kyung-Chang; Jung, Sunghun; Lee, Jong-Ho; Park, Byung-Gook

    2011-12-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array structures based on silicon technology are proposed. There have been many features of OTP NVM devices utilizing various combinations of channel, breakdown region, barrier, and contact materials. However, this invention can be realized by simple materials and fabrication methods: it is silicon-based materials and fully compatible with the conventional CMOS process. An individual memory cell is a silicon diode vertically integrated. Historically, OTP memories were widely used for read-only-memory (ROM) in the central processing unit (CPU) of the computer systems. By implanting the nanoscale fabrication technology into the concept of OTP memory, innovative high-density NVM appliances for massive storage media becomes very promising. The program operation is performed by breaking down the thin oxide layer between pn doped structure and wordline (WL) and its state can be sensed by the leakage current through the broken oxide. Since this invention is based on neither transistor structure nor charge-based mechanism, it is highly reliable and functional for the ultra-large scale integration. The feasibility of its stacked array will be also checked.

  17. Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond

    NASA Astrophysics Data System (ADS)

    Kim, Jaeyoon; Lee, Sanghyeon; Rubin, J.; Kim, Moonkyung; Tiwari, Sandip

    2013-06-01

    After six decades of device size reduction and its efficient use through hierarchical design, semiconductor electronics and its use in integrated digital processing encounters two major conflicting constraints. From size reduction and their small collective behavior, i.e., from the bottom, these constraints include quantum effects, stochastic effects arising from discreteness and noise, and other probabilistic effects. From the large scale integration and their large ensemble behavior, i.e., from the top, these include thermodynamic consequences in the inefficiencies of the data engine as a large numbers of devices are assembled together hierarchically. These conflicting currents are the central intellectual challenge when discussing the future of nanostructure devices and their use in data processing machines. We discuss the conceptual fundamentals of the small and the large that ties these scale changes that exist in time, size, energy, and other dimensions of the machinery. From this, we derive ideas for devices, robustness, data manipulation efficiency, and performance under practical constraints so that the next six decades are as fruitful and useful for the society as the past six have been.

  18. An imidazolyl-pyreno-imidazole conjugate as a cyanide sensor and a set-reset memorized sequential logic device.

    PubMed

    Mardanya, Sourav; Karmakar, Srikanta; Mondal, Debiprasad; Baitalik, Sujoy

    2015-09-28

    In this work a pyrenyl-bisimidazole receptor has been synthesized and fully characterized by standard analytical tools and spectroscopic techniques including single crystal X-ray crystallography. Crystal structure analysis shows the occurrence of strong π-π and CH-π interactions among the adjacent Py-BiimzH2 units. Moreover, each NH proton on the imidazole ring is involved in strong intermolecular hydrogen bonding interactions with N atoms of the neighboring unit forming infinite chains. The absorption and both steady state and time-resolved emission properties of the compound were found to be modulated to a significant extent by selective inorganic anions and transition metal cations in solution. Theoretical calculations employing density functional theory (DFT) and time-dependent density functional theory (TD-DFT) were carried out and good correlation between the experimental and the TD-DFT calculated results led to the accurate assignment of the main absorption and emission bands of the original compound as well as its anionic and metal complexes. More importantly, the compound can act as an efficient ratiometric optical chemosensor for CN(-) in H2O-DMSO (9 : 1) media. The anion sensing properties of the receptor was thoroughly investigated in both neat DMSO as well as mixed H2O-DMSO (9 : 1) media through different channels. From the response profiles in terms of absorption or emission intensity and wavelength towards inorganic ions (Cu(2+) and CN(-)), we developed a molecular system which can mimic sequential Boolean logic functions of XOR, OR, XNOR and NOR logic gates. Moreover, we were able to construct a memory device which nicely demonstrates the "Write-Read-Erase-Read" behavior. PMID:26282824

  19. A programmable droplet-based microfluidic device applied to multiparameter analysis of single microbes and microbial communities

    PubMed Central

    Leung, Kaston; Zahn, Hans; Leaver, Timothy; Konwar, Kishori M.; Hanson, Niels W.; Pagé, Antoine P.; Lo, Chien-Chi; Chain, Patrick S.; Hallam, Steven J.; Hansen, Carl L.

    2012-01-01

    We present a programmable droplet-based microfluidic device that combines the reconfigurable flow-routing capabilities of integrated microvalve technology with the sample compartmentalization and dispersion-free transport that is inherent to droplets. The device allows for the execution of user-defined multistep reaction protocols in 95 individually addressable nanoliter-volume storage chambers by consecutively merging programmable sequences of picoliter-volume droplets containing reagents or cells. This functionality is enabled by “flow-controlled wetting,” a droplet docking and merging mechanism that exploits the physics of droplet flow through a channel to control the precise location of droplet wetting. The device also allows for automated cross-contamination-free recovery of reaction products from individual chambers into standard microfuge tubes for downstream analysis. The combined features of programmability, addressability, and selective recovery provide a general hardware platform that can be reprogrammed for multiple applications. We demonstrate this versatility by implementing multiple single-cell experiment types with this device: bacterial cell sorting and cultivation, taxonomic gene identification, and high-throughput single-cell whole genome amplification and sequencing using common laboratory strains. Finally, we apply the device to genome analysis of single cells and microbial consortia from diverse environmental samples including a marine enrichment culture, deep-sea sediments, and the human oral cavity. The resulting datasets capture genotypic properties of individual cells and illuminate known and potentially unique partnerships between microbial community members. PMID:22547789

  20. Ferrite logic reliability study

    NASA Technical Reports Server (NTRS)

    Baer, J. A.; Clark, C. B.

    1973-01-01

    Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)

  1. Fabrication of microfluidic devices using MeV ion beam Programmable Proximity Aperture Lithography (PPAL)

    NASA Astrophysics Data System (ADS)

    Gorelick, S.; Puttaraksa, N.; Sajavaara, T.; Laitinen, M.; Singkarat, S.; Whitlow, H. J.

    2008-05-01

    MeV ion beam lithography is a direct writing technique capable of producing microfluidic patterns and lab-on-chip devices with straight walls in thick resist films. In this technique a small beam spot of MeV ions is scanned over the resist surface to generate a latent image of the pattern. The microstructures in resist polymer can be then revealed using a chemical developer that removes exposed resist, while leaving unexposed resist unaffected. In our system the size of the rectangular beam spot is programmably defined by two L-shaped tantalum blades with well-polished edges. This allows rapid exposure of entire rectangular pattern elements up to 500 × 500 μm in one step. By combining different dimensions of the defining aperture with the sample movements relative to the beam spot, entire fluidic patterns with large reservoirs and narrow flow channels can be written over large areas in short time. Fluidic patterns were written in PMMA using 56 MeV 14N3+ and a 3 MeV 4He2+ beams from K130 cyclotron and a 1.7 MV Pelletron accelerators, respectively, at the University of Jyväskylä Accelerator Laboratory. The patterns were characterized using SEM, and the factors affecting patterns quality are discussed.

  2. A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

    PubMed

    Bayindir, Ramazan; Cetinceviz, Yucel

    2011-04-01

    This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications. PMID:21126739

  3. Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach

    NASA Astrophysics Data System (ADS)

    Nath Roy, Jitendra; Gayen, Dilip Kumar

    2007-08-01

    Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.

  4. Programmable Pulser

    NASA Technical Reports Server (NTRS)

    Baumann, Eric; Merolla, Anthony

    1988-01-01

    User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

  5. Architecture and data processing alternatives for the TSE computer. Volume 3: Execution of a parallel counting algorithm using array logic (Tse) devices

    NASA Technical Reports Server (NTRS)

    Metcalfe, A. G.; Bodenheimer, R. E.

    1976-01-01

    A parallel algorithm for counting the number of logic-l elements in a binary array or image developed during preliminary investigation of the Tse concept is described. The counting algorithm is implemented using a basic combinational structure. Modifications which improve the efficiency of the basic structure are also presented. A programmable Tse computer structure is proposed, along with a hardware control unit, Tse instruction set, and software program for execution of the counting algorithm. Finally, a comparison is made between the different structures in terms of their more important characteristics.

  6. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells

    NASA Astrophysics Data System (ADS)

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B.; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

    2016-06-01

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed ‘dual-layer’ device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing.

  7. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells.

    PubMed

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J; Kozicki, Michael N

    2016-06-24

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed 'dual-layer' device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing. PMID:27171505

  8. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  9. Label-free and enzyme-free platform for the construction of advanced DNA logic devices based on the assembly of graphene oxide and DNA-templated AgNCs

    NASA Astrophysics Data System (ADS)

    Fan, Daoqing; Zhu, Jinbo; Liu, Yaqing; Wang, Erkang; Dong, Shaojun

    2016-02-01

    DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator.DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator. Electronic supplementary information (ESI) available: Optimization experiments, Table S1, Fig. S1-S5 in ESI. See DOI: 10.1039/c6nr00032k

  10. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    PubMed Central

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-01-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency −70 cd A−1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices. PMID:27187936

  11. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    NASA Astrophysics Data System (ADS)

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-05-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A-1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices.

  12. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process.

    PubMed

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-01-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A(-1) under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices. PMID:27187936

  13. Digital Holographic Logic

    NASA Technical Reports Server (NTRS)

    Preston, K., Jr.

    1972-01-01

    The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

  14. Designing and simulation smart multifunctional continuous logic device as a basic cell of advanced high-performance sensor systems with MIMO-structure

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

    2015-01-01

    We have proposed a design and simulation of hardware realizations of smart multifunctional continuous logic devices (SMCLD) as advanced basic cells of the sensor systems with MIMO- structure for images processing and interconnection. The SMCLD realize function of two-valued, multi-valued and continuous logics with current inputs and current outputs. Such advanced basic cells realize function nonlinear time-pulse transformation, analog-to-digital converters and neural logic. We showed advantages of such elements. It's have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The conception of construction of SMCLD consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 50÷70 transistors, 1 PD and 1 LED makes the offered circuits quite compact. The simulation results of NOT, MIN, MAX, equivalence (EQ), normalize summation, averaging and other functions, that implemented SMCLD, showed that the level of logical variables can change from 0.1μA to 10μA for low-power consumption variants. The SMCLD have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V.

  15. Field programmable gate arrays: Evaluation report for space-flight application

    NASA Technical Reports Server (NTRS)

    Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

    1992-01-01

    Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

  16. Excitonic AND Logic Gates on DNA Brick Nanobreadboards

    PubMed Central

    2015-01-01

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

  17. Simulation of reconfigurable multifunctional continuous logic devices as advanced components of the next generation high-performance MIMO-systems for the processing and interconnection

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

    2013-12-01

    We consider design and modeling of hardware realizations of reconfigurable multifunctional continuous logic devices (R MCL D) as advanced components of the next generation high-performance MIMO-systems for the processing and interconnection. The R MCL D realize function of two-valued and continuous logics with current inputs and current outputs on the basis of CMOS current mirrors and circuits which realize the limited difference functions. We show advantages of such elements consisting in encoding of variables by the photocurrent levels, that allows easily providing optical inputs (by photo-detectors (PD)) and optical outputs (by LED). The conception of construction of R MCL D consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 55÷65 transistors, 1 PD and 1 LED makes the offered circuits quite compact and allows their integration in 1D and 2D arrays. In the presentation we consider the capabilities of the offered circuits, show the simulation results and possible prospects of application of the circuits in particular for time-pulse coding for multivalued, continuous, neuro-fuzzy and matrix logics. The simulation results of NOT, MIN, MAX, equivalence (EQ) and other functions, that implemented R MCL D, showed that the level of logical variables can change from 1 μA to 10 μA for low-power consumption variants. The base cell of the R MCL D have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V. Modeling of such cells in OrCad is made.

  18. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    PubMed Central

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-01-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

  19. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    NASA Astrophysics Data System (ADS)

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-02-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

  20. flexTMS--a novel repetitive transcranial magnetic stimulation device with freely programmable stimulus currents.

    PubMed

    Gattinger, Norbert; Moessnang, Georg; Gleich, Bernhard

    2012-07-01

    Transcranial magnetic stimulation (TMS) is able to noninvasively excite neuronal populations due to brief magnetic field pulses. The efficiency and the characteristics of stimulation pulse shapes influence the physiological effect of TMS. However, commercial devices allow only a minimum of control of different pulse shapes. Basically, just sinusoidal and monophasic pulse shapes with fixed pulse widths are available. Only few research groups work on TMS devices with controllable pulse parameters such as pulse shape or pulse width. We describe a novel TMS device with a full-bridge circuit topology incorporating four insulated-gate bipolar transistor (IGBT) modules and one energy storage capacitor to generate arbitrary waveforms. This flexible TMS (flexTMS ) device can generate magnetic pulses which can be adjusted with respect to pulse width, polarity, and intensity. Furthermore, the equipment allows us to set paired pulses with a variable interstimulus interval (ISI) from 0 to 20 ms with a step size of 10  μs. All user-defined pulses can be applied continually with repetition rates up to 30 pulses per second (pps) or, respectively, up to 100 pps in theta burst mode. Offering this variety of flexibility, flexTMS will allow the enhancement of existing TMS paradigms and novel research applications. PMID:22531742

  1. LOGSIM programmer's manual

    NASA Technical Reports Server (NTRS)

    Mitchell, C. L.; Taylor, J. F.

    1976-01-01

    A programmer's manual is reported for a Logic Simulator (LOGSIM) computer program that is a large capacity event simulator with the capability to accurately simulate the effects of certain unknown states, rise and fall times, and floating nodes in large scale metal oxide semiconductor logic circuits. A detailed description of the software with flow charts is included within the report.

  2. Radiation tolerant combinational logic cell

    NASA Technical Reports Server (NTRS)

    Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

    2009-01-01

    A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

  3. Origami-inspired active graphene-based paper for programmable instant self-folding walking devices

    PubMed Central

    Mu, Jiuke; Hou, Chengyi; Wang, Hongzhi; Li, Yaogang; Zhang, Qinghong; Zhu, Meifang

    2015-01-01

    Origami-inspired active graphene-based paper with programmed gradients in vertical and lateral directions is developed to address many of the limitations of polymer active materials including slow response and violent operation methods. Specifically, we used function-designed graphene oxide as nanoscale building blocks to fabricate an all-graphene self-folding paper that has a single-component gradient structure. A functional device composed of this graphene paper can (i) adopt predesigned shapes, (ii) walk, and (iii) turn a corner. These processes can be remote-controlled by gentle light or heating. We believe that this self-folding material holds potential for a wide range of applications such as sensing, artificial muscles, and robotics. PMID:26601135

  4. Study of design-based e-beam defect inspection for hotspot detection and process window characterization on 10nm logic device

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Halder, Sandip; Di Lorenzo, Paolo; Wang, Fei; Zhang, Pengcheng; Fang, Wei; Liu, Kevin; Jau, Jack

    2016-03-01

    With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.

  5. Introducing Exclusion Logic as a Deontic Logic

    NASA Astrophysics Data System (ADS)

    Evans, Richard

    This paper introduces Exclusion Logic - a simple modal logic without negation or disjunction. We show that this logic has an efficient decision procedure. We describe how Exclusion Logic can be used as a deontic logic. We compare this deontic logic with Standard Deontic Logic and with more syntactically restricted logics.

  6. FAST TRACK COMMUNICATION: Reversible arithmetic logic unit for quantum arithmetic

    NASA Astrophysics Data System (ADS)

    Kirkedal Thomsen, Michael; Glück, Robert; Axelsen, Holger Bock

    2010-09-01

    This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks.

  7. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    NASA Astrophysics Data System (ADS)

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-04-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1-3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top-down template definition with bottom-up three-dimensional nanoscale features.

  8. Solid-state non-volatile electronically programmable reversible variable resistance device

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni (Inventor); Thakoor, Sarita (Inventor); Daud, Taher (Inventor); Thakoor, Aniklumar P. (Inventor)

    1989-01-01

    A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.

  9. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    PubMed Central

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-01-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1–3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top–down template definition with bottom–up three-dimensional nanoscale features. PMID:25914024

  10. G(sup 4)FET Implementations of Some Logic Circuits

    NASA Technical Reports Server (NTRS)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  11. MLS, a magnetic logic simulator for magnetic bubble logic design

    NASA Astrophysics Data System (ADS)

    Kinsman, Thomas B.; Cendes, Zoltan J.

    1987-04-01

    A computer program that simulates the logic functions of magnetic bubble devices has been developed. The program uses a color graphics screen to display the locations of bubbles on a chip during operation. It complements the simulator previously developed for modeling bubble devices on the gate level [Smith et al., IEEE Trans. Magn. MAG-19, 1835 (1983); Smith and Kryder, ibid. MAG-21, 1779 (1985)]. This new tool simplifies the design and testing of bubble logic devices, and facilitates the development of complicated LSI bubble circuits. The program operation is demonstrated with the design of an in-stream faulty loop compensator using bubble logic.

  12. Interference of GSM mobile phones with communication between Cardiac Rhythm Management devices and programmers: A combined in vivo and in vitro study.

    PubMed

    Huang, Dong; Dong, Zhi-Feng; Chen, Yan; Wang, Fa-Bin; Wei, Zhi; Zhao, Wen-Bin; Li, Shuai; Liu, Ming-Ya; Zhu, Wei; Wei, Meng; Li, Jing-Bo

    2015-07-01

    To investigate interference, and how to avoid it, by high-frequency electromagnetic fields (EMFs) of Global System for Mobile Communications (GSM) mobile phone with communication between cardiac rhythm management devices (CRMs) and programmers, a combined in vivo and in vitro testing was conducted. During in vivo testing, GSM mobile phones interfered with CRM-programmer communication in 33 of 65 subjects tested (50.8%). Losing ventricle sensing was representative in this study. In terms of clinical symptoms, only 4 subjects (0.6%) felt dizzy during testing. CRM-programmer communication recovered upon termination of mobile phone communication. During in vitro testing, electromagnetic interference by high-frequency (700-950 MHz) EMFs reproducibly occurred in duplicate testing in 18 of 20 CRMs (90%). During each interference, the pacing pulse signal on the programmer would suddenly disappear while the synchronous signal was normal on the amplifier-oscilloscope. Simulation analysis showed that interference by radiofrequency emitting devices with CRM-programmer communication may be attributed to factors including materials, excitation source distance, and implant depth. Results suggested that patients implanted with CRMs should not be restricted from using GSM mobile phones; however, CRMs should be kept away from high-frequency EMFs of GSM mobile phone during programming. PMID:25864643

  13. Dispositional logic

    SciTech Connect

    Zadeh, L.A.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived. 7 references.

  14. Dispositional logic

    NASA Technical Reports Server (NTRS)

    Le Balleur, J. C.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

  15. Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

    NASA Astrophysics Data System (ADS)

    Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

    2016-03-01

    Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

  16. Teaching Logic.

    ERIC Educational Resources Information Center

    Dyrud, Marilyn A.

    To make introducing logic to college students in speech and expository writing classes more interesting, letters to the editor can be used to teach logical fallacies. Letters to the editor are particularly useful because they give students a sense of the community they live in (issues, concerns, and the spectrum of opinion), they are easily…

  17. Mechanical passive logic module

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay; Caulfield, H. John

    2015-02-01

    Nothing from nothing gives simple simile, but something from nothing is an interesting and challenging task. Adolf Lohmann once proposed 'do nothing machine' in optics, which only copies input to output. Passive logic module (PALM) is a special type of 'do nothing machine' which can converts inputs into one of 16 possible binary outputs. This logic module is not like the conventional irreversible one. It is a simple type of reversible Turing machine. In this manuscript we discussed and demonstrated PALM using mechanical movement of plane mirrors. Also we discussed the theoretical model of micro electro mechanical system (MEMS) based PALM in this manuscript. It may have several valuable properties such as passive operation (no need for nonlinear elements as other logic device require) and modular logic (one device implementing any Boolean logic function with simple internal changes). The result is obtained from the demonstration by only looking up the output. No calculation is required to get the result. Not only that, PALM is a simple type of the famous 'billiard ball machine', which also discussed in this manuscript.

  18. New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices

    NASA Astrophysics Data System (ADS)

    Conley, Will; Brunsvold, William R.; Buehrer, Fred; DellaGuardia, Ronald; Dobuzinsky, David; Farrell, Timothy R.; Ho, Hok; Katnani, Ahmad D.; Keller, Robin; Marsh, James T.; Muller, Paul; Nunes, Ronald; Ng, Hung Y.; Oberschmidt, James M.; Pike, Michael; Ryan, Deborah; Cotler-Wagner, Tina; Schulz, Ron; Ito, Hiroshi; Hofer, Donald C.; Breyta, Gregory; Fenzel-Alexander, Debra; Wallraff, Gregory M.; Opitz, Juliann; Thackeray, James W.; Barclay, George G.; Cameron, James F.; Lindsay, Tracy K.; Cronin, Michael F.; Moynihan, Matthew L.; Nour, Sassan; Georger, Jacque H., Jr.; Mori, Mike; Hagerty, Peter; Sinta, Roger F.; Zydowsky, Thomas M.

    1997-07-01

    This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.

  19. Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

    NASA Astrophysics Data System (ADS)

    Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2015-04-01

    Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

  20. Negative tone imaging (NTI) with KrF: extension of 248nm IIP lithography to under sub-20nm logic device

    NASA Astrophysics Data System (ADS)

    Oh, Tae-Hwan; Kim, Tae-Sun; Kim, Yura; Kim, Jahee; Heo, Sujeong; Youn, Bumjoon; Seo, Jaekyung; Yoon, Kwang-Sub; Choi, Byoung-il

    2013-03-01

    One of the most prospective alternative lithography ways prior to EUV implementation is the reverse imaging by means of a negative tone development (NTD) process with solvent-based developer. Contact and trench patterns can be printed in CAR (Chemically amplified resist) using a bright field mask through NTD development, and can give much better image contrast (NILS) than PTD process. Not only for contact or trench masks, but also pattering of IIP (Ion Implantation) layers whose mask opening ratio is less than 20% may get the benefit of NTD process, not only in the point of aerial imaging, but also in achievement of vertical resist profile, especially for post gate layers which have complex sub_topologies and nitride substrate. In this paper, we present applications for the NTD technique to IIP (Ion Implantation) layer lithography patterning, via KrF exposure, comparing the performance to that of the PTD process. Especially, to extend 248nm IIP litho to sub-20nm logic device, optimization of negative tone imaging (NTI) with KrF exposure is the main focus in this paper. With the special resin system designed for KrF NTD process, even sub 100nm half-pitch trench pattern can be defined with enough process margin and vertical resist profiles can be also obtained on the nitride substrate with KrF exposure.

  1. Description Logics

    NASA Astrophysics Data System (ADS)

    Baader, Franz

    Description Logics (DLs) are a well-investigated family of logic-based knowledge representation formalisms, which can be used to represent the conceptual knowledge of an application domain in a structured and formally well-understood way. They are employed in various application domains, such as natural language processing, configuration, and databases, but their most notable success so far is the adoption of the DL-based language OWL as standard ontology language for the semantic web.

  2. Programmable Pacemaker

    NASA Technical Reports Server (NTRS)

    1980-01-01

    St. Jude Medical's Cardiac Rhythm Management Division, formerly known as Pacesetter Systems, Inc., incorporated Apollo technology into the development of the programmable pacemaker system. This consists of the implantable pacemaker together with a physician's console containing the programmer and a data printer. Physician can communicate with patient's pacemaker by means of wireless telemetry signals transmitted through the communicating head held over the patient's chest. Where earlier pacemakers deliver a fixed type of stimulus once implanted, Programalith enables surgery free "fine tuning" of device to best suit the patient's changing needs.

  3. The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations

    NASA Astrophysics Data System (ADS)

    Lee, Junwoo; Suh, Dong Ik; Park, Wanjun

    2015-05-01

    The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.

  4. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers

    NASA Astrophysics Data System (ADS)

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-07-01

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations.For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr04069a

  5. Fully Electrical Read-Write Device Out of a Ferromagnetic Semiconductor

    NASA Astrophysics Data System (ADS)

    Mark, S.; Dürrenfeld, P.; Pappert, K.; Ebel, L.; Brunner, K.; Gould, C.; Molenkamp, L. W.

    2011-02-01

    We report the realization of a read-write device out of the ferromagnetic semiconductor (Ga,Mn)As as the first step to a fundamentally new information processing paradigm. Writing the magnetic state is achieved by current-induced switching and readout of the state is done by the means of the tunneling anisotropic magnetoresistance effect. This 1 bit demonstrator device can be used to design an electrically programmable memory and logic device.

  6. Fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lofti A.

    1988-01-01

    The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.

  7. Interlocked DNA nanostructures controlled by a reversible logic circuit.

    PubMed

    Li, Tao; Lohmann, Finn; Famulok, Michael

    2014-01-01

    DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

  8. Synthesizing Biomolecule-based Boolean Logic Gates

    PubMed Central

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2012-01-01

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

  9. New Approach on Logic Application of Ferroelectric Random Access Memory Technology

    NASA Astrophysics Data System (ADS)

    Takayama, Masao; Koyama, Shinzo; Nozawa, Hiroshi

    2002-11-01

    In this paper, a new approach is described to solve some problems that occur when ferroelectric random access memory (FeRAM) is applied to logic circuits, particularly RSA cryptography. Application of a programmable switch device to RSA-based cryptography processing circuits was explored. RSA-based cryptography processing circuits have been designed as code conversion circuits. The capacity of the code conversion programmable AND gate and FeRAM and the translation rate have been investigated as a function of bit length. As a result, a problem of huge capacity at the practical bit length can be predicted theoretically. To solve this problem, we propose a new scheme for circuits and a new algorithm of logic operation using the binomial theorem.

  10. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers.

    PubMed

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-08-01

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. PMID:27396871

  11. Helical logic

    NASA Astrophysics Data System (ADS)

    Merkle, Ralph C.; Drexler, K. Eric

    1996-12-01

    Helical logic is a theoretical proposal for a future computing technology using the presence or absence of individual electrons (or holes) to encode 1s and 0s. The electrons are constrained to move along helical paths, driven by a rotating electric field in which the entire circuit is immersed. The electric field remains roughly orthogonal to the major axis of the helix and confines each charge carrier to a fraction of a turn of a single helical loop, moving it like water in an Archimedean screw. Each loop could in principle hold an independent carrier, permitting high information density. One computationally universal logic operation involves two helices, one of which splits into two `descendant' helices. At the point of divergence, differences in the electrostatic potential resulting from the presence or absence of a carrier in the adjacent helix controls the direction taken by a carrier in the splitting helix. The reverse of this sequence can be used to merge two initially distinct helical paths into a single outgoing helical path without forcing a dissipative transition. Because these operations are both logically and thermodynamically reversible, energy dissipation can be reduced to extremely low levels. This is the first proposal known to the authors that combines thermodynamic reversibility with the use of single charge carriers. It is important to note that this proposal permits a single electron to switch another single electron, and does not require that many electrons be used to switch one electron. The energy dissipated per logic operation can very likely be reduced to less than 0957-4484/7/4/004/img5 at a temperature of 1 K and a speed of 10 GHz, though further analysis is required to confirm this. Irreversible operations, when required, can be easily implemented and should have a dissipation approaching the fundamental limit of 0957-4484/7/4/004/img6.

  12. Optically controllable molecular logic circuits

    NASA Astrophysics Data System (ADS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-07-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

  13. Optically controllable molecular logic circuits

    SciTech Connect

    Nishimura, Takahiro Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-07-06

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

  14. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to noninvasively change one or more...

  15. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to noninvasively change one or more...

  16. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  17. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  18. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  19. Low delay and area efficient soft error correction in arbitration logic

    DOEpatents

    Sugawara, Yutaka

    2013-09-10

    There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.

  20. Summary of Proton Test on the Quick Logic QL3025 at Indiana University

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

  1. Adaptive parallel logic networks

    NASA Technical Reports Server (NTRS)

    Martinez, Tony R.; Vidal, Jacques J.

    1988-01-01

    Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.

  2. Efficient G(sup 4)FET-Based Logic Circuits

    NASA Technical Reports Server (NTRS)

    Vatan, Farrokh

    2008-01-01

    A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

  3. An enzyme-free and resettable platform for the construction of advanced molecular logic devices based on magnetic beads and DNA.

    PubMed

    Zhang, Siqi; Wang, Kun; Huang, Congcong; Li, Zhenyu; Sun, Ting; Han, De-Man

    2016-08-25

    A series of multiple logic circuits based on magnetic beads and DNA are constructed to perform resettable nonarithmetic functions, including a digital comparator, 4-to-2 encoder and 2-to-3 decoder, 2-to-1 encoder and 1-to-2 decoder. The signal reporter is composed of a G-quadruplex/NMM complex and a AuNP-surface immobilized molecular beacon. It is the first time that the designed DNA-based nonarithmetic nanodevices can share the same DNA platform with a reset function, which has great potential application in information processing at the molecular level. Another novel feature of the designed system is that the developed nanodevices are operated on a simple DNA/magnetic bead platform and share a constant threshold setpoint without the assistance of any negative logic conversion. The reset function is realized by heating the output system and the magnetic separation of the computing modules. Due to the biocompatibility and design flexibility of DNA, these investigations may provide a new route towards the development of resettable advanced logic circuits in biological and biomedical fields. PMID:27524500

  4. Current Mode Logic Fan Out

    Energy Science and Technology Software Center (ESTSC)

    2011-05-07

    Current mode logic is used in high speed timing systems for particle accelerators due to the fast rise time of the electrical signal. This software provides the necessary documentation to produce multiple copies of a single input for distribution to multiple devices. This software supports the DOE mission by providing a method for producing high speed signals in accelerator timing systems.

  5. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    SciTech Connect

    Berger, Andrew J. Page, Michael R.; Young, Justin R.; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris; Jacob, Jan; Lewis, Jim; Wenzel, Lothar

    2014-12-15

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  6. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

    PubMed

    Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field. PMID:25554296

  7. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    NASA Astrophysics Data System (ADS)

    Berger, Andrew J.; Page, Michael R.; Jacob, Jan; Young, Justin R.; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  8. Slime mould processors, logic gates and sensors.

    PubMed

    Adamatzky, A

    2015-07-28

    A heterotic, or hybrid, computation implies that two or more substrates of different physical nature are merged into a single device with indistinguishable parts. These hybrid devices then undertake coherent acts on programmable and sensible processing of information. We study the potential of heterotic computers using slime mould acting under the guidance of chemical, mechanical and optical stimuli. Plasmodium of acellular slime mould Physarum polycephalum is a gigantic single cell visible to the unaided eye. The cell shows a rich spectrum of behavioural morphological patterns in response to changing environmental conditions. Given data represented by chemical or physical stimuli, we can employ and modify the behaviour of the slime mould to make it solve a range of computing and sensing tasks. We overview results of laboratory experimental studies on prototyping of the slime mould morphological processors for approximation of Voronoi diagrams, planar shapes and solving mazes, and discuss logic gates implemented via collision of active growing zones and tactile responses of P. polycephalum. We also overview a range of electronic components--memristor, chemical, tactile and colour sensors-made of the slime mould. PMID:26078344

  9. Majority logic gate for 3D magnetic computing.

    PubMed

    Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

    2014-08-22

    For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities. PMID:25073985

  10. Majority logic gate for 3D magnetic computing

    NASA Astrophysics Data System (ADS)

    Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

    2014-08-01

    For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states ‘0’ and ‘1.’ Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

  11. Queuing register uses fluid logic elements

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Queuing register /a multistage bit-shifting device/ uses a series of pure fluid elements to perform the required logic operations. The register has several stages of three-state pure fluid elements combined with two-input NOR gates.

  12. Programmable scan/read circuitry for charge coupled device imaging detectors. [spcecraft attitude control and star trackers

    NASA Technical Reports Server (NTRS)

    Salomon, P. M.; Smilowitz, K.

    1984-01-01

    A circuit for scanning and outputting the induced charges in a solid state charge coupled device (CCD) image detector is disclosed in an image detection system for use in a spacecraft attitude control system. The image detection system includes timing control circuitry for selectively controlling the output of the CCD detector so that video outputs are provided only with respect to induced charges corresponding to predetermined sensing element lines of the CCD detector. The timing control circuit and the analog to digital converter are controlled by a programmed microprocessor which defines the video outputs to be converted and further controls the timing control circuit so that no video outputs are provided during the delay associated with analog to digital conversion.

  13. Bilayer avalanche spin-diode logic

    NASA Astrophysics Data System (ADS)

    Friedman, Joseph S.; Fadel, Eric R.; Wessels, Bruce W.; Querlioz, Damien; Sahakian, Alan V.

    2015-11-01

    A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

  14. Bilayer avalanche spin-diode logic

    SciTech Connect

    Friedman, Joseph S. Querlioz, Damien; Fadel, Eric R.; Wessels, Bruce W.; Sahakian, Alan V.

    2015-11-15

    A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

  15. Synthetic Aperture Radar Image Formation in Reconfigurable Logic

    SciTech Connect

    DUDLEY,PETER A.

    2001-06-01

    This paper studies the implementation of polar format, synthetic aperture radar image formation in modern Field Programmable Gate Arrays (FPGA's). The polar format algorithm is described in rough terms and each of the processing steps is mapped to FPGA logic. This FPGA logic is analyzed with respect to throughput and circuit size for compatibility with airborne image formation.

  16. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  17. Adaptive parallel logic networks

    SciTech Connect

    Martinez, T.R.; Vidal, J.J.

    1988-02-01

    This paper presents a novel class of special purpose processors referred to as ASOCS (adaptive self-organizing concurrent systems). Intended applications include adaptive logic devices, robotics, process control, system malfunction management, and in general, applications of logic reasoning. ASOCS combines massive parallelism with self-organization to attain a distributed mechanism for adaptation. The ASOCS approach is based on an adaptive network composed of many simple computing elements (nodes) which operate in a combinational and asynchronous fashion. Problem specification (programming) is obtained by presenting to the system if-then rules expressed as Boolean conjunctions. New rules are added incrementally. In the current model, when conflicts occur, precedence is given to the most recent inputs. With each rule, desired network response is simply presented to the system, following which the network adjusts itself to maintain consistency and parsimony of representation. Data processing and adaptation form two separate phases of operation. During processing, the network acts as a parallel hardware circuit. Control of the adaptive process is distributed among the network nodes and efficiently exploits parallelism.

  18. Oscillatory Threshold Logic

    PubMed Central

    Borresen, Jon; Lynch, Stephen

    2012-01-01

    In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

  19. Using a Commercial Ethernet PHY Device in a Radiation Environment

    NASA Technical Reports Server (NTRS)

    Parks, Jeremy; Arani, Michael; Arroyo, Roberto

    2014-01-01

    This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

  20. LOGIC CIRCUIT

    DOEpatents

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  1. Fluid logic control circuit operates nutator actuator motor

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.

  2. Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

    NASA Astrophysics Data System (ADS)

    Shin, Sunhae; Rok Kim, Kyung

    2015-06-01

    In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

  3. Assembly For Moving a Robotic Device Along Selected Axes

    NASA Technical Reports Server (NTRS)

    Nowlin, Brentley Craig (Inventor); Koch, Lisa Danielle (Inventor)

    2001-01-01

    An assembly for moving a robotic device along selected axes includes a programmable logic controller (PLC) for controlling movement of the device along selected axes to effect movement of the device to a selected disposition. The PLC includes a plurality of single axis motion control modules, and a central processing unit (CPU) in communication with the motion control modules. A human-machine interface is provided for operator selection of configurations of device movements and is in communication with the CPU. A motor drive is in communication with each of the motion control modules and is operable to effect movement of the device along the selected axes to obtain movement of the device to the selected disposition.

  4. Fuzzy logic controller optimization

    DOEpatents

    Sepe, Jr., Raymond B; Miller, John Michael

    2004-03-23

    A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.

  5. Paraconsistent quantum logics

    NASA Astrophysics Data System (ADS)

    Chiara, Maria Luisa Dalla; Giuntini, Roberto

    1989-07-01

    Paraconsistent quantum logics are weak forms of quantum logic, where the noncontradiction and the excluded-middle laws are violated. These logics find interesting applications in the operational approach to quantum mechanics. In this paper, we present an axiomatization, a Kripke-style, and an algebraic semantical characterization for two forms of paraconsistent quantum logic. Further developments are contained in Giuntini and Greuling's paper in this issue.

  6. Configuration and debug of field programmable gate arrays using MATLAB®/SIMULINK®

    NASA Astrophysics Data System (ADS)

    Grout, I.; Ryan, J.; O'Shea, T.

    2005-01-01

    Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB® model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB® model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK® model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use.

  7. OncoLogicTM

    EPA Science Inventory

    OncoLogicTM - A Computer System to Evaluate the Carcinogenic Potential of Chemicals
    OncoLogicTM is a software program that evaluates the likelihood that a chemical may cause cancer. OncoLogicTM has been peer reviewed and is being rele...

  8. Nonlinear dynamics based digital logic and circuits

    PubMed Central

    Kia, Behnam; Lindner, John. F.; Ditto, William L.

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096

  9. Nonlinear dynamics based digital logic and circuits.

    PubMed

    Kia, Behnam; Lindner, John F; Ditto, William L

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096

  10. Fuzzy logic control for an automated guided vehicle

    NASA Astrophysics Data System (ADS)

    Cao, Ming; Hall, Ernest L.

    1998-10-01

    This paper describes the use of fuzzy logic control for the high level control systems of a mobile robot. The advantages of the fuzzy logic system are that multiple types of input such as that from vision and sonar sensors as well as stored map information can be used to guide the robot. Sensor fusion can be accomplished between real time sensed information and stored information in a manner similar to a human decision maker. Vision guidance is accomplished with a CCD camera with a zoom lens. The data is collected through a commercial tracking device, communicating to the computer the X,Y coordinates of a lane marker. Testing of these systems yielded positive results by showing that at five miles per hour, the vehicle can follow a line and avoid obstacles. The obstacle detection uses information from Polaroid sonar detection system. The motor control system uses a programmable Galil motion control system. This design, in its modularity, creates a portable autonomous controller that could be used for any mobile vehicle with only minor adaptations.