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Sample records for programmable logic devices

  1. Fuzzy logic and coarse coding using programmable logic devices

    NASA Astrophysics Data System (ADS)

    Brooks, Geoffrey

    2009-05-01

    Naturally-occurring sensory signal processing algorithms, such as those that inspired fuzzy-logic control, can be integrated into non-naturally-occurring high-performance technology, such as programmable logic devices, to realize novel bio-inspired designs. Research is underway concerning an investigation into using field programmable logic devices (FPLD's) to implement fuzzy logic sensory processing. A discussion is provided concerning the commonality between bio-inspired fuzzy logic algorithms and coarse coding that is prevalent in naturally-occurring sensory systems. Undergraduate design projects using fuzzy logic for an obstacle-avoidance robot has been accomplished at our institution and other places; numerous other successful fuzzy logic applications can be found as well. The long-term goal is to leverage such biomimetic algorithms for future applications. This paper outlines a design approach for implementing fuzzy-logic algorithms into reconfigurable computing devices. This paper is presented in an effort to connect with others who may be interested in collaboration as well as to establish a starting point for future research.

  2. Electronic systems miniaturization using programmable logic devices

    SciTech Connect

    Ashton, E.C.; Bergeson, G.C.

    1990-10-01

    This report describes the steps which were taken to miniaturize a target circuit using Erasable Programmable Logic Devices (EPLDs). The original objective of this project was to explore the miniaturization of a circuit using both Application Specific Integrated Circuits (ASICs) and EPLDs to meet the following goals: balance cost and circuit density; reduce fabrication time; improve quality control issues by keeping much of the design in-house; and eliminate security risks by partitioning the design into ASIC and PLD (EPLD) sections. Due to cost considerations, the target circuit was miniaturized using only PLDs. The results of this project indicate that PLDs are capable of realizing fairly dense circuitry, are considerably less expensive than ASICs (by a factor of 500--1000), and are able to eliminate security risks and reduce fabrication time by keeping the design completely in-house.

  3. Table-top mirror based parallel programmable optical logic device

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay

    2014-12-01

    Light rays can easily be reflected to different path by mechanical movement of mirrors. Using this basic operational principle we can design parallel programmable optical logic device (PPOLD) by arranging mirrors on a table. The ‘table-top mirror' models of this proposed circuit have been shown here. We can program it to design all the two input 16-Boolean logical expressions from a single design. The design is based on only plane mirrors. No active optical material is used in this design. Not only that the proposed circuit is optically reversible in nature. Moreover this design is very simple in sense. It can be fabricated in MEMS based optical switches.

  4. Preface of the "Symposium on Logic Synthesis for Programmable Logic Devices"

    NASA Astrophysics Data System (ADS)

    Kania, Dariusz

    2015-12-01

    Logic synthesis is an indirect link between design description and technology mapping. In the result of synthesis process an implementation in terms of an interconnection of logic gates, flip-flops, LUTs, etc. is generated. Typically, synthesis is performed for an objective function, such as minimizing the number of logic blocks (area), delay of interconnection, minimizing the power consumed, or making the implementation more testable. Logic synthesis is typically separated into two stages: technology-independent optimization, followed by a technology mapping. Technology mapping is the process of expressing a boolean network in terms of elements characteristic for a given technology (or device family). The aim of the symposium is to show all aspects of logic synthesis dedicated for Programmable Logic Devices.

  5. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm

  6. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

  7. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

  8. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.

  9. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.

  10. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    2000-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.

  11. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Day, John H. (Technical Monitor)

    2001-01-01

    This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

  12. A novel productivity-driven logic element for field-programmable devices

    NASA Astrophysics Data System (ADS)

    Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

    2014-06-01

    Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

  13. Flexible programmable logic module

    SciTech Connect

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  14. Programmable Logic Application Notes

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1999-01-01

    This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.

  15. Programmable Logic Controllers.

    ERIC Educational Resources Information Center

    Insolia, Gerard; Anderson, Kathleen

    This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…

  16. A complex programmable logic device-based high-precision electrical capacitance tomography system

    NASA Astrophysics Data System (ADS)

    Zhou, Haili; Xu, Lijun; Cao, Zhang; Liu, XiaoLei; Liu, Shi

    2013-07-01

    In this paper, a high-precision measurement system for electrical capacitance tomography (ECT) is presented. A low-cost complex programmable logic device (CPLD) is employed to accomplish logic control, signal generation, data acquisition, digital demodulation and communication with the aid of external components. By adopting a simple digital demodulator recently developed by the authors, the demodulation to ac signals becomes rather simple and resource-saving. A double-T-switches configuration is developed to improve the precision and lower the limit of multi-channel capacitance measurement. A capacitance network is constructed for system calibration. A square ECT sensor with 16 electrodes is constructed to test the practical performance of the measurement system. With a data acquisition rate of 185 frame s-1, the signal-to-noise ratio and standard deviation of capacitance measurement can reach up to 70 dB and 0.09 fF, respectively. Image reconstruction experiment has validated the CPLD-based ECT system.

  17. Software Safety Assurance of Programmable Logic

    NASA Technical Reports Server (NTRS)

    Berens, Kalynnda

    2002-01-01

    Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

  18. Programmable Logic Controllers. Teacher Edition.

    ERIC Educational Resources Information Center

    Rauh, Bob; Kaltwasser, Stan

    These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…

  19. Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

    NASA Technical Reports Server (NTRS)

    Darrin, Ann Garrison; Conde, Richard; Chern, Bobbie; Luers, Phil; Jurczyk, Steve; Mills, Carl; Day, John H. (Technical Monitor)

    2001-01-01

    The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of

  20. Implementation of field programmable logic arrays. Final report

    SciTech Connect

    Anderson, J.D.

    1981-03-01

    Field Programmable Logic Arrays (FPLAs) were incorporated into a fire set tester and a development tester used to test a signal generator's logic boards. Other circuits were designed using the FPLA in code conversion and sequential control applications. A Curtiss Electro Devices FPLA programmer was purchased to program Signetics 82S100 and 82S101 devices.

  1. Microelectromechanical reprogrammable logic device

    PubMed Central

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  2. Microelectromechanical reprogrammable logic device.

    PubMed

    Hafiz, M A A; Kosuru, L; Younis, M I

    2016-01-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

  3. Microelectromechanical reprogrammable logic device

    NASA Astrophysics Data System (ADS)

    Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

    2016-03-01

    In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

  4. Benchmarking emerging logic devices

    NASA Astrophysics Data System (ADS)

    Nikonov, Dmitri

    2014-03-01

    As complementary metal-oxide-semiconductor field-effect transistors (CMOS FET) are being scaled to ever smaller sizes by the semiconductor industry, the demand is growing for emerging logic devices to supplement CMOS in various special functions. Research directions and concepts of such devices are overviewed. They include tunneling, graphene based, spintronic devices etc. The methodology to estimate future performance of emerging (beyond CMOS) devices and simple logic circuits based on them is explained. Results of benchmarking are used to identify more promising concepts and to map pathways for improvement of beyond CMOS computing.

  5. Universal programmable logic gate and routing method

    NASA Technical Reports Server (NTRS)

    Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

    2009-01-01

    An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

  6. Design of a Ferroelectric Programmable Logic Gate Array

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Ho, Fat Duen

    2003-01-01

    A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

  7. Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

    ERIC Educational Resources Information Center

    Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

    2009-01-01

    Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

  8. Implementing neural nets with programmable logic

    NASA Technical Reports Server (NTRS)

    Vidal, Jacques J.

    1988-01-01

    Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

  9. High-speed, cascaded optical logic operations using programmable optical logic gate arrays

    SciTech Connect

    Lu, B.; Lu, Y.C.; Cheng, J.; Hafich, M.J.; Klem, J.; Zolper, J.C.

    1996-01-01

    Programmable optical logic operations are demonstrated using arrays of nonlatching binary optical switches consisting of vertical-cavity surface-emitting lasers, p-i-n photodetectors and heterojunction bipolar transistors. Individual arrays can perform Boolean optical logic functions at 100 Mb/s using both optical and electrical logic inputs, while the routing and fan-out of the optical logic outputs can be controlled at the gate level. Cascaded optical logic operation is demonstrated using two programmable logic gate arrays.

  10. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  11. Reversible logic gate using adiabatic superconducting devices

    PubMed Central

    Takeuchi, N.; Yamanashi, Y.; Yoshikawa, N.

    2014-01-01

    Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of the problems is that reversible logic gates must be built by using extremely energy-efficient logic devices. Another difficulty is that reversible logic gates must be both logically and physically reversible. Here we propose the first practical reversible logic gate using adiabatic superconducting devices and experimentally demonstrate the logical and physical reversibility of the gate. Additionally, we estimate the energy dissipation of the gate, and discuss the minimum energy dissipation required for reversible logic operations. It is expected that the results of this study will enable reversible computing to move from the theoretical stage into practical usage. PMID:25220698

  12. Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

    ERIC Educational Resources Information Center

    Debiec, P.; Byczuk, M.

    2011-01-01

    Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these laboratories.…

  13. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  14. Multifunction minimization for programmable logic arrays

    SciTech Connect

    Campbell, J.A.

    1984-01-01

    The problem of minimizing two-level AND/OR Boolean algebraic functions of n inputs and m outputs for implementation on programmable logic arrays (PLA) is examined. The theory of multiple-output functions as well as the historically alternative approaches to reckoning the cost of an equation implementation are reviewed. The PLA is shown to be a realization of the least product gate equation cost criterion. The multi-function minimization is dealt with in the context of a directed tree search algorithm developed in previous research. The PLA oriented minimization is shown to alter the nature of each of the basic tenets of multiple-output minimization used in earlier work. The concept of a non-prime but selectable implicant is introduced. A new cost criterion, the quantum cost, is discussed, and an approximation algorithm utilizing this criterion is developed. A timing analysis of a cyclic resolution algorithm for PLA based functions is presented. Lastly, the question of efficiency in automated minimization algorithms is examined. The application of the PLA cost criterion is shown to exhibit intrinsic increases in computational efficiency. A minterm classification algorithm is suggested and a PLA minimization algorithm is implemented in the FORTRAN language.

  15. Hybrid Programmable Logic Controller for Load Automation

    NASA Astrophysics Data System (ADS)

    Shahzad, Aamir; Farooq, Hashim; Abbar, Sofia; Yousaf, Mushtaq; Hafeez, Kamran; Hanif, M.

    The purpose of this study is to design a Programmable Logic Controller (PLC) to command 8-relays to control and automate ac loads via PC parallel port. In this project, the PLC is connected to the Personal Computer called hybrid PLC and this PC controls all the field ac loads via parallel printer port. Eight signals of different sequences are sent on parallel port via computer keyboard, which activate the microcontroller as inputs. Microcontroller responds according to these inputs and its user programming, which then commands 8-relays to control (on/off) different electronic appliances. Microcontroller memory makes easier to store its programming permanently. This hybrid PLC is applicable for controlling and monitoring industrial processes particularly of small to medium scale manufacturing processes and may be used for home automation as well. Parallel port is accessed by a program written in C++ language and microcontroller is programmed in assembly language. Ac load of any kind, whether resistive or inductive can be controlled with the help of this project.

  16. Logic and structured design for computer programmers

    SciTech Connect

    Rood, H.J.

    1985-01-01

    This text provides a language- and system-independent introduction to logical structures, and teaches logic plus the programming and data processing applications in which logic is used. The author has eliminated the need to cover basic program design at the beginning of every language course, and has used logic of sets, Boolean algebra, conditional statements, and truth tables to establish logic of structure flowchart, pseudocode, Warnier/Orr diagrams, and so on. After chapter three, the chapters are independent so that instructors can select the coverage of programming tools and techniques most relevant to their students.

  17. Programmable ubiquitous telerobotic devices

    NASA Astrophysics Data System (ADS)

    Doherty, Michael; Greene, Matthew; Keaton, David; Och, Christian; Seidl, Matthew L.; Waite, William; Zorn, Benjamin G.

    1997-12-01

    We are investigating a field of research that we call ubiquitous telepresence, which involves the design and implementation of low-cost robotic devices that can be programmed and operated from anywhere on the Internet. These devices, which we call ubots, can be used for academic purposes (e.g., a biologist could remote conduct a population survey), commercial purposes (e.g., a house could be shown remotely by a real-estate agent), and for recreation and education (e.g., someone could tour a museum remotely). We anticipate that such devices will become increasingly common due to recent changes in hardware and software technology. In particular, current hardware technology enables such devices to be constructed very cheaply (less than $500), and current software and network technology allows highly portable code to be written and downloaded across the Internet. In this paper, we present our prototype system architecture, and the ubot implementation we have constructed based on it. The hardware technology we use is the handy board, a 6811-based controller board with digital and analog inputs and outputs. Our software includes a network layer based on TCP/IP and software layers written in Java. Our software enables users across the Internet to program the behavior of the vehicle and to receive image feedback from a camera mounted on it.

  18. Magnetic tunnel junction based spintronic logic devices

    NASA Astrophysics Data System (ADS)

    Lyle, Andrew Paul

    The International Technology Roadmap for Semiconductors (ITRS) predicts that complimentary metal oxide semiconductor (CMOS) based technologies will hit their last generation on or near the 16 nm node, which we expect to reach by the year 2025. Thus future advances in computational power will not be realized from ever-shrinking device sizes, but rather by 'outside the box' designs and new physics, including molecular or DNA based computation, organics, magnonics, or spintronic. This dissertation investigates magnetic logic devices for post-CMOS computation. Three different architectures were studied, each relying on a different magnetic mechanism to compute logic functions. Each design has it benefits and challenges that must be overcome. This dissertation focuses on pushing each design from the drawing board to a realistic logic technology. The first logic architecture is based on electrically connected magnetic tunnel junctions (MTJs) that allow direct communication between elements without intermediate sensing amplifiers. Two and three input logic gates, which consist of two and three MTJs connected in parallel, respectively were fabricated and are compared. The direct communication is realized by electrically connecting the output in series with the input and applying voltage across the series connections. The logic gates rely on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin transfer torque switching the output. The change in resistance at the input resulted in a voltage margin of 50--200 mV and 250--300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three input logic function realizes the Majority, AND, NAND, NOR, and OR logic operations. The second logic architecture utilizes magnetostatically coupled nanomagnets to compute logic functions, which is the basis of

  19. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.; Paolini, W.; Sin, B.

    1998-01-01

    State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

  20. Current Radiation Issues for Programmable Elements and Devices

    NASA Technical Reports Server (NTRS)

    Katz, R.; Wang, J. J.; Koga, R.; LaBel, K. A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.; Paolini, W.; Sin, B.

    1998-01-01

    State of the an programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers' modifications to their COTS-based and their impact on future programmable devices will be analyzed.

  1. Pathway to the Piezoelectronic Transduction Logic Device

    NASA Astrophysics Data System (ADS)

    Solomon, P. M.; Bryce, B. A.; Kuroda, M. A.; Keech, R.; Shetty, S.; Shaw, T. M.; Copel, M.; Hung, L.-W.; Schrott, A. G.; Armstrong, C.; Gordon, M. S.; Reuter, K. B.; Theis, T. N.; Haensch, W.; Rossnagel, S. M.; Miyazoe, H.; Elmegreen, B. G.; Liu, X.-H.; Trolier-McKinstry, S.; Martyna, G. J.; Newns, D. M.

    2015-04-01

    The information age challenges computer technology to process an exponentially increasing computational load on a limited energy budget - a requirement that demands an exponential reduction in energy per operation. In digital logic circuits, the switching energy of present FET devices is intimately connected with the switching voltage, and can no longer be lowered sufficiently, limiting the ability of current technology to address the challenge. Quantum computing offers a leap forward in capability, but a clear advantage requires algorithms presently developed for only a small set of applications. Therefore, a new, general purpose, classical technology based on a different paradigm is needed to meet the ever increasing demand for data processing.

  2. Magnetic tunnel junction based spintronic logic and memory devices

    NASA Astrophysics Data System (ADS)

    Yao, Xiaofeng

    2011-12-01

    The development of semiconductor devices is limited by the high power consumption and further physical dimension reduction. Spintronic devices, especially the magnetic tunnel junction (MTJ) based devices, have advantages of non-volatility, reconfigurable capability, fast-switching speed, small-dimension, and compatibility to semiconductor devices, which is a promising candidate for future logic and memory devices. However, the previously proposed MTJ logic devices have been operated independently and therefore are limited to only basic logic operations. Consequently, the MTJ device has only been used as ancillary device in the circuit, rather than the main computation component. In this thesis, study has been done on both spintronic logic and memory devices. In the first part, systematic study has been performed on MTJ based logic devices in order to expand the functionalities and properties of MTJ devices. Basic logic cell with three-input has been designed and simulated. Nano-magnetic-channel has been proposed, which is the first design to realize the communication between the MTJ logic cells. With basic logic unit as a building block, a spintronic logic circuit has been designed with MTJ as the dominant component. HSPICE simulation has been done for this spintronic logic circuit, which acts as an Arithmetic Logic Unit. In the spintronic memory device part, study has been focused on the fundamental study on the current induced switching in MTJ devices with hybrid free layer. With hybrid free layer, magnetic non-uniformity is introduced along the current direction, which induces extra spin torque component. Unique current-induced switching has been observed and studied in the hybrid free layer MTJ. Adiabatic spin torque, which is introduced by spatial non-uniform magnetization in the hybrid free layer, plays an important role for the unique switching. By tuning the bias field, single-polar current switching was achieved in this hybrid MTJ device, which gives the

  3. Applying programmable logic controllers to safety-related systems

    SciTech Connect

    Ruether, J.C. )

    1992-01-01

    Northern States Power Company (NSP) recently installed programmable logic controllers (PLCs) in two safety-related systems at its Prairie Island nuclear generating plant. The lessons learned during these applications at the 19-yr old two-unit plant may benefit similar projects. Prairie Island responded to the station black out (SBO) issue by upgrading its electrical distribution system. This included installing additional safeguard diesel generators (DGs), new 4160-V buses, and new 480-V buses. As part of this upgrade, PLCs were commercially dedicated for use in two safety-related applications: (1) bus load sequencer project, (2) 480-V voltage regulator project.

  4. Building and using a highly parallel programmable logic array

    SciTech Connect

    Gokhale, M.; Holmes, W.; Kopser, A.; Lucas, S.; Minnich, R.; Sweely, D. ); Lopresti, D. )

    1991-01-01

    With a $13,000 two-slot addition called Splash, a Sun workstation can outperform a Cray-2 on certain applications. Several applications, most involving bit-stream computations, have been run on Splash, which received a 1989 Gordon Bell Prize honorable mention for timings on a problem that compared a new DNA sequence against a library of sequences to find the closest match. In essence, Splash is a programmable linear logic array that can be configured to suit the problem at hand; it bridges the gap between the traditional fixed-function VLSI systolic array and the more versatile programmable array. As originally conceived, a systolic array is a collection of simple processing elements, along with a one- or two-dimensional nearest-neighbor communication pattern. The local nature of the communication gives the systolic array a high communications bandwidth, and the simple, fixed function gives a high packing density for VLSI implementation.

  5. Development of ferrite logic devices for an arithmetic processor

    NASA Technical Reports Server (NTRS)

    Heckler, C. H., Jr.

    1972-01-01

    A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.

  6. Sandia ATM SONET Interface Logic

    Energy Science and Technology Software Center (ESTSC)

    1994-07-21

    SASIL is used to program the EPLD's (Erasable Programmable Logic Devices) and PAL's (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  7. Improving immunization of programmable logic controllers using weighted median filters.

    PubMed

    Paredes, José L; Díaz, Dhionel

    2005-04-01

    This paper addresses the problem of improving immunization of programmable logic controllers (PLC's) to electromagnetic interference with impulsive characteristics. A filtering structure, based on weighted median filters, that does not require additional hardware and can be implemented in legacy PLC's is proposed. The filtering operation is implemented in the binary domain and removes the impulsive noise presented in the discrete input adding thus robustness to PLC's. By modifying the sampling clock structure, two variants of the filter are obtained. Both structures exploit the cyclic nature of the PLC to form an N-sample observation window of the discrete input, hence a status change on it is determined by the filter output taking into account all the N samples avoiding thus that a single impulse affects the PLC functionality. A comparative study, based on a statistical analysis, of the different filters' performances is presented. PMID:15868861

  8. The programmable (logic) controller: Adapting in an environment of change

    SciTech Connect

    Levine, P.S.

    1995-03-01

    Reports of the imminent death of the PLC (programmable logic controller) were greatly exaggerated, to paraphrase Mark Twain. In fact, the PLC is not only alive and working worldwide in thousands of applications, but it is also integrating well with related technologies. Long-term survival is a larger question - probably unanswerable given the pace of technological change. However, a few questions arise about the PLC today and in the immediate future: (1) What`s happening with programming languages? (2) Will there continue to be a {open_quotes}blurring of the lines{close_quotes} between the PLC and other technologies, and what role will software play in this integration? (3) How will the PLC`s cost and size affect the market?

  9. Processing device with self-scrubbing logic

    DOEpatents

    Wojahn, Christopher K.

    2016-03-01

    An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

  10. Programmable logic controller optical fibre sensor interface module

    NASA Astrophysics Data System (ADS)

    Allwood, Gary; Wild, Graham; Hinckley, Steven

    2011-12-01

    Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

  11. Voltage controlled spintronic devices for logic applications

    DOEpatents

    You, Chun-Yeol; Bader, Samuel D.

    2001-01-01

    A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

  12. Programmable and Multiparameter DNA-Based Logic Platform For Cancer Recognition and Targeted Therapy

    PubMed Central

    2014-01-01

    The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

  13. Programmable and multiparameter DNA-based logic platform for cancer recognition and targeted therapy.

    PubMed

    You, Mingxu; Zhu, Guizhi; Chen, Tao; Donovan, Michael J; Tan, Weihong

    2015-01-21

    The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

  14. Ultrafast phase-change logic device driven by melting processes

    PubMed Central

    Loke, Desmond; Skelton, Jonathan M.; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R.

    2014-01-01

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change–based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change–based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change–based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates. PMID:25197044

  15. Ultrafast phase-change logic device driven by melting processes.

    PubMed

    Loke, Desmond; Skelton, Jonathan M; Wang, Wei-Jie; Lee, Tae-Hoon; Zhao, Rong; Chong, Tow-Chong; Elliott, Stephen R

    2014-09-16

    The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change-based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change-based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change-based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates. PMID:25197044

  16. SASIL. Sandia ATM SONET Interface Logic

    SciTech Connect

    Kitta, J.P.

    1994-07-01

    SASIL is used to program the EPLD`s (Erasable Programmable Logic Devices) and PAL`s (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.

  17. Compact programmable photonic variable delay devices

    NASA Technical Reports Server (NTRS)

    Yao, X. Steve (Inventor)

    1999-01-01

    Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

  18. Supramolecular photochemistry applied to artificial photosynthesis and molecular logic devices.

    PubMed

    Gust, Devens

    2015-01-01

    Supramolecular photochemical systems consist of photochemically active components such as chromophores, electron donors or electron acceptors that are associated via non-covalent or covalent interactions and that interact in some functional way. Examples of interactions are singlet-singlet energy transfer, triplet-triplet energy transfer, photoinduced electron transfer, quantum coherence and spin-spin magnetic interactions. Supramolecular photochemical "devices" may have applications in areas such as solar energy conversion, molecular logic, computation and data storage, biomedicine, sensing, imaging, and displays. This short review illustrates supramolecular photochemistry with examples drawn from artificial photosynthesis, molecular logic, analog photochemical devices and models for avian magnetic orientation. PMID:26515930

  19. Pathway to the piezoelectronic transduction logic device.

    PubMed

    Solomon, P M; Bryce, B A; Kuroda, M A; Keech, R; Shetty, S; Shaw, T M; Copel, M; Hung, L-W; Schrott, A G; Armstrong, C; Gordon, M S; Reuter, K B; Theis, T N; Haensch, W; Rossnagel, S M; Miyazoe, H; Elmegreen, B G; Liu, X-H; Trolier-McKinstry, S; Martyna, G J; Newns, D M

    2015-04-01

    The piezoelectronic transistor (PET) has been proposed as a transduction device not subject to the voltage limits of field-effect transistors. The PET transduces voltage to stress, activating a facile insulator-metal transition, thereby achieving multigigahertz switching speeds, as predicted by modeling, at lower power than the comparable generation field effect transistor (FET). Here, the fabrication and measurement of the first physical PET devices are reported, showing both on/off switching and cycling. The results demonstrate the realization of a stress-based transduction principle, representing the early steps on a developmental pathway to PET technology with potential to contribute to the IT industry. PMID:25793915

  20. Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

    PubMed

    Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

    2013-05-01

    A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors. PMID:23858841

  1. Cascade DNA logic device programmed ratiometric DNA analysis and logic devices based on a fluorescent dual-signal probe of a G-quadruplex DNAzyme.

    PubMed

    Fan, Daoqing; Zhu, Jinbo; Zhai, Qingfeng; Wang, Erkang; Dong, Shaojun

    2016-03-01

    Herein, two fluorescence sensitive substrates of G-quadruplex/hemin DNAzyme with inverse responses (Scopoletin and Amplex Red) were simultaneously used in one homogeneous system to construct a cascade advanced DNA logic device for the first time (a functional logic device (a three input based DNA calliper) cascade with an advanced non-arithmetic logic gate (1 to 2 decoder)). This cascade logic device was applied to label-free ratiometric target DNA detection and length measurement. PMID:26882417

  2. General purpose programmable accelerator board

    DOEpatents

    Robertson, Perry J.; Witzke, Edward L.

    2001-01-01

    A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

  3. Programme Costing - A Logical Step Toward Improved Management.

    ERIC Educational Resources Information Center

    McDougall, Ronald N.

    The analysis of costs of university activities from a functional or program point of view, rather than an organizational unit basis, is not only an imperative for the planning and management of universities, but also a logical method of examing the costs of university operations. A task force of the Committee of Finance Officers-Universities of…

  4. Energy Efficient Digital Logic Using Nanoscale Magnetic Devices

    NASA Astrophysics Data System (ADS)

    Lambson, Brian James

    Increasing demand for information processing in the last 50 years has been largely satisfied by the steadily declining price and improving performance of microelectronic devices. Much of this progress has been made by aggressively scaling the size of semiconductor transistors and metal interconnects that microprocessors are built from. As devices shrink to the size regime in which quantum effects pose significant challenges, new physics may be required in order to continue historical scaling trends. A variety of new devices and physics are currently under investigation throughout the scientific and engineering community to meet these challenges. One of the more drastic proposals on the table is to replace the electronic components of information processors with magnetic components. Magnetic components are already commonplace in computers for their information storage capability. Unlike most electronic devices, magnetic materials can store data in the absence of a power supply. Today's magnetic hard disk drives can routinely hold billions of bits of information and are in widespread commercial use. Their ability to function without a constant power source hints at an intrinsic energy efficiency. The question we investigate in this dissertation is whether or not this advantage can be extended from information storage to the notoriously energy intensive task of information processing. Several proof-of-concept magnetic logic devices were proposed and tested in the past decade. In this dissertation, we build on the prior work by answering fundamental questions about how magnetic devices achieve such high energy efficiency and how they can best function in digital logic applications. The results of this analysis are used to suggest and test improvements to nanomagnetic computing devices. Two of our results are seen as especially important to the field of nanomagnetic computing: (1) we show that it is possible to operate nanomagnetic computers at the fundamental

  5. Motor imaginary-based brain-machine interface design using programmable logic controllers for the disabled.

    PubMed

    Jeyabalan, Vickneswaran; Samraj, Andrews; Loo, Chu Kiong

    2010-10-01

    Aiming at the implementation of brain-machine interfaces (BMI) for the aid of disabled people, this paper presents a system design for real-time communication between the BMI and programmable logic controllers (PLCs) to control an electrical actuator that could be used in devices to help the disabled. Motor imaginary signals extracted from the brain’s motor cortex using an electroencephalogram (EEG) were used as a control signal. The EEG signals were pre-processed by means of adaptive recursive band-pass filtrations (ARBF) and classified using simplified fuzzy adaptive resonance theory mapping (ARTMAP) in which the classified signals are then translated into control signals used for machine control via the PLC. A real-time test system was designed using MATLAB for signal processing, KEP-Ware V4 OLE for process control (OPC), a wireless local area network router, an Omron Sysmac CPM1 PLC and a 5 V/0.3A motor. This paper explains the signal processing techniques, the PLC's hardware configuration, OPC configuration and real-time data exchange between MATLAB and PLC using the MATLAB OPC toolbox. The test results indicate that the function of exchanging real-time data can be attained between the BMI and PLC through OPC server and proves that it is an effective and feasible method to be applied to devices such as wheelchairs or electronic equipment. PMID:20336561

  6. Preliminary surface-emitting laser logic device evaluation

    NASA Astrophysics Data System (ADS)

    Libby, S. I.; Parker, M. A.; Olbright, G. R.; Swanson, P. D.

    1993-03-01

    This report discusses the evaluation of a monolithically integrated heterojunction phototransistor and vertical-cavity surface-emitting laser, designated the surface-Emitting Laser Logic device (CELL). Included is a discussion of the device structure and theory of operation, test procedures, results, and conclusions. Also presented is the CELL's opto-electronic input/output characteristics which includes spectral analysis, characteristic emitted light versus current and current versus voltage curves, input wavelength tolerance, output wavelength sensitivity to bias current, and insensitivity to input wavelength and power within a specified range.

  7. Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

    ERIC Educational Resources Information Center

    Todorovich, E.; Marone, J. A.; Vazquez, M.

    2012-01-01

    Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

  8. A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

    ERIC Educational Resources Information Center

    Kellett, C. M.

    2012-01-01

    This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

  9. Thermally reliable clocked non-volatile spin wave logic device

    NASA Astrophysics Data System (ADS)

    Dutta, Sourav; Nikonov, Dmitri; Manipatruni, Sasikanth; Young, Ian; Naeemi, Azad

    The possibility of utilizing spin waves for information transmission and computation has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits. Here, we present a comprehensive scheme for building a thermally reliable clocked non-volatile spin wave logic device (SWLD) by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, exploiting the magneto-electric effect for spin wave transmission, detection and non-volatile memory, utilizing the phase of the spin wave as information token, ensuring phase-dependent deterministic switching of the magnetoelectric spin wave detector in the presence of thermal noise via compensation of demagnetization and a novel clocking scheme that ensures sequential transmission of information in a cascaded SWLD and non- reciprocity

  10. Multifunctional devices and logic gates with undoped silicon nanowires.

    PubMed

    Mongillo, Massimo; Spathis, Panayotis; Katsaros, Georgios; Gentile, Pascal; De Franceschi, Silvano

    2012-06-13

    We report on the electronic transport properties of multiple-gate devices fabricated from undoped silicon nanowires. Understanding and control of the relevant transport mechanisms was achieved by means of local electrostatic gating and temperature-dependent measurements. The roles of the source/drain contacts and of the silicon channel could be independently evaluated and tuned. Wrap gates surrounding the silicide-silicon contact interfaces were proved to be effective in inducing a full suppression of the contact Schottky barriers, thereby enabling carrier injection down to liquid helium temperature. By independently tuning the effective Schottky barrier heights, a variety of reconfigurable device functionalities could be obtained. In particular, the same nanowire device could be configured to work as a Schottky barrier transistor, a Schottky diode, or a p-n diode with tunable polarities. This versatility was eventually exploited to realize a NAND logic gate with gain well above one. PMID:22594644

  11. Current-limiting challenges for all-spin logic devices.

    PubMed

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-01-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

  12. Current-limiting challenges for all-spin logic devices

    PubMed Central

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-01-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

  13. Current-limiting challenges for all-spin logic devices

    NASA Astrophysics Data System (ADS)

    Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

    2015-10-01

    All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications.

  14. Lateral Programmable Metallization Cell Devices And Applications

    NASA Astrophysics Data System (ADS)

    Ren, Minghan

    2011-12-01

    Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in situ, via the application of a bias on laterally placed electrodes, creates a large number of promising applications. A novel PMC-based lateral microwave switch was fabricated and characterized for use in microwave systems. It has demonstrated low insertion loss, high isolation, low voltage operation, low power and low energy consumption, and excellent linearity. Due to its non-volatile nature the switch operates with fewer biases and its simple planar geometry makes possible innovative device structures which can be potentially integrated into microwave power distribution circuits. PMC technology is also used to develop lateral dendritic metal electrodes. A lateral metallic dendritic network can be grown in a solid electrolyte (GeSe) or electrodeposited on SiO2 or Si using a water-mediated method. These dendritic electrodes grown in a solid electrolyte (GeSe) can be used to lower resistances for applications like self-healing interconnects despite its relatively low light transparency; while the dendritic electrodes grown using water-mediated method can be potentially integrated into solar cell applications, like replacing conventional Ag screen-printed top electrodes as they not only reduce resistances but also are highly transparent. This research effort also laid a solid foundation for developing dendritic plasmonic structures. A PMC-based lateral dendritic plasmonic structure is a device that has metallic dendritic networks grown electrochemically on SiO2 with a thin layer of surface metal nanoparticles in liquid electrolyte. These structures increase the distribution of particle sizes by connecting pre-deposited Ag

  15. Improved overlay metrology device correlation on 90-nm logic processes

    NASA Astrophysics Data System (ADS)

    Ueno, Atsushi; Tsujita, Kouichirou; Kurita, Hiroyuki; Iwata, Yasuhisa; Ghinovker, Mark; Poplawski, Jorge M.; Kassel, Elyakim; Adel, Mike E.

    2004-05-01

    Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

  16. Towards manufacturing of advanced logic devices by double-patterning

    NASA Astrophysics Data System (ADS)

    Koay, Chiew-seng; Halle, Scott; Holmes, Steven; Petrillo, Karen; Colburn, Matthew; van Dommelen, Youri; Jiang, Aiqin; Crouse, Michael; Dunn, Shannon; Hetzer, David; Kawakami, Shinichiro; Cantone, Jason; Huli, Lior; Rodgers, Martin; Martinick, Brian

    2011-04-01

    As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

  17. 46 CFR 62.25-25 - Programmable systems and devices.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 46 Shipping 2 2014-10-01 2014-10-01 false Programmable systems and devices. 62.25-25 Section 62.25-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM AUTOMATION General Requirements for All Automated Vital Systems § 62.25-25 Programmable systems and...

  18. Fabrication of stretchable single-walled carbon nanotube logic devices.

    PubMed

    Yoon, Jangyeol; Shin, Gunchul; Kim, Joonsung; Moon, Young Sun; Lee, Seung-Jung; Zi, Goangseup; Ha, Jeong Sook

    2014-07-23

    The fabrication of a stretchable single-walled carbon nanotube (SWCNT) complementary metal oxide semiconductor (CMOS) inverter array and ring oscillators is reported. The SWCNT CMOS inverter exhibits static voltage transfer characteristics with a maximum gain of 8.9 at a supply voltage of 5 V. The fabricated devices show stable electrical performance under the maximum strain of 30% via forming wavy configurations. In addition, the 3-stage ring oscillator demonstrates a stable oscillator frequency of ∼3.5 kHz at a supply voltage of 10 V and the oscillating waveforms are maintained without any distortion under cycles of pre-strain and release. The strains applied to the device upon deformation are also analyzed by using the classical lamination theory, estimating the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions which is small enough to keep the device performance stable under the pre-strain up to 30%. This work demonstrates the potential application of stretchable SWCNT logic circuit devices in future wearable electronics. PMID:24700788

  19. D0 General Support: The Use of Programmable Logic Controllers (PLCS) at D0

    SciTech Connect

    Hance, R.; /Fermilab

    2000-05-05

    With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

  20. Programmable logic controller performance enhancement by field programmable gate array based design.

    PubMed

    Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

    2015-01-01

    PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. PMID:25441219

  1. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  2. WeaselBoard : zero-day exploit detection for programmable logic controllers.

    SciTech Connect

    Mulder, John C.; Schwartz, Moses Daniel; Berg, Michael J.; Van Houten, Jonathan Roger; Urrea, Jorge Mario; King, Michael Aaron; Clements, Abraham Anthony; Jacob, Joshua A.

    2013-10-01

    Critical infrastructures, such as electrical power plants and oil refineries, rely on programmable logic controllers (PLCs) to control essential processes. State of the art security cannot detect attacks on PLCs at the hardware or firmware level. This renders critical infrastructure control systems vulnerable to costly and dangerous attacks. WeaselBoard is a PLC backplane analysis system that connects directly to the PLC backplane to capture backplane communications between modules. WeaselBoard forwards inter-module traffic to an external analysis system that detects changes to process control settings, sensor values, module configuration information, firmware updates, and process control program (logic) updates. WeaselBoard provides zero-day exploit detection for PLCs by detecting changes in the PLC and the process. This approach to PLC monitoring is protected under U.S. Patent Application 13/947,887.

  3. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  4. A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell

    NASA Astrophysics Data System (ADS)

    Yi-Hung Tsai,; Hsiao-Lan Yang,; Wun-Jie Lin,; Chrong Jung Lin,; Ya-Chin King,

    2010-04-01

    This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 Å for 90 nm complementary metal-oxide-semiconductor (CMOS) node and beyond.

  5. Programmable synaptic devices for electronic neural nets

    NASA Technical Reports Server (NTRS)

    Moopenn, A.; Thakoor, A. P.

    1990-01-01

    The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

  6. Improvement of photovoltaic pumping systems based on standard frequency converters by means of programmable logic controllers

    SciTech Connect

    Fernandez-Ramos, Jose; Narvarte-Fernandez, Luis; Poza-Saura, Fernando

    2010-01-15

    Photovoltaic pumping systems (PVPS) based on standard frequency converters (SFCs) are currently experiencing a growing interest in pumping programmes implemented in remote areas because of their high performance in terms of component reliability, low cost, high power range and good availability of components virtually anywhere in the world. However, in practical applications there have appeared a number of problems related to the adaptation of the SFCs to the requirements of the photovoltaic pumping systems (PVPS). Another disadvantage of dedicated PVPS is the difficulty in implementing maximum power point tracking (MPPT). This paper shows that these problems can be solved through the addition of a basic industrial programmable logic controller (PLC) to the system. This PLC does not increase the cost and complexity of the system, but improves the adaptation of the SFC to the photovoltaic pumping system, and increases the overall performance of the system. (author)

  7. The Programmable Logic Controller and its application in nuclear reactor systems

    SciTech Connect

    Palomar, J.; Wyman, R.

    1993-09-01

    This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

  8. The research and applications of programmable analog device

    NASA Astrophysics Data System (ADS)

    Yang, Xiaohui; Zhao, Qiudi; Yang, Yongjian

    2005-01-01

    This paper introduces the inner structure principle and signal adjusting applications of programmable analogy device ispPAC which was manufactured by Lattice semiconductor company.It expounds the chip functions of agility,diverse amplification,smoothing and deamplification at length and discusses the design method of every function.

  9. A logical molecular circuit for programmable and autonomous regulation of protein activity using DNA aptamer-protein interactions

    PubMed Central

    Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R.; Tan, Weihong

    2013-01-01

    Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo.1 As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy. PMID:23194304

  10. A logical molecular circuit for programmable and autonomous regulation of protein activity using DNA aptamer-protein interactions.

    PubMed

    Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R; Tan, Weihong

    2012-12-26

    Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo. (1) As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here, we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy. PMID:23194304

  11. All-optical logic devices with cascaded nonlinear couplers.

    PubMed

    Wang, Y; Wang, Z H; Bialkowski, M E

    2000-08-10

    The switching behaviors of cascaded nonlinear couplers were investigated. They have nearly ideal digital-switching characteristics, and their output power levels can be adjusted by means of varying the nonlinear coupling coefficient of the final coupler. The two-input excitation nonlinear cascaded couplers can perform not only switching operations but also a series of logic operations. The logic operations depend mainly on the coupling length of the two-input coupler and its initial inputs. The power corresponding to the rising and falling ridge of the logic operating waveforms can be shifted effectively by means of varying the switching power of the reshaper. Allowable ranges of three important parameters--coupling length of the two-input coupler L(1), bias optical power P(bia), and phase difference psi between the signal and bias beams for six fundamental logic operations--were calculated. Curves for design considerations and suggestions for the best choice of parameters for stable and reliable logic operations and, or, xor, nand, nor, and nxor are also presented individually. PMID:18349996

  12. Implementation of motor speed control using PID control in programmable logic controller

    NASA Astrophysics Data System (ADS)

    Samin, R. E.; Azmi, N. A.; Ahmad, M. A.; Ghazali, M. R.; Zawawi, M. A.

    2012-11-01

    This paper presents the implementation of motor speed control using Proportional Integral Derrivative (PID) controller using Programmable Logic Controller (PLC). Proportional Integral Derrivative (PID) controller is the technique used to actively control the speed of the motor. An AC motor is used in the research together with the PLC, encoder and Proface touch screen. The model of the PLC that has been used in this project is OMRON CJIG-CPU42P where this PLC has a build in loop control that can be made the ladder diagram quite simple using function block in CX-process tools. A complete experimental analysis of the technique in terms of system response is presented. Comparative assessment of the impact of Proportional, Integral and Derivative in the controller on the system performance is presented and discussed.

  13. Programmable logic controller implementation of an auto-tuned predictive control based on minimal plant information.

    PubMed

    Valencia-Palomo, G; Rossiter, J A

    2011-01-01

    This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules. PMID:21056412

  14. Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

    SciTech Connect

    WHITE, K.A.

    2000-11-28

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309, Rev. 1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  15. Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

    SciTech Connect

    KOCH, M.R.

    1999-11-16

    This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309, Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis.

  16. Controlling High Power Devices with Computers or TTL Logic Circuits

    ERIC Educational Resources Information Center

    Carlton, Kevin

    2002-01-01

    Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…

  17. Electrically reconfigurable logic array

    NASA Technical Reports Server (NTRS)

    Agarwal, R. K.

    1982-01-01

    To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

  18. ``Spin inverter'' as building block of All Spin Logic devices

    NASA Astrophysics Data System (ADS)

    Sarkar, Angik; Srinivasan, Srikant; Datta, Supriyo

    2012-02-01

    All-spin logic (ASL) represents a new approach to information processing where the roles of charges and capacitors in charge based transistors are played by spins and magnets, without the need for repeated spin-charge conversion. In our past work, we have presented numerical simulations based on a coupled spin transport and Landau Lifshitz Gilbert model showing that ring oscillators and logic circuits with intrinsic directionality [IEEE Trans. Magn. 47,10, 4026, 2011; Proc. IEDM, 2011)] can be implemented by manipulation of spins in magnetic nanostructures. The aim of this talk is (1) to identify a basic ASL unit that can be interconnected to build up spin circuits analogous to the way transistors are interconnected to build conventional circuits and (2) to present a compact model for this basic unit that can be used to design and analyze large scale spin circuits. We will show that this basic ASL unit is a one-magnet ``spin inverter'' with gain that can be cascaded to accomplish a spin circuit implementation of almost any logic functionality

  19. Logic synthesis of cascade circuits

    NASA Astrophysics Data System (ADS)

    Zakrevskii, A. D.

    The work reviews aspects of the logic design of cascade circuits, particularly programmable logic matrices. Effective methods for solving various problems of the analysis and synthesis of these devices are examined; these methods are based on a matrix representation of the structure of these devices, and a vector-matrix interpretation of certain aspects of Boolean algebra. Particular consideration is given to the theory of elementary matrix circuits, methods for the minimization of Boolean functions, the synthesis of programmable logic matrices, multilevel combinational networks, and the development of automata with memory.

  20. Proposal for an all-spin logic device with built-in memory.

    PubMed

    Behin-Aein, Behtash; Datta, Deepanjan; Salahuddin, Sayeef; Datta, Supriyo

    2010-04-01

    The possible use of spin rather than charge as a state variable in devices for processing and storing information has been widely discussed, because it could allow low-power operation and might also have applications in quantum computing. However, spin-based experiments and proposals for logic applications typically use spin only as an internal variable, the terminal quantities for each individual logic gate still being charge-based. This requires repeated spin-to-charge conversion, using extra hardware that offsets any possible advantage. Here we propose a spintronic device that uses spin at every stage of its operation. Input and output information are represented by the magnetization of nanomagnets that communicate through spin-coherent channels. Based on simulations with an experimentally benchmarked model, we argue that the device is both feasible and shows the five essential characteristics for logic applications: concatenability, nonlinearity, feedback elimination, gain and a complete set of Boolean operations. PMID:20190748

  1. Designing the Expanded Programme on Immunisation (EPI) as a service: Prioritising patients over administrative logic.

    PubMed

    McKnight, Jacob; Holt, Douglas B

    2014-01-01

    Expanded Programme on Immunisation (EPI) vaccination rates remain well below herd immunity in regions of many countries despite huge international resources devoted to both financing and access. We draw upon service marketing theory, organisational sociology, development anthropology and cultural consumer research to conduct an ethnographic study of vaccination delivery in Jimma Zone, Ethiopia - one such region. We find that Western public health sector policies are dominated by an administrative logic. Critical failures in delivery are produced by a system that obfuscates the on-the-ground problems that mothers face in trying to vaccinate their children, while instead prioritising administrative processes. Our ethnographic analysis of 83 mothers who had not vaccinated their children reveals key barriers to vaccination from a 'customer' perspective. While mothers value vaccination, it is a 'low involvement' good compared to the acute daily needs of a subsistence life. The costs imposed by poor service - such as uncaring staff with class hostilities, unpredictable and missed schedules and long waits - are too much and so they forego the service. Our service design framework illuminates specific service problems from the mother's perspective and points towards simple service innovations that could improve vaccination rates in regions that have poor uptake. PMID:25363481

  2. The spatial and logical organization of devices in an advanced industrial robot system

    NASA Technical Reports Server (NTRS)

    Ruoff, C. F.

    1980-01-01

    This paper describes the geometrical and device organization of a robot system which is based in part upon transformations of Cartesian frames and exchangeable device tree structures. It discusses coordinate frame transformations, geometrical device representation and solution degeneracy along with the data structures which support the exchangeable logical-physical device assignments. The system, which has been implemented in a minicomputer, supports vision, force, and other sensors. It allows tasks to be instantiated with logically equivalent devices and it allows tasks to be defined relative to appropriate frames. Since these frames are, in turn, defined relative other frames this organization provides a significant simplification in task specification and a high degree of system modularity.

  3. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications

    NASA Astrophysics Data System (ADS)

    Khatami, Yasin; Kang, Jiahao; Banerjee, Kaustav

    2013-01-01

    Negative resistance devices offer opportunities in design of compact and fast analog and digital circuits. However, their implementation in logic applications has been limited due to their small ON current to OFF current ratios (peak to valley ratio). In this paper, a design for a 2-port negative resistance device based on arm-chair graphene nanoribbon is presented. The proposed structure takes advantage of electrostatic doping, and offers high ON current (˜700 μA/μm) as well as ON current to OFF current ratio of more than 105. The effects of several design parameters such as doping profile, gate workfunction, bandgap, and hetero-interface characteristics are investigated to improve the performance of the proposed devices. The proposed device offers high flexibility in terms of the design and optimization, and is suitable for digital logic applications. A complementary logic is developed based on the proposed device, which can be operated down to 200 mV of supply voltage. The complementary logic is used in design of an ultra-compact bi-stable switching static memory cell. Due to its compactness and high drive current, the proposed memory cell can outperform the conventional static random access memory cells in terms of switching speed and power consumption.

  4. Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

    NASA Astrophysics Data System (ADS)

    Wang, Jian-Ping

    An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

  5. Cellular signaling circuits interfaced with synthetic, post-translational, negating Boolean logic devices.

    PubMed

    Razavi, Shiva; Su, Steven; Inoue, Takanari

    2014-09-19

    A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top-down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers. PMID:25000210

  6. Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

    SciTech Connect

    Koga, R.; Crain, W.R.; Hansel, S.J.; Crawford, K.B.; Kirshman, J.F.; Pinkerton, S.D.; Penzin, S.H.; Moss, S.C.; Maher, M.

    1995-12-01

    This paper presents single event upset (SEU) and latchup test results for selected Emitter Coupled Logic (ECL) microcircuits, including several types of low capacity SRAMs and other memory devices. The high speed of ECL memory devices makes them attractive for use in space applications. However, the emitter coupled transistor design increases susceptibility to radiation induced functional errors, especially SEU, because the transistors are not saturated, unlike the transistors in a CMOS device. Charge collection at the sensitive nodes in ECL memory elements differs accordingly. These differences are responsible, in part, for the heightened SEU vulnerability of ECL memory devices relative to their CMOS counterparts.

  7. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, Roger J.; Osbourn, Gordon C.; Zipperian, Thomas E.

    1991-01-01

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

  8. SLS complementary logic devices with increase carrier mobility

    DOEpatents

    Chaffin, R.J.; Osbourn, G.C.; Zipperian, T.E.

    1991-07-09

    In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.

  9. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    NASA Astrophysics Data System (ADS)

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-Min; Lu, Meng

    2016-03-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively.

  10. A programmable nanoreplica molding for the fabrication of nanophotonic devices.

    PubMed

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-Min; Lu, Meng

    2016-01-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively. PMID:26925828

  11. A programmable nanoreplica molding for the fabrication of nanophotonic devices

    PubMed Central

    Liu, Longju; Zhang, Jingxiang; Badshah, Mohsin Ali; Dong, Liang; Li, Jingjing; Kim, Seok-min; Lu, Meng

    2016-01-01

    The ability to fabricate periodic structures with sub-wavelength features has a great potential for impact on integrated optics, optical sensors, and photovoltaic devices. Here, we report a programmable nanoreplica molding process to fabricate a variety of sub-micrometer periodic patterns using a single mold. The process utilizes a stretchable mold to produce the desired periodic structure in a photopolymer on glass or plastic substrates. During the replica molding process, a uniaxial force is applied to the mold and results in changes of the periodic structure, which resides on the surface of the mold. Direction and magnitude of the force determine the array geometry, including the lattice constant and arrangement. By stretching the mold, 2D arrays with square, rectangular, and triangular lattice structures can be fabricated. As one example, we present a plasmonic crystal device with surface plasmon resonances determined by the force applied during molding. In addition, photonic crystal slabs with different array patterns are fabricated and characterized. This unique process offers the capability of generating various periodic nanostructures rapidly and inexpensively. PMID:26925828

  12. Micromagnetic simulation of exploratory magnetic logic device with missing corner defect

    NASA Astrophysics Data System (ADS)

    Yang, Xiaokuo; Cai, Li; Zhang, Bin; Cui, Huanqing; Zhang, Mingliang

    2015-11-01

    Magnetic film nanostructures are attractive components of nonvolatile magnetoresistive memories and nanomagnet logic circuits. Recently, we studied switching properties (i.e., null logic preserving) of rectangle shape nanomagnet subjected to fabrication imperfections. Specifically, we presented typical missing corner material-related imperfections and adopted an isosceles triangle to model this defect for nanomagnets. Micromagnetic simulation shows that this kind of imperfections modeling method agrees well with previous experimental observations. Using the proposed defect modeling scheme, we investigate in detail the switching characteristics of different defective stand-alone and coupled nanomagnets. The results suggest that the state transition of defective nanomagnet element highly depends on defect type and device's aspect ratio, and the defect type Bd needs the largest coercive field, while the defect type D requires the largest null field for switching. These findings can provide key technical parameters and guides for nanomagnet logic circuit design.

  13. Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices

    NASA Astrophysics Data System (ADS)

    Cricchio, Dario; Fiordilino, Emilio

    2016-01-01

    We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device.

  14. Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices.

    PubMed

    Cricchio, Dario; Fiordilino, Emilio

    2016-01-28

    We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device. PMID:26662194

  15. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    NASA Technical Reports Server (NTRS)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  16. Analysis of an nn+ low-high junction and the application to integrated injection logic devices

    NASA Astrophysics Data System (ADS)

    Gannon, T. L.

    1980-12-01

    The literature on pnn+ devices is reviewed with an itemization of the assumptions typically made as well as a derivation of the most widely accepted theory. These assumptions are analyzed separately with the aid of sample calculations made using numerical analysis. The effects associated with heavy doping and Auger recombination are introduced with the associated theories described. A computational approach for the analysis of nn+ is developed that provides excellent agreement with the more complex and rigorous numerical analysis. The basic operation of integrated injection logic is described along with a development of a d.c. model. The a.c. or transient analysis of an integrated injection logic device using a charge control model is discussed. An extended Ebers-Moll model is described with a technique for calculating the model parameters for diffusion capacitance determination. The numerical techniques utilized in the derivations as well as determining how heavy doping and Auger effects can be incorporated into the algorithm are considered.

  17. Spin-wave logic devices based on isotropic forward volume magnetostatic waves

    SciTech Connect

    Klingler, S. Pirro, P.; Brächer, T.; Leven, B.; Hillebrands, B.; Chumak, A. V.

    2015-05-25

    We propose the utilization of isotropic forward volume magnetostatic spin waves in modern wave-based logic devices and suggest a concrete design for a spin-wave majority gate operating with these waves. We demonstrate by numerical simulations that the proposed out-of-plane magnetized majority gate overcomes the limitations of anisotropic in-plane magnetized majority gates due to the high spin-wave transmission through the gate, which enables a reduced energy consumption of these devices. Moreover, the functionality of the out-of-plane majority gate is increased due to the lack of parasitic generation of short-wavelength exchange spin waves.

  18. CAMAC modular programmable function generator

    SciTech Connect

    Turner, G.W.; Suehiro, S.; Hendricks, R.W.

    1980-12-01

    A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve.

  19. A novel design-based global CDU metrology for 1X nm node logic devices

    NASA Astrophysics Data System (ADS)

    Yoon, Young-Keun; Chung, Dong H.; Kim, Min-Ho; Seo, Jung-Uk; Kim, Byung-Gook; Jeon, Chan-Uk; Hur, JiUk; Cho, Wonil; Yamamoto, Tetsuya

    2013-09-01

    As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view (FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics. For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in order to maximize the coverage area on a mask. In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its fundamental performance such as accuracy, repeatability, and correlation with other CD metrology

  20. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    SciTech Connect

    Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-17

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  1. A Novel 2-D Programmable Photonic Time Delay Device for MM-Wave Signal Processing Applications

    NASA Technical Reports Server (NTRS)

    Yao, X.; Maleki, L.

    1994-01-01

    We describe a novel programmable photonic true time delay device that has the properties of low loss, inherent two dimensionality with a packing density exceeding 25 lines/cm super 2, virtually infinite bandwidth, and is easy to manufacture.

  2. Topological frustration in graphene nanoflakes: magnetic order and spin logic devices.

    PubMed

    Wang, Wei L; Yazyev, Oleg V; Meng, Sheng; Kaxiras, Efthimios

    2009-04-17

    Magnetic order in graphene-related structures can arise from size effects or from topological frustration. We introduce a rigorous classification scheme for the types of finite graphene structures (nanoflakes) which lead to large net spin or to antiferromagnetic coupling between groups of electron spins. Based on this scheme, we propose specific examples of structures that can serve as the fundamental (NOR and NAND) logic gates for the design of high-density ultrafast spintronic devices. We demonstrate, using ab initio electronic structure calculations, that these gates can in principle operate at room temperature with very low and correctable error rates. PMID:19518670

  3. Quantum logical gates with four-level superconducting quantum interference devices coupled to a superconducting resonator

    SciTech Connect

    He Xiaoling; Luo Junyan; Yang Chuiping; Li Sheng; Han Siyuan

    2010-08-15

    We propose a way for realizing a two-qubit controlled phase gate with superconducting quantum interference devices (SQUIDs) coupled to a superconducting resonator. In this proposal, the two lowest levels of each SQUID serve as the logical states and two intermediate levels of each SQUID are used for the gate realization. We show that neither adjustment of SQUID level spacings during the gate operation nor uniformity in SQUID parameters is required by this proposal. In addition, this proposal does not require the adiabatic passage or a second-order detuning and thus the gate is much faster.

  4. Programmable hardware for reconfigurable computing systems

    NASA Astrophysics Data System (ADS)

    Smith, Stephen

    1996-10-01

    In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

  5. Remote Control Laboratory Using EJS Applets and TwinCAT Programmable Logic Controllers

    ERIC Educational Resources Information Center

    Besada-Portas, E.; Lopez-Orozco, J. A.; de la Torre, L.; de la Cruz, J. M.

    2013-01-01

    This paper presents a new methodology to develop remote laboratories for systems engineering and automation control courses, based on the combined use of TwinCAT, a laboratory Java server application, and Easy Java Simulations (EJS). The TwinCAT system is used to close the control loop for the selected plants by means of programmable logic…

  6. Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

    NASA Astrophysics Data System (ADS)

    Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

    2015-02-01

    A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer,a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

  7. Top coat less resist process development for contact layer of 40nm node logic devices

    NASA Astrophysics Data System (ADS)

    Fujita, Masafumi; Uchiyama, Takayuki; Furusho, Tetsunari; Otsuka, Takahisa; Tsuchiya, Katsuhiro

    2010-04-01

    ArF immersion lithography has been introduced in mass production of 55nm node devices and beyond as the post ArF dry lithography. Due to the existence of water between the resist film and lens, we have many concerns such as leaching of PAG and quencher from resist film into immersion water, resist film swelling by water, keeping water in the immersion hood to avoid water droplets coming in contact with the wafer, and so on. We have applied to the ArF dry resist process an immersion topcoat (TC) process in order to ensure the hydrophobic property as well as one for protecting the surface. We investigate the TC-less resist process with an aim to improve CoO, the yield and productivity in mass production of immersion lithography. In this paper, we will report TC-less resist process development for the contact layer of 40nm node logic devices. It is important to control the resist surface condition to reduce pattern defects, in particular in the case of the contact layer. We evaluated defectivity and lithography performance of TC-less resist with changing hydrophobicity before and after development. Hydrophobicity of TC-less resist was controlled by changing additives with TC functions introduced into conventional ArF dry resist. However, the hydrophobicity control was not sufficient to reduce the number of Blob defects compared with the TC process. Therefore, we introduced Advanced Defect Reduction (ADR) rinse, which was a new developer rinse technique that is effective against hydrophobic surfaces. We have realized Blob defect reduction by hydrophobicity control and ADR rinse. Furthermore, we will report device performance, yield, and immersion defect data at 40nm node logic devices with TC-less resist process.

  8. Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews

    PubMed Central

    Kneale, Dylan; Thomas, James; Harris, Katherine

    2015-01-01

    Background Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to ‘think’ conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. Methods and Findings In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Conclusions Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions. PMID:26575182

  9. Magnetic dipolar coupling and collective effects for binary information codification in cost-effective logic devices

    NASA Astrophysics Data System (ADS)

    Chiolerio, Alessandro; Allia, Paolo; Graziano, Mariagrazia

    2012-09-01

    Physical limitations foreshadow the eventual end to traditional Complementary Metal Oxide Semiconductor (CMOS) scaling. Therefore, interest has turned to various materials and technologies aimed to succeed to traditional CMOS. Magnetic Quantum dot Cellular Automata (MQCA) are one of these technologies. Working MQCA arrays require very complex techniques and an excellent control on the geometry of the nanomagnets and on the quality of the magnetic thin film, thus limiting the possibility for MQCA of representing a definite solution to cost-effective, high density and low power consumption device demand. Counter-intuitively, moving towards bigger sizes and lighter technologies it is still possible to develop multi-state logic devices, as we demonstrated, whose main advantage is cost-effectiveness. Applications may be seen in low cost logic devices where integration and computational power are not the main issue, eventually using flexible substrates and taking advantage of the intrinsic mechanical toughness of systems where long range interactions do not need wirings. We realized cobalt micrometric MQCA arrays by means of Electron Beam Lithography, exploiting cost-effective processes such as lift-off and RF sputtering that usually are avoided due to their low control on array geometry and film roughness. Information relative to the magnetic configuration of MQCA elements including their eventual magnetic interactions was obtained from Magnetic Force Microscope (MFM) images, enhanced by means of a numerical procedure and presented in differential maps. We report the existence of bi-stable magnetic patterns, as detected by MFM while sampling the z-component of magnetic induction field, arising from dipolar inter-element magnetostatic coupling, able to store and propagate binary information. This is achieved despite the array quality and element magnetic state, which are low and multi-domain, respectively. We discuss in detail shape, inter-element spacing and dot profile

  10. Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

    NASA Technical Reports Server (NTRS)

    Taylor, B.

    1990-01-01

    The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

  11. Crystalline Direction Dependence of Spin Precession Angle and Its Application to Complementary Spin Logic Devices.

    PubMed

    Park, Youn Ho; Kim, Hyung-Jun; Chang, Joonyeon; Choi, Heon-Jin; Koo, Hyun Cheol

    2015-10-01

    In a semiconductor channel, spin-orbit interaction is divided into two terms, Rashba and Dresselhaus effects, which are key phenomena for modulating spin precession angles. The direction of Rashba field is always perpendicular to the wavevector but that of Dresselhaus field depends on the crystal orientation. Based on the individual Rashba and Dresselhaus strengths, we calculate spin precession angles for various crystal orientations in an InAs quantum well structure. When the channel length is 1 μm, the precession angle is 550° for the [110] direction and 460° for the [1-10] direction, respectively. Using the two spin transistors with different crystal directions, which play roles of n- and p-type transistors in conventional charge transistors, we propose a complementary logic device. PMID:26726362

  12. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGESBeta

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  13. The use of programmable logic controllers (PLC) for rocket engine component testing

    NASA Technical Reports Server (NTRS)

    Nail, William; Scheuermann, Patrick; Witcher, Kern

    1991-01-01

    Application of PLCs to the rocket engine component testing at a new Stennis Space Center Component Test Facility is suggested as an alternative to dedicated specialized computers. The PLC systems are characterized by rugged design, intuitive software, fault tolerance, flexibility, multiple end device options, networking capability, and built-in diagnostics. A distributed PLC-based system is projected to be used for testing LH2/LOx turbopumps required for the ALS/NLS rocket engines.

  14. Light programmable organic transistor memory device based on hybrid dielectric

    NASA Astrophysics Data System (ADS)

    Ren, Xiaochen; Chan, Paddy K. L.

    2013-09-01

    We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

  15. Automated hotspot analysis with aerial image CD metrology for advanced logic devices

    NASA Astrophysics Data System (ADS)

    Buttgereit, Ute; Trautzsch, Thomas; Kim, Min-ho; Seo, Jung-Uk; Yoon, Young-Keun; Han, Hak-Seung; Chung, Dong Hoon; Jeon, Chan-Uk; Meyers, Gary

    2014-09-01

    Continuously shrinking designs by further extension of 193nm technology lead to a much higher probability of hotspots especially for the manufacturing of advanced logic devices. The CD of these potential hotspots needs to be precisely controlled and measured on the mask. On top of that, the feature complexity increases due to high OPC load in the logic mask design which is an additional challenge for CD metrology. Therefore the hotspot measurements have been performed on WLCD from ZEISS, which provides the benefit of reduced complexity by measuring the CD in the aerial image and qualifying the printing relevant CD. This is especially of advantage for complex 2D feature measurements. Additionally, the data preparation for CD measurement becomes more critical due to the larger amount of CD measurements and the increasing feature diversity. For the data preparation this means to identify these hotspots and mark them automatically with the correct marker required to make the feature specific CD measurement successful. Currently available methods can address generic pattern but cannot deal with the pattern diversity of the hotspots. The paper will explore a method how to overcome those limitations and to enhance the time-to-result in the marking process dramatically. For the marking process the Synopsys WLCD Output Module was utilized, which is an interface between the CATS mask data prep software and the WLCD metrology tool. It translates the CATS marking directly into an executable WLCD measurement job including CD analysis. The paper will describe the utilized method and flow for the hotspot measurement. Additionally, the achieved results on hotspot measurements utilizing this method will be presented.

  16. On the Spot: Using Mobile Devices for Listening and Speaking Practice on a French Language Programme

    ERIC Educational Resources Information Center

    Demouy, Valerie; Kukulska-Hulme, Agnes

    2010-01-01

    This paper presents and discusses the initial findings of a mobile language learning project undertaken in the context of an undergraduate distance-learning French language programme at The Open University (UK). The overall objective of the project was to investigate students' experiences when using their own portable devices for additional…

  17. Biophotonic logic devices based on quantum dots and temporally-staggered Förster energy transfer relays

    NASA Astrophysics Data System (ADS)

    Claussen, Jonathan C.; Algar, W. Russ; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G.; Medintz, Igor L.

    2013-11-01

    Integrating photonic inputs/outputs into unimolecular logic devices can provide significantly increased functional complexity and the ability to expand the repertoire of available operations. Here, we build upon a system previously utilized for biosensing to assemble and prototype several increasingly sophisticated biophotonic logic devices that function based upon multistep Förster resonance energy transfer (FRET) relays. The core system combines a central semiconductor quantum dot (QD) nanoplatform with a long-lifetime Tb complex FRET donor and a near-IR organic fluorophore acceptor; the latter acts as two unique inputs for the QD-based device. The Tb complex allows for a form of temporal memory by providing unique access to a time-delayed modality as an alternate output which significantly increases the inherent computing options. Altering the device by controlling the configuration parameters with biologically based self-assembly provides input control while monitoring changes in emission output of all participants, in both a spectral and temporal-dependent manner, gives rise to two input, single output Boolean Logic operations including OR, AND, INHIBIT, XOR, NOR, NAND, along with the possibility of gate transitions. Incorporation of an enzymatic cleavage step provides for a set-reset function that can be implemented repeatedly with the same building blocks and is demonstrated with single input, single output YES and NOT gates. Potential applications for these devices are discussed in the context of their constituent parts and the richness of available signal.

  18. A study of source mask optimization for logic device through experiment and simulations

    NASA Astrophysics Data System (ADS)

    Kim, Hyo-chan; Lee, Jeong-Hoon; Shin, Jong-Chan; Bae, Yong-Kug; Choi, Siyoung; Kang, Ho-Kyu

    2011-04-01

    Source and Mask co-Optimization (SMO) plays an increasingly important role in the advanced RETs required to continue shrinking designs in the low-k1 lithography regime. Instead of costly double pattering patterning techniques, SMO has been explored as an enabling technology for low-k1 design node. It is clear that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. In this work, source and mask shape for logic device have been optimized in order to improve process window of critical layouts which include complex 2D shape and dense contact. Tachyon SMO solution developed by BRION was introduced to obtain the optimization. In order to improve the accuracy of SMO model, AI blur which represents resist effect on wafer was considered during optimization. Based on simulation results, improvement in terms of process window as well as Mask Error Enhancement Factor (MEEF) was approximately 20 % in comparison with reference conditions. However, the corresponding experimental results should be investigated as the evidence of the performance SMO. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

  19. The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

    NASA Astrophysics Data System (ADS)

    Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J.

    2015-05-01

    All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau-Lifshitz-Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

  20. The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

    SciTech Connect

    Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J.

    2015-05-07

    All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.

  1. Reliability concerns with logical constants in Xilinx FPGA designs

    SciTech Connect

    Quinn, Heather M; Graham, Paul; Morgan, Keith; Ostler, Patrick; Allen, Greg; Swift, Gary; Tseng, Chen W

    2009-01-01

    In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

  2. High-frequency programmable acoustic wave device realized through ferroelectric domain engineering

    SciTech Connect

    Ivry, Yachin E-mail: cd229@eng.cam.ac.uk; Wang, Nan; Durkan, Colm E-mail: cd229@eng.cam.ac.uk

    2014-03-31

    Surface acoustic wave devices are extensively used in contemporary wireless communication devices. We used atomic force microscopy to form periodic macroscopic ferroelectric domains in sol-gel deposited lead zirconate titanate, where each ferroelectric domain is composed of many crystallites, each of which contains many microscopic ferroelastic domains. We examined the electro-acoustic characteristics of the apparatus and found a resonator behavior similar to that of an equivalent surface or bulk acoustic wave device. We show that the operational frequency of the device can be tailored by altering the periodicity of the engineered domains and demonstrate high-frequency filter behavior (>8 GHz), allowing low-cost programmable high-frequency resonators.

  3. Development and Validation of a Miniature Programmable tDCS Device.

    PubMed

    Kouzani, Abbas Z; Jaberzadeh, Shapour; Zoghi, Maryam; Usma, Clara; Parastarfeizabadi, Mahboubeh

    2016-01-01

    Research is being conducted on the use of transcranial direct current stimulation (tDCS) for therapeutic effects, and also on the mechanisms through which such therapeutic effects are mediated. A bottleneck in the progress of the research has been the large size of the existing tDCS systems which prevents subjects from performing their daily activities. To help research into the principles, mechanisms, and benefits of tDCS, reduction of size and weight, improvement in simplicity and user friendliness, portability, and programmability of tDCS systems are vital. This paper presents a design for a low-cost, light-weight, programmable, and portable tDCS device. The device is head-mountable and can be concealed in a hat and worn on the head by the subject while receiving the stimulation. The strength of the direct current stimulation can be selected through a simple user interface. The device is constructed and its performance evaluated through bench and in vivo tests. The tests validated the operation of the device in inducing neuromodulatory changes in primary motor cortex, M1, through measuring excitability of dominant M1 of resting right first dorsal interosseus muscle by transcranial magnetic stimulation induced motor evoked potentials. It was observed that the tDCS device induced comparable neuromodulatory effects in M1 as the existing bulky tDCS systems. PMID:26285208

  4. Logic gates and antisense DNA devices operating on a translator nucleic Acid scaffold.

    PubMed

    Shlyahovsky, Bella; Li, Yang; Lioubashevski, Oleg; Elbaz, Johann; Willner, Itamar

    2009-07-28

    A series of logic gates, "AND", "OR", and "XOR", are designed using a DNA scaffold that includes four "footholds" on which the logic operations are activated. Two of the footholds represent input-recognition strands, and these are blocked by complementary nucleic acids, whereas the other two footholds are blocked by nucleic acids that include the horseradish peroxidase (HRP)-mimicking DNAzyme sequence. The logic gates are activated by either nucleic acid inputs that hybridize to the respective "footholds", or by low-molecular-weight inputs (adenosine monophosphate or cocaine) that yield the respective aptamer-substrate complexes. This results in the respective translocation of the blocking nucleic acids to the footholds carrying the HRP-mimicking DNAzyme sequence, and the concomitant release of the respective DNAzyme. The released product-strands then self-assemble into the hemin/G-quadruplex-HRP-mimicking DNAzyme that biocatalyzes the formation of a colored product and provides an output signal for the different logic gates. The principle of the logic operation is, then, implemented as a possible paradigm for future nanomedicine. The nucleic acid inputs that bind to the blocked footholds result in the translocation of the blocking nucleic acids to the respective footholds carrying the antithrombin aptamer. The released aptamer inhibits, then, the hydrolytic activity of thrombin. The system demonstrates the regulation of a biocatalytic reaction by a translator system activated on a DNA scaffold. PMID:19507821

  5. Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices

    NASA Astrophysics Data System (ADS)

    Suzuki, Daisuke; Natsui, Masanori; Mochizuki, Akira; Hanyu, Takahiro

    2014-01-01

    A 6-input nonvolatile logic element (NV-LE) using domain-wall motion (DWM) devices is presented for low-power and real-time reconfigurable logic LSI applications. Because the write current path of a DWM device is separated from its read current path and the resistance value of the write current path is quite small, multiple DWM devices can be reprogrammed in parallel, thus affording real-time logic-function reconfiguration within a few nanoseconds. Moreover, by merging a circuit component between combinational and sequential logic functions, transistor counts can be minimized. As a result, 2-ns 64-bit-parallel circuit reconfiguration is realized by the proposed 6-input NV-LE with 67% lesser area than a conventional CMOS-based alternative, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS/MTJ technologies.

  6. Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

    NASA Astrophysics Data System (ADS)

    Roy, Debapriya; Biswas, Abhijit

    2016-09-01

    Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4-0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

  7. Project W-058 monitor and control system logic

    SciTech Connect

    ROBERTS, J.B.

    1999-05-12

    This supporting document contains the printout of the control logic for the Project W-058 Monitor and Control System, as developed by Programmable Control Services, Inc. The logic is arranged in five appendices, one for each programmable logic controller console.

  8. Programmable digital memory devices based on nanoscale thin films of a thermally dimensionally stable polyimide.

    PubMed

    Lee, Taek Joon; Chang, Cha-Wen; Hahm, Suk Gyu; Kim, Kyungtae; Park, Samdae; Kim, Dong Min; Kim, Jinchul; Kwon, Won-Sang; Liou, Guey-Sheng; Ree, Moonhor

    2009-04-01

    We have fabricated electrically programmable memory devices with thermally and dimensionally stable poly(N-(N',N'-diphenyl-N'-1,4-phenyl)-N,N-4,4'-diphenylene hexafluoroisopropylidene-diphthalimide) (6F-2TPA PI) films and investigated their switching characteristics and reliability. 6F-2TPA PI films were found to reveal a conductivity of 1.0 x 10(-13)-1.0 x 10(-14) S cm(-1). The 6F-2TPA PI films exhibit versatile memory characteristics that depend on the film thickness. All the PI films are initially present in the OFF state. The PI films with a thickness of >15 to <100 nm exhibit excellent write-once-read-many-times (WORM) (i.e. fuse-type) memory characteristics with and without polarity depending on the thickness. The WORM memory devices are electrically stable, even in air ambient, for a very long time. The devices' ON/OFF current ratio is high, up to 10(10). Therefore, these WORM memory devices can provide an efficient, low-cost means of permanent data storage. On the other hand, the 100 nm thick PI films exhibit excellent dynamic random access memory (DRAM) characteristics with polarity. The ON/OFF current ratio of the DRAM devices is as high as 10(11). The observed electrical switching behaviors were found to be governed by trap-limited space-charge-limited conduction and local filament formation and further dependent on the differences between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels of the PI film and the work functions of the top and bottom electrodes as well as the PI film thickness. In summary, the excellent memory properties of 6F-2TPA PI make it a promising candidate material for the low-cost mass production of high density and very stable digital nonvolatile WORM and volatile DRAM memory devices. PMID:19420490

  9. Molecular implementation of simple logic programs.

    PubMed

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-10-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation. PMID:19809454

  10. Molecular implementation of simple logic programs

    NASA Astrophysics Data System (ADS)

    Ran, Tom; Kaplan, Shai; Shapiro, Ehud

    2009-11-01

    Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

  11. Stem-directed growth of highly fluorescent silver nanoclusters for versatile logic devices.

    PubMed

    Li, Jing; Jia, Xiaofang; Li, Dongyue; Ren, Jiangtao; Han, Yanchao; Xia, Yong; Wang, Erkang

    2013-07-01

    This work described for the first time the stem-directed growth of silver nanoclusters (AgNCs) with high brightness using the well-chosen hairpin DNA structure. In comparison with the corresponding double-stranded (ds) DNA capped AgNCs, the fluorescence emission of hairpin DNA structure templated AgNCs were lighted up with 12.5-fold enhancement fluorescent intensity by sequence modification with T-loop. It provided a new prospect for precise placement of nanoscale optical elements onto DNA scaffolds. And these DNA protected AgNCs exhibited the base sequence, strand length and microenvironment-dependent fluorescent properties. Benefiting from these properties, versatile logic gates (or, not, inhibit, XNOR, implication) were constructed using different ions as inputs with AgNCs as signal transducer. PMID:23728712

  12. Programmable immersive peripheral environmental system (PIPES): a prototype control system for environmental feedback devices

    NASA Astrophysics Data System (ADS)

    Frend, Chauncey; Boyles, Michael

    2015-03-01

    This paper describes an environmental feedback device (EFD) control system aimed at simplifying the VR development cycle. Programmable Immersive Peripheral Environmental System (PIPES) affords VR developers a custom approach to programming and controlling EFD behaviors while relaxing the required knowledge and expertise of electronic systems. PIPES has been implemented for the Unity engine and features EFD control using the Arduino integrated development environment. PIPES was installed and tested on two VR systems, a large format CAVE system and an Oculus Rift HMD system. A photocell based end-to-end latency experiment was conducted to measure latency within the system. This work extends previously unpublished prototypes of a similar design. Development and experiments described in this paper are part of the VR community goal to understand and apply environment effects to VEs that ultimately add to users' perceived presence.

  13. Stem-directed growth of highly fluorescent silver nanoclusters for versatile logic devices

    NASA Astrophysics Data System (ADS)

    Li, Jing; Jia, Xiaofang; Li, Dongyue; Ren, Jiangtao; Han, Yanchao; Xia, Yong; Wang, Erkang

    2013-06-01

    This work described for the first time the stem-directed growth of silver nanoclusters (AgNCs) with high brightness using the well-chosen hairpin DNA structure. In comparison with the corresponding double-stranded (ds) DNA capped AgNCs, the fluorescence emission of hairpin DNA structure templated AgNCs were lighted up with 12.5-fold enhancement fluorescent intensity by sequence modification with T-loop. It provided a new prospect for precise placement of nanoscale optical elements onto DNA scaffolds. And these DNA protected AgNCs exhibited the base sequence, strand length and microenvironment-dependent fluorescent properties. Benefiting from these properties, versatile logic gates (OR, NOT, INHIBIT, XNOR, IMPLICATION) were constructed using different ions as inputs with AgNCs as signal transducer.This work described for the first time the stem-directed growth of silver nanoclusters (AgNCs) with high brightness using the well-chosen hairpin DNA structure. In comparison with the corresponding double-stranded (ds) DNA capped AgNCs, the fluorescence emission of hairpin DNA structure templated AgNCs were lighted up with 12.5-fold enhancement fluorescent intensity by sequence modification with T-loop. It provided a new prospect for precise placement of nanoscale optical elements onto DNA scaffolds. And these DNA protected AgNCs exhibited the base sequence, strand length and microenvironment-dependent fluorescent properties. Benefiting from these properties, versatile logic gates (OR, NOT, INHIBIT, XNOR, IMPLICATION) were constructed using different ions as inputs with AgNCs as signal transducer. Electronic supplementary information (ESI) available: DNA sequences used, Tm curves and spectra data of the obtained AgNCs. See DOI: 10.1039/c3nr00998j

  14. Sensor sentinel computing device

    DOEpatents

    Damico, Joseph P.

    2016-08-02

    Technologies pertaining to authenticating data output by sensors in an industrial environment are described herein. A sensor sentinel computing device receives time-series data from a sensor by way of a wireline connection. The sensor sentinel computing device generates a validation signal that is a function of the time-series signal. The sensor sentinel computing device then transmits the validation signal to a programmable logic controller in the industrial environment.

  15. Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond

    NASA Astrophysics Data System (ADS)

    Kim, Jaeyoon; Lee, Sanghyeon; Rubin, J.; Kim, Moonkyung; Tiwari, Sandip

    2013-06-01

    After six decades of device size reduction and its efficient use through hierarchical design, semiconductor electronics and its use in integrated digital processing encounters two major conflicting constraints. From size reduction and their small collective behavior, i.e., from the bottom, these constraints include quantum effects, stochastic effects arising from discreteness and noise, and other probabilistic effects. From the large scale integration and their large ensemble behavior, i.e., from the top, these include thermodynamic consequences in the inefficiencies of the data engine as a large numbers of devices are assembled together hierarchically. These conflicting currents are the central intellectual challenge when discussing the future of nanostructure devices and their use in data processing machines. We discuss the conceptual fundamentals of the small and the large that ties these scale changes that exist in time, size, energy, and other dimensions of the machinery. From this, we derive ideas for devices, robustness, data manipulation efficiency, and performance under practical constraints so that the next six decades are as fruitful and useful for the society as the past six have been.

  16. Customizable 3D Printed ‘Plug and Play’ Millifluidic Devices for Programmable Fluidics

    PubMed Central

    Tsuda, Soichiro; Jaffery, Hussain; Doran, David; Hezwani, Mohammad; Robbins, Phillip J.; Yoshida, Mari; Cronin, Leroy

    2015-01-01

    Three dimensional (3D) printing is actively sought after in recent years as a promising novel technology to construct complex objects, which scope spans from nano- to over millimeter scale. Previously we utilized Fused deposition modeling (FDM)-based 3D printer to construct complex 3D chemical fluidic systems, and here we demonstrate the construction of 3D milli-fluidic structures for programmable liquid handling and control of biological samples. Basic fluidic operation devices, such as water-in-oil (W/O) droplet generators for producing compartmentalized mono-disperse droplets, sensor-integrated chamber for online monitoring of cellular growth, are presented. In addition, chemical surface treatment techniques are used to construct valve-based flow selector for liquid flow control and inter-connectable modular devices for networking fluidic parts. As such this work paves the way for complex operations, such as mixing, flow control, and monitoring of reaction / cell culture progress can be carried out by constructing both passive and active components in 3D printed structures, which designs can be shared online so that anyone with 3D printers can reproduce them by themselves. PMID:26558389

  17. Vertically Stackable Novel One-Time Programmable Nonvolatile Memory Devices Based on Dielectric Breakdown Mechanism

    NASA Astrophysics Data System (ADS)

    Cho, Seongjae; Lee, Jung Hoon; Ryoo, Kyung-Chang; Jung, Sunghun; Lee, Jong-Ho; Park, Byung-Gook

    2011-12-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array structures based on silicon technology are proposed. There have been many features of OTP NVM devices utilizing various combinations of channel, breakdown region, barrier, and contact materials. However, this invention can be realized by simple materials and fabrication methods: it is silicon-based materials and fully compatible with the conventional CMOS process. An individual memory cell is a silicon diode vertically integrated. Historically, OTP memories were widely used for read-only-memory (ROM) in the central processing unit (CPU) of the computer systems. By implanting the nanoscale fabrication technology into the concept of OTP memory, innovative high-density NVM appliances for massive storage media becomes very promising. The program operation is performed by breaking down the thin oxide layer between pn doped structure and wordline (WL) and its state can be sensed by the leakage current through the broken oxide. Since this invention is based on neither transistor structure nor charge-based mechanism, it is highly reliable and functional for the ultra-large scale integration. The feasibility of its stacked array will be also checked.

  18. An imidazolyl-pyreno-imidazole conjugate as a cyanide sensor and a set-reset memorized sequential logic device.

    PubMed

    Mardanya, Sourav; Karmakar, Srikanta; Mondal, Debiprasad; Baitalik, Sujoy

    2015-09-28

    In this work a pyrenyl-bisimidazole receptor has been synthesized and fully characterized by standard analytical tools and spectroscopic techniques including single crystal X-ray crystallography. Crystal structure analysis shows the occurrence of strong π-π and CH-π interactions among the adjacent Py-BiimzH2 units. Moreover, each NH proton on the imidazole ring is involved in strong intermolecular hydrogen bonding interactions with N atoms of the neighboring unit forming infinite chains. The absorption and both steady state and time-resolved emission properties of the compound were found to be modulated to a significant extent by selective inorganic anions and transition metal cations in solution. Theoretical calculations employing density functional theory (DFT) and time-dependent density functional theory (TD-DFT) were carried out and good correlation between the experimental and the TD-DFT calculated results led to the accurate assignment of the main absorption and emission bands of the original compound as well as its anionic and metal complexes. More importantly, the compound can act as an efficient ratiometric optical chemosensor for CN(-) in H2O-DMSO (9 : 1) media. The anion sensing properties of the receptor was thoroughly investigated in both neat DMSO as well as mixed H2O-DMSO (9 : 1) media through different channels. From the response profiles in terms of absorption or emission intensity and wavelength towards inorganic ions (Cu(2+) and CN(-)), we developed a molecular system which can mimic sequential Boolean logic functions of XOR, OR, XNOR and NOR logic gates. Moreover, we were able to construct a memory device which nicely demonstrates the "Write-Read-Erase-Read" behavior. PMID:26282824

  19. A programmable droplet-based microfluidic device applied to multiparameter analysis of single microbes and microbial communities

    PubMed Central

    Leung, Kaston; Zahn, Hans; Leaver, Timothy; Konwar, Kishori M.; Hanson, Niels W.; Pagé, Antoine P.; Lo, Chien-Chi; Chain, Patrick S.; Hallam, Steven J.; Hansen, Carl L.

    2012-01-01

    We present a programmable droplet-based microfluidic device that combines the reconfigurable flow-routing capabilities of integrated microvalve technology with the sample compartmentalization and dispersion-free transport that is inherent to droplets. The device allows for the execution of user-defined multistep reaction protocols in 95 individually addressable nanoliter-volume storage chambers by consecutively merging programmable sequences of picoliter-volume droplets containing reagents or cells. This functionality is enabled by “flow-controlled wetting,” a droplet docking and merging mechanism that exploits the physics of droplet flow through a channel to control the precise location of droplet wetting. The device also allows for automated cross-contamination-free recovery of reaction products from individual chambers into standard microfuge tubes for downstream analysis. The combined features of programmability, addressability, and selective recovery provide a general hardware platform that can be reprogrammed for multiple applications. We demonstrate this versatility by implementing multiple single-cell experiment types with this device: bacterial cell sorting and cultivation, taxonomic gene identification, and high-throughput single-cell whole genome amplification and sequencing using common laboratory strains. Finally, we apply the device to genome analysis of single cells and microbial consortia from diverse environmental samples including a marine enrichment culture, deep-sea sediments, and the human oral cavity. The resulting datasets capture genotypic properties of individual cells and illuminate known and potentially unique partnerships between microbial community members. PMID:22547789

  20. Ferrite logic reliability study

    NASA Technical Reports Server (NTRS)

    Baer, J. A.; Clark, C. B.

    1973-01-01

    Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)

  1. Fabrication of microfluidic devices using MeV ion beam Programmable Proximity Aperture Lithography (PPAL)

    NASA Astrophysics Data System (ADS)

    Gorelick, S.; Puttaraksa, N.; Sajavaara, T.; Laitinen, M.; Singkarat, S.; Whitlow, H. J.

    2008-05-01

    MeV ion beam lithography is a direct writing technique capable of producing microfluidic patterns and lab-on-chip devices with straight walls in thick resist films. In this technique a small beam spot of MeV ions is scanned over the resist surface to generate a latent image of the pattern. The microstructures in resist polymer can be then revealed using a chemical developer that removes exposed resist, while leaving unexposed resist unaffected. In our system the size of the rectangular beam spot is programmably defined by two L-shaped tantalum blades with well-polished edges. This allows rapid exposure of entire rectangular pattern elements up to 500 × 500 μm in one step. By combining different dimensions of the defining aperture with the sample movements relative to the beam spot, entire fluidic patterns with large reservoirs and narrow flow channels can be written over large areas in short time. Fluidic patterns were written in PMMA using 56 MeV 14N3+ and a 3 MeV 4He2+ beams from K130 cyclotron and a 1.7 MV Pelletron accelerators, respectively, at the University of Jyväskylä Accelerator Laboratory. The patterns were characterized using SEM, and the factors affecting patterns quality are discussed.

  2. A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

    PubMed

    Bayindir, Ramazan; Cetinceviz, Yucel

    2011-04-01

    This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications. PMID:21126739

  3. Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach

    NASA Astrophysics Data System (ADS)

    Nath Roy, Jitendra; Gayen, Dilip Kumar

    2007-08-01

    Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.

  4. Programmable Pulser

    NASA Technical Reports Server (NTRS)

    Baumann, Eric; Merolla, Anthony

    1988-01-01

    User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

  5. Architecture and data processing alternatives for the TSE computer. Volume 3: Execution of a parallel counting algorithm using array logic (Tse) devices

    NASA Technical Reports Server (NTRS)

    Metcalfe, A. G.; Bodenheimer, R. E.

    1976-01-01

    A parallel algorithm for counting the number of logic-l elements in a binary array or image developed during preliminary investigation of the Tse concept is described. The counting algorithm is implemented using a basic combinational structure. Modifications which improve the efficiency of the basic structure are also presented. A programmable Tse computer structure is proposed, along with a hardware control unit, Tse instruction set, and software program for execution of the counting algorithm. Finally, a comparison is made between the different structures in terms of their more important characteristics.

  6. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells.

    PubMed

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J; Kozicki, Michael N

    2016-06-24

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed 'dual-layer' device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing. PMID:27171505

  7. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells

    NASA Astrophysics Data System (ADS)

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B.; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

    2016-06-01

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed ‘dual-layer’ device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing.

  8. Label-free and enzyme-free platform for the construction of advanced DNA logic devices based on the assembly of graphene oxide and DNA-templated AgNCs

    NASA Astrophysics Data System (ADS)

    Fan, Daoqing; Zhu, Jinbo; Liu, Yaqing; Wang, Erkang; Dong, Shaojun

    2016-02-01

    DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator.DNA-based molecular logic computation has drawn extensive attention in bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. Herein, taking 2-to-1 and 4-to-2 encoders and a 1-to-2 decoder as model molecular logic devices, we for the first time combined the quenching ability of GO (graphene oxide) to DNA-templated AgNCs with G-quadruplex-enhanced fluorescence intensity of porphyrin dyes for the construction of label-free and enzyme-free dual-output advanced DNA molecular logic devices. Also, through the application of negative logic conversion to an XOR logic gate and combined with an INHIBIT logic gate, we also operated a label-free and enzyme-free comparator. Electronic supplementary information (ESI) available: Optimization experiments, Table S1, Fig. S1-S5 in ESI. See DOI: 10.1039/c6nr00032k

  9. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  10. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    PubMed Central

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-01-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency −70 cd A−1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices. PMID:27187936

  11. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process

    NASA Astrophysics Data System (ADS)

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-05-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A-1 under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices.

  12. Efficient and mechanically robust stretchable organic light-emitting devices by a laser-programmable buckling process.

    PubMed

    Yin, Da; Feng, Jing; Ma, Rui; Liu, Yue-Feng; Zhang, Yong-Lai; Zhang, Xu-Lin; Bi, Yan-Gang; Chen, Qi-Dai; Sun, Hong-Bo

    2016-01-01

    Stretchable organic light-emitting devices are becoming increasingly important in the fast-growing fields of wearable displays, biomedical devices and health-monitoring technology. Although highly stretchable devices have been demonstrated, their luminous efficiency and mechanical stability remain impractical for the purposes of real-life applications. This is due to significant challenges arising from the high strain-induced limitations on the structure design of the device, the materials used and the difficulty of controlling the stretch-release process. Here we have developed a laser-programmable buckling process to overcome these obstacles and realize a highly stretchable organic light-emitting diode with unprecedented efficiency and mechanical robustness. The strained device luminous efficiency -70 cd A(-1) under 70% strain - is the largest to date and the device can accommodate 100% strain while exhibiting only small fluctuations in performance over 15,000 stretch-release cycles. This work paves the way towards fully stretchable organic light-emitting diodes that can be used in wearable electronic devices. PMID:27187936

  13. Digital Holographic Logic

    NASA Technical Reports Server (NTRS)

    Preston, K., Jr.

    1972-01-01

    The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

  14. Designing and simulation smart multifunctional continuous logic device as a basic cell of advanced high-performance sensor systems with MIMO-structure

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

    2015-01-01

    We have proposed a design and simulation of hardware realizations of smart multifunctional continuous logic devices (SMCLD) as advanced basic cells of the sensor systems with MIMO- structure for images processing and interconnection. The SMCLD realize function of two-valued, multi-valued and continuous logics with current inputs and current outputs. Such advanced basic cells realize function nonlinear time-pulse transformation, analog-to-digital converters and neural logic. We showed advantages of such elements. It's have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The conception of construction of SMCLD consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 50÷70 transistors, 1 PD and 1 LED makes the offered circuits quite compact. The simulation results of NOT, MIN, MAX, equivalence (EQ), normalize summation, averaging and other functions, that implemented SMCLD, showed that the level of logical variables can change from 0.1μA to 10μA for low-power consumption variants. The SMCLD have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V.

  15. Field programmable gate arrays: Evaluation report for space-flight application

    NASA Technical Reports Server (NTRS)

    Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

    1992-01-01

    Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

  16. Excitonic AND Logic Gates on DNA Brick Nanobreadboards

    PubMed Central

    2015-01-01

    A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

  17. Simulation of reconfigurable multifunctional continuous logic devices as advanced components of the next generation high-performance MIMO-systems for the processing and interconnection

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolskyy, Aleksandr I.; Lazarev, Alexander A.

    2013-12-01

    We consider design and modeling of hardware realizations of reconfigurable multifunctional continuous logic devices (R MCL D) as advanced components of the next generation high-performance MIMO-systems for the processing and interconnection. The R MCL D realize function of two-valued and continuous logics with current inputs and current outputs on the basis of CMOS current mirrors and circuits which realize the limited difference functions. We show advantages of such elements consisting in encoding of variables by the photocurrent levels, that allows easily providing optical inputs (by photo-detectors (PD)) and optical outputs (by LED). The conception of construction of R MCL D consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 55÷65 transistors, 1 PD and 1 LED makes the offered circuits quite compact and allows their integration in 1D and 2D arrays. In the presentation we consider the capabilities of the offered circuits, show the simulation results and possible prospects of application of the circuits in particular for time-pulse coding for multivalued, continuous, neuro-fuzzy and matrix logics. The simulation results of NOT, MIN, MAX, equivalence (EQ) and other functions, that implemented R MCL D, showed that the level of logical variables can change from 1 μA to 10 μA for low-power consumption variants. The base cell of the R MCL D have low power consumption <1mW and processing time about 1÷11μS at supply voltage 2.4÷3.3V. Modeling of such cells in OrCad is made.

  18. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    PubMed Central

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-01-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

  19. Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

    NASA Astrophysics Data System (ADS)

    Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

    2016-02-01

    An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

  20. flexTMS--a novel repetitive transcranial magnetic stimulation device with freely programmable stimulus currents.

    PubMed

    Gattinger, Norbert; Moessnang, Georg; Gleich, Bernhard

    2012-07-01

    Transcranial magnetic stimulation (TMS) is able to noninvasively excite neuronal populations due to brief magnetic field pulses. The efficiency and the characteristics of stimulation pulse shapes influence the physiological effect of TMS. However, commercial devices allow only a minimum of control of different pulse shapes. Basically, just sinusoidal and monophasic pulse shapes with fixed pulse widths are available. Only few research groups work on TMS devices with controllable pulse parameters such as pulse shape or pulse width. We describe a novel TMS device with a full-bridge circuit topology incorporating four insulated-gate bipolar transistor (IGBT) modules and one energy storage capacitor to generate arbitrary waveforms. This flexible TMS (flexTMS ) device can generate magnetic pulses which can be adjusted with respect to pulse width, polarity, and intensity. Furthermore, the equipment allows us to set paired pulses with a variable interstimulus interval (ISI) from 0 to 20 ms with a step size of 10  μs. All user-defined pulses can be applied continually with repetition rates up to 30 pulses per second (pps) or, respectively, up to 100 pps in theta burst mode. Offering this variety of flexibility, flexTMS will allow the enhancement of existing TMS paradigms and novel research applications. PMID:22531742

  1. LOGSIM programmer's manual

    NASA Technical Reports Server (NTRS)

    Mitchell, C. L.; Taylor, J. F.

    1976-01-01

    A programmer's manual is reported for a Logic Simulator (LOGSIM) computer program that is a large capacity event simulator with the capability to accurately simulate the effects of certain unknown states, rise and fall times, and floating nodes in large scale metal oxide semiconductor logic circuits. A detailed description of the software with flow charts is included within the report.

  2. Radiation tolerant combinational logic cell

    NASA Technical Reports Server (NTRS)

    Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

    2009-01-01

    A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

  3. Origami-inspired active graphene-based paper for programmable instant self-folding walking devices

    PubMed Central

    Mu, Jiuke; Hou, Chengyi; Wang, Hongzhi; Li, Yaogang; Zhang, Qinghong; Zhu, Meifang

    2015-01-01

    Origami-inspired active graphene-based paper with programmed gradients in vertical and lateral directions is developed to address many of the limitations of polymer active materials including slow response and violent operation methods. Specifically, we used function-designed graphene oxide as nanoscale building blocks to fabricate an all-graphene self-folding paper that has a single-component gradient structure. A functional device composed of this graphene paper can (i) adopt predesigned shapes, (ii) walk, and (iii) turn a corner. These processes can be remote-controlled by gentle light or heating. We believe that this self-folding material holds potential for a wide range of applications such as sensing, artificial muscles, and robotics. PMID:26601135

  4. Study of design-based e-beam defect inspection for hotspot detection and process window characterization on 10nm logic device

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Halder, Sandip; Di Lorenzo, Paolo; Wang, Fei; Zhang, Pengcheng; Fang, Wei; Liu, Kevin; Jau, Jack

    2016-03-01

    With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.

  5. Introducing Exclusion Logic as a Deontic Logic

    NASA Astrophysics Data System (ADS)

    Evans, Richard

    This paper introduces Exclusion Logic - a simple modal logic without negation or disjunction. We show that this logic has an efficient decision procedure. We describe how Exclusion Logic can be used as a deontic logic. We compare this deontic logic with Standard Deontic Logic and with more syntactically restricted logics.

  6. FAST TRACK COMMUNICATION: Reversible arithmetic logic unit for quantum arithmetic

    NASA Astrophysics Data System (ADS)

    Kirkedal Thomsen, Michael; Glück, Robert; Axelsen, Holger Bock

    2010-09-01

    This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks.

  7. Solid-state non-volatile electronically programmable reversible variable resistance device

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni (Inventor); Thakoor, Sarita (Inventor); Daud, Taher (Inventor); Thakoor, Aniklumar P. (Inventor)

    1989-01-01

    A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.

  8. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    PubMed Central

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-01-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1–3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top–down template definition with bottom–up three-dimensional nanoscale features. PMID:25914024

  9. Programmable definition of nanogap electronic devices using self-inhibited reagent depletion

    NASA Astrophysics Data System (ADS)

    Lam, Brian; Zhou, Wendi; Kelley, Shana O.; Sargent, Edward H.

    2015-04-01

    Electrodes exhibiting controlled nanoscale separations are required in devices for light detection, semiconductor electronics and medical diagnostics. Here we use low-cost lithography to define micron-separated electrodes, which we downscale to create three-dimensional electrodes separated by nanoscale gaps. Only by devising a new strategy, which we term electrochemical self-inhibited reagent depletion, were we able to produce a robust self-limiting nanogap manufacturing technology. We investigate the method using experiment and simulation and find that, when electrodeposition is carried out using micron-spaced electrodes simultaneously poised at the same potential, these exhibit self-inhibited reagent depletion, leading to defined and robust nanogaps. Particularly remarkable is the formation of fractal electrodes that exhibit interpenetrating jagged elements that consistently avoid electrical contact. We showcase the new technology by fabricating photodetectors with responsivities (A/W) that are one hundred times higher than previously reported photodetectors operating at the same low (1-3 V) voltages. The new strategy adds to the nanofabrication toolkit method that unites top-down template definition with bottom-up three-dimensional nanoscale features.

  10. MLS, a magnetic logic simulator for magnetic bubble logic design

    NASA Astrophysics Data System (ADS)

    Kinsman, Thomas B.; Cendes, Zoltan J.

    1987-04-01

    A computer program that simulates the logic functions of magnetic bubble devices has been developed. The program uses a color graphics screen to display the locations of bubbles on a chip during operation. It complements the simulator previously developed for modeling bubble devices on the gate level [Smith et al., IEEE Trans. Magn. MAG-19, 1835 (1983); Smith and Kryder, ibid. MAG-21, 1779 (1985)]. This new tool simplifies the design and testing of bubble logic devices, and facilitates the development of complicated LSI bubble circuits. The program operation is demonstrated with the design of an in-stream faulty loop compensator using bubble logic.

  11. G(sup 4)FET Implementations of Some Logic Circuits

    NASA Technical Reports Server (NTRS)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  12. Interference of GSM mobile phones with communication between Cardiac Rhythm Management devices and programmers: A combined in vivo and in vitro study.

    PubMed

    Huang, Dong; Dong, Zhi-Feng; Chen, Yan; Wang, Fa-Bin; Wei, Zhi; Zhao, Wen-Bin; Li, Shuai; Liu, Ming-Ya; Zhu, Wei; Wei, Meng; Li, Jing-Bo

    2015-07-01

    To investigate interference, and how to avoid it, by high-frequency electromagnetic fields (EMFs) of Global System for Mobile Communications (GSM) mobile phone with communication between cardiac rhythm management devices (CRMs) and programmers, a combined in vivo and in vitro testing was conducted. During in vivo testing, GSM mobile phones interfered with CRM-programmer communication in 33 of 65 subjects tested (50.8%). Losing ventricle sensing was representative in this study. In terms of clinical symptoms, only 4 subjects (0.6%) felt dizzy during testing. CRM-programmer communication recovered upon termination of mobile phone communication. During in vitro testing, electromagnetic interference by high-frequency (700-950 MHz) EMFs reproducibly occurred in duplicate testing in 18 of 20 CRMs (90%). During each interference, the pacing pulse signal on the programmer would suddenly disappear while the synchronous signal was normal on the amplifier-oscilloscope. Simulation analysis showed that interference by radiofrequency emitting devices with CRM-programmer communication may be attributed to factors including materials, excitation source distance, and implant depth. Results suggested that patients implanted with CRMs should not be restricted from using GSM mobile phones; however, CRMs should be kept away from high-frequency EMFs of GSM mobile phone during programming. PMID:25864643

  13. Dispositional logic

    SciTech Connect

    Zadeh, L.A.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived. 7 references.

  14. Dispositional logic

    NASA Technical Reports Server (NTRS)

    Le Balleur, J. C.

    1988-01-01

    The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

  15. Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

    NASA Astrophysics Data System (ADS)

    Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

    2016-03-01

    Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

  16. Teaching Logic.

    ERIC Educational Resources Information Center

    Dyrud, Marilyn A.

    To make introducing logic to college students in speech and expository writing classes more interesting, letters to the editor can be used to teach logical fallacies. Letters to the editor are particularly useful because they give students a sense of the community they live in (issues, concerns, and the spectrum of opinion), they are easily…

  17. Mechanical passive logic module

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay; Caulfield, H. John

    2015-02-01

    Nothing from nothing gives simple simile, but something from nothing is an interesting and challenging task. Adolf Lohmann once proposed 'do nothing machine' in optics, which only copies input to output. Passive logic module (PALM) is a special type of 'do nothing machine' which can converts inputs into one of 16 possible binary outputs. This logic module is not like the conventional irreversible one. It is a simple type of reversible Turing machine. In this manuscript we discussed and demonstrated PALM using mechanical movement of plane mirrors. Also we discussed the theoretical model of micro electro mechanical system (MEMS) based PALM in this manuscript. It may have several valuable properties such as passive operation (no need for nonlinear elements as other logic device require) and modular logic (one device implementing any Boolean logic function with simple internal changes). The result is obtained from the demonstration by only looking up the output. No calculation is required to get the result. Not only that, PALM is a simple type of the famous 'billiard ball machine', which also discussed in this manuscript.

  18. New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices

    NASA Astrophysics Data System (ADS)

    Conley, Will; Brunsvold, William R.; Buehrer, Fred; DellaGuardia, Ronald; Dobuzinsky, David; Farrell, Timothy R.; Ho, Hok; Katnani, Ahmad D.; Keller, Robin; Marsh, James T.; Muller, Paul; Nunes, Ronald; Ng, Hung Y.; Oberschmidt, James M.; Pike, Michael; Ryan, Deborah; Cotler-Wagner, Tina; Schulz, Ron; Ito, Hiroshi; Hofer, Donald C.; Breyta, Gregory; Fenzel-Alexander, Debra; Wallraff, Gregory M.; Opitz, Juliann; Thackeray, James W.; Barclay, George G.; Cameron, James F.; Lindsay, Tracy K.; Cronin, Michael F.; Moynihan, Matthew L.; Nour, Sassan; Georger, Jacque H., Jr.; Mori, Mike; Hagerty, Peter; Sinta, Roger F.; Zydowsky, Thomas M.

    1997-07-01

    This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.

  19. Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

    NASA Astrophysics Data System (ADS)

    Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2015-04-01

    Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

  20. Negative tone imaging (NTI) with KrF: extension of 248nm IIP lithography to under sub-20nm logic device

    NASA Astrophysics Data System (ADS)

    Oh, Tae-Hwan; Kim, Tae-Sun; Kim, Yura; Kim, Jahee; Heo, Sujeong; Youn, Bumjoon; Seo, Jaekyung; Yoon, Kwang-Sub; Choi, Byoung-il

    2013-03-01

    One of the most prospective alternative lithography ways prior to EUV implementation is the reverse imaging by means of a negative tone development (NTD) process with solvent-based developer. Contact and trench patterns can be printed in CAR (Chemically amplified resist) using a bright field mask through NTD development, and can give much better image contrast (NILS) than PTD process. Not only for contact or trench masks, but also pattering of IIP (Ion Implantation) layers whose mask opening ratio is less than 20% may get the benefit of NTD process, not only in the point of aerial imaging, but also in achievement of vertical resist profile, especially for post gate layers which have complex sub_topologies and nitride substrate. In this paper, we present applications for the NTD technique to IIP (Ion Implantation) layer lithography patterning, via KrF exposure, comparing the performance to that of the PTD process. Especially, to extend 248nm IIP litho to sub-20nm logic device, optimization of negative tone imaging (NTI) with KrF exposure is the main focus in this paper. With the special resin system designed for KrF NTD process, even sub 100nm half-pitch trench pattern can be defined with enough process margin and vertical resist profiles can be also obtained on the nitride substrate with KrF exposure.

  1. Description Logics

    NASA Astrophysics Data System (ADS)

    Baader, Franz

    Description Logics (DLs) are a well-investigated family of logic-based knowledge representation formalisms, which can be used to represent the conceptual knowledge of an application domain in a structured and formally well-understood way. They are employed in various application domains, such as natural language processing, configuration, and databases, but their most notable success so far is the adoption of the DL-based language OWL as standard ontology language for the semantic web.

  2. Programmable Pacemaker

    NASA Technical Reports Server (NTRS)

    1980-01-01

    St. Jude Medical's Cardiac Rhythm Management Division, formerly known as Pacesetter Systems, Inc., incorporated Apollo technology into the development of the programmable pacemaker system. This consists of the implantable pacemaker together with a physician's console containing the programmer and a data printer. Physician can communicate with patient's pacemaker by means of wireless telemetry signals transmitted through the communicating head held over the patient's chest. Where earlier pacemakers deliver a fixed type of stimulus once implanted, Programalith enables surgery free "fine tuning" of device to best suit the patient's changing needs.

  3. The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations

    NASA Astrophysics Data System (ADS)

    Lee, Junwoo; Suh, Dong Ik; Park, Wanjun

    2015-05-01

    The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.

  4. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers

    NASA Astrophysics Data System (ADS)

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-07-01

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations.For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr04069a

  5. Fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lofti A.

    1988-01-01

    The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.

  6. Fully Electrical Read-Write Device Out of a Ferromagnetic Semiconductor

    NASA Astrophysics Data System (ADS)

    Mark, S.; Dürrenfeld, P.; Pappert, K.; Ebel, L.; Brunner, K.; Gould, C.; Molenkamp, L. W.

    2011-02-01

    We report the realization of a read-write device out of the ferromagnetic semiconductor (Ga,Mn)As as the first step to a fundamentally new information processing paradigm. Writing the magnetic state is achieved by current-induced switching and readout of the state is done by the means of the tunneling anisotropic magnetoresistance effect. This 1 bit demonstrator device can be used to design an electrically programmable memory and logic device.

  7. Interlocked DNA nanostructures controlled by a reversible logic circuit.

    PubMed

    Li, Tao; Lohmann, Finn; Famulok, Michael

    2014-01-01

    DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

  8. Synthesizing Biomolecule-based Boolean Logic Gates

    PubMed Central

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2012-01-01

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

  9. New Approach on Logic Application of Ferroelectric Random Access Memory Technology

    NASA Astrophysics Data System (ADS)

    Takayama, Masao; Koyama, Shinzo; Nozawa, Hiroshi

    2002-11-01

    In this paper, a new approach is described to solve some problems that occur when ferroelectric random access memory (FeRAM) is applied to logic circuits, particularly RSA cryptography. Application of a programmable switch device to RSA-based cryptography processing circuits was explored. RSA-based cryptography processing circuits have been designed as code conversion circuits. The capacity of the code conversion programmable AND gate and FeRAM and the translation rate have been investigated as a function of bit length. As a result, a problem of huge capacity at the practical bit length can be predicted theoretically. To solve this problem, we propose a new scheme for circuits and a new algorithm of logic operation using the binomial theorem.

  10. A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers.

    PubMed

    Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

    2016-08-01

    For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. PMID:27396871

  11. Helical logic

    NASA Astrophysics Data System (ADS)

    Merkle, Ralph C.; Drexler, K. Eric

    1996-12-01

    Helical logic is a theoretical proposal for a future computing technology using the presence or absence of individual electrons (or holes) to encode 1s and 0s. The electrons are constrained to move along helical paths, driven by a rotating electric field in which the entire circuit is immersed. The electric field remains roughly orthogonal to the major axis of the helix and confines each charge carrier to a fraction of a turn of a single helical loop, moving it like water in an Archimedean screw. Each loop could in principle hold an independent carrier, permitting high information density. One computationally universal logic operation involves two helices, one of which splits into two `descendant' helices. At the point of divergence, differences in the electrostatic potential resulting from the presence or absence of a carrier in the adjacent helix controls the direction taken by a carrier in the splitting helix. The reverse of this sequence can be used to merge two initially distinct helical paths into a single outgoing helical path without forcing a dissipative transition. Because these operations are both logically and thermodynamically reversible, energy dissipation can be reduced to extremely low levels. This is the first proposal known to the authors that combines thermodynamic reversibility with the use of single charge carriers. It is important to note that this proposal permits a single electron to switch another single electron, and does not require that many electrons be used to switch one electron. The energy dissipated per logic operation can very likely be reduced to less than 0957-4484/7/4/004/img5 at a temperature of 1 K and a speed of 10 GHz, though further analysis is required to confirm this. Irreversible operations, when required, can be easily implemented and should have a dissipation approaching the fundamental limit of 0957-4484/7/4/004/img6.

  12. Optically controllable molecular logic circuits

    NASA Astrophysics Data System (ADS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-07-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

  13. Optically controllable molecular logic circuits

    SciTech Connect

    Nishimura, Takahiro Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-07-06

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

  14. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to noninvasively change one or more...

  15. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to noninvasively change one or more...

  16. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  17. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  18. 21 CFR 870.3700 - Pacemaker programmers.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Pacemaker programmers. 870.3700 Section 870.3700...) MEDICAL DEVICES CARDIOVASCULAR DEVICES Cardiovascular Prosthetic Devices § 870.3700 Pacemaker programmers. (a) Identification. A pacemaker programmer is a device used to change noninvasively one or more...

  19. Low delay and area efficient soft error correction in arbitration logic

    DOEpatents

    Sugawara, Yutaka

    2013-09-10

    There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.

  20. Summary of Proton Test on the Quick Logic QL3025 at Indiana University

    NASA Technical Reports Server (NTRS)

    Katz, Richard

    1998-01-01

    This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

  1. Adaptive parallel logic networks

    NASA Technical Reports Server (NTRS)

    Martinez, Tony R.; Vidal, Jacques J.

    1988-01-01

    Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.

  2. Efficient G(sup 4)FET-Based Logic Circuits

    NASA Technical Reports Server (NTRS)

    Vatan, Farrokh

    2008-01-01

    A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

  3. An enzyme-free and resettable platform for the construction of advanced molecular logic devices based on magnetic beads and DNA.

    PubMed

    Zhang, Siqi; Wang, Kun; Huang, Congcong; Li, Zhenyu; Sun, Ting; Han, De-Man

    2016-08-25

    A series of multiple logic circuits based on magnetic beads and DNA are constructed to perform resettable nonarithmetic functions, including a digital comparator, 4-to-2 encoder and 2-to-3 decoder, 2-to-1 encoder and 1-to-2 decoder. The signal reporter is composed of a G-quadruplex/NMM complex and a AuNP-surface immobilized molecular beacon. It is the first time that the designed DNA-based nonarithmetic nanodevices can share the same DNA platform with a reset function, which has great potential application in information processing at the molecular level. Another novel feature of the designed system is that the developed nanodevices are operated on a simple DNA/magnetic bead platform and share a constant threshold setpoint without the assistance of any negative logic conversion. The reset function is realized by heating the output system and the magnetic separation of the computing modules. Due to the biocompatibility and design flexibility of DNA, these investigations may provide a new route towards the development of resettable advanced logic circuits in biological and biomedical fields. PMID:27524500

  4. Current Mode Logic Fan Out

    Energy Science and Technology Software Center (ESTSC)

    2011-05-07

    Current mode logic is used in high speed timing systems for particle accelerators due to the fast rise time of the electrical signal. This software provides the necessary documentation to produce multiple copies of a single input for distribution to multiple devices. This software supports the DOE mission by providing a method for producing high speed signals in accelerator timing systems.

  5. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    SciTech Connect

    Berger, Andrew J. Page, Michael R.; Young, Justin R.; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris; Jacob, Jan; Lewis, Jim; Wenzel, Lothar

    2014-12-15

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  6. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

    PubMed

    Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field. PMID:25554296

  7. A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

    NASA Astrophysics Data System (ADS)

    Berger, Andrew J.; Page, Michael R.; Jacob, Jan; Young, Justin R.; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P.; Johnston-Halperin, Ezekiel; Pelekhov, Denis V.; Hammel, P. Chris

    2014-12-01

    Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

  8. Slime mould processors, logic gates and sensors.

    PubMed

    Adamatzky, A

    2015-07-28

    A heterotic, or hybrid, computation implies that two or more substrates of different physical nature are merged into a single device with indistinguishable parts. These hybrid devices then undertake coherent acts on programmable and sensible processing of information. We study the potential of heterotic computers using slime mould acting under the guidance of chemical, mechanical and optical stimuli. Plasmodium of acellular slime mould Physarum polycephalum is a gigantic single cell visible to the unaided eye. The cell shows a rich spectrum of behavioural morphological patterns in response to changing environmental conditions. Given data represented by chemical or physical stimuli, we can employ and modify the behaviour of the slime mould to make it solve a range of computing and sensing tasks. We overview results of laboratory experimental studies on prototyping of the slime mould morphological processors for approximation of Voronoi diagrams, planar shapes and solving mazes, and discuss logic gates implemented via collision of active growing zones and tactile responses of P. polycephalum. We also overview a range of electronic components--memristor, chemical, tactile and colour sensors-made of the slime mould. PMID:26078344

  9. Majority logic gate for 3D magnetic computing.

    PubMed

    Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

    2014-08-22

    For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities. PMID:25073985

  10. Majority logic gate for 3D magnetic computing

    NASA Astrophysics Data System (ADS)

    Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

    2014-08-01

    For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states ‘0’ and ‘1.’ Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

  11. Queuing register uses fluid logic elements

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Queuing register /a multistage bit-shifting device/ uses a series of pure fluid elements to perform the required logic operations. The register has several stages of three-state pure fluid elements combined with two-input NOR gates.

  12. Programmable scan/read circuitry for charge coupled device imaging detectors. [spcecraft attitude control and star trackers

    NASA Technical Reports Server (NTRS)

    Salomon, P. M.; Smilowitz, K.

    1984-01-01

    A circuit for scanning and outputting the induced charges in a solid state charge coupled device (CCD) image detector is disclosed in an image detection system for use in a spacecraft attitude control system. The image detection system includes timing control circuitry for selectively controlling the output of the CCD detector so that video outputs are provided only with respect to induced charges corresponding to predetermined sensing element lines of the CCD detector. The timing control circuit and the analog to digital converter are controlled by a programmed microprocessor which defines the video outputs to be converted and further controls the timing control circuit so that no video outputs are provided during the delay associated with analog to digital conversion.

  13. Bilayer avalanche spin-diode logic

    SciTech Connect

    Friedman, Joseph S. Querlioz, Damien; Fadel, Eric R.; Wessels, Bruce W.; Sahakian, Alan V.

    2015-11-15

    A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

  14. Bilayer avalanche spin-diode logic

    NASA Astrophysics Data System (ADS)

    Friedman, Joseph S.; Fadel, Eric R.; Wessels, Bruce W.; Querlioz, Damien; Sahakian, Alan V.

    2015-11-01

    A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

  15. Synthetic Aperture Radar Image Formation in Reconfigurable Logic

    SciTech Connect

    DUDLEY,PETER A.

    2001-06-01

    This paper studies the implementation of polar format, synthetic aperture radar image formation in modern Field Programmable Gate Arrays (FPGA's). The polar format algorithm is described in rough terms and each of the processing steps is mapped to FPGA logic. This FPGA logic is analyzed with respect to throughput and circuit size for compatibility with airborne image formation.

  16. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  17. Adaptive parallel logic networks

    SciTech Connect

    Martinez, T.R.; Vidal, J.J.

    1988-02-01

    This paper presents a novel class of special purpose processors referred to as ASOCS (adaptive self-organizing concurrent systems). Intended applications include adaptive logic devices, robotics, process control, system malfunction management, and in general, applications of logic reasoning. ASOCS combines massive parallelism with self-organization to attain a distributed mechanism for adaptation. The ASOCS approach is based on an adaptive network composed of many simple computing elements (nodes) which operate in a combinational and asynchronous fashion. Problem specification (programming) is obtained by presenting to the system if-then rules expressed as Boolean conjunctions. New rules are added incrementally. In the current model, when conflicts occur, precedence is given to the most recent inputs. With each rule, desired network response is simply presented to the system, following which the network adjusts itself to maintain consistency and parsimony of representation. Data processing and adaptation form two separate phases of operation. During processing, the network acts as a parallel hardware circuit. Control of the adaptive process is distributed among the network nodes and efficiently exploits parallelism.

  18. Oscillatory Threshold Logic

    PubMed Central

    Borresen, Jon; Lynch, Stephen

    2012-01-01

    In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

  19. Using a Commercial Ethernet PHY Device in a Radiation Environment

    NASA Technical Reports Server (NTRS)

    Parks, Jeremy; Arani, Michael; Arroyo, Roberto

    2014-01-01

    This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

  20. LOGIC CIRCUIT

    DOEpatents

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  1. Fluid logic control circuit operates nutator actuator motor

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.

  2. Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

    NASA Astrophysics Data System (ADS)

    Shin, Sunhae; Rok Kim, Kyung

    2015-06-01

    In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

  3. Fuzzy logic controller optimization

    DOEpatents

    Sepe, Jr., Raymond B; Miller, John Michael

    2004-03-23

    A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.

  4. Assembly For Moving a Robotic Device Along Selected Axes

    NASA Technical Reports Server (NTRS)

    Nowlin, Brentley Craig (Inventor); Koch, Lisa Danielle (Inventor)

    2001-01-01

    An assembly for moving a robotic device along selected axes includes a programmable logic controller (PLC) for controlling movement of the device along selected axes to effect movement of the device to a selected disposition. The PLC includes a plurality of single axis motion control modules, and a central processing unit (CPU) in communication with the motion control modules. A human-machine interface is provided for operator selection of configurations of device movements and is in communication with the CPU. A motor drive is in communication with each of the motion control modules and is operable to effect movement of the device along the selected axes to obtain movement of the device to the selected disposition.

  5. Paraconsistent quantum logics

    NASA Astrophysics Data System (ADS)

    Chiara, Maria Luisa Dalla; Giuntini, Roberto

    1989-07-01

    Paraconsistent quantum logics are weak forms of quantum logic, where the noncontradiction and the excluded-middle laws are violated. These logics find interesting applications in the operational approach to quantum mechanics. In this paper, we present an axiomatization, a Kripke-style, and an algebraic semantical characterization for two forms of paraconsistent quantum logic. Further developments are contained in Giuntini and Greuling's paper in this issue.

  6. Configuration and debug of field programmable gate arrays using MATLAB®/SIMULINK®

    NASA Astrophysics Data System (ADS)

    Grout, I.; Ryan, J.; O'Shea, T.

    2005-01-01

    Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB® model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB® model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK® model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use.

  7. OncoLogicTM

    EPA Science Inventory

    OncoLogicTM - A Computer System to Evaluate the Carcinogenic Potential of Chemicals
    OncoLogicTM is a software program that evaluates the likelihood that a chemical may cause cancer. OncoLogicTM has been peer reviewed and is being rele...

  8. Nonlinear dynamics based digital logic and circuits

    PubMed Central

    Kia, Behnam; Lindner, John. F.; Ditto, William L.

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096

  9. Nonlinear dynamics based digital logic and circuits.

    PubMed

    Kia, Behnam; Lindner, John F; Ditto, William L

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096

  10. Fuzzy logic control for an automated guided vehicle

    NASA Astrophysics Data System (ADS)

    Cao, Ming; Hall, Ernest L.

    1998-10-01

    This paper describes the use of fuzzy logic control for the high level control systems of a mobile robot. The advantages of the fuzzy logic system are that multiple types of input such as that from vision and sonar sensors as well as stored map information can be used to guide the robot. Sensor fusion can be accomplished between real time sensed information and stored information in a manner similar to a human decision maker. Vision guidance is accomplished with a CCD camera with a zoom lens. The data is collected through a commercial tracking device, communicating to the computer the X,Y coordinates of a lane marker. Testing of these systems yielded positive results by showing that at five miles per hour, the vehicle can follow a line and avoid obstacles. The obstacle detection uses information from Polaroid sonar detection system. The motor control system uses a programmable Galil motion control system. This design, in its modularity, creates a portable autonomous controller that could be used for any mobile vehicle with only minor adaptations.

  11. The Logical Extension

    NASA Technical Reports Server (NTRS)

    2003-01-01

    The same software controlling autonomous and crew-assisted operations for the International Space Station (ISS) is enabling commercial enterprises to integrate and automate manual operations, also known as decision logic, in real time across complex and disparate networked applications, databases, servers, and other devices, all with quantifiable business benefits. Auspice Corporation, of Framingham, Massachusetts, developed the Auspice TLX (The Logical Extension) software platform to effectively mimic the human decision-making process. Auspice TLX automates operations across extended enterprise systems, where any given infrastructure can include thousands of computers, servers, switches, and modems that are connected, and therefore, dependent upon each other. The concept behind the Auspice software spawned from a computer program originally developed in 1981 by Cambridge, Massachusetts-based Draper Laboratory for simulating tasks performed by astronauts aboard the Space Shuttle. At the time, the Space Shuttle Program was dependent upon paper-based procedures for its manned space missions, which typically averaged 2 weeks in duration. As the Shuttle Program progressed, NASA began increasing the length of manned missions in preparation for a more permanent space habitat. Acknowledging the need to relinquish paper-based procedures in favor of an electronic processing format to properly monitor and manage the complexities of these longer missions, NASA realized that Draper's task simulation software could be applied to its vision of year-round space occupancy. In 1992, Draper was awarded a NASA contract to build User Interface Language software to enable autonomous operations of a multitude of functions on Space Station Freedom (the station was redesigned in 1993 and converted into the international venture known today as the ISS)

  12. Fuzzy Logic Particle Tracking

    NASA Technical Reports Server (NTRS)

    2005-01-01

    A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true

  13. Programmable physiological infusion

    NASA Technical Reports Server (NTRS)

    Howard, W. H.; Young, D. R.; Adachi, R. R. (Inventor)

    1974-01-01

    A programmable physiological infusion device and method are provided wherein a program source, such as a paper tape, is used to actuate an infusion pump in accordance with a desired program. The system is particularly applicable for dispensing calcium in a variety of waveforms.

  14. Logic Design Pathology and Space Flight Electronics

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Barto, Rod L.; Erickson, K.

    1997-01-01

    Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

  15. Content-addressable-memory for the three key operations of fuzzy logic

    NASA Astrophysics Data System (ADS)

    Jiang, Tao; Li, Yao

    1999-03-01

    Today, most fuzzy logic operations are performed via software means, which is inevitably slow. While searching for long term hardware solutions to realize analog fuzzy logic operations, the use of the well-developed Boolean logic hardware with analog to digital and digital to analog converters to implement the digitized fuzzy logic could provide an efficient solution. Similar to Boolean logic, digitized fuzzy logic operations can be written as a minimized sum-of-product term format, which can then be implemented based on programmable logic arrays. We address a fundamental issue of the computational complexity of this method. We derive the minimum number of the Boolean sum-of-product terms for some key fuzzy logic operations, such as Union, Intersection, and Complement operators. Our derivations provide ways to estimate the general computational complexity or memory capacity of using binary circuits, electronic or optoelectronic, to implement the digitized analog logic operations.

  16. Toward spin-based Magneto Logic Gate in Graphene

    NASA Astrophysics Data System (ADS)

    Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

    Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

  17. Electro-optical graphene plasmonic logic gates.

    PubMed

    Ooi, Kelvin J A; Chu, Hong Son; Bai, Ping; Ang, Lay Kee

    2014-03-15

    The versatile control of graphene's plasmonic modes via an external gate-voltage inspires us to design efficient electro-optical graphene plasmonic logic gates at the midinfrared wavelengths. We show that these devices are superior to the conventional optical logic gates because the former possess cut-off states and interferometric effects. Moreover, the designed six basic logic gates (i.e., NOR/AND, NAND/OR, XNOR/XOR) achieved not only ultracompact size lengths of less than λ/28 with respect to the operating wavelength of 10 μm, but also a minimum extinction ratio as high as 15 dB. These graphene plasmonic logic gates are potential building blocks for future nanoscale midinfrared photonic integrated circuits. PMID:24690855

  18. Foundations of logic programming

    SciTech Connect

    Lloyd, J.W.

    1987-01-01

    This is the second edition of the first book to give an account of the mathematical foundations of Logic Programming. Its purpose is to collect the basic theoretical results of Logic Programming, which have previously only been available in widely scattered research papers. In addition to presenting the technical results, the book also contains many illustrative examples. Many of the examples and problems are part of the folklore of Logic Programming and are not easily obtainable elsewhere.

  19. Digital Microfluidic Logic Gates

    NASA Astrophysics Data System (ADS)

    Zhao, Yang; Xu, Tao; Chakrabarty, Krishnendu

    Microfluidic computing is an emerging application for microfluidics technology. We propose microfluidic logic gates based on digital microfluidics. Using the principle of electrowetting-on-dielectric, AND, OR, NOT and XOR gates are implemented through basic droplet-handling operations such as transporting, merging and splitting. The same input-output interpretation enables the cascading of gates to create nontrivial computing systems. We present a potential application for microfluidic logic gates by implementing microfluidic logic operations for on-chip HIV test.

  20. Chaogates: morphing logic gates that exploit dynamical patterns.

    PubMed

    Ditto, William L; Miliotis, A; Murali, K; Sinha, Sudeshna; Spano, Mark L

    2010-09-01

    Chaotic systems can yield a wide variety of patterns. Here we use this feature to generate all possible fundamental logic gate functions. This forms the basis of the design of a dynamical computing device, a chaogate, that can be rapidly morphed to become any desired logic gate. Here we review the basic concepts underlying this and present an extension of the formalism to include asymmetric logic functions. PMID:20887073

  1. Chaogates: Morphing logic gates that exploit dynamical patterns

    NASA Astrophysics Data System (ADS)

    Ditto, William L.; Miliotis, A.; Murali, K.; Sinha, Sudeshna; Spano, Mark L.

    2010-09-01

    Chaotic systems can yield a wide variety of patterns. Here we use this feature to generate all possible fundamental logic gate functions. This forms the basis of the design of a dynamical computing device, a chaogate, that can be rapidly morphed to become any desired logic gate. Here we review the basic concepts underlying this and present an extension of the formalism to include asymmetric logic functions.

  2. Fuzzy Logic Engine

    NASA Technical Reports Server (NTRS)

    Howard, Ayanna

    2005-01-01

    The Fuzzy Logic Engine is a software package that enables users to embed fuzzy-logic modules into their application programs. Fuzzy logic is useful as a means of formulating human expert knowledge and translating it into software to solve problems. Fuzzy logic provides flexibility for modeling relationships between input and output information and is distinguished by its robustness with respect to noise and variations in system parameters. In addition, linguistic fuzzy sets and conditional statements allow systems to make decisions based on imprecise and incomplete information. The user of the Fuzzy Logic Engine need not be an expert in fuzzy logic: it suffices to have a basic understanding of how linguistic rules can be applied to the user's problem. The Fuzzy Logic Engine is divided into two modules: (1) a graphical-interface software tool for creating linguistic fuzzy sets and conditional statements and (2) a fuzzy-logic software library for embedding fuzzy processing capability into current application programs. The graphical- interface tool was developed using the Tcl/Tk programming language. The fuzzy-logic software library was written in the C programming language.

  3. Complete all-optical processing polarization-based binary logic gates and optical processors.

    PubMed

    Zaghloul, Y A; Zaghloul, A R M

    2006-10-16

    We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple

  4. Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; Label, Kenneth; Kim, Kim

    2014-01-01

    An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

  5. AROUSAL AND LOGICAL INFERENCE.

    ERIC Educational Resources Information Center

    KOEN, FRANK

    THE PURPOSE OF THE EXPERIMENT WAS TO DETERMINE THE DEGREE TO WHICH PHYSIOLOGICAL AROUSAL, AS INDEXED BY THE GRASON STADLER TYPE OPERANT CONDITIONING APPARATUS (GSR), IS RELATED TO THE ACCURACY OF LOGICAL REASONING. THE STIMULI WERE 12 SYLLOGISMS, THREE OF EACH OF FOUR DIFFERENT LOGICAL FORMS. THE 14 SUBJECTS (SS) INDICATED THEIR AGREEMENT OR…

  6. Fundamentals of Digital Logic.

    ERIC Educational Resources Information Center

    Noell, Monica L.

    This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

  7. Identifying Logical Necessity

    ERIC Educational Resources Information Center

    Yopp, David

    2010-01-01

    Understanding logical necessity is an important component of proof and reasoning for teachers of grades K-8. The ability to determine exactly where young students' arguments are faulty offers teachers the chance to give youngsters feedback as they progress toward writing mathematically valid deductive proofs. As defined, logical necessity is the…

  8. Logic via Computer Programming.

    ERIC Educational Resources Information Center

    Wieschenberg, Agnes A.

    This paper proposed the question "How do we teach logical thinking and sophisticated mathematics to unsophisticated college students?" One answer among many is through the writing of computer programs. The writing of computer algorithms is mathematical problem solving and logic in disguise and it may attract students who would otherwise stop…

  9. A programmable heater control circuit for spacecraft

    NASA Technical Reports Server (NTRS)

    Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

    1994-01-01

    Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

  10. Fuzziness in abacus logic

    NASA Astrophysics Data System (ADS)

    Malhas, Othman Qasim

    1993-10-01

    The concept of “abacus logic” has recently been developed by the author (Malhas, n.d.). In this paper the relation of abacus logic to the concept of fuzziness is explored. It is shown that if a certain “regularity” condition is met, concepts from fuzzy set theory arise naturally within abacus logics. In particular it is shown that every abacus logic then has a “pre-Zadeh orthocomplementation”. It is also shown that it is then possible to associate a fuzzy set with every proposition of abacus logic and that the collection of all such sets satisfies natural conditions expected in systems of fuzzy logic. Finally, the relevance to quantum mechanics is discussed.

  11. Regulatory Conformance Checking: Logic and Logical Form

    ERIC Educational Resources Information Center

    Dinesh, Nikhil

    2010-01-01

    We consider the problem of checking whether an organization conforms to a body of regulation. Conformance is studied in a runtime verification setting. The regulation is translated to a logic, from which we synthesize monitors. The monitors are evaluated as the state of an organization evolves over time, raising an alarm if a violation is…

  12. Aerospace Ground Equipment for model 4080 sequence programmer. A standard computer terminal is adapted to provide convenient operator to device interface

    NASA Technical Reports Server (NTRS)

    Nissley, L. E.

    1979-01-01

    The Aerospace Ground Equipment (AGE) provides an interface between a human operator and a complete spaceborne sequence timing device with a memory storage program. The AGE provides a means for composing, editing, syntax checking, and storing timing device programs. The AGE is implemented with a standard Hewlett-Packard 2649A terminal system and a minimum of special hardware. The terminal's dual tape interface is used to store timing device programs and to read in special AGE operating system software. To compose a new program for the timing device the keyboard is used to fill in a form displayed on the screen.

  13. SRAM Based Re-programmable FPGA for Space Applications

    NASA Technical Reports Server (NTRS)

    Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

    1999-01-01

    An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

  14. Design and simulation of programmable relational optoelectronic time-pulse coded processors as base elements for sorting neural networks

    NASA Astrophysics Data System (ADS)

    Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

    2010-05-01

    In the paper we show that the biologically motivated conception of time-pulse encoding usage gives a set of advantages (single methodological basis, universality, tuning simplicity, learning and programming et al) at creation and design of sensor systems with parallel input-output and processing for 2D structures hybrid and next generations neuro-fuzzy neurocomputers. We show design principles of programmable relational optoelectronic time-pulse encoded processors on the base of continuous logic, order logic and temporal waves processes. We consider a structure that execute analog signal extraction, analog and time-pulse coded variables sorting. We offer optoelectronic realization of such base relational order logic element, that consists of time-pulse coded photoconverters (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutation blocks. We make technical parameters estimations of devices and processors on such base elements by simulation and experimental research: optical input signals power 0.2 - 20 uW, processing time 1 - 10 us, supply voltage 1 - 3 V, consumption power 10 - 100 uW, extended functional possibilities, learning possibilities. We discuss some aspects of possible rules and principles of learning and programmable tuning on required function, relational operation and realization of hardware blocks for modifications of such processors. We show that it is possible to create sorting machines, neural networks and hybrid data-processing systems with untraditional numerical systems and pictures operands on the basis of such quasiuniversal hardware simple blocks with flexible programmable tuning.

  15. Smart molecules at work--mimicking advanced logic operations.

    PubMed

    Andréasson, Joakim; Pischel, Uwe

    2010-01-01

    Molecular logic is an interdisciplinary research field, which has captured worldwide interest. This tutorial review gives a brief introduction into molecular logic and Boolean algebra. This serves as the basis for a discussion of the state-of-the-art and future challenges in the field. Representative examples from the most recent literature including adders/subtractors, multiplexers/demultiplexers, encoders/decoders, and sequential logic devices (keypad locks) are highlighted. Other horizons, such as the utility of molecular logic in bio-related applications, are discussed as well. PMID:20023848

  16. Applications of fuzzy logic

    SciTech Connect

    Zargham, M.R.

    1995-06-01

    Recently, fuzzy logic has been applied to many areas, such as process control, image understanding, robots, expert systems, and decision support systems. This paper will explain the basic concepts of fuzzy logic and its application in different fields. The steps to design a control system will be explained in detail. Fuzzy control is the first successful industrial application of fuzzy logic. A fuzzy controller is able to control systems which previously could only be controlled by skilled operators. In recent years Japan has achieved significant progress in this area and has applied it to variety of products such as cruise control for cars, video cameras, rice cookers, washing machines, etc.

  17. Valve system incorporating single failure protection logic

    DOEpatents

    Ryan, Rodger; Timmerman, Walter J. H.

    1980-01-01

    A valve system incorporating single failure protective logic. The system consists of a valve combination or composite valve which allows actuation or de-actuation of a device such as a hydraulic cylinder or other mechanism, integral with or separate from the valve assembly, by means of three independent input signals combined in a function commonly known as two-out-of-three logic. Using the input signals as independent and redundant actuation/de-actuation signals, a single signal failure, or failure of the corresponding valve or valve set, will neither prevent the desired action, nor cause the undesired action of the mechanism.

  18. Optical logic array processor

    SciTech Connect

    Tanida, J.; Ichioka, Y.

    1983-01-01

    A simple method for optically implementing digital logic gates in parallel has been developed. Parallel logic gates can be achieved by using a lensless shadow-casting system with a light emitting diode array as an incoherent light source. All the sixteen logic functions for two binary variables, which are the fundamental computations of Boolean algebra, can be simply realised in parallel with these gates by changing the switching modes of a led array. Parallel computation structures of the developed optical digital array processor are demonstrated by implementing pattern logics for two binary images with high space-bandwidth product. Applications of the proposed method to parallel shift operation of the image, differentiation, and processing of gray-level image are shown. 9 references.

  19. Photonic encryption using all optical logic.

    SciTech Connect

    Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.; Robertson, Perry J.; Vawter, Gregory Allen; Tarman, Thomas David; Pierson, Lyndon George

    2003-12-01

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an

  20. Spin gated transistors for reprogrammable logic

    NASA Astrophysics Data System (ADS)

    Ciccarelli, Chiara; Gonzalez-Zalba, Fernando; Irvine, Andrew; Campion, Richard; Zarbo, Liviu; Gallagher, Brian; Ferguson, Andrew; Jungwirth, Tomas; Wunderlich, Joerg; Institute of Physics ASCR Collaboration; University of Nottingham Collaboration; Hitachi Cambridge Laboratory Team; Institute of Physics ASCR Collaboration; University of Nottingham Collaboration; University of Cambridge Team

    2014-03-01

    In spin-orbit coupled magnetic materials the chemical potential depends on the orientation of the magnetisation. By making the gate of a field effect transistor magnetic, it is possible to tune the channel conductance not only electrically but also magnetically. We show that these magnetic transistor can be used to realise non-volatile reprogrammable Boolean logic. The non-volatile reconfigurable capability resides in the magnetization-dependent band structure of the magnetic stack. A change in magnetization orientation produces a change in the electrochemical potential, which induces a charge accumulation in the correspondent gate electrode. This is readily sensed by a field-effect device such as standard field-effect transistors or more exotic single-electron transistors. We propose circuits for low power consumption applications that can be magnetically switched between NAND and OR logic functions and between NOR and AND logic functions.

  1. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications

    PubMed Central

    Sun, Li; Savory, Joshua J.; Warncke, Kurt

    2014-01-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range. PMID:25076864

  2. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    PubMed

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range. PMID:25076864

  3. Nanoeletromechanical switch and logic circuits formed therefrom

    DOEpatents

    Nordquist, Christopher D.; Czaplewski, David A.

    2010-05-18

    A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

  4. Fuzzy logic based on-line fault detection and classification in transmission line.

    PubMed

    Adhikari, Shuma; Sinha, Nidul; Dorendrajit, Thingam

    2016-01-01

    This study presents fuzzy logic based online fault detection and classification of transmission line using Programmable Automation and Control technology based National Instrument Compact Reconfigurable i/o (CRIO) devices. The LabVIEW software combined with CRIO can perform real time data acquisition of transmission line. When fault occurs in the system current waveforms are distorted due to transients and their pattern changes according to the type of fault in the system. The three phase alternating current, zero sequence and positive sequence current data generated by LabVIEW through CRIO-9067 are processed directly for relaying. The result shows that proposed technique is capable of right tripping action and classification of type of fault at high speed therefore can be employed in practical application. PMID:27398278

  5. Feasibility study for future implantable neural-silicon interface devices.

    PubMed

    Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

    2011-01-01

    The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures. PMID:22254974

  6. Diagnosable structured logic array

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)

    2009-01-01

    A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

  7. The service telemetry and control device for space experiment “GRIS”

    NASA Astrophysics Data System (ADS)

    Glyanenko, A. S.

    2016-02-01

    Problems of scientific devices control (for example, fine control of measuring paths), collecting auxiliary (service information about working capacity, conditions of experiment carrying out, etc.) and preliminary data processing are actual for any space device. Modern devices for space research it is impossible to imagine without devices that didn't use digital data processing methods and specialized or standard interfaces and computing facilities. For realization of these functions in “GRIS” experiment onboard ISS for purposes minimization of dimensions, power consumption, the concept “system-on-chip” was chosen and realized. In the programmable logical integrated scheme by Microsemi from ProASIC3 family with maximum capacity up to 3M system gates, the computing kernel and all necessary peripherals are created. In this paper we discuss structure, possibilities and resources the service telemetry and control device for “GRIS” space experiment.

  8. 'Memristive' switches enable 'stateful' logic operations via material implication.

    PubMed

    Borghetti, Julien; Snider, Gregory S; Kuekes, Philip J; Yang, J Joshua; Stewart, Duncan R; Williams, R Stanley

    2010-04-01

    The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable. PMID:20376145

  9. Logic Simulator Program

    NASA Technical Reports Server (NTRS)

    Agarwal, R. K.

    1983-01-01

    The source code for the SPICE 2 program was deblocked in order to isolate and compile the subroutine in an effort to provide a software simulation of discrete and combinatorial electronic components. Incompatibilities between the UNIVAC 1180 FORTRAN and the Sigma V CP-V FORTRAN 4 were resolved. The SPICE 2 model is to be used to determine gate and fan-out delays, logic state conditions, and signal race conditions for transistor array elements and circuit logic to be patterned in the (SPI) 7101 CMOS silicon gate semicustom array. The simulator is to be operable from the CP-V time sharing terminals.

  10. Programmable Oscillator

    NASA Technical Reports Server (NTRS)

    Quirk, Kevin J.; Patawaran, Ferze D.; Nguyen, Danh H.; Lee, Clement G.; Nguyen, Huy

    2011-01-01

    A programmable oscillator is a frequency synthesizer with an output phase that tracks an arbitrary function. An offset, phase-locked loop circuit is used in combination with an error control feedback loop to precisely control the output phase of the oscillator. To down-convert the received signal, several stages of mixing may be employed with the compensation for the time-base distortion of the carrier occurring at any one of those stages. In the Goldstone Solar System Radar (GSSR), the compensation occurs in the mixing from an intermediate frequency (IF), whose value is dependent on the station and band, to a common IF used in the final stage of down-conversion to baseband. The programmable oscillator (PO) is used in the final stage of down-conversion to generate the IF, along with a time-varying phase component that matches the time-base distortion of the carrier, thus removing it from the final down-converted signal.

  11. A programmable CCD driver circuit for multiphase CCD operation

    NASA Technical Reports Server (NTRS)

    Ewin, Audrey J.; Reed, Kenneth V.

    1989-01-01

    A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

  12. 21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Fibrinopeptide A immuno-logical test system. 866.5350 Section 866.5350 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5350 Fibrinopeptide A immuno-logical...

  13. 21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Fibrinopeptide A immuno-logical test system. 866.5350 Section 866.5350 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5350 Fibrinopeptide A immuno-logical...

  14. 21 CFR 866.5330 - Factor XIII, A, S, immuno-logical test system.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Factor XIII, A, S, immuno-logical test system. 866.5330 Section 866.5330 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5330 Factor XIII, A, S, immuno-logical...

  15. Optically programmable excitonic traps

    PubMed Central

    Alloing, Mathieu; Lemaître, Aristide; Galopin, Elisabeth; Dubin, François

    2013-01-01

    With atomic systems, optically programmed trapping potentials have led to remarkable progress in quantum optics and quantum information science. Programmable trapping potentials could have a similar impact on studies of semiconductor quasi-particles, particularly excitons. However, engineering such potentials inside a semiconductor heterostructure remains an outstanding challenge and optical techniques have not yet achieved a high degree of control. Here, we synthesize optically programmable trapping potentials for indirect excitons of bilayer heterostructures. Our approach relies on the injection and spatial patterning of charges trapped in a field-effect device. We thereby imprint in-situ and on-demand electrostatic traps into which we optically inject cold and dense ensembles of excitons. This technique creates new opportunities to improve state-of-the-art technologies for the study of collective quantum behavior of excitons and also for the functionalisation of emerging exciton-based opto-electronic circuits. PMID:23546532

  16. Fuzzy logic controller to improve powerline communication

    NASA Astrophysics Data System (ADS)

    Tirrito, Salvatore

    2015-12-01

    The Power Line Communications (PLC) technology allows the use of the power grid in order to ensure the exchange of data information among devices. This work proposes an approach, based on Fuzzy Logic, that dynamically manages the amplitude of the signal, with which each node transmits, by processing the master-slave link quality measured and the master-slave distance. The main objective of this is to reduce both the impact of communication interferences induced and power consumption.

  17. Reconfigurable magnetic logic combined with non-volatile memory in silicon

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.

  18. Extremely large magnetoresistance and magnetic logic by coupling semiconductor nonlinear transport effect and anomalous Hall Effect

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaozhong; Luo, Zhaochu

    Size limitation of silicon FET hinders the further scaling down of silicon based CPU. To solve this problem, spin based magnetic logic devices were proposed but almost all of them could not be realized experimentally except for NOT logic operation. A magnetic field controlled reconfigurable semiconductor logic using InSb was reported. However, InSb is very expensive and not compatible with the silicon technology. Based on our Si based magnetoresistance (MR) device, we developed a Si based reconfigurable magnetic logic device, which could do all four Boolean logic operations including AND, OR, NOR and NAND. By coupling nonlinear transport effect of semiconductor and anomalous Hall effect of magnetic material, we propose a PMA material based MR device with a remarkable non local MR of >20000 % at ~1 mT. Based on this MR device, we further developed a PMA material based magnetic logic device which could do all four Boolean logic operations. This makes it possible that magnetic material does both memory and logic. This may result in a memory-logic integrated system leading to a non von Neumann computer

  19. Anion Sensors as Logic Gates: A Close Encounter?

    PubMed

    Madhuprasad; Bhat, Mahesh P; Jung, Ho-Young; Losic, Dusan; Kurkuri, Mahaveer D

    2016-04-25

    Computers have become smarter, smaller, and more efficient due to the downscaling of silicon-based components. Top-down miniaturisation of silicon-based computer components is fast reaching its limitations because of physical constraints and economical non-feasibility. Therefore, the possibility of a bottom-up approach that uses molecules to build nano-sized devices has been initiated. As a result, molecular logic gates based on chemical inputs and measurable optical outputs have captured significant attention very recently. In addition, it would be interesting if such molecular logic gates could be developed by making use of ion sensors, which can give significantly sensitive output information. This review provides a brief introduction to anion receptors, molecular logic gates, a comprehensive review on describing recent advances and progress on development of ion receptors for molecular logic gates, and a brief idea about the application of molecular logic gates. PMID:26890404

  20. Synthetic circuits integrating logic and memory in living cells.

    PubMed

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications. PMID:23396014

  1. Reconfigurable Boolean logic using magnetic single-electron transistors.

    PubMed

    Gonzalez-Zalba, M Fernando; Ciccarelli, Chiara; Zarbo, Liviu P; Irvine, Andrew C; Campion, Richard C; Gallagher, Bryan L; Jungwirth, Tomas; Ferguson, Andrew J; Wunderlich, Joerg

    2015-01-01

    We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistor with a GaMnAs magnetic back-gate. Changing between different logic gate functions is realized by reorienting the magnetic moments of the magnetic layer, which induces a voltage shift on the Coulomb blockade oscillations of the MSET. We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation. Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level. Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network. PMID:25923789

  2. The impact of software and CAE tools on SEU in field programmable gate arrays

    SciTech Connect

    Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

    1999-12-01

    Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.

  3. Temporal logics meet telerobotics

    NASA Technical Reports Server (NTRS)

    Rutten, Eric; Marce, Lionel

    1989-01-01

    The specificity of telerobotics being the presence of a human operator, decision assistance tools are necessary for the operator, especially in hostile environments. In order to reduce execution hazards due to a degraded ability for quick and efficient recovery of unexpected dangerous situations, it is of importance to have the opportunity, amongst others, to simulate the possible consequences of a plan before its actual execution, in order to detect these problematic situations. Hence the idea of providing the operator with a simulator enabling him to verify the temporal and logical coherence of his plans. Therefore, the power of logical formalisms is used for representation and deduction purposes. Starting from the class of situations that are represented, a STRIPS (the STanford Research Institute Problem Solver)-like formalism and its underlying logic are adapted to the simulation of plans of actions in time. The choice of a temporal logic enables to build a world representation, on which the effects of plans, grouping actions into control structures, will be transcribed by the simulation, resulting in a verdict and information about the plan's coherence.

  4. Quantum probabilistic logic programming

    NASA Astrophysics Data System (ADS)

    Balu, Radhakrishnan

    2015-05-01

    We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.

  5. Logic and Simulation.

    ERIC Educational Resources Information Center

    Straumanis, Joan

    A major problem in teaching symbolic logic is that of providing individualized and early feedback to students who are learning to do proofs. To overcome this difficulty, a computer program was developed which functions as a line-by-line proof checker in Sentential Calculus. The program, DEMON, first evaluates any statement supplied by the student…

  6. Individual software plan for the programmable logic controller

    SciTech Connect

    Green, R

    1997-07-28

    This document defines the software quality assurance plan (SQAP) as it shall be applied to the development of the monitor and control system for the Integrated Corrosion Facility (ICF). The purpose of this SQA plan is to provide guidance to the development team in software quality and associated documentation.

  7. Application of programmable logic controllers to space simulation

    NASA Technical Reports Server (NTRS)

    Sushon, Janet

    1992-01-01

    Incorporating a state-of-the-art process control and instrumentation system into a complex system for thermal vacuum testing is discussed. The challenge was to connect several independent control systems provided by various vendors to a supervisory computer. This combination will sequentially control and monitor the process, collect the data, and transmit it to color a graphic system for subsequent manipulation. The vacuum system upgrade included: replacement of seventeen diffusion pumps with eight cryogenic pumps and one turbomolecular pump, replacing a relay based control system, replacing vacuum instrumentation, and upgrading the data acquisition system.

  8. A digital magnetic resonance imaging spectrometer using digital signal processor and field programmable gate array

    NASA Astrophysics Data System (ADS)

    Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao

    2013-05-01

    A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ˜27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.

  9. A digital magnetic resonance imaging spectrometer using digital signal processor and field programmable gate array.

    PubMed

    Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao

    2013-05-01

    A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ~27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field. PMID:23742570

  10. Behavior of faulty double BJT BiCMOS logic gates

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  11. Conditional Logic and Primary Children.

    ERIC Educational Resources Information Center

    Ennis, Robert H.

    Conditional logic, as interpreted in this paper, means deductive logic characterized by "if-then" statements. This study sought to investigate the knowledge of conditional logic possessed by primary children and to test their readiness to learn such concepts. Ninety students were designated the experimental group and participated in a 15-week…

  12. Smart programmable wireless microaccelerometers

    NASA Astrophysics Data System (ADS)

    Varadan, Vijay K.; Subramanian, Hareesh; Varadan, Vasundara V.

    1998-07-01

    The integration of MEMS, SAW devices and required microelectronics and conformal antenna to realize a programmable wireless accelerometer is presented in this paper. This unique combination of technologies results in a novel accelerometer that can be remotely sensed by a microwave system with the advantage of no power requirements at the sensor site. The microaccelerometer presented is simple in construction and easy to manufacture with existing silicon micromachining techniques. Programmable accelerometers can be achieved with splitfinger interdigital transducers (IDTs) as reflecting structures. If IDTs are short circuited or capacitively loaded, the wave propagates without any reflection whereas in an open circuit configuration, the IDTs reflect the incoming SAW signal. The programmable accelerometers can thus be achieved by using an external circuitry on a semiconductor chip using hybrid technology. The relatively small size of the sensor makes it an ideal conformal sensor. The accelerometer finds application as air bag deployment sensors, vibration sensors for noise control, deflection and strain sensors, inertial and dimensional positioning systems, ABS/traction control, smart suspension, active roll stabilization and four wheel steering. The wireless accelerometer is very attractive to study the response of a `dummy' in automobile crash test.

  13. Providing Reliability of Physical Systems: Partially Programmable Circuit Design

    NASA Astrophysics Data System (ADS)

    Matrosova, A. Yu.; Ostanin, S. A.; Kirienko, I. E.

    2014-10-01

    One of the important properties of physical systems is reliability.of their functioning, in particular, reliability of functioning of logical control components of the systems. A new approach to partially programmable circuit design that allows masking stuck-at faults at gate poles of logical circuits is considered. The logical circuit consists of gates. It is supposed that only one gate pole may be fault. There are reserved programmable blocks configurable logic blocks (CLBs) based on Look Up Table (LUT) technology that may mask the fault. First, the suggested approach in contrast to the well-known ones, allows masking any stuck-at fault rather than a part of them. Second, the approach is oriented to deriving more simple masking circuit from CLBs based on a compact description of incompletely specified functions of subcircuits.

  14. The Logic of Life

    NASA Astrophysics Data System (ADS)

    Pascal, Robert; Pross, Addy

    2016-04-01

    In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the `regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both `regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.

  15. Infinitesimals without logic

    NASA Astrophysics Data System (ADS)

    Giordano, P.

    2010-06-01

    We introduce a ring of the so-called Fermat reals, which is an extension of the real field containing nilpotent infinitesimals. The construction is inspired by Smooth Infinitesimal Analysis (SIA) and provides a powerful theory of actual infinitesimals without any background in mathematical logic. In particular, in contrast to SIA, which admits models in intuitionistic logic only, the theory of Fermat reals is consistent with the classical logic. We face the problem of deciding whether or not a product of powers of nilpotent infinitesimals vanishes, study the identity principle for polynomials, and discuss the definition and properties of the total order relation. The construction is highly constructive, and every Fermat real admits a clear and order-preserving geometrical representation. Using nilpotent infinitesimals, every smooth function becomes a polynomial because the remainder in Taylor’s formulas is now zero. Finally, we present several applications to informal classical calculations used in physics, and all these calculations now become rigorous, and at the same time, formally equal to the informal ones. In particular, an interesting rigorous deduction of the wave equation is given, which clarifies how to formalize the approximations tied with Hooke’s law using the language of nilpotent infinitesimals.

  16. A molecular logic gate

    PubMed Central

    Kompa, K. L.; Levine, R. D.

    2001-01-01

    We propose a scheme for molecule-based information processing by combining well-studied spectroscopic techniques and recent results from chemical dynamics. Specifically it is discussed how optical transitions in single molecules can be used to rapidly perform classical (Boolean) logical operations. In the proposed way, a restricted number of states in a single molecule can act as a logical gate equivalent to at least two switches. It is argued that the four-level scheme can also be used to produce gain, because it allows an inversion, and not only a switching ability. The proposed scheme is quantum mechanical in that it takes advantage of the discrete nature of the energy levels but, we here discuss the temporal evolution, with the use of the populations only. On a longer time range we suggest that the same scheme could be extended to perform quantum logic, and a tentative suggestion, based on an available experiment, is discussed. We believe that the pumping can provide a partial proof of principle, although this and similar experiments were not interpreted thus far in our terms. PMID:11209046

  17. 21 CFR 892.1870 - Radiographic film/cassette changer programmer.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Radiographic film/cassette changer programmer. 892... SERVICES (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1870 Radiographic film/cassette changer programmer. (a) Identification. A radiographic film/cassette changer programmer is...

  18. Fluidic-thermochromic display device

    NASA Technical Reports Server (NTRS)

    Grafstein, D.; Hilborn, E. H.

    1968-01-01

    Fluidic decoder and display device has low-power requirements for temperature control of thermochromic materials. An electro-to-fluid converter translates incoming electrical signals into pneumatics signal of sufficient power to operate the fluidic logic elements.

  19. Flight dynamics analysis and simulation of heavy lift airships. Volume 5: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Ringland, R. F.; Tischler, M. B.; Jex, H. R.; Emmen, R. D.; Ashkenas, I. L.

    1982-01-01

    The Programmer's Manual contains explanations of the logic embodied in the various program modules, a dictionary of program variables, a subroutine listing, subroutine/common block/cross reference listing, and a calling/called subroutine cross reference listing.

  20. Development and applications of supersonic unsteady consistent aerodynamics for intering parallel wings: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Paine, A. A.

    1972-01-01

    The computer program written in support of the problem to determine aerodynamic influence coefficients on parallel interfering wings is described. The information is geared to the programmer. It is sufficient to describe the program logic and the required peripheral storage.

  1. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  2. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  3. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  4. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  5. 21 CFR 870.1750 - External programmable pacemaker pulse generator.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false External programmable pacemaker pulse generator... External programmable pacemaker pulse generator. (a) Identification. An external programmable pacemaker pulse generators is a device that can be programmed to produce one or more pulses at...

  6. Programmability of nanowire networks

    NASA Astrophysics Data System (ADS)

    Bellew, A. T.; Bell, A. P.; McCarthy, E. K.; Fairfield, J. A.; Boland, J. J.

    2014-07-01

    Electrical connectivity in networks of nanoscale junctions must be better understood if nanowire devices are to be scaled up from single wires to functional material systems. We show that the natural connectivity behaviour found in random nanowire networks presents a new paradigm for creating multi-functional, programmable materials. In devices made from networks of Ni/NiO core-shell nanowires at different length scales, we discover the emergence of distinct behavioural regimes when networks are electrically stressed. We show that a small network, with few nanowire-nanowire junctions, acts as a unipolar resistive switch, demonstrating very high ON/OFF current ratios (>105). However, large networks of nanowires distribute an applied bias across a large number of junctions, and thus respond not by switching but instead by evolving connectivity. We demonstrate that these emergent properties lead to fault-tolerant materials whose resistance may be tuned, and which are capable of adaptively reconfiguring under stress. By combining these two behavioural regimes, we demonstrate that the same nanowire network may be programmed to act both as a metallic interconnect, and a resistive switch device with high ON/OFF ratio. These results enable the fabrication of programmable, multi-functional materials from random nanowire networks.Electrical connectivity in networks of nanoscale junctions must be better understood if nanowire devices are to be scaled up from single wires to functional material systems. We show that the natural connectivity behaviour found in random nanowire networks presents a new paradigm for creating multi-functional, programmable materials. In devices made from networks of Ni/NiO core-shell nanowires at different length scales, we discover the emergence of distinct behavioural regimes when networks are electrically stressed. We show that a small network, with few nanowire-nanowire junctions, acts as a unipolar resistive switch, demonstrating very high ON

  7. The JOSHUA (J80) system programmer`s manual

    SciTech Connect

    Smetana, A.O.; McCort, J.T.; Westmoreland, B.W.

    1993-08-01

    The JOSHUA system routines (JS routines) can be used to manage a JOSHUA data base and execute JOSHUA modules on VAX/VMS and IBM/MVS computer systems. This manual provides instructions for using the JS routines and information about the internal data structures and logic used by the routines. It is intended for use primarily by JOSHUA systems programmers, however, advanced applications programmers may also find it useful. The JS routines are, as far as possible, written in ANSI FORTRAN 77 so that they are easily maintainable and easily portable to different computer systems. Nevertheless, the JOSHUA system provides features that are not available in ANSI FORTRAN 77, notably dynamic module execution and a data base of named, variable length, unformatted records, so some parts of the routines are coded in nonstandard FORTRAN or assembler (as a last resort). In most cases, the nonstandard sections of code are different for each computer system. To make it easy for programmers using the JS routines to avoid naming conflicts, the JS routines and common block all have six character names that begin with the characters {open_quotes}JS.{close_quotes} Before using this manual, one should be familiar with the JOSHUA system as described in {open_quotes}The JOSHUA Users` Manual,{close_quotes} ANSI FORTRAN 77, and at least one of the computer systems for which the JS routines have been implemented.

  8. Distributed solid state programmable thermostat/power controller

    NASA Technical Reports Server (NTRS)

    Alexander, Jane C. (Inventor); Howard, David E. (Inventor); Smith, Dennis A. (Inventor)

    2008-01-01

    A self-contained power controller having a power driver switch, programmable controller, communication port, and environmental parameter measuring device coupled to a controllable device. The self-contained power controller needs only a single voltage source to power discrete devices, analog devices, and the controlled device. The programmable controller has a run mode which, when selected, upon the occurrence of a trigger event changes the state of a power driver switch and wherein the power driver switch is maintained by the programmable controller at the same state until the occurrence of a second event.

  9. Granular acoustic switches and logic elements

    NASA Astrophysics Data System (ADS)

    Li, Feng; Anzel, Paul; Yang, Jinkyu; Kevrekidis, Panayotis G.; Daraio, Chiara

    2014-10-01

    Electrical flow control devices are fundamental components in electrical appliances and computers; similarly, optical switches are essential in a number of communication, computation and quantum information-processing applications. An acoustic counterpart would use an acoustic (mechanical) signal to control the mechanical energy flow through a solid material. Although earlier research has demonstrated acoustic diodes or circulators, no acoustic switches with wide operational frequency ranges and controllability have been realized. Here we propose and demonstrate an acoustic switch based on a driven chain of spherical particles with a nonlinear contact force. We experimentally and numerically verify that this switching mechanism stems from a combination of nonlinearity and bandgap effects. We also realize the OR and AND acoustic logic elements by exploiting the nonlinear dynamical effects of the granular chain. We anticipate these results to enable the creation of novel acoustic devices for the control of mechanical energy flow in high-performance ultrasonic devices.

  10. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    SciTech Connect

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  11. Interfacing synthetic DNA logic operations with protein outputs.

    PubMed

    Prokup, Alexander; Deiters, Alexander

    2014-11-24

    DNA logic gates are devices composed entirely of DNA that perform Boolean logic operations on one or more oligonucleotide inputs. Typical outputs of DNA logic gates are oligonucleotides or fluorescent signals. Direct activation of protein function has not been engineered as an output of a DNA-based computational circuit. Explicit control of protein activation enables the immediate triggering of enzyme function and could yield DNA computation outputs that are otherwise difficult to generate. By using zinc-finger proteins, AND, OR, and NOR logic gates were created that respond to short oligonucleotide inputs and lead to the activation or deactivation of a split-luciferase enzyme. The gate designs are simple and modular, thus enabling integration with larger multigate circuits, and the modular structure gives flexibility in the choice of protein output. The gates were also modified with translator circuits to provide protein activation in response to microRNA inputs as potential cellular cancer markers. PMID:25283524

  12. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  13. A Very Small Logical Qubit

    NASA Astrophysics Data System (ADS)

    Kapit, Eliot

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven SQUID couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multi-qubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of forty or more compared to the individual qubit T1 and T2 using this technique.

  14. Rapidly Reconfigurable All-Optical Universal Logic Gates

    SciTech Connect

    Goddard, L L; Kallman, J S; Bond, T C

    2006-06-21

    We present designs and simulations for a highly cascadable, rapidly reconfigurable, all-optical, universal logic gate. We will discuss the gate's expected performance, e.g. speed, fanout, and contrast ratio, as a function of the device layout and biasing conditions. The gate is a three terminal on-chip device that consists of: (1) the input optical port, (2) the gate selection port, and (3) the output optical port. The device can be built monolithically using a standard multiple quantum well graded index separate confinement heterostructure laser configuration. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog electrical or optical signal at the gate selection port. Specifically, the same gate can be selected to execute one of the 2 basic unary operations (NOT or COPY), or one of the 6 binary operations (OR, XOR, AND, NOR, XNOR, or NAND), or one of the many logic operations involving more than two inputs. The speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal modulation speed of a laser, which can be on the order of tens of GHz. The reprogrammable nature of the universal gate offers maximum flexibility and interchangeability for the end user since the entire application of a photonic integrated circuit built from cascaded universal logic gates can be changed simply by adjusting the gate selection port signals.

  15. An SEU immune logic family

    NASA Technical Reports Server (NTRS)

    Canaris, J.

    1991-01-01

    A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.

  16. Barriers in Concurrent Separation Logic

    NASA Astrophysics Data System (ADS)

    Hobor, Aquinas; Gherghina, Cristian

    We develop and prove sound a concurrent separation logic for Pthreads-style barriers. Although Pthreads barriers are widely used in systems, and separation logic is widely used for verification, there has not been any effort to combine the two. Unlike locks and critical sections, Pthreads barriers enable simultaneous resource redistribution between multiple threads and are inherently stateful, leading to significant complications in the design of the logic and its soundness proof. We show how our logic can be applied to a specific example program in a modular way. Our proofs are machine-checked in Coq.

  17. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls.

    PubMed

    Currivan-Incorvia, J A; Siddiqui, S; Dutta, S; Evarts, E R; Zhang, J; Bono, D; Ross, C A; Baldo, M A

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412

  18. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

    PubMed Central

    Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412

  19. Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

    NASA Astrophysics Data System (ADS)

    Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

    2016-01-01

    Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.

  20. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    NASA Astrophysics Data System (ADS)

    Gowri Sankar, P. A.; Udhayakumar, K.

    2014-07-01

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

  1. Construction of a fuzzy and Boolean logic gates based on DNA.

    PubMed

    Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

    2015-04-17

    Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics. PMID:25565140

  2. Reversible logic gates on Physarum Polycephalum

    SciTech Connect

    Schumann, Andrew

    2015-03-10

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

  3. A Logical Process Calculus

    NASA Technical Reports Server (NTRS)

    Cleaveland, Rance; Luettgen, Gerald; Bushnell, Dennis M. (Technical Monitor)

    2002-01-01

    This paper presents the Logical Process Calculus (LPC), a formalism that supports heterogeneous system specifications containing both operational and declarative subspecifications. Syntactically, LPC extends Milner's Calculus of Communicating Systems with operators from the alternation-free linear-time mu-calculus (LT(mu)). Semantically, LPC is equipped with a behavioral preorder that generalizes Hennessy's and DeNicola's must-testing preorder as well as LT(mu's) satisfaction relation, while being compositional for all LPC operators. From a technical point of view, the new calculus is distinguished by the inclusion of: (1) both minimal and maximal fixed-point operators and (2) an unimple-mentability predicate on process terms, which tags inconsistent specifications. The utility of LPC is demonstrated by means of an example highlighting the benefits of heterogeneous system specification.

  4. The logic of deterrence

    SciTech Connect

    Kenny, A.

    1985-01-01

    In The Logic of Deterrence, Kenny presents a guide to the theory and ethics of the complicated subject of deterrence. Kenny begins by examining the necessary conditions for any war to be just and then applies these principles to the cases of limited and total nuclear war. He then critiques current deterrence policies of both East and West, concluding that they are based on a willingness to kill millions of innocent people and are morally wrong. In the final section of the book, Kenny offers proposals for nuclear disarmament. Charting a course ''between the illusory hopes of the multilateralists who seek disarmament by negotiating and the impractical idealism of those who call for immediate and total unilateral disarmament by the West,'' Kenny proposes a series of phased and partial unilateral steps by the West, coupled with pressure on the East to reciprocate.

  5. Partial quantum logics revisited

    NASA Astrophysics Data System (ADS)

    Vetterlein, Thomas

    2011-01-01

    Partial Boolean algebras (PBAs) were introduced by Kochen and Specker as an algebraic model reflecting the mutual relationships among quantum-physical yes-no tests. The fact that not all pairs of tests are compatible was taken into special account. In this paper, we review PBAs from two sides. First, we generalise the concept, taking into account also those yes-no tests which are based on unsharp measurements. Namely, we introduce partial MV-algebras, and we define a corresponding logic. Second, we turn to the representation theory of PBAs. In analogy to the case of orthomodular lattices, we give conditions for a PBA to be isomorphic to the PBA of closed subspaces of a complex Hilbert space. Hereby, we do not restrict ourselves to purely algebraic statements; we rather give preference to conditions involving automorphisms of a PBA. We conclude by outlining a critical view on the logico-algebraic approach to the foundational problem of quantum physics.

  6. Quantificational logic of context

    SciTech Connect

    Buvac, Sasa

    1996-12-31

    In this paper we extend the Propositional Logic of Context, to the quantificational (predicate calculus) case. This extension is important in the declarative representation of knowledge for two reasons. Firstly, since contexts are objects in the semantics which can be denoted by terms in the language and which can be quantified over, the extension enables us to express arbitrary first-order properties of contexts. Secondly, since the extended language is no longer only propositional, we can express that an arbitrary predicate calculus formula is true in a context. The paper describes the syntax and the semantics of a quantificational language of context, gives a Hilbert style formal system, and outlines a proof of the system`s completeness.

  7. Ground State Spin Logic

    NASA Astrophysics Data System (ADS)

    Whitfield, James; Faccin, Mauro; Biamonte, Jacob

    2013-03-01

    Designing and optimizing cost functions and energy landscapes is a problem encountered in many fields of science and engineering. These landscapes and cost functions can be embedded and annealed in experimentally controllable spin Hamiltonians. Using an approach based on group theory and symmetries, we examine the embedding of Boolean logic gates into the ground-state subspace of such spin systems. We describe parameterized families of diagonal Hamiltonians and symmetry operations which preserve the ground-state subspace encoding the truth tables of Boolean formulas. The ground-state embeddings of adder circuits are used to illustrate how gates are combined and simplified using symmetry. Our work is relevant for experimental demonstrations of ground-state embeddings found in both classical optimization as well as adiabatic quantum optimization.

  8. Simulated Laboratory in Digital Logic.

    ERIC Educational Resources Information Center

    Cleaver, Thomas G.

    Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

  9. Japanese Logic Puzzles and Proof

    ERIC Educational Resources Information Center

    Wanko, Jeffrey J.

    2009-01-01

    An understanding of proof does not start in a high school geometry course. Rather, attention to logical reasoning throughout a student's school experience can help the development of proof readiness. In the spirit of problem solving, the author has begun to use some Japanese logic puzzles other than sudoku to help students develop additional…

  10. The cognitive bases for the design of a new class of fuzzy logic controllers: The clearness transformation fuzzy logic controller

    NASA Technical Reports Server (NTRS)

    Sultan, Labib; Janabi, Talib

    1992-01-01

    This paper analyses the internal operation of fuzzy logic controllers as referenced to the human cognitive tasks of control and decision making. Two goals are targeted. The first goal focuses on the cognitive interpretation of the mechanisms employed in the current design of fuzzy logic controllers. This analysis helps to create a ground to explore the potential of enhancing the functional intelligence of fuzzy controllers. The second goal is to outline the features of a new class of fuzzy controllers, the Clearness Transformation Fuzzy Logic Controller (CT-FLC), whereby some new concepts are advanced to qualify fuzzy controllers as 'cognitive devices' rather than 'expert system devices'. The operation of the CT-FLC, as a fuzzy pattern processing controller, is explored, simulated, and evaluated.

  11. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  12. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  13. Power optimization in logic isomers

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

  14. Program to Optimize Simulated Trajectories (POST). Volume 3: Programmer's manual

    NASA Technical Reports Server (NTRS)

    Brauer, G. L.; Cornick, D. E.; Habeger, A. R.; Petersen, F. M.; Stevenson, R.

    1975-01-01

    Information pertinent to the programmer and relating to the program to optimize simulated trajectories (POST) is presented. Topics discussed include: program structure and logic, subroutine listings and flow charts, and internal FORTRAN symbols. The POST core requirements are summarized along with program macrologic.

  15. What PISA Intends to and Can Possibly Achieve: A Critical Programme Theory Analysis

    ERIC Educational Resources Information Center

    Hanberger, Anders

    2014-01-01

    This article advances the enlightened discussion of the nature, logic, and possible effects of the Programme for International Student Assessment (PISA). The purpose is to analyse the assumptions regarding how PISA is to achieve its intended effects, that is, to reconstruct PISA's programme theory (PT) and to probe the validity of its…

  16. Computerized logic design of digital circuits

    NASA Technical Reports Server (NTRS)

    Gussow, S.; Oglesby, R.

    1974-01-01

    Procedure performs all work required for logic design of digital counters or sequential circuits and simplification of Boolean expressions. Program provides simple, accurate, and comprehensive logic design capability to users both experienced and totally inexperienced in logic design

  17. Design, fabrication and calibration of a novel MEMS logic gate

    NASA Astrophysics Data System (ADS)

    Tsai, Chun-Yin; Chen, Tsung-Lin

    2010-09-01

    This paper presents the design, fabrication and calibration of a novel MEMS logic gate that can perform Boolean algebra as well as logic devices composed of solid-state transistors. Unlike existing designs, the proposed design can perform either NAND gate or NOR gate functions using the same mechanical structure, but different electrical interconnects. The proposed design imposes three requirements on the fabrication process: two voltage levels carried on a suspended plate, metal-to-metal contact between shuttle electrodes and fixed electrodes, and a low process temperature (<300 °C). To fulfill these requirements, the residual stress in the fabricated device is substantial which could impair the functionality of the device. Therefore, a novel in situ film stress calibration method is developed to assist the development of the fabrication process. In a prototype design, the fabricated device is 250 μm long, 100 μm wide and of 3.97 μm gap. Experimental results show that the device can operate at 25/-25 V and 100 Hz, and achieve the proposed logic functions. In addition, several properties of this device are experimentally evaluated, including power consumption, on/off resistance, lifetime and resonant frequency.

  18. Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

    NASA Technical Reports Server (NTRS)

    Rickard, D. A.; Bodenheimer, R. E.

    1976-01-01

    Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

  19. N channel JFET based digital logic gate structure

    NASA Technical Reports Server (NTRS)

    Krasowski, Michael J. (Inventor)

    2010-01-01

    A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

  20. Contradicting logics in everyday practice.

    PubMed

    Kristiansen, Margrethe; Obstfelder, Aud; Lotherington, Ann Therese

    2016-03-21

    Purpose - Performance management is criticised as a direct challenge to the dominant logic of professionalism in health care organisations. The purpose of this paper is to report an ethnographic study that investigates how performance management and professionalism as contradicting logics are interpreted and implemented by managers and nurses in everyday practice within Norwegian nursing homes. Design/methodology/approach - The paper presents an analysis of 18 semistructured interviews and 100 hours of observation of managers and nurses from three nursing homes. The study draws on the institutional logic perspective as a theoretical framework. In the analysis, the authors searched for patterns of activities and interactions that reflected managers and nurses' coping strategies for handling contradicting logics. Qualitative content analysis was used to systematically code the data, supported by NVIVO software. Findings - The authors identified three forms of coping strategies: the adjustment of professionalism to standards, the reinforcement of professional flexibility and problem solving, and the strategic adoption of documentation. These patterns of activities and interactions reflect new organisational structures that allowed contradicting logics to co-exist. The study demonstrates that a new complex dimension of governing processes within nursing homes is the way in which managers and nurses handle the tension between contradicting logics in their daily work and clinicians' everyday practice. Originality/value - The study provides new insight into how managers and nurses reshape internal organisational structures to cope with contradicting logics in nursing homes. PMID:26964849

  1. Fuzzy logic in control systems: Fuzzy logic controller. I, II

    NASA Technical Reports Server (NTRS)

    Lee, Chuen Chien

    1990-01-01

    Recent advances in the theory and applications of fuzzy-logic controllers (FLCs) are examined in an analytical review. The fundamental principles of fuzzy sets and fuzzy logic are recalled; the basic FLC components (fuzzification and defuzzification interfaces, knowledge base, and decision-making logic) are described; and the advantages of FLCs for incorporating expert knowledge into a control system are indicated. Particular attention is given to fuzzy implication functions, the interpretation of sentence connectives (and, also), compositional operators, and inference mechanisms. Applications discussed include the FLC-guided automobile developed by Sugeno and Nishida (1985), FLC hardware systems, FLCs for subway trains and ship-loading cranes, fuzzy-logic chips, and fuzzy computers.

  2. Photonic encryption : modeling and functional analysis of all optical logic.

    SciTech Connect

    Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.

    2004-10-01

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay

  3. Suicide as social logic.

    PubMed

    Kral, M J

    1994-01-01

    Although suicide is not viewed as a mental disorder per se, it is viewed by many if not most clinicians, researchers, and lay people as a real or natural symptom of depression. It is at least most typically seen as the unfortunate, severe, yet logical end result of a chain of negative self-appraisals, negative events, and hopelessness. Extending an approach articulated by the early French sociologist Gabriel Tarde, in this paper I argue that suicide is merely an idea, albeit a very bad one, having more in common with societal beliefs and norms regarding such things as divorce, abortion, sex, politics, consumer behavior, and fashion. I make a sharp contrast between perturbation and lethality, concepts central to Edwin S. Shneidman's theory of suicide. Evidence supportive of suicide as an idea is discussed based on what we are learning from the study of history and culture, and about contagion/cluster phenomena, media/communication, and choice of method. It is suggested that certain individuals are more vulnerable to incorporate the idea and act of suicide into their concepts of self, based on the same principles by which ideas are spread throughout society. Just as suicide impacts on society, so does society impact on suicide. PMID:7825197

  4. The Logic of Reachability

    NASA Technical Reports Server (NTRS)

    Smith, David E.; Jonsson, Ari K.; Clancy, Daniel (Technical Monitor)

    2001-01-01

    In recent years, Graphplan style reachability analysis and mutual exclusion reasoning have been used in many high performance planning systems. While numerous refinements and extensions have been developed, the basic plan graph structure and reasoning mechanisms used in these systems are tied to the very simple STRIPS model of action. In 1999, Smith and Weld generalized the Graphplan methods for reachability and mutex reasoning to allow actions to have differing durations. However, the representation of actions still has some severe limitations that prevent the use of these techniques for many real-world planning systems. In this paper, we 1) separate the logic of reachability from the particular representation and inference methods used in Graphplan, and 2) extend the notions of reachability and mutual exclusion to more general notions of time and action. As it turns out, the general rules for mutual exclusion reasoning take on a remarkably clean and simple form. However, practical instantiations of them turn out to be messy, and require that we make representation and reasoning choices.

  5. Addition of flexible body option to the TOLA computer program. Part 2: User and programmer documentation

    NASA Technical Reports Server (NTRS)

    Dick, J. W.; Benda, B. J.

    1975-01-01

    User and programmer oriented documentation for the flexible body option of the Takeoff and Landing Analysis (TOLA) computer program are provided. The user information provides sufficient knowledge of the development and use of the option to enable the engineering user to successfully operate the modified program and understand the results. The programmer's information describes the option structure and logic enabling a programmer to make major revisions to this part of the TOLA computer program.

  6. Integrated all-optical logic discriminators based on plasmonic bandgap engineering

    PubMed Central

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2013-01-01

    Optical computing uses photons as information carriers, opening up the possibility for ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic devices are indispensible core components of optical computing systems. However, up to now, little experimental progress has been made in nanoscale all-optical logic discriminators, which have the function of discriminating and encoding incident light signals according to wavelength. Here, we report a strategy to realize a nanoscale all-optical logic discriminator based on plasmonic bandgap engineering in a planar plasmonic microstructure. Light signals falling within different operating wavelength ranges are differentiated and endowed with different logic state encodings. Compared with values previously reported, the operating bandwidth is enlarged by one order of magnitude. Also the SPP light source is integrated with the logic device while retaining its ultracompact size. This opens up a way to construct on-chip all-optical information processors and artificial intelligence systems. PMID:24071647

  7. Radiation Effects on Current Field Programmable Technologies

    NASA Technical Reports Server (NTRS)

    Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

    1997-01-01

    Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

  8. VLSI implementations of threshold logic-a comprehensive survey.

    PubMed

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies. PMID:18244573

  9. Slime mould foraging behaviour as optically coupled logical operations

    NASA Astrophysics Data System (ADS)

    Mayne, R.; Adamatzky, A.

    2015-04-01

    Physarum polycephalum is a macroscopic plasmodial slime mould whose apparently 'intelligent' behaviour patterns may be interpreted as computation. We employ plasmodial phototactic responses to construct laboratory prototypes of NOT and NAND logical gates with electrical inputs/outputs and optical coupling in which the slime mould plays dual roles of computing device and electrical conductor. Slime mould logical gates are fault tolerant and resettable. The results presented here demonstrate the malleability and resilience of biological systems and highlight how the innate behaviour patterns of living substrates may be used to implement useful computation.

  10. Voltage-programmable liquid optical interface

    NASA Astrophysics Data System (ADS)

    Brown, C. V.; Wells, G. G.; Newton, M. I.; McHale, G.

    2009-07-01

    Recently, there has been intense interest in photonic devices based on microfluidics, including displays and refractive tunable microlenses and optical beamsteerers that work using the principle of electrowetting. Here, we report a novel approach to optical devices in which static wrinkles are produced at the surface of a thin film of oil as a result of dielectrophoretic forces. We have demonstrated this voltage-programmable surface wrinkling effect in periodic devices with pitch lengths of between 20 and 240 µm and with response times of less than 40 µs. By a careful choice of oils, it is possible to optimize either for high-amplitude sinusoidal wrinkles at micrometre-scale pitches or more complex non-sinusoidal profiles with higher Fourier components at longer pitches. This opens up the possibility of developing rapidly responsive voltage-programmable, polarization-insensitive transmission and reflection diffraction devices and arbitrary surface profile optical devices.

  11. Knowledge representation in fuzzy logic

    NASA Technical Reports Server (NTRS)

    Zadeh, Lotfi A.

    1989-01-01

    The author presents a summary of the basic concepts and techniques underlying the application of fuzzy logic to knowledge representation. He then describes a number of examples relating to its use as a computational system for dealing with uncertainty and imprecision in the context of knowledge, meaning, and inference. It is noted that one of the basic aims of fuzzy logic is to provide a computational framework for knowledge representation and inference in an environment of uncertainty and imprecision. In such environments, fuzzy logic is effective when the solutions need not be precise and/or it is acceptable for a conclusion to have a dispositional rather than categorical validity. The importance of fuzzy logic derives from the fact that there are many real-world applications which fit these conditions, especially in the realm of knowledge-based systems for decision-making and control.

  12. Fuzzy logic and neural networks

    SciTech Connect

    Loos, J.R.

    1994-11-01

    Combine fuzzy logic`s fuzzy sets, fuzzy operators, fuzzy inference, and fuzzy rules - like defuzzification - with neural networks and you can arrive at very unfuzzy real-time control. Fuzzy logic, cursed with a very whimsical title, simply means multivalued logic, which includes not only the conventional two-valued (true/false) crisp logic, but also the logic of three or more values. This means one can assign logic values of true, false, and somewhere in between. This is where fuzziness comes in. Multi-valued logic avoids the black-and-white, all-or-nothing assignment of true or false to an assertion. Instead, it permits the assignment of shades of gray. When assigning a value of true or false to an assertion, the numbers typically used are {open_quotes}1{close_quotes} or {open_quotes}0{close_quotes}. This is the case for programmed systems. If {open_quotes}0{close_quotes} means {open_quotes}false{close_quotes} and {open_quotes}1{close_quotes} means {open_quotes}true,{close_quotes} then {open_quotes}shades of gray{close_quotes} are any numbers between 0 and 1. Therefore, {open_quotes}nearly true{close_quotes} may be represented by 0.8 or 0.9, {open_quotes}nearly false{close_quotes} may be represented by 0.1 or 0.2, and {close_quotes}your guess is as good as mine{close_quotes} may be represented by 0.5. The flexibility available to one is limitless. One can associate any meaning, such as {open_quotes}nearly true{close_quotes}, to any value of any granularity, such as 0.9999. 2 figs.

  13. Heat exchanger expert system logic

    NASA Technical Reports Server (NTRS)

    Cormier, R.

    1988-01-01

    The reduction is described of the operation and fault diagnostics of a Deep Space Network heat exchanger to a rule base by the application of propositional calculus to a set of logic statements. The value of this approach lies in the ease of converting the logic and subsequently implementing it on a computer as an expert system. The rule base was written in Process Intelligent Control software.

  14. A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

    PubMed

    Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

    2016-06-28

    Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals. PMID:27211274

  15. R-189 (C-620) air compressor control logic software documentation. Revision 1

    SciTech Connect

    Walter, K.E.

    1995-06-08

    This relates to FFTF plant air compressors. Purpose of this document is to provide an updated Computer Software Description for the software to be used on R-189 (C-620-C) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started.

  16. What Makes Children Behave Aggressively? The Inner Logic of Dutch Children in Special Education

    ERIC Educational Resources Information Center

    Visser, Marieke; Singer, Elly; van Geert, Paul L. C.; Kunnen, Saskia E.

    2009-01-01

    The ambiguous results of existing intervention programmes show the need for new ways in research on aggression among children. The present study focuses on the children's own perspective on their aggressive behaviour. Based on a constructivist approach, the inner logic of narratives about peer conflicts of 64 children in Dutch special education…

  17. Neural logic molecular, counter-intuitive.

    PubMed

    Egorov, Igor K

    2007-09-01

    A hypothesis is proposed that multiple "LOGIC" genes control Boolean logic in a neuron. Each hypothetical LOGIC gene encodes a transcription factor that regulates another LOGIC gene(s). Through transcription regulation, LOGIC genes connect into a complex circuit, such as a XOR logic gate or a two-input flip-flop logic circuit capable of retaining information. LOGIC gene duplication, mutation and recombination may result in the diversification of Boolean logic gates. Creative thinking may sometimes require counter-intuitive reasoning, rather than common sense. Such reasoning is likely to engage novel logic circuits produced by LOGIC somatic mutations. An individual's logic maturates by a mechanism of somatic hypermutation, gene conversion and recombination of LOGIC genes in precursor cells followed by selection of neurons in the brain for functional competence. In this model, a single neuron among billions in the brain may contain a unique logic circuit being the key to a hard intellectual problem. The output of a logic neuron is likely to be a neurotransmitter. This neuron is connected to other neurons in the spiking neural network. The LOGIC gene hypothesis is testable by molecular techniques. Understanding mechanisms of authentic human ingenuity may help to invent digital systems capable of creative thinking. PMID:17509937

  18. Application of linear logic to simulation

    NASA Astrophysics Data System (ADS)

    Clarke, Thomas L.

    1998-08-01

    Linear logic, since its introduction by Girard in 1987 has proven expressive and powerful. Linear logic has provided natural encodings of Turing machines, Petri nets and other computational models. Linear logic is also capable of naturally modeling resource dependent aspects of reasoning. The distinguishing characteristic of linear logic is that it accounts for resources; two instances of the same variable are considered differently from a single instance. Linear logic thus must obey a form of the linear superposition principle. A proportion can be reasoned with only once, unless a special operator is applied. Informally, linear logic distinguishes two kinds of conjunction, two kinds of disjunction, and also introduces a modal storage operator that explicitly indicates propositions that can be reused. This paper discuses the application of linear logic to simulation. A wide variety of logics have been developed; in addition to classical logic, there are fuzzy logics, affine logics, quantum logics, etc. All of these have found application in simulations of one sort or another. The special characteristics of linear logic and its benefits for simulation will be discussed. Of particular interest is a connection that can be made between linear logic and simulated dynamics by using the concept of Lie algebras and Lie groups. Lie groups provide the connection between the exponential modal storage operators of linear logic and the eigen functions of dynamic differential operators. Particularly suggestive are possible relations between complexity result for linear logic and non-computability results for dynamical systems.

  19. Pass transistor implementations of multivalued logic

    NASA Technical Reports Server (NTRS)

    Maki, G.; Whitaker, S.

    1990-01-01

    A simple straight-forward Karnaugh map logic design procedure for realization of multiple-valued logic circuits is presented in this paper. Pass transistor logic gates are used to realize multiple-valued networks. This work is an extension of pass transistor implementations for binary-valued logic.

  20. An OR logic gate based on two molecular beacons.

    PubMed

    Guo, Jing; Yang, Renqiang

    2012-03-01

    Design of elementary molecular logic gates is the key and the fundamental of performing complicated Boolean calculations. Herein, we report a strategy for constructing a DNA-based OR gate by using the mechanism of sequence recognition and the principle of fluorescence resonance energy transfer (FRET). In this system, the gate is entirely composed of a single strand of DNA (A, B and C) and the inputs are the molecular beacon probes (MB1 and MB2). Changes in fluorescence intensity confirm the realization of the OR logic operation and electrophoresis experiments verify these results. Our successful application of DNA to perform the binary operation represents that DNA can serve as an efficient biomaterial for designing molecular logic gates and devices. PMID:22278176

  1. Magnon-based logic in a multi-terminal YIG/Pt nanostructure

    NASA Astrophysics Data System (ADS)

    Ganzhorn, Kathrin; Klingler, Stefan; Wimmer, Tobias; Geprägs, Stephan; Gross, Rudolf; Huebl, Hans; Goennenwein, Sebastian T. B.

    2016-07-01

    Boolean logic is the foundation of modern digital information processing. Recently, there has been a growing interest in phenomena based on pure spin currents, which allows to move from charge to spin based logic gates. We study a proof-of-principle logic device based on the ferrimagnetic insulator Yttrium Iron Garnet, with Pt strips acting as injectors and detectors for non-equilibrium magnons. We experimentally observe incoherent superposition of magnons generated by different injectors. This allows to implement a fully functional majority gate, enabling multiple logic operations (AND and OR) in one and the same device. Clocking frequencies of the order of several GHz and straightforward down-scaling make our device promising for applications.

  2. Logic Gate Operation by DNA Translocation through Biological Nanopores.

    PubMed

    Yasuga, Hiroki; Kawano, Ryuji; Takinoue, Masahiro; Tsuji, Yutaro; Osaki, Toshihisa; Kamiya, Koki; Miki, Norihisa; Takeuchi, Shoji

    2016-01-01

    Logical operations using biological molecules, such as DNA computing or programmable diagnosis using DNA, have recently received attention. Challenges remain with respect to the development of such systems, including label-free output detection and the rapidity of operation. Here, we propose integration of biological nanopores with DNA molecules for development of a logical operating system. We configured outputs "1" and "0" as single-stranded DNA (ssDNA) that is or is not translocated through a nanopore; unlabeled DNA was detected electrically. A negative-AND (NAND) operation was successfully conducted within approximately 10 min, which is rapid compared with previous studies using unlabeled DNA. In addition, this operation was executed in a four-droplet network. DNA molecules and associated information were transferred among droplets via biological nanopores. This system would facilitate linking of molecules and electronic interfaces. Thus, it could be applied to molecular robotics, genetic engineering, and even medical diagnosis and treatment. PMID:26890568

  3. Logic Gate Operation by DNA Translocation through Biological Nanopores

    PubMed Central

    Takinoue, Masahiro; Tsuji, Yutaro; Osaki, Toshihisa; Kamiya, Koki; Miki, Norihisa; Takeuchi, Shoji

    2016-01-01

    Logical operations using biological molecules, such as DNA computing or programmable diagnosis using DNA, have recently received attention. Challenges remain with respect to the development of such systems, including label-free output detection and the rapidity of operation. Here, we propose integration of biological nanopores with DNA molecules for development of a logical operating system. We configured outputs “1” and “0” as single-stranded DNA (ssDNA) that is or is not translocated through a nanopore; unlabeled DNA was detected electrically. A negative-AND (NAND) operation was successfully conducted within approximately 10 min, which is rapid compared with previous studies using unlabeled DNA. In addition, this operation was executed in a four-droplet network. DNA molecules and associated information were transferred among droplets via biological nanopores. This system would facilitate linking of molecules and electronic interfaces. Thus, it could be applied to molecular robotics, genetic engineering, and even medical diagnosis and treatment. PMID:26890568

  4. A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

    PubMed Central

    Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

    2014-01-01

    This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

  5. A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

    PubMed

    Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

    2013-01-01

    This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

  6. Fuzzy logic control of an AGV

    NASA Astrophysics Data System (ADS)

    Kelkar, Nikhal; Samu, Tayib; Hall, Ernest L.

    1997-09-01

    Automated guided vehicles (AGVs) have many potential applications in manufacturing, medicine, space and defense. The purpose of this paper is to describe exploratory research on the design of a modular autonomous mobile robot controller. The controller incorporates a fuzzy logic approach for steering and speed control, a neuro-fuzzy approach for ultrasound sensing (not discussed in this paper) and an overall expert system. The advantages of a modular system are related to portability and transportability, i.e. any vehicle can become autonomous with minimal modifications. A mobile robot test-bed has been constructed using a golf cart base. This cart has full speed control with guidance provided by a vision system and obstacle avoidance using ultrasonic sensors. The speed and steering fuzzy logic controller is supervised by a 486 computer through a multi-axis motion controller. The obstacle avoidance system is based on a micro-controller interfaced with six ultrasonic transducers. This micro- controller independently handles all timing and distance calculations and sends a steering angle correction back to the computer via the serial line. This design yields a portable independent system in which high speed computer communication is not necessary. Vision guidance is accomplished with a CCD camera with a zoom lens. The data is collected by a vision tracking device that transmits the X, Y coordinates of the lane marker to the control computer. Simulation and testing of these systems yielded promising results. This design, in its modularity, creates a portable autonomous fuzzy logic controller applicable to any mobile vehicle with only minor adaptations.

  7. Photonic Programmable Tele-Cloning Network

    PubMed Central

    Li, Wei; Chen, Ming-Cheng

    2016-01-01

    The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling. PMID:27353838

  8. Photonic Programmable Tele-Cloning Network.

    PubMed

    Li, Wei; Chen, Ming-Cheng

    2016-01-01

    The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling. PMID:27353838

  9. Photonic Programmable Tele-Cloning Network

    NASA Astrophysics Data System (ADS)

    Li, Wei; Chen, Ming-Cheng

    2016-06-01

    The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling.

  10. Linear and passive silicon diodes, isolators, and logic gates

    NASA Astrophysics Data System (ADS)

    Li, Zhi-Yuan

    2013-12-01

    Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

  11. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    PubMed Central

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

  12. Silicon-based current-controlled reconfigurable magnetoresistance logic combined with non-volatile memory

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaozhong; Luo, Zhaochu

    2015-03-01

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success. However, the traditional development pathway is approaching its fundamental limits. Magnetoelectronics logic, especially magnetic-field-based logic, shows promise for surpassing the development limits of CMOS logic. Existing proposals of magnetic-field-based logic are based on exotic semiconductors and difficult for further technological implementation. We proposed a kind of diode-assisted geometry-enhanced low-magnetic-field magnetoresistance (MR) mechanism. It couples p-n junction's nonlinear transport characteristic and Lorentz force by geometry, and shows extremely large low-magnetic-field MR (>120% at 0.15 T) Further, it is applied to experimentally demonstrate current-controlled reconfigurable MR logic on the silicon platform at room temperature. This logic device could perform Boolean logic AND, OR, NAND and NOR in one device. Combined with non-volatile magnetic memory, this logic architecture has the advantages of current-controlled reconfiguration, zero refresh consumption, instant-on performance and would bridge the processor-memory gap.

  13. Control of electrochemical signals from quantum dots conjugated to organic materials by using DNA structure in an analog logic gate.

    PubMed

    Chen, Qi; Yoo, Si-Youl; Chung, Yong-Ho; Lee, Ji-Young; Min, Junhong; Choi, Jeong-Woo

    2016-10-01

    Various bio-logic gates have been studied intensively to overcome the rigidity of single-function silicon-based logic devices arising from combinations of various gates. Here, a simple control tool using electrochemical signals from quantum dots (QDs) was constructed using DNA and organic materials for multiple logic functions. The electrochemical redox current generated from QDs was controlled by the DNA structure. DNA structure, in turn, was dependent on the components (organic materials) and the input signal (pH). Independent electrochemical signals from two different logic units containing QDs were merged into a single analog-type logic gate, which was controlled by two inputs. We applied this electrochemical biodevice to a simple logic system and achieved various logic functions from the controlled pH input sets. This could be further improved by choosing QDs, ionic conditions, or DNA sequences. This research provides a feasible method for fabricating an artificial intelligence system. PMID:27116705

  14. Programmable multi-node quantum network design and simulation

    NASA Astrophysics Data System (ADS)

    Dasari, Venkat R.; Sadlier, Ronald J.; Prout, Ryan; Williams, Brian P.; Humble, Travis S.

    2016-05-01

    Software-defined networking offers a device-agnostic programmable framework to encode new network functions. Externally centralized control plane intelligence allows programmers to write network applications and to build functional network designs. OpenFlow is a key protocol widely adopted to build programmable networks because of its programmability, flexibility and ability to interconnect heterogeneous network devices. We simulate the functional topology of a multi-node quantum network that uses programmable network principles to manage quantum metadata for protocols such as teleportation, superdense coding, and quantum key distribution. We first show how the OpenFlow protocol can manage the quantum metadata needed to control the quantum channel. We then use numerical simulation to demonstrate robust programmability of a quantum switch via the OpenFlow network controller while executing an application of superdense coding. We describe the software framework implemented to carry out these simulations and we discuss near-term efforts to realize these applications.

  15. Fuzzy logic of Aristotelian forms

    SciTech Connect

    Perlovsky, L.I.

    1996-12-31

    Model-based approaches to pattern recognition and machine vision have been proposed to overcome the exorbitant training requirements of earlier computational paradigms. However, uncertainties in data were found to lead to a combinatorial explosion of the computational complexity. This issue is related here to the roles of a priori knowledge vs. adaptive learning. What is the a-priori knowledge representation that supports learning? I introduce Modeling Field Theory (MFT), a model-based neural network whose adaptive learning is based on a priori models. These models combine deterministic, fuzzy, and statistical aspects to account for a priori knowledge, its fuzzy nature, and data uncertainties. In the process of learning, a priori fuzzy concepts converge to crisp or probabilistic concepts. The MFT is a convergent dynamical system of only linear computational complexity. Fuzzy logic turns out to be essential for reducing the combinatorial complexity to linear one. I will discuss the relationship of the new computational paradigm to two theories due to Aristotle: theory of Forms and logic. While theory of Forms argued that the mind cannot be based on ready-made a priori concepts, Aristotelian logic operated with just such concepts. I discuss an interpretation of MFT suggesting that its fuzzy logic, combining a-priority and adaptivity, implements Aristotelian theory of Forms (theory of mind). Thus, 2300 years after Aristotle, a logic is developed suitable for his theory of mind.

  16. Auto-programmable impulse neural circuits

    NASA Technical Reports Server (NTRS)

    Watula, D.; Meador, J.

    1990-01-01

    Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.

  17. Fuzzy logic control of the building structure with CLEMR dampers

    NASA Astrophysics Data System (ADS)

    Zhang, Xiang-Cheng; Xu, Zhao-Dong; Huang, Xing-Huai; Zhu, Jun-Tao

    2013-04-01

    The semi-active control technology has been paid more attention in the field of structural vibration control due to its high controllability, excellent control effect and low power requirement. When semi-active control device are used for vibration control, some challenges must be taken into account, such as the reliability and the control strategy of the device. This study presents a new large tonnage compound lead extrusion magnetorheological (CLEMR) damper, whose mathematical model is introduced to describe the variation of damping force with current and velocity. Then a current controller based on the fuzzy logic control strategy is designed to determine control currents of the CLEMR dampers rapidly. A ten-floor frame structure with CLEMR dampers using the fuzzy logic control strategy is built and calculated by using MATLAB. Calculation results show that CLEMR dampers can reduce the seismic responses of structures effectively. Calculation results of the fuzzy logic control strategy are compared with those of the semi-active limit Hrovat control structure, the passive-off control structure, and the uncontrolled structure. Comparison results show that the fuzzy logic control strategy can determine control currents of CLEMR dampers quickly and can reduce seismic responses of the structures more effectively than the passive-off control strategy and the uncontrolled structure.

  18. Material Targets for Scaling All-Spin Logic

    NASA Astrophysics Data System (ADS)

    Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

    2016-01-01

    All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

  19. FPGA-based gating and logic for multichannel single photon counting

    SciTech Connect

    Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G; Williams, Brian P; Schaake, Jason; Humble, Travis S

    2012-01-01

    We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)

  20. A tight-binding study of logic gate circuits for adding numbers inside a molecule

    NASA Astrophysics Data System (ADS)

    Stadler, R.; Ami, S.; Forshaw, M.; Joachim, C.

    2002-06-01

    The possibilities for the design of larger diode logic circuits such as a one-bit half-adder inside a molecule are investigated, based on a recent extension of the elastic scattering quantum chemistry technique. Since any diode logic circuit for an adder needs OR-gates and AND-gates as basic components and the properties of OR-gates have already been discussed in the ballistic and tunnelling electron transport regime, we focus on the more complicated AND-gates in the present work. For this case the output current, calculated from the transmission coefficients by using the Landauer-Büttiker formula, shows four different logical levels instead of two. The origin of this level variety is analysed in detail. The concept of programmable gate logic arrays is also addressed, where for intra-molecular circuits distinct deviations from earlier macroscopic or mesoscopic implementations of this scheme are found.

  1. Fuzzy logic particle tracking velocimetry

    NASA Technical Reports Server (NTRS)

    Wernet, Mark P.

    1993-01-01

    Fuzzy logic has proven to be a simple and robust method for process control. Instead of requiring a complex model of the system, a user defined rule base is used to control the process. In this paper the principles of fuzzy logic control are applied to Particle Tracking Velocimetry (PTV). Two frames of digitally recorded, single exposure particle imagery are used as input. The fuzzy processor uses the local particle displacement information to determine the correct particle tracks. Fuzzy PTV is an improvement over traditional PTV techniques which typically require a sequence (greater than 2) of image frames for accurately tracking particles. The fuzzy processor executes in software on a PC without the use of specialized array or fuzzy logic processors. A pair of sample input images with roughly 300 particle images each, results in more than 200 velocity vectors in under 8 seconds of processing time.

  2. Intersecting Adjectives in Syllogistic Logic

    NASA Astrophysics Data System (ADS)

    Moss, Lawrence S.

    The goal of natural logic is to present and study logical systems for reasoning with sentences of (or which are reasonably close to) ordinary language. This paper explores simple systems of natural logic which make use of intersecting adjectives; these are adjectives whose interpretation does not vary with the noun they modify. Our project in this paper is to take one of the simplest syllogistic fragments, that of all and some, and to add intersecting adjectives. There are two ways to do this, depending on whether one allows iteration or prefers a "flat" structure of at most one adjective. We present rules of inference for both types of syntax, and these differ. The main results are four completeness theorems: for each of the two types of syntax we have completeness for the all fragment and for the full language of this paper.

  3. Achieving stabilization in interferometric logic operations.

    PubMed

    Zavalin, Andrey I; Shamir, Joseph; Vikram, Chandra S; Caulfield, H John

    2006-01-10

    Interferometric systems with amplitude beam splitters can implement reversible operations that, on detection, become Boolean operators. Being passive, they consume no energy, do not limit the operating bandwidth, and have negligible latency. Unfortunately, conventional interferometric systems are notoriously sensitive to uncontrolled disturbances. Here the use of polarization in a common-path interferometric logic gate with and without polarization beam splitters is explored as an attractive alternative to overcome those difficulties. Two of three device configurations considered offer significant stability and lower drive modulator voltage as advantages over the previous systems. The first experimental tests of such a system are reported. Common-path interferometry lends itself to even more stability and robustness by compatibility with no-air-gap, solid optics. PMID:16422166

  4. Achieving stabilization in interferometric logic operations

    NASA Astrophysics Data System (ADS)

    Zavalin, Andrey I.; Shamir, Joseph; Vikram, Chandra S.; Caulfield, H. John

    2006-01-01

    Interferometric systems with amplitude beam splitters can implement reversible operations that, on detection, become Boolean operators. Being passive, they consume no energy, do not limit the operating bandwidth, and have negligible latency. Unfortunately, conventional interferometric systems are notoriously sensitive to uncontrolled disturbances. Here the use of polarization in a common-path interferometric logic gate with and without polarization beam splitters is explored as an attractive alternative to overcome those difficulties. Two of three device configurations considered offer significant stability and lower drive modulator voltage as advantages over the previous systems. The first experimental tests of such a system are reported. Common-path interferometry lends itself to even more stability and robustness by compatibility with no-air-gap, solid optics.

  5. The semantics of fuzzy logic

    NASA Technical Reports Server (NTRS)

    Ruspini, Enrique H.

    1991-01-01

    Summarized here are the results of recent research on the conceptual foundations of fuzzy logic. The focus is primarily on the principle characteristics of a model that quantifies resemblance between possible worlds by means of a similarity function that assigns a number between 0 and 1 to every pair of possible worlds. Introduction of such a function permits one to interpret the major constructs and methods of fuzzy logic: conditional and unconditional possibility and necessity distributions and the generalized modus ponens of Zadeh on the basis of related metric relationships between subsets of possible worlds.

  6. A Logical Approach to Entanglement

    NASA Astrophysics Data System (ADS)

    Das, Abhishek

    2016-05-01

    In this paper we innovate a logical approach to develop an intuition regarding the phenomenon of quantum entanglement. In the vein of the logic introduced we substantiate that particles that were entangled in the past will be entangled in perpetuity and thereby abide a rule that restricts them to act otherwise. We also introduce a game and by virtue of the concept of Nash equilibrium we have been able to show that entangled particles will mutually correspond to an experiment that is performed on any one of the particle.

  7. Logic programming and metadata specifications

    NASA Technical Reports Server (NTRS)

    Lopez, Antonio M., Jr.; Saacks, Marguerite E.

    1992-01-01

    Artificial intelligence (AI) ideas and techniques are critical to the development of intelligent information systems that will be used to collect, manipulate, and retrieve the vast amounts of space data produced by 'Missions to Planet Earth.' Natural language processing, inference, and expert systems are at the core of this space application of AI. This paper presents logic programming as an AI tool that can support inference (the ability to draw conclusions from a set of complicated and interrelated facts). It reports on the use of logic programming in the study of metadata specifications for a small problem domain of airborne sensors, and the dataset characteristics and pointers that are needed for data access.

  8. Quantum Decoherence: A Logical Perspective

    NASA Astrophysics Data System (ADS)

    Fortin, Sebastian; Vanni, Leonardo

    2014-12-01

    The so-called classical limit of quantum mechanics is generally studied in terms of the decoherence of the state operator that characterizes a system. This is not the only possible approach to decoherence. In previous works we have presented the possibility of studying the classical limit in terms of the decoherence of relevant observables of the system. On the basis of this approach, in this paper we introduce the classical limit from a logical perspective, by studying the way in which the logical structure of quantum properties corresponding to relevant observables acquires Boolean characteristics.

  9. The Early Development of Programmable Machinery.

    ERIC Educational Resources Information Center

    Collins, Martin D.

    1985-01-01

    Programmable equipment innovations, precursors of today's technology, are examined, including the development of the binary code and feedback control systems, such as temperature sensing devices, interchangeable parts, punched cards carrying instructions, continuous flow oil refining process, assembly lines for mass production, and the…

  10. Nanomagnet Logic: Architectures, design, and benchmarking

    NASA Astrophysics Data System (ADS)

    Kurtz, Steven J.

    Nanomagnet Logic (NML) is an emerging technology being studied as a possible replacement or supplementary device for Complimentary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FET) by the year 2020. NML devices offer numerous potential advantages including: low energy operation, steady state non-volatility, radiation hardness and a clear path to fabrication and integration with CMOS. However, maintaining both low-energy operation and non-volatility while scaling from the device to the architectural level is non-trivial as (i) nearest neighbor interactions within NML circuits complicate the modeling of ensemble nanomagnet behavior and (ii) the energy intensive clock structures required for re-evaluation and NML's relatively high latency challenge its ability to offer system-level performance wins against other emerging nanotechnologies. Thus, further research efforts are required to model more complex circuits while also identifying circuit design techniques that balance low-energy operation with steady state non-volatility. In addition, further work is needed to design and model low-power on-chip clocks while simultaneously identifying application spaces where NML systems (including clock overhead) offer sufficient energy savings to merit their inclusion in future processors. This dissertation presents research advancing the understanding and modeling of NML at all levels including devices, circuits, and line clock structures while also benchmarking NML against both scaled CMOS and tunneling FETs (TFET) devices. This is accomplished through the development of design tools and methodologies for (i) quantifying both energy and stability in NML circuits and (ii) evaluating line-clocked NML system performance. The application of these newly developed tools improves the understanding of ideal design criteria (i.e., magnet size, clock wire geometry, etc.) for NML architectures. Finally, the system-level performance evaluation tool offers the ability to

  11. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  12. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  13. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  14. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  15. 21 CFR 870.1425 - Programmable diagnostic computer.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Programmable diagnostic computer. 870.1425 Section 870.1425 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... diagnostic computer. (a) Identification. A programmable diagnostic computer is a device that can...

  16. Orthogonally modulated molecular transport junctions for resettable electronic logic gates

    PubMed Central

    Meng, Fanben; Hervault, Yves-Marie; Shao, Qi; Hu, Benhui; Norel, Lucie; Rigaut, Stéphane; Chen, Xiaodong

    2014-01-01

    Individual molecules have been demonstrated to exhibit promising applications as functional components in the fabrication of computing nanocircuits. Based on their advantage in chemical tailorability, many molecular devices with advanced electronic functions have been developed, which can be further modulated by the introduction of external stimuli. Here, orthogonally modulated molecular transport junctions are achieved via chemically fabricated nanogaps functionalized with dithienylethene units bearing organometallic ruthenium fragments. The addressable and stepwise control of molecular isomerization can be repeatedly and reversibly completed with a judicious use of the orthogonal optical and electrochemical stimuli to reach the controllable switching of conductivity between two distinct states. These photo-/electro-cooperative nanodevices can be applied as resettable electronic logic gates for Boolean computing, such as a two-input OR and a three-input AND-OR. The proof-of-concept of such logic gates demonstrates the possibility to develop multifunctional molecular devices by rational chemical design. PMID:24394717

  17. Use of Fuzzy Logic Systems for Assessment of Primary Faults

    NASA Astrophysics Data System (ADS)

    Petrović, Ivica; Jozsa, Lajos; Baus, Zoran

    2015-09-01

    In electric power systems, grid elements are often subjected to very complex and demanding disturbances or dangerous operating conditions. Determining initial fault or cause of those states is a difficult task. When fault occurs, often it is an imperative to disconnect affected grid element from the grid. This paper contains an overview of possibilities for using fuzzy logic in an assessment of primary faults in the transmission grid. The tool for this task is SCADA system, which is based on information of currents, voltages, events of protection devices and status of circuit breakers in the grid. The function model described with the membership function and fuzzy logic systems will be presented in the paper. For input data, diagnostics system uses information of protection devices tripping, states of circuit breakers and measurements of currents and voltages before and after faults.

  18. Magnetic skyrmion logic gates: conversion, duplication and merging of skyrmions

    PubMed Central

    Zhang, Xichao; Ezawa, Motohiko; Zhou, Yan

    2015-01-01

    Magnetic skyrmions, which are topological particle-like excitations in ferromagnets, have attracted a lot of attention recently. Skyrmionics is an attempt to use magnetic skyrmions as information carriers in next generation spintronic devices. Proposals of manipulations and operations of skyrmions are highly desired. Here, we show that the conversion, duplication and merging of isolated skyrmions with different chirality and topology are possible all in one system. We also demonstrate the conversion of a skyrmion into another form of a skyrmion, i.e., a bimeron. We design spin logic gates such as the AND and OR gates based on manipulations of skyrmions. These results provide important guidelines for utilizing the topology of nanoscale spin textures as information carriers in novel magnetic sensors and spin logic devices. PMID:25802991

  19. Orthogonally modulated molecular transport junctions for resettable electronic logic gates

    NASA Astrophysics Data System (ADS)

    Meng, Fanben; Hervault, Yves-Marie; Shao, Qi; Hu, Benhui; Norel, Lucie; Rigaut, Stéphane; Chen, Xiaodong

    2014-01-01

    Individual molecules have been demonstrated to exhibit promising applications as functional components in the fabrication of computing nanocircuits. Based on their advantage in chemical tailorability, many molecular devices with advanced electronic functions have been developed, which can be further modulated by the introduction of external stimuli. Here, orthogonally modulated molecular transport junctions are achieved via chemically fabricated nanogaps functionalized with dithienylethene units bearing organometallic ruthenium fragments. The addressable and stepwise control of molecular isomerization can be repeatedly and reversibly completed with a judicious use of the orthogonal optical and electrochemical stimuli to reach the controllable switching of conductivity between two distinct states. These photo-/electro-cooperative nanodevices can be applied as resettable electronic logic gates for Boolean computing, such as a two-input OR and a three-input AND-OR. The proof-of-concept of such logic gates demonstrates the possibility to develop multifunctional molecular devices by rational chemical design.

  20. Enzyme-based logic gates switchable between OR, NXOR and NAND Boolean operations realized in a flow system.

    PubMed

    Fratto, Brian E; Roby, Lucas J; Guz, Nataliia; Katz, Evgeny

    2014-10-18

    The enzyme-based system performing a biocatalytic cascade reaction was realized in a flow device and was used to mimic Boolean logic operations. Chemical inputs applied to the system resulted in the activation of additional reaction steps, allowing the reversible switch of the logic operations between OR, NXOR and NAND gates for processing of two other biomolecular inputs. PMID:25174490

  1. Quantum logic gates based on ballistic transport in graphene

    NASA Astrophysics Data System (ADS)

    Dragoman, Daniela; Dragoman, Mircea

    2016-03-01

    The paper presents various configurations for the implementation of graphene-based Hadamard, C-phase, controlled-NOT, and Toffoli gates working at room temperature. These logic gates, essential for any quantum computing algorithm, involve ballistic graphene devices for qubit generation and processing and can be fabricated using existing nanolithographical techniques. All quantum gate configurations are based on the very large mean-free-paths of carriers in graphene at room temperature.

  2. Biosensors with Built-In Biomolecular Logic Gates for Practical Applications

    PubMed Central

    Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh

    2014-01-01

    Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423

  3. Biosensors with built-in biomolecular logic gates for practical applications.

    PubMed

    Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh

    2014-09-01

    Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating "sense and act" schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423

  4. Multichannel optical sensing device

    DOEpatents

    Selkowitz, S.E.

    1985-08-16

    A multichannel optical sensing device is disclosed, for measuring the outdoor sky luminance or illuminance or the luminance or illuminance distribution in a room, comprising a plurality of light receptors, an optical shutter matrix including a plurality of liquid crystal optical shutter elements operable by electrical control signals between light transmitting and light stopping conditions, fiber optical elements connected between the receptors and the shutter elements, a microprocessor based programmable control unit for selectively supplying control signals to the optical shutter elements in a programmable sequence, a photodetector including an optical integrating spherical chamber having an input port for receiving the light from the shutter matrix and at least one detector element in the spherical chamber for producing output signals corresponding to the light, and output units for utilizing the output signals including a storage unit having a control connection to the microprocessor based programmable control unit for storing the output signals under the sequence control of the programmable control unit.

  5. Multichannel optical sensing device

    DOEpatents

    Selkowitz, Stephen E.

    1990-01-01

    A multichannel optical sensing device is disclosed, for measuring the outr sky luminance or illuminance or the luminance or illuminance distribution in a room, comprising a plurality of light receptors, an optical shutter matrix including a plurality of liquid crystal optical shutter elements operable by electrical control signals between light transmitting and light stopping conditions, fiber optic elements connected between the receptors and the shutter elements, a microprocessor based programmable control unit for selectively supplying control signals to the optical shutter elements in a programmable sequence, a photodetector including an optical integrating spherical chamber having an input port for receiving the light from the shutter matrix and at least one detector element in the spherical chamber for producing output signals corresponding to the light, and output units for utilizing the output signals including a storage unit having a control connection to the microprocessor based programmable control unit for storing the output signals under the sequence control of the programmable control unit.

  6. Miniaturization of magnetic logic circuitry

    NASA Technical Reports Server (NTRS)

    Baba, P. D.

    1969-01-01

    Magnetic logic circuit design features two ferrite materials, with different formulation and magnetic characteristics, which are bonded into a continuous structure by preparing the materials as a slurry and using the doctor blade method to form flexible ferrite sheets. After firing, the sintering process was continuous across the bond.

  7. Logical Empiricism, Politics, and Professionalism

    ERIC Educational Resources Information Center

    Edgar, Scott

    2009-01-01

    This paper considers George A. Reisch's account of the role of Cold War political forces in shaping the apolitical stance that came to dominate philosophy of science in the late 1940s and 1950s. It argues that at least as early as the 1930s, Logical Empiricists such as Rudolf Carnap already held that philosophy of science could not properly have…

  8. Boggle Logic Puzzles: Minimal Solutions

    ERIC Educational Resources Information Center

    Needleman, Jonathan

    2013-01-01

    Boggle logic puzzles are based on the popular word game Boggle played backwards. Given a list of words, the problem is to recreate the board. We explore these puzzles on a 3 x 3 board and find the minimum number of three-letter words needed to create a puzzle with a unique solution. We conclude with a series of open questions.

  9. Program Theory Evaluation: Logic Analysis

    ERIC Educational Resources Information Center

    Brousselle, Astrid; Champagne, Francois

    2011-01-01

    Program theory evaluation, which has grown in use over the past 10 years, assesses whether a program is designed in such a way that it can achieve its intended outcomes. This article describes a particular type of program theory evaluation--logic analysis--that allows us to test the plausibility of a program's theory using scientific knowledge.…

  10. Gateways to Writing Logical Arguments

    ERIC Educational Resources Information Center

    McCann, Thomas M.

    2010-01-01

    Middle school and high school students have a conception of what the basic demands of logic are, and they draw on this understanding in anticipating certain demands of parents and teachers when the adolescents have to defend positions. At the same time, many adolescents struggle to "write" highly elaborated arguments. Teaching students lessons in…

  11. The Temporal Logic Model Concept.

    ERIC Educational Resources Information Center

    den Heyer, Molly

    2002-01-01

    Proposes an alternative program logic model based on the concepts of learning organizations and systems theory. By redefining time as an evolutionary process, the model provides a space for stakeholders to record changes in program context, interim assessments, and program modifications. (SLD)

  12. Generic physical protection logic trees

    SciTech Connect

    Paulus, W.K.

    1981-10-01

    Generic physical protection logic trees, designed for application to nuclear facilities and materials, are presented together with a method of qualitative evaluation of the trees for design and analysis of physical protection systems. One or more defense zones are defined where adversaries interact with the physical protection system. Logic trees that are needed to describe the possible scenarios within a defense zone are selected. Elements of a postulated or existing physical protection system are tagged to the primary events of the logic tree. The likelihood of adversary success in overcoming these elements is evaluated on a binary, yes/no basis. The effect of these evaluations is propagated through the logic of each tree to determine whether the adversary is likely to accomplish the end event of the tree. The physical protection system must be highly likely to overcome the adversary before he accomplishes his objective. The evaluation must be conducted for all significant states of the site. Deficiencies uncovered become inputs to redesign and further analysis, closing the loop on the design/analysis cycle.

  13. Mathematical Induction: Deductive Logic Perspective

    ERIC Educational Resources Information Center

    Dogan, Hamide

    2016-01-01

    Many studies mentioned the deductive nature of Mathematical Induction (MI) proofs but almost all fell short in explaining its potential role in the formation of the misconceptions reported in the literature. This paper is the first of its kind looking at the misconceptions from the perspective of the abstract of the deductive logic from one's…

  14. Implementing Exclusive-OR Logic

    NASA Technical Reports Server (NTRS)

    Hough, M. E.

    1983-01-01

    Two integrated circuits, BCD-to-decimal decoder and four-input NAND gate, form basic four, input XOR circuit. Multiple-input exclusive-OR logic is implemented by combining several basic elements. 16-input XOR gate is assembled from five NAND gates and five decoders. Same principle extended to handle more inputs.

  15. Coreflections in Algebraic Quantum Logic

    NASA Astrophysics Data System (ADS)

    Jacobs, Bart; Mandemaker, Jorik

    2012-07-01

    Various generalizations of Boolean algebras are being studied in algebraic quantum logic, including orthomodular lattices, orthomodular po-sets, orthoalgebras and effect algebras. This paper contains a systematic study of the structure in and between categories of such algebras. It does so via a combination of totalization (of partially defined operations) and transfer of structure via coreflections.

  16. The Logic of Research Evaluation

    ERIC Educational Resources Information Center

    Scriven, Michael; Coryn, Chris L. S.

    2008-01-01

    The authors offer suggestions about logical distinctions often overlooked in the evaluation of research, beginning with a strong plea not to treat technology as applied science, and especially not to treat research in technology as important only if it makes a contribution to scientific knowledge. They argue that the frameworks illustrated in this…

  17. Soft computing and fuzzy logic

    SciTech Connect

    Zadeh, L.A.

    1994-12-31

    Soft computing is a collection of methodologies that aim to exploit the tolerance for imprecision and uncertainty to achieve tractability, robustness, and low solution cost. Its principal constituents are fuzzy logic, neuro-computing, and probabilistic reasoning. Soft computing is likely to play an increasingly important role in many application areas, including software engineering. The role model for soft computing is the human mind.

  18. Nanomechanical molecular devices made of DNA origami.

    PubMed

    Kuzuya, Akinori; Ohya, Yuichi

    2014-06-17

    CONSPECTUS: Eight years have passed since the striking debut of the DNA origami technique ( Rothemund, P. W. K. Nature 2006 , 440 , 297 - 302 ), in which long single-stranded DNA is folded into a designed nanostructure, in either 2D or 3D, with the aid of many short staple strands. The number of proposals for new design principles for DNA origami structures seems to have already reached a peak. It is apparent that DNA origami study is now entering the second phase of creating practical applications. The development of functional nanomechanical molecular devices using the DNA origami technique is one such application attracting significant interest from researchers in the field. Nanomechanical DNA origami devices, which maintain the characteristics of DNA origami structures, have various advantages over conventional DNA nanomachines. Comparatively high assembly yield, relatively large size visible via atomic force microscopy (AFM) or transmission electron microscopy (TEM), and the capability to assemble multiple functional groups with precision using multiple staple strands are some of the advantages of the DNA origami technique for constructing sophisticated molecular devices. This Account describes the recent developments of such nanomechanical DNA origami devices and reviews the emerging target of DNA origami studies. First, simple "dynamic" DNA origami structures with transformation capability, such as DNA origami boxes and a DNA origami hatch with structure control, are briefly summarized. More elaborate nanomechanical DNA origami devices are then reviewed. The first example describes DNA origami pinching devices that can be used as "single-molecule" beacons to detect a variety of biorelated molecules, from metal ions at the size of a few tens of atomic mass number units to relatively gigantic proteins with a molecular mass greater than a hundred kilodaltons, all on a single platform. Clamshell-like DNA nanorobots equipped with logic gates can discriminate

  19. Learning fuzzy logic control system

    NASA Technical Reports Server (NTRS)

    Lung, Leung Kam

    1994-01-01

    The performance of the Learning Fuzzy Logic Control System (LFLCS), developed in this thesis, has been evaluated. The Learning Fuzzy Logic Controller (LFLC) learns to control the motor by learning the set of teaching values that are generated by a classical PI controller. It is assumed that the classical PI controller is tuned to minimize the error of a position control system of the D.C. motor. The Learning Fuzzy Logic Controller developed in this thesis is a multi-input single-output network. Training of the Learning Fuzzy Logic Controller is implemented off-line. Upon completion of the training process (using Supervised Learning, and Unsupervised Learning), the LFLC replaces the classical PI controller. In this thesis, a closed loop position control system of a D.C. motor using the LFLC is implemented. The primary focus is on the learning capabilities of the Learning Fuzzy Logic Controller. The learning includes symbolic representation of the Input Linguistic Nodes set and Output Linguistic Notes set. In addition, we investigate the knowledge-based representation for the network. As part of the design process, we implement a digital computer simulation of the LFLCS. The computer simulation program is written in 'C' computer language, and it is implemented in DOS platform. The LFLCS, designed in this thesis, has been developed on a IBM compatible 486-DX2 66 computer. First, the performance of the Learning Fuzzy Logic Controller is evaluated by comparing the angular shaft position of the D.C. motor controlled by a conventional PI controller and that controlled by the LFLC. Second, the symbolic representation of the LFLC and the knowledge-based representation for the network are investigated by observing the parameters of the Fuzzy Logic membership functions and the links at each layer of the LFLC. While there are some limitations of application with this approach, the result of the simulation shows that the LFLC is able to control the angular shaft position of the

  20. Phrase-programmable digital speech system

    SciTech Connect

    Raymond, W.J.; Morgan, R.L.; Miller, R.L.

    1987-01-27

    This patent describes a phrase speaking computer system having a programmable digital computer and a speech processor, the speech processor comprising: a voice synthesizer; a read/write speech data segment memory; a read/write command memory; control processor means including processor control programs and logic connecting to the memories and to the voice synthesizer. It is arranged to scan the command memory and to respond to command data entries stored therein by transferring corresponding speech data segments from the speech data segment memory to the voice synthesizer; data conveyance means, connecting the computer to the command memory and the speech data segment memory, for transferring the command data entries supplied by the computer into the command memory and for transferring the speech data segments supplied by the computer into the speech data segment memory; and an enable signal line connecting the computer to the speech processor and arranged to initiate the operation of the processor control programs and logic when the enable signal line is enabled by the computer; the programmable computer including speech control programs controlling the operation of the computer including data conveyance command sequences that cause the computer to supply command data entries to the data conveyance means and speech processor enabling command sequences that cause computer to energize the enable signal line.

  1. Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

    SciTech Connect

    Lee, Youngmin; Lee, Sejoon Im, Hyunsik; Hiramoto, Toshiro

    2015-02-14

    We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

  2. Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

    NASA Technical Reports Server (NTRS)

    Straka, Bartholomew

    2013-01-01

    Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

  3. Quantum Logics of Idempotents of Unital Rings

    NASA Astrophysics Data System (ADS)

    Bikchentaev, Airat; Navara, Mirko; Yakushev, Rinat

    2015-06-01

    We introduce some new examples of quantum logics of idempotents in a ring. We continue the study of symmetric logics, i.e., collections of subsets generalizing Boolean algebras and closed under the symmetric difference.

  4. An autonomous molecular computer for logical control of gene expression

    NASA Astrophysics Data System (ADS)

    Benenson, Yaakov; Gil, Binyamin; Ben-Dor, Uri; Adar, Rivka; Shapiro, Ehud

    2004-05-01

    Early biomolecular computer research focused on laboratory-scale, human-operated computers for complex computational problems. Recently, simple molecular-scale autonomous programmable computers were demonstrated allowing both input and output information to be in molecular form. Such computers, using biological molecules as input data and biologically active molecules as outputs, could produce a system for `logical' control of biological processes. Here we describe an autonomous biomolecular computer that, at least in vitro, logically analyses the levels of messenger RNA species, and in response produces a molecule capable of affecting levels of gene expression. The computer operates at a concentration of close to a trillion computers per microlitre and consists of three programmable modules: a computation module, that is, a stochastic molecular automaton; an input module, by which specific mRNA levels or point mutations regulate software molecule concentrations, and hence automaton transition probabilities; and an output module, capable of controlled release of a short single-stranded DNA molecule. This approach might be applied in vivo to biochemical sensing, genetic engineering and even medical diagnosis and treatment. As a proof of principle we programmed the computer to identify and analyse mRNA of disease-related genes associated with models of small-cell lung cancer and prostate cancer, and to produce a single-stranded DNA molecule modelled after an anticancer drug.

  5. Spintronic logic design methodology based on spin Hall effect-driven magnetic tunnel junctions

    NASA Astrophysics Data System (ADS)

    Kang, Wang; Wang, Zhaohao; Zhang, Youguang; Klein, Jacques-Olivier; Lv, Weifeng; Zhao, Weisheng

    2016-02-01

    Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau-Lifshitz-Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing.

  6. Computerized logic design of digital circuits

    NASA Technical Reports Server (NTRS)

    Sussow, S.; Oglesby, R.

    1973-01-01

    This manual presents a computer program that performs all the work required for the logic design of digital counters or sequential circuits and the simplification of Boolean logic expressions. The program provides both the experienced and inexperienced logic designer with a comprehensive logic design capability. The manual contains Boolean simplification and sequential design theory, detailed instructions for use of the program, a large number of illustrative design examples, and complete program documentation.

  7. Design of polarization encoded all-optical 4-valued MAX logic gate and its applications

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay; Nath Roy, Jitendra

    2013-07-01

    Quaternary maximum (QMAX) gate is one type of multi-valued logic gate. An all-optical scheme of polarization encoded quaternary (4-valued) MAX logic gate with the help of Terahertz Optical Asymmetric Demultiplexer (TOAD) based fiber interferometric switch is proposed and described. For the quaternary information processing in optics, the quaternary number (0, 1, 2, 3) can be represented by four discrete polarized states of light. Numerical simulation result confirming the described methods is given in this paper. Some applications of MAX gate in logical operation and memory device are also given.

  8. Optical NOR logic gate design on square lattice photonic crystal platform

    NASA Astrophysics Data System (ADS)

    D'souza, Nirmala Maria; Mathew, Vincent

    2016-05-01

    We numerically demonstrate a new configuration of all-optical NOR logic gate with square lattice photonic crystal (PhC) waveguide using finite difference time domain (FDTD) method. The logic operations are based on interference effect of optical waves. We have determined the operating frequency range by calculating the band structure for a perfectly periodic PhC using plane wave expansion (PWE) method. Response time of this logic gate is 1.98 ps and it can be operated with speed about 513 GB/s. The proposed device consists of four linear waveguides and a square ring resonator waveguides on PhC platform.

  9. Circulating Packet Threshold Logic To Implement Msd Logic Modules

    NASA Astrophysics Data System (ADS)

    Flannery, David L.; Vail, L. Maugh; Gustafson, Steven C.

    1986-03-01

    Threshold logic element designs in circulating packet form are presented for the implementation of addition and subtraction using modified sign digit (MSD) arithmetic. This arithmetic is attractive for digital optical computing due to its inherent parallelism and pipelining characteristics, which capitalize on natural strengths of optics. To illustrate application of these concepts, a design for CORDIC rotation modules to accomplish the complex Givens rotations required for systolic array QU matrix factorization is presented. This design accomplishes QU factorization using only threshold logic elements and bit-shift operations in a systolic configuration. Although implementable in principle by either electronic or optical means, the design is amenable to optical implementation because it involves high levels of parallelism and interconnections.

  10. Piaget's Logic of Meanings: Still Relevant Today

    ERIC Educational Resources Information Center

    Wavering, Michael James

    2011-01-01

    In his last book, "Toward a Logic of Meanings" (Piaget & Garcia, 1991), Jean Piaget describes how thought can be categorized into a form of propositional logic, a logic of meanings. The intent of this article is to offer this analysis by Piaget as a means to understand the language and teaching of science. Using binary propositions, conjunctions,…

  11. Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

    2000-01-01

    The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

  12. Applications of Logic Coverage Criteria and Logic Mutation to Software Testing

    ERIC Educational Resources Information Center

    Kaminski, Garrett K.

    2011-01-01

    Logic is an important component of software. Thus, software logic testing has enjoyed significant research over a period of decades, with renewed interest in the last several years. One approach to detecting logic faults is to create and execute tests that satisfy logic coverage criteria. Another approach to detecting faults is to perform mutation…

  13. Logic implementations using a single nanoparticle-protein hybrid.

    PubMed

    Medalsy, Izhar; Klein, Michael; Heyman, Arnon; Shoseyov, Oded; Remacle, F; Levine, R D; Porath, Danny

    2010-06-01

    A Set-Reset machine is the simplest logic circuit with a built-in memory. Its output is a (nonlinear) function of the input and of the state stored in the machine's memory. Here, we report a nanoscale Set-Reset machine operating at room temperature that is based on a 5-nm silicon nanoparticle attached to the inner pore of a stable circular protein. The nanoparticle-protein hybrid can also function as a balanced ternary multiplier. Conductive atomic force microscopy is used to implement the logic input and output operations, and the processing of the logic Set and Reset operations relies on the finite capacitance of the nanoparticle provided by the good electrical isolation given by the protein, thus enabling stability of the logic device states. We show that the machine can be cycled, such that in every successive cycle, the previous state in the memory is retained as the present state. The energy cost of one cycle of computation is minimized to the cost of charging this state. PMID:20400968

  14. Dynamic Reconfiguration of Application Logic During Application Migration

    NASA Astrophysics Data System (ADS)

    Klus, Holger; Schindler, Björn; Rausch, Andreas

    During migration of an application from a source to a target device, its application logic often has to be adapted to the new situation. The new situation can for instance be characterized by different hardware resources or a different usage context . Therefore, the application logic has to be adapted automatically to the new context in order to provide the most suitable behaviour before and after migration. We consider application logic that consists of components which interact with each other through well-defined interfaces. In order to adapt the behaviour of the application logic, components can be added, removed or replaced. In this chapter we introduce a concept which enables the dynamic reconfiguration of component-based applications based on context information during the migration process. Our concept enables a technology independent specification of adaptation behaviour. Furthermore, we support the specification of an application without referencing application components directly. In that way it is possible to integrate new components into applications that were not known during application development time.

  15. Fuzzy Versions of Epistemic and Deontic Logic

    NASA Technical Reports Server (NTRS)

    Gounder, Ramasamy S.; Esterline, Albert C.

    1998-01-01

    Epistemic and deontic logics are modal logics, respectively, of knowledge and of the normative concepts of obligation, permission, and prohibition. Epistemic logic is useful in formalizing systems of communicating processes and knowledge and belief in AI (Artificial Intelligence). Deontic logic is useful in computer science wherever we must distinguish between actual and ideal behavior, as in fault tolerance and database integrity constraints. We here discuss fuzzy versions of these logics. In the crisp versions, various axioms correspond to various properties of the structures used in defining the semantics of the logics. Thus, any axiomatic theory will be characterized not only by its axioms but also by the set of properties holding of the corresponding semantic structures. Fuzzy logic does not proceed with axiomatic systems, but fuzzy versions of the semantic properties exist and can be shown to correspond to some of the axioms for the crisp systems in special ways that support dependency networks among assertions in a modal domain. This in turn allows one to implement truth maintenance systems. For the technical development of epistemic logic, and for that of deontic logic. To our knowledge, we are the first to address fuzzy epistemic and fuzzy deontic logic explicitly and to consider the different systems and semantic properties available. We give the syntax and semantics of epistemic logic and discuss the correspondence between axioms of epistemic logic and properties of semantic structures. The same topics are covered for deontic logic. Fuzzy epistemic and fuzzy deontic logic discusses the relationship between axioms and semantic properties for these logics. Our results can be exploited in truth maintenance systems.

  16. Compact all-optical interferometric logic gates based on one-dimensional metal-insulator-metal structures

    NASA Astrophysics Data System (ADS)

    Bian, Yusheng; Gong, Qihuang

    2014-02-01

    The whole set of fundamental all-optical logic gates is realized theoretically using a multi-channel configuration based on one-dimensional (1D) metal-insulator-metal (MIM) structures by leveraging the linear interference between surface plasmon polariton modes. The working principle and conditions for different logic functions are analyzed and demonstrated numerically by means of the finite element method. In contrast to most of the previous studies that require more than one type of configuration to achieve different logic functions, a single geometry with fixed physical dimensions can realize all fundamental functions in our case studies. It is shown that by switching the optical signals to different input channels, the presented device can realize simple logic functions such as OR, AND and XOR. By adding signal in the control channel, more functions including NOT, XNOR, NAND and NOR can be implemented. For these considered logic functions, high intensity contrast ratios between Boolean logic states "1" and "0" can be achieved at the telecom wavelength. The presented all-optical logic device is simple, compact and efficient. Moreover, the proposed scheme can be applied to many other nano-photonic logic devices as well, thereby potentially offering useful guidelines for their designs and further applications in on-chip optical computing and optical interconnection networks.

  17. Control system devices : architectures and supply channels overview.

    SciTech Connect

    Trent, Jason; Atkins, William Dee; Schwartz, Moses Daniel; Mulder, John C.

    2010-08-01

    This report describes a research project to examine the hardware used in automated control systems like those that control the electric grid. This report provides an overview of the vendors, architectures, and supply channels for a number of control system devices. The research itself represents an attempt to probe more deeply into the area of programmable logic controllers (PLCs) - the specialized digital computers that control individual processes within supervisory control and data acquisition (SCADA) systems. The report (1) provides an overview of control system networks and PLC architecture, (2) furnishes profiles for the top eight vendors in the PLC industry, (3) discusses the communications protocols used in different industries, and (4) analyzes the hardware used in several PLC devices. As part of the project, several PLCs were disassembled to identify constituent components. That information will direct the next step of the research, which will greatly increase our understanding of PLC security in both the hardware and software areas. Such an understanding is vital for discerning the potential national security impact of security flaws in these devices, as well as for developing proactive countermeasures.

  18. An Embedded Reconfigurable Logic Module

    NASA Technical Reports Server (NTRS)

    Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

    2002-01-01

    A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

  19. Nanowire NMOS Logic Inverter Characterization.

    PubMed

    Hashim, Yasir

    2016-06-01

    This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly. PMID:27427653

  20. The Logic Behind Feynman's Paths

    NASA Astrophysics Data System (ADS)

    García Álvarez, Edgardo T.

    The classical notions of continuity and mechanical causality are left in order to reformulate the Quantum Theory starting from two principles: (I) the intrinsic randomness of quantum process at microphysical level, (II) the projective representations of symmetries of the system. The second principle determines the geometry and then a new logic for describing the history of events (Feynman's paths) that modifies the rules of classical probabilistic calculus. The notion of classical trajectory is replaced by a history of spontaneous, random and discontinuous events. So the theory is reduced to determining the probability distribution for such histories accordingly with the symmetries of the system. The representation of the logic in terms of amplitudes leads to Feynman rules and, alternatively, its representation in terms of projectors results in the Schwinger trace formula.

  1. All-optical symmetric ternary logic gate

    NASA Astrophysics Data System (ADS)

    Chattopadhyay, Tanay

    2010-09-01

    Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.

  2. Block QCA Fault-Tolerant Logic Gates

    NASA Technical Reports Server (NTRS)

    Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

    2003-01-01

    -based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

  3. Quantum dot ternary-valued full-adder: Logic synthesis by a multiobjective design optimization based on a genetic algorithm

    SciTech Connect

    Klymenko, M. V.; Remacle, F.

    2014-10-28

    A methodology is proposed for designing a low-energy consuming ternary-valued full adder based on a quantum dot (QD) electrostatically coupled with a single electron transistor operating as a charge sensor. The methodology is based on design optimization: the values of the physical parameters of the system required for implementing the logic operations are optimized using a multiobjective genetic algorithm. The searching space is determined by elements of the capacitance matrix describing the electrostatic couplings in the entire device. The objective functions are defined as the maximal absolute error over actual device logic outputs relative to the ideal truth tables for the sum and the carry-out in base 3. The logic units are implemented on the same device: a single dual-gate quantum dot and a charge sensor. Their physical parameters are optimized to compute either the sum or the carry out outputs and are compatible with current experimental capabilities. The outputs are encoded in the value of the electric current passing through the charge sensor, while the logic inputs are supplied by the voltage levels on the two gate electrodes attached to the QD. The complex logic ternary operations are directly implemented on an extremely simple device, characterized by small sizes and low-energy consumption compared to devices based on switching single-electron transistors. The design methodology is general and provides a rational approach for realizing non-switching logic operations on QD devices.

  4. Cosmic logic: a computational model

    NASA Astrophysics Data System (ADS)

    Vanchurin, Vitaly

    2016-02-01

    We initiate a formal study of logical inferences in context of the measure problem in cosmology or what we call cosmic logic. We describe a simple computational model of cosmic logic suitable for analysis of, for example, discretized cosmological systems. The construction is based on a particular model of computation, developed by Alan Turing, with cosmic observers (CO), cosmic measures (CM) and cosmic symmetries (CS) described by Turing machines. CO machines always start with a blank tape and CM machines take CO's Turing number (also known as description number or Gödel number) as input and output the corresponding probability. Similarly, CS machines take CO's Turing number as input, but output either one if the CO machines are in the same equivalence class or zero otherwise. We argue that CS machines are more fundamental than CM machines and, thus, should be used as building blocks in constructing CM machines. We prove the non-computability of a CS machine which discriminates between two classes of CO machines: mortal that halts in finite time and immortal that runs forever. In context of eternal inflation this result implies that it is impossible to construct CM machines to compute probabilities on the set of all CO machines using cut-off prescriptions. The cut-off measures can still be used if the set is reduced to include only machines which halt after a finite and predetermined number of steps.

  5. Programmed DNA Self-Assembly and Logic Circuits

    NASA Astrophysics Data System (ADS)

    Li, Wei

    DNA is a unique, highly programmable and addressable biomolecule. Due to its reliable and predictable base recognition behavior, uniform structural properties, and extraordinary stability, DNA molecules are desirable substrates for biological computation and nanotechnology. The field of DNA computation has gained considerable attention due to the possibility of exploiting the massive parallelism that is inherent in natural systems to solve computational problems. This dissertation focuses on building novel types of computational DNA systems based on both DNA reaction networks and DNA nanotechnology. A series of related research projects are presented here. First, a novel, three-input majority logic gate based on DNA strand displacement reactions was constructed. Here, the three inputs in the majority gate have equal priority, and the output will be true if any two of the inputs are true. We subsequently designed and realized a complex, 5-input majority logic gate. By controlling two of the five inputs, the complex gate is capable of realizing every combination of OR and AND gates of the other 3 inputs. Next, we constructed a half adder, which is a basic arithmetic unit, from DNA strand operated XOR and AND gates. The aim of these two projects was to develop novel types of DNA logic gates to enrich the DNA computation toolbox, and to examine plausible ways to implement large scale DNA logic circuits. The third project utilized a two dimensional DNA origami frame shaped structure with a hollow interior where DNA hybridization seeds were selectively positioned to control the assembly of small DNA tile building blocks. The small DNA tiles were directed to fill the hollow interior of the DNA origami frame, guided through sticky end interactions at prescribed positions. This research shed light on the fundamental behavior of DNA based self-assembling systems, and provided the information necessary to build programmed nanodisplays based on the self-assembly of DNA.

  6. Graphene-based aptamer logic gates and their application to multiplex detection.

    PubMed

    Wang, Li; Zhu, Jinbo; Han, Lei; Jin, Lihua; Zhu, Chengzhou; Wang, Erkang; Dong, Shaojun

    2012-08-28

    In this work, a GO/aptamer system was constructed to create multiplex logic operations and enable sensing of multiplex targets. 6-Carboxyfluorescein (FAM)-labeled adenosine triphosphate binding aptamer (ABA) and FAM-labeled thrombin binding aptamer (TBA) were first adsorbed onto graphene oxide (GO) to form a GO/aptamer complex, leading to the quenching of the fluorescence of FAM. We demonstrated that the unique GO/aptamer interaction and the specific aptamer-target recognition in the target/GO/aptamer system were programmable and could be utilized to regulate the fluorescence of FAM via OR and INHIBIT logic gates. The fluorescence changed according to different input combinations, and the integration of OR and INHIBIT logic gates provided an interesting approach for logic sensing applications where multiple target molecules were present. High-throughput fluorescence imagings that enabled the simultaneous processing of many samples by using the combinatorial logic gates were realized. The developed logic gates may find applications in further development of DNA circuits and advanced sensors for the identification of multiple targets in complex chemical environments. PMID:22823159

  7. GMAG Dissertation Award Talk: All Spin Logic -- Multimagnet Networks interacting via Spin currents

    NASA Astrophysics Data System (ADS)

    Srinivasan, Srikant

    2012-02-01

    Digital logic circuits have traditionally been based on storing information as charge on capacitors, and the stored information is transferred by controlling the flow of charge. However, electrons carry both charge and spin, the latter being responsible for magnetic phenomena. In the last few decades, there has been a significant improvement in our ability to control spins and their interaction with magnets. All Spin Logic (ASL) represents a new approach to information processing where spins and magnets now mirror the roles of charges and capacitors in conventional logic circuits. In this talk I first present a model [1] that couples non-collinear spin transport with magnet-dynamics to predict the switching behavior of the basic ASL device. This model is based on established physics and is benchmarked against available experimental data that demonstrate spin-torque switching in lateral structures. Next, the model is extended to simulate multi-magnet networks coupled with spin transport channels. The simulations suggest ASL devices have the essential characteristics for building logic circuits. In particular, (1) the example of an ASL ring oscillator [2, 3] is used to provide a clear signature of directed information transfer in cascaded ASL devices without the need for external control circuitry and (2) a simulated NAND [4] gate with fan-out of 2 suggests that ASL can implement universal logic and drive subsequent stages. Finally I will discuss how ASL based circuits could also have potential use in the design of neuromorphic circuits suitable for hybrid analog/digital information processing because of the natural mapping of ASL devices to neurons [4]. [4pt] [1] B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, ``Switching Energy-Delay of All-Spin Logic devices,'' Appl. Phys. Lett., 98, 123510 (2011).[0pt] [2] S. Srinivasan, A. Sarkar, B. Behin-Aein, and S. Datta, ``All Spin Logic Device with Inbuilt Non-reciprocity,'' IEEE Trans. Magn., 47, 10 (2011).[0pt] [3

  8. Nanomagnet logic: progress toward system-level integration

    NASA Astrophysics Data System (ADS)

    Niemier, M. T.; Bernstein, G. H.; Csaba, G.; Dingler, A.; Hu, X. S.; Kurtz, S.; Liu, S.; Nahas, J.; Porod, W.; Siddiq, M.; Varga, E.

    2011-12-01

    Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, ‘Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input-output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.’ This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain—using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

  9. Voltage-driven spintronic logic gates in graphene nanoribbons

    PubMed Central

    Zhang, WenXing

    2014-01-01

    Electronic devices lose efficacy due to quantum effect when the line-width of gate decreases to sub-10 nm. Spintronics overcome this bottleneck and logic gates are building blocks of integrated circuits. Thus, it is essential to control electronic transport of opposite spins for designing a spintronic logic gate, and spin-selective semiconductors are natural candidates such as zigzag graphene nanoribbons (ZGNR) whose edges are ferromagnetically ordered and antiferromagnetically coupled with each other. Moreover, it is necessary to sandwich ZGNR between two ferromagnetic electrodes for making a spintronic logic gate and also necessary to apply magnetic field to change the spin orientation for modulating the spin transport. By first principle calculations, we propose a method to manipulate the spin transport in graphene nanoribbons with electric field only, instead of magnetic field. We find that metal gates with specific bias nearby edges of ZGNR build up an in-plane inhomogeneous electric field which modulates the spin transport by localizing the spin density in device. The specific manipulation of spin transport we have proposed doesn't need spin-charge conversion for output and suggests a possible base for designing spintronic integrated circuit in atomic scale. PMID:25204808

  10. Electro-opto-mechanical cantilever-based logic gates

    NASA Astrophysics Data System (ADS)

    Rehder, G.; Alayo, M. I.; Medina, H. B.; Carreño, M. N. P.

    2007-01-01

    In this work we describe the fabrication and characterization of micro-opto-electro-mechanical AND, OR and XOR logic gates based in a combination of optical and micro-electro-mechanical devices. These structures consist of silicon oxynitride-based optical waveguides, through which a light beam of 633-nm can be conducted, and mobile thermo-electro actuated cantilevers, which form part of the waveguide and can work as ON-OFF switches for the laser. These switches are combined to form AND, OR and XOR gates, allowing the laser light to pass or blocking the laser light when activated electrically. The cantilevers are fabricated by freeing regions of the waveguide, which is done by front side micromachining the silicon wafer used as substrate. Also, they are actuated electrically through the heating of a metallic resistance positioned in the device, where the applied current heats the cantilevers and, due to the difference in thermal expansion coefficients of the constituent materials, it is possible to produce a controlled motion proportional to the heating current. Therefore, the switches can be electrically polarized in on/off cycles allowing or blocking the light through the waveguide, similar to logic "1's" and "0's". These switches are adequately arranged to produce an output that is similar to the conventional digital logic gates through electric control (input) of cantilever-based ON-OFF switches.

  11. Nanomagnet logic: progress toward system-level integration.

    PubMed

    Niemier, M T; Bernstein, G H; Csaba, G; Dingler, A; Hu, X S; Kurtz, S; Liu, S; Nahas, J; Porod, W; Siddiq, M; Varga, E

    2011-12-14

    Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work. PMID:22121192

  12. Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

    SciTech Connect

    Jinyuan Wu; Zonghan Shi; Irena Y Wang

    2003-11-07

    A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document.

  13. Space research programme

    NASA Astrophysics Data System (ADS)

    Magnusson, Per; Englund, Jan; Norberg, Olle

    2001-08-01

    A major highlight of the Swedish national programme was the launch of the Odin Orbital Observatory in February 2001. The atmospheric profiles measured by Odin will be calibrated with rocket and balloon validation flights during the second half of 2001. A continuation of the satellite programme after Odin depends on the outcome of an ongoing assessment and an additional budget. The future ESA microgravity programme will be of high importance for European and Swedish science and applications using weightless conditions, and for the utilisation of the International Space Station (ISS). It should also make sure that the European independent capability for launching efficient sounding rockets is preserved and developed.

  14. R-1 (C-620-A) and R-2 (C-620-B) air compressor control logic, computer software description. Revision 1

    SciTech Connect

    Walter, K.E.

    1995-06-08

    This document provides an updated computer software description for the software used on the FFTF R-1 (C-620-A) and R-2 (C-620-B) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started.

  15. Fuzzy logic controller versus classical logic controller for residential hybrid solar-wind-storage energy system

    NASA Astrophysics Data System (ADS)

    Derrouazin, A.; Aillerie, M.; Mekkakia-Maaza, N.; Charles, J. P.

    2016-07-01

    Several researches for management of diverse hybrid energy systems and many techniques have been proposed for robustness, savings and environmental purpose. In this work we aim to make a comparative study between two supervision and control techniques: fuzzy and classic logics to manage the hybrid energy system applied for typical housing fed by solar and wind power, with rack of batteries for storage. The system is assisted by the electric grid during energy drop moments. A hydrogen production device is integrated into the system to retrieve surplus energy production from renewable sources for the household purposes, intending the maximum exploitation of these sources over years. The models have been achieved and generated signals for electronic switches command of proposed both techniques are presented and discussed in this paper.

  16. SOTANCP3 Scientific Programme

    NASA Astrophysics Data System (ADS)

    2014-12-01

    The programme for the 3rd International Workshop on "State of the Art in Nuclear Cluster Physics" which was held at the KGU (Kanto Gakuin University) Kannai Media Center (8th floor of Yokohoma Media Business Center (YMBC))

  17. WORLD WATER ASSESSMENT PROGRAMME

    EPA Science Inventory

    The overall objective of the World Water Assessment Programme is to support the building of global security - food, environment, economic, social and political security -- through an integrated comprehensive freshwater assessment.The specific objectives within the assessment pr...

  18. Integrated logic circuits using single-atom transistors

    PubMed Central

    Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

    2011-01-01

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

  19. Unit testing-based approach for reconfigurable logic controllers verification

    NASA Astrophysics Data System (ADS)

    Doligalski, Michał; Tkacz, Jacek; Bukowiec, Arkadiusz; Gratkowski, Tomasz

    2015-09-01

    The paper presents unit testing-based approach to FPGA design in-circuit verification. Presented methodology is dedicated to modular reconfigurable logic controllers, but other ip-cores and systems can be verified as well. The speed and reproducibility of tests is key for rapid system prototyping, where the quality and reliability of the system is significance. Typically FPGA are programmed by means single (full) bitstream. Specific devices are able to be reconfigured partially. Usually the partial reconfiguration is a part of the design functionality. It enables the minimization of used resources or provides specific functionality like system adaptation. The paper presents the use of the partial reconfiguration as a toll for the designer. The unit testing approach well know form software engineering was adopted to modular logic controllers development. The simulation process results waveform files, the waveform can be used for synthesizable test bench generation.

  20. Integrated logic circuits using single-atom transistors.

    PubMed

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

  1. PLATO--AN AUTOMATED TEACHING DEVICE.

    ERIC Educational Resources Information Center

    BITZER, D.; AND OTHERS

    PLATO (PROGRAMED LOGIC FOR AUTOMATIC TEACHING OPERATION) IS A DEVICE FOR TEACHING A NUMBER OF STUDENTS INDIVIDUALLY BY MEANS OF A SINGLE, CENTRAL PURPOSE, DIGITAL COMPUTER. THE GENERAL ORGANIZATION OF EQUIPMENT CONSISTS OF A KEYSET FOR STUDENT RESPONSES, THE COMPUTER, STORAGE DEVICE (ELECTRIC BLACKBOARD), SLIDE SELECTOR (ELECTRICAL BOOK), AND TV…

  2. On schemes of combinatorial transcription logic

    NASA Astrophysics Data System (ADS)

    Buchler, Nicolas E.; Gerland, Ulrich; Hwa, Terence

    2003-04-01

    Cells receive a wide variety of cellular and environmental signals, which are often processed combinatorially to generate specific genetic responses. Here we explore theoretically the potentials and limitations of combinatorial signal integration at the level of cis-regulatory transcription control. Our analysis suggests that many complex transcription-control functions of the type encountered in higher eukaryotes are already implementable within the much simpler bacterial transcription system. Using a quantitative model of bacterial transcription and invoking only specific protein-DNA interaction and weak glue-like interaction between regulatory proteins, we show explicit schemes to implement regulatory logic functions of increasing complexity by appropriately selecting the strengths and arranging the relative positions of the relevant protein-binding DNA sequences in the cis-regulatory region. The architectures that emerge are naturally modular and evolvable. Our results suggest that the transcription regulatory apparatus is a "programmable" computing machine, belonging formally to the class of Boltzmann machines. Crucial to our results is the ability to regulate gene expression at a distance. In bacteria, this can be achieved for isolated genes via DNA looping controlled by the dimerization of DNA-bound proteins. However, if adopted extensively in the genome, long-distance interaction can cause unintentional intergenic cross talk, a detrimental side effect difficult to overcome by the known bacterial transcription-regulation systems. This may be a key factor limiting the genome-wide adoption of complex transcription control in bacteria. Implications of our findings for combinatorial transcription control in eukaryotes are discussed. Abbreviations: TF, transcription factor RNAP, RNA polymerase DNF, disjunctive normal form CNF, conjunctive normal form

  3. Nanoscale Optoelectronic Photosynthetic Devices

    NASA Astrophysics Data System (ADS)

    Greenbaum, Elias; Lee, Ida; Guillorn, Michael; Lee, James W.; Simpson, Michael L.

    2001-03-01

    This presentation provides an overview and recent progress in the Oak Ridge National Laboratory research program in molecular electronics and green plant photosynthesis. The photosynthetic reaction center is a nanoscale molecular diode and photovoltaic device. The key thrust of our research program is the construction of molecular electronic devices from these nanoscale structures. Progress in this multidisciplinary research program has been demonstrated by direct electrical contact of emergent electrons with the Photosystem I (PS I) reaction center by nanoparticle precipitation. Demonstration of stable diode properties of isolated reaction centers combined with the ability to orient PS I by self-assembly on a planar surface, makes this structure a good building block for 2-D and potentially 3-D devices. Metallization of isolated PS I does not alter their fundamental photophysical properties and they can be bonded to metal surfaces. We report here the first measurement of photovoltage from single PS I reaction centers. Working at the Cornell University National Nanofabrication Facility, we have constructed sets of dissimilar metal electrodes separated by distances as small as 6 nm. We plan to use these structures to make electrical contact to both ends of oriented PSI reaction centers and thereby realize biomolecular logic circuits. Potential applications of PSI reaction centers for optoelectronic applications as well as molecular logic device construction will be discussed.

  4. Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

    NASA Technical Reports Server (NTRS)

    Le, Martin; Zheng, Xin; Katanyoutant, Sunant

    2008-01-01

    Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state

  5. Color-to-speech sensory substitution device for the visually impaired

    NASA Astrophysics Data System (ADS)

    McMorrow, Gabriel; Wang, Xiaojun; Whelan, Paul F.

    1997-09-01

    A hardware device is presented that converts color to speech for use by the blind and visually impaired. The use of audio tones for transferring knowledge of colors identified to individuals was investigated but was discarded in favor of the use of direct speech. A unique color-clustering algorithm was implemented using a hardware description language (VHDL), which in-turn was used to program an Altera Corporation's programmable logic device (PLD). The PLD maps all possible incoming colors into one of 24 color names, and outputs an address to a speech device, which in-turn plays back one of 24 voice recorded color names. To the author's knowledge, there are only two such color to speech systems available on the market. However, both are designed to operate at a distance of less than an inch from the surface whose color is to be checked. The device presented here uses original front-end optics to increase the range of operation from less than an inch to sixteen feet and greater. Because of the increased range of operation, the device can not only be used for color identification, but also as a navigation aid.

  6. Optical interferometric logic gates based on metal slot waveguide network realizing whole fundamental logic operations.

    PubMed

    Pan, Deng; Wei, Hong; Xu, Hongxing

    2013-04-22

    Optical interferometric logic gates in metal slot waveguide network are designed and investigated by electromagnetic simulations. The designed logic gates can realize all fundamental logic operations. A single Y-shaped junction can work as logic gate for four logic functions: AND, NOT, OR and XOR. By cascading two Y-shaped junctions, NAND, NOR and XNOR can be realized. The working principle is analyzed in detail. In the simulations, these gates show large intensity contrast for the Boolean logic states of the output. These results can be useful for future integrated optical computing. PMID:23609666

  7. Logical elements in living cells.

    PubMed

    Kremen, A

    1984-11-01

    Recognition processes with enhanced accuracy (as performed by structures like enzymes or ribosomes) are investigated using elementary ideas of statistical mechanics and related concepts of thermodynamics. The analysis starts from a formal definition of recognition and provides a correspondence with appropriate physical properties of the macromolecular logical elements. Transitions of the recognizing system between different modifications are a necessary feature of a more exacting recognition process. Rearrangement steps provide the process with higher accuracy by performing two physical operations: (1) rearranging the phase space of the system so that the "correct" states be better separated from the "wrong" states and the probability of occupation of the "correct" states be enhanced, (2) directing the process toward the more favourable modifications thus formed. Both operations are related to changes in the physical properties of the recognizing system. These changes can be expressed as differences of macromolecular Gibbs energy levels; if ligand binding or release participate in a step, directivity of the step depends also on the actual chemical potentials of the ligands in solution. The two operations just mentioned resemble two basic operations known to be necessary in electronic digital networks: directivity of control and signal standardization. An analysis of the entire reaction catalysed by a macromolecular logical element takes into account the requirements imposed by the logical functions as well as the need that the chemical potential of the product be not restricted to very low values. To satisfy these conditions, the reaction must be supported by a so-called non-specific reaction, usually implemented by the cleavage reaction of a nucleoside triphosphate. PMID:6513567

  8. A programmable image compression system

    NASA Technical Reports Server (NTRS)

    Farrelle, Paul M.

    1989-01-01

    A programmable image compression system which has the necessary flexibility to address diverse imaging needs is described. It can compress and expand single frame video images (monochrome or color) as well as documents and graphics (black and white or color) for archival or transmission applications. Through software control, the compression mode can be set for lossless or controlled quality coding; the image size and bit depth can be varied; and the image source and destination devices can be readily changed. Despite the large combination of image data types, image sources, and algorithms, the system provides a simple consistent interface to the programmer. This system (OPTIPAC) is based on the TITMS320C25 digital signal processing (DSP) chip and has been implemented as a co-processor board for an IBM PC-AT compatible computer. The underlying philosophy can readily be applied to different hardware platforms. By using multiple DSP chips or incorporating algorithm specific chips, the compression and expansion times can be significantly reduced to meet performance requirements.

  9. An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

    ERIC Educational Resources Information Center

    Foster, D. L.

    2012-01-01

    For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

  10. Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity

    NASA Astrophysics Data System (ADS)

    Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

    2015-05-01

    Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity).

  11. Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity.

    PubMed

    Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

    2015-01-01

    Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity). PMID:25976626

  12. An error-resilient non-volatile magneto-elastic universal logic gate with ultralow energy-delay product

    PubMed Central

    Biswas, Ayan K.; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2014-01-01

    A long-standing goal of computer technology is to process and store digital information with the same device in order to implement new architectures. One way to accomplish this is to use nanomagnetic logic gates that can perform Boolean operations and then store the output data in the magnetization states of nanomagnets, thereby doubling as both logic and memory. Unfortunately, many of these nanomagnetic devices do not possess the seven essential characteristics of a Boolean logic gate : concatenability, non-linearity, isolation between input and output, gain, universal logic implementation, scalability and error resilience. More importantly, their energy-delay products and error rates tend to vastly exceed that of conventional transistor-based logic gates, which is unacceptable. Here, we propose a non-volatile voltage-controlled nanomagnetic logic gate that possesses all the necessary characteristics of a logic gate and whose energy-delay product is two orders of magnitude less than that of other nanomagnetic (non-volatile) logic gates. The error rate is also superior. PMID:25532757

  13. An error-resilient non-volatile magneto-elastic universal logic gate with ultralow energy-delay product.

    PubMed

    Biswas, Ayan K; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2014-01-01

    A long-standing goal of computer technology is to process and store digital information with the same device in order to implement new architectures. One way to accomplish this is to use nanomagnetic logic gates that can perform Boolean operations and then store the output data in the magnetization states of nanomagnets, thereby doubling as both logic and memory. Unfortunately, many of these nanomagnetic devices do not possess the seven essential characteristics of a Boolean logic gate : concatenability, non-linearity, isolation between input and output, gain, universal logic implementation, scalability and error resilience. More importantly, their energy-delay products and error rates tend to vastly exceed that of conventional transistor-based logic gates, which is unacceptable. Here, we propose a non-volatile voltage-controlled nanomagnetic logic gate that possesses all the necessary characteristics of a logic gate and whose energy-delay product is two orders of magnitude less than that of other nanomagnetic (non-volatile) logic gates. The error rate is also superior. PMID:25532757

  14. An error-resilient non-volatile magneto-elastic universal logic gate with ultralow energy-delay product

    NASA Astrophysics Data System (ADS)

    Biswas, Ayan K.; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2014-12-01

    A long-standing goal of computer technology is to process and store digital information with the same device in order to implement new architectures. One way to accomplish this is to use nanomagnetic logic gates that can perform Boolean operations and then store the output data in the magnetization states of nanomagnets, thereby doubling as both logic and memory. Unfortunately, many of these nanomagnetic devices do not possess the seven essential characteristics of a Boolean logic gate : concatenability, non-linearity, isolation between input and output, gain, universal logic implementation, scalability and error resilience. More importantly, their energy-delay products and error rates tend to vastly exceed that of conventional transistor-based logic gates, which is unacceptable. Here, we propose a non-volatile voltage-controlled nanomagnetic logic gate that possesses all the necessary characteristics of a logic gate and whose energy-delay product is two orders of magnitude less than that of other nanomagnetic (non-volatile) logic gates. The error rate is also superior.

  15. Electronic logic for enhanced switch reliability

    DOEpatents

    Cooper, J.A.

    1984-01-20

    A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and fail-safe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.

  16. Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

    NASA Astrophysics Data System (ADS)

    Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

    2016-06-01

    Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis

  17. The performativity of "media logic" in the mass mediation of science.

    PubMed

    Plesner, Ursula

    2012-08-01

    Studies of the use of research-based expertise in the mass media often demonstrate how experts are used to confirm journalists' angles on particular stories or how research-based knowledge claims are twisted. Both among practitioners and science communication scholars, such practices are often explained with reference to a pervasive "media logic." "Media logic" is constructed as governing choices and interactions of researchers and journalists. This article critically examines the extensive use of the term "media logic" to explain choices, changes or content in media production, and presents Actor-Network-Theory as an approach that invites us to ask what takes place in practice without resorting to such generalizing explanatory devices. The article argues that a quick jump to "media logic" as an explanation may imply that we forget its contingency and ignore what actually takes place in journalists' and researchers' negotiations about texts and facts in the mass mediation of science. PMID:23832154

  18. Polarization-based all-optical logic operations in volume holographic photopolymer

    NASA Astrophysics Data System (ADS)

    Li, Chengmingyue; Cao, Liangcai; Li, Jingming; Wang, Zheng; Jin, Guofan

    2014-11-01

    Polarization-based all-optical logic operations were realized with dual-channel polarization holographic recording system. The polarization property of 9, 10-phenanthrenequinone-doped poly-methyl methacrylate (PQ/PMMA) photopolymer is investigated experimentally. To accurately represent the optical operations, the diffraction efficiency of parallel and orthogonal polarization recording in PQ/PMMA with the thickness of 1 mm are characterized for holographic recording and reconstruction process. A dual-channel polarization holographic recording system is set up for simultaneously recording two input pages. By changing the polarization state of the diffraction beam, all-optical logic OR and NAND operations are realized in the volume holograms. The polarization-based all-optical logic operations in the volume holographic photopolymer may pave a way for practical all-optical logic devices with high speed and large information capacity.

  19. Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

    NASA Astrophysics Data System (ADS)

    Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

    2014-02-01

    Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

  20. Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

    SciTech Connect

    Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

    2014-02-12

    Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.