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Sample records for radhard soi technology

  1. Study of proton radiation effects on analog IC designed for high energy physics in a BICMOS-JFET radhard SOI technology

    SciTech Connect

    Blanquart, L.; Delpierre, P.; Habrard, M.C.

    1994-12-01

    The authors present experimental results from a fast charge amplifier and a wideband analog buffer processed in the DMILL BiCMOS-JFET radhard SOI technology and irradiated up to 4.5 {times} 10{sup 14} protons/cm{sup 2}. In parallel, they have irradiated elementary transistors. These components were biased and electrical measurements were done 30 min after beam stop. By evaluating variations of main SPICE parameters, i.e., threshold voltage shift for CMOS and current gain variation for bipolar transistors, they have simulated the wideband analog buffer at different doses. These SPICE simulations are in good agreement with measured circuit degradations. The behavior of the charge amplifier is consistent with extraction of transconductance and pinch-off voltage shift of the PJFET.

  2. Advanced monolithic pixel sensors using SOI technology

    NASA Astrophysics Data System (ADS)

    Miyoshi, Toshinobu; Arai, Yasuo; Asano, Mari; Fujita, Yowichi; Hamasaki, Ryutaro; Hara, Kazuhiko; Honda, Shunsuke; Ikegami, Yoichi; Kurachi, Ikuo; Mitsui, Shingo; Nishimura, Ryutaro; Tauchi, Kazuya; Tobita, Naoshi; Tsuboyama, Toru; Yamada, Miho

    2016-07-01

    We are developing advanced pixel sensors using silicon-on-insulator (SOI) technology. A SOI wafer is used; top silicon is used for electric circuit and bottom silicon is used as a sensor. Target applications are high-energy physics, X-ray astronomy, material science, non-destructive inspection, medical application and so on. We have developed two integration-type pixel sensors, FPIXb and INTPIX7. These sensors were processed on single SOI wafers with various substrates in n- or p-type and double SOI wafers. The development status of double SOI sensors and some up-to-date test results of n-type and p-type SOI sensors are shown.

  3. Analysis of the breakdown voltage in SOI and SOS technologies

    NASA Astrophysics Data System (ADS)

    Roig, J.; Vellvehi, M.; Flores, D.; Rebollo, J.; Millan, J.; Krishnan, S.; De Souza, M. M.; Sankara Narayanan, E. M.

    2002-02-01

    The aim of the paper is to analyse the breakdown voltage performance of lateral power devices in silicon on insulator (SOI) technologies. Both silicon on oxide (termed SOI as per the convention) and silicon on sapphire (SOS) technologies have been considered. Detailed numerical modelling together with analytical evaluation has been carried out on lateral devices employing uniformly doped and variation in lateral doping drift regions. The results indicate that existing theories to predict breakdown voltage are valid only in the case of ultrathin insulator layers and fail when ultrathick layers are considered. Predicted results for devices with ultrathick dielectric layers, as it is the case in SOS technology, are presented. Moreover, the breakdown voltage sensitivity with respect to the SOI layer and dielectric thickness is also analysed.

  4. Measurement results of DIPIX pixel sensor developed in SOI technology

    NASA Astrophysics Data System (ADS)

    Ahmed, Mohammed Imran; Arai, Yasuo; Idzik, Marek; Kapusta, Piotr; Miyoshi, Toshinobu; Turala, Michal

    2013-08-01

    The development of integration type pixel detectors presents interest for physics communities because it brings optimization of design, simplicity of production-which means smaller cost, and reduction of detector material budget. During the last decade a lot of research and development activities took place in the field of CMOS Silicon-On-Insulator (SOI) technology resulting in improvement in wafer size, wafer resistivity and MIM capacitance. Several ideas have been tested successfully and are gradually entering into the application phase. Some of the novel concepts exploring SOI technology are pursued at KEK; several prototypes of dual mode integration type pixel (DIPIX) have been recently produced and described. This report presents initial test results of some of the prototypes including tests obtained with the infrared laser beams and Americium (Am-241) source. The Equivalent Noise Charge (ENC) of 86 e - has been measured. The measured performance demonstrates that SOI technology is a feasible choice for future applications.

  5. A Wide Range Temperature Sensor Using SOI Technology

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Elbuluk, Malik E.; Hammoud, Ahmad

    2009-01-01

    Silicon-on-insulator (SOI) technology is becoming widely used in integrated circuit chips for its advantages over the conventional silicon counterpart. The decrease in leakage current combined with lower power consumption allows electronics to operate in a broader temperature range. This paper describes the performance of an SOIbased temperature sensor under extreme temperatures and thermal cycling. The sensor comprised of a temperature-to-frequency relaxation oscillator circuit utilizing an SOI precision timer chip. The circuit was evaluated under extreme temperature exposure and thermal cycling between -190 C and +210 C. The results indicate that the sensor performed well over the entire test temperature range and it was able to re-start at extreme temperatures.

  6. Total-dose characterization of CMOS/SOI-ZMR technology

    SciTech Connect

    Coumar, O.; Gaillard, R. )

    1992-06-01

    In this paper the authors present the total dose radiation characterization of an unhardened SOI/ZMR technology of CNET/CNS (Centre National d'Etudes des Telecommunications - France). Various bias conditions are applied on front gate oxide and buried oxide during gamma irradiation in order to define the worst and best case configurations for different devices: transistors, capacitors and ring oscillator. The authors compare the radiation responses of transistors with different structures to allow clear separation of device conduction on top channel, back channel and edge channel along the sidewalls of the island. A good correlation is observed between n-substrate capacitor and p-channel transistors irradiated at {minus}5V back-gate bias. Radiation induced kink effects are observed on PMOS transistors for a positive back gate bias (+5V) during irradiation.

  7. Mongoose: Creation of a Rad-Hard MIPS R3000

    NASA Technical Reports Server (NTRS)

    Lincoln, Dan; Smith, Brian

    1993-01-01

    This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

  8. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

    NASA Astrophysics Data System (ADS)

    Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

    2016-01-01

    We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

  9. Smart-Cut ® technology: from 300 mm ultrathin SOI production to advanced engineered substrates

    NASA Astrophysics Data System (ADS)

    Maleville, Christophe; Mazuré, Carlos

    2004-06-01

    The Smart-Cut ® process, based on hydrogen implantation and wafer bonding, is a generic thin layer process transfer. Unibond ® SOI wafers are today in volume production, showing that splitting and bonding steps can be controlled, with high yields. Taking advantage of standard equipments flexibility, the process has been successfully scaled up to 300 mm. Most advanced 200 mm processes were successfully transferred to 300 mm, with wafers showing uniformity and defectivity results compatible with industry requirements for fully depleted device applications. The number of wafer solutions offered by the Smart-Cut ® technology is already much greater than just SOI. Strained silicon on insulator, silicon on quartz (SOQ), single crystal silicon layer on plastic supports, silicon carbide on insulator, germanium on insulator, multilayer SOI structures are just few examples of the potential of Smart Cut ® to engineer and design new substrates to answer the demands of the industry. A review of the progress achieved is given.

  10. Special Issue: Planar Fully-Depleted SOI technology

    NASA Astrophysics Data System (ADS)

    Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

    2016-03-01

    We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

  11. Nonvolatile Rad-Hard Holographic Memory

    NASA Technical Reports Server (NTRS)

    Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

    2001-01-01

    We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

  12. Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

    NASA Technical Reports Server (NTRS)

    Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

    2013-01-01

    This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

  13. Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

    NASA Technical Reports Server (NTRS)

    DeGregorio, Kelly; Wilson, Dale G.

    2009-01-01

    Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand

  14. Low thermal budget for Si and SiGe surface preparation for FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Labrot, M.; Cheynis, F.; Barge, D.; Müller, P.; Juhel, M.

    2016-05-01

    Ultra thin Silicon films of Silicon-on-Insulator technology are metastable and thus cannot be submitted to high temperature treatments that may roughen or disrupt the film during the set of technological steps required for device fabrication. This paper concerns the development of an efficient low temperature cleaning process of Si and SiGe surfaces that enables a subsequent good-quality epitaxy of raised source and drain. For this purpose wet-clean, plasma-clean and several combinations of both are used. We thus propose two effective surface cleaning processes with low thermal budget optimized for FD-SOI technology.

  15. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  16. High total dose effects on CMOS/SOI technology

    SciTech Connect

    Flament, O.; Dupont-Nivet, E.; Leray, J.L.; Pere, J.F.; Delagnes, E. ); Auberton-Herve, A.J.; Giffard, B. ); Borel, G.; Ouisse, T. )

    1992-06-01

    This paper reports that, CMOS silicon on insulator technology has shown its ability to process hardened components which remain functional after irradiation with a total dose of several tens of Megarads. New tests on elementary transistors and 29101 microprocessor have been made at doses up to 100 Mrad (SiO{sub 2}) and above. Results of irradiation at these total doses are presented for different biases, together with the post-irradiation behavior of the components. All the observations show that new parameters must be taken into account for hardness insurance at a high level of total dose.

  17. 15158A SP6T RF switch based on IBM SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhiqun, Cheng; Guoguo, Yan; Wayne, Ni; Dandan, Zhu; Hannah, Ni; Jin, Li; Shuai, Chen; Guohua, Liu

    2016-05-01

    This paper presents the design of single-pole six-throw (SP6T) RF switch with IBM 0.18 μm SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is (+2.46 V, 0, ‑2.46 V) in the frequency from 0.1 to 2.7 GHz. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001).

  18. Cost-effective mask-sharing technology for SOI LIGBT and PLDMOS

    NASA Astrophysics Data System (ADS)

    Huang, Yong; Qiao, Ming; Zhou, Xin; Liang, Tao; Li, Yang; Li, Zhaoji; Zhang, Bo

    2016-04-01

    Cost-effective mask-sharing technology for the 200 V silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) and p-channel lateral double-diffused MOS (PLDMOS) are proposed in this paper. N-well and P-body implantations are shared as an N-buffer implantation of the LIGBT and P-buffer implantation of the PLDMOS, respectively, which reduces two masks compared with the conventional process. The structure and process parameters for LIGBT and PLDMOS with the new process are optimized by simulation to achieve good performance. The experimental results indicate that the LIGBT and PLDMOS using the new process maintain the same performance compared to the conventional devices.

  19. Evaluation of soft error rates using nuclear probes in bulk and SOI SRAMs with a technology node of 90 nm

    NASA Astrophysics Data System (ADS)

    Abo, Satoshi; Masuda, Naoyuki; Wakaya, Fujio; Onoda, Shinobu; Hirao, Toshio; Ohshima, Takeshi; Iwamatsu, Toshiaki; Takai, Mikio

    2010-06-01

    The difference of soft error rates (SERs) in conventional bulk Si and silicon-on-insulator (SOI) static random access memories (SRAMs) with a technology node of 90 nm has been investigated by helium ion probes with energies ranging from 0.8 to 6.0 MeV and a dose of 75 ions/μm 2. The SERs in the SOI SRAM were also investigated by oxygen ion probes with energies ranging from 9.0 to 18.0 MeV and doses of 0.14-0.76 ions/μm 2. The soft error in the bulk and SOI SRAMs occurred by helium ion irradiation with energies at and above 1.95 and 2.10 MeV, respectively. The SER in the bulk SRAM saturated with ion energies at and above 2.5 MeV. The SER in the SOI SRAM became the highest by helium ion irradiation at 2.5 MeV and drastically decreased with increasing the ion energies above 2.5 MeV, in which helium ions at this energy range generated the maximum amount of excess charge carriers in a SOI body. The soft errors occurred by helium ions were induced by a floating body effect due to generated excess charge carriers in the channel regions. The soft error occurred by oxygen ion irradiation with energies at and above 10.5 MeV in the SOI SRAM. The SER in the SOI SRAM gradually increased with energies from 10.5 to 13.5 MeV and saturated at 18 MeV, in which the amount of charge carriers induced by oxygen ions in this energy range gradually increased. The computer calculation indicated that the oxygen ions with energies above 13.0 MeV generated more excess charge carriers than the critical charge of the 90 nm node SOI SRAM with the designed over-layer thickness. The soft errors, occurred by oxygen ions with energies at and below 12.5 MeV, were induced by a floating body effect due to the generated excess charge carriers in the channel regions and those with energies at and above 13.0 MeV were induced by both the floating body effect and generated excess carriers. The difference of the threshold energy of the oxygen ions between the experiment and the computer calculation might

  20. SOI monolithic pixel detector

    NASA Astrophysics Data System (ADS)

    Miyoshi, T.; Ahmed, M. I.; Arai, Y.; Fujita, Y.; Ikemoto, Y.; Takeda, A.; Tauchi, K.

    2014-05-01

    We are developing monolithic pixel detector using fully-depleted (FD) silicon-on-insulator (SOI) pixel process technology. The SOI substrate is high resistivity silicon with p-n junctions and another layer is a low resistivity silicon for SOI-CMOS circuitry. Tungsten vias are used for the connection between two silicons. Since flip-chip bump bonding process is not used, high sensor gain in a small pixel area can be obtained. In 2010 and 2011, high-resolution integration-type SOI pixel sensors, DIPIX and INTPIX5, have been developed. The characterizations by evaluating pixel-to-pixel crosstalk, quantum efficiency (QE), dark noise, and energy resolution were done. A phase-contrast imaging was demonstrated using the INTPIX5 pixel sensor for an X-ray application. The current issues and future prospect are also discussed.

  1. The development of x-ray bolometers based on SOI technology for astronomy

    NASA Astrophysics Data System (ADS)

    Aliane, A.; De Moro, F.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Szeflinski, V.; Gasse, A.; Arnaud, M.; de la Broïse, X.; Navick, X.-F.; Routin, J.; Mathieu, L.; Cigna, J.-C.; Berger, F.; Ribot, H.; Gobil, Y.

    2008-07-01

    Several successful development programs have been conducted on Infra-Red bolometer arrays at the French Atomic Energy Commission (CEA-LETI Grenoble), in collaboration with the CEA-Sap (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors. These micro-calorimeter arrays will be used for future space missions. A 8×8 array prototype consisting of a grid of 64 suspended pixels on SOI (Silicon On Insulator) has been created. Each pixel of this array detector is made of a tantalum (Ta) absorber and is bonded, by means of an indium bump hybridization process, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process step. The fabrication process of our detector involves a combination of standard silicon technologies such as Si bulk micromachining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on the different building elements and processes that are required to create a detector array up to 32*32 pixels in size.

  2. Study of millisecond laser annealing on ion implanted soi and application to scaled finfet technology

    NASA Astrophysics Data System (ADS)

    Michalak, Tyler J.

    The fabrication of metal-oxide-semiconductor field effect transistors (MOSFET) requires the engineering of low resistance, low leakage, and extremely precise p-n junctions. The introduction of finFET technology has introduced new challenges for traditional ion implantation and annealing techniques in junction design as the fin widths continue to decrease for improved short channel control. This work investigates the use of millisecond scanning laser annealing in the formation of n-type source/drain junctions in next generation MOSFET. We present a model to approximate the true thermal profile for a commercial laser annealing process which allows us to represent more precisely specific thermal steps using Technology Computer Aided Design (TCAD). Sheet resistance and Hall Effect measurements for blanket films are used to correlate dopant activation and mobility with the regrowth process during laser anneal. We show the onset of high conductivity associated with completion of solid phase epitaxial regrowth (SPER) in the films. The Lattice Kinetic Monte Carlo (LKMC) model shows excellent agreement with cross section transmission electron microscopy (TEM), correlating the increase of conductivity with completion of crystal regrowth, increased activation, and crystal quality at various temperatures. As scaled devices move into the non-planar geometries and possibly adopt silicon-on-insulator (SOI) substrates, the crystal regrowth and dopant activation of amorphizing implants becomes more complicated and doping methods must adapt accordingly. Following the concept of the more recently proposed hot ion implantation and the benefits of laser anneal, we investigate a possible process flow for a 10/14 nm node SOI finFET by utilizing process and device TCAD. Device simulation parameters for the 10/14 nm node device are taken from a calibrated model based on fabricated non-planar 40 nm gate length device finFET. The implications on device performance are considered for the

  3. Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

    NASA Astrophysics Data System (ADS)

    Kho Ching Tee, Elizabeth; Antoniou, Marina; Udrea, Florin; Hoelke, Alexander; Ng, Liang Yew; Bin Wan Zainal Abidin, Wan Azlan; Pilkington, Steven John; Pal, Deb Kumar

    2014-06-01

    Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given.

  4. Strained SOI/SGOI dual-channel CMOS technology based on the Ge condensation technique

    NASA Astrophysics Data System (ADS)

    Tezuka, Tsutomu; Nakaharai, Shu; Moriyama, Yoshihiko; Hirashita, Norio; Toyoda, Eiji; Numata, Toshinori; Irisawa, Toshifumi; Usuda, Koji; Sugiyama, Naoharu; Mizuno, Tomohisa; Takagi, Shin-ichi

    2007-01-01

    Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs were fabricated by oxidizing strained SiGe layers on SOI substrates at high temperatures. It was found that strain was accumulated in the SGOI channels during this process, called Ge condensation, associated with the increase in the Ge fraction. Significant hole-mobility enhancements up to a factor of 10 were observed due to the high Ge fractions over 0.5 and large strain values over 1%. The SGOI pMOSFETs were also co-integrated with strained SOI nMOSFETs or ultra-thin SOI nMOSFETs to form dual-channel CMOS devices. The dual-channel structures were fabricated by conventional CMOS processes combined with the Ge condensation process and selective epitaxial growth processes. High hole mobility was observed in the SGOI pMOSFETs of the CMOS devices, whereas an enhancement or no degradation of electron mobility was observed in the strained or the unstrained SOI nMOSFETs. Based on the measured carrier mobility of the long-channel nMOSFETs and pMOSFETs, short-channel CMOS performance enhancement of around 30% was estimated.

  5. A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device.

    PubMed

    Lee, Myung-Jae; Sun, Pengfei; Charbon, Edoardo

    2015-05-18

    This paper reports on the first implementation of a single-photon avalanche diode (SPAD) in standard silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The SPAD is realized in a circular shape, and it is based on a P(+)/N-well junction along with a P-well guard-ring structure formed by lateral diffusion of two closely spaced N-well regions. The SPAD electric-field profile is analyzed by means of simulation to predict the breakdown voltage and the effectiveness of premature edge breakdown. Measurements confirm these predictions and also provide a complete characterization of the device, including current-voltage characteristics, dark count rate (DCR), photon detection probability (PDP), afterpulsing probability, and photon timing jitter. The SOI CMOS SPAD has a PDP above 25% at 490-nm wavelength and, thanks to built-in optical sensitivity enhancement mechanisms, it is as high as 7.7% at 850-nm wavelength. The DCR is 244 Hz/μm2, and the afterpulsing probability is less than 0.1% for a dead time longer than 200 ns. The SPAD exhibits a timing response without exponential tail and provides a remarkable timing jitter of 65 ps (FWHM). The new device is well suited to operate in backside illumination within complex three-dimensional (3D) integrated circuits, thus contributing to a great improvement of fill factor and jitter uniformity in large arrays. PMID:26074572

  6. Development of 1×4 micro optical switch based on SOI vertical micromirror technology

    NASA Astrophysics Data System (ADS)

    Wang, Zhenfeng P.; Shan, Xue Chuan; Wang, Zhiping; Cao, Wenqing; Xu, Jianfeng; Lim, Siak-Piang; Noell, Wilfried; de Rooij, Nico F.

    2003-01-01

    In this paper, the development of a 1X4 micro optical switch utilizing electrostatic actuation and vertical silicon mirrors was reported. This device was fabricated from silicon-on-insulator (SOI) wafer using a bulk micromachining process, which allowed the fabrication of vertical mirrors and U-grooves through deep reactive ion etching (DRIE) of silicon. A few process steps were required in the fabrication. Moreover, the device was patterned in a single lithographic step. A relatively high yield (up to 70%) was achieved during the microfabrication due to this compact process flow. More importantly, the footprint was less than 13mm2. To verify the design, the stress/strain distribution around the actuator was examined using FEM simulation. The relationship between driving voltage and mirror displacement derived from simulation agreed well with the measurement. Tapered lensed singlemode fiber were assembled into U-grooves and positioned passively by fiber stopper. The device was then packaged and pigtailed. Characterization on the mechanical and optical performance of this device show the promising characteristics of this 1×4 optical switch for use in optical networks.

  7. Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

    NASA Astrophysics Data System (ADS)

    Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; de Moro, F.; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

    2008-09-01

    Several successful development programs have been conducted on infra-red bolometer arrays at the "Commissariat à l'Energie Atomique" (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8×8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32×32 pixels in size.

  8. Development of a CMOS SOI Pixel Detector

    SciTech Connect

    Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; Ikeda, H.; Hara, K.; Ishino, H.; Kawasaki, T.; Miyake, H.; Martin, E.; Varner, G.; Tajima, H.; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

    2008-08-19

    We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

  9. Development of X-ray microcalorimeters based on SOI technology and experimental results

    NASA Astrophysics Data System (ADS)

    Szeflinski, V.; Aliane, A.; De Moro, F.; Pigot, C.; Sauvageot, J.-L.; Agnèse, P.; Gasse, A.; Ribot, H.; Gremion, E.; De La Broise, X.; Navick, X. F.

    2009-10-01

    We are developing an X-ray spectro-imaging detector at cryogenic temperature (<100 mK) for next space generation missions, using silicon technology. Each pixel of this array detector is made of a tantalum absorber bonded by indium bump hybridization, to an implanted and high-temperature diffused silicon thermistor. The thermo-mechanical link, provided by the indium bump hybridization, is being improved in terms of thermal capacitance. We present the state of development and experimental results on this new generation of X-ray microcalorimeters.

  10. A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

    NASA Astrophysics Data System (ADS)

    Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

    2016-02-01

    A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

  11. RC64, a Rad-Hard Many-Core High- Performance DSP for Space Applications

    NASA Astrophysics Data System (ADS)

    Ginosar, Ran; Aviely, Peleg; Gellis, Hagay; Liran, Tuvia; Israeli, Tsvika; Nesher, Roy; Lange, Fredy; Dobkin, Reuven; Meirov, Henri; Reznik, Dror

    2015-09-01

    RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

  12. SOI diode uncooled infrared focal plane arrays

    NASA Astrophysics Data System (ADS)

    Kimata, Masafumi; Ueno, Masashi; Takeda, Munehisa; Seto, Toshiki

    2006-02-01

    An uncooled infrared focal plane array (IR FPA) is a MEMS device that integrates an array of tiny thermal infrared detector pixels. An SOI diode uncooled IR FPA is a type that uses freestanding single-crystal diodes as temperature sensors and has various advantages over the other MEMS-based uncooled IR FPAs. Since the first demonstration of an SOI diode uncooled IR FPA in 1999, the pixel structure has been improved by developing sophisticated MEMS processes. The most advanced pixel has a three-level structure that has an independent metal reflector for interference infrared absorption between the temperature sensor (bottom level) and the infrared-absorbing thin metal film (top level). This structure makes it possible to design pixels with lower thermal conductance by allocating more area for thermal isolation without reducing infrared absorption. The new MEMS process for the three-level structure includes a XeF II dry bulk silicon etching process and a double organic sacrificial layer surface micromachining process. Employing advanced MEMS technology, we have developed a 640 x 480-element SOI diode uncooled IR FPA with 25-μm square pixels. The noise equivalent temperature difference of the FPA is 40 mK with f/1.0 optics. This result clearly demonstrates the great potential of the SOI diode uncooled IR FPA for high-end applications. In this paper, we explain the advances and state-of-the-art technology of the SOI diode uncooled IR FPA.

  13. Implementation and Application of SOIS

    NASA Astrophysics Data System (ADS)

    Fowell, S.; Notebaert, O.; Gunes-Lasnet, S.

    2009-05-01

    This paper describes the implementation of a reference library of the CCSDS Spacecraft Onboard Interface Services (SOIS) standards in the SOIS Reference Implementation project, an ESA TRP contract, and the application of SOIS within the GenFAS onboard software framework for the Modular Architecture for Robust Computing (MARC) project, an ESA GSTP contract.

  14. Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

    NASA Astrophysics Data System (ADS)

    Koyama, M.; Cassé, M.; Barraud, S.; Ghibaudo, G.; Iwai, H.; Faynot, O.; Reimbold, G.

    2015-06-01

    A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.

  15. Compact analytical modeling of SOI partially depleted MOSFETs with LETISOI

    NASA Astrophysics Data System (ADS)

    Faynot, O.; Poiroux, T.; Pelloie, J. L.

    2001-04-01

    As SOI technology becomes very attractive for ULSI CMOS, a dedicated and accurate SOI model has to be developed in order to take into account all specific electrical effects related to the SOI structure. The LETISOI model has been developed for partially depleted SOI devices; current and charge equations are built on a physical basis. In addition to the classical MOS conduction, FB effects, self-heating and bipolar transistor action have to be accurately modeled. The transient behavior, very different from the static one, has to be analyzed and kept in mind by designers to take full benefit of SOI devices in circuits, while avoiding any design issue due to SOI. Both FB and body-contacted devices can be described with this model. This paper describes how the model is built with an emphasis on the specific SOI needs and the related strategy for parameter extraction. Typical simulation results are also presented, outlining the capability of the model to simulate SOI specific dynamic behavior like bipolar activation and history effects.

  16. A 60 GOPS/W, -1.8V to 0.9V body bias ULP cluster in 28nm UTBB FD-SOI technology

    NASA Astrophysics Data System (ADS)

    Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

    2016-03-01

    Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors

  17. Preliminary results on low power sigmoid neuron transistor response in 28 nm high-k metal gate Fully Depleted SOI technology

    NASA Astrophysics Data System (ADS)

    Galy, Ph.; Dehan, P.; Jimenez, J.; Heitz, B.

    2013-11-01

    The purpose of this paper is to describe a preliminary approach to achieve a sigmoid neuron transistor response using the 28 nm high-k metal gate Fully Depleted SOI (FDSOI) technology. It is well known that a neural network is an ambitious way to handle signal and/or data flow. Of interest also is the 'learning phase' of the proposed structure. However, the major difficulty of such structures, where the elementary device is a "Neuron Design (ND)" is in their integration. The elementary ND is based upon a circuit with at least ten interconnected CMOS transistors in order to obtain a sigmoid response activation function (in this example) with multiple inputs typically as per the McCulloch and Pitts model. Given that a large number of NDs are required to build an Artificial Neural Network (ANN), the power consumption of such a structure is a key topic that is also addressed. Another open question concerns the dispersion response due to process variability. This study reports on a new single undoped Formal Neuron Transistor (NT) solution.

  18. Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

    NASA Astrophysics Data System (ADS)

    Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

    2014-08-01

    The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STARDundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITARfree and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

  19. The ESA Rad-Hard electron monitor (RADEM) for JUICE

    NASA Astrophysics Data System (ADS)

    Desorgher, Laurent; Hajdas, Wojtek; Goncalves, Patricia; Pinto, Costa; Marques, Arlindo; Chastellain, Frédéric; Gambarara, Fabio; Muff, Reto; Maehlum, Gunnar; Meier, Dirk

    2014-05-01

    The ESA Jupiter Icy moons explorer (JUICE) mission will encounter a harsh radiation environment that is known to be severe but that is not yet fully understood. The Rad-Hard electron monitor (RADEM), currently under development, is a compact instrument (1L, 1kg, 2.2W) that will be set on JUICE for measuring the radiation environment during the mission. Its design is adapted to the harsh Jovian radiation environment and optimized for the detection of high energetic electrons. RADEM will consist of three detector subunits. The magneto-spectrometer will measure the electron spectrum in the 0.3 to 40 MeV range. The directionality sensor will characterize the pitch angle distribution of the electron environment. The Silicon stack detector will be dedicated to measure the spectrum of solar and Jovian protons, as well as the LET spectrum of heavy ions. In this paper we present the status of the development of RADEM, as well as Geant4 Monte Carlo analysis of the capability of the instruments.

  20. Assessment of SOI Devices and Circuits at Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

    2007-01-01

    Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

  1. Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

    NASA Astrophysics Data System (ADS)

    Schwarzenbach, Walter; Nguyen, Bich-Yen; Allibert, Frederic; Girard, Christophe; Maleville, Christophe

    2016-03-01

    This paper reviews the properties of the SOI wafers fabricated using the Smart Cut™ technology, with ultra-thin body and buried oxide (BOX) required for the FD-SOI CMOS platform. It focuses on the parameters that require specific attention for this technology, namely, the top silicon layer thickness uniformity and buried oxide reliability. The first one is linked to the threshold voltage variability and the second to the active role played by the BOX when a back-bias is used. An overview of the specific process optimization and metrology developed to achieve the targeted specifications is given.

  2. A low-noise wide-dynamic-range event-driven detector using SOI pixel technology for high-energy particle imaging

    NASA Astrophysics Data System (ADS)

    Shrestha, Sumeet; Kamehama, Hiroki; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

    2015-08-01

    This paper presents a low-noise wide-dynamic-range pixel design for a high-energy particle detector in astronomical applications. A silicon on insulator (SOI) based detector is used for the detection of wide energy range of high energy particles (mainly for X-ray). The sensor has a thin layer of SOI CMOS readout circuitry and a thick layer of high-resistivity detector vertically stacked in a single chip. Pixel circuits are divided into two parts; signal sensing circuit and event detection circuit. The event detection circuit consisting of a comparator and logic circuits which detect the incidence of high energy particle categorizes the incident photon it into two energy groups using an appropriate energy threshold and generate a two-bit code for an event and energy level. The code for energy level is then used for selection of the gain of the in-pixel amplifier for the detected signal, providing a function of high-dynamic-range signal measurement. The two-bit code for the event and energy level is scanned in the event scanning block and the signals from the hit pixels only are read out. The variable-gain in-pixel amplifier uses a continuous integrator and integration-time control for the variable gain. The proposed design allows the small signal detection and wide dynamic range due to the adaptive gain technique and capability of correlated double sampling (CDS) technique of kTC noise canceling of the charge detector.

  3. Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements

    NASA Astrophysics Data System (ADS)

    Kazemi Esfeh, B.; Kilchytska, V.; Barral, V.; Planes, N.; Haond, M.; Flandre, D.; Raskin, J.-P.

    2016-03-01

    This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are determined. It is shown that fT of ∼280 GHz and fmax of ∼250 GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S-parameters.

  4. CMOS/SOI hardening at 100 MRAD (SiO sub 2 )

    SciTech Connect

    Leray, J.L.; Dupont-Nivet, E.; Pere, J.F.; Coic, Y.M.; Raffaelli, M. ); Auberton-Herve, A.J.; Bruel, M.; Giffard, B., Margail, J. )

    1990-12-01

    Hardened CMOS/SOI 29101 microprocessor, elementary cells and transistor shave been irradiated at levels between 10 Mrad(SiO{sub 2}) and 1 Grad(SiO{sub 2}) ({sup 60}Co and 10 keV x-rays). SIMOX buried oxide behavior in the range of 100 Mrad(SiO{sub 2}) and a channel-stopped MOS/SOI structure avoiding lateral leakage current are presented. These two items indicate the feasibility of a CMOS/SOI technology operating in the hundred Mrad(SiO{sub 2}) range.

  5. Micro biochemical sensor based on SOI planar optical waveguide

    NASA Astrophysics Data System (ADS)

    Du, Yang; Dong, Ying

    2014-02-01

    A novel biochemical sensor based on planar optical waveguide is presented in this paper. The features of the sensor are as follows, the planar optical waveguide is made of SOI (Silicon-On-Insulator) material, a Mach Zehnder (M-Z) Interferometer structure is adopted as the sensing part, the sensor chip is fabricated using CMOS compatible technology and the size of the sensor chip is on the micron scale. Compared with the traditional biochemical sensors, this new type of sensor has such notable advantages as miniaturization, integration, high sensitivity and strong anti-interference capability, which provide the sensor with potential applications where traditional biochemical sensors cannot be used. At first, the benefits of SOI material comparing to other optical waveguide materials were analyzed in this paper. Then, according to the optical waveguide mode theory, M-Z interferometer waveguide was designed for the single mode behavior. By theoretical analysis of the radiation loss in the Y-junction of the planar waveguide interferometer, the relationship between the branch angle and the radiation loss was obtained. The power transfer function and the parametric equation of sensitivity of the M-Z interferometer were obtained through analysis of the waveguide structure. At last, the resolution of the effective refractive index and the characteristics of sensitivity of the sensor based on SOI M-Z Interferometer waveguide were simulated and analyzed by utilizing MATLAB software. As a result, the sensitivity of SOI M-Z Interferometer sensor can reach the order of 10-7 magnitude.

  6. Method to improve commercial bonded SOI material

    DOEpatents

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  7. MEMS Using SOI Substrate

    NASA Technical Reports Server (NTRS)

    Tang, Tony K.

    1999-01-01

    At NASA, the focus for smaller, less costly missions has given impetus for the development of microspacecraft. MicroElectroMechanical System (MEMS) technology advances in the area of sensor, propulsion systems, and instruments, make the notion of a specialized microspacecraft feasible in the immediate future. Similar to the micro-electronics revolution,the emerging MEMS technology offers the integration of recent advances in micromachining and nanofabrication techniques with microelectronics in a mass-producible format,is viewed as the next step in device and instrument miniaturization. MEMS technology offers the potential of enabling or enhancing NASA missions in a variety of ways. This new technology allows the miniaturization of components and systems, where the primary benefit is a reduction in size, mass and power. MEMS technology also provides new capabilities and enhanced performance, where the most significant impact is in performance, regardless of system size. Finally,with the availability of mass-produced, miniature MEMS instrumentation comes the opportunity to rethink our fundamental measurement paradigms. It is now possible to expand our horizons from a single instrument perspective to one involving multi-node distributed systems. In the distributed systems and missions, a new system in which the functionality is enabled through a multiplicity of elements. Further in the future, the integration of electronics, photonics, and micromechanical functionalities into "instruments-on-a-chip" will provide the ultimate size, cost, function, and performance advantage. In this presentation, I will discuss recent development, requirement, and applications of various MEMS technologies and devices for space applications.

  8. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOEpatents

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  9. Temporal analysis of SEU in SOI/GAA SRAMs

    SciTech Connect

    Francis, P.; Colinge, J.P.; Berger, G.

    1995-12-01

    This paper analyzes the very strong SEU hardness of a 1k static random-access memory fabricated using the SOI/GAA technology, irradiated with a xenon ion beam at various angles of incidence. The memory has been shown to operate with a supply voltage as low as 2V while still presenting excellent SEU hardness. Since the different physical charge collection mechanisms are particularly slow in SOI devices, it is shown that collected and critical charges must be dynamically compared in order to determine the SEU threshold. A new approach is then proposed to evaluate the time-variable critical charge independently of the pulse shape generated by the incident ion, and a general analytical model is derived. Finally, predictions in good agreement with experimental data are obtained.

  10. Leakage currents in SOI MOSFETS

    SciTech Connect

    Annamala, N.K.; Biwer, M.C.

    1988-12-01

    Total dose response of both NMOS and PMOS FETs fabricated on SOI substrates was studied. Two types of back-channel leakage currents were identified. A back-channel leakage due to MOSFET action uses the substrate bias as the gate bias. The other component is due to soft reverse characteristics of the body-drain junction. The back-channel leakage due to MOSFET action varies with the substrate bias and hence varies with irradiation due to threshold voltage shift. The soft reverse characteristics are a function of drain-body voltage and hence vary with substrate bias and irradiation. I-V characteristics and subthreshold currents of both front and back channels as a function of total dose were obtained.

  11. Rad-Hard Structured ASIC Body of Knowledge

    NASA Technical Reports Server (NTRS)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  12. SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

    SciTech Connect

    Alles, M.L. )

    1994-12-01

    Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

  13. Electron trapping in rad-hard RCA IC's irradiated with electrons and gamma rays

    NASA Technical Reports Server (NTRS)

    Danchenko, V.; Brashears, S. S.; Fang, P. H.

    1984-01-01

    Enhanced electron trapping has been observed in n-channels of rad-hard CMOS devices due to electron and gamma-ray irradiation. Room-temperature annealing results in a positive shift in the threshold potential far beyond its initial value. The slope of the annealing curve immediately after irradiation was found to depend strongly on the gate bias applied during irradiation. Some dependence was also observed on the electron dose rate. No clear dependence on energy and shielding over a delidded device was observed. The threshold shift is probably due to electron trapping at the radiation-induced interface states and tunneling of electrons through the oxide-silicon energy barrier to fill the radiation-induced electron traps. A mathematical analysis, based on two parallel annealing kinetics, hole annealing and electron trapping, is applied to the data for various electron dose rates.

  14. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  15. A self-priming, high performance, check valve diaphragm micropump made from SOI wafers

    NASA Astrophysics Data System (ADS)

    Kang, Jianke; Mantese, Joseph V.; Auner, Gregory W.

    2008-12-01

    In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named 'SOI/SOI wafer bonding and etching back followed by a second wafer bonding' was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l µm min-1 by adjusting frequency. The maximum pumping rate was 860 µl min-1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

  16. Experimental developments of A2RAM memory cells on SOI and bulk substrates

    NASA Astrophysics Data System (ADS)

    Rodriguez, Noel; Gamiz, Francisco; Navarro, Carlos; Marquez, Carlos; Andrieu, François; Faynot, Olivier; Cristoloveanu, Sorin

    2015-01-01

    A2RAM prototype devices have been demonstrated in both SOI and bulk technologies. The fabrication process has successfully achieved the characteristic retrograde doping profile of the channel which allows the coexistence of electrons and holes in the same body while maintaining low-voltage single-gate operation. The different prototypes have been electrically characterized, all of them exhibiting memory effect. The SOI samples present the best performance, showing very attractive current margin between states, competitive retention time, reasonable variability, immunity to disturbance events and no endurance issues even in the short-channel devices fabricated in the most advanced 22 nm process.

  17. Advanced CAD methodology for history effect characterization in partially depleted SOI libraries

    NASA Astrophysics Data System (ADS)

    Liot, Vincent; Flatresse, Philippe; Fournier, Jean Michel; Belleville, Marc

    2005-09-01

    To design large digital circuits in partially depleted SOI technology, worst and best case propagation delays of digital cells induced by floating body effects must be predicted. In this paper, we propose a time efficient and accurate method based on a smart transistor initialisation technique. This solution allows dividing by a factor 2 n-1 the number of simulations required to completely characterize an n-input gate. This method offers the opportunity to build CAD tools suitable for industrial PD-SOI standard cell libraries characterization.

  18. Test of a fine pitch SOI pixel detector with laser beam

    NASA Astrophysics Data System (ADS)

    Yi, Liu; Yunpeng, Lu; Xudong, Ju; Qun, Ou-Yang

    2016-01-01

    A silicon pixel detector with fine pitch size of 19 μm × 19 μm, developed based on SOI (silicon-on-insulator) technology, was tested under the illumination of infrared laser pulses. As an alternative method for particle beam tests, the laser pulses were tuned to very short duration and small transverse profile to simulate the tracks of MIPs (minimum ionization particles) in silicon. Hit cluster sizes were measured with focused laser pulses propagating through the SOI detector perpendicular to its surface and most of the induced charge was found to be collected inside the seed pixel. For the first time, the signal amplitude as a function of the applied bias voltage was measured for this SOI detector, deepening understanding of its depletion characteristics. Supported by National Natural Science Foundation of China (11375226)

  19. Applying the S.O.I. Model to Curriculum Development.

    ERIC Educational Resources Information Center

    Brown, Marilyn A.

    The article discusses the use of the Structure of Intellect (SOI) model as a basis for developing thinking abilities in a variety of curriculum areas: (1) the integration of subject matter areas and SOI operations; (2) thematic lessons that sequence specific cells of the SOI model; (3) directed teaching lessons to develop student awareness of…

  20. Radiation hardness of a 180 nm SOI monolithic active pixel sensor

    NASA Astrophysics Data System (ADS)

    Fernandez-Perez, S.; Backhaus, M.; Pernegger, H.; Hemperek, T.; Kishishita, T.; Krüger, H.; Wermes, N.

    2015-10-01

    The use of Silicon-on-Insulator (SOI) technology as a particle detector in a high radiation environment is, at present, limited mostly by radiation effects on the transistor characteristics, back gate effect, and mutual coupling between the Buried Oxide (BOX) and the sensor. We have fabricated and tested a new 0.18 μm SOI CMOS monolithic pixel sensor using the XFAB process. In contrast to the most commonly used SOI technologies, this particular technology uses partially depleted SOI transistors, offering a double well structure, which shields the thin gate oxide transistors from the BOX. In addition, an increased distance between transistors and a thicker BOX than has been previously used offers promising solutions to the performance limitations mentioned above. The process further allows the use of high voltages (up to 200 V), which are used to partially deplete the substrate. Thus, the newly fabricated device in the XFAB process is especially interesting for applications in extremely high radiation environments, such as LHC experiments. A four stage validation programme of the technology and the fabricated monolithic pixel sensor has been performed and its results are shown in this paper. The first targets radiation hardness of the transistor characteristics up to 700 Mrad, the second investigates the existence of the back gate effect, the third one targets the coupling between the BOX and the sensor, and the fourth investigates the characterization of charge collection in the sensor diode below the BOX.

  1. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  2. Performance analysis of SOI MOSFET with rectangular recessed channel

    NASA Astrophysics Data System (ADS)

    Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

    2016-03-01

    In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

  3. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  4. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

    PubMed

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-01-01

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

  5. Cantilever-type Thermal Microactuators Fabricated by SOI-MUMPs with U-type and I-type Configurations

    NASA Astrophysics Data System (ADS)

    Osada, Takahiro; Ochiai, Kuniyuki; Osada, Kazuki; Muro, Hideo

    Recently, the micro fluid systems have been extensively studied, where microactuators such as micro valves fabricated by MEMS technology are essential for realizing these systems. In this paper thermal microactuators with U-type and I-type shapes fabricated by SOI-MUMPs technology have been investigated for optimizing their configurations.

  6. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

    PubMed Central

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-01-01

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA. PMID:26295235

  7. Studies of vertex tracking with SOI pixel sensors for future lepton colliders

    NASA Astrophysics Data System (ADS)

    Battaglia, Marco; Contarato, Devis; Denes, Peter; Liko, Dietrich; Mattiazzo, Serena; Pantano, Devis

    2012-07-01

    This paper presents a study of vertex tracking with a beam hodoscope consisting of three layers of monolithic pixel sensors in SOI technology on high-resistivity substrate. We study the track extrapolation accuracy, two-track separation and vertex reconstruction accuracy in π- Cu interactions with 150 and 300 GeV/c pions at the CERN SPS. Results are discussed in the context of vertex tracking at future lepton colliders.

  8. Cassini SOI Radio Occultation of Saturn's Rings

    NASA Astrophysics Data System (ADS)

    Marouf, E.; French, R.; Rappaport, N.; Thomson, F.; McGhee, C.; Asmar, S.; Johnston, D.

    2004-11-01

    On July 1, 2005 at 01:12 SCET-UTC, Cassini started the engine burn required to insert the spacecraft into orbit around Saturn (SOI). Almost 30 minutes later, Cassini was occulted by Saturn's rings as seen from the Earth. The geometric ring occultation covered all main ring features, starting at the outer edge of Ring A at 01:42 and ending at the inner edge of Ring C at 02:40. From 01:12 to 03:07, Cassini X-band radio signal (3.6 cm-wavelength) was turned on, primarily to monitor the burn. The sinusoidal transmitted signal was referenced to the on board ultrastable oscillator, allowing measurement of the signal amplitude and phase at the 70-m ground receiving station of the Deep Space Network at Canberra, Australia. As a useful by-product, a complete ring occultation observation, including free-space baseline, was achieved. Because of the special orientation of the spacecraft during the burn, the Cassini low-gain antenna was used to transmit the signal. Nominal radio occultations are conducted using the high-gain antenna, hence have intrinsic free-space signal-to-noise ratio (SNR) higher by a factor of 10,000 than the SOI occultation. Nonetheless, clearly detectable signal was observed during occultation by features in Rings A, Cassini Division, and Ring C, but not Ring B. The measurements, after reconstruction to remove diffraction effects, may be used to obtain an optical-depth and phase-shift profiles of resolved ring features. Achievable radial resolution primarily depends on the ring-opening-angle B, available free-space SNR, and occultation geometry. We compare radial resolution achievable for the Cassini SOI occultation (B = 24.7 deg, SNR = 10 dB-Hz) with those of the Voyager ring occultation (B = 5.9 deg, SNR = 50 dB-Hz), and contrast the results with those expected from nominal radio occultations during the Cassini tour. Example optical depth profiles from the Cassini SOI occultation are presented.

  9. Cassini SOI: Magnetometer data re-analysed

    NASA Astrophysics Data System (ADS)

    Southwood, D. J.; Yates, J. N.; Dougherty, M. K.

    2015-10-01

    The Cassini Saturn Orbit Insertion (SOI) on June 30 2004 marked Cassini's closest approach to Saturn in the mission so far. In advance of the proximal orbits it is appropriate to re-examine in preparation for the proximal orbit mission phase. SOI was the only occasion so far that Cassini has been on magnetic shells mapping to the A and B rings. At periapsis (r = 1.33 RS, Γ = 15°) it was magnetically conjugate to the inner edge of the C ring. It cannot be ruled out that the observed field inside L ≈ 1.5 is partly due to the longitude dependent internal field. g11 is a primary target and should show up in the data in special manner in part because of the spacecraft switch from retrograde to prograde motion around L &sim 2. Accordingly, for a source rotating at around 10.5-10.7 h., the spacecraft would sample azimuthal phase three times. This is illustrated here for the external cam source (G11) where the effect is dramatic as the amplitude does change with r. We show in particular that the cam fields appear to extend into the regime over the rings.

  10. Influence of edge effects on single event upset susceptibility of SOI SRAMs

    NASA Astrophysics Data System (ADS)

    Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

    2015-01-01

    An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down.

  11. Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

    NASA Astrophysics Data System (ADS)

    Cortés, I.; Fernández-Martínez, P.; Flores, D.; Hidalgo, S.; Rebollo, J.

    2008-01-01

    This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (Ron) value maintaining the same voltage capability. The increment of the N+ source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low Ron results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

  12. The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications

    NASA Astrophysics Data System (ADS)

    Cortés, I.; Fernández-Martínez, P.; Flores, D.; Hidalgo, S.; Rebollo, J.

    2007-10-01

    This paper is addressed to the analysis of the trench gate LDMOS transistor (TGLDMOS) in a thin SOI technology and to investigate its suitability for low voltage power applications. The static and dynamic performances have been extensively analyzed by means of numerical simulations and compared with a conventional thin SOI power LDMOS transistor. The specific on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. In this sense, a modified TGLDMOS is also proposed to reduce the gate-drain capacitance and to increase the frequency capability. The expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors corroborate their suitability for 80 V switching and amplifying applications.

  13. Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

    NASA Technical Reports Server (NTRS)

    Brucker, G. J.; Van Gunten, O.; Stassinopoulos, E. G.; Shapiro, P.; August, L. S.; Jordan, T. M.

    1983-01-01

    This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

  14. Charge accumulation in the buried oxide of SOI structures with the bonded Si/SiO2 interface under γ-irradiation: effect of preliminary ion implantation

    NASA Astrophysics Data System (ADS)

    Naumova, O. V.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P.

    2012-06-01

    In this study, we examined the effect of preliminary boron or phosphorous implantation on charge accumulation in the buried oxide of SOI-MOSFETs irradiated with γ-rays in the total dose range (D) of 105-5 × 107 rad. The buried oxide was obtained by high-temperature thermal oxidation of Si, and it was not subjected to any implantation during the fabrication process of SOI structures. It was found that implantation with boron or phosphorous ions, used in fabrication technologies of SOI-MOSFETs, increases the concentration of precursor traps in the buried oxide of SOI structures. Unlike in the case of boron implantation, phosphorous implantation leads to an increased density of states at the Si/buried SiO2 interface during subsequent γ-irradiation. In the γ-irradiated SOI-MOSFETs, the accumulated charge density and the density of surface states in the Si/buried oxide layer systems both vary in proportion to kiln D. The coefficients ki for as-fabricated and ion-implanted Si/buried SiO2 systems were evaluated. From the data obtained, it was concluded that a low density of precursor hole traps was a factor limiting the positive charge accumulation in the buried oxide of as-fabricated (non-implanted) SOI structures with the bonded Si/buried SiO2 interface.

  15. Application of heat flow models to SOI current mirrors

    NASA Astrophysics Data System (ADS)

    Yu, Feixia; Cheng, Ming-C.

    2004-11-01

    An analytical heat flow model for SOI circuits is presented. The model is able to account for heat exchanges among devices and heat loss from the silicon film and interconnects to the substrate through the buried oxide. The developed model can accurately and efficiently predict the temperature distribution in the interconnect/poly-lines and SOI devices. The model is applied to SOI current mirrors to study heat flow in different layout designs. The results from the developed model are verified with those from Raphael, a 3D numerical simulator that can provide the detailed 3D temperature distribution in interconnect/poly-lines.

  16. High temperature spice modeling of partially depleted SOI MOSFETs

    SciTech Connect

    Osman, M.A.; Osman, A.A.

    1996-03-01

    Several partially depleted SOI N- and P-mosfets with dimensions ranging from W/L=30/10 to 15/3 were characterized from room temperature up to 300 C. The devices exhibited a well defined and sharp zero temperature coefficient biasing point up to 573 K in both linear and saturation regions. Simulation of the I-V characteristics using a temperature dependent SOI SPICE were in excellent agreement with measurements. Additionally, measured ZTC points agreed favorably with the predicted ZTC points using expressions derived from the temperature dependent SOI model for the ZTC {copyright} {ital 1996 American Institute of Physics.}

  17. Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

    2008-01-01

    Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

  18. Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment

    NASA Astrophysics Data System (ADS)

    Flandre, Denis; Nazarov, Alexei N.; Hemment, Peter L. F.

    This book collects the papers presented during NATO Advanced Research Workshop "Science and technology of Semiconductor on Insulator (SOI) structures and devices operating in a harsh environment" held in Kiev 26-30 April 2004. The volume contains both reviews from invited speakers and selected papers presenting major innovations in SOI materials and devices. Particular attention is paid to the reliability of SOI structures operated under harsh conditions. In the first part of the book dealing with SOI material technology, the evolution of SOI materials, achievements in the main standard technologies as Smart Cut, SIMOX, porous silicon as well as methods to create more exotic structures are described.

  19. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  20. Charge collection properties of a depleted monolithic active pixel sensor using a HV-SOI process

    NASA Astrophysics Data System (ADS)

    Fernandez-Perez, S.; Backhaus, M.; Fernandez-Garcia, M.; Gallrapp, C.; Hemperek, T.; Kishishita, T.; Krueger, H.; Moll, M.; Padilla, C.; Pernegger, H.

    2016-01-01

    New pixel detector concepts, based on commercial high voltage and/or high resistivity CMOS processes, are being investigated as a possible candidate to the inner and outer layers of the ATLAS Inner Tracker in the HL-LHC upgrade. A depleted monolithic active pixel sensor on thick film SOI technology is being extensively investigated for that purpose. This particular technology provides a double well structure, which shields the thin gate oxide transistors from the Buried Oxide (BOX). In addition, the distance between transistors and BOX is one order of magnitude bigger than conventional SOI technologies, making the technology promising against its main limitations, as radiation hardness or back gate effects. Its radiation hardness to Total Ionizing Dose (TID) and the absence of back gate effect up to 700 Mrad has been measured and published [1]. The process allows the use of high voltages (up to 300V) which are used to partially deplete the substrate. The process allows fabrication in higher resistivity, therefore a fully depleted substrate could be achieved after thinning. This article shows the results on charge collection properties of the silicon bulk below the BOX by different techniques, in a laboratory with radioactive sources and by edge Transient Current Technique, for unirradiated and irradiated samples.

  1. The effect of integration of Strontium-Bismuth-Tantalate capacitors onto SOI wafers

    NASA Technical Reports Server (NTRS)

    Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki; Strauss, Karl

    2005-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  2. The Effect of Integration of Strontium-Bismuth-Tantalate Capacitors onto SOI Wafers

    NASA Technical Reports Server (NTRS)

    Strauss, Karl F.; Joshi, Vikram; Ohno, Morifumo; Ida, Jiro; Nagatomo, Yoshiki

    2006-01-01

    We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

  3. Germanium-on-SOI waveguides for mid-infrared wavelengths.

    PubMed

    Younis, Usman; Vanga, Sudheer K; Lim, Andy Eu-Jin; Lo, Patrick Guo-Qiang; Bettiol, Andrew A; Ang, Kah-Wee

    2016-05-30

    We report on the development of Germanium-on-SOI waveguides for mid-infrared wavelengths. The strip waveguides have been formed in 0.85 and 2 μm thick Ge grown on SOI substrate with 220 nm thick Si overlayer. The propagation loss for various waveguide widths has been measured using the Fabry-Perot method with temperature tuning. The minimum loss of ~8 dB/cm has been achieved for 0.85 μm thick Ge core using 3.682 μm laser excitation. The transparency of these waveguides has been measured up to at least 3.82 μm. PMID:27410120

  4. A novel nanoscale low-voltage SOI MOSFET with dual tunnel diode (DTD-SOI): Investigation and fundamental physics

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.; Orouji, Ali A.

    2015-06-01

    In this paper, critical electrical characteristics of a nanoscale low-voltage partially-depleted silicon-on-insulator (PD-SOI) MOSFET have been improved in terms of floating body effect, short channel effects, subthreshold swing, leakage current, self-heating effect, voltage gain, parasitic bipolar device effect, parasitic capacitance, and unilateral power gain. The heart of the proposed structure is a dual tunnel diode formed by a heavily doped P-type L-shaped trench. The accumulated holes are effectively released by the tunnel current of the dual tunnel diode. The proposed structure is found to be free of kink effect. Other substantial parameters of the proposed structure have been improved owing to L-shaped trench. Comparing the proposed structure with a conventional SOI (C-SOI), the proposed structure is considered as an undeniable contender in nanoscale integrated applications.

  5. Reduced nonlinearities in 100-nm high SOI waveguides

    NASA Astrophysics Data System (ADS)

    Lacava, C.; Marchetti, R.; Vitali, V.; Cristiani, I.; Giuliani, G.; Fournier, M.; Bernabe, S.; Minzioni, P.

    2016-03-01

    Here we show the results of an experimental analysis dedicated to investigate the impact of optical non linear effects, such as two-photon absorption (TPA), free-carrier absorption (FCA) and free-carrier dispersion (FCD), on the performance of integrated micro-resonator based filters for application in WDM telecommunication systems. The filters were fabricated using SOI (Silicon-on-Insulator) technology by CEA-Leti, in the frame of the FP7 Fabulous Project, which aims to develop low-cost and high-performance integrated optical devices to be used in new generation passive optical- networks (NG-PON2). Different designs were tested, including both ring-based structures and racetrack-based structures, with single-, double- or triple- resonator configuration, and using different waveguide cross-sections (from 500 x 200 nm to 825 x 100 nm). Measurements were carried out using an external cavity tunable laser source operating in the extended telecom bandwidth, using both continuous wave signals and 10 Gbit/s modulated signals. Results show that the use 100-nm high waveguide allows reducing the impact of non-linear losses, with respect to the standard waveguides, thus increasing by more than 3 dB the maximum amount of optical power that can be injected into the devices before causing significant non-linear effects. Measurements with OOK-modulated signals at 10 Gbit/s showed that TPA and FCA don't affect the back-to-back BER of the signal, even when long pseudo-random-bit-sequences (PRBS) are used, as the FCD-induced filter-detuning increases filter losses but "prevents" excessive signal degradation.

  6. An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

    NASA Technical Reports Server (NTRS)

    Jackson, S. A.; Blalock, B. J.; Mojarradi, M. M.; Li, H. W.

    2001-01-01

    The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

  7. An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect

    NASA Astrophysics Data System (ADS)

    Fan-Yu, Liu; Heng-Zhu, Liu; Bi-Wei, Liu; Yu-Feng, Guo

    2016-04-01

    In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SOI FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. Project supported by the Research Program of the National University of Defense Technology (Grant No. JC 13-06-04).

  8. On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

    NASA Astrophysics Data System (ADS)

    de Souza, Michelly; Flandre, Denis; Doria, Rodrigo Trevisoli; Trevisoli, Renan; Pavanello, Marcelo Antonio

    2016-03-01

    This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.

  9. Fabrication and device characteristics of strained-Si-on-insulator (strained-SOI) CMOS

    NASA Astrophysics Data System (ADS)

    Takagi, Shin-ichi; Mizuno, Tomohisa; Tezuka, Tsutomu; Sugiyama, Naoharu; Numata, Toshinori; Usuda, Koji; Moriyama, Yoshihiko; Nakaharai, Shu; Koga, Junji; Tanabe, Akihito; Maeda, Tatsuro

    2004-03-01

    Strained-Si-on-insulator (strained-SOI) CMOS is a promising device structure for satisfying requirements of both high current drive and low supply voltage under sub-100 nm nodes, because of the combination of advantages of SOI MOSFETs and high mobility strained-Si channels. In this paper, we present the concept, the device structures and the fabrication techniques of strained-SOI CMOS. We introduce our original fabrication method of strained-SOI substrates, called the Ge condensation technique. It is experimentally shown that strained-SOI CMOS has higher electron and hole mobility and that strained-SOI CMOS ring oscillators successfully operate with the performance enhancement of 30-70% against conventional SOI CMOS ones.

  10. Analysis of Aluminum-Nitride SOI for High-Temperature Electronics

    NASA Technical Reports Server (NTRS)

    Biegel, Bryan A.; Osman, Mohamed A.; Yu, Zhiping

    2000-01-01

    We use numerical simulation to investigate the high-temperature (up to 500K) operation of SOI MOSFETs with Aluminum-Nitride (AIN) buried insulators, rather than the conventional silicon-dioxide (SiO2). Because the thermal conductivity of AIN is about 100 times that of SiO2, AIN SOI should greatly reduce the often severe self-heating problem of conventional SOI, making SOI potentially suitable for high-temperature applications. A detailed electrothermal transport model is used in the simulations, and solved with a PDE solver called PROPHET In this work, we compare the performance of AIN-based SOI with that of SiO2-based SOI and conventional MOSFETs. We find that AIN SOI does indeed remove the self-heating penalty of SOL However, several device design trade-offs remain, which our simulations highlight.

  11. SOI waveguide based planar reflective grating demultiplexer for FTTH

    NASA Astrophysics Data System (ADS)

    Bidnyk, S.; Feng, D.; Balakrishnan, A.; Pearson, M.; Gao, M.; Liang, H.; Qian, W.; Kung, C.-C.; Fong, J.; Yin, J.; Asghari, M.

    2007-02-01

    Recent deployments of fiber-to-the-home (FTTH) represent the fastest growing sector of the telecommunication industry. The emergence of the silicon-on-insulator (SOI) photonics presents an opportunity to exploit the wide availability of silicon foundries and high-quality low-cost substrates for addressing the FTTH market. We have now demonstrated that a monolithically integrated FTTH demultiplexer can be built using the SOI platform. The SOI filter comprises a monolithically integrated planar reflective grating and a multi-stage Mach-Zehnder interferometer that were fabricated using a CMOS-compatible SOI process with the core thickness of 3.0 μm and optically insulating layer of silica with a thickness of 0.375 μm. The Mach-Zehnder interferometer was used to coarsely separate the 1310 nm channel from 1490 and 1550 nm channels. Subsequently, a planar reflective grating was used to demultiplex the 1490 and 1550 nm channels. The manufactured device showed the 1-dB bandwidth of 110 nm for the 1310 nm channel. For the 1490 nm and 1550 nm channels, the 1-dB bandwidth was measured to be 30 nm. The adjacent channel isolation between the 1490 nm and 1550 nm channels was better than 32 dB. The optical isolation between the 1310 nm and 1490 and 1550 nm channels was better than 45 dB. Applications of the planar reflective gratings in the FTTH networks are discussed.

  12. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    NASA Astrophysics Data System (ADS)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  13. A numerical study of field plate configurations in RF SOI LDMOS transistors

    NASA Astrophysics Data System (ADS)

    Cortés, I.; Roig, J.; Flores, D.; Urresti, J.; Hidalgo, S.; Rebollo, J.

    2006-02-01

    The effect of the source field plate architecture on the static and dynamic electrical performances of SOI LDMOS transistors for RF applications is analysed in this paper. Three architectures are envisaged: source field plate SFP, extended gate field plate and independently biased field plate. Moreover, two different drift diffusion profiles are considered: shallow SDD and deep doped DDD diffusion. The resultant drift region is analytically modelled and the impact of geometrical and technological parameters on the transconductance value is determined by means of numerical simulation techniques. Finally, the dependence of the LDMOS capacitances on the field plate configuration is also studied. Simulation results show the trade-off between reliability and transconductance in each field plate configuration. In spite of the power efficiency improvement, the field plate biasing can significantly degrade the SOI LDMOS performances due to hot-carrier and self-heating effects. On the contrary, the SFP configuration leads to an enhanced reliability at the cost of the on-state resistance increase. The SFP structure with deep doped drift (DDD) diffusion provides the best performances in terms of cut-off frequency and self-heating degradation.

  14. An SOI-based 1550-nm 4×4 multimode interference coupler used for OADC

    NASA Astrophysics Data System (ADS)

    Tian, Ye; Wei, Shile; Qiu, Jifang; Wu, Jian; Zhang, Daolin; Wang, Yue

    2015-08-01

    A novel integrable optical analog-to-digital converter (OADC) scheme based on phase-shifted optical quantization has been proposed for years, the quantization module of which is mainly composed of a 1×2 multi-mode interference (MMI) coupler, a phase modulator and a 4×4MMI. Although the manufacture technology of 1×2 MMI and phase modulator has been very mature, the 4×4MMI on a silicon-on-insulator (SOI) substrate with superior performance has not been realized. Since the 4×4MMI is crucial for the realization of the OADC, we designed and fabricated a 4×4 MMI coupler on SOI substrate. The width and length of the multi-mode section are 10.2 um and 182.6 um respectively. Measurement results show that the imbalance of the four output ports at 1550-nm is around 1.9 dB, while the insertion losses are 5.6 dB.

  15. Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

    NASA Technical Reports Server (NTRS)

    Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

    2006-01-01

    The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

  16. A novel SOI MESFET by reducing the electric field crowding for high voltage applications

    NASA Astrophysics Data System (ADS)

    Orouji, Ali A.; Jam, Moein Eslami; Nejaty, Mohammad

    2014-08-01

    In this paper, a novel silicon-on-insulator (SOI) metal-semiconductor field-effect transistor (MESFET) is presented by reducing the electric field crowding. The charge distribution in channel modifies by reducing the electric field crowding and results in the breakdown voltage (VBR) improves. To reduce the electric field crowding, a buried field plate (BFP) is employed in the buried oxide of the SOI MESFET and connected to source. DC and frequency response characteristics of the SOI MESFET with BFP (BFP-SOI MESFET) are analyzed via a 2-D numerical simulation and the results are compared with characteristics of a conventional SOI MESFET (C-SOI MESFET) structure. The BFP has outstanding effect on the VBR of the device. The VBR of the proposed BFP-SOI MESFET improves by 84% compared with that of the C-SOI MESFET. Although the saturation drain current of the proposed structure has decreased to a small extent, 37% increase in maximum power density is obtained. In addition, the proposed structure showed an approximately 70% decrease in the gate-drain capacitance (Cgd), which in-turn resulted in 5 dB maximum available gain (MAG) improvement at 2 GHz. As a result of employing the buried field plate, the BFP SOI-MESFET has an outstanding DC and frequency response performance compared with the C-SOI MESFET.

  17. Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature

  18. Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

    NASA Astrophysics Data System (ADS)

    Cortes, I.; Fernández-Martínez, P.; Flores, D.; Hidalgo, S.; Rebollo, J.

    2008-09-01

    The benefits of applying the shallow trench isolation (STI) concept to a higher voltage thin-SOI laterally diffused metal oxide semiconductor (LDMOS) (in the range of 80 V) are analysed in this paper by means of 2D technology computer-aided design (TCAD) numerical simulations. The TCAD simulation results allow comparing the electrical performance of the studied STI LDMOS structure with that of a conventional LDMOS in terms of the main static (breakdown voltage (VBR) and specific on-state resistance (RON-sp)) and dynamic (gate-drain capacitance (CGD) and cut-off frequency (fT)) characteristics. Moreover, the impact of the STI length (LSTI) and thickness (TSTI), and the N-drift implantation energy on the electrical characteristics is considered in detail. On the other hand, the STI block helps to move the harmful high electric field further away from the silicon surface, thus minimizing gate-oxide degradation by hot carriers.

  19. Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

  20. Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

    NASA Technical Reports Server (NTRS)

    Patterson, Richard; Hammoud, Ahmad; Dones, Keishla Rivera

    2009-01-01

    Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing

  1. Worst-Case Bias During Total Dose Irradiation of SOI Transistors

    SciTech Connect

    FERLET-CAVROIS,V.; COLLADANT,T.; PAILLET,P.; LERAY,J.-L; MUSSEAU,O.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; PELLOIE,J.L.; DE PONCHARRA,J. JU PORT

    2000-08-15

    The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

  2. Improvement in thickness uniformity of thick SOI by numerically controlled local wet etching.

    PubMed

    Yamamura, Kazuya; Ueda, Kazuaki; Hosoda, Mao; Zettsu, Nobuyuki

    2011-04-01

    Silicon-on-insulator (SOI) wafers are promising semiconductor materials for high-speed LSIs, low-power-consumption electric devices and micro electro mechanical systems (MEMS). The thickness distribution of an SOI causes the variation of threshold voltage in electronic devices manufactured on the SOI wafer. The thickness distribution of a thin SOI, which is manufactured by applying a smart cut technique, is comparatively uniform. On the other hand, a thick SOI has a large thickness distribution because a bonded wafer is thinned by conventional grinding and polishing. For a thick SOI wafer with a thickness of 1 microm, it is required that the tolerance of thickness variation is less than 50 nm. However, improving the thickness uniformity of a thick SOI layer to a tolerance of +/- 5% is difficult by conventional machining because of the fundamental limitations of these techniques. We have developed numerically controlled local wet etching (NC-LWE) technique as a novel deterministic subaperture figuring and finishing technique, which utilizes a localized chemical reaction between the etchant and the surface of the workpiece. We demonstrated an improvement in the thickness distribution of a thick SOI by NC-LWE using an HF/HNO3 mixture, and thickness variation improved from 480 nm to 200 nm within a diameter of 170 mm. PMID:21776652

  3. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  4. Using SST, PDO and SOI for Streamflow Reconstruction

    NASA Astrophysics Data System (ADS)

    Bukhary, S. S.; Kalra, A.; Ahmad, S.

    2015-12-01

    Recurring droughts in southwestern U.S. particularly California, have strained the existing water reserves of the region. Frequency, severity and duration of these recurring drought events may not be captured by the available instrumental records. Thus streamflow reconstruction becomes imperative to identify the historic hydroclimatic extremes of a region and assists in developing better water management strategies, vital for sustainability of water reserves. Tree ring chronologies (TRC) are conventionally used to reconstruct streamflows, since tree rings are representative of climatic information. Studies have shown that sea surface temperature (SST) and climate indices of southern oscillation index (SOI) and pacific decadal oscillation (PDO) influence U.S. streamflow volumes. The purpose of this study was to improve the traditional reconstruction methodology by incorporating the oceanic-atmospheric variables of PDO, SOI, and Pacific Ocean SST, alongwith TRC as predictors in a step-wise linear regression model. The methodology of singular value decomposition was used to identify teleconnected regions of streamflow and SST. The approach was tested on eleven gage stations in Sacramento River Basin (SRB) and San Joaquin River Basin (JRB). The reconstructions were successfully generated from 1800-1980, having an overlap period of 1932-1980. Improved results were exhibited when using the predictor variable of SST along with TRC (calibration r2=0.6-0.91) compared to when using TRC in combination with SOI and PDO (calibration r2=0.51-0.78) or when using TRC by itself (calibration r2=0.51-0.86). For future work, this approach can be replicated for other watersheds by using the oceanic-atmospheric climate variables influencing that region.

  5. Slow light SOI slot photonic crystal waveguides with low loss

    NASA Astrophysics Data System (ADS)

    Caer, Charles; Combrie, Sylvain; Le Roux, Xavier; De Rossi, Alfredo; Cassan, Eric

    2013-05-01

    Slow light in SOI Slotted Photonic Crystal Waveguides (SPCW) infiltrated by a refractive liquid are investigated. By employing an interferometric technique similar to Optical Coherent Tomography (OCT), we report a group velocity lower than c/20 over a 1 mm-long SPCW. From the OCT measurements, we also infer moderate propagation losses. In the fast light regime (nG <10) propagation loss is about 15 dB.cm-1. Moreover, the coupling to slow modes is efficient. These results show that infiltrated slow light SPCW are a promising route to silicon organic hybrid photonics.

  6. SOI/MDI studies of active region seismology and evolution

    NASA Technical Reports Server (NTRS)

    Tarbell, Ted D.; Title, Alan; Hoeksema, J. Todd; Scherrer, Phil; Zweibel, Ellen

    1995-01-01

    The solar oscillations investigation (SOI) will study solar active regions using both helioseismic and conventional observation techniques. The Michelson Doppler imager (MDI) can perform Doppler continuum and line depth imagery and can produce longitudinal magnetograms, showing either the full disk or a high resolution field of view. A dynamics program of continuous full disk Doppler observations for two months per year, campaign programs of eight hours of continuous observation per day, and a synoptic magnetic program of about 15 full disk magnetograms per day, are planned. The scientific plans, measurements and observation programs, are described.

  7. Design, simulation, and fabrication of a 90° SOI optical hybrid based on the self-imaging principle

    NASA Astrophysics Data System (ADS)

    Abdul-Majid, Sawsan; Hasan, Imad I.; Bock, Przemek J.; Hall, Trevor J.

    2010-05-01

    This paper introduces a compact 90º optical hybrid, built on small size SOI waveguide technology .This optical hybrid is a critical component of a potentially low-cost coherent optical receiver design developed within the frame of our Optical Coherent Transmission for Access Network Extensions (OCTANE) project. In previous recent work, 90º optical hybrids were realized in SOI rib waveguide technology with 4 μm top silicon and a rib height of approximately 2 μm. In this paper, we introduce a compact 90º optical hybrid, built on small size SOI waveguide technology (1.5 μm SOI -based rib waveguide, with 0.8μm rib height). The proposed device consists of multimode interferometers (MMIs) connected in such a way that four different vector additions of a reference signal (local oscillator) and the signal to be detected are obtained. At the outputs, the hybrid provides four linear combination of the signal with the reference which differs by a relative phase shift of the reference of 90º. The four output signals are detected by a pair of balanced receivers to provide in-phase and quadrature (I&Q) channels. The phase differences arise naturally from the self imaging property of a MMI. The key elements of the 90º optical hybrid, including a 2×2 MMI, a 4×4 MMI, and polarization diversity configuration have been designed and simulated, using the numerical mode solving tool FIMMPROB. The 2×2 and 4×4 MMI had overall lengths of 701μm and 3712.5μm lengths respectively. Tapers are used to couple adiabatically single mode waveguides to the entrance and exit ports of the MMI to assure correct operation by avoiding coupling to the higher order transverse modes allowed at the entrance and exit ports of the MMI. The simulation results at 1550nm show polarization independence and phase errors between the ports of less than 0.03 degrees. Currently the design is in fabrication at the Canadian Photonics Fabrication Center with the support of CMC Microsystems and experimental

  8. Monolithically fabricated germanium-on-SOI photodetector and Si CMOS circuit for integrated photonic applications

    NASA Astrophysics Data System (ADS)

    Ang, Kah-Wee; Liow, Tsung-Yang; Yu, Ming-Bin; Fang, Qing; Song, Junfeng; Lo, Guo Q.; Kwong, Dim-Lee

    2010-05-01

    In this paper, we report our design and fabrication approach towards realizing a monolithic integration of Ge photodetector and Si CMOS circuits on common SOI platform for integrated photonic applications. The approach, based on the Ge-on-SOI technology, enables the realization of high sensitivity and low noise photodetector that is capable of performing efficient optical-to-electrical encoding in the near-infrared wavelengths regime. When operated at a bias of -1.0V, a vertical PIN detector achieved a lower Idark of ~0.57μA as compared to a lateral PIN detector, a value that is below the typical ~1μA upper limit acceptable for high speed receiver design. Very high responsivity of ~0.92A/W was obtained in both detector designs for a wavelength of 1550nm, which corresponds to a quantum efficiency of ~73%. Impulse response measurements showed that a vertical PIN photodetector gives rise to a smaller FWHM of ~24.4ps, which corresponds to a -3dB bandwidth of ~11.3GHz where RC time delay is known to be the dominant factor limiting the speed performance. Eye patterns (PRBS 27-1) measurement further confirms the achievement of high speed and low noise photodetection at a bit-rate of 8.5Gb/s. In addition, we evaluate the DC characteristics of the monolithically fabricated Si CMOS inverter circuit. Excellent transfer and output characteristics were achieved by the integrated CMOS inverter circuits in addition to the well behaved logic functions. We also assess the impact of the additional thermal budget introduced by the Ge epitaxy growth on the threshold voltage variation of the short channel CMOS transistors and discuss the issues and potential for the seamless integration of electronic and photonic integrated circuits.

  9. Improving breakdown voltage performance of SOI power device with folded drift region

    NASA Astrophysics Data System (ADS)

    Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

    2016-07-01

    A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  10. SOI based electromagnetic MEMS scanners and applications in laser systems

    NASA Astrophysics Data System (ADS)

    Brown, G.; Bauer, R.; Lubeigt, W.; Uttamchandani, D.

    2013-03-01

    MEMS scanners are of interest for their potential as low-cost, low operating power devices for use in various photonic systems. The devices reported here are actuated by the electromagnetic force between a static external magnetic field and a current flowing through an SOI MEMS scanner. These scanners have several modes of operation: their mirrors may be rotated and maintained at a static angle (up to +/- 1.4 degrees), scanned rapidly (up to 500 Hz); or may be operated in a resonance mode, at the device's mechanical resonance frequency (~1.2 kHz) for higher rate scanning. The use of these scanners as a Q-switching element within a Nd:YAG laser cavity has been demonstrated. Pulse durations of 400 ns were obtained with a pulse energy of 58 μJ and a pulse peak power of 145 W. The use of an external magnetic field, generated by compact rare-earth magnets, allows a simple and cost-effective commercial fabrication process to be employed (the multi-user SOI process provided by MEMSCAP Inc) and avoids the requirement to deposit magnetic materials on the MEMS structure.

  11. Contactless electrical characterization of surface and interface of SOI materials

    NASA Astrophysics Data System (ADS)

    Nakamura, S.; Watanabe, D.; En, A.; Suhara, M.; Okumura, T.

    2003-06-01

    Electronic properties of the surface as well as the interface of silicon-on-insulator (SOI) materials have been characterized by the Kelvin method combined with surface photovoltage (SPV) measurements. In order to separate the interface properties from the surface ones, we used the data for the bulk Si surface, which was treated in the same manner, i.e. dipping in a diluted HF solution, as for the SOI surface. From the temperature dependence of the SPV for the bulk Si, the values of the built-in potential, the surface state density and the surface recombination velocity were determined to be about 0.60 eV, 6×10 11 cm -2 and 6×10 3 cm/s, respectively, for the HF-treated Si surface. By taking these values into account, we analyzed the SPV data for separation by implanted oxygen (SIMOX) wafer. The values of the interface state density and the interface recombination velocity at the buried-oxide/SIMOX interface were estimated to be about 3×10 12 cm -2 and 3×10 4 cm/s, respectively.

  12. Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI

    NASA Astrophysics Data System (ADS)

    Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander

    2016-03-01

    In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300 mV of supply voltage, a 4 × 4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOS ⧹ DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.

  13. Parasitic bipolar effect in ultra-thin FD SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Liu, F. Y.; Ionica, I.; Bawedin, M.; Cristoloveanu, S.

    2015-10-01

    The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5-10 nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD > 1.0 V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.

  14. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs

    NASA Astrophysics Data System (ADS)

    Sasaki, K. R. A.; Manini, M. B.; Simoen, E.; Claeys, C.; Martino, J. A.

    2015-10-01

    This work aims to analyze the impact of the Ground Plane (GP) on a new generation of the dynamic threshold (DT2) operation in Ultra-thin Body and Buried Oxide (UTBB) SOI nMOSFETs. The DT2, using a short-circuit between the gate and the substrate contact, the enhanced dynamic threshold (eDT), where the substrate bias is a multiple value of the gate bias (VB = k × VG,k = 1,2,…,5), and the inverse eDT (with VG = k × VB) were compared to the conventional mode with grounded substrate. Although the improvement of the DT2 mode observed for devices with GP is lower, they presented lower short channel effects, mainly for shorter channel lengths. Regarding the direct and inverse eDT modes, a stronger dynamic threshold (DT) effect on devices with GP also results in better DC parameters such as lower subthreshold swing and higher maximum transconductance.

  15. Dynamics Explorer 1 SOI images of the Antarctic ozone hole

    NASA Technical Reports Server (NTRS)

    Keating, G. M.; Bressette, W. E.; Chen, C.; Pitts, M. C.; Craven, J.

    1988-01-01

    The Dynamics Explorer (DE) satellite carries an Auroral Imaging Package which contains filters designed for performing backscatter ultraviolet measurements to measure total column ozone in the Earth's middle and lower atmosphere. Measurements are obtained at 317.5 mm (to measure ozone absorption) and 360 nm (to measure scene reflectivity). In October 1985 and 1986, measurements were obtained near apogee of the Antarctic ozone hole. The only other high spatial resolution measurements were obtained from the Nimbus 7 Total Ozone Mapping Spectrometer (TOMS) experiment. In October 1987, the Dynamics Explorer apogee had precessed into the Northern Hemisphere preventing measurements of the ozone hole. However, measurements should be obtained from DE of the ozone hole in both 1988 and 1989. Considering that the Nimbus 7 TOMS instrument has long exceeded its expected lifetime, the DE Spin Scan Ozone Imager (SOI) experiment could easily play a crucial role in studies of the ozone hole over the next few years.

  16. Design, realization and test of a rad-hard 2D-compressor and packing chip for high energy physics experiments

    NASA Astrophysics Data System (ADS)

    Antinori, Samuele; Falchieri, Davide; Gabrielli, Alessandro; Gandolfi, Enzo

    2004-09-01

    CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 μm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN.

  17. SOIS Support for Onboard Device Virtualisation and the Use of Electronic Data Sheets

    NASA Astrophysics Data System (ADS)

    Fowell, Stuart D.; Melvin, Richard; Mendham, Peter; Torelli, Felice; Taylor, Chris

    2014-08-01

    This paper describes the motivation for, current status of prototyping, and planned standardisation of SOIS Electronic Data Sheets. This is based upon the recent "Adoption of Electronic Data Sheets for Device Virtualisation for Onboard Devices" TRP project for ESA.

  18. A novel high-performance SOI MESFET by stopping the depletion region extension

    NASA Astrophysics Data System (ADS)

    Orouji, Ali A.; Ramezani, Zeinab; Heydari, Akram Anbar

    2014-11-01

    A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for high-power applications. The key idea in this work is to stop the depletion region extension toward the drain and source regions and eliminate the gate adjacent spaces. We called the proposed structure as stopped depletion region extension SOI (SDR-SOI) MESFET. The breakdown voltage (VBR) and small-signal characteristics of the proposed structure improve due to the high critical electric field of the insulator region and less extended depletion region. The optimized results show that the VBR of the SDR-SOI MESFET is 45% larger than that obtained for the conventional SOI MESFET (C-MESFET). Furthermore the maximum output power density of the SDR-SOI MESFET is 0.33 W/mm compared with 0.24 W/mm of the C-MESFET. Meanwhile the elimination of the gate depletion layer extension to source/drain leads to decrease gate-drain capacitance (CGD). So, the proposed structure presents the potential for high-power applications.

  19. Heterojunction fully depleted SOI-TFET with oxide/source overlap

    NASA Astrophysics Data System (ADS)

    Chander, Sweta; Bhowmick, B.; Baishya, S.

    2015-10-01

    In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

  20. Higher-Order Factors in Structure-of-Intellect (SOI) Aptitude Tests Hypothesized to Portray Constructs of Military Leadership: A Re-analysis of an SOI Data Base.

    ERIC Educational Resources Information Center

    Ulosevich, Steven N.; And Others

    1991-01-01

    A correlation matrix of 21 structure-of-intellect (SOI) tests taken by 204 Marine officers at a military base in Southern California, which was intended to reflect aptitudes for military leadership, was reanalyzed through exploratory factor analysis and confirmatory maximum likelihood factor analysis. Higher order factors appeared to have…

  1. High performance SOI microring resonator for biochemical sensing

    NASA Astrophysics Data System (ADS)

    Ciminelli, C.; Dell'Olio, F.; Conteduca, D.; Campanella, C. M.; Armenise, M. N.

    2014-07-01

    In this work we have investigated different silicon-on-insulator (SOI) microcavities based on a planar geometry having a footprint on chip as small as 100 μm2 with a ring, disk and hybrid configurations with the aim of being poorly intrusive for both in-body and out-of-body biosensing purposes. Accurate numerical results have been achieved by using the 3D finite element method and compared to 3D finite discrete time domain ones with a good agreement for both methods. The most promising resonator among the devices we have analyzed shows a Q-factor of the order of 105, that allows a limit of detection for the sensor equal to 10-6 RIU and a sensor sensitivity of 120 nm/RIU. The resonator has been designed for glucose biosensing, considering both the homogeneous sensing and the surface one, that enhances the sensor selectivity by the device functionalization with a glucose-oxidase (GOD) layer. The glucose concentration has been evaluated both with the microcavity surrounded by a water solution and with water only in the inner part of the cavity.

  2. A new latch-free LIGBT on SOI with very high current density and low drive voltage

    NASA Astrophysics Data System (ADS)

    Olsson, J.; Vestling, L.; Eklund, K.-H.

    2016-01-01

    A new latch-free LIGBT on SOI is presented. The new device combines advantages from both LDMOS as well as LIGBT technologies; high breakdown voltage, high drive current density, low control voltages, at the same time eliminating latch-up problems. The new LIGBT has the unique property of independent scaling of the input control device, i.e. LDMOS, and the output part of the device, i.e. the p-n-p part. This allows for additional freedom in designing and optimizing the device properties. Breakdown voltage of over 200 V, on-state current density over 3 A/mm, specific on-resistance below 190 mΩ mm2, and latch-free operation is demonstrated.

  3. An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

    NASA Astrophysics Data System (ADS)

    Ye, Fan; Xiaorong, Luo; Kun, Zhou; Yuanhang, Fan; Yongheng, Jiang; Qi, Wang; Pei, Wang; Yinchun, Luo; Bo, Zhang

    2014-03-01

    A low specific on-resistance (Ron,sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron,sp. Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron,sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron,sp by 80% at the same BV.

  4. Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

    NASA Astrophysics Data System (ADS)

    Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

    2012-04-01

    This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

  5. Higher-Order Abilities Conceptualized within Guilford's Structure-of-Intellect (SOI) Model for a Sample of United States Coast Guard Academy Cadets: A Reanalysis of an SOI Data Base.

    ERIC Educational Resources Information Center

    Chen, Chin-Yi; Michael, William B.

    1993-01-01

    Empirical validation of the first-order and higher-order factor structures of the structure-of-intellect (SOI) model was provided by reanalysis of a database of 39 measures administered to 178 Coast Guard Cadets. Results suggest that SOI could be reconceptualized as a pyramid-like hierarchical theory of intelligence. (SLD)

  6. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  7. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-02-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  8. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 μm. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  9. A novel high-performance high-frequency SOI MESFET by the damped electric field

    NASA Astrophysics Data System (ADS)

    Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

    2016-06-01

    In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

  10. Analysis of surface and interface charge interactions in silicon on insulator (SOI) substrates

    NASA Astrophysics Data System (ADS)

    Lukasiak, L.; Roman, P.; Jakubowski, A.; Ruzyllo, J.

    2001-01-01

    Surface photovoltage (SPV) measurements may provide an effective method for determining electrical properties of silicon on insulator (SOI) surfaces. In the experimental part of this work the use of the non-contact SPV-based method of surface charge profiling (SCP) in the monitoring of surface charges is explored. It was demonstrated that application of this method is constrained by the interactions between charges on the Si surface and at the interface between the Si active layer and buried oxide (box). These interactions are subsequently modeled and related to the SCP measurements. It is demonstrated that at a given doping level, the thickness of the active layer and density of charge associated with the box are factors predetermining the effectiveness of this method in SOI surface characterization. Through modeling, the SOI substrate parameter space for which the SCP method can yield useful information is defined.

  11. Simulation of dual-gate SOI MOSFET with different dielectric layers

    NASA Astrophysics Data System (ADS)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  12. Instrument Technology Development: Key Enabling-Technologies for the Future of Planetary Science

    NASA Astrophysics Data System (ADS)

    Hoffman, J. P.; Piepmeier, J. R.

    2001-11-01

    What are the enabling technologies for the next decade of planetary exploration? The Instrumentation Technology Development Panel (ITD) is working to identify the areas of recent innovation and continuing deficiency in instrument technology as it pertains to planetary science goals and missions. Collaboration between science and technology aspects of all planetary science disciplines is crucial to the success of this task. While it is obvious that mission success, even mission plausibility, is strongly dependent on technical capability, it is, perhaps, less obvious that improvements in technology can also lead to a greater number and/or new types of missions. Therefore, we are interested not only in identifying new types of instrumentation, but also in improving existing (even mature) technologies by reducing size, complexity, and cost. Improvements of this type not only lower mission costs, but also enable more complex instrument suites to be considered for advanced data fusion measurement concepts. We need to identify the short-term and long-term technological needs (new instruments) and bottlenecks (better instruments) for each of the planetary science disciplines and we need input from every discipline to do this. Certain disciplines may feel little pressure to invest time and money into ITD since their instruments are mature. However, if mature technologies can be made less expensive and smaller, more opportunities for science will become available by enabling previously impossible secondary mission instruments. Currently identified areas requiring technology development: - Deployable large (10's of meters) microwave antennas - FIR (sub/mmwave) detectors and antennas - Extreme-temperature semiconductors for Venus (high-temp), Titan (low-temp) - Low power rad-hard electronics - Rad-hard on-board processing power - Increased DSN capacity - Optical interplanetary communications - Lightweight deployable optics - Lightweight, inexpensive, in-situ atmospheric probes

  13. ENVIRONMENTAL TECHNOLOGY VERIFICATION REPORT: IMMUNOASSAY KIT, ENVIROLOGIX, INC., PCB IN SOIL TUBE ASSAY

    EPA Science Inventory

    In July 1997, the U.S. Environmental Protection Agency (EPA) conducted a demonstration of polychlorinated biphenyl (PCB) field analytical techniques. The purpose of this demonstration was to evaluate field analytical technologies capable of detecting and quantifying PCB's in soi...

  14. Polarized single-mode condition for SOI rib waveguide with large cross section

    NASA Astrophysics Data System (ADS)

    Yuan, Dengpeng; Dong, Ying; Liu, Yujin; Li, Tianjian; Zhang, Xudong; Tan, Yushan

    2015-08-01

    In this paper the single mode condition of silicon-on-insulator (SOI) rib waveguide with large cross section is investigated based on the effective index method (EIM) by using numerical computation and analytical derivation with the consideration of the polarization effects. A polarized single-mode condition for SOI rib waveguide with large cross section is presented, the results from analytical derivation are highly concordant with that from numerical computation. For the vertical single-mode condition, the deviations between HE and EH modes correlate oppositely with the total rib height of rib waveguide, and the critical rib height ratio gradually approaches but never equals to 0.5 with the increase of the total rib height. There, HE mode and EH mode are commonly known as quasi-transverse-electric (TE) mode and quasi-transverse-magnetic (TM) mode respectively. The deviation of the critical rib width between HE and EH modes for the lateral single-mode condition is relatively small, which is a function of the rib height ratio but irrelevant to the total rib height for the specified index profile. The fact that the total rib height, index profile, and polarization of modes have effects on the single-mode condition of SOI rib waveguide with large cross section was demonstrated in this work, which was not discussed in the previous works. The results in this work can give guidance to design, simulation and fabrication of SOI rib waveguide with large cross section in practical applications.

  15. 640 x 480 pixel uncooled infrared FPA with SOI diode detectors

    NASA Astrophysics Data System (ADS)

    Ueno, Masashi; Kosasayama, Yasuhiro; Sugino, Takaki; Nakaki, Yoshiyuki; Fujii, Yoshio; Inoue, Hiromoto; Kama, Keisuke; Seto, Toshiki; Takeda, Munehisa; Kimata, Masafumi

    2005-05-01

    This paper describes the structure and performance of a 25-micron pitch 640 x 480 pixel uncooled infrared focal plane array (IR FPA) with silicon-on-insulator (SOI) diode detectors. The uncooled IR FPA is a thermal type FPA that has a temperature sensor of single crystal PN junction diodes formed in an SOI layer. In the conventional pixel structure, the temperature sensor and two support legs for thermal isolation are made in the lower level of the pixel, and an IR absorbing structure is made in the upper pixel level to cover almost the entire pixel area. The IR absorption utilizes IR reflections from the lower level. Since the reflection from the support leg portions is not perfect due to the slits in the metal reflector, the reflection becomes smaller as the support leg section increases in reduced pixel pitches. In order to achieve high thermal isolation and high IR absorption simultaneously, we have developed a new pixel structure that has an independent IR reflector between the lower and upper levels. The structure assures perfect IR reflection and thus improves IR absorption. The FPA shows a noise equivalent temperature difference (NETD) of 40 mK (f/1.0) and a responsivity non-uniformity of less than 0.9%. The good uniformity is due to the high uniformity of the electrical characteristics of SOI diodes made of single crystal silicon (Si). We have confirmed that the SOI diodes architecture is suitable for large format uncooled IR FPAs.

  16. Multiple-layer SOI based on Single-Crystal Si Nanomembrane Transfer

    NASA Astrophysics Data System (ADS)

    Peng, Weina; Roberts, Michelle; Nordberg, Eric; Flack, Frank; Colavita, Paula; Hamers, Robert; Savage, Donald; Lagally, Max; Eriksson, Mark

    2007-03-01

    Silicon-on-insulator (SOI) has many advantages over bulk Si including the reduction of parasitic resistance and increased device speed. Multiple-layer SOI, having more device layers per unit area, enables 3D process integration as well as applications in optics. However, it is impossible to achieve such a system by growth techniques (one can grow only non-crystalline Si on SiO2), and multiple Smart Cut transfers used to create single layer SOI may be prohibitively expensive. We present here a novel method to fabricate such a multiple SOI system using transferred Si nanomembranes^ and subsequent oxidation. The surface roughness and interface quality are examined respectively by AFM and cross-sectional SEM. Low surface roughness (0.176nm) and smooth interfaces are achieved. As an example optical application, we apply the multilayer system to fabricate a Si-based Bragg reflector. The specular reflectivity of one, two, and three-membrane mirrors is measured using FTIR. High specular reflectivity, above 99%, is achieved for three stacked membranes. Comparison of the measured reflectivity with theoretical calculations shows good agreement.

  17. Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

    NASA Technical Reports Server (NTRS)

    Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

    2007-01-01

    We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

  18. The Avionics SOIS Services of CORDET On-Board Software Architecture

    NASA Astrophysics Data System (ADS)

    Alana, Elena; del Carmen Lomba, Maria; Jung, Andreas; Grenham, Adrian; Fowell, Stuart

    2013-08-01

    This paper introduces the specification of the Execution Platform Layer of the On-Board Software Reference Architecture (OBSW-RA) presented in COrDeT-2 study. In particular, the paper addresses the avionics services defined within the context of the overall Spacecraft On-board Interface Services (SOIS) available at the Execution Platform Layer of the OBSW-RA.

  19. A novel mechanism of ultrathin SOI synthesis by extremely low-energy hot O+ implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Yachida, Gosuke; Inoue, Kodai; Toyohara, Taiga; Nakata, Jyoji

    2016-08-01

    Extremely low-energy oxygen implantations at 10 keV in silicon were challengingly performed to directly synthesize ultrathin silicon-on-insulator (SOI) structure separated by a buried oxide (BOX) layer. We quantitatively investigated the optimum condition and the formation mechanism of homogeneous and continuous stoichiometric SOI/BOX structure. In this study, oxygen ions were implanted into Si(0 0 1) substrates with keeping the temperatures at 500, 800, and 1000 °C with ion-fluences from 0.5 to 2.0× {{10}17} ions cm‑2. These samples were then postannealed at high temperatures from 950 to 1150 °C in Ar ambient for several hours. We found that ultrathin stoichiometric SOI/BOX structure with less than 20 nm thick was synthesized by oxygen implantation with an ion dose of 1.0× {{10}17} ions cm‑2 from 500 °C to 800 °C followed by annealing at a significantly low temperature of 1050 °C for 5 h. According to the RBS-channeling analysis, the crystallinity was excellent as quality as that of the SOI structure formed by a wafer-bonding method. We found that the BOX layer was finally formed around the deeper end of the oxygen distribution in the as-implanted sample, though the depth of the BOX formation was much deeper than the projected range of oxygen and the damage peak of silicon. The formation process of the SOI/BOX structure proposed so far could not be applicable to the present conditions for ultrathin SOI/BOX synthesis by extremely low-energy implantation followed by low-temperature annealing. We thus suggested a novel mechanism of the ultrathin SOI/BOX synthesis as follows. The mechanism during the thermal treatment was demonstrated that the recrystallization of the damaged Si layers induced by ion irradiation took place from the very surface with relatively less irradiation-damages toward deeper layers with sweeping interstitial oxygen atoms, and the condensed oxygen atoms finally synthesized the stoichiometric BOX layer.

  20. Rad-hard vertical JFET switch for the HV-MUX system of the ATLAS upgrade Inner Tracker

    NASA Astrophysics Data System (ADS)

    Fernández-Martínez, P.; Ullán, M.; Flores, D.; Hidalgo, S.; Quirion, D.; Lynn, D.

    2016-01-01

    This work presents a new silicon vertical JFET (V-JFET) device, based on the trenched 3D-detector technology developed at IMB-CNM, to be used as a switch for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The optimization of the device characteristics is performed by 2D and 3D TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. In addition, a set of parameter values has been extracted from the simulated curves to implement a SPICE model of the proposed V-JFET transistor. As these devices are expected to operate under very high radiation conditions during the whole experiment life-time, a study of the radiation damage effects and the expected degradation of the device performance is also presented at the end of the paper.

  1. GSFC Cutting Edge Avionics Technologies for Spacecraft

    NASA Technical Reports Server (NTRS)

    Luers, Philip J.; Culver, Harry L.; Plante, Jeannette

    1998-01-01

    With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

  2. Novel spot size converter for coupling standard single mode fibers to SOI waveguides

    NASA Astrophysics Data System (ADS)

    Sisto, Marco Michele; Fisette, Bruno; Paultre, Jacques-Edmond; Paquet, Alex; Desroches, Yan

    2016-03-01

    We have designed and numerically simulated a novel spot size converter for coupling standard single mode fibers with 10.4μm mode field diameter to 500nm × 220nm SOI waveguides. Simulations based on the eigenmode expansion method show a coupling loss of 0.4dB at 1550nm for the TE mode at perfect alignment. The alignment tolerance on the plane normal to the fiber axis is evaluated at +/-2.2μm for <=1dB excess loss, which is comparable to the alignment tolerance between two butt-coupled standard single mode fibers. The converter is based on a cross-like arrangement of SiOxNy waveguides immersed in a 12μm-thick SiO2 cladding region deposited on top of the SOI chip. The waveguides are designed to collectively support a single degenerate mode for TE and TM polarizations. This guided mode features a large overlap to the LP01 mode of standard telecom fibers. Along the spot size converter length (450μm), the mode is first gradually confined in a single SiOxNy waveguide by tapering its width. Then, the mode is adiabatically coupled to a SOI waveguide underneath the structure through a SOI inverted taper. The shapes of SiOxNy and SOI tapers are optimized to minimize coupling loss and structure length, and to ensure adiabatic mode evolution along the structure, thus improving the design robustness to fabrication process errors. A tolerance analysis based on conservative microfabrication capabilities suggests that coupling loss penalty from fabrication errors can be maintained below 0.3dB. The proposed spot size converter is fully compliant to industry standard microfabrication processes available at INO.

  3. Suppression of 1/f Noise in Accumulation Mode FD-SOI MOSFETs on Si(100) and (110) Surfaces

    SciTech Connect

    Cheng, W.; Gaubert, P.; Teramoto, A.; Tye, C.; Sugawa, S.; Ohmi, T.

    2009-04-23

    In this paper, a new approach to reduce the 1/f noise levels in the MOSFETs on varied silicon orientations, such as Si(100) and (110) surfaces, has been carried out. We focus on the Accumulation-mode (AM) FD-SOI device structure and demonstrate that the 1/f noise levels in this AM FD-SOI MOSFETs are obviously reduced on both the Si(100) and (110) surfaces.

  4. Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

    NASA Astrophysics Data System (ADS)

    Hu, Shengdong; Luo, Jun; Jiang, YuYu; Cheng, Kun; Chen, Yinhui; Jin, Jingjing; Wang, Jian'an; Zhou, Jianlin; Tang, Fang; Zhou, Xichuan; Gan, Ping

    2016-03-01

    A novel SOI LDMOS with a partial compound buried layer structure (P-CBL SOI) is proposed in this paper. The buried oxide layer at the source-side is replaced by a compound buried layer (CBL) of "top oxide-middle polysilicon-bottom oxide", and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS (C-SOI). Firstly, a new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV. Secondly, impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide is thinner than the conventional buried oxide layer, leading to a lower Ron,sp at the on-state and an enhanced vertical BV at the off-state. Finally, thermal conductivity of polysilicon is higher than that of SiO2, offering a lower self-heating effect. The influences of structure parameters on the devices performances are investigated. Compared with those of C-SOI LDMOS on the same top silicon layer of 4 μm, buried dielectric layer of 4 μm, and drift region of 40 μm, BV of P-CBL SOI LDMOS is enhanced by 33.4%, Ron,sp is reduced by 37.4%, and the maximum temperature at the power of 1 mW/μm is depressed by 13.3 K, respectively.

  5. Back gate induced breakdown mechanisms for thin layer SOI field P-channel LDMOS

    NASA Astrophysics Data System (ADS)

    Zhou, Xin; Qiao, Ming; He, Yitao; Yang, Wen; Li, Zhaoji; Zhang, Bo

    2016-01-01

    The back gate (BG) induced breakdown mechanisms for thin layer SOI Field P-channel LDMOS (FPLDMOS) are investigated in this paper. Surface breakdown, bulk breakdown and punch-through breakdown are discussed, revealing that the block capability depends on not drain voltage (Vd), but also BG voltage (VBG). For surface breakdown, the breakdown voltage (BVs) increases linearly with VBG increasing. An expression of BVs on VBG is given, providing a good fitting to measured and simulated results. Bulk breakdown with a low breakdown voltage is attributed to high VBG. VBG induces depletion in n-well, giving rise to punch-through breakdown. A design requirement for the thin layer SOI FPLDMOS is proposed that breakdown voltages for the three breakdown mechanisms are compelled to be higher than the supply voltage of switching IC.

  6. Integration of a UV curable polymer lens and MUMPs structures on a SOI optical bench

    NASA Astrophysics Data System (ADS)

    Hsieh, Jerwei; Hsiao, Sheng-Yi; Lai, Chun-Feng; Fang, Weileun

    2007-08-01

    This work presents the design concept of integrating a polymer lens, poly-Si MUMPs and single-crystal-silicon HARM structures on a SOI wafer to form a silicon optical bench. This approach enables the monolithic integration of various optical components on the wafer so as to improve the design flexibility of the silicon optical bench. Fabrication processes, including surface and bulk micromachining on the SOI wafer, have been established to realize bi-convex spherical polymer lenses with in-plane as well as out-of-plane optical axes. In addition, a micro device consisting of an in-plane polymer lens, a thick fiber holder and a mechanical shutter driven by an electrothermal actuator is also demonstrated using the present approach. In summary, this study significantly improves the design flexibility as well as the functions of SiOBs.

  7. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    NASA Astrophysics Data System (ADS)

    Ryeol Lee, Kang; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-04-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 µm and 30 µm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively.

  8. Electron Pattern Recognition using trigger mode SOI pixel sensor for Advanced Compton Imaging

    NASA Astrophysics Data System (ADS)

    Shimazoe, K.; Yoshihara, Y.; Fairuz, A.; Koyama, A.; Takahashi, H.; Takeda, A.; Tsuru, T.; Arai, Y.

    2016-02-01

    Compton imaging is a useful method for localizing sub MeV to a few MeV gamma-rays and widely used for environmental and medical applications. The direction of recoiled electrons in Compton scattering process provides the additional information to limit the Compton cones and increases the sensitivity in the system. The capability of recoiled electron tracking using trigger-mode Silicon-On-Insulator (SOI) sensor is investigated with various radiation sources. The trigger-mode SOI sensor consists of 144 by 144 active pixels with 30 μm cells and the thickness of sensor is 500 μm. The sensor generates the digital output when it is hit by gamma-rays and 25 by 25 pixel pattern of surrounding the triggered pixel is readout to extract the recoiled electron track. The electron track is successfully observed for 60Co and 137Cs sources, which provides useful information for future electron tracking Compton camera.

  9. Study of novel techniques for reducing self-heating effects in SOI power LDMOS

    NASA Astrophysics Data System (ADS)

    Roig, J.; Flores, D.; Hidalgo, S.; Vellvehi, M.; Rebollo, J.; Millán, J.

    2002-12-01

    Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.

  10. Investigation of the chip to photodetector coupler with subwavelength grating on SOI

    NASA Astrophysics Data System (ADS)

    Li, Hongqiang; Cui, Beibei; Liu, Yu; Liu, Hongwei; Zhang, Zanyun; Zhang, Cheng; Tang, Chunxiao; Li, Enbang

    2016-01-01

    We report on two kinds of investigation of the chip to photodetector coupler (CTPC) with uniform and blazed subwavelength grating (SWG) on silicon-on-insulator (SOI) that were conducted for silicon-based hybrid photodetector integration in an arrayed waveguide grating demodulation integrated microsystem. The theoretical model is presented, 3D FDTD and BPM simulations are used to optimize the coupler design. InP/InGaAs photodetector and SOI wafer were integrated through benzocyclobutene bonding. An efficient high-power absorption for TE mode in a broad band is achieved. The power absorption efficiencies of uniform and blazed SWGs in silicon-based hybrid photodetector integration at 1550 nm reach 73% and 75%, respectively in the simulation and it reaches as high as 25% in the measurement when coupling the TE-polarized 1550 nm light.

  11. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

    PubMed

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-01-01

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

  12. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Navarenho de Souza Fino, Leonardo; Davini Neto, Enrico; Aparecida Guazzelli da Silveira, Marcilei; Renaux, Christian; Flandre, Denis; Pinillos Gimenez, Salvador

    2015-10-01

    This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET bird’s beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.

  13. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    PubMed Central

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-01-01

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

  14. Universal trench design method for a high-voltage SOI trench LDMOS

    NASA Astrophysics Data System (ADS)

    Xiarong, Hu; Bo, Zhang; Xiaorong, Luo; Zhaoji, Li

    2012-07-01

    The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account. The high-k (relative permittivity) dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

  15. Formation of SIMOX-SOI structure by high-temperature oxygen implantation

    NASA Astrophysics Data System (ADS)

    Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

    2015-12-01

    We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 1017-1018 ions/cm2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

  16. Heterogeneously integrated long-wavelength VCSEL using silicon high contrast grating on an SOI substrate.

    PubMed

    Ferrara, James; Yang, Weijian; Zhu, Li; Qiao, Pengfei; Chang-Hasnain, Connie J

    2015-02-01

    We report an electrically pumped hybrid cavity AlGaInAs-silicon long-wavelength VCSEL using a high contrast grating (HCG) reflector on a silicon-on-insulator (SOI) substrate. The VCSEL operates at silicon transparent wavelengths ~1.57 μm with >1 mW CW power outcoupled from the semiconductor DBR, and single-mode operation up to 65 °C. The thermal resistance of our device is measured to be 1.46 K/mW. We demonstrate >2.5 GHz 3-dB direct modulation bandwidth, and show error-free transmission over 2.5 km single mode fiber under 5 Gb/s direct modulation. We show a theoretical design of SOI-HCG serving both as a VCSEL reflector as well as waveguide coupler for an in-plane SOI waveguide, facilitating integration of VCSEL with in-plane silicon photonic circuits. The novel HCG-VCSEL design, which employs scalable flip-chip eutectic bonding, may enable low cost light sources for integrated optical links. PMID:25836117

  17. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  18. Features of SOI substrates heating in MBE growth process obtained by low-coherence tandem interferometry

    NASA Astrophysics Data System (ADS)

    Volkov, P. V.; Goryunov, A.. V.; Lobanov, D. N.; Luk'yanov, A. Yu.; Novikov, A. V.; Tertyshnik, A. D.; Shaleev, M. V.; Yurasov, D. V.

    2016-08-01

    Differences in heating of silicon and silicon-on-insulator (SOI) substrates in molecular beam epitaxy were revealed by low-coherence tandem interferometry. Using this technique the interference effects which impede the correct evaluation of SOI substrate temperature by infrared pyrometers can be eliminated and so the reliable temperature readout can be achieved. It was shown that at the same thermocouple and heater power settings the real temperature of SOI substrates is higher than of silicon ones and the difference may be as high as 40-50 °C at temperatures close to 600 °C. It is supposed that such effect is caused by the additional absorption of heater radiation by the buried oxide layer in the mid-infrared range. Independent proof of this effect was obtained by growing on both types of substrates a series of structures with self-assembled Ge nanoislands whose parameters are known to be very temperature sensitive. The proposed low-coherence interferometry technique provides precise real-time control of the growth temperature and so allows formation of SiGe nanostructures with desired parameters.

  19. Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

    SciTech Connect

    Naumova, O. V. Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P.

    2015-10-15

    The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

  20. Foundry-compatible SOI waveguides with a graphene top layer for wideband wavelength conversion

    NASA Astrophysics Data System (ADS)

    Vermeulen, N.; Cheng, J. L.; Sipe, J. E.; Thienpont, H.

    2016-05-01

    The tremendous progress in the fabrication of highly confining silicon-on-insulator (SOI) waveguides has been very beneficial for four-wave-mixing (FWM)-based wavelength conversion applications. Nevertheless, to establish power-efficient and wideband FWM wavelength conversion, one typically requires long (cm-scale) SOI waveguides with dispersion-engineered cross-sections that do not comply with the fabrication constraints of multiproject- wafer-oriented silicon photonics foundries. In this paper, we numerically examine the opportunities for wideband wavelength conversion through FWM in a foundry-compatible SOI waveguide covered with the highly nonlinear two-dimensional material of graphene. When combining subwatt level pump powers with a short waveguide length of only a few hundreds of microns, perfectly phase-matched conversion with significant efficiencies close to 20 dB can be obtained over a more than 40 THz-wide signal band adjacent to the pump frequency. Because of the tunability of the graphene properties, it is also possible to obtain quasi-phase matched FWM conversion through a periodic sign reversal of the graphene third-order nonlinearity along the waveguide. Conversion efficiencies exceeding 30 dB can be achieved over a 3.4 THz-wide signal band that is situated as much as 58 THz away from the pump frequency. Finally, the graphene tunability also allows for switching between the perfectly phase-matched and quasi-phase-matched operation modes.

  1. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

    NASA Astrophysics Data System (ADS)

    Tianfei, Lei; Xiaorong, Luo; Rui, Ge; Xi, Chen; Yuangang, Wang; Guoliang, Yao; Yongheng, Jiang; Bo, Zhang; Zhaoji, Li

    2011-10-01

    An ultra-low specific on-resistance (Ron, sp) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce Ron, sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a Ron, sp of 51.8 mΩ·mm2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the Ron, sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively.

  2. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    NASA Technical Reports Server (NTRS)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  3. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

    2002-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  4. Differentially piezoresistive transduction of high-Q encapsulated SOI-MEMS resonators with sub-100 nm gaps.

    PubMed

    Li, Cheng-Syun; Li, Ming-Huang; Li, Sheng-Shian

    2015-01-01

    A differentially piezoresistive (piezo-R) readout proposed for single-crystal-silicon (SCS) microelectromechanical systems (MEMS) resonators is implemented in a foundrybased resonator platform, demonstrating effective feedthrough cancellation using just simple piezoresistors from the resonator supports while maximizing their capacitively transduced driving areas. The SCS resonators are fabricated by a CMOS foundry using an SOI-MEMS technology together with a polysilicon refill process. A high electromechanical coupling coefficient is attained by the use of 50-nm transducer gap spacing. Moreover, a vacuum package of the fabricated resonators is carried out through wafer-level bonding process. In this work, the corner supporting beams of the resonator serve not only mechanical supports but also piezoresistors for detecting the motional signal, hence substantially simplifying the overall resonator design to realize the piezo-R sensing. In addition, the fabricated resonators are capable of either capacitive sensing or piezo-R detection under the same capacitive drive. To mitigate feedthrough signals from parasitics, a differential measurement configuration of the piezo-R transduction is implemented in this work, featuring more than 30-dB improvement on the feedthrough level as compared with the single-ended piezo-R counterpart and purely capacitive sensing readout. Furthermore, the high-Q design of the mechanical supports is also investigated, offering Q more than 10 000 with efficient piezo-R transduction for MEMS resonators. PMID:25585404

  5. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

  6. Atomic Precision Donor Devices Fabricated on Strained Silicon on Insulator (sSOI) with SiGe

    NASA Astrophysics Data System (ADS)

    Yitamben, E.; Bussmann, E.; Scrymgeour, D. A.; Rudolph, M.; Carr, S. M.; Ward, D. R.; Carroll, M. S.

    Recently, Si:P donor spin qubits have achieved coherence times (nuclear & e-) that underscore their quantum computing potential. One next major challenge is to integrate donors into a gated structure where electrons can be moved between P, or drawn off of the P to interact, e.g. to an interface as in Kane's proposal. A key constraint is limited thermal budget, to limit P thermal segregation, which precludes typical gate oxidation of Si. We are developing an alternative materials stack utilizing an interfacial barrier layer of relaxed epitaxial SiGe, with donors placed in a strained Si-on-insulator (sSOI) substrate. We fabricate atomic precision donor structures in sSOI via STM hydrogen lithography. Utilizing Si microfabrication and STM in tandem with our Si and Ge molecular beam epitaxy (MBE), we fabricated devices to test our SiGe/sSOI stack concept and atomic-precision fab techniques. To establish our donor-doping capability, we made Hall and Van der Pauw devices in P:sSOI delta-doped layers exhibiting ne >1014/cm2 and mobilities of ~100 cm2/Vs (T =4K) similar to results reported relaxed Si reported elsewhere. Second, we have grown our concept epitaxial SiGe/sSOI stack, evaluated the morphology using STM, and fabricated Hall devices to evaluate low-T transport in our first SiGe/sSOI. Here, we report on these advances in atomic precision donor fab, along with STM analysis our MBE SiGe/sSOI. This work extends STM-based atom precision fab on strained Si toward a vertically gated architecture.

  7. Optimising apodized grating couplers in a pure SOI platform to -0.5 dB coupling efficiency.

    PubMed

    Bozzola, Angelo; Carroll, Lee; Gerace, Dario; Cristiani, Ilaria; Andreani, Lucio Claudio

    2015-06-15

    We present a theoretical optimisation of 1D apodized grating couplers in a "pure" Silicon-On-Insulator (SOI) architecture, i.e. without any bottom reflector element, by means of a general mutative method. We perform a comprehensive 2D Finite Difference Time Domain study of chirped and apodized grating couplers in 220 nm SOI, and demonstrate that the global maximum coupling efficiency in that platform is capped to 65% (-1.9 dB). Moving to designs with thicker Si-layers, we identify a new record design in 340 nm SOI, with a simulated coupling efficiency of 89% (-0.5 dB). Going to thicker Si layers does not further improve the efficiency, implying that -0.5 dB may be a global maximum for a grating coupler in SOI without a bottom-reflector. Even after allowing for 193 nm UV-lithographic fabrication constraints, the 340 nm design still offers -0.7 dB efficiency. These new apodized designs are the first pure SOI couplers compatible with deep-UV lithography to offer better than -1 dB insertion losses. With only very minor changes to existing deposition and lithography recipes, they are compatible with the multi-project wafer runs already offered by Si-Photonics foundries. PMID:26193602

  8. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    NASA Astrophysics Data System (ADS)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  9. Efficient Chemical Sensing by Coupled Slot SOI Waveguides

    PubMed Central

    Passaro, Vittorio M. N.; Dell'Olio, Francesco; Ciminelli, Caterina; Armenise, Mario N.

    2009-01-01

    A guided-wave chemical sensor for the detection of environmental pollutants or biochemical substances has been designed. The sensor is based on an asymmetric directional coupler employing slot optical waveguides. The use of a nanometer guiding structure where optical mode is confined in a low-index region permits a very compact sensor (device area about 1200 μm2) to be realized, having the minimum detectable refractive index change as low as 10-5. Silicon-on-Insulator technology has been assumed in sensor design and a very accurate modelling procedure based on Finite Element Method and Coupled Mode Theory has been pointed out. Sensor design and optimization have allowed a very good trade-off between device length and sensitivity. Expected device sensitivity to glucose concentration change in an aqueous solution is of the order of 0.1 g/L. PMID:22399953

  10. Efficient Chemical Sensing by Coupled Slot SOI Waveguides.

    PubMed

    Passaro, Vittorio M N; Dell'olio, Francesco; Ciminelli, Caterina; Armenise, Mario N

    2009-01-01

    A guided-wave chemical sensor for the detection of environmental pollutants or biochemical substances has been designed. The sensor is based on an asymmetric directional coupler employing slot optical waveguides. The use of a nanometer guiding structure where optical mode is confined in a low-index region permits a very compact sensor (device area about 1200 μm(2)) to be realized, having the minimum detectable refractive index change as low as 10(-5). Silicon-on-Insulator technology has been assumed in sensor design and a very accurate modelling procedure based on Finite Element Method and Coupled Mode Theory has been pointed out. Sensor design and optimization have allowed a very good trade-off between device length and sensitivity. Expected device sensitivity to glucose concentration change in an aqueous solution is of the order of 0.1 g/L. PMID:22399953

  11. Monolithic pixel detectors in silicon on insulator technology

    NASA Astrophysics Data System (ADS)

    Bisello, Dario

    2013-05-01

    Silicon On Insulator (SOI) is becoming an attractive technology to fabricate monolithic pixel detectors. The possibility of using the depleted resistive substrate as a drift collection volume and to connect it by means of vias through the buried oxide to the pixel electronic makes this kind of approach interesting both for particle and photon detection. In this paper I report the results obtained in the development of monolithic pixel detectors in an SOI technology by a collaboration between groups from the University and INFN of Padova (Italy) and the LBNL and the SCIPP at UCSC (USA).

  12. New Insights into Fully-Depleted SOI Transistor Response During Total-Dose Irradiation

    SciTech Connect

    BURNS,J.A.; DODD,PAUL E.; KEAST,C.L.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; WYATT,P.W.

    1999-09-14

    Previous work showed the possible existence of a total-dose latch effect in fully-depleted SOI transistors that could severely limit the radiation hardness of SOI devices. Other work showed that worst-case bias configuration during irradiation was the transmission gate bias configuration. In this work we further explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10-keV x rays. Our results show no evidence for a total-dose latch effect as proposed by others. Instead, in absence of parasitic trench sidewall leakage, our data suggests that the increase in radiation-induced leakage current is caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current is amplified to considerably higher levels by impact ionization. Because the back-channel interface is in weak inversion, the top-gate bias can modulate the back-channel interface and turn the leakage current off at large, negative voltage levels. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. However, it is likely that this current also is amplified by impact ionization. For these transistors, the worst-case bias configuration was determined to be the ''ON'' bias configuration. These results have important implication on hardness assurance.

  13. Vertical-coupled high-efficiency tunable III-V- CMOS SOI hybrid external-cavity laser.

    PubMed

    Lin, Shiyun; Djordjevic, Stevan S; Cunningham, John E; Shubin, Ivan; Luo, Ying; Yao, Jin; Li, Guoliang; Thacker, Hiren; Lee, Jin-Hyoung; Raj, Kannan; Zheng, Xuezhe; Krishnamoorthy, Ashok V

    2013-12-30

    We demonstrate a hybrid III-V/SOI laser by vertically coupling a III-V RSOA chip with a SOI-CMOS chip containing a tunable wavelength selective reflector. We report a waveguide-coupled wall-plug-efficiency of 5.5% and output power of 10 mW. A silicon resistor-based microheater was integrated to thermally tune a ring resonator for precise lasing wavelength control. A high tuning efficiency of 2.2 nm/mW over a range of 18 nm was achieved by locally removing the SOI handler substrate. C-band single mode lasing was confirmed with a side mode suppression ratio of 35 dB. This grating coupler based vertical integration approach can be scaled up in two dimensions for efficient multi-wavelength sources in silicon photonics. PMID:24514836

  14. A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter

    NASA Astrophysics Data System (ADS)

    Mitra, Suman Kr.; Goswami, Rupam; Bhowmick, Brinda

    2016-04-01

    A Silicon based two dimensional (2D) hetero-dielectric stack gate SOI Tunneling Field Effect Transistor (SOI-TFET) with back-gate is proposed. Simulation results show that the proposed structure can be scaled down without affecting Subthreshold Swing unlike conventional TFETs with SiO2 as gate dielectric. On state of the device is independent of back-gate voltage unlike MOSFETs. The effects of gate lengths, lengths of high-k dielectric in lower stack (L) and back-gate voltages on the threshold voltage, Ion/Ioff and Subthreshold Swing (SS) of the SOI-TFET are analyzed. Capacitance components CGG, CGD, CGS are also observed and device shows good performance as an inverter. The fall time, overshoot and undershoot are not above 27 fs, 1.712% and 0.77% respectively considering mixed mode device and circuit simulation of capacitive loaded inverter.

  15. XeF2 vapor phase silicon etch used in the fabrication of movable SOI structures.

    SciTech Connect

    Wiwi, M.; Sanchez, Carlos Anthony; Plut, Thomas Alvin; Salazar, M.; Stevens, Jeffrey; Bauer, Todd M.; Ford, C.; Shul, Randy John; Grossetete, Grant David

    2010-10-01

    Vapor phase XeF{sub 2} has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF{sub 2} Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF{sub 2} vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO{sub 2}) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF{sub 2} etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO{sub 2}. The buried SiO{sub 2} was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO{sub 2}. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO{sub 2} was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF{sub 2} was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF{sub 2} due to protection from the top SiO{sub 2} mask, sidewall passivation, and the buried SiO{sub 2} layer. Optimization of the XeF{sub 2

  16. Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures

    NASA Astrophysics Data System (ADS)

    Novo, C.; Giacomini, R.; Doria, R.; Afzalian, A.; Flandre, D.

    2014-07-01

    This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation mode and under high temperatures of operation, independently of the anode voltage. The obtained results show that the doping concentration of the intrinsic region has influence on the sensitivity of the diodes: the larger the doping concentration, the smaller the IDR. Furthermore, the photocurrent and dark current present lower values as the silicon film thickness is decreased, resulting in a further increase in the illuminated to dark ratio.

  17. Improvement of radiation hardness in fully-depleted SOI n-MOSFETs using Ge-implantation

    SciTech Connect

    Wei, H.F.; Chung, J.E. . Dept. of Electrical Engineering and Computer Science); Kalkhoran, N.M.; Namavar, F. ); Annamalai, N.K.; Shedd, W.M. )

    1994-12-01

    This work demonstrates a well-controlled technique of channel defect engineering by implanting germanium into the channel of a Silicon-On-Insulator (SOI) MOSFET to generate subgap energy states. These subgap states act as minority-carrier lifetime killers to reduce parasitic bipolar effects. The Ge-implant also serves the dual purpose of positioning most of the subgap states in the back interface region which retard the total dose responses of off-state leakage and front-channel threshold voltage.

  18. Design and characterization of low loss 50 picoseconds delay line on SOI platform.

    PubMed

    Xiao, Zhe; Luo, Xianshu; Liow, Tsung-Yang; Lim, Peng Huei; Prabhathan, Patinharekandy; Zhang, Jing; Luan, Feng

    2013-09-01

    We design and experimentally demonstrate 50 picoseconds (ps) low loss delay line on 300 nm SOI platform. The delay line unit consists of straight rib waveguide and strip bend section linked by a transition taper waveguide. Low propagation loss of ~0.1 dB/cm is achieved on the straight rib waveguide. With taking into account both low loss and desirable delay, a complete design and characterization process for passive delay line is presented. Our measurement results show that about 0.7 dB excess loss is achievable for 50 ps delay. The loss can be further reduced by adjusting the layout parameters. PMID:24104002

  19. Trigger voltage walk-out phenomenon in SOI lateral insulated gate bipolar transistor under repetitive electrostatic discharge stresses

    NASA Astrophysics Data System (ADS)

    Zhang, Shifeng; Han, Yan; Ma, Fei

    2016-05-01

    Trigger voltage walk-out phenomenon is found in SOI LIGBT's under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.

  20. High LET Single Event Upset Cross Sections For Bulk and SOI CMOS SRAMs

    SciTech Connect

    McDaniel, F.D.; Doyle, B.L.; Vizkelethy, G.; Dodd, P.E.; Rossi, P.

    2003-08-26

    Electronics in spacecraft and satellites are exposed to high-energy cosmic radiation. In addition, terrestrial radiation can also affect earth-based electronics. To study the effects of radiation upon integrated circuits and to insure the reliability of electronic devices, cosmic and terrestrial radiations are simulated with ion beams from particle accelerators. A new, higher Linear Energy Transfer (LET) acceleration system for heavy ions has been developed at Sandia National Laboratories. Heavy ions from a 6.5 MV EN tandem Van de Graaff accelerator at 0.25 MeV/amu are injected into a two-stage Radio Frequency Quadrupole (RFQ) linac, which accelerates the ions to 1.9 MeV/amu. These ions together with those from the Brookhaven National Laboratory MP Tandem have been used to measure single event upset (SEU) cross sections as a function of LET for both bulk and Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor, Static Random Access Memories. The magnitudes of these cross sections indicate that the upsets in both the SOI and bulk parts are caused by OFF-drain strikes.

  1. AlN-on-SOI platform-based micro-machined hydrophone

    NASA Astrophysics Data System (ADS)

    Xu, Jinghui; Zhang, Xiaolin; Fernando, Sanchitha N.; Chai, Kevin Tshunchuan; Gu, Yuandong

    2016-07-01

    This paper reports a piezoelectric aluminum nitride (AlN) based micro-machined infrasonic hydrophone. We have conducted a systematic design study for the hydrophone sensor to meet the stringent requirements of underwater applications. The hydrophone sensor was fabricated on a cavity silicon-on-insulator (SOI) substrate using an in-house CMOS-compatible AlN-on-SOI process platform. A 5 × 5 arrayed hydrophone sensor was characterized thoroughly using an industry-standard hydrophone calibration instrument. The results show that the hydrophone achieved a sound sensitivity of -182.5 dB ± 0.3 dB (ref. to 1 V rms/μPa) and an eligible acceleration sensitivity of only -196.5 dB (ref. to 1 V rms/μg), respectively, a non-linearity of 0.11%, a noise resolution of 57.5 dB referenced to 1 μPa/√Hz within an ultra-low operation bandwidth of 10 Hz˜100 Hz, the highest noise resolution of micro-machined hydrophones reported to date, and better than traditional bulky hydrophones in terms of the same application. The size of the 5 × 5 arrayed hydrophone sensor is about 2 mm × 2 mm.

  2. Impact of technology scaling on analog and RF performance of SOI-TFET

    NASA Astrophysics Data System (ADS)

    Kumari, P.; Dash, S.; Mishra, G. P.

    2015-12-01

    This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD sentaurus device simulation results.

  3. Implementation of a gap-closing differential capacitive sensing Z-axis accelerometer on an SOI wafer

    NASA Astrophysics Data System (ADS)

    Hsu, Chia-Pao; Yip, Ming-Chuen; Fang, Weileun

    2009-07-01

    This study presents a novel capacitive-type Z-axis (out-of-plane) accelerometer implemented on an SOI wafer. This accelerometer contains special designed gap-closing differential sensing electrodes. The present Z-axis accelerometer has four merits: (1) mass of the proof mass is increased by combining both device and handle silicon layers of the SOI wafer, (2) the sensitivity is improved by the gap-closing differential electrodes design, (3) the electrical interconnection between the device and handle silicon layers of the SOI wafer is available by means of the metal-vias, and (4) the sensing gap thickness is precisely defined by the buried-oxide layer of the SOI wafer. In application, the Z-axis accelerometer is fabricated and characterized. Typical measurement results demonstrate that the presented Z-axis accelerometer has a sensitivity of 196.3 mV G-1 (42.5 fF G-1) and a maximum nonlinearity of 2% over the range of 0.1-1 G.

  4. SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Almad

    2009-01-01

    Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80

  5. Prediction of coronal and heliospheric magnetic fields: The promise of SOI-MDI on SOHO

    NASA Technical Reports Server (NTRS)

    Hoeksema, J. T.; Zhao, X. P.; Scherrer, P. H.

    1995-01-01

    Models of the coronal magnetic field have been developed over the years that reproduce the static characteristics of coronal and heliospheric structures fairly well. Limitations of spatial and temporal resolution and nonuniform quality of the input data have made it particularly difficult to investigate the response of the corona to rapidly changing photospheric conditions. The Solar Oscillations Investigation (SOI) experiment on SOHO, scheduled for launch late in 1995, will produce a series of full-disk photospheric magnetic field observations with 4" resolution about every 2 hours for the next several years. Higher resolution observations of the center of the disk will be available several times per day. These data should provide a basis for predicting the coronal and heliospheric field and their changes with unprecedented accuracy during the rising phase of Solar Cycle 23.

  6. Ultra-compact broadband nanowire-to-slot waveguide mode converter based on SOI

    NASA Astrophysics Data System (ADS)

    Qi, Ying; An, Junming; Wang, Yue; Zhang, Xiaoguang

    2014-11-01

    A novel ultra-compact high-efficiency broadband mode converter between silicon (Si) nanowire and silicon slot waveguide based on Silicon-on-Insulator (SOI) is proposed in this paper. By introducing a gradual-width structure between Si nanowire and slot waveguide, the favorable transition between nanowire mode (Gaussian-like mode) and slot mode (non-Gaussian-like mode) can be obtained and then the coupling efficiency is improved. The structure is simulated and optimized by using the three-dimension Finite-Difference Time-Domain Method (3D-FDTD). The coupling efficiency of over 90% within bandwidth of over 600nm can be achieved by only 200nm-length converter which is the smallest size to our knowledge. This presented mode converter can meet the demand of ultra-compact, wavelength-insensitive of monolithic integration.

  7. Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications

    NASA Astrophysics Data System (ADS)

    Receveur, Rogier A. M.; Zickar, Michael; Marxer, Cornel; Larik, Vincent; de Rooij, Nicolaas F.

    2006-04-01

    We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine/gross leak test after thermal cycling and mechanical shock/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is 114 ± 26 N in correspondence with the theoretically expected 100 N. Ruthenium microcontacts are a factor of 100 more robust than gold microcontacts, being stable over 106 cycles measured in a N2 atmosphere inside the package presented here. Future work will include a more extensive bond quality assessment and continued microcontact reliability measurements.

  8. MONOLITHIC ACTIVE PIXEL MATRIX WITH BINARY COUNTERS IN AN SOI PROCESS.

    SciTech Connect

    DUPTUCH,G.; YAREMA, R.

    2007-06-07

    The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}.

  9. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2005-01-01

    Work on the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings was carried out primarily in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife). This ongoing collaboration produced new results for the inversion of the internal solar rotation rate and further development in inversion methodologies. It also resulted in inferences on the solar stratification. Substantial progress towards the characterization of high-degree p-modes has been achieved. In collaboration with Drs. Rabello-Soares and Schou (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This work has precise implications on the properties and the characterization of the HMI instrument being developed for the SDO mission.

  10. Increase in the scattering of electric field lines in a new high voltage SOI MESFET

    NASA Astrophysics Data System (ADS)

    Anvarifard, Mohammad K.

    2016-09-01

    This paper illustrates a new efficient technique to enhance the critical features of a silicon-on-insulator metal-semiconductor field-effect transistor (SOI MESFET) applied in high voltage applications. The structure we proposed utilizes a new method to scatter the electric field lines along the channel region. Realization of two trenches with different materials, which a trench is created in the channel region and the other one is created in the buried oxide, helps the proposed structure to improve the breakdown voltage, driving current, drain-source conductance, minimum noise figure, unilateral power gain and output power density. Exploring the obtained results, the proposed structure has superior electrical performance in comparison to the conventional structure.

  11. Novel adiabatic tapered couplers for active III-V/SOI devices fabricated through transfer printing.

    PubMed

    Dhoore, Sören; Uvin, Sarah; Van Thourhout, Dries; Morthier, Geert; Roelkens, Gunther

    2016-06-13

    We present the design of two novel adiabatic tapered coupling structures that allow efficient and alignment tolerant mode conversion between a III-V membrane waveguide and a single-mode SOI waveguide in active heterogeneously integrated devices. Both proposed couplers employ a broad intermediate waveguide to facilitate highly alignment tolerant coupling. This robustness is needed to comply with the current misalignment tolerance requirements for high-throughput transfer printing. The proposed coupling structures are expected to pave the way for transfer-printing-based heterogeneous integration of active III-V devices such as semiconductor optical amplifiers (SOAs), photodetectors, electro-absorption modulators (EAMs) and single wavelength lasers on silicon photonic integrated circuits. PMID:27410317

  12. SOI-Diode TEC-less Uncooled Infrared Micro-camera

    NASA Astrophysics Data System (ADS)

    Kibe, Michiya; Nagashima, Mitsuhiro; Doshida, Minoru; Kama, Keisuke; Ohnakado, Takahiro

    This paper describes an uncooled infrared (IR) camera especially optimized for small size & weight, less power consumption without degrading noise equivalent temperature difference (NETD). This camera has two features, including a wafer-level chip scale vacuum package with 160x120 SOI-diode array and germanium lid for good IR transmission, and also a real-time signal correction capability with respect to ambient temperature. These features enabled the considerable size/power consumption reduction and the operation without thermoelectric cooler (TEC) which usual IR cameras require for temperature stabilization. As a result, we realized compact infrared camera (less than 71grams) with low-power consumption and excellent NETD of 22 mK (F/0.8 optics).

  13. Impact of gate workfunction in junctionless versus junction SOI n-MOSFET transistor

    NASA Astrophysics Data System (ADS)

    Huda, A. R. N.; Arshad, M. K. Md.; Othman, Noraini; Voon, C. H.; Liu, Wei-Wen; Hashim, U.; Lee, H. Cheun; Adelyn, P. Y. P.; Kahar, S. M.

    2016-07-01

    In this paper, the effect of gate workfunction variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on/off-current ratio, subthreshold voltage, and drain-induced-barrier-lowering are the main parameters that have been investigated. The rate of change in VTH with the respect to gate workfunction for both JLT and JT devices was almost same. Besides that, it shows the designated JLT device is achieving full-depletion at higher gate workfunction of more than 5.0 eV whereas the designated JT device is more wider range, ranging from low, mid-gap or high workfunction.

  14. Worst case total dose radiation response of 0.35 {micro}m SOI CMOSFETs

    SciTech Connect

    Liu, S.T.; Balster, S.; Sinha, S.; Jenkins, W.C.

    1999-12-01

    Through experimental results and analysis by TSUPREM4/MEDICI simulations, the worst case back gate total dose bias condition is established for body tied SOI NMOSFETs. Utilizing the worst-case bias condition, a recently proposed model that describes the back n-channel threshold voltage shift as a function of total dose, TSUPREM4/MEDICI simulations, and circuit level SPICE simulations, a methodology to model post-rad standby current is developed and presented. This methodology requires the extraction of fundamental starting material/material preparation constants, and then can be utilized to examine post-rad stand-by current at the device and circuit level as function of total dose. Good agreement between experimental results and simulations is demonstrated.

  15. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    NASA Astrophysics Data System (ADS)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  16. Analytical two-dimensional modeling for potential distribution and threshold voltage of the short-channel fully depleted SOI (silicon-on-insulator) MOSFET

    NASA Astrophysics Data System (ADS)

    Aggarwal, Vaneeta; Khanna, Manoj K.; Sood, Rachna; Haldar, Subhasis; Gupta, R. S.

    1994-08-01

    A two-dimensional analytical model for fully depleted SOI MOSFETs is presented. An extensive study of potential distribution in the silicon film is carried out for non-uniform doping distribution and extended to find an expression for threshold voltage in the sub micrometer region. The results so obtained are verified with experimental data. The present model calculates a critical gate voltage (for short channel fully depleted SOI devices) beyond which gate losses its control on drain current. The advantages of SOI MOSFETs over the bulk counterparts are explained on the basis of drain induced barrier lowering [DIBL]. It is also shown that the threshold voltage for the thin film SOI MOSFET is less than that of bulk MOSFET. The short-channel effects, DIBL and threshold voltage reduction, are well predicted in the present model.

  17. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  18. SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting.

    PubMed

    Du, Wei; Inokawa, Hiroshi; Satoh, Hiroaki; Ono, Atsushi

    2011-08-01

    In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved. PMID:21808317

  19. Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

    NASA Astrophysics Data System (ADS)

    de Souza, Michelly; Flandre, Denis; Pavanello, Marcelo Antonio

    2009-11-01

    This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures.

  20. 28 Gb/s direct modulation heterogeneously integrated C-band InP/SOI DFB laser.

    PubMed

    Abbasi, Amin; Verbist, Jochem; Van Kerrebrouck, Joris; Lelarge, Francois; Duan, Guang-Hua; Yin, Xin; Bauwelinck, Johan; Roelkens, Gunther; Morthier, Geert

    2015-10-01

    We demonstrate direct modulation of a heterogeneously integrated C-band DFB laser on SOI at 28 Gb/s with a 2 dB extinction ratio. This is the highest direct modulation bitrate so far reported for a membrane laser coupled to an SOI waveguide. The laser operates single mode with 6 mW output power at 100 mA bias current. The 3 dB modulation bandwidth is 15 GHz. Transmission experiments using a 2 km non zero dispersion shifted single mode fiber were performed at 28 Gb/s bitrate using a 2(7)-1 NRZ-PRBS pattern resulting in a 1 dB power penalty. PMID:26480161

  1. Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

  2. Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

    NASA Astrophysics Data System (ADS)

    Qiao, Ming; Wang, Yuru; Li, Yanfei; Zhang, Bo; Li, Zhaoji

    2014-11-01

    A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80 μm, the NBL PSOI LDMOS obtains a high BV of 1243 V which is improved by around 105 V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333 K at a power (P) of 1 mW/μm which is reduced by around 61 K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

  3. A Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for Deep Sub-0.1-μm Channel Regime

    NASA Astrophysics Data System (ADS)

    Yanagi, Shin-ichiro; Nakakubo, Atsushi; Omura, Yasuhisa

    2001-04-01

    Silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) offers a number of advantages over conventional bulk silicon transistors. In this paper, we present a new SOI device structure called a “partial-ground-plane” SOI MOSFET down to 50 nm channel length. This new device shows good suppression of short-channel effect together with a small subthreshold swing and has a good driveability with a low leakage current.

  4. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

    PubMed

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-11-17

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < -17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

  5. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper

    PubMed Central

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-01-01

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM0 mode into the TE1 mode, which will output as the TE0 mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < −17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

  6. A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric

    NASA Astrophysics Data System (ADS)

    Gopi Krishna, Saramekala; Sarvesh, Dubey; Pramod, Kumar Tiwari

    2015-10-01

    In this paper, a surface potential based threshold voltage model of fully-depleted (FD) recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional (2D) Poisson’s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model’s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters, including the dielectric constant of gate-dielectric material. The author, Pramod Kumar Tiwari, was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology, Ministry of Human Resource and Development, Government of India under Young Scientist Research (Grant No. SB/FTP/ETA-415/2012).

  7. SOI waveguide fabrication process development using star coupler scattering loss measurements

    NASA Astrophysics Data System (ADS)

    Yap, K. P.; Lapointe, J.; Lamontagne, B.; Delâge, A.; Bogdanov, A.; Janz, S.; Syrett, B.

    2007-12-01

    We show that integrated optical star couplers can be useful characterization devices to measure the sidewall roughness-induced scattering losses of planar waveguides. We describe the detailed fabrication processes of these star couplers on the silicon-on-insulator (SOI) platform and the process improvements implemented to reduce the waveguide sidewall roughness and scattering loss. We report the main process challenges, particularly to assure a clear gap between any adjacent waveguides of the dense and closely spaced output waveguide array. These challenges are addressed by optimizing the exposure dose of the resist and adding an oxygen ashing treatment to eliminate waveguide footings. We demonstrate further improvement on the waveguide profile and sidewall roughness through the use of a thin Cr hardmask for the dry plasma etching. This optimized fabrication process is capable of producing approximately a 3 nm root-mean-square sidewall roughness, measured using both scanning electron microscopy (SEM) and atomic force microscopy (AFM). Using the fabricated star couplers, we manage to measure the relative scattering losses of various waveguides with the width varying from 0.2 to 2.0 μm in a single measurement, and show that the measured losses agree with the measured sidewall roughness.

  8. Compact add-and-drop and wavelength filter based on microdisk on SOI substrate

    NASA Astrophysics Data System (ADS)

    Morand, Alain; Phan-Huy, Kien; Martin, Bruno; Bredillot, Fanny; Amans, David; Benech, Pierre; Verbert, Jérémy; Hadji, Emmanuel; Fedeli, Jean-Marc

    2006-02-01

    Recently, integrated optic applications on SOI substrate like add-and-drop structures or wavelength filters based on microdisk resonators have been investigated by many research groups. Microdisks exhibiting high quality-factor thanks to the high refractive index contrast between silica and silicon materials have been already reported. However efficient components usually show few micrometers diameter which is huge compared to photonic crystals ones. In this paper, realization and characterization of efficient and compact components are reported. The dropped-wavelength function, composed of a 1.5 μm radius disk and 0.3 μm x 0.3 μm square section waveguides is demonstrated. 22 dB extinction ratio is measured from spectral measurement while keeping a quality factor of 1000. In this structure, the distance between the microdisk and the waveguide is discussed from experimental point of view. Indeed, the efficiency of the add-and-drop strongly depends on this parameter. Moreover, a wavelength filter based on a 4 μm radius microdisk is also shown. Quality-factors of 92,900 +/- 5500 were measured showing that these filters are more efficient than equivalent microring filters. A 10 dB extinction ratio of the wavelength rejected signal is reported. For some resonance wavelengths, spectral response degeneracy of the filter appears. An explanation of this effect is given in this paper.

  9. Nanopore patterning using Al2O3 hard masks on SOI substrates

    NASA Astrophysics Data System (ADS)

    Wang, Xiaofeng; Goryll, Michael

    2015-07-01

    Aluminum oxide Al2O3, deposited using amorphous atomic layer deposition (ALD), is a very promising material to be utilized as a hard mask for nano-patterning. We used an aluminum oxide hard mask on a silicon-on-insulator (SOI) substrate to implement a sub-100 nm nanopore process. The transfer of nanoscale patterns via dry etching of the Al2O3 thin film was investigated by comparing etch profiles, etch rates, and selectivity of Al2O3 over PMMA resist, using different gas chemistries such as Cl2, Ar, Ar/BCl3 mixtures, and BCl3 plasma. A selectivity of 1:4 was observed using an inductively coupled plasma reactive ion etching (ICP-RIE) tool with BCl3 plasma, and the sub-100 nm nanopore patterns were anisotropically transferred to the alumina layer from a 250 nm PMMA layer. The dense and inert Al2O3 hard mask showed exceptional etch selectivity to Si and SiO2, which allowed the subsequent transfer of the nanopore patterns into the 340 nm-thick Si device layer and made it possible to attempt etching the 1 μm-thick buried oxide (BOX) layer. Using chlorine chemistry, nanopores patterned in the Si device layer showed excellent anisotropy while preserving the original pattern dimensions. The process demonstrated is ideally suited for patterning high aspect ratio nanofluidic structures.

  10. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    SciTech Connect

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-04-24

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  11. Electrical detection of amine ligation to a metalloporphyrin via a hybrid SOI-MOSFET.

    PubMed

    Takulapalli, Bharath R; Laws, Gez M; Liddell, Paul A; Andréasson, Joakim; Erno, Zach; Gust, Devens; Thornton, Trevor J

    2008-02-20

    A close-packed monolayer of zinc 5,10,15,20-tetrakis(3-carboxyphenyl)porphyrin has been prepared and deposited on the thin native oxide covering the surface of an SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor field effect transistor) using Langmuir-Blodgett techniques. When the device is exposed to amine vapors in a nitrogen atmosphere, the amine coordinates to the zinc atom. The resulting change in electron distribution within the porphyrin leads to a large change in the drain current of the transistor, biased via a back gate. This change is sensitive to both the amount of amine present and the base strength of the amine. Only very small changes in drain current were observed with a monolayer of free base porphyrin or palmitic acid. After exposure to high pyridine concentrations, the device response saturates, but partially recovers after overnight exposure to flowing nitrogen gas. Interestingly, the device response is instantaneously reset by exposure to visible light, suggesting that photode-ligation occurs. An electrical model for the hybrid device that describes its response to ligand binding in terms of a change in the work function of the porphyrin monolayer has been developed. A transistor response to a few hundred attomoles of bound pyridine can be readily detected. This extreme sensitivity, coupled with the ability to reset the device using light, suggests that such systems might be useful as sensors. PMID:18225896

  12. Line-edge roughness induced single event transient variation in SOI FinFETs

    NASA Astrophysics Data System (ADS)

    Weikang, Wu; Xia, An; Xiaobo, Jiang; Yehua, Chen; Jingjing, Liu; Xing, Zhang; Ru, Huang

    2015-11-01

    The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (Vgs = 0, Vds = Vdd) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

  13. Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

    NASA Astrophysics Data System (ADS)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

    2016-09-01

    In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

  14. On the feasibility of superjunction thick-SOI power LDMOS transistors for RF base station applications

    NASA Astrophysics Data System (ADS)

    Cortes, I.; Roig, J.; Flores, D.; Hidalgo, S.; Rebollo, J.

    2007-02-01

    The feasibility of applying the superjunction (SJ) concept to a thick-SOI LDMOS transistor for base station applications is studied in this paper. An extensive comparison with conventional RF LDMOS structures is performed in terms of breakdown voltage (VBR) versus drift resistance (Rdr) values. Unlike conventional LDMOS structures, the Rdr value in SJ LDMOS structures not only depends on the doping concentration but especially on the characteristics of P and N pillars. The charge compensation due to inter-diffusion between adjacent pillars is responsible for the observed Rdr increase. In order to accomplish an optimum pillar formation with the minimum possible transition between P and N pillars with inherent net doping reduction, high energy multi-implantations and a small thermal budget must be used. Moreover, the distance between P and N pillar implantation windows must be properly set to alleviate the doping inter-diffusion effect. The VBR/Rdr ratio value is a good indicator to evaluate the SJ LDMOS feasibility for RF applications.

  15. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    NASA Astrophysics Data System (ADS)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-04-01

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (˜ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and - 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10-9 of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  16. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    SciTech Connect

    Trimpl, M.; Deptuch, G.; Yarema, R.; /Fermilab

    2010-11-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm{sup 2} large detector array with 20 {micro}m and 40 {micro}m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  17. A 32-site neural recording probe fabricated by DRIE of SOI substrates

    NASA Astrophysics Data System (ADS)

    Norlin, Peter; Kindlundh, Maria; Mouroux, Aliette; Yoshida, Ken; Hofmann, Ulrich G.

    2002-07-01

    An all-dry silicon-etch based micromachining process for neural probes was demonstrated in the manufacture of a probe with a 32-site recording electrode array. The fork-like probe shafts were formed by double-sided deep reactive ion etching (DRIE) of a silicon-on-insulator (SOI) substrate, with the buried SiO2 layer acting as an etch stop. The shafts typically had the dimensions 5 mm × 25 μm × 20 μm and ended in chisel-shaped tips with lateral taper angles of 4°. An array of Ir electrodes, each 100 μm2, and Au conductor traces were formed on top of the shafts by e-beam evaporation. An accompanying interconnect solution based on flexible printed circuitry was designed, enabling precise and flexible positioning of the probes in neural tissue. SEM studies showed sharply defined probes and probe tips. The electrical yield and function were verified in bench-top measurements in saline. The magnitude of the electrode impedance was in the 1 MΩ range at 1 kHz, which is consistent with neurophysiological recordings.

  18. Low-loss delay lines with small footprint on a micron-scale SOI platform

    NASA Astrophysics Data System (ADS)

    Cherchi, Matteo; Harjanne, Mikko; Vyrsokinos, Konstantinos; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani; Aalto, Timo

    2015-02-01

    Long and yet compact spiral waveguides based on micron-scale silicon strip waveguides has been enabled very recently by the introduction of the Euler bends. By ensuring effective broadband single mode operation of otherwise highly multimodal waveguides, these bends can have very low losses (<0.01 dB/90°) even with effective radii of a few microns. Together with the low propagation losses (< 0.15 dB/cm) of micron-scale strip waveguides, these bends enable centimeter-long delay lines with negligible losses and very small foot-print (< 1 mm2). In particular, interferometers delayed by ≈ 1 cm long spirals on one of the two arms have been fabricated on SOI wafers with both 3 um- and 4 umthick silicon layer, based on the well assessed process developed by VTT. The full devices have footprint smaller than 1.5 mm2, and they have been measured to have extinction ratios < 15 dB (reaching up to 21 dB) and about 3 dB excess losses. Functional characterization of the delayed interferometers at about 10 Gbps through demodulation of pseudorandom Differential Phase Shift Keying signals led to clearly opened eye diagrams with Q factor of 8.6 and bit error rates lower than 10-15.

  19. A low specific on-resistance SOI LDMOS with a novel junction field plate

    NASA Astrophysics Data System (ADS)

    Luo, Yin-Chun; Luo, Xiao-Rong; Hu, Gang-Yi; Fan, Yuan-Hang; Li, Peng-Cheng; Wei, Jie; Tan, Qiao; Zhang, Bo

    2014-07-01

    A low specific on-resistance SOI LDMOS with a novel junction field plate (JFP) is proposed and investigated theoretically. The most significant feature of the JFP LDMOS is a PP—N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buried oxide layer (BOX) and thus widens the vertical conduction area. As a result, the breakdown voltage (BV) is improved and the specific on-resistance (Ron,sp) is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ·cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

  20. Sub-wavelength grating components for integrated optics applications on SOI chips.

    PubMed

    Donzella, Valentina; Sherwali, Ahmed; Flueckiger, Jonas; Talebi Fard, Sahba; Grist, Samantha M; Chrostowski, Lukas

    2014-08-25

    In this paper we demonstrate silicon on insulator (SOI) sub-wavelength grating (SWG) optical components for integrated optics and sensing. Light propagation in SWG devices is studied and realized with no cladding on top of the waveguide. In particular, we focused on SWG bends, tapers and directional couplers, all realized with compatible geometries in order to be used as building blocks for more complex integrated optics devices (interferometers, switches, resonators, etc.). Fabricated SWG tapers for TE and TM polarizations are described; they allow for connecting SWG devices to regular strip waveguides with loss lower than 1 dB per taper. Our SWG directional coupler presents a very compact design and a negligible wavelength dependence of its crossover length (and as a consequence of its coupling coefficient, κ), over a 40 nm bandwidth. This wavelength flatten response represents a bandwidth enhancement with respect to standard directional couplers (made using strip or rib waveguides), in particular for the TE mode. SWG bends are demonstrated, their loss dependence on radius is analyzed, and fabricated bends have a loss in the range 0.8-1.6 dB per 90 degrees bend. Simulated and measured results show promise for large-scale fabrication of complex optical devices and high sensitivity sensors based on SWG waveguides with engineered optical properties, tailored to specific applications. PMID:25321304

  1. Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

    PubMed

    Takulapalli, Bharath R

    2010-02-23

    Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory. PMID:20085285

  2. Global and Local Helioseismic Studies of Solar Convection Zone Dynamics Using SOI-MDI on SOHO

    NASA Technical Reports Server (NTRS)

    Toomre, Juri; Haber, Deborah; Hindman, Bradley; Christensen-Dalsgaard, Joergen; Gough, Douglas; Thompson, Michael

    2003-01-01

    Our joint collaborative analyses of global mode data to characterize the solar differential rotation (e.g. Thompson et al. 1996, Schou et al. 1998), and most recently to detect and analyze temporal variations in angular velocity Omega profiles both within the convection zone and in the deeper radiative interior (e.g. Howe et al 2000a,b; Toomre et al. 2000), have led to a series of fascinating discoveries. These should be pursued further as the solar cycle continues. The physical deductions being made from these studies have been greatly strengthened by utilizing both SOI-MDI and GONG data in order to have two independent observational realizations of Doppler images spanning a five-year interval, using two separate procedures to determine global mode splittings, and then analyzing those splitting data sets using both RLS and SOLA inversion procedures. There are considerable subtleties in the effects of instrumental response functions and calibrations, sensitivity of peak finding algorithms and their mode leakage estimates, and stochastic variations in mode amplitudes that can all contribute to apparent changes in the Omega profiles being inferred from sequences of helioseismic data. We have come to understand the implications of many of these calibration and analysis steps, greatly aided by frequent multi-week collaborative working sessions in our Helioseismic Analysis Facility (HAF) at JILA involving many members of the SO1 dynamics and inversion team, including most of our Co-Is during the summer months when we hold intensive working sessions. Considerable further focused attention is required in a collaborative setting on such global mode issues as we continue studying the changing sun.

  3. Seismic Study of the Solar Interior: Inferences from SOI/MDI Observations During Solar Activity

    NASA Technical Reports Server (NTRS)

    Korzennik, Sylvain G.; Wagner, William J. (Technical Monitor)

    2001-01-01

    We have continued in collaboration with Dr. Eff-Darwich (University of La Laguna, Tenerife, Spain) the study of the structure, asphericity and dynamics of the solar interior from p-mode frequencies and frequency splittings. In March 2001, Dr. Eff-Darwich came for 3 weeks visit to CfA. During this visit we completed our work on the inversion of the internal solar rotation rate, and submitted a paper describing this work to the Astrophysical Journal. This paper has been recently revised in response to the referee comments and I expect that it will be accepted for publication very soon. We also have analyzed helioseismic data looking for temporal variations of the solar stratification near the base of the convection zone. We have expanded on the initial work that was presented at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife), and are in the process of writing this up. Substantial progress towards the characterization of high-degree p-modes has been achieved. Indeed, in collaboration Dr. Rabello-Soares (Stanford University), we have gained a clear conceptual understanding of the various elements that affect the leakage matrix of the SOI/MDI instrument. This was presented in an invited talk at the SOHO-10/GONG-2000 meeting (October 2000, Tenerife). Once we will have successfully migrated from a qualitative to a quantitative assessment of these effects, we should be able to generate high-degree p-modes frequencies so crucial in the diagnostic of the layers just below solar surface.

  4. A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

    NASA Astrophysics Data System (ADS)

    Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

    2015-09-01

    In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

  5. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    NASA Astrophysics Data System (ADS)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  6. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    SciTech Connect

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  7. Bonding III-V material to SOI with transparent and conductive ZnO film at low temperature.

    PubMed

    Huang, Xinnan; Gao, Yonghao; Xu, Xingsheng

    2014-06-16

    A procedure of bonding III-V material to SOI at low temperature using conductive and transparent adhesive ZnO as intermediate layer is demonstrated. Bonding layer thickness of less than 100 nm was achieved in our experiment that guaranteed good light coupling efficiency between III-V and silicon. This bonding method showed good bonding strength with shear stress of 80 N/cm(2). The lowest resistance of the bonded samples was 48.9 Ω and the transmittance of the spin-coated ZnO layer was above 99%. This procedure is applicable for fabricating hybrid III-V/Si lasers. PMID:24977526

  8. Shallow trench isolation-related narrow channel effect on the kink behaviour of 40 nm PD SOI NMOS device

    NASA Astrophysics Data System (ADS)

    Hung, H. J.; Kuo, J. B.; Chen, D.; Tsai, C. T.; Yeh, C. S.

    2010-05-01

    This paper reports the shallow trench isolation (STI)-related narrow channel effect (NCE) on the kink behaviour of the 40 nm PD SOI NMOS device. As verified by the experimentally measured data, with a smaller channel width, the onset of the kink effect behaviour occurs at a higher drain voltage and the breakdown voltage is also larger due to the weaker parasitic bipolar device in the floating thin film as a result of a smaller electron recombination lifetime caused by the STI-related defect effect.

  9. Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

    NASA Astrophysics Data System (ADS)

    Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

    2016-03-01

    In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

  10. 3D analytical model for the SOI LDMOS with alternating silicon and high-k dielectric pillars

    NASA Astrophysics Data System (ADS)

    Yao, Jia-fei; Guo, Yu-feng; Xia, Tian; Zhang, Jun; Lin, Hong

    2016-08-01

    In this paper, a 3D analytical model for the SOI LDMOS with alternating silicon and high-k dielectric pillars (HK LDMOS) is presented. By solving the 3D Poisson's equation, the surface potential and electric field distribution are derived. A criterion for obtaining the optimal breakdown voltage and drift region doping concentration is obtained. The analytical results are well matched with the numerical results, which confirms the model validity. Based on these models and the numerical simulation, the electric field modulation mechanism and the breakdown characteristics of HK LDMOS are investigated.

  11. The nature and impact of chronic stressors on refugee children in Ban Mai Nai Soi camp, Thailand.

    PubMed

    Meyer, Sarah; Murray, Laura K; Puffer, Eve S; Larsen, Jillian; Bolton, Paul

    2013-01-01

    Refugee camps are replete with risk factors for mental health problems among children, including poverty, disruption of family structure, family violence and food insecurity. This study, focused on refugee children from Burma, in Ban Mai Nai Soi camp in Thailand, sought to identify the particular risks children are exposed to in this context, and the impacts on their mental health and psychosocial well-being. This study employed two qualitative methods--free list interviews and key informant interviews--to identify the main problems impacting children in Ban Mai Nai Soi camp and to explore the causes of these problems and their impact on children's well-being. Respondents in free list interviews identified a number of problems that impact children in this context, including fighting between adults, alcohol use by adults and children, and child abuse and neglect. Across the issues, the causes included economic and social conditions associated with living in the camp and changes in family structures. Children are chronically exposed to stressors during their growth and development in the camp environment. Policies and interventions in areas of protracted displacement in camp-based settings should work to address these stressors and their impacts at community, household and individual levels. PMID:23886374

  12. Impact of Ge profile on the performance of PNP SiGe HBT on thin film SOI

    NASA Astrophysics Data System (ADS)

    Misra, Prasanna K.; Qureshi, S.

    2012-10-01

    The pnp SiGe HBT on thin film SOI is investigated with different Ge profiles using 2D numerical simulations in MEDICI. The base current, collector current, DC current gain, AC voltage gain, unity current gain frequency and breakdown voltage is obtained for a 0.09 × 1.0 μm2 pnp SiGe HBT with triangular (0%-30%), trapezoidal (10%- 20%) and box (15%) Ge profiles in the base layer. The results obtained with the Ge profiles, has been analyzed and compared. The Ft BVCEO product for triangular, trapezoidal and box Ge profiles has been found as 190.8, 401, and 359.6 GHzV respectively. The tradeoff between voltage gain and unity current gain frequency for the Ge profiles has been analyzed. The simulation result suggests that the pnp SiGe HBT on thin film SOI with trapezoidal Ge profile is a potential candidate for the high speed complementary bipolar circuits that can be used in high performance mixed signal applications.

  13. A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

    NASA Astrophysics Data System (ADS)

    Mert Torunbalci, Mustafa; Emre Alper, Said; Akin, Tayfun

    2015-12-01

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  14. Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

    NASA Technical Reports Server (NTRS)

    Tu, Juliana; Smith, Rosemary L.

    1995-01-01

    The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

  15. One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

    NASA Astrophysics Data System (ADS)

    Zhang, Jun; Guo, Yu-Feng; Xu, Yue; Lin, Hong; Yang, Hui; Hong, Yang; Yao, Jia-Fei

    2015-02-01

    A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. Project supported by the National Natural Science Foundation of China (Grant No. 61076073) and the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20133223110003).

  16. Rad-Hard Microcontroller for Space Applications

    NASA Astrophysics Data System (ADS)

    Habinc, Sandi; Johansson, Fredrik; Sturesson, Fredrik; Simlastik, Martin; Hjorth, Magnus; Andersson, Jan; Redant, Steven; Sijbers, Wim; Thys, Geert; Monteleone, Claudio

    2015-09-01

    This paper describes a mixed-signal LEON3FT microcontroller ASIC (Application Specific Integrated Circuit) targeting embedded control applications with hard real-time requirements. The prototype device is currently in development at Cobham Gaisler, Sweden, and IMEC, Belgium, in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA).

  17. Technology.

    ERIC Educational Resources Information Center

    Online-Offline, 1998

    1998-01-01

    Focuses on technology, on advances in such areas as aeronautics, electronics, physics, the space sciences, as well as computers and the attendant progress in medicine, robotics, and artificial intelligence. Describes educational resources for elementary and middle school students, including Web sites, CD-ROMs and software, videotapes, books,…

  18. Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies

  19. A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling

    NASA Astrophysics Data System (ADS)

    Rudenko, T.; Nazarov, A.; Kilchytska, V.; Flandre, D.

    2016-03-01

    The charge coupling between the front and back gates is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOSFET. It is traditionally described by the classical Lim and Fossum model (Lim and Fossum, 1983). However, in the case of lightly-doped ultra-thin-body (UTB) SOI MOSFETs with ultra-thin gate dielectrics, significant deviations from this model have been observed and analyzed over the years. In this paper, we present a thorough review of special features of gate coupling in such devices, combining a large set of results from one-dimensional numerical simulations in classical and quantum-mechanical modes, experimental data and analytical modeling. We show that UTB SOI MOSFETs with ultra-thin gate dielectrics feature stronger modulation of the threshold voltage at the conduction side with opposite gate bias and much wider range of gate voltages for interface coupling than predicted by the Lim and Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects is presented. The model enables an easy assessment of the quantization-induced threshold voltage increase in a long-channel SOI MOSFET versus opposite gate bias and the electric field in the silicon film associated with gate decoupling.

  20. Structural Make-up, Biopolymer Conformation, and Biodegradation Characteristics of Newly Developed Super Genotype of Oats (CDC SO-I vs. Conventional Varieties): Novel Approach

    SciTech Connect

    Damiran, D.; Yu, P

    2010-01-01

    Recently, a new 'super' genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE{sub L3x}, 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  1. Development FD-SOI MOSFET Amplifiers for Integrated Read-Out Circuit of Superconducting-Tunnel-Junction Single-Photon-Detectors

    SciTech Connect

    Kiuchi, Kenji; et al.

    2015-07-27

    We proposed a new high-resolution single-photon infrared spectrometer for search for radiative decay of cosmic neutrino background (Cν#23;B). The superconducting-tunnel-junctions(STJs) are used as a single-photon counting device. Each STJ consists of Nb/Al/AlxOy/Al/Nb layers, and their thicknesses are optimized for the operation temperature at 370 mK cooled by a 3He sorption refrigerator. Our STJs achieved the leak current 250 pA, and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio (S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a nonlinear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors is 0.4 mV, and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET-based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp is required to have a fast response (GBW ≥ #21;100 MHz), and it must have low power dissipation as compared to the cooling power of refrigerator.

  2. Two-way reflector based on two-dimensional sub-wavelength high-index contrast grating on SOI

    NASA Astrophysics Data System (ADS)

    Kaur, Harpinder; Kumar, Mukesh

    2016-05-01

    A two-dimensional (2D) high-index contrast grating (HCG) is proposed as a two-way reflector on Silicon-on-insulator (SOI). The proposed reflector provides high reflectivity over two (practically important) sets of angles of incidence- normal (θ = 0 °) and oblique/grazing (θ = 80 ° - 85 ° / 90 °). Analytical model of 2D HCG is presented using improved Fourier modal method. The vertical incidence is useful for application in VCSEL while oblique/grazing incidence can be utilized in high confinement (HCG mirrors based) hollow waveguides and Bragg reflectors. The proposed two-way reflector also exhibits a large reflection bandwidth (around telecom wavelength) which is an advantage for broadband photonic devices.

  3. Polarization rotator-splitters and controllers in a Si3N4-on-SOI integrated photonics platform.

    PubMed

    Sacher, Wesley D; Huang, Ying; Ding, Liang; Barwicz, Tymon; Mikkelsen, Jared C; Taylor, Benjamin J F; Lo, Guo-Qiang; Poon, Joyce K S

    2014-05-01

    We demonstrate novel polarization management devices in a custom-designed silicon nitride (Si(3)N(4)) on silicon-on-insulator (SOI) integrated photonics platform. In the platform, Si(3)N(4) waveguides are defined atop silicon waveguides. A broadband polarization rotator-splitter using a TM0-TE1 mode converter in a composite Si(3)N(4)-silicon waveguide is demonstrated. The polarization crosstalk, insertion loss, and polarization dependent loss are less than -19 dB, 1.5 dB, and 1.0 dB, respectively, over a bandwidth of 80 nm. A polarization controller composed of polarization rotator-splitters, multimode interference couplers, and thin film heaters is also demonstrated. PMID:24921814

  4. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology

    PubMed Central

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K. Kirk

    2015-01-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of −56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle. PMID:25914609

  5. Design of a switch matrix gate/bulk driver controller for thin film lithium microbatteries using microwave SOI technology

    NASA Technical Reports Server (NTRS)

    Whitacre, J.; West, W. C.; Mojarradi, M.; Sukumar, V.; Hess, H.; Li, H.; Buck, K.; Cox, D.; Alahmad, M.; Zghoul, F. N.; Jackson, J.; Terry, S.; Blalock, B.

    2003-01-01

    This paper presents a design approach to help attain any random grouping pattern between the microbatteries. In this case, the result is an ability to charge microbatteries in parallel and to discharge microbatteries in parallel or pairs of microbatteries in series.

  6. Comparison of the radiation hardness of various VLSI technologies for defense applications

    SciTech Connect

    Gibbon, C.F.

    1985-01-01

    In this review the radiation hardness of various potential very large scale (VLSI) IC technologies is evaluated. IC scaling produces several countervailing trends. Reducing vertical dimensions tends to increase total dose hardness, while reducing lateral feature sizes may increase susceptibility to transient radiation effects. It is concluded that during the next decade at least, silicon complimentary MOS (CMOS), perhaps on an insulating substrate (SOI) will be the technology of choice for VLSI in defense systems.

  7. Advanced microelectronics technologies for future small satellite systems

    NASA Astrophysics Data System (ADS)

    Alkalai, Leon

    2000-03-01

    Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjoint markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

  8. Advanced Microelectronics Technologies for Future Small Satellite Systems

    NASA Technical Reports Server (NTRS)

    Alkalai, Leon

    1999-01-01

    Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjointed markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

  9. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

    NASA Astrophysics Data System (ADS)

    Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der; Martino, Joao Antonio; Simoen, Eddy; Claeys, Cor; Collaert, Nadine; Thean, Aaron

    2016-09-01

    This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.

  10. Impact of front oxide quality on transient effects and low-frequency noise in partially and fully depleted SOI N-MOSFETs

    NASA Astrophysics Data System (ADS)

    Haendler, S.; Dieudonné, F.; Jomaah, J.; Balestra, F.; Raynaud, C.; Pelloie, J. L.

    2002-07-01

    The impact of the front oxide quality on the performance of SOI devices is investigated. In this respect, a Fowler-Nordheim stress is performed for both partially (PD) and fully (FD) depleted N-MOSFETs. Various special SOI mechanisms are analyzed, as floating body effects for PD devices and coupling effects, between front and back interfaces, for FD ones. In the first part, the influence of the front oxide quality in PD transistors on transient effects and low-frequency noise (LFN), which both are influenced by the floating body, is analyzed. In the second part, the impact of the front oxide and coupling effects on the LFN in FD MOSFETs is investigated.