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Sample records for solder interconnect integrity

  1. Solder joint reliability of indium-alloy interconnection

    NASA Astrophysics Data System (ADS)

    Shimizu, Kozo; Nakanishi, Teru; Karasawa, Kazuaki; Hashimoto, Kaoru; Niwa, Koichi

    1995-01-01

    Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.

  2. Assessment of Solder Interconnect Integrity in Dismantled Electronic Components from N57 and B61 Tube-Type Radars

    SciTech Connect

    Rejent, J.A.; Vianco, P.T.; Woodrum, R.A.

    1999-07-01

    Aging analyses were performed on solder joints from two radar units: (1) a laboratory, N57 tube-type radar unit and (2) a field-returned, B61-0, tube-type radar unit. The cumulative temperature environments experienced by the units during aging were calculated from the intermetallic compound layer thickness and the mean Pb-rich phase particle size metrics for solder joints in the units, assuming an aging time of 35 years for both radars. Baseline aging metrics were obtained from a laboratory test vehicle assembled at AS/FM and T; the aging kinetics of both metrics were calculated from isothermal aging experiments. The N57 radar unit interconnect board solder joints exhibited very little aging. The eyelet solder joints did show cracking that most likely occurred at the time of assembly. The eyelet, SA1126 connector solder joints, showed some delamination between the Cu pad and underlying laminate. The B61 field-returned radar solder joints showed a nominal degree of aging. Cracking of the eyelet solder joints was observed. The Pb-rich phase particle measurements indicated additional aging of the interconnects as a result of residual stresses. Cracking of the terminal pole connector, pin-to-pin solder joint was observed; but it was not believed to jeopardize the electrical functionality of the interconnect. Extending the stockpile lifetime of the B61 tube-type radar by an additional 20 years would not be impacted by the reliability of the solder joints with respect to further growth of the intermetallic compound layer. Additional coarsening of the Pb-rich phase will increase the joints' sensitivity to thermomechanical fatigue.

  3. Effect of grain orientation on mechanical properties and thermomechanical response of Sn-based solder interconnects

    SciTech Connect

    Chen, Hongtao; Yan, Bingbing; Yang, Ming; Ma, Xin; Li, Mingyu

    2013-11-15

    The thermomechanical response of Sn-based solder interconnects with differently oriented grains was investigated by electron backscattered diffraction technique under thermal cycling and thermal shock testing in this study. The results showed that deformation and cracking of solder interconnects have a close relationship with the unique characteristics of grain orientation and boundaries in each solder interconnect, and deformation was frequently confined within the high-angle grain boundaries. The micro Vickers hardness testing results showed that the hardness varied significantly depending on the grain orientation and structure, and deformation twins can be induced around the indents by the indentation testing. - Highlights: • Thermomechanical response shows a close relationship with the grain structure. • Deformation was frequently confined within the high-angle grain boundaries. • Different grain orientations exhibit different hardness. • Deformation twins can be induced around the indents in SAC105 solder interconnects.

  4. Integrated environmentally compatible soldering technologies. Final report

    SciTech Connect

    Hosking, F.M.; Frear, D.R.; Iman, R.L.; Keicher, D.M.; Lopez, E.P.; Peebles, H.C.; Sorensen, N.R.; Vianco, P.T.

    1994-05-01

    Chemical fluxes are typically used during conventional electronic soldering to enhance solder wettability. Most fluxes contain very reactive, hazardous constituents that require special storage and handling. Corrosive flux residues that remain on soldered parts can severely degrade product reliability. The residues are removed with chlorofluorocarbon (CFC), hydrochlorofluorocarbon (HCFC), or other hazardous solvents that contribute to ozone depletion, release volatile organic compounds into the atmosphere, or add to the solvent waste stream. Alternative materials and processes that offer the potential for the reduction or elimination of cleaning are being developed to address these environmental issues. Timing of the effort is critical, since the targeted chemicals will soon be heavily taxed or banned. DOE`s Office of Environmental Restoration and Waste Management (DOE/EM) has supported Sandia National Laboratories` Environmentally Conscious Manufacturing Integrated Demonstration (ECMID). Part of the ECM program involves the integration of several environmentally compatible soldering technologies for assembling electronics devices. Fluxless or {open_quotes}low-residue/no clean{close_quotes} soldering technologies (conventional and ablative laser processing, controlled atmospheres, ultrasonic tinning, protective coatings, and environmentally compatible fluxes) have been demonstrated at Sandia (SNL/NM), the University of California at Berkeley, and Allied Signal Aerospace-Kansas City Division (AS-KCD). The university demonstrations were directed under the guidance of Sandia staff. Results of the FY93 Soldering ID are presented in this report.

  5. Evaluating the Impact of Dwell Time on Solder Interconnect Durability Under Bending Loads

    NASA Astrophysics Data System (ADS)

    Menon, Sandeep; Osterman, Michael; Pecht, Michael

    2015-11-01

    With the increasing portability and miniaturization of modern-day electronics, the mechanical robustness of these systems has become more of a concern. Existing standards for conducting mechanical durability tests of electronic assemblies include bend, shock/drop, vibration, and torsion. Although these standards provide insights into both cyclic fatigue and overstress damage incurred in solder interconnects (widely regarded as the primary mode of failure in electronic assemblies), they fail to address the impact of time- dependent (creep) behavior due to sustained mechanical loads on solder interconnect durability. It has been seen in previous studies that solder durability under thermal cycling loads is inversely proportional to the dwell time or hold time at either temperature extreme of the imposed temperature cycle. Fatigue life models, which include dwell time, have been developed for solder interconnects subject to temperature cycling. However, the fatigue life models that have been developed in the literature for solder interconnects under mechanical loads fail to address the influence of the duration of loading. In this study, solder interconnect test vehicles were subjected to cyclic mechanical bending with various dwell times in order to understand the impact of the duration of mechanical loads on solder interconnect durability. The solder interconnects examined in this study were formed with 2512 resistor packages using various solder compositions [tin-lead (Sn-Pb) and 96.5Sn-3Ag-0.5Cu (SAC305)]. To evaluate the impact of dwell time, the boards were tested with 0 s, 60 s, and 300 s of dwell time at both extremes of the loading profile. It was observed that an increase in the dwell time of the loading profile resulted in a decrease in the characteristic life of the solder interconnects. The decrease in fatigue life was attributed to increased creep damage as identified using finite-element simulations. An energy partitioning approach was then used to

  6. Solder Interconnect Predictor (SIP) Software v. 0.5

    Energy Science and Technology Software Center (ESTSC)

    2008-11-19

    This software tool was developed for predicting the fatigue damage in a wide variety of 63Sn-37Pb solder joints used in electronics applications. This tool is based upon the unified creep plasticity damage model CompSIR developed at Sandia National Laboratories. The software can be used as a design tool for predicting the long term reliability of consumer, military and space electronics. Both service as well as accelerated testing environments can be addressed by the user. Themore » mesh generating function provides the user with the greater versatility to explore different package and I/O configurations. For example, different solder joint geometries can be investigated to determine the effects of workmanship quality on reliability. Graphical user interfaces provide the user with easy data input screens as well as results profiles.« less

  7. Solder Interconnect Predictor (SIP) Software v. 0.5

    SciTech Connect

    VIANCO, PAUL; NEILSEN, MICHAEL; & REJENT, JEROME

    2008-11-19

    This software tool was developed for predicting the fatigue damage in a wide variety of 63Sn-37Pb solder joints used in electronics applications. This tool is based upon the unified creep plasticity damage model CompSIR developed at Sandia National Laboratories. The software can be used as a design tool for predicting the long term reliability of consumer, military and space electronics. Both service as well as accelerated testing environments can be addressed by the user. The mesh generating function provides the user with the greater versatility to explore different package and I/O configurations. For example, different solder joint geometries can be investigated to determine the effects of workmanship quality on reliability. Graphical user interfaces provide the user with easy data input screens as well as results profiles.

  8. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  9. Cell interconnection without glueing or soldering for crystalline Si photovoltaic modules

    NASA Astrophysics Data System (ADS)

    Summhammer, Johann; Halavani, Zahra

    2016-05-01

    In order to maximize the power output of polycrystalline silicon PV-modules, in previous work we have already tested rectangular cells of 39 × 156 mm which are overlapped along the long sides. The low current density at the cell overlap allows interconnections which need neither soldering nor glueing, but use metallic strips inserted between the cells in the overlap region. The contact is established by the pressure applied to the module during lamination and is retained by the slightly bent cells in the solidified encapsulant. Here we report on the long term stability of different contact materials and contact cross sections applied in eight modules of the 240 W class monitored for up to 24 months of outdoor operation and in a variety of small 5-cell modules exposed to rapid ageing tests with up to 1000 thermal cycles. Cells with three different electrode designs were tested and the contact materials were Cu, Ag, SnPbAg and Sn. Focussing especially on series resistance, fill factor and peak power, it is found that Ag-coated contact strips perform equally well and have practically the same stability as soldered cell interconnections. Due to 70-90% savings in copper and simpler manufacturing the cost of PV-modules may thus be reduced further.

  10. The Reliability of Microalloyed Sn-Ag-Cu Solder Interconnections Under Cyclic Thermal and Mechanical Shock Loading

    NASA Astrophysics Data System (ADS)

    Mattila, Toni T.; Hokka, Jussi; Paulasto-Kröckel, Mervi

    2014-11-01

    In this study, the performance of three microalloyed Sn-Ag-Cu solder interconnection compositions (Sn-3.1Ag-0.52Cu, Sn-3.0Ag-0.52Cu-0.24Bi, and Sn-1.1Ag-0.52Cu-0.1Ni) was compared under mechanical shock loading (JESD22-B111 standard) and cyclic thermal loading (40 ± 125°C, 42 min cycle) conditions. In the drop tests, the component boards with the low-silver nickel-containing composition (Sn-Ag-Cu-Ni) showed the highest average number of drops-to-failure, while those with the bismuth-containing alloy (Sn-Ag-Cu-Bi) showed the lowest. Results of the thermal cycling tests showed that boards with Sn-Ag-Cu-Bi interconnections performed the best, while those with Sn-Ag-Cu-Ni performed the worst. Sn-Ag-Cu was placed in the middle in both tests. In this paper, we demonstrate that solder strength is an essential reliability factor and that higher strength can be beneficial for thermal cycling reliability but detrimental to drop reliability. We discuss these findings from the perspective of the microstructures and mechanical properties of the three solder interconnection compositions and, based on a comprehensive literature review, investigate how the differences in the solder compositions influence the mechanical properties of the interconnections and discuss how the differences are reflected in the failure mechanisms under both loading conditions.

  11. Investigation Of The Effects Of Reflow Profile Parameters On Lead-free Solder Bump Volumes And Joint Integrity

    NASA Astrophysics Data System (ADS)

    Amalu, E. H.; Lui, Y. T.; Ekere, N. N.; Bhatti, R. S.; Takyi, G.

    2011-01-01

    The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high-density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip-chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad-to-pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, and the effect of reflow profile parameters on lead-free solder bump formation and the associated solder joint integrity. The study uses a fractional factorial design (FFD) of 24-1 Ramp-Soak-Spike reflow profile, with all main effects and two-way interactions estimable to determine the optimal factorial combination. The results from the study show that the percentage change in the VSPD depends on the combination of the process parameters and reliability issues could become critical as the size of solder joints soldered on the same board assembly vary greatly. Mathematical models describe the relationships among VSPD, VSBF and theoretical volume of solder paste. Some factors have main effects across the volumes and a number of interactions exist among them. These results would be useful for R&D personnel in designing and implementing newer applications with finer-pitch interconnect.

  12. Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections. Part 1: Effects of Test Parameters

    NASA Astrophysics Data System (ADS)

    Hokka, Jussi; Mattila, Toni. T.; Xu, Hongbo; Paulasto-Kröckel, Mervi

    2013-06-01

    The work presented in part 1 of this study focuses on identifying the effects of thermal cycling test parameters on the lifetime of ball grid array (BGA) component boards. Detailed understanding about the effects of the thermal cycling parameters is essential because it provides means to develop more efficient and meaningful methods of reliability assessment for electronic products. The study was carried out with a single package type (BGA with 144 solder balls), printed wiring board (eight-layer build-up FR4 structure), and solder interconnection composition (Sn-3.1Ag-0.5Cu) to ensure that individual test results would be comparable with each other. The effects of (i) temperature difference (Δ T), (ii) lower dwell temperature and lower dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate were evaluated. Based on the characteristic lifetimes, the thermal cycling profiles were categorized into three lifetime groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. Thus, one might be tempted to use the highly accelerated conditions to produce lifetime statistics as quickly as possible. However, to do this one needs to know that the failure mechanisms do not change from one lifetime group to another and that the failure mechanisms correlate with real-use failures. Therefore, in part 2 the observed differences in component board lifetimes will be explained by studying the failure mechanisms that take place in the three lifetime groups.

  13. INTERCONNECTIONS BETWEEN HUMAN HEALTH AND ECOLOGICAL INTEGRITY

    EPA Science Inventory

    Interconnections between Human Health and Ecological Integrity emanates from a June 2000 Pellston Workshop in Snowbird, Utah, USA. Jointly sponsored by the Society of Environmental Toxicology and Chemistry (SETAC) and the Society of Toxicology (SOT), the workshop was motivated by...

  14. Recent advances on electromigration in very-large-scale-integration of interconnects

    NASA Astrophysics Data System (ADS)

    Tu, K. N.

    2003-11-01

    Today, the price of building a factory to produce submicron size electronic devices on 300 mm Si wafers is over billions of dollars. In processing a 300 mm Si wafer, over half of the production cost comes from fabricating the very-large-scale-integration of the interconnect metallization. The most serious and persistent reliability problem in interconnect metallization is electromigration. In the past 40 years, the microelectronic industry has used Al as the on-chip conductor. Due to miniaturization, however, a better conductor is needed in terms of resistance-capacitance delay, electromigration resistance, and cost of production. The industry has turned to Cu as the on-chip conductor, so the question of electromigration in Cu metallization must be examined. On the basis of what we have learned from the use of Al in devices, we review here what is current with respect to electromigration in Cu. In addition, the system of interconnects on an advanced device includes flip chip solder joints, which now tend to become weak links in the system due to, surprisingly, electromigration. In this review, we compare the electromigration in Al, Cu, and solder on the basis of the ratio of their melting point to the device operating temperature of 100 °C. Accordingly, grain boundary diffusion, surface diffusion, and lattice diffusion dominate, respectively, the electromigration in Al, Cu, and solder. In turn, the effects of microstructure, solute, and stress on electromigration in Al, Cu, and solder are different. The stress induced by electromigration in Cu/low-k interconnects will be a very serious issue since the low-k dielectric (with a value of k around 2) tends to be weak mechanically. In a multilevel interconnect, a electromigration force due to current crowding, acting normal to current flow, has been proposed to explain why many electromigration induced damages occur away from the high current density region. In mean-time-to-failure analysis, the time taken to nucleate

  15. Microstructure and Grain Orientation Evolution in Sn-3.0Ag-0.5Cu Solder Interconnects Under Electrical Current Stressing

    NASA Astrophysics Data System (ADS)

    Chen, Hongtao; Hang, Chunjin; Fu, Xing; Li, Mingyu

    2015-10-01

    In situ observation was performed on cross-sections of Sn-3.0Ag-0.5Cu solder interconnects to track the evolution of microstructure and grain orientation under electrical current stressing. Cross-sections of Cu/Ni-Sn-3.0Ag-0.5Cu-Ni/Cu sandwich-structured solder interconnects were prepared by the standard metallographic method and subjected to electrical current stressing for different times. The electron backscatter diffraction technique was adopted to characterize the grain orientation and structure of the solder interconnects. The results show that metallization dissolution and intermetallic compound (IMC) migration have close relationships with the grain orientation and structure of the solder interconnects. Ni metallization dissolution at the cathode interface and IMC migration in the solder bulk can be accelerated when the c-axis of the grain is parallel to the electron flow direction, while no observable change was found when the c-axis of the grain was perpendicular to the electron flow direction. IMC can migrate along or be blocked at the grain boundary, depending on the misorientation between the current flow direction and grain boundary.

  16. Laser soldering of Sn plated brass integrator assembly housings

    SciTech Connect

    Keicher, D.M.; Poulter, G.A.; Sorensen, N.R.

    1993-09-01

    The high conductivity provided by solder closure joints of component housings is sometimes required to ensure electrical shielding of the components contained within. However, using a soldering iron to produce the solder joints can lead to charring of the insulating materials within the housing. To overcome this problem, the localized heating characteristics of laser soldering can be exploited. Feasibility of laser soldering Sn plated brass housings with a CW Nd:YAG laser has been investigated. It has been determined that laser soldering of these housings using a low solids solder flux is a viable technique and will minimize the amount of heat input to the enclosed electronic components. Metallographic analysis has shown good wetting of the solder on the housing components. Accelerated aging experiments indicate that no significant corrosion potential due to solder flux residues exists. Although a low solids flux was used to make the joints, initial results indicate that a fluxless technique can be developed to eliminate fluxes completely.

  17. Laser soldering of Sn plated brass integrator assembly housings

    NASA Astrophysics Data System (ADS)

    Keicher, D. M.; Poulter, G. A.; Sorensen, N. R.

    1993-09-01

    The high conductivity provided by solder closure joints of component housings is sometimes required to ensure electrical shielding of the components contained within. However, using a soldering iron to produce the solder joints can lead to charring of the insulating materials within the housing. To overcome this problem, the localized heating characteristics of laser soldering can be exploited. The feasibility of laser soldering Sn plated brass housings with a CW Nd:YAG laser has been investigated. It has been determined that laser soldering of these housings using a low solids solder flux is a viable technique and will minimize the amount of heat input to the enclosed electronic components. Metallographic analysis has shown good wetting of the solder on the housing components. Accelerated aging experiments indicate that no significant corrosion potential due to solder flux residues exists. Although a low solids flux was used to make the joints, initial results indicate that a fluxless technique can be developed to eliminate fluxes completely.

  18. Healing Voids In Interconnections In Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

    1989-01-01

    Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

  19. Influence of High- G Mechanical Shock and Thermal Cycling on Localized Recrystallization in Sn-Ag-Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Kim, Choong-Un; Bieler, Thomas R.

    2014-01-01

    The impact of isothermal aging and recrystallized grain structure distribution on mechanical shock and thermal cycling performance of solder joints with 1% and 3% silver content Sn-Ag-Cu interconnects were investigated. Localized recrystallized grain structure distributions were analyzed to identify correlations between the microstructure evolution and shock performance. The results reveal that the shock tolerance depends on the amount of shock energy that can be absorbed during each shock cycle, which depends on microstructural features. Based on the recrystallized grain distribution, additional isothermal aging in 1% silver Sn-Ag-Cu interconnects shows improved shock performance, whereas degraded shock performance was observed in 3% Sn-Ag-Cu interconnects. Using the same grain boundary distribution analysis on thermally cycled samples, relationships between the particle size distribution, localized recrystallized grain structure development, shock, and thermomechanical performance were identified: finer particle spacing is beneficial for thermal cycling as it resists grain boundary generation, while conversely, wider particle spacing facilitates recrystallization and grain boundary mobility that allows Sn to absorb shock energy.

  20. Sn-Ag-Cu Nanosolders: Solder Joints Integrity and Strength

    NASA Astrophysics Data System (ADS)

    Roshanghias, Ali; Khatibi, Golta; Yakymovych, Andriy; Bernardi, Johannes; Ipser, Herbert

    2016-08-01

    Although considerable research has been dedicated to the synthesis and characterization of lead-free nanoparticle solder alloys, only very little has been reported on the reliability of the respective joints. In fact, the merit of nanoparticle solders with depressed melting temperatures close to the Sn-Pb eutectic temperature has always been challenged when compared with conventional solder joints, especially in terms of inferior solderability due to the oxide shell commonly present on the nanoparticles, as well as due to compatibility problems with common fluxing agents. Correspondingly, in the current study, Sn-Ag-Cu (SAC) nanoparticle alloys were combined with a proper fluxing vehicle to produce prototype nanosolder pastes. The reliability of the solder joints was successively investigated by means of electron microscopy and mechanical tests. As a result, the optimized condition for employing nanoparticles as a competent nanopaste and a novel procedure for surface treatment of the SAC nanoparticles to diminish the oxide shell prior to soldering are being proposed.

  1. Sn-Ag-Cu Nanosolders: Solder Joints Integrity and Strength

    NASA Astrophysics Data System (ADS)

    Roshanghias, Ali; Khatibi, Golta; Yakymovych, Andriy; Bernardi, Johannes; Ipser, Herbert

    2016-05-01

    Although considerable research has been dedicated to the synthesis and characterization of lead-free nanoparticle solder alloys, only very little has been reported on the reliability of the respective joints. In fact, the merit of nanoparticle solders with depressed melting temperatures close to the Sn-Pb eutectic temperature has always been challenged when compared with conventional solder joints, especially in terms of inferior solderability due to the oxide shell commonly present on the nanoparticles, as well as due to compatibility problems with common fluxing agents. Correspondingly, in the current study, Sn-Ag-Cu (SAC) nanoparticle alloys were combined with a proper fluxing vehicle to produce prototype nanosolder pastes. The reliability of the solder joints was successively investigated by means of electron microscopy and mechanical tests. As a result, the optimized condition for employing nanoparticles as a competent nanopaste and a novel procedure for surface treatment of the SAC nanoparticles to diminish the oxide shell prior to soldering are being proposed.

  2. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  3. Integrated silicon photonic interconnect with surface-normal optical interface

    NASA Astrophysics Data System (ADS)

    Zhang, Zanyun; Huang, Beiju; Zhang, Zan; Cheng, Chuantong; Liu, Hongwei; Li, Hongqiang; Chen, Hongda

    2016-05-01

    An integrated silicon photonic interconnect with surface-normal optical interface is demonstrated by connecting a bidirectional grating based E-O modulator and a germanium waveguide photodetector. To investigate this photonic interconnect, both static and dynamic performance of the discrete devices are characterized respectively. Based on the characterization work, data transmission experiment is carried out for the photonic interconnect. Eye diagram results indicate the photonic interconnect can operate up to 7 Gb/s.

  4. PCB with fully integrated optical interconnects

    NASA Astrophysics Data System (ADS)

    Langer, Gregor; Satzinger, Valentin; Schmidt, Volker; Schmid, Gerhard; Leeb, Walter R.

    2011-01-01

    The increasing demand for miniaturization and design flexibility of polymer optical waveguides integrated into electrical printed circuit boards (PCB) calls for new coupling and integration concepts. We report on a method that allows the coupling of optical waveguides to electro-optical components as well as the integration of an entire optical link into the PCB. The electro-optical devices such as lasers and photodiodes are assembled on the PCB and then embedded in an optically transparent material. A focused femtosecond laser beam stimulates a polymerization reaction based on a two-photon absorption effect in the optical material and locally increases the refractive index of the material. In this way waveguide cores can be realized and the embedded components can be connected optically. This approach does not only allow a precise alignment of the waveguide end faces to the components but also offers a truly 3-dimensional routing capability of the waveguides. Using this technology we were able to realize butt-coupling and mirror-coupling interface solutions in several demonstrators. We were also manufacturing demonstrator boards with fully integrated driver and preamplifier chips, which show very low power consumption of down to 10 mW for about 2.5 Gbit/s. Furthermore, demonstrators with interconnects at two different optical layers were realized.

  5. Ultrafine-Grain and Isotropic Cu/SAC305/Cu Solder Interconnects Fabricated by High-Intensity Ultrasound-Assisted Solidification

    NASA Astrophysics Data System (ADS)

    Ji, Hongjun; Wang, Qiang; Li, Mingyu; Wang, Chunqing

    2014-07-01

    With the miniaturization of portable electronic devices, the size of solder joint interconnects is decreasing to micrometer levels. These joints possess only several or even one or two grains, resulting in anisotropy and failure issues. Direct ultrasound-assisted solidification of Cu/SAC305/Cu interconnects for grain refinement and fabrication of isotropic solder joints is presented herein. These joints consist of many β-Sn grains. The average cross-sectional area of the Sn-rich phase is significantly reduced by up to 99% when compared with conventional as-reflowed samples. The ultrasonic power density exhibits a threshold value for affecting the microstructures. Below 200 W cm-2, the β-Sn grains were refined and had circular shape. The Ag3Sn phase grew in a manner similar to branched coral to sizes reaching 30 μm, or as rods aggregated together with Cu6Sn5 tube fragments. Above 200 W cm-2, the microstructures were coarsened and Ag3Sn had plate-like shape. The thickness of Cu6Sn5 intermetallic layers at the Cu/solder interfaces was reduced by more than 26%. The relationships among the ultrasonic power, nucleation rate, local temperature drop, and pressure were identified. At the highest power density of 267 W cm-2, the nucleation rate was about 4.05 × 1014 m-3 s-1, the local temperature drop was 248 K, and the local pressure was on the order of several GPa.

  6. Soldered solar arrays

    NASA Astrophysics Data System (ADS)

    Allen, H. C.

    1982-06-01

    The ability of soldered interconnects to withstand a combination of long life and severe environmental conditions was investigated. Improvements in joint life from the use of solder mixes appropriate to low temperature conditons were studied. Solder samples were placed in a 150 C oven for 5 weeks (= 12 yr at 80 C, or 24 at 70 C according to Arrhenius's rule). Conventional and high solder melting point array samples underwent 1000 thermal cycles between -186 and 100 C. Results show that conventional and lead rich soldered arrays can survive 10 yr geostationary orbit missions.

  7. Impact of Cooling Rate-Induced Recrystallization on High G Mechanical Shock and Thermal Cycling in Sn-Ag-Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Bieler, Thomas R.; Kim, Choong-Un

    2016-01-01

    The mechanical stability and thermo-mechanical fatigue performance of solder joints with low silver content Sn-1.0Ag-0.5Cu (wt.%) (SAC105) alloy based on different cooling rates are investigated in high G level shock environment and thermal cycling conditions. The cooling rate-controlled samples ranging from 1°C/min to 75°C/min cooling rate, not only show differences in microstructure, where a fine poly-granular microstructure develops in the case of fast cooling versus normal cooling, but also show various shock performances based on the microstructure changes. The fast cooling rate improves the high G shock performance by over 90% compared to the normal cooled SAC105 alloy air-cooling environment commonly used after assembly reflow. The microstructure effect on thermal cycling performance is also discussed, which is analyzed based on the Sn grain orientation, interconnect stability, and solder joint bulk microstructure.

  8. Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

    NASA Technical Reports Server (NTRS)

    Mandal, R. P.

    1976-01-01

    Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

  9. Interconnection of thermal parameters, microstructure and mechanical properties in directionally solidified Sn–Sb lead-free solder alloys

    SciTech Connect

    Dias, Marcelino; Costa, Thiago; Rocha, Otávio; Spinelli, José E.; Cheung, Noé; Garcia, Amauri

    2015-08-15

    Considerable effort is being made to develop lead-free solders for assembling in environmental-conscious electronics, due to the inherent toxicity of Pb. The search for substitute alloys of Pb–Sn solders has increased in order to comply with different soldering purposes. The solder must not only meet the expected levels of electrical performance but may also have appropriate mechanical strength, with the absence of cracks in the solder joints. The Sn–Sb alloy system has a range of compositions that can be potentially included in the class of high temperature solders. This study aims to establish interrelations of solidification thermal parameters, microstructure and mechanical properties of Sn–Sb alloys (2 wt.%Sb and 5.5 wt.%Sb) samples, which were directionally solidified under cooling rates similar to those of reflow procedures in industrial practice. A complete high-cooling rate cellular growth is shown to be associated with the Sn–2.0 wt.%Sb alloy and a reverse dendrite-to-cell transition is observed for the Sn–5.5 wt.%Sb alloy. Strength and ductility of the Sn–2.0 wt.%Sb alloy are shown not to be affected by the cellular spacing. On the other hand, a considerable variation in these properties is associated with the cellular region of the Sn–5.5 wt.%Sb alloy casting. - Graphical abstract: Display Omitted - Highlights: • The microstructure of the Sn–2 wt.%Sb alloy is characterized by high-cooling rates cells. • Reverse dendrite > cell transition occurs for Sn–5.5 wt.%Sb alloy: cells prevail for cooling rates > 1.2 K/s. • Sn–5.5 wt.%Sb alloy: the dendritic region occurs for cooling rates < 0.9 K/s. • Sn–5.5 wt.%Sb alloy: tensile properties are improved with decreasing cellular spacing.

  10. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2004-09-28

    An electrochemical energy storage device includes a number of solid-state thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. Fuses and various electrical and electro-mechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  11. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2003-11-04

    The present invention is directed to an improved electrochemical energy storage device. The electrochemical energy storage device includes a number of solid-state, thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. Fuses and various electrical and electromechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  12. Stress-induced voiding study in integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Hou, Yuejin; Tan, Cher Ming

    2008-07-01

    An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

  13. Updating Interconnection Screens for PV System Integration

    SciTech Connect

    Coddington, M.; Mather, B.; Kroposki, B.; Lynn, K.; Razon, A.; Ellis, A.; Hill, R.; Key, T.; Nicole, K.; Smith, J.

    2012-02-01

    This white paper evaluates the origins and usefulness of the capacity penetration screen, offer short-term solutions which could effectively allow fast-track interconnection to many PV system applications, and considers longer-term solutions for increasing PV deployment levels in a safe and reliable manner while reducing or eliminating the emphasis on the penetration screen. Short-term and longer-term alternatives approaches are offered as examples; however, specific modifications to screening procedures should be discussed with stakeholders and must ultimately be adopted by state and federal regulatory bodies.

  14. Metallic Nanowire Interconnections for Integrated Circuit Fabrication

    NASA Technical Reports Server (NTRS)

    Ng, Hou Tee (Inventor); Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2007-01-01

    A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

  15. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  16. A Novel and Facile Method to Prepare Integrated Electrospun Nanofibrous Membrane with Soldered Junctions.

    PubMed

    Shen, Lingdi; Chen, Jiajia; Hong, Guishan; Wang, Xuefen

    2016-01-01

    Integrated electrospun nanofibrous membrane was prepared by creating soldered junctions between nanofibers via a facile strategy. Polyacrylonitrile (PAN) mixed with poly(vinylidene fluoride) (PVDF) at different ratios of PVDF were prepared in N,N'-dimethyl formamide (DMF), then electrospun to fabricate PAN/PVDF membranes. PVDF can form microgels in DMF which slows down volatile speed of DMF and affects the solidification of PAN/PVDF nanofibers. The resulting membranes were investigated by Fourier transform infrared spectroscopy, scanning electron microscopy, dynamic water contact angle and tensile testing to confirm the morphology and mechanical properties. Soldered junctions were observed between nanofibers with the increase of PVDF content. These junctions made the membrane integrated and greatly enhanced tensile strength from 5.1 to 8.1 MPa (increased by ~60%) and tensile modulus from 49.4 to 117.9 MPa (increased by ~139%) without compromising porosity when the content of PVDF increased from 0 to 60 wt%. PMID:27398532

  17. An application of carbon nanotubes for integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Coiffic, J. C.; Foa Torres, L. E.; Le Poche, H.; Fayolle, M.; Roche, S.; Maitrejean, S.; Roualdes, S.; Ayral, A.

    2008-08-01

    Integrated circuits fabrication is soon reaching strong limitations. Help could come from using carbon nanotubes as conducting wires for interconnects. Although this solution was proposed six years ago, researchers still come up with many obstacles such as localization, low temperature growth on copper, contacting and reproducibility. The integration processes exposed here intend to meet the industrial requirements. Two approaches are then possibly followed. Either using densely packed single wall (SWCNT) (or very tiny multiwall) nanotubes, or filling up the whole interconnect diameter with a single large multiwall (MWCNT) nanotube. In this work, we focus on the integration of multiwall vertical interconnects. Densely packed MWCNTs are grown in via holes by CVD. Alternatively, we have developed a method to obtain a single large nanofibre grown by PECVD (MWCNF) in each via hole. Electrical measurements are performed on CVD and PECVD grown carbon nanotubes. The role of electron-phonon interaction in these devices is also briefly discussed.

  18. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2000-01-01

    The present invention is directed to an improved electrochemical energy storage device. The electrochemical energy storage device includes a number of solid-state, thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. In one embodiment, a sheet of conductive material is processed by employing a known milling, stamping, or chemical etching technique to include a connection pattern which provides for flexible and selective interconnecting of individual electrochemical cells within the housing, which may be a hermetically sealed housing. Fuses and various electrical and electro-mechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  19. Time And Temperature Dependent Micromechanical Properties Of Solder Joints For 3D-Package Integration

    NASA Astrophysics Data System (ADS)

    Roellig, Mike; Meier, Karsten; Metasch, Rene

    2010-11-01

    The recent development of 3D-integrated electronic packages is characterized by the need to increase the diversity of functions and to miniaturize. Currently many 3D-integration concepts are being developed and all of them demand new materials, new designs and new processing technologies. The combination of simulation and experimental investigation becomes increasingly accepted since simulations help to shorten the R&D cycle time and reduce costs. Numerical calculations like the Finite-Element-Method are strong tools to calculate stress conditions in electronic packages resulting from thermal strains due to the manufacturing process and environmental loads. It is essential for the application of numerical calculations that the material data is accurate and describes sufficiently the physical behaviour. The developed machine allows the measurement of time and temperature dependent micromechanical properties of solder joints. Solder joints, which are used to mechanically and electrically connect different packages, are physically measured as they leave the process. This allows accounting for process influences, which may change material properties. Additionally, joint sizes and metallurgical interactions between solder and under bump metallization can be respected by this particular measurement. The measurement allows the determination of material properties within a temperature range of 20° C-200° C. Further, the time dependent creep deformation can be measured within a strain-rate range of 10-31/s-10-81/s. Solder alloys based on Sn-Ag/Sn-Ag-Cu with additionally impurities and joint sizes down to O/ 200 μm were investigated. To finish the material characterization process the material model coefficient were extracted by FEM-Simulation to increase the accuracy of data.

  20. Heat Lamps Solder Solar Array Quickly

    NASA Technical Reports Server (NTRS)

    Coyle, P. J.; Crouthamel, M. S.

    1982-01-01

    Interconnection tabs in a nine-solar-cell array have been soldered simultaneously with radiant heat. Cells and tabs are held in position for soldering by sandwiching them between compliant silicone-rubber vacuum platen and transparent polyimide sealing membrane. Heat lamps warm cells, producing smooth, flat solder joints of high quality.

  1. Utilization of Pb-free solders in MEMS packaging

    NASA Astrophysics Data System (ADS)

    Selvaduray, Guna S.

    2003-01-01

    Soldering of components within a package plays an important role in providing electrical interconnection, mechanical integrity and thermal dissipation. MEMS packages present challenges that are more complex than microelectronic packages because they are far more sensitive to shock and vibration and also require precision alignment. Soldering is used at two major levels within a MEMS package: at the die attach level and at the component attach level. Emerging environmental regulations worldwide, notably in Europe and Japan, have targeted the elimination of Pb usage in electronic assemblies, due to the inherent toxicity of Pb. This has provided the driving force for development and deployment of Pb-free solder alloys. A relatively large number of Pb-free solder alloys have been proposed by various researchers and companies. Some of these alloys have also been patented. After several years of research, the solder alloy system that has emerged is based on Sn as a major component. The electronics industry has identified different compositions for different specific uses, such as wave soldering, surface mount reflow, etc. The factors that affect choice of an appropriate Pb-free solder can be divided into two major categories, those related to manufacturing, and those related to long term reliability and performance.

  2. Formation of solid-solution Cu-to-Cu joints using Ga solder and Pt under bump metallurgy for three-dimensional integrated circuits

    NASA Astrophysics Data System (ADS)

    Lin, Shih-kang; Chang, Hao-miao; Cho, Cheng-liang; Liu, Yu-chen; Kuo, Yi-kai

    2015-07-01

    Three-dimensional (3D) integrated circuits (ICs) are the most important packaging technology for next-generation semiconductors. Cu-to-Cu throughsilicon via interconnections with micro-bumps are key components in the fabrication of 3D ICs. However, significant reliability concerns have been raised due to the formation of brittle intermetallic compounds in the entire 3D IC joints. This study proposes a Ga-based Cu-to-Cu bonding technology with Pt under bump metallurgy (UBM). A systematic analysis of reactive wetting between Ga solders and polycrystalline, single-crystalline, and Ptcoated Cu substrates was conducted. Pt UBM as a wetting layer was identified to be a key component for Ga-based Cu-to-Cu bonding. Pt-coated Cu substrates were bonded using Ga solders with various Ga-to-Pt ratios ( n) at 300℃. When n ≥ 4, the Cu/Pt/Ga/Pt/Cu interface evolves to Cu/facecentered cubic (fcc)/γ1-Cu9Ga4/fcc/Cu, Cu/fcc/γ1-Cu9Ga4 + Ga7Pt3/fcc/Cu, and finally Cu/fcc + Ga7Pt3/Cu structures. The desired ductile solid solution joint formed with discrete Ga7Pt3 precipitates. When n ≤ 1, a Cu/Ga7Pt3/Cu joint formed without Cu actively participating in the reactions. The reaction mechanism and microstructure evolution were elaborated with the aid of CALPHAD thermodynamic modeling. [Figure not available: see fulltext.

  3. Integration of a waveguide self-electrooptic effect device and a vertically coupled interconnect waveguide

    DOEpatents

    Vawter, G. Allen

    2008-02-26

    A self-electrooptic effect device ("SEED") is integrated with waveguide interconnects through the use of vertical directional couplers. Light initially propagating in the interconnect waveguide is vertically coupled to the active waveguide layer of the SEED and, if the SEED is in the transparent state, the light is coupled back to the interconnect waveguide.

  4. Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration

    NASA Astrophysics Data System (ADS)

    Huffman, Alan; Lannon, John; Lueck, Matthew; Gregory, Christopher; Temple, Dorota

    2009-03-01

    The use of collapsible (solder) bump interconnects in pixel detector hybridization has been shown to be very successful. However, as pixel sizes decrease, the use of non-collapsible metal-to-metal bump bonding methods is needed to push the interconnect dimensions smaller. Furthermore, these interconnects are compatible with 3D intgration technologies which are being considered to increase overall pixel and system performance. These metal-to-metal bonding structures provide robust mechanical and electrical connections and allow for a dramatic increase in pixel density. Of particular interest are Cu-Cu thermocompression bonding and Cu/Sn-Cu solid-liquid diffusion bonding processes. Working with Fermilab, RTI undertook a demonstration to show that these bump structures could be reliably used to interconnect devices designed with 20 micron I/O pitch. Cu and Cu/Sn bump fabrication processes were developed to provide a well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. The electrical resistance and yield has been quantified based on electrical measurements of daisy chain test structures and the mechanical strength of the bonding has been quantified through die shear testing. The reliability has been characterized through studies of the impact of thermal exposure on the mechanical performance of the bonds. Cross-section SEM analysis, coupled with high resolution energy dispersive spectroscopy, has provided insight into the physical and chemical nature of the bonding interfaces and aided in the evaluation of the long-term stability of the bonds.

  5. Solar cell array interconnects

    DOEpatents

    Carey, P.G.; Thompson, J.B.; Colella, N.J.; Williams, K.A.

    1995-11-14

    Electrical interconnects are disclosed for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value. 4 figs.

  6. Solar cell array interconnects

    DOEpatents

    Carey, Paul G.; Thompson, Jesse B.; Colella, Nicolas J.; Williams, Kenneth A.

    1995-01-01

    Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

  7. Solder Mounting Technologies for Electronic Packaging

    SciTech Connect

    VIANCO, PAUL T.

    1999-09-23

    Soldering provides a cost-effective means for attaching electronic packages to circuit boards using both small scale and large scale manufacturing processes. Soldering processes accommodate through-hole leaded components as well as surface mount packages, including the newer area array packages such as the Ball Grid Arrays (BGA), Chip Scale Packages (CSP), and Flip Chip Technology. The versatility of soldering is attributed to the variety of available solder alloy compositions, substrate material methodologies, and different manufacturing processes. For example, low melting temperature solders are used with temperature sensitive materials and components. On the other hand, higher melting temperature solders provide reliable interconnects for electronics used in high temperature service. Automated soldering techniques can support large-volume manufacturing processes, while providing high reliability electronic products at a reasonable cost.

  8. Induction soldering of photovoltaic system components

    DOEpatents

    Kumaria, Shashwat; de Leon, Briccio

    2015-11-17

    A method comprises positioning a pair of photovoltaic wafers in a side-by-side arrangement. An interconnect is placed on the pair of wafers such that the interconnect overlaps both wafers of the pair, solder material being provided between the interconnect and the respective wafers. A solder head is then located adjacent the interconnect, and the coil is energized to effect inductive heating of the solder material. The solder head comprises an induction coil shaped to define an eye, and a magnetic field concentrator located at least partially in the eye of the coil. The magnetic field concentrator defines a passage extending axially through the eye of the coil, and may be of a material with a high magnetic permeability.

  9. Electromigration-induced back stress in critical solder length for three-dimensional integrated circuits

    SciTech Connect

    Huang, Y. T.; Hsu, H. H.; Wu, Albert T.

    2014-01-21

    Because of the miniaturization of electronic devices, the reliability of electromigration has become a major concern when shrinking the solder dimensions in flip-chip joints. Fast reaction between solders and electrodes causes intermetallic compounds (IMCs) to form, which grow rapidly and occupy entire joints when solder volumes decrease. In this study, U-grooves were fabricated on Si chips as test vehicles. An electrode-solder-electrode sandwich structure was fabricated by using lithography and electroplating. Gaps exhibiting well-defined dimensions were filled with Sn3.5Ag solders. The gaps between the copper electrodes in the test sample were limited to less than 15 μm to simulate microbumps. The samples were stressed at various current densities at 100 °C, 125 °C, and 150 °C. The morphological changes of the IMCs were observed, and the dimensions of the IMCs were measured to determine the kinetic growth of IMCs. Therefore, this study focused on the influence of back stress caused by microstructural evolution in microbumps.

  10. Electromigration-induced back stress in critical solder length for three-dimensional integrated circuits

    NASA Astrophysics Data System (ADS)

    Huang, Y. T.; Hsu, H. H.; Wu, Albert T.

    2014-01-01

    Because of the miniaturization of electronic devices, the reliability of electromigration has become a major concern when shrinking the solder dimensions in flip-chip joints. Fast reaction between solders and electrodes causes intermetallic compounds (IMCs) to form, which grow rapidly and occupy entire joints when solder volumes decrease. In this study, U-grooves were fabricated on Si chips as test vehicles. An electrode-solder-electrode sandwich structure was fabricated by using lithography and electroplating. Gaps exhibiting well-defined dimensions were filled with Sn3.5Ag solders. The gaps between the copper electrodes in the test sample were limited to less than 15 μm to simulate microbumps. The samples were stressed at various current densities at 100 °C, 125 °C, and 150 °C. The morphological changes of the IMCs were observed, and the dimensions of the IMCs were measured to determine the kinetic growth of IMCs. Therefore, this study focused on the influence of back stress caused by microstructural evolution in microbumps.

  11. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates.

    PubMed

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-14

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. PMID:27101972

  12. Modeling and extraction of interconnect parameters in very-large-scale integrated circuits

    NASA Astrophysics Data System (ADS)

    Yuan, C. P.

    1983-08-01

    The increased complexity of the very large scale integrated circuits (VLSI) has greatly impacted the field of computer-aided design (CAD). One of the problems brought about is the interconnection problem. In this research, the goal is two fold. First of all, a more accurate numerical method to evaluate the interconnect capacitance, including the coupling capacitance between interconnects and the fringing field capacitance, was investigated, and the integral method was employed. Two FORTRAN programs "CAP2D' and "CAP3D' based on this method were developed. Second, a PASCAL extraction program emphasizing the extraction of interconnect parameters was developed. It employs the cylindrical approximation formula for the self-capacitance of a single interconnect and other simple formulas for the coupling capacitances derived by a least square method. The extractor assumes only Manhattan geometry and NMOS technology. Four-dimensional binary search trees are used as the basic data structure.

  13. Perpendicular Growth Characteristics of Cu-Sn Intermetallic Compounds at the Surface of 99Sn-1Cu/Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Chen, Zhiwen; Liu, Changqing; Wu, Yiping; An, Bing

    2015-12-01

    The growth of intermetallic compounds (IMCs) on the free surface of 99Sn-1Cu solder joints perpendicular to the interdiffusion direction has been investigated in this work. The specimens were specifically designed and polished to reveal a flat free surface at the solder/Cu interface for investigation. After aging at 175°C for progressively increased durations, the height of the perpendicular IMCs was examined and found to follow a parabolic law with aging duration that could be expressed as y = 0.11√ t, where t is the aging duration in hours and y is the height of the perpendicular IMCs in μm. For comparison, the planar growth of IMCs along the interdiffusion direction was also investigated in 99Sn-1Cu/Cu solder joints. After prolonged aging at 175°C, the thickness of the planar interfacial IMC layers also increased parabolically with aging duration and could be expressed as h_{{IMC}} = 0.27√ t + 4.6, where h is the thickness in μm and t is the time in hours. It was found that both the planar and perpendicular growth of the IMCs were diffusion-controlled processes, but the perpendicular growth of the IMCs was much slower than their planar growth due to the longer diffusion distance. It is proposed that Cu3Sn forms prior to the formation of Cu6Sn5 in the perpendicular IMCs, being the reverse order compared with the planar IMC growth.

  14. Solder poisoning

    MedlinePlus

    ... in solder that can be harmful are: Antimony Bismuth Cadmium Copper Ethylene glycol Lead Mild acids Silver ... of the bones and kidney failure Symptoms for bismuth: Diarrhea Eye irritation Gum disease ( gingivitis ) Kidney damage ...

  15. X-ray laminography analysis of ultra-fine-pitch solder connections on ultrathin boards

    NASA Astrophysics Data System (ADS)

    Adams, John A.

    1991-07-01

    As the demand increases for smaller, more powerful new products, design engineers are pressed to increase component densities while simultaneously reducing the size of interconnects. Almost every new product contains more solder joints per square inch than the previous one. New quad flatpack and TAB designs as small as 25 micron leads on 50 micron centers are in the prototype stage. Direct 'chip-on-board' (COB) components placed on a grid of solder bumps with a diameter of 75 microns and a grid of 200 microns are routinely being produced. Future plans include designs with a 25 micron diameter on 50 micron centers which are currently in development. Devices consisting of chips stacked upon chips and interconnected with solder or tungsten wires are increasingly included in new designs. Manufacturers have also begun to produce assemblies on very thin circuit boards with components on both sides. Several technologies have been applied in an effort to provide solder paste and post- reflow inspection. X-ray inspection has proven most effective at determining component placement and solder joint integrity. With its ability to pass freely through circuit board materials and extract detailed structural information from hidden and visible solder joints, the x-ray has proven more adept at assembled board inspection than other automated methods such as laser, ultrasonic, thermal and camera-based systems. This paper addresses the inspection and process control of ultra-thin boards with ultra fine pitch interconnects using x-ray laminography. In addition, the advantages and disadvantages of integrating various fine pitch technologies into the circuit board assembly process are reviewed.

  16. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates

    NASA Astrophysics Data System (ADS)

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-01

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints.Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02041k

  17. Introduction to Electrochemical Process Integration for Cu Interconnects

    NASA Astrophysics Data System (ADS)

    Ohba, Takayuki

    This chapter focuses on advanced multilevel interconnects, contributed by distinguished authors in the following sections: Damascene Concept and Process Steps (Nobuyoshi Kobayashi), Advanced BEOL Technology Overview (Takashi Yoda and Hideshi Miyajima), Lithography for Cu Damascene fabrication (Yoshihiro Hayashi), Physical Vapor Deposition Barriers for Cu metallization PVD Barriers (Junichi Koike), Low-k dielectrics (Yoshihiro Hayashi), CMP for Cu Processing (Manabu Tsujimura), Electrochemical View of Copper Chemical Mechanical Polishing (CMP) (D. Starosvetsky and Y. Ein-Eli), and Copper Post-CMP Cleaning (D. Starosvetsky and Y. Ein-Eli).

  18. Wave soldering with Pb-free solders

    SciTech Connect

    Artaki, I.; Finley, D.W.; Jackson, A.M.; Ray, U.; Vianco, P.T.

    1995-07-01

    The manufacturing feasibility and attachment reliability of a series of newly developed lead-free solders were investigated for wave soldering applications. Some of the key assembly aspects addressed included: wettability as a function of board surface finish, flux activation and surface tension of the molten solder, solder joint fillet quality and optimization of soldering thermal profiles. Generally, all new solder formulations exhibited adequate wave soldering performance and can be considered as possible alternatives to eutectic SnPb for wave soldering applications. Further process optimization and flux development is necessary to achieve the defect levels associated with the conventional SnPb process.

  19. The Influence of Sn Orientation on the Electromigration of Idealized Lead-free Interconnects

    NASA Astrophysics Data System (ADS)

    Linares, Xioranny

    As conventional lead solders are being replaced by Pb-free solders in electronic devices, the reliability of solder joints in integrated circuits (ICs) has become a high concern. Due to the miniaturization of ICs and consequently solder joints, the current density through the solder interconnects has increased causing electrical damage known as electromigration. Electromigration, atomic and mass migration due to high electron currents, is one of the most urgent reliability issues delaying the implementation of Pb-free solder materials in electronic devices. The research on Pb-free solders has mainly focused on the qualitative understanding of failure by electromigration. There has been little progress however, on the quantitative analysis of electromigration because of the lack of available material parameters, such as the effective charge, (z*), the driving force for electromigration. The research herein uses idealized interconnects to measure the z* of electromigration of Cu in Sn-3.0Ag-0.5Cu (SAC305) alloy under different experimental conditions. Planar SAC 305 interconnects were sandwiched between two Cu pads and subject to uniaxial current. The crystallographic orientation of Sn in these samples were characterized with electron backscatter diffraction (EBSD) and wavelength dispersive spectroscopy (WDS) before and after electromigration testing. Results indicate that samples with the c-axis aligned perpendicular to current flow, polycrystalline, and those with a diffusion barrier on the cathode side all inhibit the growth of intermetallic compounds (IMC). The effective charge values of Cu in SAC 305 under the different conditions tested were quantified for the first time and included in this dissertation. The following research is expected to help verify and improve the electromigration model and identify the desirable conditions to inhibit damage by electromigration in Pb-free solder joints.

  20. Process for electrically interconnecting electrodes

    DOEpatents

    Carey, Paul G.; Thompson, Jesse B.; Colella, Nicolas J.; Williams, Kenneth A.

    2002-01-01

    Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb--Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb--Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

  1. Requirements for soldered electrical connections

    NASA Technical Reports Server (NTRS)

    1992-01-01

    This publication is applicable to NASA programs involving solder connections for flight hardware, mission essential support equipment, and elements thereof. This publication sets forth hand and wave soldering requirements for reliable electrical connections. The prime consideration is the physical integrity of solder connections. Special requirements may exist which are not in conformance with the requirements of this publication. Design documentation contains the detail for these requirements, and they take precedence over conflicting portions of this publication when they are approved in writing by the procuring NASA installation.

  2. Silicon integrated nanophotonics for on-chip interconnects

    NASA Astrophysics Data System (ADS)

    Vlasov, Yurii

    2008-03-01

    Current trend in microelectronics industry is to increase the parallelism in computation by multi-threading, by building large scale multi-chip systems and, more recently, by increasing the number of cores on a single chip. With such increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. The on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. We will review recent results on silicon nanophotonic circuits based on photonic wires and photonic crystals. Strong light confinement at the diffraction limit enables dramatic scaling of the device area and allows unprecedented control over optical signals. Silicon nanophotonic devices have immense capacity for low-loss, high-bandwidth data processing that might enable the design of ultra-compact on-chip optical networks. In particular we will show recent results on design and characterization of various ultra-compact (<0.03mm2) silicon nanophotonic circuits as optical delay lines, electro-optic modulators, broadband optical switches, wavelength filters, etc.

  3. Wafer-Level 3D Integration for ULSI Interconnects

    NASA Astrophysics Data System (ADS)

    Gutmann, Ronald J.; Lu, Jian-Qiang

    Three-dimensional (3D) integration in a system-in-a-package (SiP) implementation (packaging-based 3D) is becoming increasingly used in consumer, computer, and communication applications where form factor is critical. In particular, the hand-held market for a growing myriad of voice, data, messaging, and imaging products is enabled by packaging-based 3D integration (i.e., stacking and connecting individual chips). The key drivers are for increased memory capacity and for heterogeneous integration of different IC technologies and functions.

  4. Inter-connections between human health and ecological integrity: An organizational framework for research and development

    EPA Science Inventory

    A Pellston workshop entitled, Interconnections between Human Health and Ecological Integrity, was held in 2000. Jointly sponsored by the Society of Environmental Toxicology and Chemistry (SETAC) and the Society of Toxicology (SOT), the workshop was motivated by the concern of hum...

  5. Advances in integrated photonic circuits for packet-switched interconnection

    NASA Astrophysics Data System (ADS)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  6. Agent-Based Simulation for Interconnection-Scale Renewable Integration and Demand Response Studies

    SciTech Connect

    Chassin, David P.; Behboodi, Sahand; Crawford, Curran; Djilali, Ned

    2015-12-23

    This paper collects and synthesizes the technical requirements, implementation, and validation methods for quasi-steady agent-based simulations of interconnectionscale models with particular attention to the integration of renewable generation and controllable loads. Approaches for modeling aggregated controllable loads are presented and placed in the same control and economic modeling framework as generation resources for interconnection planning studies. Model performance is examined with system parameters that are typical for an interconnection approximately the size of the Western Electricity Coordinating Council (WECC) and a control area about 1/100 the size of the system. These results are used to demonstrate and validate the methods presented.

  7. Interconnect modeling using integrated time-domain and frequency-domain techniques

    SciTech Connect

    You, Hong; Yeh, Chune-Sin; Gadepally, B.

    1995-12-31

    This paper presents an integrated time- and-frequency-domain technique for characterization and modeling of parasitic effects associated with interconnects. This technique enables direct measurements of critical transient as well as frequency responses of interconnects; accurate and efficient SPICE model extraction for coupled lines; and cross-domain verification of the measured data as well as the extracted models. To illustrate its application this technique is applied to characterize and extract the equivalent circuit model of the I/O bus on a real-world printed circuit board.

  8. Silicon nanophotonic integrated devices enabling multiplexed on-chip optical interconnects

    NASA Astrophysics Data System (ADS)

    Dai, Daoxin; Wang, Jian; Chen, Sitao

    2015-05-01

    Advanced multiplexing technologies including wavelength-division-multiplexing (WDM), polarization-division multiplexing (PDM), and mode-division multiplexing (MDM) have been utilized as a cost-effective solution to enhance the capacity of an optical-interconnect link. The on-chip (de)multiplexers, including WDM filters, PDM devices, and MDM devices, are the most important key components in a multi-channel multiplexed optical interconnect system. Hybrid (de)multiplexer to enable various multiplexing technologies simultaneously are becoming more and more important to achieve many channels. In this paper we give a review for our recent work on silicon photonic integrated devices for realizing multi-channel multiplexed on-chip optical interconnects.

  9. A process chain for integrating microfluidic interconnection elements by micro-overmoulding of thermoplastic elastomers

    NASA Astrophysics Data System (ADS)

    Attia, U. M.; Alcock, J. R.

    2010-05-01

    This paper presents a process chain for in-line integration of microfluidic interconnection elements by a variant of micro-injection moulding (µIM). A SEBS-based thermoplastic elastomer (TPE) was moulded over polymethylmethacrylate (PMMA) to produce a hybrid microfluidic structure with an aspect ratio of 2. The process chain implemented micro-milling for fabricating micro-structured tool inserts, and µIM and micro-overmoulding was used for replication. A two-plate mould was used for moulding the substrate, whilst a three-plate mould with a replaceable insert was used for TPE overmoulding. The presented application was an interconnect system for a microfluidic device, which enabled direct fitting of standard tubes into microfluidic substrates. A leakage test showed that the interconnection was leak-proof within a range of flow rates between 0.32 and 0.62 ml min-1.

  10. Solder flow over fine line PWB surface finishes

    SciTech Connect

    Hosking, F.M.; Hernandez, C.L.

    1998-08-01

    The rapid advancement of interconnect technology has stimulated the development of alternative printed wiring board (PWB) surface finishes to enhance the solderability of standard copper and solder-coated surfaces. These new finishes are based on either metallic or organic chemistries. As part of an ongoing solderability study, Sandia National Laboratories has investigated the solder flow behavior of two azole-based organic solderability preservations, immersion Au, immersion Ag, electroless Pd, and electroless Pd/Ni on fine line copper features. The coated substrates were solder tested in the as-fabricated and environmentally-stressed conditions. Samples were processed through an inerted reflow machine. The azole-based coatings generally provided the most effective protection after aging. Thin Pd over Cu yielded the best wetting results of the metallic coatings, with complete dissolution of the Pd overcoat and wetting of the underlying Cu by the flowing solder. Limited wetting was measured on the thicker Pd and Pd over Ni finishes, which were not completely dissolved by the molten solder. The immersion Au and Ag finishes yielded the lowest wetted lengths, respectively. These general differences in solderability were directly attributed to the type of surface finish which the solder came in contact with. The effects of circuit geometry, surface finish, stressing, and solder processing conditions are discussed.

  11. Multichip module with planar-integrated free-space optical vector-matrix-type interconnects

    NASA Astrophysics Data System (ADS)

    Gruber, Matthias

    2004-01-01

    Even in the semiconductor industry, free-space optical technology is nowadays seen as a prime option for solving the continually aggravating problem with VLSI chips, namely, that the interconnect technology has failed to keep pace with the increase in communication volume. To make free-space optics compatible with established lithography-based design and fabrication techniques the concept of planar integration was proposed approximately a decade ago. Here its evolution into a photonic microsystems engineering concept is described. For demonstration, a multichip module with planar-integrated free-space optical vector-matrix-type interconnects was designed and built. It contains flip-chip-bonded vertical-cavity surface emitting laser arrays and a hybrid chip with an array of multiple-quantum-well p-i-n diodes on top of a standard complementary metal-oxide semiconductor circuit as key optoelectronic hardware components. The optical system is integrated into a handy fused-silica substrate and fabricated with surface-relief diffractive phase elements. It has been optimized for the given geometrical and technological constraints and provides a good interconnection performance, as was verified in computer simulations on the basis of ray tracing and in practical experiments.

  12. Soldering tool heats workpieces and applies solder in one operation

    NASA Technical Reports Server (NTRS)

    Gudkese, V. W.

    1966-01-01

    Fountain-pen type soldering iron heats workpieces and applies solder to joints in densely packed electronics assemblies. The basic soldering tool is used with different-sized orifice tips, eliminating the need for an assortment of conventional soldering guns.

  13. Exabits/s integrated photonic interconnection technology for flexible data-centric optical networks

    NASA Astrophysics Data System (ADS)

    Binh, Le N.; Tao, Thomas W.; Ning, Gordon L.

    2016-03-01

    Optical networking is evolving from classical service-provider base data-center centric (DCC) internetworking environment with massive capacity, hence demanding novel optical switching and interconnecting technologies. The traditional telecom networks are under a flattening transformation to meet challenges from DCC networks for massive capacity serving in order of multi-Pb/s. We present proposed distributed and concentric data center based networks and the essential optical interconnection technologies, from the photonic kernels to electronic and optoelectronic server clusters, in both passive and active structures. Optical switching devices and integrated matrices are proposed composing of tunable (bandwidth and center wavelength) optical filters and switches as well as resonant microring modulators (μRM)(switching and spectral demux/mux) for multi-wavelength flexible-bandwidth optical channels of aggregate capacity reaching Ebps. The design principles and some experimental results are also reported.

  14. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    PubMed

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers. PMID:27472614

  15. Agent-Based Simulation for Interconnection-Scale Renewable Integration and Demand Response Studies

    DOE PAGESBeta

    Chassin, David P.; Behboodi, Sahand; Crawford, Curran; Djilali, Ned

    2015-12-23

    This paper collects and synthesizes the technical requirements, implementation, and validation methods for quasi-steady agent-based simulations of interconnectionscale models with particular attention to the integration of renewable generation and controllable loads. Approaches for modeling aggregated controllable loads are presented and placed in the same control and economic modeling framework as generation resources for interconnection planning studies. Model performance is examined with system parameters that are typical for an interconnection approximately the size of the Western Electricity Coordinating Council (WECC) and a control area about 1/100 the size of the system. These results are used to demonstrate and validate the methodsmore » presented.« less

  16. Design and fabrication of optical polymer waveguide devices for optical interconnects and integrated optical coherence tomography

    NASA Astrophysics Data System (ADS)

    Jiang, Guomin

    Optical interconnects is a promising technique to boost the speed of electronic systems through replacing high speed electrical data buses using optical ones. Optical coherence tomography is an attractive imaging technique that has been widely used in medical imaging applications with capability of high resolution subsurface cross sectional imaging in living tissues. Both the optical interconnects and the optical coherence tomography imaging may benefit from the use of integrated optics technology in particular polymer waveguides that can be designed and fabricated to improve the device capability, system compactness, and performance reliability. In this dissertation, we first present our innovative design and realization on the polymer waveguides with 45° integrated mirrors for optical interconnects using the vacuum assisted microfluidic (VAM) soft lithography. VAM is a new microfluidic based replication technique which can be utilized to improve the performance of imprinted devices by eliminating the residue planar layer and accomplish complex devices incorporating different materials in the same layer. A prism-assisted inclined UV lithography technique is introduced to increase the slanted angles of the side walls of the microstructures and to fabricate multidirectional slanted microstructures. It is also used to fabricate 45° integrated mirrors in polymer waveguides to support surface normal optical coupling for optical interconnects. A dynamic card-to-backplane optical interconnects system has also been demonstrated based on polymer waveguides with tunable optofluidic couplers. The operation of the tunable optofluidic coupler is accomplished by controlling the position of air bubbles and index matching liquid in the perpendicular microfluidic channel for refractive index modulation. The dynamic activation and deactivation of the backplane optofluidic couplers can save the optical signal power. 10 Gbps eye diagrams of the dynamic optical interconnect link

  17. Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

    PubMed

    Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

    2016-06-22

    We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals. PMID:27250997

  18. Soldering instrument safety improvements

    DOEpatents

    Kosslow, William J.; Giron, Ronald W.

    1996-01-01

    A safe soldering device includes a retractable heat shield which can be moved between a first position in which the solder tip of the device is exposed for soldering operation and a second position in which the solder tip is covered by the heat shield. Preferably, the heat shield is biased towards the second position and may be locked in the first position for ease of use. When the soldering device is equipped with a vacuum system, the heat shield may serve to guide the flow of gases and heat from the solder tip away from the work area. The heat shield is preferably made of non-heatsinking plastic.

  19. Advanced soldering processes

    SciTech Connect

    Jellison, J.L.; Golden, J.; Frear, D.R.; Hosking, F.M.; Keicher, D.M.; Yost, F.G.

    1993-02-20

    Advanced soldering processes are discussed in a complete manner. The ability to meet the needs of electronic manufacturing, while addressing the environmental issues are challenging goals. Government regulations mandate the elimination of most solvents in solder flux removal. Alternative approaches to promoting wetting are discussed. Inert atmosphere soldering, acid vapor fluxless soldering, atomic and ionic hydrogen as reactive atmospheres, fluxless laser soldering in a controlled atmosphere are offered as soldering mechanisms for the future. Laser are discussed as alternate heat sources. Various types of lasers, advantages of lasers, and fiber optic beam delivery are considered.

  20. Integrated receiver architectures for board-to-board free-space optical interconnects

    NASA Astrophysics Data System (ADS)

    Wu, Feiyang; Vj, Logeeswaran; Islam, M. Saif; Horsley, David A.; Walmsley, Robert G.; Mathai, Sagi; Houng, Denny; Tan, Michael R. T.; Wang, Shih-Yuan

    2009-06-01

    In many computer and server communications copper cables and wires are currently being used for data transmission and interconnects. However, due to significant shortcomings, such as long transmission time, high noise level, unstable electrical properties, and high power consumption for cooling, researchers are increasingly turning their research interests toward alternatives, such as fiber optic interconnects and free-space optical communication technologies. In this paper, we present design considerations for an integrated receiver for high-speed free-space line-of-sight optical interconnects for distortion-free data transmission in an environment with mechanical vibrations and air turbulences. The receiver consists of an array of high-speed photodiodes for data communication and an array of quadrant photodiodes for real-time beam tracking in order to compensate for the beam misalignment caused by vibrations in servers. Different configurations for spatially positioning the quadrant and data photodiodes are discussed for 4×4 and 9×9 multielement optical detector arrays. We also introduce a new beam tracking device, termed the strip quadrant photodiodes, in order to accurately track highly focused optical beams with very small beam diameter.

  1. Laser forward transfer of solder paste for microelectronics fabrication

    NASA Astrophysics Data System (ADS)

    Mathews, Scott A.; Charipar, Nicholas A.; Auyeung, Ray C.; Kim, Heungsoo; Piqué, Alberto

    2015-03-01

    The progressive miniaturization of electronic devices requires an ever-increasing density of interconnects attached via solder joints. As a consequence, the overall size and spacing (or pitch) of these solder joint interconnects keeps shrinking. When the pitch between interconnects decreases below 200 μm, current technologies, such as stencil printing, find themselves reaching their resolution limit. Laser direct-write (LDW) techniques based on laser-induced forward transfer (LIFT) of functional materials offer unique advantages and capabilities for the printing of solder pastes. At NRL, we have demonstrated the successful transfer, patterning, and subsequent reflow of commercial Pb-free solder pastes using LIFT. Transfers were achieved both with the donor substrate in contact with the receiving substrate and across a 25 μm gap, such that the donor substrate does not make contact with the receiving substrate. We demonstrate the transfer of solder paste features down to 25 μm in diameter and as large as a few hundred microns, although neither represents the ultimate limit of the LIFT process in terms of spatial dimensions. Solder paste was transferred onto circular copper pads as small as 30 μm and subsequently reflowed, in order to demonstrate that the solder and flux were not adversely affected by the LIFT process.

  2. PWB solder wettability after simulated storage

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.

    1996-03-01

    A new solderability test method has been developed at Sandia National Laboratories that simulates the capillary flow physics of solders on circuit board surfaces. The solderability test geometry was incorporated on a circuit board prototype that was developed for a National Center for Manufacturing Sciences (NCMS) program. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, NCMS, and several PWB fabricators (AT&T, IBM, Texas Instruments, United Technologies/Hamilton Standard and Hughes Aircraft) to advance PWB interconnect technology. The test was used to investigate the effects of environmental prestressing on the solderability of printed wiring board (PWB) copper finishes. Aging was performed in a controlled chamber representing a typical indoor industrial environment. Solderability testing on as-fabricated and exposed copper samples was performed with the Sn-Pb eutectic solder at four different reflow temperatures (215, 230, 245 and 260{degrees}C). Rosin mildly activated (RMA), low solids (LS), and citric acid-based (CA) fluxes were included in the evaluation. Under baseline conditions, capillary flow was minimal at the lowest temperatures with all fluxes. Wetting increased with temperature at both baseline and prestressing conditions. Poor wetting, however, was observed at all temperatures with the LS flux. Capillary flow is effectively restored with the CA flux.

  3. Mechanical Solder Characterisation Under High Strain Rate Conditions

    NASA Astrophysics Data System (ADS)

    Meier, Karsten; Roellig, Mike; Wiese, Steffen; Wolter, Klaus-Juergen

    2010-11-01

    Using a setup for high strain rate tensile experiments the mechanical behavior of two lead-free tin based solders is investigated. The first alloy is SnAg1.3Cu0.5Ni. The second alloy has a higher silver content but no addition of Ni. Solder joints are the main electrical, thermal and mechanical interconnection technology on the first and second interconnection level. With the recent rise of 3D packaging technologies many novel interconnection ideas are proposed with innovative or visionary nature. Copper pillar, stud bump, intermetallic (SLID) and even spring like joints are presented in a number of projects. However, soldering will remain one of the important interconnect technologies. Knowing the mechanical properties of solder joints is important for any reliability assessment, especially when it comes to vibration and mechanical shock associated with mobile applications. Taking the ongoing miniaturization and linked changes in solder joint microstructure and mechanical behavior into account the need for experimental work on that issue is not satisfied. The tests are accomplished utilizing miniature bulk specimens to match the microstructure of real solder joints as close as possible. The dogbone shaped bulk specimens have a crucial diameter of 1 mm, which is close to BGA solder joints. Experiments were done in the strain rate range from 20 s-1 to 600 s-1. Solder strengthening has been observed with increased strain rate for both SAC solder alloys. The yield stress increases by about 100% in the investigated strain rate range. The yield level differs strongly. A high speed camera system was used to assist the evaluation process of the stress and strain data. Besides the stress and strain data extracted from the experiment the ultimate fracture strain is determined and the fracture surfaces are evaluated using SEM technique considering rate dependency.

  4. Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

    2001-01-01

    In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

  5. Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors

    NASA Astrophysics Data System (ADS)

    Chen, Long; Preston, Kyle; Manipatruni, Sasikanth; Lipson, Michal

    2009-08-01

    We report an optical link on silicon using micrometer-scale ring-resonator enhanced silicon modulators and waveguide-integrated germanium photodetectors. We show 3 Gbps operation of the link with 0.5 V modulator voltage swing and 1.0 V detector bias. The total energy consumption for such a link is estimated to be ~120 fJ/bit. Such compact and low power monolithic link is an essential step towards large-scale on-chip optical interconnects for future microprocessors.

  6. Properties of Cerium Containing Lead Free Solder

    NASA Astrophysics Data System (ADS)

    Xie, Huxiao

    With increasing concerns of the intrinsic toxicity of lead (Pb) in electronics, a series of tin (Sn) based alloys involving silver (Ag) and copper (Cu) have been proposed as replacements for Pb-Sn solder and widely accepted by industry. However, they have a higher melting point and often exhibit poorer damage tolerance than Pb-Sn alloys. Recently, a new class of alloys with trace amount of rare-earth (RE) elements has been discovered and investigated. In previous work from Prof. Chawla's group, it has been shown that cerium (Ce)-based Pb-free solder are less prone to oxidation and Sn whiskering, and exhibit desirable attributes of microstructural refinement and enhanced ductility relative to lanthanum (La)-based Sn-3.9Ag-0.7Cu (SAC) alloy. Although the formation of RESn3 was believed to be directly responsible for the enhanced ductility in RE-containing SAC solder by allowing microscopic voids to nucleate throughout the solder volume, this cavitation-based mechanism needs to be validated experimentally and numerically. Additionally, since the previous study has exhibited the realistic feasibility of Ce-based SAC lead-free solder alloy as a replacement to conventional SAC alloys, in this study, the proposed objective focuses on the in in-depth understanding of mechanism of enhanced ductility in Ce-based SAC alloy and possible issues associated with integration of this new class of solder into electronic industry, including: (a) study of long-term thermal and mechanical stability on industrial metallization, (b) examine the role of solder volume and wetting behavior of the new solder, relative to Sn-3.9Ag-0.7Cu alloys, (c) conduct experiments of new solder alloys in the form of mechanical shock and electromigration. The research of this new class alloys will be conducted in industrially relevant conditions, and the results would serve as the first step toward integration of these new, next generation solders into the industry.

  7. Integrated optical interconnection for polymeric planar lightwave circuit device using roll-to-roll ultraviolet imprint

    NASA Astrophysics Data System (ADS)

    Cho, Sang Uk; Kang, Ho Ju; Chang, Sunghwan; Choi, Doo-sun; Kim, Chang-Seok; Jeong, Myung Yung

    2014-08-01

    We propose an integrated structure that combines chip and fiber array blocks for optical interconnection with a polymeric planar lightwave circuit (PLC) device using the roll-to-roll imprint process. The fiber array blocks and PLC chip of the integrated structure are fabricated on the same substrate, and the alignments in the three spatial directions were established with the insertion of an optical fiber. The characteristics of the integrated structure were evaluated by fabricating a 1×2 optical splitter device. The structure had an insertion loss of 3.9 dB, and the optical uniformity of the channel was 0.1 dB, indicating that the same performance for an active alignment can be expected.

  8. Integrated Energy-Water Planning in the Western and Texas Interconnections

    SciTech Connect

    Vincent Tidwell; John Gasper; Robert Goldstein; Jordan Macknick; Gerald Sehlke; Michael Webber; Mark Wigmosta

    2013-07-01

    While long-term regional electricity transmission planning has traditionally focused on cost, infrastructure utilization, and reliability, issues concerning the availability of water represent an emerging issue. Thermoelectric expansion must be considered in the context of competing demands from other water use sectors balanced with fresh and non-fresh water supplies subject to climate variability. An integrated Energy-Water Decision Support System (DSS) is being developed that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water availability and cost for long-range transmission planning. The project brings together electric transmission planners (Western Electricity Coordinating Council and Electric Reliability Council of Texas) with western water planners (Western Governors’ Association and the Western States Water Council). This paper lays out the basic framework for this integrated Energy-Water DSS.

  9. Hybrid microcircuit board assembly with lead-free solders

    SciTech Connect

    Vianco, P.T.; Hernandez, C.L.; Rejent, J.A.

    2000-01-11

    An assessment was made of the manufacturability of hybrid microcircuit test vehicles assembled using three Pb-free solder compositions 96.5Sn--3.5Ag (wt.%), 91.84Sn--3.33Ag--4.83Bi, and 86.85Sn--3.15Ag--5.0Bi--5.0Au. The test vehicle substrate was 96% alumina; the thick film conductor composition was 76Au--21Pt--3Pd. Excellent registration between the LCCC or chip capacitor packages and the thick film solder pads was observed. Reduced wetting of bare (Au-coated) LCCC castellations was eliminated by hot solder dipping the I/Os prior to assembly of the circuit card. The Pb-free solders were slightly more susceptible to void formation, but not to a degree that would significantly impact joint functionality. Microstructural damage, while noted in the Sn-Pb solder joints, was not observed in the Pb-free interconnects.

  10. Photonic bandgap crystal resonator enhanced, laser controlled modulations of optical interconnects for photonic integrated circuits.

    PubMed

    Teo, Selin H G; Liu, A Q; Zhang, J B; Hong, M H; Singh, J; Yu, M B; Singh, N; Lo, G Q

    2008-05-26

    Ultrafast high-density photonic integrated circuit devices (PICDs) are not easily obtained using traditional index-guiding mechanisms. In this paper, photonic bandgap crystal resonator enhanced, laser-controlled modulations of optical interconnect PICDs were achieved in slab-type mix-guiding configuration - through developed CMOS-compatible processing technologies. The devices, with smallest critical dimensions of 90 nm have footprints of less than 5 x 5 microm(2). Quality-factors an order larger than previously realized was achieved. Through use of effective coupling structures; simultaneous alignment for probing and pumping laser beams, optical measurements of both instantaneous free carriers induced device modulations were obtained together with thermo-optical effects characterizations. PMID:18545494

  11. Intra-Chip Free-Space Optical Interconnect: System, Device, Integration and Prototyping

    NASA Astrophysics Data System (ADS)

    Ciftcioglu, Berkehan

    Currently, on-chip optical interconnect schemes already proposed utilize circuit switching using wavelength division multiplexing (WDM) or all-optical packet switching, all based on planar optical waveguides and related photonic devices such as microrings. These proposed approaches pose significant challenges in latency, energy efficiency, integration, and scalability. This thesis presents a new alternative approach by utilizing free-space optics. This 3-D integrated intra-chip free-space optical interconnect (FSOI) leverages mature photonic devices such as integrated lasers, photodiodes, microlenses and mirrors. It takes full advantages of the latest developments in 3-D integration technologies. This interconnect system provides point-to-point free-space optical links between any two communication nodes to construct an all-to-all intra-chip communication network with little or no arbitration. Therefore, it has significant networking advantages over conventional electrical and waveguide-based optical interconnects. An FSOI system is evaluated based on the real device parameters, predictive technology models and International Roadmap of Semiconductor's predictions. A single FSOI link achieves 10-Gbps data rate with 0.5-pJ/bit energy efficiency and less than 10--12 bit-error-rate (BER). A system using this individual link can provide scalability up to 36 nodes, providing 10-Tbps aggregate bandwidth. A comparison analysis performed between a WDM-based waveguide interconnect system and the proposed FSOI system shows that FSOI achieves better energy efficiency than the WDM one as the technology scales. Similarly, network simulation on a 16-core microprocessor using the proposed FSOI system instead of mesh networks has been shown to speed up the system by 12% and reduce the energy consumption by 33%. As a part of the development of a 3-D integrated FSOI system, operating at 850 nm with a 10-Gbps data rate per optical link, the photonics devices and optical components are

  12. An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

    SciTech Connect

    Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark; Vianco, Paul Thomas; Zender, Gary L.; Hlava, Paul Frank; Rejent, Jerome Andrew

    2008-09-01

    The assembly of the BDYE detector requires the attachment of sixteen silicon (Si) processor dice (eight on the top side; eight on the bottom side) onto a low-temperature, co-fired ceramic (LTCC) substrate using 63Sn-37Pb (wt.%, Sn-Pb) in a double-reflow soldering process (nitrogen). There are 132 solder joints per die. The bond pads were gold-platinum-palladium (71Au-26Pt-3Pd, wt.%) thick film layers fired onto the LTCC in a post-process sequence. The pull strength and failure modes provided the quality metrics for the Sn-Pb solder joints. Pull strengths were measured in both the as-fabricated condition and after exposure to thermal cycling (-55/125 C; 15 min hold times; 20 cycles). Extremely low pull strengths--referred to as the low pull strength phenomenon--were observed intermittently throughout the product build, resulting in added program costs, schedule delays, and a long-term reliability concern for the detector. There was no statistically significant correlation between the low pull strength phenomenon and (1) the LTCC 'sub-floor' lot; (2) grit blasting the LTCC surfaces prior to the post-process steps; (3) the post-process parameters; (4) the conductor pad height (thickness); (5) the dice soldering assembly sequence; or (5) the dice pull test sequence. Formation of an intermetallic compound (IMC)/LTCC interface caused by thick film consumption during either the soldering process or by solid-state IMC formation was not directly responsible for the low-strength phenomenon. Metallographic cross sections of solder joints from dice that exhibited the low pull strength behavior, revealed the presence of a reaction layer resulting from an interaction between Sn from the molten Sn-Pb and the glassy phase at the TKN/LTCC interface. The thick film porosity did not contribute, explicitly, to the occurrence of reaction layer. Rather, the process of printing the very thin conductor pads was too sensitive to minor thixotropic changes to ink, which resulted in

  13. Intra-Chip Free-Space Optical Interconnect: System, Device, Integration and Prototyping

    NASA Astrophysics Data System (ADS)

    Ciftcioglu, Berkehan

    Currently, on-chip optical interconnect schemes already proposed utilize circuit switching using wavelength division multiplexing (WDM) or all-optical packet switching, all based on planar optical waveguides and related photonic devices such as microrings. These proposed approaches pose significant challenges in latency, energy efficiency, integration, and scalability. This thesis presents a new alternative approach by utilizing free-space optics. This 3-D integrated intra-chip free-space optical interconnect (FSOI) leverages mature photonic devices such as integrated lasers, photodiodes, microlenses and mirrors. It takes full advantages of the latest developments in 3-D integration technologies. This interconnect system provides point-to-point free-space optical links between any two communication nodes to construct an all-to-all intra-chip communication network with little or no arbitration. Therefore, it has significant networking advantages over conventional electrical and waveguide-based optical interconnects. An FSOI system is evaluated based on the real device parameters, predictive technology models and International Roadmap of Semiconductor's predictions. A single FSOI link achieves 10-Gbps data rate with 0.5-pJ/bit energy efficiency and less than 10--12 bit-error-rate (BER). A system using this individual link can provide scalability up to 36 nodes, providing 10-Tbps aggregate bandwidth. A comparison analysis performed between a WDM-based waveguide interconnect system and the proposed FSOI system shows that FSOI achieves better energy efficiency than the WDM one as the technology scales. Similarly, network simulation on a 16-core microprocessor using the proposed FSOI system instead of mesh networks has been shown to speed up the system by 12% and reduce the energy consumption by 33%. As a part of the development of a 3-D integrated FSOI system, operating at 850 nm with a 10-Gbps data rate per optical link, the photonics devices and optical components are

  14. Solderability test system

    DOEpatents

    Yost, Fred; Hosking, Floyd M.; Jellison, James L.; Short, Bruce; Giversen, Terri; Reed, Jimmy R.

    1998-01-01

    A new test method to quantify capillary flow solderability on a printed wiring board surface finish. The test is based on solder flow from a pad onto narrow strips or lines. A test procedure and video image analysis technique were developed for conducting the test and evaluating the data. Feasibility tests revealed that the wetted distance was sensitive to the ratio of pad radius to line width (l/r), solder volume, and flux predry time.

  15. Solderability test system

    DOEpatents

    Yost, F.; Hosking, F.M.; Jellison, J.L.; Short, B.; Giversen, T.; Reed, J.R.

    1998-10-27

    A new test method to quantify capillary flow solderability on a printed wiring board surface finish. The test is based on solder flow from a pad onto narrow strips or lines. A test procedure and video image analysis technique were developed for conducting the test and evaluating the data. Feasibility tests revealed that the wetted distance was sensitive to the ratio of pad radius to line width (l/r), solder volume, and flux predry time. 11 figs.

  16. Soldering In Space Investigation

    NASA Technical Reports Server (NTRS)

    2004-01-01

    This video captures Mike Fincke melting solder during the first set of planned In-Space Soldering Investigation (ISSI) experiments onboard the International Space Station (ISS). In the video, Fincke touches the tip of the soldering iron to a wire wrapped with rosin-core solder. Review of the experiment video revealed melting kinetics, wetting characteristics, and equilibrium shape attainment of the solder charge. The main photograph shows the results of feeding solder wire onto a heated surface. Here the solder is still attached with the spool seen floating in the foreground of the image. The inset photograph at right, shows a set of three simple melting experiments in which the solder, not affected by gravity, achieved an unexpected equilibrium football shape on the wire. Samples returned to Earth were examined for porosity and flux distribution as well as micro structural development. ISSI's purpose was to find out how solder behaves in a weightless environment and promote our knowledge of fabrication and repair techniques that might be employed during extended space exploration missions.

  17. Soldering In Space Investigation

    NASA Technical Reports Server (NTRS)

    2004-01-01

    This video captures Mike Fincke melting solder during the first set of planned In-Space Soldering Investigation (ISSI) experiments onboard the International Space Station (ISS). In the video, Fincke touches the tip of the soldering iron to a wire wrapped with rosin-core solder.Review of the experiment video revealed melting kinetics, wetting characteristics, and equilibrium shape attainment of the solder charge. The main photograph shows the results of feeding solder wire onto a heated surface. Here the solder is still attached with the spool seen floating in the foreground of the image. The inset photograph at right, shows a set of three simple melting experiments in which the solder, not affected by gravity, achieved an unexpected equilibrium football shape on the wire. Samples returned to Earth were examined for porosity and flux distribution as well as micro structural development. ISSI's purpose was to find out how solder behaves in a weightless environment and promote our knowledge of fabrication and repair techniques that might be employed during extended space exploration missions.

  18. Laser soldering of Sn-Ag solder

    SciTech Connect

    Felipe, T.S. de; O`Laughlin, D.

    1994-12-31

    In recent years, there has been pressure from federal and state environmental agencies to find substitutes for Pb-containing solders. Our research team has been studying SnAg solder as a possible alternative. in comparison to Sn-Pb solder, SnAg poses less of an environmental threat and can be used for higher temperature applications such as in avionics or under the hood in automobiles. Our study also compares the processes of laser and IR reflow soldering and their effects on microstructure, microstructure stability, and mechanical and thermomechanical properties of joints. Several laser soldered joints were produced by varying beam power and scan rate. Microhardness was measured and joint microstructure analyzed in order to find the optimum parameters. Laser soldered joints with optimum parameters were then exposed to temperatures between 40{degrees}C and 190{degrees}C for times up to 300 days along with conventional IR reflowed joints. The purpose was to determine the long term microstructural stability and mechanical reliability of the joints for the two processes. The results obtained show that there is a processing window where good quality laser solder joints can be produced. Our study also revealed that, initially, laser-produced joints differed significantly in microstructural details and were superior to IR reflowed joints in both microhardness and microstructure. As the samples were aged, it was observed that the microstructures and microhardnesses became increasingly similar. Finally, after significant aging, voids were found at the intermetallic layers formed at Cu or Cu alloy substrates and the joints began to fail.

  19. Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

    NASA Astrophysics Data System (ADS)

    Aggarwal, Ankur

    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

  20. On integral input-to-state stability for a feedback interconnection of parameterised discrete-time systems

    NASA Astrophysics Data System (ADS)

    Noroozi, N.; Khayatian, A.; Ahmadizadeh, S.; Karimi, H. R.

    2016-05-01

    This paper addresses integral input-to-state stability (iISS) for a feedback interconnection of parameterised discrete-time systems involving two subsystems. Particularly, we give a construction for a smooth iISS Lyapunov function for the whole system from the sum of nonlinearly weighted Lyapunov functions of individual subsystems. Motivations for such a construction are given. We consider two main cases. The first one investigates iISS for the whole system when both subsystems are iISS. The second one gives iISS for the interconnected system when one of subsystems is allowed to be input-to-state stable. The approach is also valid for both discrete-time cascades and a feedback interconnection of iISS and static systems. Examples are given to illustrate the effectiveness of the results.

  1. Reduced oxide soldering activation (ROSA) PWB solderability testing

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.; Reed, J.; Tench, D.M.; White, J.

    1996-02-01

    The effect of ROSA pretreatment on the solderability of environmentally stressed PWB test coupons was investigated. The PWB surface finish was an electroplated, reflowed solder. Test results demonstrated the ability to recover plated-through-hole fill of steam aged samples with solder after ROSA processing. ROSA offers an alternative method for restoring the solderability of aged PWB surfaces.

  2. SNL initiatives in electronic fluxless soldering

    SciTech Connect

    Hosking, F.M.; Frear, D.R.; Vianco, P.T.; Keicher, D.M.

    1991-01-01

    Conventional soldering of electronic components generally requires the application of a chemical flux to promote solder wetting and flow. Chlorofluorocarbons (CFC) and halogenated solvents are normally used to remove the resulting flux residues. While such practice has been routinely accepted throughout the electronics industry, the environmental impact of hazardous solvents on ozone depletion will eventually limit or prevent their use. Solvent substitution or alternative technologies must be developed to meet these goals. Sandia National Laboratories, Albuquerque has a comprehensive environmentally conscious electronics manufacturing program underway that is funded by the DOE Office of Technology Development. Primary elements of the integrated task are the characterization and development of alternative fluxless soldering technologies that would eliminate circuit board cleaning associated with flux residue removal. Storage and handling of hazardous solvents and mixed solvent-flux waste would be consequently reduced during electronics soldering. This paper will report on the progress of the SNL fluxless soldering initiative. Emphasis is placed on the use of controlled atmospheres, laser heating, and ultrasonic soldering.

  3. Compound solder joints

    NASA Technical Reports Server (NTRS)

    Batista, R. I.; Simonson, R. B.

    1976-01-01

    Joining technique prevents contamination, may be used to join dissimilar metal tubes, minimizes fluid and gas entrapment, expedites repairs, and can yield joints having leakage rates less than 0.000001 standard cubic cm He/min. Components of joint are solder sleeve, two solder rings, Teflon sleeve, and tubing to be joined.

  4. Solder Reflow Failures in Electronic Components During Manual Soldering

    NASA Technical Reports Server (NTRS)

    Teverovsky, Alexander; Greenwell, Chris; Felt, Frederick

    2008-01-01

    This viewgraph presentation reviews the solder reflow failures in electronic components that occur during manual soldering. It discusses the specifics of manual-soldering-induced failures in plastic devices with internal solder joints. The failure analysis turned up that molten solder had squeezed up to the die surface along the die molding compound interface, and the dice were not protected with glassivation allowing solder to short gate and source to the drain contact. The failure analysis concluded that the parts failed due to overheating during manual soldering.

  5. Lead-free solder

    DOEpatents

    Anderson, Iver E.; Terpstra, Robert L.

    2001-05-15

    A Sn--Ag--Cu eutectic alloy is modified with one or more low level and low cost alloy additions to enhance high temperature microstructural stability and thermal-mechanical fatigue strength without decreasing solderability. Purposeful fourth or fifth element additions in the collective amount not exceeding about 1 weight % (wt. %) are added to Sn--Ag--Cu eutectic solder alloy based on the ternary eutectic Sn--4.7%Ag--1.7%Cu (wt. %) and are selected from the group consisting essentially of Ni, Fe, and like-acting elements as modifiers of the intermetallic interface between the solder and substrate to improve high temperature solder joint microstructural stability and solder joint thermal-mechanical fatigue strength.

  6. Removing Dross From Molten Solder

    NASA Technical Reports Server (NTRS)

    Webb, Winston S.

    1990-01-01

    Automatic device helps to assure good solder connections. Machine wipes dross away from area on surface of molten solder in pot. Sweeps across surface of molten solder somewhat in manner of windshield wiper. Each cycle of operation triggered by pulse from external robot. Equipment used wherever precise, automated soldering must be done to military specifications.

  7. Stress-relieved solder joints

    NASA Technical Reports Server (NTRS)

    Zemenick, C. J.

    1980-01-01

    Mechanical stress on solder joints is reduced by procedure for soldering electronic components to circuit boards. Procedure was developed for radio-frequency (RF) strip-line circuits, for which dimensions must be carefully controlled to minimize parasitic capacitance and inductance. Procedure consists of loosening component from its mounting after each lead is soldered relieving induced stresses before next soldering step.

  8. Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

    NASA Astrophysics Data System (ADS)

    Apostolopoulos, Dimitrios; Bakopoulos, Paraskevas; Kalavrouziotis, Dimitrios; Giannoulis, Giannis; Kanakis, Giannis; Iliadis, Nikos; Spatharakis, Christos; Bauwelinck, Johan; Avramopoulos, Hercules

    2014-03-01

    New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of opticalinterconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies.

  9. Solder Bonding for Power Transistors

    NASA Technical Reports Server (NTRS)

    Snytsheuvel, H. A.; Mandel, H.

    1985-01-01

    Indium solder boosts power rating and facilitates circuit changes. Efficient heat conduction from power transistor to heat sink provided by layer of indium solder. Low melting point of indium solder (141 degrees C) allows power transistor to be removed, if circuit must be reworked, without disturbing other components mounted with ordinary solder that melts at 181 degrees C. Solder allows devices operated at higher power levels than does conventional attachment by screws.

  10. Phase 2 Report: Oahu Wind Integration and Transmission Study (OWITS); Hawaiian Islands Transmission Interconnection Project

    SciTech Connect

    Woodford, D.

    2011-02-01

    This report provides an independent review including an initial evaluation of the technical configuration and capital costs of establishing an undersea cable system and examining impacts to the existing electric transmission systems as a result of interconnecting the islands

  11. Oahu Wind Integration and Transmission Study (OWITS): Hawaiian Islands Transmission Interconnection Project

    SciTech Connect

    Woodford, D.

    2011-02-01

    This report provides an independent review included an initial evaluation of the technical configuration and capital costs of establishing an undersea cable system and examining impacts to the existing electric transmission systems as a result of interconnecting the islands.

  12. Arc spraying solderable tabs to glass

    NASA Technical Reports Server (NTRS)

    Lindmayer, J.

    1981-01-01

    Tabs suitable for electrical or mechanical connections in solar cells and integrated circuits are made by spraying technique. Solder wets copper, copper bonds to aluminum, and aluminum adheres to glass. Arc spraying is automated and integrated with encapsulation, eliminating hand tabbing, improving reliability, and reducing cost.

  13. Effects of pre-stressing and flux on the flow of solder on PWB copper surfaces

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.

    1994-12-31

    A variety of test methods are available to evaluate the solderability of printed wiring board [PWB] surface finishes. A new test has been developed which better simulates the capillary flow physics of typical solder assembly processing, especially surface mount soldering. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, the National Center for Manufacturing Sciences, and several PWB fabricators (AT&T, IBM, Texas Instruments, and United Technologies Corporation/Hamilton Standard) to advance PWB interconnect systems technology. Particular attention has been given at Sandia to characterizing the effects of accelerated aging in a simulated indoor industrial environment on subsequent PWB solderability. The program`s baseline surface finish was copper. Solderability testing on ``as-fabricated`` and ``pre-stressed copper`` pad-strip geometries was performed with Sn-Pb eutectic solder and three different fluxes at four different reflow temperatures.

  14. Thermal Stress of Surface Oxide Layer on Micro Solder Bumps During Reflow

    NASA Astrophysics Data System (ADS)

    Key Chung, C.; Zhu, Z. X.; Kao, C. R.

    2015-02-01

    Micro-bumps are now being developed with diameters smaller than 10 μm. At these dimensions, only very small amounts of solder are used to form the interconnections. Surface oxidation of such small micro-bumps is a critical issue. The key question is whether the oxide film on the solder bumps acts as a barrier to formation of solder joints. In this work, the mechanical stability of the oxide layer on solder bumps was investigated. Solder bumps with 35- μm radii were heated for different times. Auger electron spectroscopy was used to determine the thickness of the oxide layer on the solder bumps. Solder bumps with known oxide layer thicknesses were then heated in a low-oxygen environment (<50 ppm) until they melted. The mechanical stability of the oxide layer was observed by use of a high-speed camera. Results showed that a 14-nm-thick oxide layer on a solder bump of radius 35 μm was able to withstand the molten solder without cracking, leading to a non-wetting solder joint. A thermal stress model of the surface oxide layer revealed that the stress varied substantially with bump size and temperature, and increased almost linearly with temperature. Upon melting, the thermal stress on the oxide increased abruptly, because of the higher thermal expansion of molten solder compared with its solid state. On the basis of the experimental results and the thermal stress model of the oxide film, the maximum oxide thickness that can be tolerated to form a solder joint was determined, e.g. 14 nm oxide can support liquid solder, and thus lead to a non-wetting condition. This work provided a new method of determination of the maximum stress of oxide film for solder joint formation.

  15. Operating Reserve Implication of Alternative Implementations of an Energy Imbalance Service on Wind Integration in the Western Interconnection: Preprint

    SciTech Connect

    Milligan, M.; Kirby, B.; King, J.; Beuning, S.

    2011-07-01

    During the past few years, there has been significant interest in alternative ways to manage power systems over a larger effective electrical footprint. Large regional transmission organizations in the Eastern Interconnection have effectively consolidated balancing areas, achieving significant economies of scale that result in a reduction in required reserves. Conversely, in the Western Interconnection there are many balancing areas, which will result in challenges if there is significant wind and solar energy development in the region. A recent proposal to the Western Electricity Coordinating Council suggests a regional energy imbalance service (EIS). To evaluate this EIS, a number of analyses are in process or are planned. This paper describes one part of an analysis of the EIS's implication on operating reserves under several alternative scenarios of the market footprint and participation. We improve on the operating reserves method utilized in the Eastern Wind Integration and Transmission Study and apply this modified approach to data from the Western Wind and Solar Integration Study.

  16. Embrittlement of surface mount solder joints by hot solder-dipped, gold-plated leads

    SciTech Connect

    Vianco, P.T.

    1993-07-01

    The detachment of beam-leaded transistors from several surface mount circuit boards following modest thermal cycling was examined. Microstructural analysis of the package leads and bonding pads from the failed units indicated that gold embrittlement was responsible for a loss of solder joint mechanical integrity that caused detachment of transistors from the circuit boards. An analysis of the hot dipping process used to remove gold from the leads prior to assembly demonstrated that the gold, although dissolved from the lead, remained in the nearby solder and was subsequently retained in the coating formed on the lead upon withdrawal from the bath. This scenario allowed gold to enter the circuit board solder joints. It was hypothesized, and later confirmed by experimental trials, that increasing the number of dips prevented gold from entering the solder coatings.

  17. Solder dross removal apparatus

    NASA Technical Reports Server (NTRS)

    Webb, Winston S. (Inventor)

    1990-01-01

    An automatic dross removal apparatus is disclosed for removing dross from the surface of a solder bath in an automated electric component handling system. A rotatable wiper blade is positioned adjacent the solder bath which skims the dross off of the surface prior to the dipping of a robot conveyed component into the bath. An electronic control circuit causes a motor to rotate the wiper arm one full rotational cycle each time a pulse is received from a robot controller as a component approaches the solder bath.

  18. Solder dross removal apparatus

    NASA Technical Reports Server (NTRS)

    Webb, Winston S. (Inventor)

    1992-01-01

    An automatic dross removal apparatus (10) is disclosed for removing dross from the surface of a solder bath (22) in an automated electric component handling system. A rotatable wiper blade (14) is positioned adjacent the solder bath (22) which skims the dross off of the surface prior to the dipping of a robot conveyed component into the bath. An electronic control circuit (34) causes a motor (32) to rotate the wiper arm (14) one full rotational cycle each time a pulse is received from a robot controller (44) as a component approaches the solder bath (22).

  19. Standards in process: Foundation and profiles of ISDN (Integrated Services Digital Network) and OSI (Open Systems Interconnection) studies

    NASA Astrophysics Data System (ADS)

    Cerni, D. M.

    1984-12-01

    Telecommunication and computer technologies are merging, stimulating such global communication projects as the Integrated Services Digital Network (ISDN) and the Open Systems Interconnection (OSI) Reference Model. The systems of standards needed to ensure worldwide success of these projects are being developed. These efforts, of unprecedented complexity, are demanding an increase in knowledgeable dedicated standards workers. This report offers background material on the meaning, significance, and changing nature of standards and their development, both in the United States and internationally.

  20. Integrating III-V, Si, and polymer waveguides for optical interconnects: RAPIDO

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Harjanne, Mikko; Offrein, Bert-Jan; Caër, Charles; Neumeyr, Christian; Malacarne, Antonio; Guina, Mircea; Sheehan, Robert N.; Peters, Frank H.; Melanen, Petri

    2016-03-01

    We present a vision for the hybrid integration of advanced transceivers at 1.3 μm wavelength, and the progress done towards this vision in the EU-funded RAPIDO project. The final goal of the project is to make five demonstrators that show the feasibility of the proposed concepts to make optical interconnects and packet-switched optical networks that are scalable to Pb/s systems in data centers and high performance computing. Simplest transceivers are to be made by combining directly modulated InP VCSELs with 12 μm SOI multiplexers to launch, for example, 200 Gbps data into a single polymer waveguide with 4 channels to connect processors on a single line card. For more advanced transceivers we develop novel dilute nitride amplifiers and modulators that are expected to be more power-efficient and temperatureinsensitive than InP devices. These edge-emitting III-V chips are flip-chip bonded on 3 μm SOI chips that also have polarization and temperature independent multiplexers and low-loss coupling to the 12 μm SOI interposers, enabling to launch up to 640 Gbps data into a standard single mode (SM) fiber. In this paper we present a number of experimental results, including low-loss multiplexers on SOI, zero-birefringence Si waveguides, micron-scale mirrors and bends with 0.1 dB loss, direct modulation of VCSELs up to 40 Gbps, +/-0.25μm length control for dilute nitride SOA, strong band edge shifts in dilute nitride EAMs and SM polymer waveguides with 0.4 dB/cm loss.

  1. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    NASA Astrophysics Data System (ADS)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  2. Acid soldering flux poisoning

    MedlinePlus

    The harmful substances in soldering fluxes are called hydrocarbons. They include: Ammonium chloride Rosin Hydrochloric acid Zinc ... Lee DC. Hydrocarbons. In: Marx JA, Hockberger RS, Walls RM, et ... Rosen's Emergency Medicine: Concepts and Clinical Practice . 8th ...

  3. Detecting Defective Solder Bonds

    NASA Technical Reports Server (NTRS)

    Paulson, R.; Barney, J.; Decker, H. J.

    1984-01-01

    Method is noncontact and nondestructive. Technique detects solder bonds in solar array of other large circuit board, using thermal-imaging camera. Board placed between heat lamp and camera. Poor joints indiated by "cold" spots on the infrared image.

  4. SOLDERING OF ALUMINUM BASE METALS

    DOEpatents

    Erickson, G.F.

    1958-02-25

    This patent deals with the soldering of aluminum to metals of different types, such as copper, brass, and iron. This is accomplished by heating the aluminum metal to be soldered to slightly above 30 deg C, rubbing a small amount of metallic gallium into the part of the surface to be soldered, whereby an aluminum--gallium alloy forms on the surface, and then heating the aluminum piece to the melting point of lead--tin soft solder, applying lead--tin soft solder to this alloyed surface, and combining the aluminum with the other metal to which it is to be soldered.

  5. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, D.B.

    1988-06-06

    Integrated circuit chips are electrically connected to a silicon wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability. 6 figs.

  6. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, David B.

    1991-01-01

    Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin metal lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability.

  7. Soldering of Thin Film-Metallized Glass Substrates

    SciTech Connect

    Hosking, F.M.; Hernandez, C.L.; Glass, S.J.

    1999-03-31

    The ability to produce reliable electrical and structural interconnections between glass and metals by soldering was investigated. Soldering generally requires premetallization of the glass. As a solderable surface finish over soda-lime-silicate glass, two thin films coatings, Cr-Pd-Au and NiCr-Sn, were evaluated. Solder nettability and joint strengths were determined. Test samples were processed with Sn60-Pb40 solder alloy at a reflow temperature of 210 C. Glass-to-cold rolled steel single lap samples yielded an average shear strength of 12 MPa. Solder fill was good. Control of the Au thickness was critical in minimizing the formation of AuSn{sub 4} intermetallic in the joint, with a resulting joint shear strength of 15 MPa. Similar glass-to-glass specimens with the Cr-Pd-Au finish failed at 16.5 MPa. The NiCr-Sn thin film gave even higher shear strengths of 20-22.5 MPa, with failures primarily in the glass.

  8. A new active solder for joining electronic components

    SciTech Connect

    SMITH,RONALD W.; VIANCO,PAUL T.; HERNANDEZ,CYNTHIA L.; LUGSCHEIDER,E.; RASS,I.; HILLEN,F.

    2000-05-11

    Electronic components and micro-sensors utilize ceramic substrates, copper and aluminum interconnect and silicon. The joining of these combinations require pre-metallization such that solders with fluxes can wet such combinations of metals and ceramics. The paper will present a new solder alloy that can bond metals, ceramics and composites. The alloy directly wets and bonds in air without the use flux or premetallized layers. The paper will present typical processing steps and joint microstructures in copper, aluminum, aluminum oxide, aluminum nitride, and silicon joints.

  9. Performance evaluation of multi-stratum resources integrated resilience for software defined inter-data center interconnect.

    PubMed

    Yang, Hui; Zhang, Jie; Zhao, Yongli; Ji, Yuefeng; Wu, Jialin; Lin, Yi; Han, Jianrui; Lee, Young

    2015-05-18

    Inter-data center interconnect with IP over elastic optical network (EON) is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resources integration among IP networks, optical networks and application stratums resources that allows to accommodate data center services. In view of this, this study extends to consider the service resilience in case of edge optical node failure. We propose a novel multi-stratum resources integrated resilience (MSRIR) architecture for the services in software defined inter-data center interconnect based on IP over EON. A global resources integrated resilience (GRIR) algorithm is introduced based on the proposed architecture. The MSRIR can enable cross stratum optimization and provide resilience using the multiple stratums resources, and enhance the data center service resilience responsiveness to the dynamic end-to-end service demands. The overall feasibility and efficiency of the proposed architecture is experimentally verified on the control plane of our OpenFlow-based enhanced SDN (eSDN) testbed. The performance of GRIR algorithm under heavy traffic load scenario is also quantitatively evaluated based on MSRIR architecture in terms of path blocking probability, resilience latency and resource utilization, compared with other resilience algorithms. PMID:26074588

  10. Silver flip chip interconnect technology and solid state bonding

    NASA Astrophysics Data System (ADS)

    Sha, Chu-Hsuan

    -section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active

  11. LTCC interconnects in microsystems

    NASA Astrophysics Data System (ADS)

    Rusu, Cristina; Persson, Katrin; Ottosson, Britta; Billger, Dag

    2006-06-01

    Different microelectromechanical system (MEMS) packaging strategies towards high packaging density of MEMS devices and lower expenditure exist both in the market and in research. For example, electrical interconnections and low stress wafer level packaging are essential for improving device performance. Hybrid integration of low temperature co-fired ceramics (LTCC) with Si can be a way for an easier packaging system with integrated electrical interconnection, and as well towards lower costs. Our research on LTCC-Si integration is reported in this paper.

  12. Inconsistencies in the Understanding of Solder Joint Reliability Physics

    NASA Technical Reports Server (NTRS)

    Wen, L.; Mon, G. R.; Ross, R. G., Jr.

    1997-01-01

    Over the years, many analytical and experimental research studies have aimed to improve the state-of-the-art assessment of solder joint integrity from a physics-of-failure perspective. Although much progress has been made, there still exist many inconsistent and even contradictory correlations and conclusions. Before discussing some of the prominent inconsistencies found in the literature, this paper reviews the fundamental physics underlying the nature of solder failure...Using the complex constitutive properties of solder, fundamental mechanical and thermomechanical proccesses can be modeled to demonstrate some of the inconsistencies in the literature.

  13. High integrity interconnection of silver submicron/nanoparticles on silicon wafer by femtosecond laser irradiation.

    PubMed

    Huang, H; Sivayoganathan, M; Duley, W W; Zhou, Y

    2015-01-16

    Welding of nanomaterials is a promising technique for constructing nanodevices with robust mechanical properties. To date, fabrication of these devices is limited because of difficulties in restricting damage to the nanomaterials during the welding process. In this work, by utilizing very low fluence (∼900 μJ cm(-2)) femtosecond (fs) laser irradiation, we have produced a metallic interconnection between two adjacent silver (Ag) submicron/nanoparticles which were fixed on a silicon (Si) wafer after fs laser deposition. No additional filler material was used, and the connected particles remain almost damage free. Observation of the morphology before and after joining and finite difference time domain simulations indicate that the interconnection can be attributed to plasmonic excitation in the Ag submicron/nanoparticles. Concentration of energy between the particles leads to local ablation followed by re-deposition of the ablated material to form a bridging link that joins the two particles. This welding technique shows potential applications in the fabrication of nanodevices. PMID:25526428

  14. Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

    DOEpatents

    Jansen, Kai W.; Maley, Nagi

    2000-01-01

    High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

  15. Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

    DOEpatents

    Jansen, Kai W.; Maley, Nagi

    2001-01-01

    High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

  16. Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics-Optics Heterogeneous Integration

    NASA Astrophysics Data System (ADS)

    Thanh Tung, Bui; Suzuki, Motohiro; Kato, Fumiki; Nemoto, Shunsuke; Watanabe, Naoki; Aoyagi, Masahiro

    2013-04-01

    High-precision integration has valuable meaning in heterogeneous convergent technology. In this paper we report on a new high-precision low-temperature bonding approach, capable of submicron alignment accuracy, based on the conventional ultrasonic flip-chip bonding technique and modified metal pad and bump elements. The interconnection pair made from a conductive-sloped hollow bonding pad (concave) and metal cone bump (convex) elements, i.e., misalignment self-correction elements, helps in aligning and maintaining the alignment between the chip and the substrate during stacking. By this method, the stacking accuracy can be improved significantly and effectively. Repeatable submicron (i.e., less than 500 nm) bonding accuracies are confirmed through experimental investigation. Moreover, reliable bond characteristics including electrical and mechanical properties are observed, validating the performance of the bonding approach. With these results, the proposed high-precision low-temperature bonding approach shows its suitability for heterogeneous electronics-optics integration applications.

  17. Method and apparatus for jetting, manufacturing and attaching uniform solder balls

    DOEpatents

    Yost, F.G.; Frear, D.R.; Schmale, D.T.

    1999-01-05

    An apparatus and process are disclosed for jetting molten solder in the form of balls directly onto all the metallized interconnects lands for a ball grid array package in one step with no solder paste required. Molten solder is jetted out of a grid of holes using a piston attached to a piezoelectric crystal. When voltage is applied to the crystal it expands forcing the piston to extrude a desired volume of solder through holes in the aperture plate. When the voltage is decreased the piston reverses motion creating an instability in the molten solder at the aperture plate surface and thereby forming spherical solder balls that fall onto a metallized substrate. The molten solder balls land on the substrate and form a metallurgical bond with the metallized lands. The size of the solder balls is determined by a combination of the size of the holes in the aperture plate, the duration of the piston pulse, and the displacement of the piston. The layout of the balls is dictated by the location of the hooks in the grid. Changes in ball size and layout can be easily accomplished by changing the grid plate. This invention also allows simple preparation of uniform balls for subsequent supply to BGA users. 7 figs.

  18. Method and apparatus for jetting, manufacturing and attaching uniform solder balls

    SciTech Connect

    Yost, Frederick G.; Frear, Darrel R.; Schmale, David T.

    1999-01-01

    An apparatus and process for jetting molten solder in the form of balls directly onto all the metallized interconnects lands for a ball grid array package in one step with no solder paste required. Molten solder is jetted out of a grid of holes using a piston attached to a piezoelectric crystal. When voltage is applied to the crystal it expands forcing the piston to extrude a desired volume of solder through holes in the aperture plate. When the voltage is decreased the piston reverses motion creating an instability in the molten solder at the aperture plate surface and thereby forming spherical solder balls that fall onto a metallized substrate. The molten solder balls land on the substrate and form a metallurgical bond with the metallized lands. The size of the solder balls is determined by a combination of the size of the holes in the aperture plate, the duration of the piston pulse, and the displacement of the piston. The layout of the balls is dictated by the location of the hooks in the grid. Changes in ball size and layout can be easily accomplished by changing the grid plate. This invention also allows simple preparation of uniform balls for subsequent supply to BGA users.

  19. Alignability of Optical Interconnects

    NASA Astrophysics Data System (ADS)

    Beech, Russell Scott

    With the continuing drive towards higher speed, density, and functionality in electronics, electrical interconnects become inadequate. Due to optics' high speed and bandwidth, freedom from capacitive loading effects, and freedom from crosstalk, optical interconnects can meet more stringent interconnect requirements. But, an optical interconnect requires additional components, such as an optical source and detector, lenses, holographic elements, etc. Fabrication and assembly of an optical interconnect requires precise alignment of these components. The successful development and deployment of optical interconnects depend on how easily the interconnect components can be aligned and/or how tolerant the interconnect is to misalignments. In this thesis, a method of quantitatively specifying the relative difficulty of properly aligning an optical interconnect is described. Ways of using this theory of alignment to obtain design and packaging guidelines for optical interconnects are examined. The measure of the ease with which an optical interconnect can be aligned, called the alignability, uses the efficiency of power transfer as a measure of alignment quality. The alignability is related to interconnect package design through the overall cost measure, which depends upon various physical parameters of the interconnect, such as the cost of the components and the time required for fabrication and alignment. Through a mutual dependence on detector size, the relationship between an interconnect's alignability and its bandwidth, signal-to-noise ratio, and bit-error -rate is examined. The results indicate that a range of device sizes exists for which given performance threshold values are satisfied. Next, the alignability of integrated planar-optic backplanes is analyzed in detail. The resulting data show that the alignability can be optimized by varying the substrate thickness or the angle of reflection. By including the effects of crosstalk, in a multi-channel backplane, the

  20. Soldering Tested in Reduced Gravity

    NASA Technical Reports Server (NTRS)

    Struk, Peter M.; Pettegrew, Richard D.; Watson, J. Kevin; Down, Robert S.; Haylett, Daniel R.

    2005-01-01

    Whether used occasionally for contingency repair or routinely in nominal repair operations, soldering will become increasingly important to the success of future long-duration human space missions. As a result, it will be critical to have a thorough understanding of the service characteristics of solder joints produced in reduced-gravity environments. The National Center for Space Exploration Research (via the Research for Design program), the NASA Glenn Research Center, and the NASA Johnson Space Center are conducting an experimental program to explore the influence of reduced gravity environments on the soldering process. Solder joint characteristics that are being considered include solder fillet geometry, porosity, and microstructural features. Both through-hole (see the drawing and image on the preceding figure) and surface-mounted devices are being investigated. This effort (the low-gravity portion being conducted on NASA s KC-135 research aircraft) uses the soldering hardware currently available on the International Space Station. The experiment involves manual soldering by a contingent of test operators, including both highly skilled technicians and less skilled individuals to provide a skill mix that might be encountered in space mission crews. The experiment uses both flux-cored solder and solid-core solder with an externally applied flux. Other experimental parameters include the type of flux, gravitational level (nominally zero,

  1. Damage Produced in Solder Alloys during Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Liu, X. W.; Plumbridge, W. J.

    2007-09-01

    The anisotropy of tin is associated with significant variations in its coefficient of thermal expansion and elastic modulus, with crystallographic direction. Under pure thermal cycling (with no externally applied stress or strain), substantial strains, in excess of 100%, may develop locally, and for very small structures, such as soldered interconnections comprising a few grains, structural integrity may be adversely affected. To examine this possibility, freestanding samples of tin, Sn-3.5wt.%Ag, Sn-0.5wt.%Cu, and Sn-3.8wt.%Ag-0.7wt.%Cu, have been subjected to thermal cycling. Temperature cycles from 30°C to 125°C or from -40°C to 55°C initially caused surface cracking, with openings up to several tens of microns after 3,000 cycles. Subsequently, the surface cracks grew into the interior of the specimens, with the maximum penetration ranging from a few microns after 100 cycles to more than 200 μm after 3,000 cycles. The cracks initiated from damage accumulated along grain boundaries. For the same temperature range, less damage resulted after the lower maximum (or mean) temperature cycle, and there appears to be a thermally activated component of cracking. The microstructure produced by rapid cooling (water quenching) was slightly more resistant than that formed by air, or furnace, cooling. Apart from microstructural coarsening, no damage accrues from isothermal exposure alone.

  2. Modeling the Rate-Dependent Durability of Reduced-Ag SAC Interconnects for Area Array Packages Under Torsion Loads

    NASA Astrophysics Data System (ADS)

    Srinivas, Vikram; Menon, Sandeep; Osterman, Michael; Pecht, Michael G.

    2013-08-01

    Solder durability models frequently focus on the applied strain range; however, the rate of applied loading, or strain rate, is also important. In this study, an approach to incorporate strain rate dependency into durability estimation for solder interconnects is examined. Failure data were collected for SAC105 solder ball grid arrays assembled with SAC305 solder that were subjected to displacement-controlled torsion loads. Strain-rate-dependent (Johnson-Cook model) and strain-rate-independent elastic-plastic properties were used to model the solders in finite-element simulation. Test data were then used to extract damage model constants for the reduced-Ag SAC solder. A generalized Coffin-Manson damage model was used to estimate the durability. The mechanical fatigue durability curve for reduced-silver SAC solder was generated and compared with durability curves for SAC305 and Sn-Pb from the literature.

  3. Thermomechanical fatigue behavior of Sn-Ag solder joints

    NASA Astrophysics Data System (ADS)

    Choi, S.; Subramanian, K. N.; Lucas, J. P.; Bieler, T. R.

    2000-10-01

    Microstructural studies of thermomechanically fatigued actual electronic components consisting of metallized alumina substrate and tinned copper lead, soldered with Sn-Ag or 95.5Ag/4Ag/0.5Cu solder were carried out with an optical microscope and environmental scanning electron microscope (ESEM). Damage characterization was made on samples that underwent 250 and 1000 thermal shock cycles between -40°C and 125°C, with a 20 min hold time at each extreme. Surface roughening and grain boundary cracking were evident even in samples thermally cycled for 250 times. The cracks were found to originate on the free surface of the solder joint. With increased thermal cycles these cracks grew by grain boundary decohesion. The crack that will affect the integrity of the solder joint was found to originate from the free surface of the solder very near the alumina substrate and progress towards and continue along the solder region adjacent to the Ag3Sn intermetallic layer formed with the metallized alumina substrate. Re-examination of these thermally fatigued samples that were stored at room temperature after ten months revealed the effects of significant residual stress due to such thermal cycles. Such observations include enhanced surface relief effects delineating the grain boundaries and crack growth in regions inside the joint.

  4. Breakthrough: Lead-free Solder

    SciTech Connect

    Anderson, Iver

    2012-01-01

    Ames Laboratory senior metallurgist Iver Anderson explains the importance of lead-free solder in taking hazardous lead out of the environment by eliminating it from discarded computers and electronics that wind up in landfills. Anderson led a team that developed a tin-silver-copper replacement for traditional lead-tin solder that has been adopted by more than 50 companies worldwide.

  5. Breakthrough: Lead-free Solder

    ScienceCinema

    Anderson, Iver

    2013-03-01

    Ames Laboratory senior metallurgist Iver Anderson explains the importance of lead-free solder in taking hazardous lead out of the environment by eliminating it from discarded computers and electronics that wind up in landfills. Anderson led a team that developed a tin-silver-copper replacement for traditional lead-tin solder that has been adopted by more than 50 companies worldwide.

  6. Intermetallics Characterization of Lead-Free Solder Joints under Isothermal Aging

    NASA Astrophysics Data System (ADS)

    Choubey, Anupam; Yu, Hao; Osterman, Michael; Pecht, Michael; Yun, Fu; Yonghong, Li; Ming, Xu

    2008-08-01

    Solder interconnect reliability is influenced by environmentally imposed loads, solder material properties, and the intermetallics formed within the solder and the metal surfaces to which the solder is bonded. Several lead-free metallurgies are being used for component terminal plating, board pad plating, and solder materials. These metallurgies react together and form intermetallic compounds (IMCs) that affect the metallurgical bond strength and the reliability of solder joint connections. This study evaluates the composition and extent of intermetallic growth in solder joints of ball grid array components for several printed circuit board pad finishes and solder materials. Intermetallic growth during solid state aging at 100°C and 125°C up to 1000 h for two solder alloys, Sn-3.5Ag and Sn-3.0Ag-0.5Cu, was investigated. For Sn-3.5Ag solder, the electroless nickel immersion gold (ENIG) pad finish was found to result in the lowest IMC thickness compared to immersion tin (ImSn), immersion silver (ImAg), and organic solderability preservative (OSP). Due to the brittle nature of the IMC, a lower IMC thickness is generally preferred for optimal solder joint reliability. A lower IMC thickness may make ENIG a desirable finish for long-life applications. Activation energies of IMC growth in solid-state aging were found to be 0.54 ± 0.1 eV for ENIG, 0.91 ± 0.12 eV for ImSn, and 1.03 ± 0.1 eV for ImAg. Cu3Sn and Cu6Sn5 IMCs were found between the solder and the copper pad on boards with the ImSn and ImAg pad finishes. Ternary (Cu,Ni)6Sn5 intermetallics were found for the ENIG pad finish on the board side. On the component side, a ternary IMC layer composed of Ni-Cu-Sn was found. Along with intermetallics, microvoids were observed at the interface between the copper pad and solder, which presents some concern if devices are subject to shock and vibration loading.

  7. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

  8. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  9. Detection of power losses in busbar solder contacts by electroluminescence imaging of solar cells

    NASA Astrophysics Data System (ADS)

    Gazuz, Vladimir; Buerhop, Claudia

    2011-11-01

    Soldered contacts between busbar and interconnected ribbon can be missing or defective due to production or exploitation of solar cells. This causes an increase of total series resistance and thus more power losses in soldered solar cells or whole modules. There are many conventional methods for checking missing solder joints such as optical or mechanical; however they are quite complicated for practical application. We present a new method for quantitative and qualitative checking of the solar cell solder contacts. This method is based on analysis of the line-scan diagrams of the electroluminescence images of a solar cell's area by applying the appropriate voltage between front side and backside. As a theoretical justification we have used the equation for calculation of the electroluminescence emission and the equations for calculation of the voltage distribution and of series resistance in the solar cell's busbar.

  10. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 3 2014-04-01 2014-04-01 false Lead solders. 189.240 Section 189.240 Food and...-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are... in can solder is deemed to be adulterated in violation of the Federal Food, Drug, and Cosmetic...

  11. Simulation of Grain Growth in a Near-Eutectic Solder Alloy

    SciTech Connect

    TIKARE,VEENA; VIANCO,PAUL T.

    1999-12-16

    Microstructural evolution due to aging of solder alloys determines their long-term reliability as electrical, mechanical and thermal interconnects in electronics packages. The ability to accurately determine the reliability of existing electronic components as well as to predict the performance of proposed designs depends upon the development of reliable material models. A kinetic Monte Carlo simulation was used to simulate microstructural evolution in solder-class materials. The grain growth model simulated many of the microstructural features observed experimentally in 63Sn-37Pb, a popular near-eutectic solder alloy. The model was validated by comparing simulation results to new experimental data on coarsening of Sn-Pb solder. The computational and experimental grain growth exponent for two-phase solder was found to be much lower than that for normal, single phase grain growth. The grain size distributions of solders obtained from simulations were narrower than that of normal grain growth. It was found that the phase composition of solder is important in determining grain growth behavior.

  12. In-situ study of electromigration-induced grain rotation in Pb-free solder joint by synchrotron microdiffraction

    SciTech Connect

    Chen, Kai; Tamura, Nobumichi; Tu, King-Ning

    2008-10-31

    The rotation of Sn grains in Pb-free flip chip solder joints hasn't been reported in literature so far although it has been observed in Sn strips. In this letter, we report the detailed study of the grain orientation evolution induced by electromigration by synchrotron based white beam X-ray microdiffraction. It is found that the grains in solder joint rotate more slowly than in Sn strip even under higher current density. On the other hand, based on our estimation, the reorientation of the grains in solder joints also results in the reduction of electric resistivity, similar to the case of Sn strip. We will also discuss the reason why the electric resistance decreases much more in strips than in the Sn-based solders, and the different driving force for the grain growth in solder joint and in thin film interconnect lines.

  13. Porosity in collapsible Ball Grid Array solder joints

    SciTech Connect

    Gonzalez, C.A. |

    1998-05-01

    Ball Grid Array (BGA) technology has taken off in recent years due to the increased need for high interconnect density. Opposite to all the advantages BGA packages offer, porosity in collapsible BGA solder joints is often a major concern in the reliability of such packages. The effect of pores on the strength of collapsible BGA solder-joints was studied by manufacturing samples with different degrees of porosity and testing them under a shear load. It was found that the shear strength of the solder joints decreased in a linear fashion with increasing porosity. Failure occurred by internal necking of the interpore matrix. It was confirmed that entrapment of flux residues leads to porosity by manufacturing fluxless samples in a specially made furnace, and comparing them with samples assembled using flux. Also, contamination of Au electrodeposits (in substrate metallization) was determined to cause significant porosity. It was found that hard-Au (Co hardened Au) electrodeposits produce high degrees of porosity even in the absence of flux. Finally, increasing the time the solder spends in the molten state was proven to successfully decrease porosity.

  14. An Evaluation of Prototype Circuit Boards Assembled with a Sn-Ag Bi Solder

    SciTech Connect

    ARTAKI,I.; RAY,U.; REJENT,JEROME A.; VIANCO,PAUL T.

    1999-09-01

    An evaluation was performed which examined the aging of surface mount solder joints assembled with 91.84Sn-3.33Ag-4.83Bi solder. Defect analysis of the as-fabricated test vehicles revealed excellent solderability, good package alignment, and a minimum number of voids. Continuous DC electrical monitoring of the solder joints did not reveal opens during as many as 10,000 thermal cycles (0 C, 100 C). The solder joints exhibited no significant degradation through 2500 cycles, based upon an absence of microstructural damage and sustained shear and pull strengths of chip capacitors and J-leaded solder joints, respectively. Thermal cycles of 5000 and 10,000 resulted in some surface cracking of the solder fillets and coatings. In a few cases, deeper cracks were observed in the thinner reaches of several solder fillets. There was no deformation or cracking in the solder located in the gap between the package I/O and the circuit board pad nor in the interior of the fillets, both locations that would raise concerns of joint mechanical integrity. A drop in the chip capacitor shear strength was attributed to crack growth near the top of the fillet.

  15. Integrated reconfigurable microring based silicon WDM receiver for on-chip optical interconnect

    NASA Astrophysics Data System (ADS)

    Shen, Ao; Qiu, Chen; Yang, Long-Zhi; Dai, Ting-Ge; Hao, Yin-Lei; Jiang, Xiao-Qing; Yang, Jian-Yi

    2015-05-01

    We demonstrate an integrated reconfigurable wavelength division multiplexing receiver on the silicon-on-insulator (SOI) platform. The receiver is composed of a 1 × 8 thermally tunable microring resonator filter and Ge-Si photodetectors. With low thermal tuning powers the channel allocation of the receiver can be reconfigured with high accuracy and flexibility. The thermal tuning efficiency is approximately 8 mW nm-1. We show eight-channel configurations with channel spacing of 100 GHz and 50 GHz and a configuration in which all eight channels cover an entire free spectral range of the ring with uniform channel spacing of 1.2 nm. Each channel can receive high-quality signals with a data rate of up to 13.5 Gb s-1 thus an aggregate data rate higher than 100 Gb s-1 can be achieved.

  16. METHOD FOR SOLDERING NORMALLY NON-SOLDERABLE ARTICLES

    DOEpatents

    McGuire, J.C.

    1959-11-24

    Methods are presented for coating and joining materials which are considered difficult to solder by utilizing an abrasive wheel and applying a bar of a suitable coating material, such as Wood's metal, to the rotating wheel to fill the cavities of the abrasive wheel and load the wheel with the coating material. The surface of the base material is then rubbed against the loaded rotating wheel, thereby coating the surface with the soft coating metal. The coating is a cohesive bonded layer and holds the base metal as tenaciously as a solder holds to easily solderable metals.

  17. Development of a fabrication technology for integrating low cost optical interconnects on a printed circuit board

    NASA Astrophysics Data System (ADS)

    Van Steenberge, Geert; Hendrickx, Nina; Geerinck, Peter; Bosman, Erwin; Van Put, Steven; Van Erps, Jurgen; Thienpont, Hugo; Van Daele, Peter

    2006-02-01

    We present a fabrication technology for integrating polymer waveguides and 45° micromirror couplers into standard electrical printed circuit boards (PCBs). The most critical point that is being addressed is the low-cost manufacturing and the compatibility with current PCB production. The latter refers to the processes as well as material compatibility. Multimode waveguides are patterned by KrF excimer laser ablation in acrylate polymers with 0.13 dB/cm propagation loss at 850 nm. Single mode waveguides using inorganic-organic hybrid polymers show an attenuation loss of 0.62 +/- 0.08 dB/cm at 1.3 μm. A process for embedding metal coated 45° micromirrors in optical waveguiding layers is developed. Mirrors are selectively metallized using a lift-off process. Filling up the angled via without the presence of air bubbles and providing a flat surface above the mirror is only possible by enhancing the cladding deposition process with ultrasound agitation. Initial single mode coupling loss measurements at 1.3 μm show an excess mirror loss of 1.55 dB. Multimode coupling loss measurements will improve this excess loss, because of the lower surface roughness of the mirrors using the acrylate polymers for multimode waveguides.

  18. Characteristics of Al substituted nanowires fabricated by self-aligned growth for future large scale integration interconnects

    NASA Astrophysics Data System (ADS)

    Kudo, Hiroshi; Kurahashi, Teruo

    2011-06-01

    Substituted Al nanowires for use in future large scale integration interconnects were fabricated by self-aligned growth. The resistivity of an Al substituted nanowire 80 nm in width, 100 nm in height, and 20 μm in length was 4.7 μΩ cm, which is 48% lower than that of an Al nanowire with the same dimensions fabricated using a bottom-up approach. The variation in the resistivity was in a narrow range (14%) over a Si wafer. The TEM imaging revealed that the Al substituted nanowire had a bamboo-like structure with grains larger than 1.6 μm. The electromigration activation energy was 0.72 eV, which is comparable to that of a pure Al wire with a bamboo-like structure. The product of the critical current density and wire length was 1.3 × 103 A/cm at 250 °C; 2.1 times higher than that of a pure Al wire with a polycrystalline structure. The acceleration of electromigration due to current density was 2.0, indicating that incubation time dominates electromigration lifetime. The prolonged incubation time observed in the electromigration test is attributed to the reduction in electromigration-induced mass transport due to the microstructure of the Al substituted nanowire. Even the formation of a small void immediately after incubation may be a fatal defect for nanoscale Al wires.

  19. Integrated Energy-Water Planning in the Western and Texas Interconnections (Invited)

    NASA Astrophysics Data System (ADS)

    Tidwell, V. C.

    2013-12-01

    While thermoelectric power generation accounts for less than one percent of total water consumption in the western U.S, steady growth in demand is projected for this sector. Complexities and heterogeneity in water supply, water demand, and institutional controls make water development a challenging proposition throughout the West. A consortium of National Laboratories, the University of Texas and the Electric Power Research Institute are working with the Western Governors' Association and Western States Water Council to assist the Western Electricity Coordinating Council and the Electric Reliability Council of Texas to integrate water related issues into long-term transmission planning. Specifically, water withdrawal and consumption have been estimated for each western power plant and their susceptibility to climate impacts assessed. To assist with transmission planning, water availability and cost data have been mapped at the 8-digit Hydrologic Unit Code level for the conterminous western U.S. (1208 watersheds). Five water sources were individually considered, including unappropriated surface water, unappropriated groundwater, appropriated water, municipal wastewater and brackish groundwater. Also mapped is projected growth in consumptive water demand to 2030. The relative costs (capital and O&M) to secure, convey, and treat the water as necessary have also been estimated for each source of water. These data configured into watershed level supply curves were subsequently used to constrain West-wide transmission planning. Results across a range of alternative energy futures indicate the impact of water availability and cost on the makeup and siting of future power generation. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Water budgets at a 8

  20. Welding, brazing, and soldering handbook

    NASA Technical Reports Server (NTRS)

    Kilgore, A. B.; Koehler, M. L.; Metzler, J. W.; Sturges, S. R.

    1969-01-01

    Handbook gives information on the selection and application of welding, brazing, and soldering techniques for joining various metals. Summary descriptions of processes, criteria for process selection, and advantages of different methods are given.

  1. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

    NASA Astrophysics Data System (ADS)

    He, Yugui; Feng, Jiwen; Zhang, Zhi; Wang, Chao; Wang, Dong; Chen, Fang; Liu, Maili; Liu, Chaoyang

    2015-08-01

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately -170 for 1H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo 1H MRI at 0.35 T.

  2. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

    SciTech Connect

    He, Yugui; Liu, Chaoyang; Feng, Jiwen; Wang, Dong; Chen, Fang; Liu, Maili; Zhang, Zhi; Wang, Chao

    2015-08-15

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately −170 for {sup 1}H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo {sup 1}H MRI at 0.35 T.

  3. Metal-interconnection-free integration of InGaN/GaN light emitting diodes with AlGaN/GaN high electron mobility transistors

    NASA Astrophysics Data System (ADS)

    Liu, Chao; Cai, Yuefei; Liu, Zhaojun; Ma, Jun; Lau, Kei May

    2015-05-01

    We report a metal-interconnection-free integration scheme for InGaN/GaN light emitting diodes (LEDs) and AlGaN/GaN high electron mobility transistors (HEMTs) by combining selective epi removal (SER) and selective epitaxial growth (SEG) techniques. SER of HEMT epi was carried out first to expose the bottom unintentionally doped GaN buffer and the sidewall GaN channel. A LED structure was regrown in the SER region with the bottom n-type GaN layer (n-electrode of the LED) connected to the HEMTs laterally, enabling monolithic integration of the HEMTs and LEDs (HEMT-LED) without metal-interconnection. In addition to saving substrate real estate, minimal interface resistance between the regrown n-type GaN and the HEMT channel is a significant improvement over metal-interconnection. Furthermore, excellent off-state leakage characteristics of the driving transistor can also be guaranteed in such an integration scheme.

  4. Metal-interconnection-free integration of InGaN/GaN light emitting diodes with AlGaN/GaN high electron mobility transistors

    SciTech Connect

    Liu, Chao; Cai, Yuefei; Liu, Zhaojun; Ma, Jun; Lau, Kei May

    2015-05-04

    We report a metal-interconnection-free integration scheme for InGaN/GaN light emitting diodes (LEDs) and AlGaN/GaN high electron mobility transistors (HEMTs) by combining selective epi removal (SER) and selective epitaxial growth (SEG) techniques. SER of HEMT epi was carried out first to expose the bottom unintentionally doped GaN buffer and the sidewall GaN channel. A LED structure was regrown in the SER region with the bottom n-type GaN layer (n-electrode of the LED) connected to the HEMTs laterally, enabling monolithic integration of the HEMTs and LEDs (HEMT-LED) without metal-interconnection. In addition to saving substrate real estate, minimal interface resistance between the regrown n-type GaN and the HEMT channel is a significant improvement over metal-interconnection. Furthermore, excellent off-state leakage characteristics of the driving transistor can also be guaranteed in such an integration scheme.

  5. Refinement of the Microstructure of Sn-Ag-Bi-In Solder, by Addition of SiC Nanoparticles, to Reduce Electromigration Damage Under High Electric Current

    NASA Astrophysics Data System (ADS)

    Kim, Youngseok; Nagao, Shijo; Sugahara, Tohru; Suganuma, Katsuaki; Ueshima, Minoru; Albrecht, Hans-Juergen; Wilke, Klaus; Strogies, Joerg

    2014-12-01

    The trends of miniaturization, multi-functionality, and high performance in advanced electronic devices require higher densities of I/O gates and reduced area of soldering of interconnections. This increases the electric current density flowing through the interconnections, increasing the risk of interconnection failure caused by electromigration (EM). Accelerated directional atomic diffusion in solder materials under high current induces substantial growth of intermetallic compounds (IMCs) at the anode, and also void and crack formation at the cathode. In the work discussed in this paper, addition of SiC nanoparticles to Sn-Ag-Bi-In (SABI) lead-free solder refined its microstructure and improved its EM reliability under high current stress. Electron backscattering diffraction analysis revealed that the added SiC nanoparticles refined solder grain size after typical reflow. Under current stress, SABI joints with added nano-SiC had lifetimes almost twice as long as those without. Comparison of results from high-temperature aging revealed direct current affected evolution of the microstructure. Observations of IMC growth indicated that diffusion of Cu in the SiC composite solder may not have been reduced. During current flow, however, only narrow voids were formed in solder containing SiC, thus preventing the current crowding caused by bulky voids in the solder without SiC.

  6. Some Observations of Solder Joint Failure Under Tensile-Compressive Stress

    NASA Technical Reports Server (NTRS)

    Winslow, J. W.

    1993-01-01

    It has long been known that solder joints under mechanical stress are subject to failure. In early electronic systems, such failures were avoided primarily by avoiding the use of solder as a mechanical structural component. The rule was to first make sound wire connections that did not depend mechanically on solder, and only then to solder them. Careful design and miniaturization in modern electronic systems limits the mechanical stresses exerted on solder joints to values less than their yield points, and these joints have become integral parts of the mechanical structures. Unfortunately, while these joints are strong enough when new, they have proven vulnerable to fatigue failures as they age.Details of the fatigue process are poorly understood, making predictions of expected lifetimes difficult.

  7. A Probabilistic Approach to Predict Thermal Fatigue Life for Ball Grid Array Solder Joints

    NASA Astrophysics Data System (ADS)

    Wei, Helin; Wang, Kuisheng

    2011-11-01

    Numerous studies of the reliability of solder joints have been performed. Most life prediction models are limited to a deterministic approach. However, manufacturing induces uncertainty in the geometry parameters of solder joints, and the environmental temperature varies widely due to end-user diversity, creating uncertainties in the reliability of solder joints. In this study, a methodology for accounting for variation in the lifetime prediction for lead-free solder joints of ball grid array packages (PBGA) is demonstrated. The key aspects of the solder joint parameters and the cyclic temperature range related to reliability are involved. Probabilistic solutions of the inelastic strain range and thermal fatigue life based on the Engelmaier model are developed to determine the probability of solder joint failure. The results indicate that the standard deviation increases significantly when more random variations are involved. Using the probabilistic method, the influence of each variable on the thermal fatigue life is quantified. This information can be used to optimize product design and process validation acceptance criteria. The probabilistic approach creates the opportunity to identify the root causes of failed samples from product fatigue tests and field returns. The method can be applied to better understand how variation affects parameters of interest in an electronic package design with area array interconnections.

  8. Description of a solder pulse generator for the single step formation of ball grid arrays

    SciTech Connect

    Schmale, D.T.; Frear, D.R.; Yost, F.G.; Essien, M.

    1997-02-01

    The traditional geometry for surface mount devices is the peripheral array where the leads are on the edges of the device. As the technology drives towards high input/output (I/O) count (increasing number of leads) and smaller packages with finer pitch (less distance between peripheral leads), limitations on peripheral surface mount devices arise. The leads on these fine pitch devices are fragile and can be easily bent. It becomes increasingly difficult to deliver solder past to leads spaced as little as 0.012 inch apart. Too much solder mass can result in bridging between leads while too little solder can contribute to the loss of mechanical and electrical continuity. A solution is to shift the leads from the periphery of the device to the area under the device. This scheme is called areal array packaging and is exemplified by the ball grid array (BGA) package. A system has been designed and constructed to deposit an entire array of several hundred uniform solder droplets onto a printed circuit board in a fraction of a second. The solder droplets wet to the interconnect lands on a pc board and forms a basis for later application of a BGA device. The system consists of a piezoelectric solder pulse unit, heater controls, an inert gas chamber and an analog power supply/pulse unit.

  9. Optically interconnected phased arrays

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Kunath, Richard R.

    1988-01-01

    Phased-array antennas are required for many future NASA missions. They will provide agile electronic beam forming for communications and tracking in the range of 1 to 100 GHz. Such phased arrays are expected to use several hundred GaAs monolithic integrated circuits (MMICs) as transmitting and receiving elements. However, the interconnections of these elements by conventional coaxial cables and waveguides add weight, reduce flexibility, and increase electrical interference. Alternative interconnections based on optical fibers, optical processing, and holography are under evaluation as possible solutions. In this paper, the current status of these techniques is described. Since high-frequency optical components such as photodetectors, lasers, and modulators are key elements in these interconnections, their performance and limitations are discussed.

  10. Economical solder connections to thin films

    NASA Technical Reports Server (NTRS)

    Bass, J. A.; Gaddy, E. M.

    1979-01-01

    Soldering procedure, successfully tested for attaching leads to silicon solar cells, cover-glasses, is simple, inexpensive, and very effective in forming stable connection. Procedure uses solder of indium alloyed with either silver or tin.

  11. Wetting behavior of alternative solder alloys

    SciTech Connect

    Hosking, F.M.; Vianco, P.T.; Hernandez, C.L.; Rejent, J.A.

    1993-07-01

    Recent economic and environmental issues have stimulated interest in solder alloys other than the traditional Sn-Pb eutectic or near eutectic composition. Preliminary evaluations suggest that several of these alloys approach the baseline properties (wetting, mechanical, thermal, and electrical) of the Sn-Pb solders. Final alloy acceptance will require major revisions to existing industrial and military soldering specifications. Bulk alloy and solder joint properties are consequently being investigated to validate their producibility and reliability. The work reported in this paper examines the wetting behavior of several of the more promising commercial alloys on copper substrates. Solder wettability was determined by the meniscometer and wetting balance techniques. The wetting results suggest that several of the alternative solders would satisfy pretinning and surface mount soldering applications. Their use on plated through hole technology might be more difficult since the alloys generally did not spread or flow as well as the 60Sn-40Pb solder.

  12. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 3 2012-04-01 2012-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of... container that makes use of lead in can solder is deemed to be adulterated in violation of the Federal...

  13. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 3 2013-04-01 2013-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of... container that makes use of lead in can solder is deemed to be adulterated in violation of the Federal...

  14. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 3 2011-04-01 2011-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of... container that makes use of lead in can solder is deemed to be adulterated in violation of the Federal...

  15. Modified Spot Welder Solders Flat Cables

    NASA Technical Reports Server (NTRS)

    Haehner, Carl L.

    1992-01-01

    Soldering device, essentially modified spot welder, melts high-melting-temperature solders without damaging plastic insulation on flat electrical cables. Solder preform rests on exposed conductor of cable, under connector pin. Electrodes press pin/preform/conductor sandwich together and supply pulse of current to melt preform, bonding pin to conductor. Anvil acts as support and heat sink. Device used to solder flexible ribbon cables to subminiature pin connectors.

  16. Performance evaluation of multi-stratum resources integration based on network function virtualization in software defined elastic data center optical interconnect.

    PubMed

    Yang, Hui; Zhang, Jie; Ji, Yuefeng; Tian, Rui; Han, Jianrui; Lee, Young

    2015-11-30

    Data center interconnect with elastic optical network is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resilience between IP and elastic optical networks that allows to accommodate data center services. In view of this, this study extends to consider the resource integration by breaking the limit of network device, which can enhance the resource utilization. We propose a novel multi-stratum resources integration (MSRI) architecture based on network function virtualization in software defined elastic data center optical interconnect. A resource integrated mapping (RIM) scheme for MSRI is introduced in the proposed architecture. The MSRI can accommodate the data center services with resources integration when the single function or resource is relatively scarce to provision the services, and enhance globally integrated optimization of optical network and application resources. The overall feasibility and efficiency of the proposed architecture are experimentally verified on the control plane of OpenFlow-based enhanced software defined networking (eSDN) testbed. The performance of RIM scheme under heavy traffic load scenario is also quantitatively evaluated based on MSRI architecture in terms of path blocking probability, provisioning latency and resource utilization, compared with other provisioning schemes. PMID:26698748

  17. Research study: Device technology STAR router user's guide. [automated layout of large scale integration discretionary interconnection masks

    NASA Technical Reports Server (NTRS)

    Wright, R. A.

    1979-01-01

    The STAR Router program developed to perform automated layout of LSI discretionary interconnection masks is described. The input and output for the router are standard PR2D data files. A state-of-the-art cellular path-finding procedure, based on Lee's algorithm, which produces fast, shortest distance routing of microcircuit net data is included.

  18. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 3 2010-04-01 2009-04-01 true Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  19. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2013 CFR

    2013-01-01

    ... 16 Commercial Practices 1 2013-01-01 2013-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  20. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 1 2011-01-01 2011-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  1. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... 16 Commercial Practices 1 2012-01-01 2012-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  2. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 16 Commercial Practices 1 2010-01-01 2010-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  3. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2014 CFR

    2014-01-01

    ... 16 Commercial Practices 1 2014-01-01 2014-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  4. Laser micromachining of through via interconnects in active die for 3-D multichip module

    SciTech Connect

    Chu, D.; Miller, W.D.

    1995-09-01

    One method to increase density in integrated circuits (IC) is to stack die to create a 3-D multichip module (MCM). In the past, special post wafer processing was done to bring interconnects out to the edge of the die. The die were sawed, glued, and stacked. Special processing was done to create interconnects on the edge to provide for interconnects to each of the die. These processes require an IC type fabrication facility (fab) and special processing equipment. In contrast, we have developed packaging assembly methods to created vertical through vias in bond pads of active silicon die, isolate these vias, and metal fill these vias without the use of a special IC fab. These die with through vias can then be joined and stacked to create a 3-D MCM. Vertical through vias in active die are created by laser micromachining using a Nd:YAG laser. Besides the fundamental 1064 nm (infra-red) laser wavelength of a Nd:YAG laser, modifications to our Nd:YAG laser allowed us to generate the second harmonic 532 nm (green) laser wavelength and fourth harmonic 266nm (ultra violet) laser wavelength in laser micromachining for these vias. Experiments were conducted to determine the best laser wavelengths to use for laser micromachining of vertical through vias in order to minimize damage to the active die. Via isolation experiments were done in order to determine the best method in isolating the bond pads of the die. Die thinning techniques were developed to allow for die thickness as thin as 50 {mu}m. This would allow for high 3-D density when the die are stacked. A method was developed to metal fill the vias with solder using a wire bonder with solder wire.

  5. Solder Joint Health Monitoring Testbed

    NASA Technical Reports Server (NTRS)

    Delaney, Michael M.; Flynn, James G.; Browder, Mark E.

    2009-01-01

    A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

  6. Universal solders for direct and powerful bonding on semiconductors, diamond, and optical materials

    NASA Astrophysics Data System (ADS)

    Mavoori, Hareesh; Ramirez, Ainissa G.; Jin, Sungho

    2001-05-01

    The surfaces of electronic and optical materials such as nitrides, carbides, oxides, sulfides, fluorides, selenides, diamond, silicon, and GaAs are known to be very difficult to bond with low melting point solders (<300 °C). We have achieved a direct and powerful bonding on these surfaces by using low temperature solders doped with rare-earth elements. The rare earth is stored in micron-scale, finely-dispersed intermetallic islands (Sn3Lu or Au4Lu), and when released, causes chemical reactions at the interface producing strong bonds. These solders directly bond to semiconductor surfaces and provide ohmic contacts. They can be useful for providing direct electrical contacts and interconnects in a variety of electronic assemblies, dimensionally stable and reliable bonding in optical fiber, laser, or thermal management assemblies.

  7. Low-temperature solder for joining large cryogenic structures. [cooling cools for the National Transonic Facility

    NASA Technical Reports Server (NTRS)

    Buckley, J. D.; Sandefur, P. G., Jr.

    1980-01-01

    Three joining methods were considered for use in fabricating cooling coils for the National Transonic Facility. After analysis and preliminary testing, soldering was chosen as the cooling coil joining technique over mechanical force fit and brazing techniques. Charpy V-Notch tests, cyclic thermal tests (ambient to 77.8 K) and tensile tests at cryogenic temperatures were performed on solder joints to evaluate their structural integrity. It was determined that low temperature solder can be used to ensure good fin-to-tube contact for cooling-coil applications.

  8. Application of ESEM to fluxless soldering.

    PubMed

    Koopman, N

    1993-08-01

    The ESEM is ideally suited to study soldering processes. We have used it to observe solder reflow and joining in ambient gases. It reproduces effects of atmospheric pressure reflow in a hot stage light microscope, but with much better clarity and depth of field. Compared to a regular SEM, the ESEM offers advantages of atmosphere control and ability to observe the solder samples without carbon or gold coating. These coatings could interfere with the oxidation/reduction reactions which occur at the solder/ambient gas interface. Very thin surface films, especially oxide layers, dramatically influence the flow of liquid solder and the ability of solder to wet or join to another surface. Fluxless processes in particular are ideally suited for study in the ESEM. We have used the ESEM to observe dynamic fluxless soldering and have recorded events on videotape for later stop-action still pictures and slow motion photography. Examples of these processes are shown to illustrate the ESEM capability. Included are solder deformation structure, balling reflow of eutectic solder in hydrogen, balling reflow of eutectic solder in nitrogen, joining of two solder disks in nitrogen, and dynamic melting and freezing of an off-eutectic dendritic alloy. All of these are observed in the absence of flux. PMID:8400444

  9. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  10. Eddy current measurement of the thickness of top Cu film of the multilayer interconnects in the integrated circuit (IC) manufacturing process

    NASA Astrophysics Data System (ADS)

    Qu, Zilian; Meng, Yonggang; Zhao, Qian

    2015-03-01

    This paper proposes a new eddy current method, named equivalent unit method (EUM), for the thickness measurement of the top copper film of multilayer interconnects in the chemical mechanical polishing (CMP) process, which is an important step in the integrated circuit (IC) manufacturing. The influence of the underneath circuit layers on the eddy current is modeled and treated as an equivalent film thickness. By subtracting this equivalent film component, the accuracy of the thickness measurement of the top copper layer with an eddy current sensor is improved and the absolute error is 3 nm for sampler measurement.

  11. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  12. Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections—Part 2: Failure Mechanisms

    NASA Astrophysics Data System (ADS)

    Hokka, Jussi; Mattila, Toni T.; Xu, Hongbo; Paulasto-Kröckel, Mervi

    2013-06-01

    Part 1 of this study focused on identifying the effects of (i) temperature difference (Δ T), (ii) lower dwell temperature and shorter dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate on the lifetime of ball grid array (with 144 solder balls) component boards. Based on the characteristic lifetime, the studied thermal cycling profiles were categorized into three groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. In this work, the observed differences in component board lifetime are explained by studying the failure mechanisms and microstructural changes that take place in the three groups of loading conditions. It was observed that, under the standardized thermal cycling conditions (highly accelerated conditions), the networks of grain boundaries formed by recrystallization provided favorable paths for cracks to propagate intergranularly. It is noteworthy that the coarsening of intermetallic particles was strong in the recrystallized regions (the cellular structure had disappeared completely in the crack region). However, under real-use conditions (mildly/nonaccelerated conditions), recrystallization was not observed in the solder interconnections and cracks had propagated transgranularly in the bulk solder or between the intermetallic compound (IMC) layer and the bulk solder. The real-use conditions showed slight coarsening of the microstructure close to the crack region, but the solder bulk still included finer IMC particles and β-Sn cells characteristic of the as-solidified microstructures. These findings suggest that standardized thermal cycling tests used to assess the solder interconnection reliability of BGA144 component boards create failure mechanisms that differ from those seen in conditions representing real-use operation.

  13. Development of Readout Interconnections for the Si-W Calorimeter of SiD

    SciTech Connect

    Woods, M.; Fields, R.G.; Holbrook, B.; Lander, R.L.; Moskaleva, A.; Neher, C.; Pasner, J.; Tripathi, M.; Brau, J.E.; Frey, R.E.; Strom, D.; Breidenbach, M.; Freytag, D.; Haller, G.; Herbst, R.; Nelson, T.; Schier, S.; Schumm, B.; /UC, Santa Cruz

    2012-09-14

    The SiD collaboration is developing a Si-W sampling electromagnetic calorimeter, with anticipated application for the International Linear Collider. Assembling the modules for such a detector will involve special bonding technologies for the interconnections, especially for attaching a silicon detector wafer to a flex cable readout bus. We review the interconnect technologies involved, including oxidation removal processes, pad surface preparation, solder ball selection and placement, and bond quality assurance. Our results show that solder ball bonding is a promising technique for the Si-W ECAL, and unresolved issues are being addressed.

  14. Repairable chip bonding/interconnect process

    DOEpatents

    Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

    1997-01-01

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

  15. Repairable chip bonding/interconnect process

    DOEpatents

    Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

    1997-08-05

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

  16. Investigation of welded interconnection of large area wraparound contacted silicon solar cells

    NASA Technical Reports Server (NTRS)

    Lott, D. R.

    1984-01-01

    An investigation was conducted to evaluate the welding and temperature cycle testing of large area 5.9 x 5.9 wraparound silicon solar cells utilizing printed circuit substrates with SSC-155 interconnect copper metals and the LMSC Infrared Controlled weld station. An initial group of 5 welded modules containing Phase 2 developmental 5.9 x 5.9 cm cells were subjected to cyclical temperatures of + or 80 C at a rate of 120 cycles per day. Anomalies were noted in the adhesion of the cell contact metallization; therefore, 5 additional modules were fabricated and tested using available Phase I cells with demonstrated contact integrity. Cycling of the later module type through 12,000 cycles indicated the viability of this type of lightweight flexible array concept. This project demonstrated acceptable use of an alternate interconnect copper in combination with large area wraparound cells and emphasized the necessity to implement weld pull as opposed to solder pull procedures at the cell vendors for cells that will be interconnected by welding.

  17. Electrical interconnect

    DOEpatents

    Frost, John S.; Brandt, Randolph J.; Hebert, Peter; Al Taher, Omar

    2015-10-06

    An interconnect includes a first set of connector pads, a second set of connector pads, and a continuous central portion. A first plurality of legs extends at a first angle from the continuous central portion. Each leg of the first plurality of legs is connected to a connector pad of a first set of connector pads. A second plurality of legs extends at a second angle from the continuous central portion. Each leg of the second plurality of legs is connected to a connector pad of the second set of connector pads. Gaps are defined between legs. The gaps enable movement of the first set of connector pads relative to the second set of connector pads.

  18. Fluxless laser soldering of radar housings

    SciTech Connect

    Keicher, D.M.; Hosking, F.M.

    1990-01-01

    Laser soldering of electronic components is a rapidly maturing technology and has been found to be particularly useful in the attachment of very fine pitch surface mount devices. Conversely, very little progress has been made to extend this technology to other soldering applications. It was the intention of this study to explore the feasibility of utilizing laser soldering to produce hermetic closure joints in radar packages. In producing hermetic joints, several requirements had to be met. It was essential to have a process that would eliminate the potential for entrapment of corrosive flux residues within the radar unit. In addition, it was desirable to create higher strength solder joints than could be produced by conventional step solder techniques which require lower temperature solders to be used in the final closure process. Further, solder mixing of the closure joint solder and solders used on components inside the radar was to be avoided. To fulfill the requirements, the localized heating characteristics of laser soldering made it an obvious choice for this application.

  19. NTF: Soldering Technology Development for Cryogenics

    NASA Technical Reports Server (NTRS)

    Hall, E. T., Jr.

    1985-01-01

    The advent of the National Transonic Facility (NTF) brought about a new application for an old joining method, soldering. Soldering for use at cryogenic temperatures requires that solders remain ductile and free from tin-pest (grey tin), have toughness to withstand aerodynamic loads associated with flight research, and maintain their surface finishes. Solders are used to attach 347 Stainless-Steel tubing in surface grooves of models. The solder must fill up the gap and metallurgically bound to the tubing and model. Cryogenic temperatures require that only specific materials for models can be used, including: Vasco Max 200 CVM, lescalloy A-286 Vac Arc, pH 13-8 Mo. Solders identified for testing at this time are: 50% Sn - 49.5% Pb - 0.5% Sb, 95% Sn - 5% Sb, 50% In 50% Pb, and 37.5% Sn - 37.5% Pb - 25% In. With these materials and solders, it is necessary to determine their solderability. After solderability is determined, tube/groove specimens are fabricated and stressed under cryogenic temperatures. Compatible solders are then used for acutual models.

  20. Interconnecting heterogeneous database management systems

    NASA Technical Reports Server (NTRS)

    Gligor, V. D.; Luckenbaugh, G. L.

    1984-01-01

    It is pointed out that there is still a great need for the development of improved communication between remote, heterogeneous database management systems (DBMS). Problems regarding the effective communication between distributed DBMSs are primarily related to significant differences between local data managers, local data models and representations, and local transaction managers. A system of interconnected DBMSs which exhibit such differences is called a network of distributed, heterogeneous DBMSs. In order to achieve effective interconnection of remote, heterogeneous DBMSs, the users must have uniform, integrated access to the different DBMs. The present investigation is mainly concerned with an analysis of the existing approaches to interconnecting heterogeneous DBMSs, taking into account four experimental DBMS projects.

  1. Release Resistant Electrical Interconnections For Mems Devices

    DOEpatents

    Peterson, Kenneth A.; Garrett, Stephen E.; Reber, Cathleen A.

    2005-02-22

    A release resistant electrical interconnection comprising a gold-based electrical conductor compression bonded directly to a highly-doped polysilicon bonding pad in a MEMS, IMEMS, or MOEMS device, without using any intermediate layers of aluminum, titanium, solder, or conductive adhesive disposed in-between the conductor and polysilicon pad. After the initial compression bond has been formed, subsequent heat treatment of the joint above 363 C creates a liquid eutectic phase at the bondline comprising gold plus approximately 3 wt % silicon, which, upon re-solidification, significantly improves the bond strength by reforming and enhancing the initial bond. This type of electrical interconnection is resistant to chemical attack from acids used for releasing MEMS elements (HF, HCL), thereby enabling the use of a "package-first, release-second" sequence for fabricating MEMS devices. Likewise, the bond strength of an Au--Ge compression bond may be increased by forming a transient liquid eutectic phase comprising Au-12 wt % Ge.

  2. Laser Assisted Soldering: Effects of Hydration on Solder-Tissue Adhesion

    NASA Astrophysics Data System (ADS)

    Chan, Eric K.; Brown, Dennis T.; Kovach, Ian S.; Welch, Ashley J.

    1998-10-01

    Wound stabilization is critical in early wound healing. Other than superficial skin wounds, most tissue repair is exposed to a hydrated environment postoperatively. To simulate the stability of laser-soldered tissue in a wet environment, we studied the effects of hydration on laser soldered rat dermis and baboon articular cartilage. In this in vitro study, we used a solder composed of human serum albumin, sodium hyaluronate, and Indocyanine Green. A 2 (mu) L solder droplet was deposited on each tissue specimen and then the solder was irradiated with a scanning laser beam (808 nm and 27 W/cm2). After photocoagulation, each tissue specimen was cut into two halves dividing the solder. One half was reserved as control while the other half was soaked in saline for a designated period before fixation (1 h, 1, 2, and 7 days). All tissue specimens were prepared for scanning electron microscopy (SEM). SEM examinations revealed nonuniform coagulation across the solder thickness for most of the specimens, likely a result of the temperature gradient generated by laser heating. Closer to the laser beam, the uppermost region of the solder formed a dense coagulum. The solder aggregated into small globules in the region anterior to the solder-tissue interface. All cartilage specimens soaked in saline suffered coagulum detachment from tissue surface. We noted a high concentration of the protein globules in the detached coagulum. These globules were likely responsible for solder detachment from the cartilage surface. Solder adhered better to the dermis than to cartilage. The dermal layer of the skin, composed of collagen matrix, provided a better entrapment of the solder than the smooth surface of articular cartilage. Insufficient laser heating of solder formed protein globules. Unstable solder-tissue fusion was likely a result of these globules being detached from tissue substrate when the specimen was submerged in a hydrated environment. The solder-tissue bonding was compromised

  3. Characterization of solder flow on PWB surfaces

    SciTech Connect

    Hosking, F.M.; Yost, F.G.

    1995-07-01

    Different solderability tests have been developed to determine the wetting behavior of solder on metallic surfaces. None offer an exact measure of capillary flow associated with conventional mixed technology soldering. With shrinking package designs, increasing reliability requirements, and the emergence of new soldering technologies, there is a growing need to better understand and predict the flow of solder on printed wiring board (PWB) surfaces. Sandia National Laboratories has developed a capillary flow solderability test, through a joint effort with the National Center for Manufacturing Sciences, that considers this fundamental wetting issue for surface mount technology. The test geometry consists of a metal strip (width, {delta}) connected to a circular metal pad (radius, r{sub c}). Test methodology, experimental results, and validation of a flow model are presented in this paper.

  4. Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

    PubMed Central

    Sutanto, Jemmy; Anand, Sindhu; Patel, Chetan; Muthuswamy, Jit

    2013-01-01

    Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking. PMID:24504168

  5. Microstructurally based thermomechanical fatigue lifetime model of solder joints for electronic applications

    SciTech Connect

    Frear, D.R.; Rashid, M.M.; Burchett, S.N.

    1993-07-01

    We present a new methodology for predicting the fatigue life of solder joints for electronics applications. This approach involves integration of experimental and computational techniques. The first stage involves correlating the manufacturing and processing parameters with the starting microstructure of the solder joint. The second stage involves a series of experiments that characterize the evolution of the microstructure during thermal cycling. The third stage consists of a computer modeling and simulation effort that utilizes the starting microstructure and experimental data to produce a reliability prediction of the solder joint. This approach is an improvement over current methodologies because it incorporates the microstructure and properties of the solder directly into the model and allows these properties to evolve as the microstructure changes during fatigue.

  6. Tin soldering of aluminum and its alloys

    NASA Technical Reports Server (NTRS)

    Gallo, Gino

    1921-01-01

    A method is presented for soldering aluminum to other metals. The method adopted consists of a galvanic application to the surface of the light-metal parts to be soldered, of a layer of another metal, which, without reacting electrolytically on the aluminum, adheres strongly to the surface to which it is applied, and is, on the other hand, adapted to receive the soft solder. The metal found to meet the criteria best was iron.

  7. Advanced Interconnect Development

    SciTech Connect

    Yang, Z.G.; Maupin, G.; Simner, S.; Singh, P.; Stevenson, J.; Xia, G.

    2005-01-27

    The objectives of this project are to develop cost-effective, optimized materials for intermediate temperature SOFC interconnect and interconnect/electrode interface applications and identify and understand degradation processes in interconnects and at their interfaces with electrodes.

  8. New cathode-ray tube (CRT) gun interconnection assembly

    NASA Astrophysics Data System (ADS)

    McCormick, David M.

    1992-07-01

    A novel interconnection assembly method was developed for the electron gun of airborne CRTs, which makes it possible for the connectors to be connected and disconnected repeatedly (as opposed to soldering as in the conventional method) to provide access to the tube and its interconnecting cable harness. Environmental tests were conducted on one series of CRTs, which included electrical and environmental conditions which would be experienced in a worst-case aircraft cabin environment, including the altitude, humidity, thermal shock, vibration, and mechanical shock.

  9. Thermal Cycling Fatigue in DIPs Mounted with Eutectic Tin-Lead Solder Joints in Stub and Gullwing Geometries

    NASA Technical Reports Server (NTRS)

    Winslow, J. W.; Silveira, C. de

    1993-01-01

    It has long been known that solder joints under mechanical stress are subject to failure. In early electronic systems, such failures were avoided primarily by avoiding the use of solder as a mechanical structural component. The rule was first to make sound wire connections that did not depend mechanically on solder, and only then to solder them. Careful design and miniaturization in modern electronic systems limits the mechanical stresses exerted on solder joints to values less than their yield points, and these joints have become integral parts of the mechanical structures. Unfortunately, while these joints are strong enough when new, they have proven vulnerable to fatigue failures as they age. Details of the fatigue process are poorly understood, making predictions of expected lifetimes difficult.

  10. Die Soldering in Aluminium Die Casting

    SciTech Connect

    Han, Q.; Kenik, E.A.; Viswanathan, S.

    2000-03-15

    Two types of tests, dipping tests and dip-coating tests were carried out on small steel cylinders using pure aluminum and 380 alloy to investigate the mechanism of die soldering during aluminum die casting. Optical and scanning electron microscopy were used to study the morphology and composition of the phases formed during soldering. A soldering mechanism is postulated based on experimental observations. A soldering critical temperature is postulated at which iron begins to react with aluminum to form an aluminum-rich liquid phase and solid intermetallic compounds. When the temperature at the die surface is higher than this critical temperature, the aluminum-rich phase is liquid and joins the die with the casting during the subsequent solidification. The paper discusses the mechanism of soldering for the case of pure aluminum and 380 alloy casting in a steel mold, the factors that promote soldering, and the strength of the bond formed when soldering occurs. conditions, an aluminum-rich soldering layer may also form over the intermetallic layer. Although a significant amount of research has been conducted on the nature of these intermetallics, little is known about the conditions under which soldering occurs.

  11. Soldering of complex multilayer printed boards

    NASA Astrophysics Data System (ADS)

    Garrigue, Jean-Marie; Braun, Jean-Francois

    1990-09-01

    The soldering limits of complex multilayer printed boards used for spaceborne electronic equipment are presented. 6400 configurations related to board design, component's lead characteristics and manual and wave soldering parameters, are tested. Choices and recommendations are suggested to overcome these limits. Quality and reliability aspects of the soldered joints are broached, and research topics are proposed. Soldering problems are found to develop beyond 8 to 10 layers of circuits in components with connection conductivities of less than 1 to 2 W per cm over temperature in degrees centigrade.

  12. Intermetallic Layers in Soldered Joints

    Energy Science and Technology Software Center (ESTSC)

    1998-12-10

    ILAG solves the one-dimensional partial differential equations describing the multiphase, multicomponent, solid-state diffusion-controlled growth of intermetallic layers in soldered joints. This software provides an analysis capability for materials researchers to examine intermetallic growth mechanisms in a wide variety of defense and commercial applications involving both traditional and advanced materials. ILAG calculates the interface positions of the layers, as well as the spatial distribution of constituent mass fractions, and outputs the results at user-prescribed simulation times.

  13. Interconnected semiconductor devices

    DOEpatents

    Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

    1990-10-23

    Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

  14. Compatibility of lead-free solders with lead containing surface finishes as a reliability issue in electronic assemblies

    SciTech Connect

    Vianco, P.; Rejent, J.; Artaki, I.; Ray, U.; Finley, D.; Jackson, A.

    1996-03-01

    Enhanced performance goals and environmental restrictions have heightened the consideration for use of alternative solders as replacements for the traditional tin-lead (Sn-Pb) eutectic and near-eutectic alloys. However, the implementation of non-Pb bearing surface finishes may lag behind solder alloy development. A study was performed which examined the effect(s) of Pb contamination on the performance of Sn-Ag-Bi and Sn-Ag-Cu-Sb lead-free solders by the controlled addition of 63Sn-37Pb solder at levels of 0.5 {minus} 8.0 wt.%. Thermal analysis and ring-in-plug shear strength studies were conducted on bulk solder properties. Circuit board prototype studies centered on the performance of 20I/O SOIC gull wing joints. Both alloys exhibited declines in their melting temperatures with greater Sn-Pb additions. The ring-in-plug shear strength of the Sn-Ag-Cu-Sb solder increased slightly with Sn-Pb levels while the Sn-Ag-Bi alloy experienced a strength loss. The mechanical behavior of the SOIC (Small Outline Integrated Circuit) Sn-Ag-Bi solder joints reproduced the strength levels were insensitive to 10,106 thermal cycles. The Sn-Ag-Cu-Sb solder showed a slight decrease in the gull wing joint strengths that was sensitive to the Pb content of the surface finish.

  15. Solderability of surface mount devices

    NASA Astrophysics Data System (ADS)

    Holder, Nanette S.

    1993-06-01

    As electronic products become much smaller, a limiting factor in the reduction of product size has been the size of the electronic components which make up the product. The leads of the current electronic components are inserted onto a printed circuit board through holes. Due to the use of wire leads, it becomes more difficult to decrease the size of the components. A new method was created to mount components directly to the surface of the printed circuit board. This new technique is surface mount technology. A concern over the use of this is experienced by the military. Since the leads are not inserted through the board and crimped before soldering as conventional components are mounted, there is some regard as to whether the components can be mounted securely to the board. Due to the high forces that many munitions experience when dispensed, it is imperative that the electronic components be soldered to the circuits boards so they will not slip out of place or fall from the board. The military also requires many munitions to lie dormant in storage warehouses for up to 20 years. When the munition is needed, it must perform reliably. Little work has been done to study the effects of this long-term storage on these surface mount devices, particularly on the ability of different soldering techniques used to attach surface mount components to printed circuit boards to withstand damaging effects of long-term storage.

  16. Interconnection networks

    DOEpatents

    Faber, V.; Moore, J.W.

    1988-06-20

    A network of interconnected processors is formed from a vertex symmetric graph selected from graphs GAMMA/sub d/(k) with degree d, diameter k, and (d + 1)exclamation/ (d /minus/ k + 1)exclamation processors for each d greater than or equal to k and GAMMA/sub d/(k, /minus/1) with degree d /minus/ 1, diameter k + 1, and (d + 1)exclamation/(d /minus/ k + 1)exclamation processors for each d greater than or equal to k greater than or equal to 4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network GAMMA/sub d/(k, /minus/1) is provided, no processor has a channel connected to form an edge in a direction delta/sub 1/. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations. 9 figs.

  17. Effects of hydration on laser soldering

    NASA Astrophysics Data System (ADS)

    Chan, Eric K.; Brown, Dennis T.; Kovach, Ian S.; Welch, Ashley J.

    1997-05-01

    Laser welding with albumin-based tissue solder has been investigated as an alternative to surgical suturing. Many surgical procedures require the soldered tissues to be in a hydrated environment. We have studied the effects of hydration on laser soldered rat dermis and baboon articular cartilage in vitro. The solder is composed of human serum albumin, sodium hyaluronate and indocyanine green. We used a micro-pipette to deposit 2 (mu) l of solder on each tissue specimen. An 808 nm cw laser beam with irradiance of 27 W/cm2 was scanned 4 times over the same solder area at a constant speed of 0.84 mm/sec. After photo-coagulation, each tissue specimen was cut into two halves at the center of the solder, perpendicular to the direction of the scanning laser beam. One half was reserved as control while the other half was soaked in phosphate buffered saline for a designated hydration period. The hydration periods were 1 hr, 1, 2, and 7 days. All tissue specimens were fixed in glutaraldahyde, then prepared for scanning electron microcopy analysis. For most of the specimens, there was non-uniform coagulation across the thickness of the solder. Closer to the laser beam, the upper solder region formed a more dense coagulum. While the region closer to solder-tissue interface, the solder aggregated into small globules. This non-uniform coagulation was likely caused by non-uniform energy distribution during photocoagulation. The protein globules and coagulum seem to be responsible for the solder attachment from the specimen surface. However, we have noted that the solder detached from the cartilage substrate as early as after 1 hr of hydration. On the other hand, the solder attached to the dermis much better than to cartilage. This may be explained by the difference in surface roughness of the two tissue types. The dermal layer of the skin is composed of collagen matrix which may provide a better entrapment of the solder than the smooth surface of articular cartilage.

  18. Electronic hidden solder joint geometry characterization

    NASA Astrophysics Data System (ADS)

    Hsieh, Sheng-Jen

    2009-05-01

    To reduce the size of electronic equipment, multi-layer printed circuit board structures have become popular in recent years. As a result, the inspection of hidden solder joints between layers of boards has become increasingly difficult. Xray machines have been used for ball grid array (BGA) and hidden solder joint inspection; however, the equipment is costly and the inspection process is time consuming. In this paper, we investigate an active thermography approach to probing solder joint geometry. A set of boards having the same number of solder joints and amount of solder paste (0.061 g) was fabricated. Each solder joint had a different geometry. A semi-automated system was built to heat and then transfer each board to a chamber where an infrared camera was used to scan the board as it was cooling down. Two-thirds of the data set was used for model development and one-third was used for model evaluation. Both artificial neural network (ANN) and binary logistic regression models were constructed. Results suggest that solder joints with more surface area cool much faster than those with less surface area. In addition, both modeling approaches are consistent in predicting solder geometry; ANN had 85% accuracy and the regression model had 80%. This approach can potentially be used to test for cold solder joints prior to BGA assembly, since cold solder joints may have air gaps between the joint and the board and air is a poor heat conductor. Therefore, a cold solder joint may have a slower cooling rate than a normal one.

  19. Modeling the solid-state reaction between Sn-Pb solder and a porous substrate coating

    SciTech Connect

    Erickson, K.L.; Hopkins, P.L.; Vianco, P.T.

    1998-11-01

    Solder joints in hybrid microelectronic circuit electronics are formed between the solder alloy and the noble metal thick film conductor that has been printed and fired onto the ceramic. Although the noble metal conductors provide excellent solderability at the time of manufacture, they are susceptible to solid-state reactions with Sn or other constituents of the solder. The reaction products consist of one or more intermetallic compounds (IMC). The integrity of these solder joints can be jeopardized by formation of IMC layers, which can have thermal and mechanical properties that are substantially different from the solder and substrate and which can consume the conductor layer by solid-state reaction. Analytical models predicting IMC growth for a variety of conditions are needed to improve predictions of long-term joint reliability and manufacturing processes. This paper discusses initial 2-D results from a coupled experimental and computational effort to develop a mathematical model and computer code that will ultimately predict 3-D results from a coupled experimental and computational effort to develop a mathematical model and computer code that will ultimately predict 3-D intermetallic growth in porous substrate-solder systems. The numerical model is based on an implicit interface tracking approach developed for diffusion-reaction analyses in complicated geometries. To illustrate the implicit approach with a real system, the 2-D calculations were based on the reaction couple formed between 63Sn-37Pb solder and 76Au-21Pt-3Pd substrates. Physical constants in the model were evaluated from experimental data. Consumption of the thick film was predicted as a function of time and compared with data from independent experiments.

  20. Effect of interface microstructure on the mechanical properties of Pb-free hybrid microcircuit solder joints

    SciTech Connect

    Hernandez, C.L.; Vianco, P.T.; Rejent, J.A.

    1998-08-01

    Although Sn-Pb eutectic alloy is widely used as a joining material in the electronics industry, it has well documented environmental and toxicity issues. Sandia National Laboratories is developing alternative solder materials to replace traditional Pb-containing alloys. The alloys are based on the Sn-Ag, Sn-Ag-Bi and Sn-Ag-Bi-Au systems. Prototype hybrid microcircuit (HMC) test vehicles have been developed to evaluate these Pb-free solders, using Au-Pt-Pd thick film metallization. Populated test vehicles with surface mount devices have been designed and fabricated to evaluate the reliability of surface mount solder joints. The test components consist of a variety of dummy chip capacitors and leadless ceramic chip carriers (LCCC`s). Intermetallic compound (IMC) layer reaction products that form at the solder/substrate interface have been characterized and their respective growth kinetics quantified. Thicker IMC layers pose a potential reliability problem with solder joint integrity. Since the IMC layer is brittle, the likelihood of mechanical failure of a joint in service is increased. The effect of microstructure and the response of these different materials to wetting, aging and mechanical testing was also investigated. Solid-state reaction data for intermetallic formation and mechanical properties of the solder joints are reported.

  1. Development of extremely ductile lead-free Sn-Al solders for futuristic electronic packaging applications

    NASA Astrophysics Data System (ADS)

    Alam, Md Ershadul; Gupta, Manoj

    2014-03-01

    In the present study, new lead-free Sn-Al solders are developed incorporating varying amount of Al (0.4 and 0.6% by weight) into pure Sn using disintegrated melt deposition technique. Solder samples were then subsequently extruded at room temperature and characterized. Microstructural characterization studies revealed equiaxed grain morphology, minimal porosity, reasonably uniform distribution of Al particles and good Sn-Al interfacial integrity. Melting temperature of Sn-0.6Al (228°C) was found to be close to the eutectic Sn-0.7Cu (227°C) solders. Microhardness was increased with increasing amount of Al in pure Sn. Room temperature tensile test results revealed that newly developed Sn-0.6Al solders exhibited significant improvement in 0.2% yield strength (˜67%), ultimate tensile strength (˜18%) and ductility (˜123%) when compared to commercial Sn-0.7Cu solder. Ductility was improved about 222%, 263% and 81% when compared to commercially available Sn-3.5Ag-0.7Cu, Sn-3.5Ag and Sn-37Pb solders, respectively without compromising strength.

  2. Numerical and experimental study of residual stresses and thermal fatigue in soldered electronic assemblies

    NASA Astrophysics Data System (ADS)

    Bourcier, R. J.; Stephens, J. J.

    The assembly examined consists of thin plates of alumina, Kovar, 410 stainless steel and 6061 aluminum bonded together using layers of three different solder alloys: 63% Sn - 37% Pb, 50% Pb - 50% In and 40% In - 40% Sn - 20% Pb. Numerical simulation of the fabrication process was performed using a simplified axisymmetric finite element microcell model of the actual assembly. The alumina, Kovar, 410 stainless steel and 6061 aluminum layers were modeled as temperature-dependent elastic-plastic materials while the solder alloys were treated as creeping solids following solidification. Experimental testing of the solder alloys was used to generate input for the finite element code constitutive models. The numerical results of this study have provided guidelines for the successful fabrication of the subject assembly. In particular, slower cooling rates following solidification of the solders have been shown to dramatically lower bending stresses generated in the alumina plate. The experimental portion of the program has provided data on the degration of solder bond integrity used to thermal cycling and has identified possible important factors in the mechanical response of thin solder layers.

  3. Nano-soldering to single atomic layer

    DOEpatents

    Girit, Caglar O.; Zettl, Alexander K.

    2011-10-11

    A simple technique to solder submicron sized, ohmic contacts to nanostructures has been disclosed. The technique has several advantages over standard electron beam lithography methods, which are complex, costly, and can contaminate samples. To demonstrate the soldering technique graphene, a single atomic layer of carbon, has been contacted, and low- and high-field electronic transport properties have been measured.

  4. Experiments and Demonstrations with Soldering Guns.

    ERIC Educational Resources Information Center

    Henry, Dennis C.; Danielson, Sarah A.

    1993-01-01

    Discusses the essential electrical characteristics of a particular model of soldering gun. Presents four classroom demonstrations that utilize the soldering gun to test the following geometrics of wire loops as electromagnets: (1) the original tip; (2) a single circular loop; (3) a Helmholtz coil; and (4) the solenoid. (MDH)

  5. Development of a Robust and Integrated Methodology for Predicting the Reliability of Microelectronic Packaging Systems

    NASA Astrophysics Data System (ADS)

    Fallah-Adl, Ali

    Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.

  6. Cartan's soldered spaces and conservation laws in physics

    NASA Astrophysics Data System (ADS)

    Kouneiher, Joseph; Barbachoux, Cécile

    2015-06-01

    In this paper, we will introduce a generalized soldering p-forms geometry, which can be the right framework to describe many new approaches and concepts in modern physics. Here we will treat some aspects of the theory of local cohomology in fields theory or more precisely the theory of soldering-form conservation laws in physics. We provide some illustrative applications, primarily taken from the Einstein equations of general theory of relativity and Yang-Mills theory. This theory can be considered to be a generalization of Noether's theory of conserved current to differential forms of any degree. An essential result of this, is that the conservation of the energy-momentum in general relativity, is linked to the fact that the vacuum field equations are equivalent to the integrability conditions of a first-order system of differential equations. We also apply the idea of the soldered space and the integrability conditions to the case of Yang-Mills theory. The mathematical framework, where these intuitive considerations would fit naturally, can be used to describe also the dynamics of changing manifolds.

  7. An Accelerated Method for Soldering Testing

    SciTech Connect

    Han, Qingyou; Xu, Hanbing; Ried, Paul; Olson, Paul

    2007-01-01

    An accelerated method for testing die soldering has been developed. High intensity ultrasonic vibrations have been applied to simulate the die casting conditions such as high pressure and high molten metal velocity on the pin. The soldering tendency of steels and coated pins has been examined. The results suggest that in the low carbon steel/Al system, the onset of soldering is 60 times faster with ultrasonic vibration than that without ultrasonic vibration. In the H13/A380 system, the onset of soldering reaction is accelerated to between 30-60 times. Coatings significantly reduce the soldering tendency. For purposes of this study, several commercial coatings from Balzers demonstrated the potential for increasing the service life of core pins between 15 and 180 times.

  8. Solderability enhancement of copper through chemical etching

    SciTech Connect

    Stevenson, J.O.; Guilinger, T.R.; Hosking, F.M.; Yost, F.G.; Sorensen, N.R.

    1995-05-01

    Sandia National Laboratories has established a Cooperative Research and Development Agreement with consortium members of the National Center for Manufacturing Sciences (NCMS) to develop fundamental generic technology in the area of printed wiring board materials and surface finishes. Improved solderability of copper substrates is an important component of the Sandia-NCMS program. The authors are investigating the effects of surface roughness on the wettability and solderability behavior of several different types of copper board finishes. In this paper, the authors present roughness and solderability characterizations for a variety of chemically-etched copper substrates. Initial testing on six chemical etches demonstrate that surface roughness can be greatly enhanced through chemical etching. Noticeable improvements in solder wettability were observed to accompany increases in roughness. A number of different algorithms and measures of roughness were used to gain insight into surface morphologies that lead to improved solderability.

  9. Thermophysical Characteristics of the Protective Coating of the Soldering Rod

    NASA Astrophysics Data System (ADS)

    Shtennikov, V. N.

    2015-01-01

    An analytical dependence of the change in the soldering temperature on the material, thickness of the soldering rod protective coating, and the time of soldering is obtained. The relation derived allows one to ensure the needed temperature of contact soldering of electronic and electrical-engineering components and, consequently, their high quality.

  10. Improving student comprehension of the interconnectivity of the hydrologic cycle with a novel 'hydrology toolbox', integrated watershed model, and companion textbook

    NASA Astrophysics Data System (ADS)

    Huning, L. S.; Margulis, S. A.

    2013-12-01

    Concepts in introductory hydrology courses are often taught in the context of process-based modeling that ultimately is integrated into a watershed model. In an effort to reduce the learning curve associated with applying hydrologic concepts to real-world applications, we developed and incorporated a 'hydrology toolbox' that complements a new, companion textbook into introductory undergraduate hydrology courses. The hydrology toolbox contains the basic building blocks (functions coded in MATLAB) for an integrated spatially-distributed watershed model that makes hydrologic topics (e.g. precipitation, snow, radiation, evaporation, unsaturated flow, infiltration, groundwater, and runoff) more user-friendly and accessible for students. The toolbox functions can be used in a modular format so that students can study individual hydrologic processes and become familiar with the hydrology toolbox. This approach allows such courses to emphasize understanding and application of hydrologic concepts rather than computer coding or programming. While topics in introductory hydrology courses are often introduced and taught independently or semi-independently, they are inherently interconnected. These toolbox functions are therefore linked together at the end of the course to reinforce a holistic understanding of how these hydrologic processes are measured, interconnected, and modeled. They are integrated into a spatially-distributed watershed model or numerical laboratory where students can explore a range of topics such as rainfall-runoff modeling, urbanization, deforestation, watershed response to changes in parameters or forcings, etc. Model output can readily be visualized and analyzed by students to understand watershed response in a real river basin or a simple 'toy' basin. These tools complement the textbook, each of which has been well received by students in multiple hydrology courses with various disciplinary backgrounds. The same governing equations that students have

  11. Polymeric optoelectronic interconnects

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.

    2000-04-01

    Electrical interconnects are reaching their fundamental limits and are becoming the speed bottleneck as processor speeds are increasing. A polymer-based interconnect technology was developed for affordable integrated optical circuits that address the optical signal processing needs in the telecom, datacom, and performance computing industries. We engineered organic polymers that can be readily made into single-mode, multimode, and micro-optical waveguide structures of controlled numerical apertures and geometries. These materials are formed from highly-crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, robustness, optical loss, thermal stability, and humidity resistance. These monomers are intermiscible, providing for precise continuous adjustment of the refractive index over a wide range. In polymer form, they exhibit state-of-the-art loss values and exceptional environmental stability, enabling use in a variety of demanding applications. A wide range of rigid and flexible substrates can be used, including glass, quartz, silicon, glass-filled epoxy printed circuit board substrates, and flexible plastic films. The devices we describe include a variety of routing elements that can be sued as part of a massively parallel photonic integrated circuit on the MCM, board, or backplane level.

  12. Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

    NASA Astrophysics Data System (ADS)

    Shima, K.; Tu, Y.; Takamizawa, H.; Shimizu, H.; Shimizu, Y.; Momose, T.; Inoue, K.; Nagai, Y.; Shimogaki, Y.

    2014-09-01

    We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

  13. Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

    SciTech Connect

    Shima, K.; Shimizu, H.; Momose, T.; Shimogaki, Y.; Tu, Y.; Takamizawa, H.; Shimizu, Y.; Inoue, K.; Nagai, Y.

    2014-09-29

    We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

  14. Fatigue failure kinetics and structural changes in lead-free interconnects due to mechanical and thermal cycling

    NASA Astrophysics Data System (ADS)

    Fiedler, Brent Alan

    Environmental and human health concerns drove European parliament to mandate the Reduction of Hazardous Substances (RoHS) for electronics. This was enacted in July 2006 and has practically eliminated lead in solder interconnects. There is concern in the electronics packaging community because modern lead-free solder is rich in tin. Presently, near-eutectic tin-silver-copper solders are favored by industry. These solders are stiffer than the lead-tin near-eutectic alloys, have a higher melting temperature, fewer slip systems, and form intermetallic compounds (IMC) with Cu, Ni and Ag, each of which tend to have a negative effect on lifetime. In order to design more reliable interconnects, the experimental observation of cracking mechanisms is necessary for the correct application of existing theories. The goal of this research is to observe the failure modes resulting from mode II strain and to determine the damage mechanisms which describe fatigue failures in 95.5 Sn- 4.0 Ag - 0.5 Cu wt% (SAC405) lead-free solder interconnects. In this work the initiation sites and crack paths were characterized for SAC405 ball-grid array (BGA) interconnects with electroless-nickel immersion-gold (ENIG) pad-finish. The interconnects were arranged in a perimeter array and tested in fully assembled packages. Evaluation methods included monotonic and displacement controlled mechanical shear fatigue tests, and temperature cycling. The specimens were characterized using metallogaphy, including optical and electron microscopy as well as energy dispersive spectroscopy (EDS) and precise real-time electrical resistance structural health monitoring (SHM). In mechanical shear fatigue tests, strain was applied by the substrates, simulating dissimilar coefficients of thermal expansion (CTE) between the board and chip-carrier. This type of strain caused cracks to initiate in the soft Sn-rich solder and grow near the interface between the solder and intermetallic compounds (IMC). The growth near

  15. Design and analysis of tilt integral derivative controller with filter for load frequency control of multi-area interconnected power systems.

    PubMed

    Kumar Sahu, Rabindra; Panda, Sidhartha; Biswal, Ashutosh; Chandra Sekhar, G T

    2016-03-01

    In this paper, a novel Tilt Integral Derivative controller with Filter (TIDF) is proposed for Load Frequency Control (LFC) of multi-area power systems. Initially, a two-area power system is considered and the parameters of the TIDF controller are optimized using Differential Evolution (DE) algorithm employing an Integral of Time multiplied Absolute Error (ITAE) criterion. The superiority of the proposed approach is demonstrated by comparing the results with some recently published heuristic approaches such as Firefly Algorithm (FA), Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) optimized PID controllers for the same interconnected power system. Investigations reveal that proposed TIDF controllers provide better dynamic response compared to PID controller in terms of minimum undershoots and settling times of frequency as well as tie-line power deviations following a disturbance. The proposed approach is also extended to two widely used three area test systems considering nonlinearities such as Generation Rate Constraint (GRC) and Governor Dead Band (GDB). To improve the performance of the system, a Thyristor Controlled Series Compensator (TCSC) is also considered and the performance of TIDF controller in presence of TCSC is investigated. It is observed that system performance improves with the inclusion of TCSC. Finally, sensitivity analysis is carried out to test the robustness of the proposed controller by varying the system parameters, operating condition and load pattern. It is observed that the proposed controllers are robust and perform satisfactorily with variations in operating condition, system parameters and load pattern. PMID:26712682

  16. Solder flow on narrow copper strips

    SciTech Connect

    Hosking, F.M.; Yost, F.G.; Holm, E.A.; Michael, J.R.

    1996-07-01

    Various solderability tests have been developed over the years to quantify the wetting behavior of solder on metallic surfaces. None offer an exact measure of capillary flow normally associated with conventional plated-through-hole and surface mount soldering. With shrinking package designs, increasing reliability requirements, and the emergence of new soldering technologies, there is a growing need to better understand and predict the flow of solder on printed wiring board (PWB) surfaces. Sandia National Laboratories has developed a capillary flow solderability test, through a joint effort with the National Center for Manufacturing Sciences, that considers this fundamental wetting issue for surface mount technology. The test geometry consists of a metal strip (width, {delta}) connected to a circular metal pad (radius, r{sub c}). Solder flow from the pad onto the strip depends on the geometric relationship between {delta} and r{sub c}. Test methodology, experimental results, and validation of a flow model are presented in this paper. 17 refs., 11 figs., 4 tabs.

  17. Solderability of melting lead-free solder to tiny joint of electronic products

    NASA Astrophysics Data System (ADS)

    Chen, Fang; Du, Changhua; Du, Yunfei

    2005-12-01

    The behavior of melting solder has an important influence on the tiny joints of electronic products. In order to improve the properties of lead-free solder, a Sn-3.5Ag0.6Cu alloy was smelted using traditional and a modified technology, respectively. The solderability of the two alloys were investigated using a wetting balance method for the different conditions. The test results showed that the modified solder had good solderability, where the excellent flux used was rosin-ethanol or rosin-isopropanol solution. In experimental condition, when the added active agent is 0.4% of rosin mass or 0.1% of solution mass, the wetting velocity and wetting force can be improved 5 times and 1.5 times, respectively. The best soldering parameters are temperature levels less than or equal to 270°, and the soakage time in 2-3s.

  18. Comparison of Extensive Thermal Cycling Effects on Microstructure Development in Micro-alloyed Sn-Ag-Cu Solder Joints

    SciTech Connect

    Anderson, Iver E.; Boesenberg, Adam; Harringa, Joel; Riegner, David; Steinmetz, Andrew; Hillman, David

    2011-09-28

    Pb-free solder alloys based on the Sn-Ag-Cu (SAC) ternary eutectic have promise for widespread adoption across assembly conditions and operating environments, but enhanced microstructural control is needed. Micro-alloying with elements such as Zn was demonstrated for promoting a preferred solidification path and joint microstructure earlier in simple (Cu/Cu) solder joints studies for different cooling rates. This beneficial behavior now has been verified in reworked ball grid array (BGA) joints, using dissimilar SAC305 (Sn-3.0Ag-0.5Cu, wt.%) solder paste. After industrial assembly, BGA components joined with Sn-3.5Ag-0.74Cu-0.21Zn solder were tested in thermal cycling (-55 C/+125 C) along with baseline SAC305 BGA joints beyond 3000 cycles with continuous failure monitoring. Weibull analysis of the results demonstrated that BGA components joined with SAC + Zn/SAC305 have less joint integrity than SAC305 joints, but their lifetime is sufficient for severe applications in consumer, defense, and avionics electronic product field environments. Failure analysis of the BGA joints revealed that cracking did not deviate from the typical top area (BGA component side) of each joint, in spite of different Ag3Sn blade content. Thus, SAC + Zn solder has not shown any advantage over SAC305 solder in these thermal cycling trials, but other characteristics of SAC + Zn solder may make it more attractive for use across the full range of harsh conditions of avionics or defense applications.

  19. Laser Assisted Soldering: Effects of Hydration on Solder-Tissue Adhesion

    SciTech Connect

    Chan, E.K.; Welch, A.J.; Brown, D.T.; Kovach, I.S.

    1998-10-01

    Wound stabilization is critical in early wound healing. Other than superficial skin wounds, most tissue repair is exposed to a hydrated environment postoperatively. To simulate the stability of laser-soldered tissue in a wet environment, we studied the effects of hydration on laser soldered rat dermis and baboon articular cartilage. In this {ital in vitro} study, we used a solder composed of human serum albumin, sodium hyaluronate, and Indocyanine Green. A 2 {mu}L solder droplet was deposited on each tissue specimen and then the solder was irradiated with a scanning laser beam (808 nm and 27thinspW/cm{sup 2}). After photocoagulation, each tissue specimen was cut into two halves dividing the solder. One half was reserved as control while the other half was soaked in saline for a designated period before fixation (1 h, 1, 2, and 7 days). All tissue specimens were prepared for scanning electron microscopy (SEM). SEM examinations revealed nonuniform coagulation across the solder thickness for most of the specimens, likely a result of the temperature gradient generated by laser heating. Closer to the laser beam, the uppermost region of the solder formed a dense coagulum. The solder aggregated into small globules in the region anterior to the solder-tissue interface. All cartilage specimens soaked in saline suffered coagulum detachment from tissue surface. We noted a high concentration of the protein globules in the detached coagulum. These globules were likely responsible for solder detachment from the cartilage surface. Solder adhered better to the dermis than to cartilage. The dermal layer of the skin, composed of collagen matrix, provided a better entrapment of the solder than the smooth surface of articular cartilage. Insufficient laser heating of solder formed protein globules. Unstable solder-tissue fusion was likely a result of these globules being detached from tissue substrate when the specimen was submerged in a hydrated environment. The solder-tissue bonding

  20. Multichip packaging technology with laser-patterned interconnects

    NASA Astrophysics Data System (ADS)

    Barfknecht, Andrew T.; Tuckerman, David B.; Kaschmitter, James L.; McWilliams, Bruce M.

    1989-04-01

    A multichip silicon-on-silicon packaging technology was developed which incorporates laser-patterned thin-film interconnects. This technology is particularly suited for application in high speed, high power, and high I/O systems where its unique characteristics provide many advantages over more traditional methods. The laser-patterned thin-film interconnects allow higher I/O densities and better electrical performance than wire bonds or TAB. The face-up, thin-film eutectic die attach technique used provides much lower thermal resistance between the substrate and the chips than solder bump die attach can achieve. In addition, laser-patterned interconnects demonstrate superior ruggedness and fatigue resistance under thermomechanical cycling and shock. This technology was used to produce a 10-chip memory module, samples of which were tested to relevant methods of MIL-STD 883C.

  1. Printed Module Interconnects

    SciTech Connect

    Stockert, Talysa R.; Fields, Jeremy D.; Pach, Gregory F.; Mauger, Scott A.; van Hest, Maikel F. A. M.

    2015-06-14

    Monolithic interconnects in photovoltaic modules connect adjacent cells in series, and are typically formed sequentially involving multiple deposition and scribing steps. Interconnect widths of 500 um every 10 mm result in 5% dead area, which does not contribute to power generation in an interconnected solar panel. This work expands on previous work that introduced an alternative interconnection method capable of producing interconnect widths less than 100 um. The interconnect is added to the module in a single step after deposition of the photovoltaic stack, eliminating the need for scribe alignment. This alternative method can be used for all types of thin film photovoltaic modules. Voltage addition with copper-indium-gallium-diselenide (CIGS) solar cells using a 2-scribe printed interconnect approach is demonstrated. Additionally, interconnect widths of 250 um are shown.

  2. Computational modeling of direct molten solder delivery for ball grid array applications

    SciTech Connect

    Essien, M.; Frear, D.; Sackinger, P.

    1996-09-01

    Computational modeling has been performed to determine optimum operational parameters for a piston-driven molten solder jetting device used to create array interconnects for BGA applications. The device is capable of delivering a 20 x 20 array of 600-800 {mu}m diameter molten 60Sn40Pb solder droplets onto an array of copper pads and primarily consists of an electromechanically driven piston, a heated reservoir, and an orifice plate. computer simulations were performed to determine the relationship between the amplitude and the rate of piston displacement, the onset of fluid ``pinch off``, and the production of satellite droplets. Results show that stable droplets are generated when the volume of the displaced fluid has a spherical diameter that is approximately equal to the orifice diameter.

  3. A study of thermal cycling and radiation effects on indium and solder bump bonding

    SciTech Connect

    Selcuk Cihangir et al.

    2001-09-12

    The BTeV hybrid pixel detector is constructed of readout chips and sensor arrays which are developed separately. The detector is assembled by flip-chip mating of the two parts. This method requires the availability of highly reliable, reasonably low cost fine-pitch flip-chip attachment technology. We have tested the quality of two bump-bonding technologies; indium bumps (by Advanced Interconnect Technology Ltd. (AIT) of Hong Kong) and fluxless solder bumps (by MCNC in North Carolina, USA). The results have been presented elsewhere[1]. In this paper we describe tests we performed to further evaluate these technologies. We subjected 15 indium bump-bonded and 15 fluxless solder bump-bonded dummy detectors through a thermal cycle and then a dose of radiation to observe the effects of cooling, heating and radiation on bump-bonds.

  4. Roles of service parameters on the mechanical behavior of lead-free solder joints

    NASA Astrophysics Data System (ADS)

    Rhee, Hongjoo

    2005-07-01

    Lead-based solders have been extensively used as interconnects in various electronic applications due to their low cost and suitable material properties. However, in view of environmental and health concerns, the electronics industry is forced to develop lead-free alternative solders. Eutectic Sn-3.5Ag based solders are being considered as suitable substitutes due to their non-toxicity, tolerable melting temperatures, and comparable mechanical as well as electrical properties. Smaller electronic packaging and emerging new technologies impose several constraints on the solder interconnect that require better inherent properties in the solder to resist failure during operation. Hence, it is important to develop a clear understanding of the deformation behavior of eutectic Sn-Ag solder joints. Mechanical characterization was performed to investigate the behavior of eutectic Sn-Ag solder joints. Peak shear stress and flow stress decreased with increasing testing temperature and with decreasing simple shear-strain rate. The effect of simple shear-strain rate on the peak shear stress was found to be more significant at temperature regimes less than 125°C. The deformation structure of specimens deformed at higher temperatures was dominated by grain boundary deformation, while at lower temperatures it was dominated by shear banding. Stress relaxation studies on eutectic Sn-Ag solder joints were carried out to provide a better understanding of various parameters contributing to thermomechanical damage accumulation. Monotonic stress relaxation tests at various pre-strain conditions and testing temperatures can provide information relevant to the effects of ramp rates during heating and cooling excursions experienced during thermomechanical fatigue. Peak shear stress and residual shear stress, resulting from stress relaxation period, decreased with increasing testing temperature for a given pre-strain condition. A faster ramp rate was found to cause higher resultant residual

  5. Alining Solder Pads on a Solar Cell

    NASA Technical Reports Server (NTRS)

    Lazzery, A. G.

    1984-01-01

    Mechanism consisting of stylus and hand-operated lever incorporated into screening machine to precisely register front and back solder pads during solar-cell assembly. Technique may interest those assembling solar cells manually for research or prototype work.

  6. High temperature solder device for flat cables

    NASA Technical Reports Server (NTRS)

    Haehner, Carl L. (Inventor)

    1992-01-01

    A high temperature solder device for flat cables includes a microwelder, an anvil which acts as a heat sink and supports a flexible flat ribbon cable that is to be connected to a multiple pin connector. The microwelder is made from a modified commercially available resistance welding machine such as the Split Tip Electrode microwelder by Weltek, which consists of two separate electrode halves with a removable dielectric spacer in between. The microwelder is not used to weld the items together, but to provide a controlled compressive force on, and energy pulse to, a solder preform placed between a pin of the connector and a conductor of the flexible flat ribbon cable. When the microwelder is operated, an electric pulse will flow down one electrode, through the solder preform and back up the other electrode. This pulse of electrical energy will cause the solder preform to heat up and melt, joining the pin and conductor.

  7. Interconnecting conductively coated coverslides. [for ISEE-1

    NASA Technical Reports Server (NTRS)

    Gaddy, E. M.; Bass, J. A.

    1978-01-01

    The International Sun Earth Explorer-1 has the requirement that the entire outer surface of the spacecraft be conductive. A transparent coating of indium oxide was deposited for that reason on the satellite's solar cell coverglasses in order to give them a conductive surface, and the surfaces were interconnected to ground. This paper examines the interconnector attachment problem. On the ISEE-1, wires were bonded to the coverglasses by using a conductive epoxy; the resistance of these bonds increased dramatically with time. A program was initiated to find the functional cause of the resistance increase and to flight-qualify an alternative method of bonding. It was found the tests initiated were insufficient to find the cause of resistance increase and that an alternative solution of using indium solder is acceptable for bonding wires directly to indium oxide.

  8. Whisker Formation on SAC305 Soldered Assemblies

    NASA Astrophysics Data System (ADS)

    Meschter, S.; Snugovsky, P.; Bagheri, Z.; Kosiba, E.; Romansky, M.; Kennedy, J.; Snugovsky, L.; Perovic, D.

    2014-11-01

    This article describes the results of a whisker formation study on SAC305 assemblies, evaluating the effects of lead-frame materials and cleanliness in different environments: low-stress simulated power cycling (50-85°C thermal cycling), thermal shock (-55°C to 85°C), and high temperature/high humidity (85°C/85% RH). Cleaned and contaminated small outline transistors, large leaded quad flat packs (QFP), plastic leaded chip carrier packages, and solder balls with and without rare earth elements (REE) were soldered to custom designed test boards with Sn3Ag0.5Cu (SAC305) solder. After assembly, all the boards were cleaned, and half of them were recontaminated (1.56 µg/cm2 Cl-). Whisker length, diameter, and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets, where the thickness is less than 25 µm, unless REE was present. The influence of lead-frame and solder ball material, microstructure, cleanliness, and environment on whisker characteristics is discussed. This article provides detailed metallurgical observations and select whisker length data obtained during this multiyear testing program.

  9. Integrated wireless neural interface based on the Utah electrode array.

    PubMed

    Kim, S; Bhandari, R; Klein, M; Negi, S; Rieth, L; Tathireddy, P; Toepper, M; Oppermann, H; Solzbacher, F

    2009-04-01

    This report presents results from research towards a fully integrated, wireless neural interface consisting of a 100-channel microelectrode array, a custom-designed signal processing and telemetry IC, an inductive power receiving coil, and SMD capacitors. An integration concept for such a device was developed, and the materials and methods used to implement this concept were investigated. We developed a multi-level hybrid assembly process that used the Utah Electrode Array (UEA) as a circuit board. The signal processing IC was flip-chip bonded to the UEA using Au/Sn reflow soldering, and included amplifiers for up to 100 channels, signal processing units, an RF transmitter, and a power receiving and clock recovery module. An under bump metallization (UBM) using potentially biocompatible materials was developed and optimized, which consisted of a sputter deposited Ti/Pt/Au thin film stack with layer thicknesses of 50/150/150 nm, respectively. After flip-chip bonding, an underfiller was applied between the IC and the UEA to improve mechanical stability and prevent fluid ingress in in vivo conditions. A planar power receiving coil fabricated by patterning electroplated gold films on polyimide substrates was connected to the IC by using a custom metallized ceramic spacer and SnCu reflow soldering. The SnCu soldering was also used to assemble SMD capacitors on the UEA. The mechanical properties and stability of the optimized interconnections between the UEA and the IC and SMD components were measured. Measurements included the tape tests to evaluate UBM adhesion, shear testing between the Au/Sn solder bumps and the substrate, and accelerated lifetime testing of the long-term stability for the underfiller material coated with a a-SiC(x):H by PECVD, which was intended as a device encapsulation layer. The materials and processes used to generate the integrated neural interface device were found to yield a robust and reliable integrated package. PMID:19067174

  10. Microstructural influences on the mechanical properties of solder

    SciTech Connect

    Morris, J.W. Jr.; Goldstein, J.L.F.; Mei, Z.

    1993-04-01

    Intent of this book is to review analytic methods for predicting behavior of solder joints, based on continuum mechanics. The solder is treated as a continuous, homogeneous body, or composite of such bodies, whose mechanical behavior is uniform and governed by simple constitutive equations. The microstructure of a solder joint influences its mechanical properties in 3 ways: it governs deformation and failure; common solders deform inhomogeneously; and common solders are microstructurally unstable. The variety of microstructures often found in solder joints are briefly reviewed, and some of the ways are discussed in which the microstructure influences the common types of high-temperature mechanical behavior. 25 figs, 40 refs.

  11. Use of organic solderability preservatives on solderability retention of copper after accelerated aging

    SciTech Connect

    Hernandez, C.L.; Sorensen, N.R.; Lucero, S.J.

    1997-02-01

    Organic solderability preservatives (OSP`s) have been used by the electronics industry for some time to maintain the solderability of circuit boards and components. Since solderability affects both manufacturing efficiency and product reliability, there is significant interest in maintaining good solder wettability. There is often a considerable time interval between the initial fabrication of a circuit board or component and its use at the assembly level. Parts are often stored under a variety of conditions, in many cases not well controlled. Solder wettability can deteriorate during storage, especially in harsh environments. This paper describes the ongoing efforts at Sandia National Laboratories to quantify solder watability on bare and aged copper surfaces. Benzotriazole and imidazole were applied to electronic grade copper to retard aging effects on solderability. The coupons were introduced into Sandia`s Facility for Atmospheric Corrosion Testing (FACT) to simulate aging in a typical indoor industrial environment. H{sub 2}S, NO{sub 2} and Cl{sub 2} mixed gas was introduced into the test cell and maintained at 35{degrees}C and 70% relative humidity for test periods of one day to two weeks. The OSP`s generally performed better than bare Cu, although solderability diminished with increasing exposure times.

  12. Sensitivity of Solder Joint Fatigue to Sources of Variation in Advanced Vehicular Power Electronics Cooling

    SciTech Connect

    Vlahinos, A.; O'Keefe, M.

    2010-06-01

    This paper demonstrates a methodology for taking variation into account in thermal and fatigue analyses of the die attach for an inverter of an electric traction drive vehicle. This method can be used to understand how variation and mission profile affect parameters of interest in a design. Three parameters are varied to represent manufacturing, material, and loading variation: solder joint voiding, aluminum nitride substrate thermal conductivity, and heat generation at the integrated gate bipolar transistor. The influence of these parameters on temperature and solder fatigue life is presented. The heat generation loading variation shows the largest influence on the results for the assumptions used in this problem setup.

  13. Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

    NASA Astrophysics Data System (ADS)

    Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

    2001-11-01

    The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

  14. A systems approach to solder joint fatigue in spacecraft electronic packaging

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.

    1991-01-01

    Differential expansion induced fatigue resulting from temperature cycling is a leading cause of solder joint failures in spacecraft. Achieving high reliability flight hardware requires that each element of the fatigue issue be addressed carefully. This includes defining the complete thermal-cycle environment to be experienced by the hardware, developing electronic packaging concepts that are consistent with the defined environments, and validating the completed designs with a thorough qualification and acceptance test program. This paper describes a useful systems approach to solder fatigue based principally on the fundamental log-strain versus log-cycles-to-failure behavior of fatigue. This fundamental behavior has been useful to integrate diverse ground test and flight operational thermal-cycle environments into a unified electronics design approach. Each element of the approach reflects both the mechanism physics that control solder fatigue, as well as the practical realities of the hardware build, test, delivery, and application cycle.

  15. Prototyping lead-free solders on hand-soldered, through-hole circuit boards

    SciTech Connect

    Vianco, P.T.; Mizik, P.M.

    1993-12-31

    The lead-free solders 96.5Sn-3.5Ag (wt %), 95.5Sn-4.0Cu-0.5Ag, 91. 84Sn-3.33Ag-4.83Bi were used in the assembly of a through-hole circuit board to determine the feasibility of their suitability in hand soldering processes. Prototypes assembled with 63Sn-37Pb solder were manufactured to serve as control units. Implementation of the lead-free alloys were performed with a rosin-based, mildly activated (RMA) flux and a 700{degree}F soldering tip. A procedure was developed to remove the tin-lead finish from the leaded components and replace it with a 100Sn hot dipped coating. Assembly feasibility was demonstrated for all three lead-free solders. Defect counts were greater than observed with the tin-lead control alloy; however, the number of defects diminished with experience gained by the operator. Visual examination of the solder joints indicated satisfactory wetting of both the device leads and circuit board land with no apparent damage to the underlying laminate nor to the device packages. Cross sections of the lead-free solder joints showed that the were more susceptible to void formation within the holes than was the case with the tin-lead solder. Some cracking was observed at the interface between the Sn-Ag-Bi solder and the copper lands; the relatively high strength of this solder and fast cooling rate of the hand assembly process was believed responsible for this defect.

  16. Mechanical Shock Behavior of Environmentally-Benign Lead-free Solders

    NASA Astrophysics Data System (ADS)

    Yazzie, Kyle

    The mechanical behavior of Pb-free solder alloys is important, since they must maintain mechanical integrity under thermomechanical fatigue, creep, and mechanical shock conditions. Mechanical shock, in particular, has become an increasing concern in the electronics industry, since electronic packages can be subjected to mechanical shock by mishandling during manufacture or by accidental dropping. In this study, the mechanical shock behavior of Sn and Sn-Ag-Cu alloys was systematically analyzed over the strain rate range 10-3 -- 30 s-1 in bulk samples, and over 10-3 -- 12 s-1 on the single solder joint level. More importantly, the influences of solder microstructure and intermetallic compounds (IMC) on mechanical shock resistance were quantified. A thorough microstructural characterization of Sn-rich alloys was conducted using synchrotron x-ray computed tomography. The three-dimensional morphology and distribution of contiguous phases and precipitates was analyzed. A multiscale approach was utilized to characterize Sn-rich phases on the microscale with x-ray tomography and focused ion beam tomography to characterize nanoscale precipitates. A high strain rate servohydraulic test system was developed in conjunction with a modified tensile specimen geometry and a high speed camera for quantifying deformation. The effect of microstructure and applied strain rate on the local strain and strain rate distributions were quantified using digital image correlation. Necking behavior was analyzed using a novel mirror fixture, and the triaxial stresses associated with necking were corrected using a self-consistent method to obtain the true stress-true strain constitutive behavior. Fracture mechanisms were quantified as a function of strain rate. Finally, the relationship between solder microstructure and intermetallic compound layer thickness with the mechanical shock resistance of Sn-3.8Ag-0.7Cu solder joints was characterized. It was found that at low strain rates the dynamic

  17. Computer simulation of solder joint failure

    SciTech Connect

    Burchett, S.N.; Frear, D.R.; Rashid, M.M.

    1997-04-01

    The thermomechanical fatigue failure of solder joints is increasingly becoming an important reliability issue for electronic packages. The purpose of this Laboratory Directed Research and Development (LDRD) project was to develop computational tools for simulating the behavior of solder joints under strain and temperature cycling, taking into account the microstructural heterogeneities that exist in as-solidified near eutectic Sn-Pb joints, as well as subsequent microstructural evolution. The authors present two computational constitutive models, a two-phase model and a single-phase model, that were developed to predict the behavior of near eutectic Sn-Pb solder joints under fatigue conditions. Unique metallurgical tests provide the fundamental input for the constitutive relations. The two-phase model mathematically predicts the heterogeneous coarsening behavior of near eutectic Sn-Pb solder. The finite element simulations with this model agree qualitatively with experimental thermomechanical fatigue tests. The simulations show that the presence of an initial heterogeneity in the solder microstructure could significantly degrade the fatigue lifetime. The single-phase model was developed to predict solder joint behavior using materials data for constitutive relation constants that could be determined through straightforward metallurgical experiments. Special thermomechanical fatigue tests were developed to give fundamental materials input to the models, and an in situ SEM thermomechanical fatigue test system was developed to characterize microstructural evolution and the mechanical behavior of solder joints during the test. A shear/torsion test sample was developed to impose strain in two different orientations. Materials constants were derived from these tests. The simulation results from the two-phase model showed good fit to the experimental test results.

  18. African electricity infrastructure, interconnections and exchanges

    SciTech Connect

    Hammons, T.J.; Taher, F.; Gulstone, A.B.; Blyden, B.K.; Johnston, R.; Isekemanga, E.; Paluku, K.; Calitz, A.C.; Simanga, N.N.

    1997-01-01

    A 1996 IEEE PES Summer Meeting panel session focused on African Electricity Infrastructure, Interconnections, and Electricity Exchanges. The session was sponsored by the PES Energy Development and Power Generation Committee and organized/moderated by T.J. Hammons, chair of the International Practices Subcommittee. Panelists discussed energy resources, feasibility studies to interconnect power systems, the present state of the electric power sector, future expansion of African power systems, interconnections and power exchanges, and the impact of the private sector on electricity supply. The presentations were as follows: Prospects of the Evolution of a Unified Interconnection Power System in Africa, Fouad Taher; The World Bank`s Involvement with African Electricity Infrastructure, Alfred Gulstone; Towards the implementation of an Integrated African Grid, Bai K. Blyden, Raymond Johnston; Grand Inga Interconnection Projects, Elese Isekemanga, K. Paluku; The Innovative Southern African Kilowatt Hour, Andries C. Calitz; Report on Burundi, Rwanda, and Zaire, Ngove-Ngulu Simanga.

  19. Age-aware solder performance models : level 2 milestone completion.

    SciTech Connect

    Neilsen, Michael K.; Vianco, Paul Thomas; Neidigk, Matthew Aaron; Holm, Elizabeth Ann

    2010-09-01

    Legislated requirements and industry standards are replacing eutectic lead-tin (Pb-Sn) solders with lead-free (Pb-free) solders in future component designs and in replacements and retrofits. Since Pb-free solders have not yet seen service for long periods, their long-term behavior is poorly characterized. Because understanding the reliability of Pb-free solders is critical to supporting the next generation of circuit board designs, it is imperative that we develop, validate and exercise a solder lifetime model that can capture the thermomechanical response of Pb-free solder joints in stockpile components. To this end, an ASC Level 2 milestone was identified for fiscal year 2010: Milestone 3605: Utilize experimentally validated constitutive model for lead-free solder to simulate aging and reliability of solder joints in stockpile components. This report documents the completion of this milestone, including evidence that the milestone completion criteria were met and a summary of the milestone Program Review.

  20. Electromigration and thermomigration in lead-free tin-silver-copper and eutectic tin-lead flip chip solder joints

    NASA Astrophysics Data System (ADS)

    Ou Yang, Fan-Yi

    Phase separation and microstructure change of eutectic SnPb and SnAgCu flip chip solder joint were investigated under thermomigration, electromigration, stressmigration and the combination of these effects. Different morphological behaviors under DC and AC electromigration were seen. Phase separation with Pb rich phase migration to the anode was observed when current density is below 1.6 x 104 A/cm2 at 100°C. For some cases, phase separation of Pb-rich phase and Su-rich phase as well as refinement of lamellar microstructure has also been observed. We propose that the refinement is due to recrystallization. On the other hand, time-dependent melting of eutectic SnPb flip chip solder joints has been observed to occur frequently with current density above 1.6 x 104 A/cm 2at 100°C. It has been found that it is due to joule heating of the on-chip Al interconnects. We found that electromigration has especially generated voids at the anode of the Al. This damage has greatly increased the resistance of the Al, which produces the heat needed to melt the solder joint. Owing to the line-to-bump configuration in flip chip solder joints, current crowding occurs when electrons enters into or exits from the solder bump. At the cathode contact, current crowding induced pancake-type void formation was observed widely. Furthermore, at the anode contact, we note that hillock or whisker forms. The cross-sectioned surface in SnPb showed dimple and bulge after electromigration, while that of SnAgCu remained flat. The difference is due to a larger back stress in the SnAgCu, consequently electromigration in SnAgCu is slower than that in SnPb. For thermomigration in eutectic SnPb flip chip solder joints, phase separation of Sn and Pb occurred, with Pb moving to the cold end. Both Sn and Pb have a stepwise concentration profile across solder bump. Refinement of lamellar microstructure was observed, indicating recrystallization. Also, thermomigration in eutectic SnAgCu flip chip solder

  1. Electromigration kinetics and critical current of Pb-free interconnects

    SciTech Connect

    Lu, Minhua; Rosenberg, Robert

    2014-04-07

    Electromigration kinetics of Pb-free solder bump interconnects have been studied using a single bump parameter sweep technique. By removing bump to bump variations in structure, texture, and composition, the single bump sweep technique has provided both activation energy and power exponents that reflect atomic migration and interface reactions with fewer samples, shorter stress time, and better statistics than standard failure testing procedures. Contact metallurgies based on Cu and Ni have been studied. Critical current, which corresponds to the Blech limit, was found to exist in the Ni metallurgy, but not in the Cu metallurgy. A temperature dependence of critical current was also observed.

  2. Perforation patterned electrical interconnects

    SciTech Connect

    Frey, Jonathan

    2014-01-28

    This disclosure describes systems and methods for increasing the usable surface area of electrical contacts within a device, such as a thin film solid state device, through the implementation of electrically conductive interconnects. Embodiments described herein include the use of a plurality of electrically conductive interconnects that penetrate through a top contact layer, through one or more multiple layers, and into a bottom contact layer. The plurality of conductive interconnects may form horizontal and vertical cross-sectional patterns. The use of lasers to form the plurality of electrically conductive interconnects from reflowed layer material further aids in the manufacturing process of a device.

  3. Fluxless laser soldering for electronic packaging

    SciTech Connect

    Hosking, F.M.; Keicher, D.M.

    1991-12-31

    Conventional soldering typically requires the use of reactive fluxes to promote wetting. The resulting flux residues are removed primarily with halogenated or chlorofluorocarbon (CFC) solvents. With the mandated phaseout of CFCs by the year 2000, there has been a concentrated effort to develop alternative, environmentally compatible manufacturing and cleaning technologies that will satisfy the restrictions placed on CFCs, but still yield high quality product. Sandia National Laboratories is currently evaluating a variety of alternative fluxless soldering technologies which can be applied to electronic packaging. Laser soldering in a controlled atmosphere has shown great potential as an environmentally compatible process. The effects of laser heating with a 100 watt CW Nd:YAG laser, joint design, and base/filler metal reactions on achieving fluxless wetting with good metallurgical bonds were examined. Satisfactory Ni-Au plated Kovar{reg_sign} solder joints were made with 80In-15Pb-5Ag and 63Sn-37Pb (wt. %) solder alloys in a slightly reducing cover gas. Wetting generally increased with increasing laser power, decreasing laser beam spot size, and decreasing part travel speed. The materials and processing interaction effects are identified and discussed.

  4. Fluxless laser soldering for electronic packaging

    SciTech Connect

    Hosking, F M; Keicher, D M

    1991-01-01

    Conventional soldering typically requires the use of reactive fluxes to promote wetting. The resulting flux residues are removed primarily with halogenated or chlorofluorocarbon (CFC) solvents. With the mandated phaseout of CFCs by the year 2000, there has been a concentrated effort to develop alternative, environmentally compatible manufacturing and cleaning technologies that will satisfy the restrictions placed on CFCs, but still yield high quality product. Sandia National Laboratories is currently evaluating a variety of alternative fluxless soldering technologies which can be applied to electronic packaging. Laser soldering in a controlled atmosphere has shown great potential as an environmentally compatible process. The effects of laser heating with a 100 watt CW Nd:YAG laser, joint design, and base/filler metal reactions on achieving fluxless wetting with good metallurgical bonds were examined. Satisfactory Ni-Au plated Kovar{reg sign} solder joints were made with 80In-15Pb-5Ag and 63Sn-37Pb (wt. %) solder alloys in a slightly reducing cover gas. Wetting generally increased with increasing laser power, decreasing laser beam spot size, and decreasing part travel speed. The materials and processing interaction effects are identified and discussed.

  5. Testing of printed circuit board solder joints by optical correlation

    NASA Technical Reports Server (NTRS)

    Espy, P. N.

    1975-01-01

    An optical correlation technique for the nondestructive evaluation of printed circuit board solder joints was evaluated. Reliable indications of induced stress levels in solder joint lead wires are achievable. Definite relations between the inherent strength of a solder joint, with its associated ability to survive stress, are demonstrable.

  6. Thermal resistances of solder-boss/potting compound combinations

    NASA Technical Reports Server (NTRS)

    Veilleux, E. D.

    1968-01-01

    Formulas, which can be used as a design tool, are derived to calculate the thermal resistance of solder-boss/potting compound combinations, for different depths of a solder boss, in electronic cordwood modules. Since the solder boss is the heat source, its shape and position will affect the thermal resistance of the surrounding potting compound.

  7. Efforts to Develop a 300°C Solder

    SciTech Connect

    Norann, Randy A

    2015-01-25

    This paper covers the efforts made to find a 300°C electrical solder solution for geothermal well monitoring and logging tools by Perma Works LLC. This paper covers: why a high temperature solder is needed, what makes for a good solder, testing flux, testing conductive epoxy and testing intermetallic bonds. Future areas of research are suggested.

  8. Inspection criteria ensure quality control of parallel gap soldering

    NASA Technical Reports Server (NTRS)

    Burka, J. A.

    1968-01-01

    Investigation of parallel gap soldering of electrical leads resulted in recommendation on material preparation, equipment, process control, and visual inspection criteria to ensure reliable solder joints. The recommendations will minimize problems in heat-dwell time, amount of solder, bridging conductors, and damage of circuitry.

  9. Microstructural evolution of eutectic Au-Sn solder joints

    SciTech Connect

    Song, Ho Geon

    2002-05-31

    Current trends toward miniaturization and the use of lead(Pb)-free solder in electronic packaging present new problems in the reliability of solder joints. This study was performed in order to understand the microstructure and microstructural evolution of small volumes of nominally eutectic Au-Sn solder joints (80Au-20Sn by weight), which gives insight into properties and reliability.

  10. A novel method for direct solder bump pull testing using lead-free solders

    NASA Astrophysics Data System (ADS)

    Turner, Gregory Alan

    This thesis focuses on the design, fabrication, and evaluation of a new method for testing the adhesion strength of lead-free solders, named the Isotraction Bump Pull method (IBP). In order to develop a direct solder joint-strength testing method that did not require customization for different solder types, bump sizes, specific equipment, or trial-and-error, a combination of two widely used and accepted standards was created. First, solder bumps were made from three types of lead free solder were generated on untreated copper PCB substrates using an in-house fabricated solder bump-on-demand generator, Following this, the newly developed method made use of a polymer epoxy to encapsulate the solder bumps that could then be tested under tension using a high precision universal vertical load machine. The tests produced repeatable and predictable results for each of the three alloys tested that were in agreement with the relative behavior of the same alloys using other testing methods in the literature. The median peak stress at failure for the three solders tested were 2020.52 psi, 940.57 psi, and 2781.0 psi, and were within one standard deviation of the of all data collected for each solder. The assumptions in this work that brittle fracture occurred through the Intermetallic Compound layer (IMC) were validated with the use of Energy-Dispersive X-Ray Spectrometry and high magnification of the fractured surface of both newly exposed sides of the test specimens. Following this, an examination of the process to apply the results from the tensile tests into standard material science equations for the fracture of the systems was performed..

  11. Thermoelectric Coolers with Sintered Silver Interconnects

    NASA Astrophysics Data System (ADS)

    Kähler, Julian; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2014-06-01

    The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm2 were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm2) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10-5 Ω cm2 was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.

  12. Nanocopper Based Solder-Free Electronic Assembly

    NASA Astrophysics Data System (ADS)

    Schnabl, K.; Wentlent, L.; Mootoo, K.; Khasawneh, S.; Zinn, A. A.; Beddow, J.; Hauptfleisch, E.; Blass, D.; Borgesen, P.

    2014-12-01

    CuantumFuse nano copper material has been used to assemble functional LED test boards and a small camera board with a 48 pad CMOS sensor quad-flat no-lead chip and a 10 in flexible electronics demo. Drop-in replacement of solder, by use of stencil printing and standard surface mount technology equipment, has been demonstrated. Applications in space and commercial systems are currently under consideration. The stable copper-nanoparticle paste has been examined and characterized by scanning electron microscopy and high-resolution transmission electron microscopy; this has shown that the joints are nanocrystalline but with substantial porosity. Assessment of reliability is expected to be complicated by this and by the effects of thermal and strain-enhanced coarsening of pores. Strength, creep, and fatigue properties were measured and results are discussed with reference to our understanding of solder reliability to assess the potential of this nano-copper based solder alternative.

  13. Intelligent laser soldering inspection and process control

    NASA Technical Reports Server (NTRS)

    Vanzetti, Riccardo

    1987-01-01

    Component assembly on printed circuitry keeps making giant strides toward denser packaging and smaller dimensions. From a single layer to multilayer, from through holes to surface mounted components and tape applied bonds, unrelenting progress results in new, difficult problems in assembling, soldering, inspecting and controlling the manufacturing process of the new electronics. Among the major problems are the variables introduced by human operators. The small dimensions and the tight assembly tolerances are now successfully met by machines which are faster and more precise than the human hand. The same is true for soldering. But visual inspection of the solder joints is now so severely limited by the ever shrinking area accessible to the human eye that the inspector's diagnosis cannot be trusted any longer. Solutions to correcting these problems are discussed.

  14. Solder Joint Health Monitoring Testbed System

    NASA Technical Reports Server (NTRS)

    Delaney, Michael M.

    2009-01-01

    The density and pin count for Field Programmable Gate Arrays (FPGAs) has been increasing, and has exceeded current methods of solder joint inspection, making early detection of failures more problematic. These failures are a concern for both flight safety and maintenance in commercial aviation. Ridgetop Group, Inc. has developed a method for detecting solder joint failures in real time. The NASA Dryden Flight Research Center is developing a set of boards to test this method in ground environmental and accelerated testing as well as flight test on a Dryden F-15 or F-18 research aircraft. In addition to detecting intermittent and total solder joint failures, environmental data on the boards, such as temperature and vibration, will be collected and time-correlated to aircraft state data. This paper details the technical approach involved in the detection process, and describes the design process and products to date for Dryden s FPGA failure detection boards.

  15. Solderability Study of RABiTS-Based YBCO Coated Conductors

    SciTech Connect

    Zhang, Yifei; Duckworth, Robert C; Ha, Tam T; Gouge, Michael J

    2011-01-01

    The solderability of commercially available YBa{sub 2}Cu{sub 3}O{sub 7-x} (YBCO) coated conductors that were made from Rolling Assisted Biaxially Textured Substrates (RABiTS)-based templates was studied. The coated conductors, also known as second-generation (2G) high temperature superconductor (HTS) wires (in the geometry of flat tapes about 4 mm wide), were laminated with copper, brass, or stainless steel strips as stabilizers. To understand the factors that influence their solderability, surface profilometry and scanning electron microscopy were used to characterize the wire surfaces. The solderability of three solders, 52In48Sn, 67Bi33In, and 100In (wt.%), was evaluated using a standard test (IPC/ECA J-STD-002) and with two different commercial fluxes. It was found that the solderability varied with the solder and flux but the three different wires showed similar solderability for a fixed combination of solder and flux. Solder joints of the 2G wires were fabricated using the tools and the procedures recommended by the HTS wire manufacturer. The solder joints were made in a lap-joint geometry and with the superconducting sides of the two wires face-to-face. The electrical resistances of the solder joints were measured at 77 K, and the results were analyzed to qualify the soldering materials and evaluate the soldering process. It was concluded that although the selection of soldering materials affected the resistance of a solder joint, the resistivity of the stabilizer was the dominant factor.

  16. Microwave Tissue Soldering for Immediate Wound Closure

    NASA Technical Reports Server (NTRS)

    Arndt, G. Dickey; Ngo, Phong H.; Plan, Chau T.; Byerly, Diane; Dusl, John; Sognier, Marguerite A.

    2011-01-01

    A novel approach for the immediate sealing of traumatic wounds is under development. A portable microwave generator and handheld antenna are used to seal wounds, binding the edges of the wound together using a biodegradable protein sealant or solder. This method could be used for repairing wounds in emergency settings, by restoring the wound surface to its original strength within minutes. This technique could also be utilized for surgical purposes involving solid visceral organs (i.e., liver, spleen, and kidney) that currently do not respond well to ordinary surgical procedures. A miniaturized microwave generator and a handheld antenna are used to deliver microwave energy to the protein solder, which is applied to the wound. The antenna can be of several alternative designs optimized for placement either in contact with or proximity to the protein solder covering the wound. In either case, optimization of the design includes the matching of impedances to maximize the energy delivered to the protein solder and wound at a chosen frequency. For certain applications, an antenna could be designed that would emit power only when it is in direct contact with the wound. The optimum frequency or frequencies for a specific application would depend on the required depth of penetration of the microwave energy. In fact, a computational simulation for each specific application could be performed, which would then match the characteristics of the antenna with the protein solder and tissue to best effect wound closure. An additional area of interest with potential benefit that remains to be validated is whether microwave energy can effectively kill bacteria in and around the wound. Thus, this may be an efficient method for simultaneously sterilizing and closing wounds. Using microwave energy to seal wounds has a number of advantages over lasers, which are currently in experimental use in some hospitals. Laser tissue welding is unsuitable for emergency use because its large, bulky

  17. ESD Test Apparatus for Soldering Irons

    NASA Technical Reports Server (NTRS)

    Sancho, Jose; Esser, Robert

    2013-01-01

    ESDA (Electrostatic Discharge Association) ESD STM 13.1-2000 requires frequent testing of the voltage leakage from the tip of a soldering iron and the resistance from the tip of the soldering iron to the common point ground. Without this test apparatus, the process is time-consuming and requires several wires, alligator clips, or test probes, as well as additional equipment. Soldering iron tips must be tested for electrostatic discharge risks frequently, and this typically takes a lot of time in setup and testing. This device enables the operator to execute the full test in one minute or less. This innovation is a simple apparatus that plugs into a digital multimeter (DMM) and the Common Point Ground (CPG) reference. It enables the user to perform two of the electrostatic discharge tests required in ESD STM 13.1-2000. The device consists of a small black box with two prongs sticking out of one end, two inputs on the opposite end (one of the inputs is used to connect the reference CPG to the DMM), and a metal tab on one side. Inside the box are wires, several washers of various materials, and assembly hardware (nuts and screws/bolts). The device is a passive electronic component that is plugged into a DMM. The operator sets the DMM to read voltage. The operator places the heated tip of the soldering iron onto the metal tab with a small amount of solder to ensure a complete connection. The voltage is read and recorded. The operator switches the DMM to read resistance. The operator places the heated tip of the soldering iron onto the metal tab with a small amount of solder to ensure a complete connection. The resistance is recorded. If the recorded voltage and resistance are below a number stated in ESDA ESD STM 13.1-2000, the test is considered to pass. The device includes all the necessary wiring internal to its body so the operator does not need to do any independent wiring, except for grounding. It uses a stack of high-thermal-resistance washers to minimize the

  18. An Accelerated Method for Testing Soldering Tendency of Core Pins

    SciTech Connect

    Han, Qingyou; Xu, Hanbing; Ried, Paul; Olson, Paul

    2010-01-01

    An accelerated method for testing die soldering has been developed. High intensity ultrasonic vibrations has been used to simulate the die casting conditions such as high pressure and high impingement speed of molten metal on the pin. Soldering tendency of steels and coated pins has been examined. The results indicate that in the low carbon steel/Al system, the onset of soldering is 60 times faster with ultrasonic vibration than that without ultrasonic vibration. In the H13/A380 system, the onset of soldering reaction is accelerated to 30-60 times. Coating significantly reduces the soldering tendency of the core pins.

  19. Flexible multisensor inspection system for solder-joint analysis

    NASA Astrophysics Data System (ADS)

    Lacey, Gerard; Waldron, Ronan; Dinten, Jean-Marc; Lilley, Francis

    1993-08-01

    This paper describes the design and construction of an open, automated, solder bond verification machine for the electronics manufacturing industry. The application domain is the higher end assembly technologies, with an emphasis on fine pitch surface mount components. The system serves a measurement function, quantifying the solder bonds. It interfaces with the manufacturing process to close the manufacturing loop. A geometric model of the solder in a joint, coupled with a finite element analysis of the physical properties of solder, lead to objective measurement of the solder. Principle illumination systems are laser, X-ray and noncoherent lighting. Open, Objected Oriented design and implementation practices enable a forward looking system to be developed.

  20. Submicron accuracy optimization for laser beam soldering processes

    NASA Astrophysics Data System (ADS)

    Beckert, Erik; Burkhardt, Thomas; Hornaff, Marcel; Kamm, Andreas; Scheidig, Ingo; Stiehl, Cornelia; Eberhardt, Ramona; Tünnermann, Andreas

    2010-02-01

    Laser beam soldering is a packaging technology alternative to polymeric adhesive bonding in terms of stability and functionality. Nevertheless, when packaging especially micro optical and MOEMS systems this technology has to fulfil stringent requirements for accuracy in the micron and submicron range. Investigating the assembly of several laser optical systems it has been shown that micron accuracy and submicron reproducibility can be reached when using design-of-experiment optimized solder processes that are based on applying liquid solder drops ("Solder Bumping") onto wettable metalized joining surfaces of optical components. The soldered assemblies were subject to thermal cycles and vibration/ shock test also.

  1. Study of the oxidation effects on isothermal solidification based high temperature stable Pt/In/Au and Pt/In/Ag thick film interconnections on LTCC substrate

    NASA Astrophysics Data System (ADS)

    Kumar, Duguta Suresh; Suri, Nikhil; Khanna, P. K.; Sharma, R. P.

    2016-03-01

    The objective of the presented paper is to determine the oxidized phase compositions of indium lead-free solders during solidification at 190 ° C under room environment with the help of X-ray diffraction (XRD) and Energy dispersive spectroscopy (EDX). Many lead-free solders alloys available oxidizes and have poor wetting properties. The oxidation of pure indium solder foil, Au, Pt, and Ag alloys were identified and investigated, in the process of isothermal solidification based solder joints construction at room environment and humidity. Both EDX and XRD characterization techniques were performed to trace out the amount of oxide levels and variety of oxide formations at solder interface respectively. The paper also aims to report the isothermal solidification technique to provide interconnections to pads on Low temperature co-fired ceramic (LTCC) substrate. It also elaborates advantages of isothermal solidification over the other methods of interconnection. Scanning electron microscope (SEM) used to identify the oxidized spots on the surface of Pt, Ag substrates and In solder. The identified oxides were reported.

  2. Microsoldering using a YAG laser: on lead-free solder

    NASA Astrophysics Data System (ADS)

    Nakahara, Sumio; Kamata, Tatsuya; Yoneda, Noriyuki; Hisada, Shigeyoshi; Fujita, Takeyoshi

    2000-11-01

    Solderability of conventional Sn-37Pb solder pastes and Pb- free alloys (Sn-43Bi and Sn-2Ag-5Bi-0.5Cu) were examined on micro soldering using a YAG laser. Experiments were performed in order to determine the range of soldering parameters of a laser power density and an irradiation time for obtaining an appropriate wettability based on a visual inspection by a Japanese Industrial Standard. And the laser soldering processes were monitored by measuring temperature change inside solder joint (solder and Cu pad) and on a surface of a chip component. Next joining strength of chip components for surface mounting soldered on printed circuit board (glass epoxy) was tested on application thickness of solder paste (0.2, 0.3, and 0.4 mm). In addition, joining strength characteristics at different power density and materials were examined around thermal shock test by the gas phase method. As a result, characteristics of Sn-Ag-Bi-Cu (Pb-free) solder paste are equivalent to that of Sn-Pb solder paste.

  3. Solder for oxide layer-building metals and alloys

    DOEpatents

    Kronberg, J.W.

    1992-09-15

    A low temperature solder and method for soldering an oxide layer-building metal such as aluminum, titanium, tantalum or stainless steel is disclosed. The composition comprises tin and zinc; germanium as a wetting agent; preferably small amounts of copper and antimony; and a grit, such as silicon carbide. The grit abrades any oxide layer formed on the surface of the metal as the germanium penetrates beneath and loosens the oxide layer to provide good metal-to-metal contact. The germanium comprises less than approximately 10% by weight of the solder composition so that it provides sufficient wetting action but does not result in a melting temperature above approximately 300 C. The method comprises the steps rubbing the solder against the metal surface so the grit in the solder abrades the surface while heating the surface until the solder begins to melt and the germanium penetrates the oxide layer, then brushing aside any oxide layer loosened by the solder.

  4. Solder for oxide layer-building metals and alloys

    DOEpatents

    Kronberg, James W.

    1992-01-01

    A low temperature solder and method for soldering an oxide layer-building metal such as aluminum, titanium, tantalum or stainless steel. The comosition comprises tin and zinc; germanium as a wetting agent; preferably small amounts of copper and antimony; and a grit, such as silicon carbide. The grit abrades any oxide layer formed on the surface of the metal as the germanium penetrates beneath and loosens the oxide layer to provide good metal-to-metal contact. The germanium comprises less than aproximatley 10% by weight of the solder composition so that it provides sufficient wetting action but does not result in a melting temperature above approximately 300.degree. C. The method comprises the steps rubbing the solder against the metal surface so the grit in the solder abrades the surface while heating the surface until the solder begins to melt and the germanium penetrates the oxide layer, then brushing aside any oxide layer loosened by the solder.

  5. Capillary flow of solder on chemically roughened PWB surfaces

    SciTech Connect

    Hosking, F.M.; Stevenson, J.O.; Yost, F.G.

    1996-02-01

    The Center for Solder Science and Technology at Sandia National Laboratories has developed a solderability test for evaluating fundamental solder flow over PWB (printed wiring boards) surface finishes. The work supports a cooperative research and development agreement between Sandia, the National Center for Manufacturing Sciences (NCMS), and several industrial partners. An important facet of the effort involved the ``engineering`` of copper surfaces through mechanical and chemical roughening. The roughened topography enhances solder flow, especially over very fine features. In this paper, we describe how etching with different chemical solutions can affect solder flow on a specially designed ball grid array test vehicle (BGATV). The effects of circuit geometry, solution concentration, and etching time are discussed. Surface roughness and solder flow data are presented to support the roughening premise. Noticeable improvements in solder wettability were observed on uniformly etched surfaces having relatively steep peak-to-valley slopes.

  6. Electronic interconnects and devices with topological surface states and methods for fabricating same

    DOEpatents

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2016-05-03

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  7. Electromigration performance of Pb-free solder joints in terms of solder composition and joining path

    NASA Astrophysics Data System (ADS)

    Seo, Sun-Kyoung; Kang, Sung K.; Cho, Moon Gi; Lee, Hyuck Mo

    2010-07-01

    The electromigration (EM) performance of Pb-free solder joints is investigated in terms of solder composition (Sn-0.5Cu vs. Sn-1.8Ag) and joining path to Cu vs. Ni(P) under bump metallization (UBM). In the double-sided joints of Ni(P)/solder/Cu, the micro-structure of solder joints and the interfacial intermetallic compound (IMC) layers are significantly affected by solder composition and joining path. The as-reflowed microstructure of Sn-0.5Cu joints consists of small columnar grains with thin IMC layers at both UBM interfaces, independent of the joining path, while Sn-1.8Ag joints have a few large grains of low-angle grain boundaries with thick IMC layers when joined first to Ni(P) UBM, but a few 60° twins with thin IMC layers when joined first to Cu UBM. The EM stressing under high current densities at 150°C reveals that Sn-1.8Ag joints have a superior lifetime compared to Sn-0.5Cu joints. In addition, the EM lifetime of Sn-1.8Ag joints reflowed first on Ni(P) UBM is the longest among four groups of the solder joints examined.

  8. Microstructural Evolution of Lead-Free Solder Joints in Ultrasonic-Assisted Soldering

    NASA Astrophysics Data System (ADS)

    Ji, Hongjun; Wang, Qiang; Li, Mingyu

    2016-01-01

    Solder joint reliability greatly depends on the microstructure of the solder matrix and the morphology of intermetallic compounds (IMCs) in the joints. Addition of strengthening phases such as carbon nanotubes and ceramic particles to solder joints to improve their properties has been widely studied. In this work, ultrasonic vibration (USV) of casting ingots was applied to considerably improve their microstructure and properties, and the resulting influence on fluxless soldering of Cu/Sn-3.0Ag-0.5Cu/Cu joints and their microstructural evolution was investigated. It was demonstrated that USV application during reflow of Sn-based solder had favorable effects on β-Sn grain size refinement as well as the growth and distribution of various IMC phases within the joints. The β-Sn grain size was significantly refined as the ultrasound power was increased, with a reduction of almost 90% from more than 100 μm to below 10 μm. Long and large Cu6Sn5 tubes in the solder matrix of the joints were broken into tiny ones. Needle-shaped Ag3Sn was transformed into flake-shaped. These IMCs were mainly precipitated along β-Sn phase boundaries. High-temperature storage tests indicated that the growth rate of interfacial IMCs in joints formed with USV was slower than in conventional reflow joints. The mechanisms of grain refinement and IMC fragmentation are discussed and related to the ultrasonic effects.

  9. Investigation of the Growth of Intermetallic Compounds Between Cu Pillars and Solder Caps

    NASA Astrophysics Data System (ADS)

    Lin, Jui-Ching; Qin, Yi; Woertink, Julia

    2014-11-01

    In flip chip applications, Cu pillars with solder caps are regarded as next-generation electronic interconnection technology, because of high input/output density. However, because of diffusion and reaction of Sn and Cu during the high-temperature reflow process, intermetallic compounds (IMC) are formed, and grow, at the interface between the cap and the pillar. Understanding the growth behavior of interfacial IMC is critical in the design of solder interconnections, because excessive growth of IMC can reduce the reliability of connections. In this study, the growth of IMC during thermal cycling, an accelerated method of testing the service environment of electronic devices, was studied by use of focused ion beam-scanning electron microscopy. Under alternating high and low-temperature extremes, growth of Cu6Sn5 ( η-phase) and Cu3Sn ( ɛ-phase) IMC was imaged and measured as a function of the number of cycles. The total IMC layer grew significantly thicker but became more uniform during thermal cycling. The Cu3Sn layer was initially thinner than the Cu6Sn5 layer but outgrew the Cu6Sn5 layer after 1000 cycles. It was found that, with limited Cu and Sn diffusion, consumption of Cu6Sn5 for growth of the Cu3Sn layer can result in a thinner Cu6Sn5 layer after thermal cycling.

  10. Micro-fluidic interconnect

    DOEpatents

    Okandan, Murat; Galambos, Paul C.; Benavides, Gilbert L.; Hetherington, Dale L.

    2006-02-28

    An apparatus for simultaneously aligning and interconnecting microfluidic ports is presented. Such interconnections are required to utilize microfluidic devices fabricated in Micro-Electromechanical-Systems (MEMS) technologies, that have multiple fluidic access ports (e.g. 100 micron diameter) within a small footprint, (e.g. 3 mm.times.6 mm). Fanout of the small ports of a microfluidic device to a larger diameter (e.g. 500 microns) facilitates packaging and interconnection of the microfluidic device to printed wiring boards, electronics packages, fluidic manifolds etc.

  11. Multilead, Vaporization-Cooled Soldering Heat Sink

    NASA Technical Reports Server (NTRS)

    Rice, John

    1995-01-01

    Vaporization-cooled heat sink proposed for use during soldering of multiple electrical leads of packaged electronic devices to circuit boards. Heat sink includes compliant wicks held in grooves on edges of metal fixture. Wicks saturated with water. Prevents excessive increases in temperature at entrances of leads into package.

  12. 40 CFR 141.43 - Prohibition on use of lead pipes, solder, and flux.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ..., solder, and flux. 141.43 Section 141.43 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY..., solder, and flux. (a) In general—(1) Prohibition. Any pipe, solder, or flux, which is used after June 19...) When used with respect to solders and flux refers to solders and flux containing not more than...

  13. 40 CFR 141.43 - Prohibition on use of lead pipes, solder, and flux.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ..., solder, and flux. 141.43 Section 141.43 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY..., solder, and flux. (a) In general—(1) Prohibition. Any pipe, solder, or flux, which is used after June 19...) When used with respect to solders and flux refers to solders and flux containing not more than...

  14. 40 CFR 141.43 - Prohibition on use of lead pipes, solder, and flux.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ..., solder, and flux. 141.43 Section 141.43 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY..., solder, and flux. (a) In general—(1) Prohibition. Any pipe, solder, or flux, which is used after June 19...) When used with respect to solders and flux refers to solders and flux containing not more than...

  15. 40 CFR 141.43 - Prohibition on use of lead pipes, solder, and flux.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ..., solder, and flux. 141.43 Section 141.43 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY..., solder, and flux. (a) In general—(1) Prohibition. Any pipe, solder, or flux, which is used after June 19...) When used with respect to solders and flux refers to solders and flux containing not more than...

  16. Immortality of Cu damascene interconnects

    NASA Astrophysics Data System (ADS)

    Hau-Riege, Stefan P.

    2002-04-01

    We have studied short-line effects in fully-integrated Cu damascene interconnects through electromigration experiments on lines of various lengths and embedded in different dielectric materials. We compare these results with results from analogous experiments on subtractively-etched Al-based interconnects. It is known that Al-based interconnects exhibit three different behaviors, depending on the magnitude of the product of current density, j, and line length, L: For small values of (jL), no void nucleation occurs, and the line is immortal. For intermediate values, voids nucleate, but the line does not fail because the current can flow through the higher-resistivity refractory-metal-based shunt layers. Here, the resistance of the line increases but eventually saturates, and the relative resistance increase is proportional to (jL/B), where B is the effective elastic modulus of the metallization system. For large values of (jL/B), voiding leads to an unacceptably high resistance increase, and the line is considered failed. By contrast, we observed only two regimes for Cu-based interconnects: Either the resistance of the line stays constant during the duration of the experiment, and the line is considered immortal, or the line fails due to an abrupt open-circuit failure. The absence of an intermediate regime in which the resistance saturates is due to the absence of a shunt layer that is able to support a large amount of current once voiding occurs. Since voids nucleate much more easily in Cu- than in Al-based interconnects, a small fraction of short Cu lines fails even at low current densities. It is therefore more appropriate to consider the probability of immortality in the case of Cu rather than assuming a sharp boundary between mortality and immortality. The probability of immortality decreases with increasing amount of material depleted from the cathode, which is proportional to (jL2/B) at steady state. By contrast, the immortality of Al-based interconnects is

  17. Thermal cycling life prediction of Sn-3.0Ag-0.5Cu solder joint using type-I censored data.

    PubMed

    Mi, Jinhua; Li, Yan-Feng; Yang, Yuan-Jian; Peng, Weiwen; Huang, Hong-Zhong

    2014-01-01

    Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products. PMID:25121138

  18. Thermal Cycling Life Prediction of Sn-3.0Ag-0.5Cu Solder Joint Using Type-I Censored Data

    PubMed Central

    Mi, Jinhua; Yang, Yuan-Jian; Huang, Hong-Zhong

    2014-01-01

    Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products. PMID:25121138

  19. Microwave Tissue Soldering for Immediate Wound Closure

    NASA Technical Reports Server (NTRS)

    Arndt, G. Dickey; Ngo, Phong H.; Phan, Chau T.; Byerly, Diane; Dusl, John; Sognier, Marguerite A.; Carl, James

    2011-01-01

    A novel approach for the immediate sealing of traumatic wounds is under development. A portable microwave generator and handheld antenna are used to seal wounds, binding the edges of the wound together using a biodegradable protein sealant or solder. This method could be used for repairing wounds in emergency settings by restoring the wound surface to its original strength within minutes. This technique could also be utilized for surgical purposes involving solid visceral organs (i.e., liver, spleen, and kidney) that currently do not respond well to ordinary surgical procedures. A miniaturized microwave generator and a handheld antenna are used to deliver microwave energy to the protein solder, which is applied to the wound. The antenna can be of several alternative designs optimized for placement either in contact with or in proximity to the protein solder covering the wound. In either case, optimization of the design includes the matching of impedances to maximize the energy delivered to the protein solder and wound at a chosen frequency. For certain applications, an antenna could be designed that would emit power only when it is in direct contact with the wound. The optimum frequency or frequencies for a specific application would depend on the required depth of penetration of the microwave energy. In fact, a computational simulation for each specific application could be performed, which would then match the characteristics of the antenna with the protein solder and tissue to best effect wound closure. An additional area of interest with potential benefit that remains to be validated is whether microwave energy can effectively kill bacteria in and around the wound. Thus, this may be an efficient method for simultaneously sterilizing and closing wounds.

  20. Quantifying Electromigration Processes in Sn-0.7Cu Solder with Lab-Scale X-Ray Computed Micro-Tomography

    NASA Astrophysics Data System (ADS)

    Mertens, James Charles Edwin

    For decades, microelectronics manufacturing has been concerned with failures related to electromigration phenomena in conductors experiencing high current densities. The influence of interconnect microstructure on device failures related to electromigration in BGA and flip chip solder interconnects has become a significant interest with reduced individual solder interconnect volumes. A survey indicates that x-ray computed micro-tomography (muXCT) is an emerging, novel means for characterizing the microstructures' role in governing electromigration failures. This work details the design and construction of a lab-scale muXCT system to characterize electromigration in the Sn-0.7Cu lead-free solder system by leveraging in situ imaging. In order to enhance the attenuation contrast observed in multi-phase material systems, a modeling approach has been developed to predict settings for the controllable imaging parameters which yield relatively high detection rates over the range of x-ray energies for which maximum attenuation contrast is expected in the polychromatic x-ray imaging system. In order to develop this predictive tool, a model has been constructed for the Bremsstrahlung spectrum of an x-ray tube, and calculations for the detector's efficiency over the relevant range of x-ray energies have been made, and the product of emitted and detected spectra has been used to calculate the effective x-ray imaging spectrum. An approach has also been established for filtering 'zinger' noise in x-ray radiographs, which has proven problematic at high x-ray energies used for solder imaging. The performance of this filter has been compared with a known existing method and the results indicate a significant increase in the accuracy of zinger filtered radiographs. The obtained results indicate the conception of a powerful means for the study of failure causing processes in solder systems used as interconnects in microelectronic packaging devices. These results include the

  1. Cross-border impacts of the restriction of hazardous substances: a perspective based on Japanese solders.

    PubMed

    Fuse, Masaaki; Tsunemi, Kiyotaka

    2013-08-20

    Despite the relevance of the global economy, Regulatory Impact Assessments of the restriction of hazardous substances (RoHS) in the European Union (EU) are based only on domestic impacts. This paper explores the cross-border environmental impacts of the RoHS by focusing on the shifts to lead-free solders in Japan, which exports many electronics to the EU. The regulatory impacts are quantified by integrating a material flow analysis for metals constituting a solder with a scenario analysis with and without the RoHS. The results indicate that the EU regulation, the RoHS, has triggered shifts in Japan to lead-free solders, not only for electronics subject to this regulation, but for other products as well. We also find that the RoHS leads to a slow reduction in environmental emissions of the target, lead, but results in a rapid increase in the use of tin and silver in lead-free solders. This indicates the importance of assessing potential alternative substances, the use of which may increase as a result of adhering to the RoHS. The latter constitutes a negative impact because of recent concerns regarding resource criticality. PMID:23875815

  2. Effect of Solder Joint Length on Fracture Under Bending

    NASA Astrophysics Data System (ADS)

    Akbari, Saeed; Nourani, Amir; Spelt, Jan K.

    2016-01-01

    Fracture tests were conducted on copper-solder-copper joints of various lengths using double-cantilever-beam (DCB) specimens under mode I loading conditions. The thickness and length of the solder joints were large enough to neglect any anisotropy associated with the solder microstructure. It was found that the critical strain energy release rate at crack initiation, G ci, was insensitive to the length of the solder joint; however, for joints shorter than a characteristic length which was a function of the thickness and the mechanical properties of the solder layer and the substrates, the fracture load increased with increasing solder joint length. A sandwich model was developed for the analysis of the stress and strain in solder joints, taking into account the influence of both the bending deformation and the shear deformation of the substrates on the solder joint stresses. Consistent with the experimental results, it was found that solder joints longer than the characteristic length have a maximum peel stress that remains unchanged with joint length, causing the joint strength to become independent of the joint length. A closed-form analytical solution was developed for the characteristic length of DCB specimens under mode I loading. The experimental results were in good agreement with the analytical model and with finite element results. The generality of the G ci failure criterion was demonstrated by comparing the experimental results and the fracture load predictions of mode I DCB solder joints with different lengths.

  3. Soldering of Carbon Materials Using Transition Metal Rich Alloys.

    PubMed

    Burda, Marek; Lekawa-Raus, Agnieszka; Gruszczyk, Andrzej; Koziol, Krzysztof K K

    2015-08-25

    Joining of carbon materials via soldering has not been possible up to now due to lack of wetting of carbons by metals at standard soldering temperatures. This issue has been a severely restricting factor for many potential electrical/electronic and mechanical applications of nanostructured and conventional carbon materials. Here we demonstrate the formation of alloys that enable soldering of these structures. By addition of several percent (2.5-5%) of transition metal such as chromium or nickel to a standard lead-free soldering tin based alloy we obtained a solder that can be applied using a commercial soldering iron at typical soldering temperatures of approximately 350 °C and at ambient conditions. The use of this solder enables the formation of mechanically strong and electrically conductive joints between carbon materials and, when supported by a simple two-step technique, can successfully bond carbon structures to any metal terminal. It has been shown using optical and scanning electron microscope images as well as X-ray diffraction patterns and energy dispersive X-ray mapping that the successful formation of carbon-solder bonds is possible, first, thanks to the uniform nonreactive dispersion of transition metals in the tin-based matrix. Further, during the soldering process, these free elements diffuse into the carbon-alloy border with no formation of brazing-like carbides, which would damage the surface of the carbon materials. PMID:26256042

  4. Zee electrical interconnect

    NASA Technical Reports Server (NTRS)

    Rust, Thomas M. (Inventor); Gaddy, Edward M. (Inventor); Herriage, Michael J. (Inventor); Patterson, Robert E. (Inventor); Partin, Richard D. (Inventor)

    2001-01-01

    An interconnect, having some length, that reliably connects two conductors separated by the length of the interconnect when the connection is made but in which one length if unstressed would change relative to the other in operation. The interconnect comprises a base element an intermediate element and a top element. Each element is rectangular and formed of a conducting material and has opposed ends. The elements are arranged in a generally Z-shape with the base element having one end adapted to be connected to one conductor. The top element has one end adapted to be connected to another conductor and the intermediate element has its ends disposed against the other end of the base and the top element. Brazes mechanically and electrically interconnect the intermediate element to the base and the top elements proximate the corresponding ends of the elements. When the respective ends of the base and the top elements are connected to the conductors, an electrical connection is formed therebetween, and when the conductors are relatively moved or the interconnect elements change length the elements accommodate the changes and the associated compression and tension forces in such a way that the interconnect does not mechanically fatigue.

  5. Carbon Nanotube Interconnects Realized through Functionalization and Sintered Silver Attachment.

    PubMed

    Gopee, V; Thomas, O; Hunt, C; Stolojan, V; Allam, J; Silva, S R P

    2016-03-01

    Carbon nanotubes (CNTs) in the form of interconnects have many potential applications, and their ability to perform at high temperatures gives them a unique capability. We show the development of a novel transfer process using CNTs and sintered silver that offers a unique high-temperature, high-conductivity, and potentially flexible interconnect solution. Arrays of vertically aligned multiwalled carbon nanotubes of approximately 200 μm in length were grown on silicon substrates, using low-temperature photothermal chemical vapor deposition. Oxygen plasma treatment was used to introduce defects, in the form of hydroxyl, carbonyl, and carboxyl groups, on the walls of the carbon nanotubes so that they could bond to palladium (Pd). Nanoparticle silver was then used to bind the Pd-coated multiwalled CNTs to a copper substrate. The silver-CNT-silver interconnects were found to be ohmic conductors, with resistivity of 6.2 × 10(-4) Ωm; the interconnects were heated to temperatures exceeding 300 °C (where common solders fail) and were found to maintain their electrical performance. PMID:26835786

  6. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1989-03-21

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration. 6 figs.

  7. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1987-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  8. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1989-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  9. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-08-23

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  10. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-06-24

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  11. Effect of the Soldering Process on the Microstructure and Mechanical Properties of Sn-9Zn/Al Solder Joints

    NASA Astrophysics Data System (ADS)

    Yao, Yao; Feng, Xue; Jian, Zhou; Zhanying, Feng; Xu, Chen

    2015-08-01

    Tin-zinc solder alloys are considered to be appropriate for soldering of aluminum alloys at low-temperature in electronics and radiators applications. In this paper, the effects of different soldering parameters on the microstructure and interfacial reaction behaviors of 1070Al/Sn-9Zn/1070Al joints were investigated. The results show that the Al substrate was dissolved by the liquid solder, but Al-related intermetallic was not observed in the interface. Two kinds of Al-rich phases formed in the solder matrix. Large butterfly-shaped solid solution (Al)″ phases (about 10 μm) were formed in the liquid alloys, and compact-shaped precipitations (nano-size) were dissolved out from solders during solidification process. With increasing of the soldering time, Al″ phases were migrated upwards in the solders and the amount of this phase increased. In addition, with the increase of the soldering temperature, the dissolution rate of Al into the solder increased and the formation time of (Al)″ phases was reduced. Shear test results indicate when soldered at 250 °C, the shear strength increased from 48.6 MPa to a maximum 60.5 MPa and then decreased to a stable value (about 55 MPa) with increasing of the soldering time. Similar trends were also observed at 300 and 350 °C, while the soldering time needed to obtain maximum shear strength was shortened. The formation of these Al-rich phases improves the shear strength but deteriorates the ductility.

  12. Issues in the replacement of lead-bearing solders

    NASA Astrophysics Data System (ADS)

    Vianco, Paul T.; Frear, Darrel R.

    1993-07-01

    The use of soft solders, particularly those containing lead, dates back nearly 5,000 years. Solders similar to the materials used to seal the aqueducts of ancient Rome are now an important building block in the manufacture of high-speed computer assemblies. This history attests to the technological versatility of soft solders and, in particular, the solder alloys that contain lead. However, the health effects of prolonged exposure to lead have also been documented; measures to limit human exposure—at the work place and indirectly through the environment—are being considered. The successful introduction of lead-free solders into future electronic products will rely heavily upon their solderability, which can be evaluated by test procedures such as the meniscometer/wetting balance technique and the capillary flow test.

  13. Investigation of Solder Cracking Problems on Printed Circuit Boards

    NASA Technical Reports Server (NTRS)

    Berkebile, M. J.

    1967-01-01

    A Solder Committee designated to investigate a solder cracking phenomena occurring on the SATURN electrical/electronic hardware found the cause to be induced stress in the soldered connections rather than faulty soldering techniques. The design of the printed circuit (PC) board assemblies did not allow for thermal expansion of the boards that occurred during normal operation. The difference between the thermal expansion properties of the boards and component lead materials caused stress and cracking in the soldered connections. The failure mechanism and various PC boards component mounting configurations are examined in this report. Effective rework techniques using flanged tubelets, copper tubelets, and soft copper wiring are detailed. Future design considerations to provide adequate strain relief in mounting configurations are included to ensure successful solder terminations.

  14. Microstructure and Solderability of Zn-6Al- xSn Solders

    NASA Astrophysics Data System (ADS)

    Yang, Xiaojun; Hu, Wei; Yan, Xin; Lei, Yongping

    2015-04-01

    The eutectic point of Zn-6Al alloy is 381°C, and the peritectic reaction of Zn-Al-Sn alloy occurs at 280°C. In order to find an alloy with an appropriate melting point between 280°C and 340°C, Zn-6Al-5Sn, Zn-6Al-10Sn, Zn-6Al-15Sn, and Zn-6Al-20Sn alloys were prepared. The microstructure, melting behavior, and wettability of the Zn-6Al- xSn solder alloys were investigated by scanning electron microscopy (SEM), differential scanning calorimetry (DSC), and the sessile drop method. The results show that the alloys were composed of Zn-rich phase, Zn-Al structure, Sn-Zn-Al peritectic structure, and Sn-Zn eutectic structure. The progressive decrease of the liquidus temperature of the Zn-6Al- xSn solders was confirmed by the DSC results in the order: Zn-6Al-5Sn, Zn-6Al-10Sn, Zn-6Al-15Sn, Zn-6Al-20Sn. A decrease of the wetting angle, selected for evaluation of the solderability of the Zn-6Al- xSn solders, was observed in the same order. The cross-section of a solder joint on a Cu substrate was examined by SEM coupled with energy-dispersive x-ray (EDS) analysis.

  15. Application of optical interconnect technology at Lawrence Livermore National Laboratory

    SciTech Connect

    Haigh, R.E.; Lowry, M.E.; McCammon, K.; Hills, R.; Mitchell, R.; Sweider, D.

    1995-08-10

    Optical interconnects will be required to meet the information bandwidth requirements of future communication and computing applications. At Lawrence Livermore National Laboratory, the authors are involved in applying optical interconnect technologies in two distinct application areas: Multi-Gigabit/sec Computer Backplanes and Gigabit/sec Wide Area Networking using Wavelength Division Multiplexing. In this paper, the authors discuss their efforts to integrate optical interconnect technologies into prototype computing and communication systems.

  16. Solder Creep-Fatigue Interactions with Flexible Leaded Part

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.; Wen, L. C.

    1994-01-01

    In most electronic packaging applications it is not a single high stress event that breaks a component solder joint; rather it is repeated or prolonged load applications that result in fatigue or creep failure of the solder. The principal strain in solder joints is caused by differential expansion between the part and its mounting environment due to hanges in temperature (thermal cycles) and/or due to temperature gradients between the part and the board.

  17. Capillary flow solderability test for printed wiring boards

    SciTech Connect

    Hosking, F.M.; Yost, F.G.; Hernandez, C.L.; Sackinger, S.J.

    1994-04-01

    This report describes a new technique for evaluating capillary flow solderability on printed circuit boards. The test involves the flow of molten solder from a pad onto different-sized conductor lines. It simulates the spreading dynamics of either plated-through-hole (PTH) or surface mount technology (SMT) soldering. A standard procedure has been developed for the test. Preliminary experiments were conducted and the results demonstrate test feasibility. Test procedures and results are presented in this report.

  18. SOFC INTERCONNECT DEVELOPMENT

    SciTech Connect

    Diane M. England

    2004-03-16

    An interconnect for an SOFC stack is used to connect fuel cells into a stack. SOFC stacks are expected to run for 40,000 hours and 10 thermal cycles for the stationary application and 10,000 hours and 7000 thermal cycles for the transportation application. The interconnect of a stack must be economical and robust enough to survive the SOFC stack operation temperature of 750 C and must maintain the electrical connection to the fuel cells throughout the lifetime and under thermal cycling conditions. Ferritic and austenitic stainless steels, and nickel-based superalloys were investigated as possible interconnect materials for solid oxide fuel cell (SOFC) stacks. The alloys were thermally cycled in air and in a wet nitrogen-argon-hydrogen (N2-Ar-H2-H2O) atmosphere. Thermogravimetry was used to determine the parabolic oxidation rate constants of the alloys in both atmospheres. The area-specific resistance of the oxide scale and metal substrates were measured using a two-probe technique with platinum contacts. The study identifies two new interconnect designs which can be used with both bonded and compressive stack sealing mechanisms. The new interconnect designs offer a solution to chromium vaporization, which can lead to degradation of some (chromium-sensitive) SOFC cathodes.

  19. Magellan/Galileo solder joint failure analysis and recommendations

    NASA Technical Reports Server (NTRS)

    Ross, Ronald G., Jr.

    1989-01-01

    On or about November 10, 1988 an open circuit solder joint was discovered in the Magellan Radar digital unit (DFU) during integration testing at Kennedy Space Center (KSC). A detailed analysis of the cause of the failure was conducted at the Jet Propulsion Laboratory leading to the successful repair of many pieces of affected electronic hardware on both the Magellan and Galileo spacecraft. The problem was caused by the presence of high thermal coefficient of expansion heat sink and conformal coating materials located in the large (0.055 inch) gap between Dual Inline Packages (DIPS) and the printed wiring board. The details of the observed problems are described and recommendations are made for improved design and testing activities in the future.

  20. Study of heating capacity of focused IR light soldering systems.

    PubMed

    Anguiano, C; Félix, M; Medel, A; Bravo, M; Salazar, D; Márquez, H

    2013-10-01

    An experimental study about four optical setups used for developing a Focused IR Light Soldering System (FILSS) for Surface Mount Technology (SMT) lead-free electronic devices specifically for Ball Grid Arrays (BGA) is presented. An analysis of irradiance and infrared thermography at BGA surface is presented, as well as heat transfer by radiation and conduction process from the surface of the BGA to the solder balls. The results of this work show that the heating provided by our proposed optical setups, measured at the BGA under soldering process, meets the high temperature and uniform thermal distribution requirements, which are defined by the reflow solder method for SMT devices. PMID:24104296

  1. High temperature solder alloys for underhood applications: Final report

    SciTech Connect

    Kern, J.A.; Drewien, C.A.; Yost, F.G.; Sackinger, S.; Weiser, M.W.

    1996-06-01

    In this continued study, the microstructural evolution and peel strength as a function of thermal aging were evaluated for four Sn-Ag solders deposited on double layered Ag-Pt metallization. Additionally, activation energies for intermetallic growth over the temperature range of 134 to 190{degrees}C were obtained through thickness measurements of the Ag-Sn intermetallic that formed at the solder-metallization interface. It was found that Bi-containing solders yielded higher activation energies for the intermetallic growth, leading to thicker intermetallic layers at 175 and 190{degrees}C for times of 542 and 20.5 hrs, respectively, than the solders free of Bi. Complete reaction of the solder with the metallization occurred and lower peel strengths were measured on the Bi-containing solders. In all solder systems, a Ag-Sn intermetallic thickness of greater than {approximately}7 {mu}m contributed to lower peel strength values. The Ag-Sn binary eutectic composition and the Ag-Sn-Cu ternary eutectic composition solders yielded lower activation energies for intermetallic formation, less microstructural change with time, and higher peel strengths; these solder systems were resilient to the effects of temperatures up to 175{degrees}C. Accelerated isothermal aging studies provide useful criteria for recommendation of materials systems. The Sn-Ag and Sn-Ag-Cu eutectic compositions should be considered for future service life and reliability studies based upon their performance in this study.

  2. Solderability preservation through the use of organic inhibitors

    SciTech Connect

    Sorensen, N.R.; Hosking, F.M.

    1994-12-01

    Organic inhibitors can be used to prevent corrosion of metals and have application in the electronics industry as solderability preservatives. We have developed a model to describe the action of two inhibitors (benzotriazole and imidazole) during the environmental aging and soldering process. The inhibitors bond with the metal surface and form a barrier that prevents or retards oxidation. At soldering temperatures, the metal-organic complex breaks down leaving an oxide-free metal surface that allows excellent wetting by molten solder. The presence of the inhibitor retards the wetting rate relative to clean copper, but provides a vast improvement relative to oxidized copper.

  3. Aging, stressing and solderability of electroplated and electroless copper

    SciTech Connect

    Sorensen, N.R.; Hosking, F.M.

    1995-08-01

    Organic inhibitors can be used to prevent corrosion of metals have application in the electronics industry as solderability preservatives. We have developed a model to describe the action of two inhibitors (benzotriazole and imidazole) during the environmental aging and soldering process. The inhibitors bond with the metal surface and form a barrier that prevents or retards oxidation. At soldering temperatures, the metal-organic complex breaks down leaving an oxide-free metal surface that allows excellent wetting by the molten solder. The presence of the inhibitor retards the wetting rate relative to clean copper but provides a vast improvement relative to oxidized copper.

  4. Coarsening of the Sn-Pb Solder Microstructure in Constitutive Model-Based Predictions of Solder Joint Thermal Mechanical Fatigue

    SciTech Connect

    Vianco, P.T.; Burchett, S.N.; Neilsen, M.K.; Rejent, J.A.; Frear, D.R.

    1999-04-12

    Thermal mechanical fatigue (TMF) is an important damage mechanism for solder joints exposed to cyclic temperature environments. Predicting the service reliability of solder joints exposed to such conditions requires two knowledge bases: first, the extent of fatigue damage incurred by the solder microstructure leading up to fatigue crack initiation, must be quantified in both time and space domains. Secondly, fatigue crack initiation and growth must be predicted since this metric determines, explicitly, the loss of solder joint functionality as it pertains to its mechanical fastening as well as electrical continuity roles. This paper will describe recent progress in a research effort to establish a microstructurally-based, constitutive model that predicts TMF deformation to 63Sn-37Pb solder in electronic solder joints up to the crack initiation step. The model is implemented using a finite element setting; therefore, the effects of both global and local thermal expansion mismatch conditions in the joint that would arise from temperature cycling.

  5. Novel Three-Dimensional Vertical Interconnect Technology for Microwave and RF Applications

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.

    1999-01-01

    In this paper, novel 3D interconnects suitable for applications in microwave and RF integrated circuit technology have been presented. The interconnect fabrication process and design details are presented. In addition, measured and numerically modeled results of the performance of the interconnects have been shown. The results indicate that the proposed technology has tremendous potential applications in integrated circuit technology. C,

  6. Shaping Transistor Leads for Better Solder Joints

    NASA Technical Reports Server (NTRS)

    Mandel, H.; Dillon, J. D.

    1982-01-01

    Special lead-forming tool puts step in leads of microwave power transistors without damaging braze joints that fasten leads to package. Stepped leads are soldered to circuit boards more reliably than straight leads, and stress on brazes is relieved. Lead-forming hand-tool has two parts: a forming die and an actuator. Spring-loaded saddle is adjusted so that when transistor package is placed on it, leads rest on forming rails.

  7. SOFC INTERCONNECT DEVELOPMENT

    SciTech Connect

    Diane M. England

    2003-06-06

    This report summarizes the interconnect work being performed at Delphi. Materials were chosen for this interconnect project were chosen from ferritic and austenitic stainless steels, and nickel-based superalloys. The alloys are thermally cycled in air and a wet hydrogen atmosphere. The oxide scale adherence, electrical resistance and oxidation resistance are determined after long-term oxidation of each alloy. The oxide scale adherence will be observed using a scanning electron microscope. The electrical resistance of the oxidized alloys will be determined using an electrical resistance measurement apparatus which has been designed and is currently being built. Data from the electrical resistance measurement is expected to be provided in the second quarter.

  8. Central American electrical interconnection

    SciTech Connect

    Not Available

    1988-12-01

    A technical cooperation grant of $2.25 million, designed to strengthen the capacity of Central American countries to operate their regional interconnected electrical system, was announced by the Inter-American Development Bank (IDB). The grant, extended from the banks Fund for Special Operations, will help improve the capacity of the regions electric power companies to achieve economical, safe operation of the interconnected electric power systems. The funds will also be used to finance regional studies of the accords, procedures, regulations, and supervisory mechanisms for the system, as well as program development and data bases.

  9. Effect of Metal Bond-Pad Configurations on the Solder Microstructure Development of Flip-Chip Solder Joints

    NASA Astrophysics Data System (ADS)

    Hu, Y. J.; Hsu, Y. C.; Huang, T. S.; Lu, C. T.; Wu, Albert T.; Liu, C. Y.

    2014-01-01

    Various microstructural zones were observed in the solidified solder of flip-chip solder joints with three metal bond-pad configurations (Cu/Sn/Cu, Ni/Sn/Cu, and Cu/Sn/Ni). The developed microstructures of the solidified flip-chip solder joints were strongly related to the associated metal bond pad. A hypoeutectic microstructure always developed near the Ni bond pad, and a eutectic or hypereutectic microstructure formed near the Cu pad. The effect of the metal bond pads on the solder microstructure alters the Cu solubility in the molten solder. The Cu content (solubility) in the molten Sn(Cu) solder eventually leads to the development of particular microstructures. In addition to the effect of the associated metal bond pads, the developed microstructure of the flip-chip solder joint depends on the configuration of the metal bond pads. A hypereutectic microstructure formed near the bottom Cu pad, and a eutectic microstructure formed near the top Cu pad. Directional cooling in the flip-chip solder joint during the solidification process causes the effects of the metal bond-pad configuration. Directional cooling causes the Cu content to vary in the liquid Sn(Cu) phase, resulting in the formation of distinct microstructural zones in the developed microstructure of the flip-chip solder joint.

  10. Open Systems Interconnection.

    ERIC Educational Resources Information Center

    Denenberg, Ray

    1985-01-01

    Discusses the need for standards allowing computer-to-computer communication and gives examples of technical issues. The seven-layer framework of the Open Systems Interconnection (OSI) Reference Model is explained and illustrated. Sidebars feature public data networks and Recommendation X.25, OSI standards, OSI layer functions, and a glossary.…

  11. Interconnecting with VIPs

    ERIC Educational Resources Information Center

    Collins, Robert

    2013-01-01

    Interconnectedness changes lives. It can even save lives. Recently the author got to witness and be part of something in his role as a teacher of primary science that has changed lives: it may even have saved lives. It involved primary science teaching--and the climate. Robert Collins describes how it is all interconnected. The "Toilet…

  12. Capillary interconnect device

    SciTech Connect

    Renzi, Ronald F

    2013-11-19

    An interconnecting device for connecting a plurality of first fluid-bearing conduits to a corresponding plurality of second fluid-bearing conduits thereby providing fluid communication between the first fluid-bearing conduits and the second fluid-bearing conduits. The device includes a manifold and one or two ferrule plates that are held by compressive axial forces.

  13. CAISSON: Interconnect Network Simulator

    NASA Technical Reports Server (NTRS)

    Springer, Paul L.

    2006-01-01

    Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.

  14. Solder self-assembled, surface micromachined MEMS for micromirror applications and atom trapping

    NASA Astrophysics Data System (ADS)

    McCarthy, Brian

    Solder self-assembly can be used to expand the versatility of a commercial foundry, like MEMSCAP's PolyMUMPs process. These foundries are attractive for prototyping MEMS as they can offer consistent, low cost fabrication runs by sticking to a single process and integrating multiple customers on each wafer. However, this standardization limits the utility of the process for a given application. Solder self-assembly gives back some of this versatility and expands the envelope of surface micromachining capability in the form of a simple post-process step. Here it is used to create novel micromirrors and micromirror arrays as well as to delve into the field of ultracold atom optics where the utility of MEMS as an enabling technology for atom control is explored. Two types of torsional, electrostatic micromirrors are demonstrated, both of which can achieve +/-10° of rotation. The first is a novel out-of-plane micromirror that can be rotated to a desired angle from the substrate. This integrated, on-chip assembly allows much simpler packaging technology to be used for devices that require a laser beam to be steered off-chip. Planar micromirror arrays that use solder self-assembly to tailor the electrode gap height are also demonstrated. With these designs, no special fabrication techniques are required to achieve large gap heights, and micromirrors with a variety of gap heights can even be fabricated on the same chip. Finally, solder self-assembly is used to explore how complex micro-scale structures can be used to control ultracold atoms. For this study, a MEMS version of a magneto-optical trap, the basis for most ultracold atomic systems, is used to control Rb atoms. In doing so, it provides a path for the successful integration of a number of MEMS devices in these types of systems.

  15. Effect of silver and copper on tin-silver-copper interconnects

    NASA Astrophysics Data System (ADS)

    Lu, Yuan

    Environmental concerns over the toxicity of lead-bearing solders have stimulated research activities in seeking lead-free (LF) alloys. Sn-x%Ag-y%Cu alloys have become the most promising LF candidates. Our understanding about Sn-x%Ag-y%Cu interconnects is limited compared to lead-based interconnects. For example, even the discovery of Sn-x%Ag-y%Cu comes with a group of alloys, discernible by x and y. The objective of this research was to understand the effects of Ag and Cu content on Sn-x%Ag-y%Cu interconnects, especially to understand how Ag and Cu apply their effects. The research was conducted from aspects of alloy thermal characteristic behavior, alloy phase formation, solder-substrate interactions, interconnect microstructural development and their impact on the interconnect mechanical performance and reliability. During the research, surface microetching microscopy (SMM), a brand-new three-dimensional microanalysis technique, was developed to closely examine the interfacial microstructures. The research indicated: All Sn-x%Ag-Cu alloys possess a similar melting point about 217.4°C. The latent heat increases as Ag content increases. The alloy undercooling behaves similar to a quasi-parabolic function of Ag content. A correlation between alloy undercooling and Ag3Sn plate occurrence exists. Ag 3Sn plates can grow only if the undercooling is large. Ag3Sn plates can grow with Ag content as low as 1.2 wt.%. This content is much lower than the reported threshold value (3.13 wt.%). Sn-x%Ag-y%Cu interconnects can have different interfacial microstructures, depending on Ag and Cu contents. High Ag and/or high Cu content make the interconnects brittle through interfacial microstructural development. With assistance of SMM, the mechanisms via which Ag and Cu apply their influences were revealed: There is a coupled-growth between Ag3Sn plates and Cu6Sn5 IMC. Ag applies its influence via creating Ag3Sn plates which are brittle due to their incompatible geometry to that of

  16. Graphene Nanoribbons (GNRs) for Future Interconnect

    NASA Astrophysics Data System (ADS)

    Saptono Duryat, Rahmat

    2016-05-01

    Selecting and developing materials for the future devices require a sound understanding of design requirements. Miniaturization of electronic devices, as commonly expressed by Moore Law, has involved the integration level. Increase of the level has caused some consequences in the design and selection of materials for interconnection. The present paper deals with the challenge of materials design and selection beyond the nanoscale limit and the ability of traditional materials to cope with. One of the emerging materials, i.e. Graphene, will be reviewed with particular reference to its characteristics and potentials for future interconnection.

  17. Direct-soldering 6061 aluminum alloys with ultrasonic coating.

    PubMed

    Ding, Min; Zhang, Pei-lei; Zhang, Zhen-yu; Yao, Shun

    2010-02-01

    In this study, the authors applied furnace soldering with ultrasonic coating method to solder 6061 aluminum alloy and investigated the effects of both coating time and soldering temperature on its properties. The following results were obtained: firstly, the solder region mainly composed of four kinds of microstructure zones: rich Sn zone, rich-Pb zone, Sn-Pb eutectic phase and rich Al zone. Meanwhile, the microanalysis identified a continuous reaction product at the alumina-solder interface as a rich-Pb zone. Therefore, the joint strength changed with soldering time and soldering temperature. Secondly, the tensile data had significantly greater variability, with values ranging from 13.99MPa to 24.74MPa. The highest value was obtained for the samples coated with Sn-Pb-Zn alloy for 45s. Fractures occurred along the solder-alumina interface for the 6061 aluminum alloy with its surface including hybrid tough fracture of dimple and tear ridge. The interface could initially strip at the rich Bi zone with the effect of shear stress. PMID:19900830

  18. Laser-activated protein solder for peripheral nerve repair

    NASA Astrophysics Data System (ADS)

    Trickett, Rodney I.; Lauto, Antonio; Dawes, Judith M.; Owen, Earl R.

    1995-05-01

    A 100 micrometers core optical fiber-coupled 75 mW diode laser operating at a wavelength of 800 nm has been used in conjunction with a protein solder to stripe weld severed rat tibial nerves, reducing the long operating time required for microsurgical nerve repair. Welding is produced by selective laser denaturation of the albumin based solder which contains the dye indocyanine green. Operating time for laser soldering was 10 +/- 5 min. (n equals 20) compared to 23 +/- 9 min. (n equals 10) for microsuturing. The laser solder technique resulted in patent welds with a tensile strength of 15 +/- 5 g, while microsutured nerves had a tensile strength of 40 +/- 10 g. Histopathology of the laser soldered nerves, conducted immediately after surgery, displayed solder adhesion to the outer membrane with minimal damage to the inner axons of the nerves. An in vivo study is under way comparing laser solder repaired tibial nerves to conventional microsuture repair. At the time of submission 15 laser soldered nerves and 7 sutured nerves were characterized at 3 months and showed successful regeneration with compound muscle action potentials of 27 +/- 8 mV and 29 +/- 8 mW respectively. A faster, less damaging and long lasting laser based anastomotic technique is presented.

  19. Cost comparison modeling between current solder sphere attachment technology and solder jetting technology

    SciTech Connect

    Davidson, R.N.

    1996-10-01

    By predicting the total life-cycle cost of owning and operating production equipment, it becomes possible for processors to make accurate and intelligent decisions regarding major capitol equipment investments as well as determining the most cost effective manufacturing processes and environments. Cost of Ownership (COO) is a decision making technique based on inputting the total costs of acquiring, operating and maintaining production equipment. All quantitative economic and production data can be modeled and processed using COO software programs such as the Cost of Ownership Luminator program TWO COOL{trademark}. This report investigated the Cost of Ownership differences between the current state-of-the-art solder ball attachment process and a prototype solder jetting process developed by Sandia National Laboratories. The prototype jetting process is a novel and unique approach to address the anticipated high rate ball grid array (BGA) production requirements currently forecasted for the next decade. The jetting process, which is both economically and environmentally attractive eliminates the solder sphere fabrication step, the solder flux application step as well as the furnace reflow and post cleaning operations.

  20. Nanoscale soldering of axially positioned single-walled carbon nanotubes: a molecular dynamics simulation study.

    PubMed

    Cui, Jianlei; Yang, Lijun; Zhou, Liang; Wang, Yang

    2014-02-12

    The miniaturization of electronics devices into the nanometer scale is indispensable for next-generation semi-conductor technology. Carbon nanotubes (CNTs) are considered to be the promising candidates for future interconnection wires. To study the carbon nanotubes interconnection during nanosoldering, the melting process of nanosolder and nanosoldering process between single-walled carbon nanotubes are simulated with molecular dynamics method. As the simulation results, the melting point of 2 nm silver solder is about 605 K because of high surface energy, which is below the melting temperature of Ag bulk material. In the nanosoldering process simulations, Ag atoms may be dragged into the nanotubes to form different connection configuration, which has no apparent relationship with chirality of SWNTs. The length of core filling nanowires structure has the relationship with the diameter, and it does not become longer with the increasing diameter of SWNT. Subsequently, the dominant mechanism of was analyzed. In addition, as the heating temperature and time, respectively, increases, more Ag atoms can enter the SWNTs with longer length of Ag nanowires. And because of the strong metal bonds, less Ag atoms can remain with the tight atomic structures in the gap between SWNT and SWNT. The preferred interconnection configurations can be achieved between SWNT and SWNT in this paper. PMID:24392855

  1. Fluxless eutectic bonding of GaAs-on-Si by using Ag/Sn solder

    NASA Astrophysics Data System (ADS)

    Eo, Sung-Hwa; Kim, Dae-Seon; Jeong, Ho-Jung; Jang, Jae-Hyung

    2013-11-01

    Fluxless GaAs-on-Si wafer bonding using Ag/Sn solder was investigated to realize uniform and void-free heterogeneous material integration. The effects of the diffusion barrier, Ag/Sn thickness, and Ar plasma treatment were studied to achieve the optimal fluxless bonding process. Pt on a GaAs wafer and Mo on a Si wafer act as diffusion barriers by preventing the flow of Ag/Sn solder into both the wafers. The bonding strength is closely related to the Ag/Sn thickness and Ar plasma treatment. A shear strength test was carried out to investigate the bonding strength. Under identical bonding conditions, the Ag/Sn thickness was optimized to achieve higher bonding strength and to avoid the formation of voids due to thermal stress. An Ar plasma pretreatment process improved the bonding strength because the Ar plasma removed carbon contaminants and metal-oxide bonds from the metal surface.

  2. Optical transceivers for interconnections in satellite payloads

    NASA Astrophysics Data System (ADS)

    Karppinen, Mikko; Heikkinen, Veli; Juntunen, Eveliina; Kautio, Kari; Ollila, Jyrki; Sitomaniemi, Aila; Tanskanen, Antti

    2013-02-01

    The increasing data rates and processing on board satellites call for the use of photonic interconnects providing high-bitrate performance as well as valuable savings in mass and volume. Therefore, optical transmitter and receiver technology is developed for aerospace applications. The metal-ceramic-packaging with hermetic fiber pigtails enables robustness for the harsh spacecraft environment, while the 850-nm VCSEL-based transceiver technology meets the high bit-rate and low power requirements. The developed components include 6 Gbps SpaceFibre duplex transceivers for intra-satellite data links and 40 Gbps parallel optical transceivers for board-to-board interconnects. Also, integration concept of interchip optical interconnects for onboard processor ICs is presented.

  3. Nanotrench for nano and microparticle electrical interconnects

    NASA Astrophysics Data System (ADS)

    Dayen, J.-F.; Faramarzi, V.; Pauly, M.; Kemp, N. T.; Barbero, M.; Pichon, B. P.; Majjad, H.; Begin-Colin, S.; Doudin, B.

    2010-08-01

    We present a simple and versatile patterning procedure for the reliable and reproducible fabrication of high aspect ratio (104) electrical interconnects that have separation distances down to 20 nm and lengths of several hundreds of microns. The process uses standard optical lithography techniques and allows parallel processing of many junctions, making it easily scalable and industrially relevant. We demonstrate the suitability of these nanotrenches as electrical interconnects for addressing micro and nanoparticles by realizing several circuits with integrated species. Furthermore, low impedance metal-metal low contacts are shown to be obtained when trapping a single metal-coated microsphere in the gap, emphasizing the intrinsic good electrical conductivity of the interconnects, even though a wet process is used. Highly resistive magnetite-based nanoparticles networks also demonstrate the advantage of the high aspect ratio of the nanotrenches for providing access to electrical properties of highly resistive materials, with leakage current levels below 1 pA.

  4. Strength of Soldered Joints Formed under Microgravity Conditions

    NASA Astrophysics Data System (ADS)

    Thomas, B.; Atkinson, A.; Dashwood, R. J.

    2007-01-01

    Experiments have been carried out to compare the mechanical strength of joints soldered with Sn-Ag-Cu under different gravitational conditions. Joints soldered under microgravity (produced during a parabolic flight) have lower strength (by 32% in this case) than similar joints formed under normal gravity. Electron microscopy has shown that this is due to a larger volume of residual porosity (14%) in the joints formed in microgravity compared with <1% for joints formed in normal gravity. The residual porosity in joints formed in microgravity is mainly within the bulk of the solder, with some microporosity in the Cu6Sn5 intermetallic layer near the copper interfaces. The porosity not only weakens the joint, but also biases the failure path away from the intermetallic layer and into the bulk of the solder. These observations show that gravitational buoyancy is important for the expulsion of flux and flux residues from soldered joints.

  5. Development of lead-free solders for hybrid microcircuits

    SciTech Connect

    Hosking, F.M.; Vianco, P.T.; Frear, D.R.; Robinson, D.G.

    1996-01-01

    Extensive work has been conducted by industry to develop lead-free solders for electronics applications. The driving force behind this effort is pressure to ban or tax the use of lead-bearing solders. There has been further interest to reduce the use of hazardous chemical cleaners. Lead-free soldering and low-residue, ``no clean`` assembly processing are being considered as solutions to these environmental issues. Most of the work has been directed toward commercial and military printed wiring board (PWB) technology, although similar problems confront the hybrid microcircuit (HMC) industry, where the development of lead-free HMC solders is generally lagging. Sandia National Laboratories is responsible for designing a variety of critical, high reliability hybrid components for radars. Sandia has consequently initiated a project, as part of its Environmentally Conscious Manufacturing program, to develop low-residue, lead-free soldering for HMCs. This paper discusses the progress of that work.

  6. Dry soldering with hot filament produced atomic hydrogen

    DOEpatents

    Panitz, Janda K. G.; Jellison, James L.; Staley, David J.

    1995-01-01

    A system for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs.

  7. Dry soldering with hot filament produced atomic hydrogen

    DOEpatents

    Panitz, J.K.G.; Jellison, J.L.; Staley, D.J.

    1995-04-25

    A system is disclosed for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs. 1 fig.

  8. A Study of Solder Alloy Ductility for Cryogenic Applications

    NASA Technical Reports Server (NTRS)

    Lupinacci, A.; Shapiro, A. A.; Suh, J-O.; Minor, A. M.

    2013-01-01

    For aerospace applications it is important to understand the mechanical performance of components at the extreme temperature conditions seen in service. For solder alloys used in microelectronics, cryogenic temperatures can prove problematic. At low temperatures Sn-based solders undergo a ductile to brittle transition that leads to brittle cracks, which can result in catastrophic failure of electronic components, assemblies and spacecraft payloads. As industrial processes begin to move away from Pb-Sn solder, it is even more critical to characterize the behavior of alternative Sn-based solders. Here we report on initial investigations using a modified Charpy test apparatus to characterize the ductile to brittle transformation temperature of nine different solder systems.

  9. The influence of microstructure on the mechanical properties of solder

    SciTech Connect

    Morris, J.W. Jr.; Reynolds, H.L.

    1996-06-01

    Solder joints in microelectronics devices consist of low-melting solder compositions that wet and join metal contacts and are, ordinarily, used at high homologous temperatures in the as-solidified condition. Differences in solidification rate and substrate interactions have the consequence that even solder joints of similar compositions exhibit a wide range of microstructures. The variation in microstructure causes a variation in properties; in particular, the high-temperature creep properties that govern much of the mechanical behavior of the solder may differ significantly from joint to joint. The present paper reviews the varieties of microstructure that are found in common solder joints, and describes some of the ways in which microstructural changes affect mechanical properties and joint reliability.

  10. Digital image correlation analysis of the deformation behavior of Pb-free solders at intermediate strain rates

    NASA Astrophysics Data System (ADS)

    Yazzie, K. E.; Williams, J. J.; Kingsbury, D.; Peralta, P.; Jiang, H.; Chawla, N.

    2010-07-01

    Digital image correlation (DIC) is a powerful tool for quantifying local stresses and strains. The demand for environmentally benign Pb-free solders and the push toward smaller portable electronics will make it more likely for solder interconnects to en-counter mechanical shock through dropping or mishandling. Thus, quantifying the strain rate behavior of Pb-free solders from the quasi-static to the shock regime is essential for developing reliable numerical models of the mechanical shock behavior. In this paper we report on the use of DIC to measure the local strain and strain rate occurring in the neck of Sn-3.5Ag-0.7Cu specimens, at the onset of necking. Tensile tests were conducted in the range 10-3s-1-30 s-1. A parametric study was conducted to identify the optimum DIC parameters for the experimental setup. The effect of microstructure and applied strain rate on the local values of strain and strain rate is discussed

  11. Electromigration enhanced kinetics of copper-tin intermetallic compounds in lead-free solder joints and copper low-k dual damascene processing using step and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Chao, Huang-Lin

    This dissertation constitutes two major sections. In the first major section, a kinetic analysis was established to investigate the electromigration (EM), enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints to Cu under bump metallization (UBM). The model takes into account the interfacial intermetallic reaction, Cu-Sn interdiffusion, and current stressing. A new approach was developed to derive atomic diffusivities and effective charge numbers based on Simulated Annealing (SA) in conjunction with the kinetic model. The finite difference (FD) kinetic model based on this approach accurately predicted the intermetallic compound growth when compared to empirical observation. The ultimate electromigration failure of the solder joints was caused by extensive void formation at the intermetallic interface. The void formation mechanism was analyzed by modeling the vacancy transport under electromigration. The effects of current density and Cu diffusivity in Sn solder were also investigated with the kinetic model. The second major section describes the integration of Step and Flash Imprint Lithography (S-FILRTM) into an industry standard Cu/low-k dual damascene process. The yield on a Back End Of the Line (BEOL) test vehicle that contains standard test structures such as via chains with 120 nm vias was established by electrical tests. S-FIL shows promise as a cost effective solution to patterning sub 45 nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a low cost BEOL process. The critical processing step in the integration is the reactive ion etching (RIE) process that transfers the multilevel patterns to the inter-level dielectrics (ILD). An in-situ, multistep etch process was developed that gives excellent pattern structures in two industry standard Chemical Vapor Deposited (CVD) low-k dielectrics. The etch process showed excellent pattern fidelity and a wide process

  12. Microstructural Evolution and Mechanical Properties of Au-20wt.%Sn|Ni Interconnection

    NASA Astrophysics Data System (ADS)

    Dong, H. Q.; Vuorinen, V.; Liu, X. W.; Laurila, T.; Li, J.; Paulasto-Kröckel, M.

    2016-01-01

    In this paper, the microstructural evolution and properties of Au-20wt.%Sn|Ni reaction couples were investigated from two perspectives: (1) by analyzing the microstructure of the as-soldered and aged samples, as well as (2) by measuring the mechanical properties of the intermetallic compounds formed within the reaction zone. The evolution of interfacial reaction products for both the as-soldered and aged interconnections was rationalized by using the experimental results in combination with assessed thermodynamic data from the Au-Ni-Sn system. Moreover, nanoindentation tests were implemented to measure the indentation modulus and hardness of the compounds formed at the interface. It was found that aging had a negligible influence on the elastic modulus and hardness of AuSn and Au5Sn, while the solubility of the third element significantly changed the indentation modulus and hardness of the intermetallic compounds.

  13. A study of thermal cycling and radiation effects on indium and solder bump bonds

    SciTech Connect

    Simon Kwan et al.

    2001-12-11

    The BTeV hybrid pixel detector is constructed of readout chips and sensor arrays which are developed separately. The detector is assembled by flip-chip mating of the two parts. This method requires the availability of highly reliable, reasonably low cost fine-pitch flip-chip attachment technology. We have tested the quality of two bump-bonding technologies; indium bumps (by Advanced Interconnect Technology Ltd. (AIT) of Hong Kong) and fluxless solder bumps (by MCNC in North Carolina, USA). The results have been presented elsewhere [1]. In this paper we describe tests we performed to further evaluate these technologies. We subjected 15 indium bump-bonded and 15 fluxless solder bump-bonded dummy detectors through a thermal cycle and then a dose of radiation to observe the effects of cooling, heating and radiation on bump-bonds. We also exercised the processes of HDI mounting and wire bonding to some of the dummy detectors to see the effect of these processes on bump bonds.

  14. Laser beam soldering of fine-pitch technology packages with solid solder deposits

    NASA Astrophysics Data System (ADS)

    Pucher, Hans-Joerg; Glasmacher, Mathias; Geiger, Manfred

    1996-04-01

    Micro electronics is a key technology attracting the attention of information, communication, automation and data processing technologies. Ongoing miniaturization combined with an increasing number of I/Os has inevitably lead to ever finer lead geometries. Therefore the demands put upon the surface mount technology are increasing continuously. Processing of high lead count fine pitch packages, for example those which are applied in high-capacity computers, has not increased the demands put upon the assembly process only, but also on the connecting techniques. By reflow soldering with laser beam radiation the benefits from the tool `laser beam' are used extensively, for example contact and force free processing, strictly localized heating and the good controllability thereof, formation of fine crystalline and homogeneous structures, etc. Within the scope of this paper the fundamentals of laser beam soldering are discussed for fine pitch lead frames (pitch 300 micrometers ) for plastic packages, made by a modified CuFe2P alloy with a 5 micrometers Sn90Pb plating, on solid solder depths (Sn63Pb) performed by the so called High-Pad process. These investigations are unique in the field of laser beam soldering and are carried out by means of a Nd:YAG-laser. A pyrometer is used for detection of the emission of the temperature radiation of the joining area for process control. The additional use of a high-speed camera gives a detailed description of the melting and wetting process. The influence of laser beam parameters and the volume of the solid solder deposits on the joining result are presented.

  15. Copper metallization for on-chip interconnects

    NASA Astrophysics Data System (ADS)

    Gelatos, A. V.; Nguyen, Bich-Yen; Perry, Kathleen A.; Marsh, R.; Peschke, J.; Filipiak, Stanley M.; Travis, Edward O.; Thompson, Matthew A.; Saaranen, T.; Tobin, Phil J.; Mogab, C. J.

    1996-09-01

    Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length will be at 0.l8piri [1], while microprocessors will pack more than 15 million transistors over an area of '-700mm2. To conserve area, interconnects will continue to be stacked at an increasing number of levels (6 by the year 2000, vs 4 in todays leading microprocessors) and the minimum spacing and width within an interconnect layer will shrink to 0.3.tm. In addition, it is expected that future interconnects will need to sustain increasingly higher current densities without electromigration failures [2]. Aluminum alloys are the conductors of choice in present-day interconnects, and much effort is focused n means to extend the usefulness of aluminum through improvements in reliability, either by new alloy formulations [3], or by the development of complicated multimetal stacks [4. A more radical approach, which is gaining increased attention, is the replacement of aluminum altogether by copper. The bulk resistivity of copper is significantly lower than that of aluminum (1.7.tW-cm for Cu vs. 3.0iW-cm for Al-Cu), which is expected to translate to interconnects of higher performance because of reduction in signal propagation delay. In addition, the significantly higher melting temperature of copper (.-1100°C vs. -600°C for Al-Cu alloys) and its higher atomic weight are expected to translate to improved resistance to electromigration [5]. However, as with any new process trying to break into the mainstream, significant improvement in reliability and performance over that achievable with aluminum alloys must be demonstrated first. Towards this purpose, processes need to be developed that deposit conformal copper films of high purity with acceptable throughput, and integration schemes need to be developed which produce

  16. Optical Interconnection Networks

    NASA Astrophysics Data System (ADS)

    Bergman, Keren; Hughes, Gary

    2004-07-01

    In current high-performance computing and communications systems an emerging need for ultra-high-capacity, low-latency interconnection networks has led investigators to consider insertion of optical-domain switching fabrics. The use of optical technology for the physical switching layer within data communication systems is clearly advantageous in providing maximum bandwidth per cable particularly through the exploitation of DWDM. Furthermore, the transparency offered in the optical domain allows potentially wide flexibility in the data encoding and protocols. However, many key challenges remain to the successful implementation of optical packet routing, as optical signals cannot be processed efficiently or buffered for an arbitrary time. Clearly, innovative architectures, switching fabrics, and packet processing subsystems that employ optical technologies in synergetic fashions with powerful electronic techniques would be poised to harvest the immense transmission bandwidth of optics creating the ultimate "unlimited-capacity" interconnection network.

  17. Optical Interconnection Networks

    NASA Astrophysics Data System (ADS)

    Bergman, Keren; Hughes, Gary

    2004-05-01

    In current high-performance computing and communications systems an emerging need for ultra-high-capacity, low-latency interconnection networks has led investigators to consider insertion of optical-domain switching fabrics. The use of optical technology for the physical switching layer within data communication systems is clearly advantageous in providing maximum bandwidth per cable particularly through the exploitation of DWDM. Furthermore, the transparency offered in the optical domain allows potentially wide flexibility in the data encoding and protocols. However, many key challenges remain to the successful implementation of optical packet routing, as optical signals cannot be processed efficiently or buffered for an arbitrary time. Clearly, innovative architectures, switching fabrics, and packet processing subsystems that employ optical technologies in synergetic fashions with powerful electronic techniques would be poised to harvest the immense transmission bandwidth of optics creating the ultimate "unlimited-capacity" interconnection network.

  18. Optical Interconnection Networks

    NASA Astrophysics Data System (ADS)

    Bergman, Keren; Hughes, Gary

    2004-06-01

    In current high-performance computing and communications systems an emerging need for ultra-high-capacity, low-latency interconnection networks has led investigators to consider insertion of optical-domain switching fabrics. The use of optical technology for the physical switching layer within data communication systems is clearly advantageous in providing maximum bandwidth per cable particularly through the exploitation of DWDM. Furthermore, the transparency offered in the optical domain allows potentially wide flexibility in the data encoding and protocols. However, many key challenges remain to the successful implementation of optical packet routing, as optical signals cannot be processed efficiently or buffered for an arbitrary time. Clearly, innovative architectures, switching fabrics, and packet processing subsystems that employ optical technologies in synergetic fashions with powerful electronic techniques would be poised to harvest the immense transmission bandwidth of optics creating the ultimate "unlimited-capacity" interconnection network.

  19. Soldering-based easy packaging of thin polyimide multichannel electrodes for neuro-signal recording

    NASA Astrophysics Data System (ADS)

    Baek, Dong-Hyun; Han, Chang-Hee; Jung, Ha-Chul; Kim, Seon Min; Im, Chang-Hwan; Oh, Hyun-Jik; Jungho Pak, James; Lee, Sang-Hoon

    2012-11-01

    We propose a novel packaging method for preparing thin polyimide (PI) multichannel microelectrodes. The electrodes were connected simply by making a via-hole at the interconnection pad of a thin PI electrode, and a nickel (Ni) ring was constructed by electroplating through the via-hole to permit stable soldering with strong adhesion to the electrode and the printed circuit board. The electroplating conditions were optimized for the construction of a well-organized Ni ring. The electrical properties of the packaged electrode were evaluated by fabricating and packaging a 40-channel thin PI electrode. Animal experiments were performed using the packaged electrode for high-resolution recording of somatosensory evoked potential from the skull of a rat. The in vivo and in vitro tests demonstrated that the packaged PI electrode may be used broadly for the continuous measurement of bio-signals or for neural prosthetics.

  20. Printability Optimization For Fine Pitch Solder Bonding

    SciTech Connect

    Kwon, Sang-Hyun; Lee, Chang-Woo; Yoo, Sehoon

    2011-01-17

    Effect of metal mask and pad design on solder printability was evaluated by DOE in this study. The process parameters were stencil thickness, squeegee angle, squeegee speed, mask separating speed, and pad angle of PCB. The main process parameters for printability were stencil thickness and squeegee angle. The response surface showed that maximum printability of 1005 chip was achieved at the stencil thickness of 0.12 mm while the maximum printability of 0603 and 0402 chip was obtained at the stencil thickness of 0.05 mm. The bonding strength of the MLCC chips was also directly related with the printability.

  1. Controlled fracture of Cu/ultralow-k interconnects

    NASA Astrophysics Data System (ADS)

    Li, Han; Kobrinsky, Mauro J.; Shariq, Ahmed; Richards, John; Liu, Jimmy; Kuhn, Markus

    2013-12-01

    Mechanical failures of on-chip interconnects in the forms of delamination and cracking are among the most critical challenges for integrating ultralow-dielectric-constant (ultralow-"k") materials in advanced integrated circuits. Designing a mechanically robust interconnect stack against fabrication and packaging stresses requires quantitative characterization of the fracture properties of the integrated structure and its component materials. In this Letter, we demonstrate a simple method to control crack propagation in Cu/ultralow-k interconnect and thereby extract the fracture properties of the metal vias and interlayer dielectrics from integrated structures. Important implications of the method are discussed for interconnect technology development and for fundamental study of fracture behaviors of materials having nano-scale structures.

  2. Simulation of thermomechanical fatigue in solder joints

    SciTech Connect

    Fang, H.E.; Porter, V.L.; Fye, R.M.; Holm, E.A.

    1997-12-31

    Thermomechanical fatigue (TMF) is a very complex phenomenon in electronic component systems and has been identified as one prominent degradation mechanism for surface mount solder joints in the stockpile. In order to precisely predict the TMF-related effects on the reliability of electronic components in weapons, a multi-level simulation methodology is being developed at Sandia National Laboratories. This methodology links simulation codes of continuum mechanics (JAS3D), microstructural mechanics (GLAD), and microstructural evolution (PARGRAIN) to treat the disparate length scales that exist between the macroscopic response of the component and the microstructural changes occurring in its constituent materials. JAS3D is used to predict strain/temperature distributions in the component due to environmental variable fluctuations. GLAD identifies damage initiation and accumulation in detail based on the spatial information provided by JAS3D. PARGRAIN simulates the changes of material microstructure, such as the heterogeneous coarsening in Sn-Pb solder, when the component`s service environment varies.

  3. Passive alignment and soldering technique for optical components

    NASA Astrophysics Data System (ADS)

    Faidel, Heinrich; Gronloh, Bastian; Winzen, Matthias; Liermann, Erik; Esser, Dominik; Morasch, Valentin; Luttmann, Jörg; Leers, Michael; Hoffmann, Dieter

    2012-03-01

    The passive-alignment-packaging technique presented in this work provides a method for mounting tolerance-insensitive optical components e.g. non-linear crystals by means of mechanical stops. The requested tolerances for the angle deviation are +/-100 μrad and for the position tolerance +/-100 μm. Only the angle tolerances were investigated, because they are more critical. The measurements were carried out with an autocollimator. Fused silica components were used for test series. A solder investigation was carried out. Different types of solder were tested. Due to good solderability on air and low induced stress in optical components, Sn based solders were indicated as the most suitable solders. In addition several concepts of reflow soldering configuration were realized. In the first iteration a system with only the alignment of the yaw angle was implemented. The deviation for all materials after the thermal and mechanical cycling was within the tolerances. The solderability of BBO and LBO crystals was investigated and concepts for mounting were developed.

  4. Environmentally compatible solder materials for thick film hybrid assemblies

    SciTech Connect

    Hosking, F.M.; Vianco, P.T.; Rejent, J.A.; Hernandez, C.L.

    1997-02-01

    New soldering materials and processes have been developed over the last several years to address a variety of environmental issues. One of the primary efforts by the electronics industry has involved the development of alternative solders to replace the traditional lead-containing alloys. Sandia National Laboratories is developing such alternative solder materials for printed circuit board and hybrid microcircuit (HMC) applications. This paper describes the work associated with low residue, lead-free soldering of thick film HMC`s. The response of the different materials to wetting, aging, and mechanical test conditions was investigated. Hybrid test vehicles were designed and fabricated with a variety of chip capacitors and leadless ceramic chip carriers to conduct thermal, electrical continuity, and mechanical evaluations of prototype joints. Microstructural development along the solder and thick film interface, after isothermal solid state aging over a range of elevated temperatures and times, was quantified using microanalytical techniques. Flux residues on soldered samples were stressed (temperature-humidity aged) to identify potential corrosion problems. Mechanical tests also supported the development of a solder joint lifetime prediction model. Progress of this effort is summarized.

  5. Fatigue and thermal fatigue of Pb-Sn solder joints

    SciTech Connect

    Frear, D.; Grivas, D.; McCormack, M.; Tribula, D.; Morris, J.W. Jr.

    1987-01-01

    This paper presents a fundamental investigation of the fatigue and thermal fatigue characteristics, with an emphasis on the microstructural development during fatigue, of Sn-Pb solder joints. Fatigue tests were performed in simple shear on both 60Sn-40Pb and 5Sn-95Pb solder joints. Isothermal fatigue tests show increasing fatigue life of 60Sn-40Pb solder joints with decreasing strain and temperature. In contrast, such behavior was not observed in the isothermal fatigue of 5Sn-95Pb solder joints. Thermal fatigue results on 60Sn-40Pb solder cycled between -55/sup 0/C and 125/sup 0/C show that a coarsened region develops in the center of the joint. Both Pb-rich and Sn-rich phases coarsen, and cracks form within these coarsened regions. The failure mode 60Sn-40Pb solder joints in thermal and isothermal fatigue is similar: cracks form intergranularly through the Sn-rich phase or along Sn/Pb interphase boundaries. Extensive cracking is found throughout the 5Sn-95Pb joint for both thermal and isothermal fatigue. In thermal fatigue the 5Sn-95Pb solder joints failed after fewer cycles than 60Sn-40Pb.

  6. Energy and water in the Western and Texas interconnects.

    SciTech Connect

    Tidwell, Vincent Carroll

    2010-08-01

    The Department of Energy's Office of Electricity has initiated a $60M program to assist the electric industry in interconnection-level analysis and planning. The objective of this effort is to facilitate the development or strengthening of capabilities in each of the three interconnections serving the lower 48 states of the United States, to prepare analyses of transmission requirements under a broad range of alternative futures and develop long-term interconnection-wide transmission expansion plans. The interconnections are the Western Interconnection, the Eastern Interconnection, and the Texas Interconnection. One element of this program address the support and development of an integrated energy-water Decision Support System (DSS) that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water stress for transmission and resource planning (the Eastern Interconnection is not participating in this element). Specific objectives include: (1) Develop an integrated Energy-Water Decision Support System (DSS) that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water stress for transmission and resource planning. (2) Pursue the formulation and development of the Energy-Water DSS through a strongly collaborative process between members of this proposal team and the Western Electricity Coordinating Council (WECC), Western Governors Association (WGA), the Electric Reliability Council of Texas (ERCOT) and their associated stakeholder teams. (3) Exercise the Energy-Water DSS to investigate water stress implications of the transmission planning scenarios put forward by WECC, WGA, and ERCOT. The goals of this project are: (1) Develop an integrated Energy-Water Decision Support System (DSS) that will enable planners to analyze the potential implications of water stress for transmission and resource planning. (2) Pursue the formulation and development of the Energy

  7. Teaching minority middle-school students to solder

    NASA Astrophysics Data System (ADS)

    Reardon, James; Gates, Billy J., Jr.

    2014-03-01

    We aspired to teach minority middle school students to solder. We found that important variables affecting our ability to do so included: student-to-teacher ratio, venue of instruction, relationships with community partners, and understanding of the structure of the student's worldview. Once the effects of these variables had been understood, we found the students readily learned to solder. We now want to see whether the acquisition of the skill of soldering leads the students to be more interested in technical careers and in going to college. Supported by an APS Outreach Mini-grant.

  8. Solder extrusion pressure bonding process and bonded products produced thereby

    DOEpatents

    Beavis, L.C.; Karnowsky, M.M.; Yost, F.G.

    1992-06-16

    Disclosed is a process for production of soldered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about [minus]40 C and 110 C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  9. Solder extrusion pressure bonding process and bonded products produced thereby

    DOEpatents

    Beavis, Leonard C.; Karnowsky, Maurice M.; Yost, Frederick G.

    1992-01-01

    Production of soldered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about -40.degree. C. and 110.degree. C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  10. Solder technology in the manufacturing of electronic products

    SciTech Connect

    Vianco, P.T.

    1993-08-01

    The electronics industry has relied heavily upon the use of soldering for both package construction and circuit assembly. The solder attachment of devices onto printed circuit boards and ceramic microcircuits has supported the high volume manufacturing processes responsible for low cost, high quality consumer products and military hardware. Defects incurred during the manufacturing process are minimized by the proper selection of solder alloys, substrate materials and process parameters. Prototyping efforts are then used to evaluate the manufacturability of the chosen material systems. Once manufacturing feasibility has been established, service reliability of the final product is evaluated through accelerated testing procedures.

  11. Carbon Nanotube Interconnect

    NASA Technical Reports Server (NTRS)

    Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2006-01-01

    Method and system for fabricating an electrical interconnect capable of supporting very high current densities ( 10(exp 6)-10(exp 10) Amps/sq cm), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw, or SiuNv is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

  12. Clad metals, roll bonding and their applications for SOFC interconnects

    NASA Astrophysics Data System (ADS)

    Chen, Lichun; Yang, Zhenguo; Jha, Bijendra; Xia, Guanguang; Stevenson, Jeffry W.

    Metallic interconnects have been becoming an increasingly interesting topic in the development in intermediate temperature solid oxide fuel cells (SOFC). High temperature oxidation resistant alloys are currently considered as candidate materials. Among these alloys however, different groups of alloys demonstrate different advantages and disadvantages, and few if any can completely satisfy the stringent requirements for the application. To integrate the advantages and avoid the disadvantages of different groups of alloys, clad metal has been proposed for SOFC interconnect applications and interconnect structures. This paper gives a brief overview of the cladding approach and its applications, and discuss the viability of this technology to fabricate the metallic layered-structure interconnects. To examine the feasibility of this approach, the austenitic Ni-base alloy Haynes 230 and the ferritic stainless steel AL 453 were selected as examples and manufactured into a clad metal. Its suitability as an interconnect construction material was investigated.

  13. Clad Metals, Roll Bonding and their Applications for SOFC Interconnects

    SciTech Connect

    Chen, L.; Yang, Zhenguo; Jha, B.; Xia, Guanguang; Stevenson, Jeffry W.

    2005-12-01

    High temperature oxidation resistant alloys are currently considered as candidate materials for construction of interconnects in intermediate temperature SOFCs. Among these alloys however, different groups of alloys demonstrate different advantages and disadvantages for the interconnect applications, and few if any can completely satisfied the stringent requirements for the applications. To integrate the advantages and avoid the disadvantages of different groups of alloys, cladding has been proposed as the approach to fabricate metallic layered interconnect structures. To examine the feasibility of this approach, the austenitic Ni-base alloy Haynes 230 and the ferritic stainless steel AL453 were selected as examples and manufactured into a clad metal. It’s suitability as interconnect construction materials were investigated. This paper will give a brief overview of the cladding approach and discuss the viability of this technology to fabricate the metallic layered-structure interconnects.

  14. Clad metals by roll bonding for SOFC interconnects

    SciTech Connect

    Chen, L.; Jha, B; Yang, Z Gary; Xia, Gordon; Stevenson, Jeffry W.; Singh, Prabhakar

    2006-08-01

    Metallic interconnects have been becoming an increasingly interesting topic in the development in intermediate temperature solid oxide fuel cells (SOFC). High temperature oxidation resistant alloys are currently considered as candidate materials. Among these alloys however, different groups of alloys demonstrate different advantages and disadvantages, and few if any can completely satisfy the stringent requirements for the application. To integrate the advantages and avoid the disadvantages of different groups of alloys, clad metal has been proposed for SOFC interconnect applications and interconnect structures. This paper gives a brief overview of the cladding approach and its applications, and discuss the viability of this technology to fabricate the metallic layered-structure interconnects. To examine the feasibility of this approach, the austenitic Ni-base alloy Haynes 230 and the ferritic stainless steel AL 453 were selected as examples and manufactured into a clad metal. Its suitability as an interconnect construction material was investigated.

  15. Policy issues in interconnecting networks

    NASA Technical Reports Server (NTRS)

    Leiner, Barry M.

    1989-01-01

    To support the activities of the Federal Research Coordinating Committee (FRICC) in creating an interconnected set of networks to serve the research community, two workshops were held to address the technical support of policy issues that arise when interconnecting such networks. The workshops addressed the required and feasible technologies and architectures that could be used to satisfy the desired policies for interconnection. The results of the workshop are documented.

  16. Fuel cell system with interconnect

    SciTech Connect

    Liu, Zhien; Goettler, Richard

    2015-09-29

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  17. Fuel cell system with interconnect

    SciTech Connect

    Goettler, Richard; Liu, Zhien

    2015-08-11

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  18. Fuel cell system with interconnect

    SciTech Connect

    Goettler, Richard; Liu, Zhien

    2015-03-10

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  19. Precision dispensing of small volumes of albumin solder for laser-assisted wound closure

    NASA Astrophysics Data System (ADS)

    Sorg, Brian S.; McNally-Heintzelman, Karen M.; Chan, Eric K.; Frederickson, Christopher J.; Welch, Ashley J.

    1999-06-01

    Recent laser-tissue soldering work in our lab has demonstrated the feasibility of building a solder bond from individually coagulated small droplets using a precision pipette for the deposition of the solder droplets. This method of using small, precise volumes of solder to build a bond may result in stronger and more reproducible bonds than coagulating an equivalent large volume of solder all at once. We have investigated the technique further in this study. The solder was dispensed onto the intimal side of a bovine aorta substrate and irradiated with an 808nm diode laser. A bond was created across an incision in the tissue substrate by alternately dispensing and coagulating each small volume of solder, or by coagulating a single large equivalent volume. Acute strength analysis was performed on the solder bond. Future work will concentrate on testing a bench-top solder dispensing device and investigating the feasibility of turning the deice into a prototype tool for clinical applications.

  20. Development of a soft-soldering system for aluminum

    NASA Astrophysics Data System (ADS)

    Falke, W. L.; Lee, A. Y.; Neumeier, L. A.

    1983-03-01

    The method employs application of a thin nickel copper alloy coating to the substrate, which enables the tin lead solders to wet readily and spread over the areas to be joined. The aluminum substrate is mechanically or chemically cleaned to facilitate bonding to a minute layer of zinc that is subsequently applied, with an electroless zincate solution. The nickel copper alloy (30 to 70 pct Ni) coating is then applied electrolytically over the zinc, using immersion cell or brush coating techniques. Development of acetate electrolytes has permitted deposition of the proper alloys coatings. The coated areas can then be readily joined with conventional tin lead solders and fluxs. The joints so formed are ductile, strong, and relatively corrosion resistant, and exhibit strengths equivalent to those formed on copper and brass when the same solders and fluxes are used. The method has also been employed to soft solder magnesium alloys.

  1. Robotic 3D vision solder joint verification system evaluation

    SciTech Connect

    Trent, M.A.

    1992-02-01

    A comparative performance evaluation was conducted between a proprietary inspection system using intelligent 3D vision and manual visual inspection of solder joints. The purpose was to assess the compatibility and correlation of the automated system with current visual inspection criteria. The results indicated that the automated system was more accurate (> 90%) than visual inspection (60--70%) in locating and/or categorizing solder joint defects. In addition, the automated system can offer significant capabilities to characterize and monitor a soldering process by measuring physical attributes, such as solder joint volumes and wetting angles, which are not available through manual visual inspection. A more in-depth evaluation of this technology is recommended.

  2. High temperature solder alloys for underhood applications. Progress report

    SciTech Connect

    Drewien, C.A.; Yost, F.G.; Sackinger, S.; Kern, J.; Weiser, M.W.

    1995-02-01

    Under a cooperative research and development agreement with General Motors Corporation, lead-free solder systems including the flux, metallization, and solder are being developed for high temperature, underhood applications. Six tin-rich solders, five silver-rich metallizations, and four fluxes were screened using an experimental matrix whereby every combination was used to make sessile drops via hot plate or Heller oven processing. The contact angle, sessile drop appearance, and in some instances the microstructure was evaluated to determine combinations that would yield contact angles of less than 30{degrees}, well-formed sessile drops, and fine, uniform microstructures. Four solders, one metallization, and one flux were selected and will be used for further aging and mechanical property studies.

  3. Conductance Degradation in HTS Coated Conductor Solder Joints

    NASA Astrophysics Data System (ADS)

    Canavan, Edgar R.; Leidecker, Henning; Panashchenko, Lyudmyla

    2015-12-01

    Solder joints between YBCO coated conductors and normal metal traces have been analysed as part of an effort to develop a robust HTS lead assembly for a spaceflight mission. Measurements included critical current and current transfer profiles. X-ray micrographs were used to verify proper solder flow and to determine the extent of voiding. SEM of cross-sections with EDS analysis was crucial in understanding the diffusion of the protective silver layer over the YBCO into the solder for different solder processes. The assembly must be stored for an extended period of time prior to final cool-down and operation. Measurements of the joint resistance over the course of months show a significant increase with time. Understanding the interface condition suggests an explanation for the change.

  4. Solder fatigue reduction in point focus photovoltaic concentrator modules

    SciTech Connect

    Hund, T.D.; Burchett, S.N.

    1991-01-01

    Solder fatigue tests have been conducted on point focus photovoltaic concentration cell assemblies to identify a baseline fatigue life and to quantify the fatigue life improvements that result using a copper-molybdenum-copper low-expansion insert between the solar cell and copper heat spreader. Solder microstructural changes and fatigue crack growth were identified using cross sections and ultrasonic scans of the fatigue solder joints. The Coffin-Manson and Total Strain fatigue models for low-cycle fatigue were evaluated for use in fatigue life predictions. Since both of these models require strain calculations, two strain calculation methods were compared: hand-calculated shear strain and a finite element method shear strain. At present, the available theoretical models for low-cycle solder fatigue are limited in their ability to predict failure; consequently, extensive thermal cycling is continuing to define the fatigue life for point focus photovoltaic cell assemblies. 9 refs., 9 figs., 2 tabs.

  5. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

    1987-10-23

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In molecular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating. 1 tab.

  6. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

    1989-05-09

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

  7. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, Timothy J.; Ginley, David S.; Zipperian, Thomas E.

    1989-01-01

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

  8. Investigation of gold embrittlement in connector solder joints

    NASA Technical Reports Server (NTRS)

    Lane, F. L.

    1972-01-01

    An investigation was performed to determine to what extent typical flight connector solder joints may be embrittled by the presence of gold. In addition to mapping of gold content in connector solder joints by an electron microprobe analyzer, metallographic examinations and mechanical tests (thermal shock, vibration, impact and tensile strength) were also conducted. A description of the specimens and tests, a discussion of the data, and some conclusions are presented.

  9. Eutectic Solder Bonding for Highly Manufacturable Microelectromechanical Systems Probe Card

    NASA Astrophysics Data System (ADS)

    Kim, Bonghwan

    2011-06-01

    We developed eutectic solder bonding for the microelectromechanical systems (MEMS) probe card. We tested various eutectic solder materials, such as Sn, AgSn, and AuSn, and investigated the bonding ability of Sn-based multi-element alloys and their resistance to chemical solutions. The Sn-based alloys were formed by sputtering, electroplating, and the use of solder paste. According to our experimental results, Sn-rich solders, such as Ag3.5Sn, Ag3.5Sn96Cu0.5, and Sn, were severely damaged by silicon wet etchant such as potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). On the other hand Au80Sn20 was resistant to those chemicals. In order to verify the joint bondability of the solders, we used a cantilever probe beam, and bump which were made of nickel and nickel alloy. After flip-chip bonding of the cantilever beam and the bump with Au80Sn20 solder paste, we measured the contact force to verify the mechanical strength. We then re-inspected it with X-rays and found no voids in the joint.

  10. Thermomechanical Stress and Strain in Solder Joints During Electromigration

    NASA Astrophysics Data System (ADS)

    Zhang, J. S.; Xi, H. J.; Wu, Y. P.; Wu, F. S.

    2009-05-01

    Thermomechanical stress and strain in the solder joints of a dummy area array package were studied as electromigration occurred. A current density of 0.4 × 104 A/cm2 was applied to this package, constructed with 9 × 9 solder joints in a daisy chain, to perform the electromigration test. After 37 h, the first joint on the path of the electron flow broke off at the cathode, and the first three solder joints all exhibited a typical accumulation of intermetallic compounds at the anode. Different solder joints exhibited dissimilar electromigration states, such as steady state and nonsteady state. Finite element analysis indicated that during steady-state electromigration, although the symmetrical structure produced uniform distributions of current density and Joule heating in all solder joints, the distribution of temperature was nonuniform. This was due to the imbalanced heat dissipation, which in turn affected the distribution of thermomechanical stress and strain in the solder joints. The maximum thermomechanical stress and strain, as well the highest temperature and current crowding, appeared in the Ni/Cu layer of each joint. The strain in the Ni/Cu layer was significant along the z-axis, but was constrained in the x- y plane. The thermomechanical stress and strain increased with advancing electromigration; thus, a potential delamination between the Ni/Cu layer and the printed circuit board could occur.

  11. Soldering in prosthodontics--an overview, part I.

    PubMed

    Byrne, Gerard

    2011-04-01

    The fit of fixed multiunit dental prostheses (FDP), traditionally termed fixed partial dentures (FPDs), is an ongoing problem. Poorly fitting restorations may hasten mechanical failure, due to abutment caries or screw failure. Soldering and welding play an important role in trying to overcome misfit of fixed multiunit prostheses. The term FPD will be used to denote multiunit fixed dental prostheses in this review. This is the first of a series of articles that review the state of the art and science of soldering and welding in relation to the fit of cemented or screw-retained multiunit prostheses. A comprehensive archive of background information and scientific findings is presented. Texts in dental materials and prosthodontics were reviewed. Scientific data were drawn from the numerous laboratory studies up to and including 2009. The background, theory, terminology, and working principles, along with the applied research, are presented. This first article focuses on soldering principles and dimensional accuracy in soldering. There is some discussion and suggestions for future research and development. Soldering may improve dimensional accuracy or reduce the distortion of multiunit fixed prostheses. Many variables can affect the outcome in soldering technique. Research science has developed some helpful guidelines. Research projects are disconnected and limited in scope. PMID:21323788

  12. The effect of interconnection resistance on the performance enhancement of liquid-nitrogen-cooled CMOS circuits

    SciTech Connect

    Watt, J.T. ); Plummer, J.D. . Center for Integrated Systems)

    1989-08-01

    The effect of interconnection resistance on CMOS circuit performance is examined at room temperature and liquid-nitrogen temperature. The interconnection is modeled as a distributed RLC line driven by an optimal configuration of cascaded inverters. The thin-film resistivity of pure aluminum has been measured to allow accurate prediction of the effect of interconnection resistance on performance. A critical interconnect length is defined as the point at which interconnect resistance begins to dominate propagation delay time. The critical interconnect length is computed at room temperature and liquid-nitrogen temperature for present-day and scaled CMOS technologies and compared to the maximum interconnect length expected in state-of-the-art VLSI circuits. Conclusions are drawn concerning the importance of interconnection resistance in determining the enhancement in performance achieved through reduced-temperature operation of CMOS integrated circuits.

  13. Hybrid optically interconnected microprocessor: an InP I-MSM integrated onto a mixed-signal CMOS analog optical receiver with a digital CMOS microprocessor

    NASA Astrophysics Data System (ADS)

    Chang, Jae J.; Jung, Sungyong; Vrazel, Michael; Jung, Keeshik; Lee, Myunghee; Brooke, Martin A.; Jokerst, Nan Marie; Wills, Scott

    2000-05-01

    This paper presents the results of simultaneously working fully-differential optoelectronic receiver fabricated in Si CMOS with digital SIMD microprocessor on the same die next to analog, optical interface circuitry, the receiver have been hybrid integrated with a thin film InP-based inverted (I)-MSM photodetector and optically tested using external light source modulated by digital input signal. The noise immunity to mixed-signal digital switching noise of the differential receiver has been shown to be good enough to generate 10-9 BER.

  14. Evaluation of temperatures attained by electronic components during various manual soldering operations

    NASA Astrophysics Data System (ADS)

    Dunn, B. D.; Hilbrands, G.; Nielsen, P. J.

    1983-03-01

    After component-failure analyses showed that defective spacecraft devices were overheated during soldering, it was verified that quality-assurance personnel omitted to control pretinning-bath and soldering iron temperatures, so data were acquired under controlled processing conditions. Component temperature rises were recorded during degolding, pretinning, soldering and the reworking of soldered joints. Results show that existing ESA specifications for manual soldering and repair ensure that the maximum temperature ratings ascribed to standard spacecraft components are not exceeded. Application of heat sinks to certain delicate components during degolding is essential, and it can be advantageous to apply them during pretinning and other soldering operations.

  15. Lead-free solder technology transfer from ASE Americas

    SciTech Connect

    FTHENAKIS,V.

    1999-10-19

    To safeguard the environmental friendliness of photovoltaics, the PV industry follows a proactive, long-term environmental strategy involving a life-of-cycle approach to prevent environmental damage by its processes and products from cradle to grave. Part of this strategy is to examine substituting lead-based solder on PV modules with other solder alloys. Lead is a toxic metal that, if ingested, can damage the brain, nervous system, liver and kidneys. Lead from solder in electronic products has been found to leach out from municipal waste landfills and municipal incinerator ash was found to be high in lead also because of disposed consumer electronics and batteries. Consequently, there is a movement in Europe and Japan to ban lead altogether from use in electronic products and to restrict the movement across geographical boundaries of waste containing lead. Photovoltaic modules may contain small amounts of regulated materials, which vary from one technology to another. Environmental regulations impact the cost and complexity of dealing with end-of-life PV modules. If they were classified as hazardous according to Federal or State criteria, then special requirements for material handling, disposal, record-keeping and reporting would escalate the cost of decommissioning the modules. Fthenakis showed that several of today's x-Si modules failed the US-EPA Toxicity Characteristic Leaching Procedure (TCLP) for potential leaching of Pb in landfills and also California's standard on Total Threshold Limit Concentration (TTLC) for Pb. Consequently, such modules may be classified as hazardous waste. He highlighted potential legislation in Europe and Japan which could ban or restrict the use of lead and the efforts of the printed-circuit industries in developing Pb-free solder technologies in response to such expected legislation. Japanese firms already have introduced electronic products with Pb-free solder, and one PV manufacturer in the US, ASE Americas has used a Pb

  16. Characterization of Low-Melting-Point Sn-Bi-In Lead-Free Solders

    NASA Astrophysics Data System (ADS)

    Li, Qin; Ma, Ninshu; Lei, YongPing; Lin, Jian; Fu, HanGuang; Gu, Jian

    2016-02-01

    Development of lead-free solders with low melting temperature is important for substitution of Pb-based solders to reduce direct risks to human health and the environment. In the present work, Sn-Bi-In solders were studied for different ratios of Bi and Sn to obtain solders with low melting temperature. The microstructure, thermal properties, wettability, mechanical properties, and reliability of joints with Cu have been investigated. The results show that the microstructures of the Sn-Bi-In solders were composed of β-Sn, Bi, and InBi phases. The intermetallic compound (IMC) layer was mainly composed of Cu6Sn5, and its thickness increased slightly as the Bi content was increased. The melting temperature of the solders was around 100°C to 104°C. However, when the Sn content exceeded 50 wt.%, the melting range became larger and the wettability became worse. The tensile strength of the solder alloys and solder joints declined with increasing Bi content. Two fracture modes (IMC layer fracture and solder/IMC mixed fracture) were found in solder joints. The fracture mechanism of solder joints was brittle fracture. In addition, cleavage steps on the fracture surface and coarse grains in the fracture structure were comparatively apparent for higher Bi content, resulting in decreased elongation for both solder alloys and solder joints.

  17. Microbial leaching of waste solder for recovery of metal.

    PubMed

    Hocheng, H; Hong, T; Jadhav, U

    2014-05-01

    This study proposes an environment-friendly bioleaching process for recovery of metals from solders. Tin-copper (Sn-Cu), tin-copper-silver (Sn-Cu-Ag), and tin-lead (Sn-Pb) solders were used in the current study. The culture supernatant of Aspergillus niger removed metals faster than the culture supernatant of Acidithiobacillus ferrooxidans. Also, the metal removal by A. niger culture supernatant is faster for Sn-Cu-Ag solder as compared to other solder types. The effect of various process parameters such as shaking speed, temperature, volume of culture supernatant, and increased solder weight on bioleaching of metals was studied. About 99 (±1.75) % metal dissolution was achieved in 60 h, at 200-rpm shaking speed, 30 °C temperature, and by using 100-ml A. niger culture supernatant. An optimum solder weight for bioleaching was found to be 5 g/l. Addition of sodium hydroxide (NaOH) and sodium chloride (NaCl) in the bioleached solution from Sn-Cu-Ag precipitated tin (85 ± 0.35 %) and silver (80 ± 0.08 %), respectively. Passing of hydrogen sulfide (H2S) gas at pH 8.1 selectively precipitated lead (57.18 ± 0.13 %) from the Sn-Pb bioleached solution. The proposed innovative bioleaching process provides an alternative technology for recycling waste solders to conserve resources and protect environment. PMID:24634142

  18. Solder wetting behavior enhancement via laser-textured surface microcosmic topography

    NASA Astrophysics Data System (ADS)

    Chen, Haiyan; Peng, Jianke; Fu, Li; Wang, Xincheng; Xie, Yan

    2016-04-01

    In order to reduce or even replace the use of Sn-Pb solder in electronics industry, the laser-textured surface microstructures were used to enhance the wetting behavior of lead free solder during soldering. According to wetting theory and Sn-Ag-Cu lead free solder performance, we calculated and designed four microcosmic structures with the similar shape and different sizes to control the wetting behavior of lead free solder. The micro-structured surfaces with different dimensions were processed on copper plates by fiber femtosecond laser, and the effect of microstructures on wetting behavior was verified experimentally. The results showed that the wetting angle of Sn-Ag-Cu solder on the copper plate with microstructures decreased effectively compared with that on the smooth copper plate. The wetting angles had a sound fit with the theoretical values calculated by wetting model. The novel method provided a feasible route for adjusting the wetting behavior of solders and optimizing solders system.

  19. Development of a new Pb-free solder: Sn-Ag-Cu

    SciTech Connect

    Miller, C.M.

    1995-02-10

    With the ever increasing awareness of the toxicity of Pb, significant pressure has been put on the electronics industry to get the Pb out of solder. This work pertains to the development and characterization of an alloy which is Pb-free, yet retains the proven positive qualities of current Sn-Pb solders while enhancing the shortcomings of Sn-Pb solder. The solder studied is the Sn-4.7Ag-1.7Cu wt% alloy. By utilizing a variety of experimental techniques the alloy was characterized. The alloy has a melting temperature of 217{degrees}C and exhibits eutectic melting behavior. The solder was examined by subjecting to different annealing schedules and examining the microstructural stability. The effect of cooling rate on the microstructure of the solder was also examined. Overall, this solder alloy shows great promise as a viable alternative to Pb-bearing solders and, as such, an application for a patent has been filed.

  20. Optics vs copper: from the perspective of "Thunderbolt" interconnect technology

    NASA Astrophysics Data System (ADS)

    Cheng, Hengju; Krause, Christine; Ko, Jamyuen; Gao, Miaobin; Liu, Guobin; Wu, Huichin; Qi, Mike; Lam, Chun-Chit

    2013-02-01

    Interconnect technology has been progressed at a very fast pace for the past decade. The signaling rates have steadily increased from 100:Mb/s to 25Gb/s. In every generation of interconnect technology evolution, optics always seems to take over at first, however, at the end, the cost advantage of copper wins over. Because of this, optical interconnects are limited to longer distance links where the attenuation in copper cable is too large for the integrated circuits to compensate. Optical interconnect has long been viewed as the premier solution in compared with copper interconnect. With the release of Thunderbolt technology, we are entering a new era in consumer electronics that runs at 10Gb/s line rate (20Gb/s throughput per connector interface). Thunderbolt interconnect technology includes both active copper cables and active optical cables as the transmission media which have very different physical characteristics. In order for optics to succeed in consumer electronics, several technology hurdles need to be cleared. For example, the optical cable needs to handle the consumer abuses such as pinch and bend. Also, the optical engine used in the active optical cable needs to be physically very small so that we don't change the looks and feels of the cable/connector. Most importantly, the cost of optics needs to come down significantly to effectively compete with the copper solution. Two interconnect technologies are compared and discussed on the relative cost, power consumption, form factor, density, and future scalability.

  1. Interconnect resistance of photovoltaic submodules

    NASA Technical Reports Server (NTRS)

    Volltrauer, H.; Eser, E.; Delahoy, A. E.

    1985-01-01

    Small area amorphous silicon solar cells generally have higher efficiencies than large interconnected submodules. Among the reasons for the differences in performance are the lack of large area uniformity, the effect of nonzero tin oxide sheet resistance, and possibly pinholes in the various layers. Another and usually small effect that can contribute to reduced performance of interconnected cells is the resistance of the interconnection i.e., the series resistance introduced by the metal to tin oxide contact through silicon. Proper processing problems to avoid poor contacts are discussed.

  2. Reliability of lead-free solders in electronic packaging technology

    NASA Astrophysics Data System (ADS)

    Choi, Woojin

    The electromigration of flip chip solder bump (eutetic SnPb) has been studied at temperatures of 100, 125 and 150°C and current densities of 1.9 to 2.75 x 104 A/cm2. The under-bump-metallization on the chip side is thin film Al/Ni(V)/Cu and on the board side is thick Cu. By simulation, we found that current crowding occurs at the corner on the chip side where the electrons enter the solder ball. We are able to match this simulation to the real electromigration damage in the sample. The experimental result showed that voids initiated from the position of current crowding and propagated across the interface between UBM and the solder ball. The Cu-Sn intermetallic compounds formed during the reflow is known to adhere well to the thin film UBM, but they detached from the UBM after current stressing. Therefore, the UBM itself becomes part of the reliability problem of the flip chip solder joint under electromigration. Currently there is a renewed interest in Sn whisker growth owing to the introduction of Pb-free solder in electronic manufacturing. The leadframe is electroplated or finished with a layer of Pb-free solder. The solder is typically pure Sn or eutectic SnCu (0.7 atomic % Cu). It is a serious reliability concern in the use of the eutectic SnCu solder as leadframe surface finish due to the growth of long whiskers on it. The origin of the driving force of compressive stress can be mechanical, thermal, and chemical. Among them, the chemical force is the most important contribution to the whisker growth and its origin is due to the reaction between Sn and Cu to form intermetallic compound (IMC) at room temperature. For whisker or hillock growth, the surface cannot be free of oxide and it must be covered with oxide and the oxide must be a protective one so that it removes effectively all the vacancy sources and sinks on the surface. Hence, only those metals, which grow protective oxides such as Al and Sn, are known to have hillock growth or whisker growth. We

  3. Nano copper based high temperature solder alternative

    NASA Astrophysics Data System (ADS)

    Sharma, Akshay

    Nano Cu an alternative to high temperature solder is developed by the Advance Technological Center at the Lockheed Martin Corporation. A printable paste of Cu nano particles is developed with an ability to fuse at 200°C in reflow oven. After reflow the deposited material has nano crystalline and nano porous structure which affects its properties. Accelerated test are performed on nano Cu deposition having nano porous and nano crystalline structure for assessment and prediction of reliability. Nano Cu assemblies with different bond layer thickness are sheared to calculate the strength of the material and are correlated with the porous and crystalline structure of nano Cu. Thermal and isothermal fatigue test are performed on nano Cu to see the dependency of life on stress and further surface of failed assemblies were observed to determine the type of failure. Creep test at RT are performed to find the type of creep mechanism and how they are affected when subjected to high temperature. TEM, SEM, X-ray, C-SAM and optical microscopy is done on the nano Cu sample for structure and surface analysis.

  4. Solder creep-fatigue interactions with flexible leaded parts

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.; Wen, L. C.; Mon, G. R.; Jetter, E.

    1992-01-01

    With flexible leaded parts, the solder-joint failure process involves a complex interplay of creep and fatigue mechanisms. To better understand the role of creep in typical multi-hour cyclic loading conditions, a specialized non-linear finite-element creep simulation computer program has been formulated. The numerical algorithm includes the complete part-lead-solder-PWB system, accounting for strain-rate dependence of creep on applied stress and temperature, and the role of the part-lead dimensions and flexibility that determine the total creep deflection (solder strain range) during stress relaxation. The computer program has been used to explore the effects of various solder creep-fatigue parameters such as lead height and stiffness, thermal-cycle test profile, and part/board differential thermal expansion properties. One of the most interesting findings is the strong presence of unidirectional creep-ratcheting that occurs during thermal cycling due to temperature dominated strain-rate effects. To corroborate the solder fatigue model predictions, a number of carefully controlled thermal-cycle tests have been conducted using special bimetallic test boards.

  5. Experimental Methods in Reduced-gravity Soldering Research

    NASA Technical Reports Server (NTRS)

    Pettegrew, Richard D.; Struk, Peter M.; Watson, John K.; Haylett, Daniel R.

    2002-01-01

    The National Center for Microgravity Research, NASA Glenn Research Center, and NASA Johnson Space Center are conducting an experimental program to explore the influence of reduced gravity environments on the soldering process. An improved understanding of the effects of the acceleration environment is important to application of soldering during current and future human space missions. Solder joint characteristics that are being considered include solder fillet geometry, porosity, and microstructural features. Both through-hole and surface mounted devices are being investigated. This paper focuses on the experimental methodology employed in this project and the results of macroscopic sample examination. The specific soldering process, sample configurations, materials, and equipment were selected to be consistent with those currently on-orbit. Other apparatus was incorporated to meet requirements imposed by operation onboard NASA's KC-135 research aircraft and instrumentation was provided to monitor both the atmospheric and acceleration environments. The contingent of test operators was selected to include both highly skilled technicians and less skilled individuals to provide a population cross-section that would be representative of the skill mix that might be encountered in space mission crews.

  6. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  7. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  8. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  9. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  10. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  11. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  12. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  13. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  14. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  15. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  16. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  17. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  18. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  19. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  20. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  1. Clad metals by roll bonding for SOFC interconnects

    NASA Astrophysics Data System (ADS)

    Chen, L.; Jha, B.; Yang, Zhenguo; Xia, Guang-Guang; Stevenson, Jeffry W.; Singh, Prabhakar

    2006-08-01

    High-temperature oxidation-resistant alloys are currently considered as a candidate material for construction of interconnects in intermediate-temperature solid oxide fuel cells. Among these alloys, however, different groups of alloys demonstrate different advantages and disadvantages, and few, if any, can completely satisfy the stringent requirements for the application. To integrate the advantages and avoid the disadvantages of different groups of alloys, cladding has been proposed as one approach in fabricating metallic layered interconnect structures. To examine the feasibility of this approach, the austenitic Ni-base alloy Haynes 230 and the ferritic stainless steel AL 453 were selected as examples and manufactured into a clad metal. Its suitability as an interconnect construction material was investigated. This paper provides a brief overview of the cladding approach and discusses the viability of this technology to fabricate the metallic layered-structure interconnects.

  2. Delay model for dynamically switching coupled RLC interconnects

    NASA Astrophysics Data System (ADS)

    Sharma, Devendra Kumar; Kaushik, Brajesh Kumar; Sharma, Rajender Kumar

    2014-04-01

    With the evolution of integrated circuit technology, the interconnect parasitics can be the limiting factor in high speed signal transmission. With increasing frequency of operation, length of interconnect and fast transition time of the signal, the RC models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are very much required. This paper proposes an analytical model for estimating propagation delay in lossy coupled RLC interconnect lines for simultaneously switching scenario. To verify the proposed model, the analytical results are compared with those of FDTD and SPICE results for the two cases of inputs switching under consideration. An average error of 2.07% is observed which shows an excellent agreement with SPICE simulation and FDTD computations.

  3. Printing Stretchable Spiral Interconnects Using Reactive Ink Chemistries.

    PubMed

    Mamidanna, Avinash; Song, Zeming; Lv, Cheng; Lefky, Christopher S; Jiang, Hanqing; Hildreth, Owen J

    2016-05-25

    Stretchable electronics have important applications in health monitoring and integrated lab-on-a-chip devices. This paper discusses the performance of serpentine stretchable interconnects printed using self-reducing, silver reactive inks. It details process optimization, device fabrication, and device characterization, while demonstrating the potential applications for reactive inks and new design strategies in stretchable electronics. Devices were printed with an ethanol stabilized silver diamine reactive ink and cycled to stretch ratios of 140 and 160% over 1000 cycles with less than 2.5% variation in electrical resistance. Maximum deformation before failure was measured at 180% elongation. Additionally, interconnect deformation was compared to finite element analysis (FEA) simulations to show that FEA can be used to accurately model the deformation of low-strain printed interconnects. Overall, this paper demonstrates a simple and affordable route toward stretchable electrical interconnects. PMID:27158736

  4. Renewable Systems Interconnection: Executive Summary

    SciTech Connect

    Kroposki, B.; Margolis, R.; Kuswa, G.; Torres, J.; Bower, W.; Key, T.; Ton, D.

    2008-02-01

    The U.S. Department of Energy launched the Renewable Systems Interconnection (RSI) study in 2007 to address the challenges to high penetrations of distributed renewable energy technologies. The RSI study consists of 14 additional reports.

  5. Integration of thin film decoupling capacitors

    SciTech Connect

    Garino, T.; Dimos, D.; Lockwood, S.

    1994-10-01

    Thin film decoupling capacitors consisting of submicron thick, sol-gel Pb(Zr,Ti)O{sub 3} layers between Pt electrodes on a Si substrate have recently been developed. Because the capacitor structure needs to be only {approximately}3 {mu}m thick, these devices offer advantages such as decreased package volume and ability to integrate so that interconnect inductance is decreased, which allows faster IC processing rates. To fully utilize these devices, techniques of integrating them onto packages such as multi-chip modules and printed wiring boards or onto IC dies must be developed. The results of our efforts at developing integration processes for these capacitors are described here. Specifically, we have demonstrated a process for printing solder on the devices at the Si wafer level and reflowing it to form bumps and have developed a process for fabricating the devices on thin (25 to 75 {mu}m) substrates to facilitate integration onto ICs and printed wiring boards. Finally, we assessed the feasibility of fabricating the devices on rough surfaces to determine whether it would be possible to fabricate these capacitors directly on multi-layer ceramic substrates.

  6. Effects of solder temperature on pin through-hole during wave soldering: thermal-fluid structure interaction analysis.

    PubMed

    Aziz, M S Abdul; Abdullah, M Z; Khor, C Y

    2014-01-01

    An efficient simulation technique was proposed to examine the thermal-fluid structure interaction in the effects of solder temperature on pin through-hole during wave soldering. This study investigated the capillary flow behavior as well as the displacement, temperature distribution, and von Mises stress of a pin passed through a solder material. A single pin through-hole connector mounted on a printed circuit board (PCB) was simulated using a 3D model solved by FLUENT. The ABAQUS solver was employed to analyze the pin structure at solder temperatures of 456.15 K (183(°)C) < T < 643.15 K (370(°)C). Both solvers were coupled by the real time coupling software and mesh-based parallel code coupling interface during analysis. In addition, an experiment was conducted to measure the temperature difference (ΔT) between the top and the bottom of the pin. Analysis results showed that an increase in temperature increased the structural displacement and the von Mises stress. Filling time exhibited a quadratic relationship to the increment of temperature. The deformation of pin showed a linear correlation to the temperature. The ΔT obtained from the simulation and the experimental method were validated. This study elucidates and clearly illustrates wave soldering for engineers in the PCB assembly industry. PMID:25225638

  7. An Overview of Surface Finishes and Their Role in Printed Circuit Board Solderability and Solder Joint Performance

    SciTech Connect

    Vianco, P.T.

    1998-10-15

    A overview has been presented on the topic of alternative surface finishes for package I/Os and circuit board features. Aspects of processability and solder joint reliability were described for the following coatings: baseline hot-dipped, plated, and plated-and-fused 100Sn and Sn-Pb coatings; Ni/Au; Pd, Ni/Pd, and Ni/Pd/Au finishes; and the recently marketed immersion Ag coatings. The Ni/Au coatings appear to provide the all-around best option in terms of solderability protection and wire bondability. Nickel/Pal ftishes offer a slightly reduced level of performance in these areas that is most likely due to variable Pd surface conditions. It is necessmy to minimize dissolved Au or Pd contents in the solder material to prevent solder joint embrittlement. Ancillary aspects that included thickness measurement techniques; the importance of finish compatibility with conformal coatings and conductive adhesives; and the need for alternative finishes for the processing of non-Pb bearing solders were discussed.

  8. Effects of Solder Temperature on Pin Through-Hole during Wave Soldering: Thermal-Fluid Structure Interaction Analysis

    PubMed Central

    Abdul Aziz, M. S.; Abdullah, M. Z.; Khor, C. Y.

    2014-01-01

    An efficient simulation technique was proposed to examine the thermal-fluid structure interaction in the effects of solder temperature on pin through-hole during wave soldering. This study investigated the capillary flow behavior as well as the displacement, temperature distribution, and von Mises stress of a pin passed through a solder material. A single pin through-hole connector mounted on a printed circuit board (PCB) was simulated using a 3D model solved by FLUENT. The ABAQUS solver was employed to analyze the pin structure at solder temperatures of 456.15 K (183°C) < T < 643.15 K (370°C). Both solvers were coupled by the real time coupling software and mesh-based parallel code coupling interface during analysis. In addition, an experiment was conducted to measure the temperature difference (ΔT) between the top and the bottom of the pin. Analysis results showed that an increase in temperature increased the structural displacement and the von Mises stress. Filling time exhibited a quadratic relationship to the increment of temperature. The deformation of pin showed a linear correlation to the temperature. The ΔT obtained from the simulation and the experimental method were validated. This study elucidates and clearly illustrates wave soldering for engineers in the PCB assembly industry. PMID:25225638

  9. Silver nanosintering: a lead-free alternative to soldering

    NASA Astrophysics Data System (ADS)

    Maruyama, Minoru; Matsubayashi, Ryo; Iwakuro, Hiroaki; Isoda, Seiji; Komatsu, Teruo

    2008-07-01

    We propose a lead-free silver paste as a replacement for a high-temperature lead-rich solder used for electronics. The pastes tested here contain a small amount of solvent, but primarily consist of silver powder and alkoxide-passivated silver nanoparticles that undergo nanosintering when heated. The pastes were used to connect silicon diode chips to copper bases at 350°C in nitrogen ambient without external pressure. The resulting diode packages had electrical and thermal properties about equal to those with lead-solder joints. The mechanical strengths also were comparable to the lead joint. These properties make this nanosilver paste the first viable lead-free alternative to a lead solder.

  10. Development of alternatives to lead-bearing solders

    SciTech Connect

    Vianco, P.T.

    1993-07-01

    Soldering technology, using tin-lead alloys has had a significant role in the packaging of highly functional, low cost electronic devices. The elimination of lead from all manufactured products, whether through legislation or tax incentives, will impact the electronics community which uses lead-containing solders. In response to these proposed measures, the National Center for Manufacturing Sciences has established a multi-year program involving participants from industry, academia, and the national laboratories with the objective to identify potential replacements for lead-bearing solders. Selection of candidate alloys is based upon the analysis of materials properties, manufacturability, modeling codes for reliability prediction, as well as toxicological properties and resource availability, data developed in the program.

  11. Corrosion Issues in Solder Joint Design and Service

    SciTech Connect

    VIANCO,PAUL T.

    1999-11-24

    Corrosion is an important consideration in the design of a solder joint. It must be addressed with respect to the service environment or, as in the case of soldered conduit, as the nature of the medium being transported within piping or tubing. Galvanic-assisted corrosion is of particular concern, given the fact that solder joints are comprised of different metals or alloy compositions that are in contact with one-another. The (thermodynamic) potential for corrosion to take place in a particular environment requires the availability of the galvanic series for those conditions and which includes the metals or alloys in question. However, the corrosion kinetics, which actually determine the rate of material loss under the specified service conditions, are only available through laboratory evaluations or field data that are found in the existing literature or must be obtained by in-house testing.

  12. Materials chemistry. Composition-matched molecular "solders" for semiconductors.

    PubMed

    Dolzhnikov, Dmitriy S; Zhang, Hao; Jang, Jaeyoung; Son, Jae Sung; Panthani, Matthew G; Shibata, Tomohiro; Chattopadhyay, Soma; Talapin, Dmitri V

    2015-01-23

    We propose a general strategy to synthesize largely unexplored soluble chalcogenidometallates of cadmium, lead, and bismuth. These compounds can be used as "solders" for semiconductors widely used in photovoltaics and thermoelectrics. The addition of solder helped to bond crystal surfaces and link nano- or mesoscale particles together. For example, CdSe nanocrystals with Na2Cd2Se3 solder was used as a soluble precursor for CdSe films with electron mobilities exceeding 300 square centimeters per volt-second. CdTe, PbTe, and Bi2Te3 powders were molded into various shapes in the presence of a small additive of composition-matched chalcogenidometallate or chalcogel, thus opening new design spaces for semiconductor technologies. PMID:25569110

  13. Solder wetting kinetics in narrow V-grooves

    SciTech Connect

    Yost, F.G.; Rye, R.R.; Mann, J.A. Jr.

    1997-12-01

    Experiments are performed to observe capillary flow in grooves cut into copper surfaces. Flow kinetics of two liquids, 1-heptanol and eutectic Sn-Pb solder, are modeled with modified Washburn kinetics and compared to flow data. It is shown that both liquids flow parabolically in narrow V-grooves, and the data scale as predicted by the modified Washburn model. The early portions of the flow kinetics are characterized by curvature in the length vs time relationship which is not accounted for in the modified Washburn model. This effect is interpreted in terms of a dynamic contact angle. It is concluded that under conditions of rapid flow, solder spreading can be understood as a simple fluid flow process. Slower kinetics, e.g. solder droplet spreading on flat surfaces, may be affected by subsidiary chemical processes such as reaction.

  14. Materials and mechanics issues of solder alloy applications

    NASA Astrophysics Data System (ADS)

    Kinsman, Ken; Frear, Darrel R.; Jones, Wendell B.

    1990-09-01

    The key conclusion out of the Solder Mechanics Workshop is that, overall, the technical and scientific community does not know as much quantitatively about solder behavior as we had hoped. The good news, however, is that the microelectronics user community, which is largely served by solder activities, has come to terms with the current environment through active participation in the workshop. The air has been cleared. As a technical community, we have a better idea of what our priorities for continued research are. A much more detailed overview of the workshop will be available shortly in monograph form. Individual chapters will be written by authors present at the workshop and will emphasize background material (e.g., literature critiques) and detail the technical consensus on critical issues central to the workshop. The book will be available through TMS and will be the first volume in a new series of technical monographs sponsored by the society's Electronic, Magnetic and Photonic Materials Division.

  15. Drinking Water Contamination Due To Lead-based Solder

    NASA Astrophysics Data System (ADS)

    Garcia, N.; Bartelt, E.; Cuff, K. E.

    2004-12-01

    The presence of lead in drinking water creates many health hazards. Exposure to lead-contaminated water can affect the brain, the central nervous system, blood cells, and kidneys, causing such problems as mental retardation, kidney disease, heart disease, stroke, and death. One way in which lead can contaminate our water supply is through the use of lead solder to join pipes. Lead solder was widely used in the past because of its ease of application as well as its low cost. Lead contamination in residential areas has previously been found to be a particularly serious problem in first-draw samples, of water that has sat stagnant in pipes overnight. To investigate the time-dependence of drinking water lead contamination, we analyzed samples taken hourly of water exposed to lead solder. While our preliminary data was insufficient to show more than a rough correlation between time of exposure and lead concentration over short periods (1-3 hours), we were able to confirm that overnight exposure of water to lead-based solder results in the presence high levels of lead. We also investigated other, external factors that previous research has indicated contribute to increased concentrations of lead. Our analysis of samples of lead-exposed water at various pH and temperatures suggests that these factors can be equally significant in terms of their contribution to elevated lead concentration levels. In particular, water that is slightly corrosive appears to severely impact the solubility of lead. As this type of water is common in much of the Northeast United States, the presence of lead-based solder in residential areas there is especially problematic. Although lead-based solder has been banned since the 1980s, it remains a serious concern, and a practical solution still requires further research.

  16. Polyhedral integrated and free space optical interconnection

    DOEpatents

    Erteza, Ireena A.

    1998-01-01

    An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment.

  17. Polyhedral integrated and free space optical interconnection

    DOEpatents

    Erteza, I.A.

    1998-01-06

    An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment. 7 figs.

  18. Solder extrusion pressure bonding process and bonded products produced thereby

    SciTech Connect

    Beavis, L.C.; Karnowsky, M.M.; Yost, F.G.

    1990-12-31

    Production of soldiered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about {minus}40{degrees}C and 110{degrees}C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  19. A ban on use of lead-bearing solders: Implications for the electronics industry

    SciTech Connect

    Vianco, P.T.; Yost, F.G.

    1992-04-01

    This white paper addresses the issue of banning lead from solders used in electronics manufacturing. The current efforts by legislative bodies and regulatory agencies to curtail the use of lead in manufactured goods, including solders, are described. In response to a ban on lead or the imposition of a tax which makes lead uneconomical for use in solder alloys, alternative technologies including lead-free solders and conductive epoxies are presented. The recommendation is made that both users and producers of solder materials join together as partners in a consortium to address this issue in a timely and cost-effective manner.

  20. Preparation of Sn—Ag—In ternary solder bumps by electroplating in sequence and reliability

    NASA Astrophysics Data System (ADS)

    Dongliang, Wang; Yuan, Yuan; Le, Luo

    2011-08-01

    This paper describes a technique that can obtain ternary Sn—Ag—In solder bumps with fine pitch and homogenous composition distribution. The mainfeature of this process is that tin-silver and indium are electroplated on copper under bump metallization (UBM) in sequence. After an accurate reflow process, Sn1.8Ag9.4In solder bumps are obtained. It is found that the intermetallic compounds (IMCs) between Sn—Ag—In solder and Cu grow with the reflow time, which results in an increase in Ag concentration in the solder area. So during solidification, more Ag2In nucleates and strengthens the solder.

  1. Process characterization and control of hand-soldered printed wiring assemblies

    SciTech Connect

    Cheray, D.L.; Mandl, R.G.

    1993-09-01

    A designed experiment was conducted to characterize the hand soldering process parameters for manufacturing printed wiring assemblies (PWAs). Component tinning was identified as the most important parameter in hand soldering. After tinning, the soldering iron tip temperature of 700{degrees}F and the choice of operators influence solder joint quality more than any other parameters. Cleaning and flux/flux core have little impact on the quality of the solder joint. The need for component cleaning prior to assembly must be evaluated for each component.

  2. Misalignment corrections in optical interconnects

    NASA Astrophysics Data System (ADS)

    Song, Deqiang

    Optical interconnects are considered a promising solution for long distance and high bitrate data transmissions, outperforming electrical interconnects in terms of loss and dispersion. Due to the bandwidth and distance advantage of optical interconnects, longer links have been implemented with optics. Recent studies show that optical interconnects have clear advantages even at very short distances---intra system interconnects. The biggest challenge for such optical interconnects is the alignment tolerance. Many free space optical components require very precise assembly and installation, and therefore the overall cost could be increased. This thesis studied the misalignment tolerance and possible alignment correction solutions for optical interconnects at backplane or board level. First the alignment tolerance for free space couplers was simulated and the result indicated the most critical alignments occur between the VCSEL, waveguide and microlens arrays. An in-situ microlens array fabrication method was designed and experimentally demonstrated, with no observable misalignment with the waveguide array. At the receiver side, conical lens arrays were proposed to replace simple microlens arrays for a larger angular alignment tolerance. Multilayer simulation models in CodeV were built to optimized the refractive index and shape profiles of the conical lens arrays. Conical lenses fabricated with micro injection molding machine and fiber etching were characterized. Active component VCSOA was used to correct misalignment in optical connectors between the board and backplane. The alignment correction capability were characterized for both DC and AC (1GHz) optical signal. The speed and bandwidth of the VCSOA was measured and compared with a same structure VCSEL. Based on the optical inverter being studied in our lab, an all-optical flip-flop was demonstrated using a pair of VCSOAs. This memory cell with random access ability can store one bit optical signal with set or

  3. Creep deformation behavior in eutectic Sn-Ag solder joints using a novel mapping technique

    SciTech Connect

    Lucas, J.P.; Guo, F.; McDougall, J.; Bieler, T.R.; Subramanian, K.N.; Park, J.K.

    1999-11-01

    Creep deformation behavior was measured for 60--100 {micro}m thick solder joints. The solder joints investigated consisted of: (1) non-composite solder joints made with eutectic Sn-Ag solder, and (2) composite solder joints with eutectic Sn-Ag solder containing 20 vol.%, 5 {micro}m diameter in-situ Cu{sub 6}Sn{sub 5} intermetallic reinforcements. All creep testing in this study was carried out at room temperature. Qualitative and quantitative assessment of creep deformation was characterized on the solder joints. Creep deformation was analyzed using a novel mapping technique where a geometrical-regular line pattern was etched over the entire solder joint using excimer laser ablation. During creep, the laser-ablation (LA) pattern becomes distorted due to deformation in the solder joint. By imaging the distortion of laser-ablation patterns using the SEM, actual deformation mapping for the entire solder joint is revealed. The technique involves sequential optical/digital imaging of the deformation versus time history during creep. By tracing and recording the deformation of the LA patterns on the solder over intervals of time, local creep data are obtained in many locations in the joint. This analysis enables global and localized creep shear strains and strain rate to be determined.

  4. Sn-Ag-Cu and Sn-Cu solders: Interfacial reactions with platinum

    NASA Astrophysics Data System (ADS)

    Kim, Tae Hyun; Kim, Young-Ho

    2004-06-01

    The interfacial reaction and intermetallic formation at the interface between tin solders containing a small amount of copper with platinum were investigated in this study. Sn-0.7Cu and Sn-1.7Cu solders were reacted with platinum by dipping Pt/Ti/Si specimens into the molten solder at 260°C. Sn-3.8Ag-0.7Cu solder was reacted with platinum by reflowing solder paste on a Pt/Ti/Si substrate at 250°C. PtSn4 intermetallic formed in all specimens while Cu6Sn5 interfacial intermetallic was not observed at the solder/platinum interfaces in any specimens. A parabolic relationship existed between the thickness of the Pt-Sn intermetallic and reaction time, which indicates the intermetallic formation in the solder/platinum interface is diffusion controlled.

  5. Local melting induced by electromigration in flip-chip solder joints

    NASA Astrophysics Data System (ADS)

    Tsai, C. M.; Lin, Y. L.; Tsai, J. Y.; Lai, Yi-Shao; Kao, C. R.

    2006-05-01

    A new electromigration failure mechanism in flip-chip solder joints is reported. The solder joints failed by local melting of a PbSn eutectic solder. Local melting occurred due to a sequence of events induced by the microstructure changes in the flip-chip solder joint. The formation of a depression in the current-crowding region of a solder joint induced the local electrical resistance to increase. The rising local resistance resulted in a larger Joule heating, which, in turn, raised the local temperature. When the local temperature rose above the eutectic temperature of the PbSn solder, the solder joint melted and consequently failed. The results of this study suggest that a dynamic, coupled simulation that takes into account the microstructure evolution, current density distribution, and temperature distribution may be needed to fully solve this problem.

  6. Soldering and brazing safety guide: A handbook on space practice for those involved in soldering and brazing

    NASA Astrophysics Data System (ADS)

    This manual provides those involved in welding and brazing with effective safety procedures for use in performance of their jobs. Hazards exist in four types of general soldering and brazing processes: (1) cleaning; (2) application of flux; (3) application of heat and filler metal; and (4) residue cleaning. Most hazards during those operations can be avoided by using care, proper ventilation, protective clothing and equipment. Specific process hazards for various methods of brazing and soldering are treated. Methods to check ventilation are presented as well as a check of personal hygiene and good maintenance practices are stressed. Several emergency first aid treatments are described.

  7. Finite width coplanar waveguide patch antenna with vertical fed through interconnect

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.; Lee, Richard Q.; Shalkhauser, Kurt A.; Owens, Jonathan; Demarco, James; Leen, Joan; Sturzebecher, Dana

    1996-01-01

    The paper presents the design, fabrication and characterization of a finite width Coplanar waveguide (FCPW) patch antenna and a FCPW-to-FCPW vertical interconnect. The experimental results demonstrate the antenna and interconnect performance. A scheme to integrate an eight element FCPW patch array with MMIC phase shifters and amplifiers using vertical interconnects is described. The antenna module has potential applications in an advanced satellite to ground transmit phased array at K-Band.

  8. Scaling of Metal Interconnects: Challenges to Functionality and Reliability

    SciTech Connect

    Engelhardt, M.; Schindler, G.; Traving, M.; Stich, A.; Gabric, Z.; Pamler, W.; Hoenlein, W.

    2006-02-07

    Copper-based nano interconnects featuring CDs well beyond today's chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today's advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low-k materials. They allowed the realization of effective k-values of the insulation of 2.4, which meet requirements of chip generations far in the future, while avoiding the integration issues associated with these soft materials. First reliability results obtained with air gaps are comparable with those obtained on full structures. Whereas leakage current behavior with electrical field strength expected to be present between neighboring lines in chip generations during the next 10 years were similar for air gaps and oxide, interconnects insulated by air gaps displayed lower breakdown fields than those insulated by oxide.

  9. Chip-to-board interconnects for high-performance computing

    NASA Astrophysics Data System (ADS)

    Riester, Markus B. K.; Houbertz-Krauss, Ruth; Steenhusen, Sönke

    2013-02-01

    Super computing is reaching out to ExaFLOP processing speeds, creating fundamental challenges for the way that computing systems are designed and built. One governing topic is the reduction of power used for operating the system, and eliminating the excess heat generated from the system. Current thinking sees optical interconnects on most interconnect levels to be a feasible solution to many of the challenges, although there are still limitations to the technical solutions, in particular with regard to manufacturability. This paper explores drivers for enabling optical interconnect technologies to advance into the module and chip level. The introduction of optical links into High Performance Computing (HPC) could be an option to allow scaling the manufacturing technology to large volume manufacturing. This will drive the need for manufacturability of optical interconnects, giving rise to other challenges that add to the realization of this type of interconnection. This paper describes a solution that allows the creation of optical components on module level, integrating optical chips, laser diodes or PIN diodes as components much like the well known SMD components used for electrical components. The paper shows the main challenges and potential solutions to this challenge and proposes a fundamental paradigm shift in the manufacturing of 3-dimensional optical links for the level 1 interconnect (chip package).

  10. Manufacturing of planar ceramic interconnects

    SciTech Connect

    Armstrong, B.L.; Coffey, G.W.; Meinhardt, K.D.; Armstrong, T.R.

    1996-12-31

    The fabrication of ceramic interconnects for solid oxide fuel cells (SOFC) and separator plates for electrochemical separation devices has been a perennial challenge facing developers. Electrochemical vapor deposition (EVD), plasma spraying, pressing, tape casting and tape calendering are processes that are typically utilized to fabricate separator plates or interconnects for the various SOFC designs and electrochemical separation devices. For sake of brevity and the selection of a planar fuel cell or gas separation device design, pressing will be the only fabrication technique discussed here. This paper reports on the effect of the characteristics of two doped lanthanum manganite powders used in the initial studies as a planar porous separator for a fuel cell cathode and as a dense interconnect for an oxygen generator.

  11. Recycling of lead solder dross, Generated from PCB manufacturing

    NASA Astrophysics Data System (ADS)

    Lucheva, Biserka; Tsonev, Tsonio; Iliev, Peter

    2011-08-01

    The main purpose of this work is to analyze lead solder dross, a waste product from manufacturing of printed circuit boards by wave soldering, and to develop an effective and environmentally sound technology for its recycling. A methodology for determination of the content and chemical composition of the metal and oxide phases of the dross is developed. Two methods for recycling of lead solder dross were examined—carbothermal reduction and recycling using boron-containing substances. The influence of various factors on the metal yield was studied and the optimal parameters of the recycling process are defined. The comparison between them under the same parameters-temperature and retention time, showed that recycling of dross with a mixture of borax and boric acid in a 1:2 ratio provides higher metal yield (93%). The recycling of this hazardous waste under developed technology gets glassy slag and solder, which after correction of the chemical composition can be used again for production of PCB.

  12. IMPACT OF LEAD AND OTHER METALLIC SOLDERS ON WATER QUALITY

    EPA Science Inventory

    A study of the relationship between water quality at the consumer's taps and the corrosion of lead solder was conducted under actual field conditions in 90 homes supplied by public water in the South Huntington Water District (New York) and at l4 houses supplied by private wells ...

  13. 28. VIEW OF THE SOLDERING NICHE FORMED WITH BRICKS. THE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    28. VIEW OF THE SOLDERING NICHE FORMED WITH BRICKS. THE BACK OF THE NICHE IS CEMENT FINISHED. THE BOTTOM HAS A 1 INCH THICK ASBESTOS SHELF. THIS PHOTO WAS TAKEN AT THE 3RD FLOOR. - Pacific Telephone & Telegraph Company Building, 1519 Franklin Street, Oakland, Alameda County, CA

  14. Horizon shells and BMS-like soldering transformations

    NASA Astrophysics Data System (ADS)

    Blau, Matthias; O'Loughlin, Martin

    2016-03-01

    We revisit the theory of null shells in general relativity, with a particular emphasis on null shells placed at horizons of black holes. We study in detail the considerable freedom that is available in the case that one solders two metrics together across null hypersurfaces (such as Killing horizons) for which the induced metric is invariant under translations along the null generators. In this case the group of soldering transformations turns out to be infinite dimensional, and these solderings create non-trivial horizon shells containing both massless matter and impulsive gravitational wave components. We also rephrase this result in the language of Carrollian symmetry groups. To illustrate this phenomenon we discuss in detail the example of shells on the horizon of the Schwarzschild black hole (with equal interior and exterior mass), uncovering a rich classical structure at the horizon and deriving an explicit expression for the general horizon shell energy-momentum tensor. In the special case of BMS-like soldering supertranslations we find a conserved shell-energy that is strikingly similar to the standard expression for asymptotic BMS supertranslation charges, suggesting a direct relation between the physical properties of these horizon shells and the recently proposed BMS supertranslation hair of a black hole.

  15. Robot End Effector To Place and Solder Solar Cells

    NASA Technical Reports Server (NTRS)

    Hagerty, J. J.

    1982-01-01

    Encapsulated in robot end effector is RF induction-heating coil for heating solar cell while in transit. Holes in encapsulant permit end of unit to act as vacuum pickup to grip solar cell. Use of RF induction heating allows cell to be heated without requiring direct mechanical and thermal contact of bonding tool such as soldering iron.

  16. Inelastic Strain Analysis of Solder Joint in NASA Fatigue Specimen

    NASA Technical Reports Server (NTRS)

    Dasgupta, Abhijit; Oyan, Chen

    1991-01-01

    The solder fatigue specimen designed by NASA-GSFC/UNISYS is analyzed in order to obtain the inelastic strain history during two different representative temperature cycles specified by UNISYS. In previous reports (dated July 25, 1990, and November 15, 1990), results were presented of the elastic-plastic and creep analysis for delta T = 31 C cycle, respectively. Subsequent results obtained during the current phase, from viscoplastic finite element analysis of the solder fatigue specimen for delta T = 113 C cycle are summarized. Some common information is repeated for self-completeness. Large-deformation continuum formulations in conjunction with a standard linear solid model is utilized for modeling the solder constitutive creep-plasticity behavior. Relevant material properties are obtained from the literature. Strain amplitudes, mean strains, and residual strains (as well as stresses) accumulated due to a representative complete temperature cycle are obtained as a result of this analysis. The partitioning between elastic strains, time-independent inelastic (plastic) strains, and time-dependent inelastic (creep) strains is also explicitly obtained for two representative cycles. Detailed plots are presented for two representative temperature cycles. This information forms an important input for fatigue damage models, when predicting the fatigue life of solder joints under thermal cycling

  17. A constitutive model for Sn-Pb solder.

    SciTech Connect

    Neilsen, Michael K.; Vianco, Paul Thomas; Boyce, Brad Lee

    2010-10-01

    A unified creep plasticity damage (UCPD) model for Sn-Pb solder is developed in this paper. Stephens and Frear (1999) studied the creep behavior of near-eutectic 60Sn-40Pb solder subjected to low strain rates and found that the inelastic (creep and plastic) strain rate could be accurately described using a hyperbolic Sine function of the applied effective stress. A recently developed high-rate servo-hydraulic method was employed to characterize the temperature and strain-rate dependent stress-strain behavior of eutectic Sn-Pb solder over a wide range of strain rates (10{sup -4} to 10{sup 2} per second). The steady state inelastic strain rate data from these latest experiments were also accurately captured by the hyperbolic Sine equation developed by Stephens and Frear. Thus, this equation was used as the basis for the UCPD model for Sn-Pb solder developed in this paper. Stephens, J.J., and Frear, D.R., Metallurgical and Materials Transactions A, Volume 30A, pp. 1301-1313, May 1999.

  18. Fundamentals of wetting and spreading with emphasis on soldering

    SciTech Connect

    Yost, F.G.

    1991-01-01

    Soldering is often referred to as a mature technology whose fundamentals were established long ago. Yet a multitude of soldering problems persist, not the least of which are related to the wetting and spreading of solder. The Buff-Goodrich approach to thermodynamics of capillarity is utilized in a review of basic wetting principles. These thermodynamics allow a very compact formulation of capillary phenomena which is used to calculate various meniscus shapes and wetting forces. These shapes and forces lend themselves to experimental techniques, such as the sessile drop and the Wilhelmy plate, for measuring useful surface and interfacial energies. The familiar equations of Young, Wilhelmy, and Neumann are all derived with this approach. The force-energy duality of surface energy is discussed and the force method is developed and used to derive the Herring relations for anisotropic surfaces. The importance of contact angle hysteresis which results from surface roughness and chemical inhomogeneity is presented and Young's equation is modified to reflect these ever present effects. Finally, an analysis of wetting with simultaneous metallurigical reaction is given and used to discuss solder wetting phenomena. 60 refs., 13 figs.

  19. Aspects of short-range interconnect packaging

    NASA Astrophysics Data System (ADS)

    Wohlfeld, Denis; Brenner, Karl-Heinz

    2012-01-01

    In short-range interconnect applications, one question arises frequently: When should optical solutions be chosen over electrical wiring? The answer to this question of course depends on several factors like costs, performance, reliability, availability of testing equipment and knowledge about optical technologies, and last but not least, it strongly depends on the application itself. Networking in high performance computing (HPC) is one such example. With bit rates around 10 Gbit/s per channel and cable length above 2 m, the high attenuation of electrical cables leads to a clear preference of optical or active optical cables (AOC) for most planned HPC systems. For AOCs, the electro-optical conversion is realized inside the connector housing, while for purely optical cables, the conversion is done at the edge of the board. Proceeding to 25 Gbit/s and higher, attenuation and loss of signal quality become critical. Therefore, either significantly more effort has to be spent on the electrical side, or the package for conversion has to be integrated closer to the chip, thus requiring new packaging technologies. The paper provides a state of the art overview of packaging concepts for short range interconnects, it describes the main challenges of optical package integration and illustrates new concepts and trends in this research area.

  20. End-to-end small bowel anastomosis by temperature controlled CO2 laser soldering and an albumin stent: a feasibility study

    NASA Astrophysics Data System (ADS)

    Simhon, David; Kopelman, Doron; Hashmonai, Moshe; Vasserman, Irena; Dror, Michael; Vasilyev, Tamar; Halpern, Marissa; Kariv, Naam; Katzir, Abraham

    2004-07-01

    Introduction: A feasibility study of small intestinal end to end anastomosis was performed in a rabbit model using temperature controlled CO2 laser system and an albumin stent. Compared with standard suturing or clipping, this method does not introduce foreign materials to the repaired wound and therefore, may lead to better and faster wound healing of the anastomotic site. Methods: Transected rabbits small intestines were either laser soldered using 47% bovine serum albumin and intraluminal albumin stent or served as controls in which conventional continuous two-layer end to end anastomosis was performed manually. The integrity of the anastomosis was investigated at the 14th postoperative day. Results: Postoperative course in both treatments was uneventful. The sutured group presented signs of partial bowel obstruction. Macroscopically, no signs of intraluminal fluid leakage were observed in both treatments. Yet, laser soldered intestinal anastomoses demonstrated significant superiority with respect to adhesions and narrowing of the intestinal lumen. Serial histological examinations revealed better wound healing characteristics of the laser soldered anastomotic site. Conclusion: Laser soldering of intestinal end to end anastomosis provide a faster surgical procedure, compared to standard suture technique, with better wound healing results. It is expected that this technique may be adopted in the future for minimal invasive surgeries.

  1. Optical interconnections and networks; Proceedings of the Meeting, The Hague, Netherlands, Mar. 14, 15, 1990

    NASA Technical Reports Server (NTRS)

    Bartelt, Hartmut (Editor)

    1990-01-01

    The conference presents papers on interconnections, clock distribution, neural networks, and components and materials. Particular attention is given to a comparison of optical and electrical data interconnections at the board and backplane levels, a wafer-level optical interconnection network layout, an analysis and simulation of photonic switch networks, and the integration of picosecond GaAs photoconductive devices with silicon circuits for optical clocking and interconnects. Consideration is also given to the optical implementation of neural networks, invariance in an optoelectronic implementation of neural networks, and the recording of reversible patterns in polymer lightguides.

  2. Technology, science, and environtmental impact of a novel Cu-Ag core-shell solderless interconnect system

    NASA Astrophysics Data System (ADS)

    Kammer, Milea Joy

    Tin-based solder is ubiquitous in microelectronics manufacturing and plays a critical role in electronic packaging and attachment. While manufacturers of consumer electronics have made the transition to the use of lead-free solder, there are still a variety of reliability issues associated with these lead-free alternatives, particularly for high performance, high reliability applications. Because of these performance short-comings, researchers are still searching for a material, an alloy, or a unique alternative that can meet the thermal, mechanical, and electrical requirements for conventional reflow solder applications. In an effort to produce a more reliable alternative, Kim et al. proposed the low-temperature (200°C) sintering of copper-silver core-shell particles as a viable solderless interconnect technology. This technology is based on the silver atoms from the shell diffusing by surface diffusion to form sintered necks between copper particles, and therefore dewetting most of the copper surfaces. This study presents a 3-fold, in-depth evaluation of this Cu-Ag core-shell lead-free solderless interconnect technology focusing on solder paste development and prototyping, silver thin film stress relaxation and dewetting kinetics, and the environmental impacts associated with this new technology. First, an evaluation of the starting particle consistency and sintered compact mechanical properties determined that a specific core-shell particle geometry (1microm average core diameter and 10nm shell thickness) outperformed other combinations, exhibiting the highest modulus and yield strengths in sintered compacts, of 620 MPa and 40-60 MPa respectively. In particular, yield strengths for sintered compacts are similar to those reported for Sn-3.5Ag-0.75Cu (a commonly used lead-free solder) for the same strain rate. Following particle evaluations, the development of a functioning flux formulation was a key factor in the creation of a viable drop-in replacement. The

  3. Wettability and Reaction between Solder and Silver Busbar during the Tabbing Process for Silicon Photovoltaic Modules

    NASA Astrophysics Data System (ADS)

    Lee, Beom-Yong; Hoang, Thi-Lien; Cho, Sung-Bin; Huh, Joo-Youl; Lee, Young-Sik

    2012-10-01

    The soldering quality of a Cu ribbon onto the Ag busbars of solar cells is one of the key factors affecting the cell-to-module loss and durability of a silicon photovoltaic module. In this study, we examined the effects of the surface chemistry and morphology of the screen-printed Ag busbars on the solder wettability and bonding uniformity of the Cu ribbon over the length of the busbar during the tabbing process. The surface of the as-fired Ag busbar was covered by a thin glass layer originating from the glass frit contained in the Ag paste. The presence of the thin glass layer significantly decreased the wettability of the solder, leading to the formation of voided regions at the solder/busbar interface. Although it had only a minor influence on solder wettability, increasing the roughness of the busbar surface resulted in the formation of more voided regions at the solder/busbar interface.

  4. Threshold current density of electromigration in eutectic SnPb solder

    SciTech Connect

    Yeh, Y.T.; Chou, C.K.; Hsu, Y.C.; Chen Chih; Tu, K.N.

    2005-05-16

    Electromigration has emerged as an important reliability issue in the microelectronics packaging industry since the dimension of solder joints has continued to shrink. In this letter, we report a technique that enables the precise measurement of the important parameters of solder electromigration, such as activation energy, critical length, threshold current density, effective charge numbers, and electromigration rate. Patterned Cu/Ti films in a Si trench were employed for eutectic SnPb solder to be reflowed on, and thus solder Blech specimens were fabricated. Atomic force microscope was used to measure the depletion volume caused by electromigration on the cathode end. The threshold current density is estimated to be 8.5x10{sup 3} A/cm{sup 2} at 100 deg. C, which relates directly to the maximum allowable current that a solder joint can carry without electromigration damage. This technique facilitates the scientifically systematic investigation of electromigration in solders.

  5. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  6. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  7. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  8. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  9. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  10. Impact of Cu/low-k Interconnect Design on Chip Package Interaction in Flip Chip Package

    NASA Astrophysics Data System (ADS)

    Uchibori, C. J.; Lee, Michael; Zhang, Xuefeng; Ho, P. S.; Nakamura, T.

    2009-06-01

    The impacts of Cu/low-k interconnect structures and solder bump layouts on Chip Package Interaction (CPI) in Flip Chip Ball Grid Array (FCBGA) was investigated. The energy release rates (ERR) that indicate the driving force for delamination were calculated to evaluate the impact of CPI on mechanical reliability of Cu/low-k in FCBGA. First, two metal layer interconnect structure was modeled to find the effects of the mechanical properties of inter layer dielectric (ILD) materials on ERR. The ERR was found to increase rapidly when the modulus of ILD is lower than 10 GPa. Then the number of the interconnect layer was increased to four to find the impact of wiring dimensions on CPI. The ERR at the upper interface were consistently higher than those of lower interface. However, when TEOS is used for M4 level, low-k is used for M3 and Ultra low-k is used for M2 and M1 level, the ERR at M3 level becomes higher than that at M4 level. The wiring dimension and mechanical properties of ILD were found to be important in controlling CPI. Then the number of interconnect layer was increased to seven and nine layers where the dimension was determined by 65 nm technology rule. The ERR increased with increasing the crack length which indicates that the crack will keep growing when it generates. Finally, arranging the dummy bump was found to be effective to reduce the peeling stress at outermost bump. Then, the impact of interconnect design and material properties of ILD on CPI will be discussed.

  11. National Offshore Wind Energy Grid Interconnection Study

    SciTech Connect

    Daniel, John P.; Liu, Shu; Ibanez, Eduardo; Pennock, Ken; Reed, Greg; Hanes, Spencer

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States. A total of 54GW of offshore wind was assumed to be the target for the analyses conducted. A variety of issues are considered including: the anticipated staging of offshore wind; the offshore wind resource availability; offshore wind energy power production profiles; offshore wind variability; present and potential technologies for collection and delivery of offshore wind energy to the onshore grid; potential impacts to existing utility systems most likely to receive large amounts of offshore wind; and regulatory influences on offshore wind development. The technologies considered the reliability of various high-voltage ac (HVAC) and high-voltage dc (HVDC) technology options and configurations. The utility system impacts of GW-scale integration of offshore wind are considered from an operational steady-state perspective and from a regional and national production cost perspective.

  12. Low-temperature sintering of nanoscale silver paste for semiconductor device interconnection

    NASA Astrophysics Data System (ADS)

    Bai, Guofeng

    This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of low-temperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ˜80% bulk density at temperatures no more than 300°C. It has been found that the low-temperature sintered silver has better electrical, thermal and overall thermomechanical properties compared with the existing semiconductor device interconnecting materials such as solder alloys and conductive epoxies. After solving the organic burnout problems associated with the covered sintering, a lead-free semiconductor device interconnect technology has been designed to be compatible with the existing surface-mounting techniques with potentially low-cost. It has been found that the low-temperature sintered silver joints have high electrical, thermal, and mechanical performance. The reliability of the silver joints has also been studied by the 50-250°C thermal cycling experiment. Finally, the bonging strength drop of the silver joints has been suggested to be ductile fracture in the silver joints as micro-voids nucleated at microscale grain boundaries during the temperature cycling. The low-temperature silver sintering technology has enabled some benchmark packaging concepts and substantial advantages in future applications.

  13. A comparison of new thick photoresists for solder bumping

    NASA Astrophysics Data System (ADS)

    Flack, Warren W.; Nguyen, Ha-Ai; Neisser, Mark; Sison, Ernesto; Lu, Ping Hung; Plass, Bob; Makii, Toshimichi; Murakami, Yoshio

    2005-05-01

    The performance requirements for ultra-thick photoresists are rapidly increasing with the dramatic growth in lithographic applications that require electroplating processes. Two of the main applications for ultra-thick photoresists are advanced packaging and nanotechnology (MEMS). Flipchip packaging has become widely adopted to address electrical device performance and chip form factor considerations. The growth in the nanotechnology market is driven by a wide range of products, which include accelerometers, ink jet print heads, biomedical sensors and optical switches. The requirements of thick photoresists for solder electroplating are significantly different from typical thin photoresists used in front end of line applications. As the photoresist becomes thicker, processing times increase for many process steps. Photospeed gets slower due to the requirements for more chemical reactions per area of coating. Coating uniformity and edge bead control also become more difficult as photoresist films get thicker and time delay issues between process steps can arise. This result has led to the requirement for special photoresist formulations for thick photoresist films. These are traditionally positive tone DNQ-Novolak materials such as AZ 50XT. Such materials can be designed to work for a particular range of thicknesses, but as the desired thicknesses increases the processing times can become very long for high volume manufacturing. Many new bumping schemes require photoresists in a 60 to 70 μm thickness range. While DNQ-Novolak chemistry can work, there is a desire for faster alternatives to improve total cost of ownership (COO) of the lithography cell. In order to have fast photospeeds and reasonable processing times a chemistry that is very photo efficient is needed. Negative tone cross linking chemistries, which can give tens of thousands of chemical events for one photochemical event, provide excellent photospeed and process times. Positive tone chemically

  14. Formation of interconnections to microfluidic devices

    DOEpatents

    Matzke, Carolyn M.; Ashby, Carol I. H.; Griego, Leonardo

    2003-07-29

    A method is disclosed to form external interconnections to a microfluidic device for coupling of a fluid or light or both into a microchannel of the device. This method can be used to form optical or fluidic interconnections to microchannels previously formed on a substrate, or to form both the interconnections and microchannels during the same process steps. The optical and fluidic interconnections are formed parallel to the plane of the substrate, and are fluid tight.

  15. Polyguide polymeric technology for optical interconnect circuits and components

    NASA Astrophysics Data System (ADS)

    Booth, Bruce L.; Marchegiano, Joseph E.; Chang, Catherine T.; Furmanak, Robert J.; Graham, Douglas M.; Wagner, Richard G.

    1997-04-01

    The expanding information revolution has been made possible by the development of optical communication technology. To meet the escalating demand for information transmitted and processed at high data rates and the need to circumvent the growing electronic circuit bottlenecks, mass deployment of not only optical fiber networks but manufacturable optical interconnect circuits, components and connectors for interfacing fibers and electronics that meet economic and performance constraints are absolutely necessary. Polymeric waveguide optical interconnection are considered increasingly important to meet these market needs. DuPont's polyguide polymeric integrated optic channel waveguide system is thought by many to have considerable potential for a broad range of passive optical interconnect applications. In this paper the recent advances, status, and unique attributes of the technology are reviewed. Product and technology developments currently in progress including parallel optical ink organization and polymer optical interconnect technology developments funded by DARPA are used as examples to describe polyguide breadth and potential for manufacture and deployment of optical interconnection products for single and multimode telecom and datacom waveguide applications.

  16. Detecting nonuniformity in small welds and solder seams using optical correlation and electronic processing.

    PubMed

    Wagner, J W

    1981-10-15

    Using holographic matched filtering and electronic processing, small variations in surface displacement along the seam of a hermetic microcircuit package can be detected when the seam is stressed. Destructive analysis of a solder-sealed package reveals a strong correlation between optical signal variations and nonuniformity of solder adhesion and wetting along the seam. The technique promises potential application as a means of nondestructively inspecting for flaws in small welded or soldered seams. PMID:20372226

  17. Conversion from solvent rinsable fluxes to aqueous rinsable fluxes for hot oil solder leveling

    NASA Astrophysics Data System (ADS)

    1992-03-01

    A water rinsable flux was evaluated for hot oil solder leveling of printed wiring boards. The previously used rosin-activated flux required a solvent containing a chlorinated hydrocarbon for removing the flux residues after soldering. The water rinsable flux requires hot water or a solution of hot detergent for removing flux residues after smoldering. The water rinsable flux produced an acceptable soldered surface. Flux residues were removed by either hot water (120 F) or a solution of hot detergent (120 F).

  18. 3D FEM Simulations of Drop Test Reliability on 3D-WLP: Effects of Solder Reflow Residual Stress and Molding Resin Parameters

    NASA Astrophysics Data System (ADS)

    Belhenini, Soufyane; Tougui, Abdellah; Bouchou, Abdelhake; Mohan, Ranganathan; Dosseul, Franck

    2014-01-01

    Numerous three-dimensional (3D) packaging technologies are currently used for 3D integration. 3D-wafer level package (3D-WLP) appears to be a way to keep increasing the density of the microelectronic components. The reliability of 3D components has to be evaluated on mechanical demonstrators with daisy chains before real production. Numerical modeling is acknowledged as a very efficient tool for design optimization. In this paper, 3D finite-elements calculations are carried out to analyze the effects of molding resin's mechanical properties and thickness on the 3D component's dynamic response under drop loading conditions. Residual stress generated by solder reflow is also discussed. The influences of residual stresses on the numerical estimation of the component behavior during drop loading are studied. Solder reflow residual stresses have an impact on solder plastic strain and die equivalent stress calculations. We have compared the result of two numerical drop test models. Stress-free initial conduction is introduced for the first model. Solder reflow residual stresses are considered as the initial condition for the second drop test model. Quantitative and qualitative comparisons are carried out to show the effect of residual stress in drop test calculations. For the effect of molding resin thickness on the component behavior under drop loading, the stress-free initial condition is considered. The effect of the molding resin's thickness on critical area location is discussed. The solder bump maximum plastic shear strain and the silicon die maximum equivalent stress are used as reliability criteria. Numerical submodeling techniques are used to increase calculation accuracy. Numerical results have contributed to the design optimization of the 3D-WLP component.

  19. 18 CFR 292.306 - Interconnection costs.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 18 Conservation of Power and Water Resources 1 2010-04-01 2010-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any...

  20. 47 CFR 90.477 - Interconnected systems.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 47 Telecommunication 5 2014-10-01 2014-10-01 false Interconnected systems. 90.477 Section 90.477 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES PRIVATE LAND MOBILE RADIO SERVICES Transmitter Control Interconnected Systems § 90.477 Interconnected systems. (a) Applicants for new land stations to...

  1. 47 CFR 90.477 - Interconnected systems.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 47 Telecommunication 5 2013-10-01 2013-10-01 false Interconnected systems. 90.477 Section 90.477 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES PRIVATE LAND MOBILE RADIO SERVICES Transmitter Control Interconnected Systems § 90.477 Interconnected systems. (a) Applicants for new land stations to...

  2. 47 CFR 90.477 - Interconnected systems.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 47 Telecommunication 5 2011-10-01 2011-10-01 false Interconnected systems. 90.477 Section 90.477... MOBILE RADIO SERVICES Transmitter Control Interconnected Systems § 90.477 Interconnected systems. (a... switched telephone network only after modifying their license. See § 1.929 of this chapter. In all cases...

  3. 47 CFR 90.477 - Interconnected systems.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 47 Telecommunication 5 2010-10-01 2010-10-01 false Interconnected systems. 90.477 Section 90.477... MOBILE RADIO SERVICES Transmitter Control Interconnected Systems § 90.477 Interconnected systems. (a... switched telephone network only after modifying their license. See § 1.929 of this chapter. In all cases...

  4. 18 CFR 292.306 - Interconnection costs.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 18 Conservation of Power and Water Resources 1 2012-04-01 2012-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any...

  5. 18 CFR 292.306 - Interconnection costs.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 18 Conservation of Power and Water Resources 1 2013-04-01 2013-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any...

  6. 47 CFR 51.305 - Interconnection.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 47 Telecommunication 3 2011-10-01 2011-10-01 false Interconnection. 51.305 Section 51.305 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) COMMON CARRIER SERVICES (CONTINUED) INTERCONNECTION Additional Obligations of Incumbent Local Exchange Carriers § 51.305 Interconnection. (a) An incumbent LEC shall provide, for the...

  7. 47 CFR 51.305 - Interconnection.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 47 Telecommunication 3 2013-10-01 2013-10-01 false Interconnection. 51.305 Section 51.305 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) COMMON CARRIER SERVICES (CONTINUED) INTERCONNECTION Additional Obligations of Incumbent Local Exchange Carriers § 51.305 Interconnection. (a) An incumbent LEC shall provide, for the...

  8. 47 CFR 51.305 - Interconnection.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 47 Telecommunication 3 2014-10-01 2014-10-01 false Interconnection. 51.305 Section 51.305 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) COMMON CARRIER SERVICES (CONTINUED) INTERCONNECTION Additional Obligations of Incumbent Local Exchange Carriers § 51.305 Interconnection. (a) An incumbent LEC shall provide, for the...

  9. 47 CFR 51.305 - Interconnection.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 47 Telecommunication 3 2012-10-01 2012-10-01 false Interconnection. 51.305 Section 51.305 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) COMMON CARRIER SERVICES (CONTINUED) INTERCONNECTION Additional Obligations of Incumbent Local Exchange Carriers § 51.305 Interconnection. (a) An incumbent LEC shall provide, for the...

  10. 14 CFR 29.674 - Interconnected controls.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Interconnected controls. 29.674 Section 29... Interconnected controls. Each primary flight control system must provide for safe flight and landing and operate independently after a malfunction, failure, or jam of any auxiliary interconnected control....

  11. 14 CFR 27.674 - Interconnected controls.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Interconnected controls. 27.674 Section 27... Interconnected controls. Each primary flight control system must provide for safe flight and landing and operate independently after a malfunction, failure, or jam of any auxiliary interconnected control....

  12. Microstructural Evolution and Mechanical Properties in (AuSn)eut-Cu Interconnections

    NASA Astrophysics Data System (ADS)

    Dong, Hongqun; Vuorinen, Vesa; Laurila, Tomi; Paulasto-Kröckel, Mervi

    2016-06-01

    The interfacial reactions between the widely employed solder Au-20wt.%Sn and the common contact metallizations (e.g. Ni, Cu and Pt) are normally complex and not well determined. In order to identify the proper contactor for Au-20wt.%Sn solder, the present study focuses on (1) rationalizing the interfacial reaction mechanisms of Au-20wt.%Sn|Cu as well as (2) measuring the mechanical properties of individual intermetallics formed at the interface. The evolution of interfacial reaction products were rationalized by using the experimental results in combination with the calculated Au-Cu-Sn phase diagram information. It was found that the growth of the AuCu interfacial intermetallic layer was diffusion-controlled. The diffusion path of Au-20wt.%Sn|Cu at 150°C was proposed. The hardness and indentation modulus of the interfacial reaction products were measured using nanoindentation tests. The results revealed a significant influence of the Cu solubility on the mechanical properties of (Au,Cu)Sn and (Au,Cu)5Sn, i.e. their hardness and contact modulus increased with the increase in the amount of Cu. Furthermore, results obtained here for the Au-20wt.%Sn|Cu joints were compared to those from Au-20wt.%Sn|Ni in order to assess the similarities and differences between these widely used interconnection metallization systems.

  13. Automated inspection of solder joints for surface mount technology

    NASA Technical Reports Server (NTRS)

    Savage, Robert M.; Park, Hyun Soo; Fan, Mark S.

    1993-01-01

    Researchers at NASA/GSFC evaluated various automated inspection systems (AIS) technologies using test boards with known defects in surface mount solder joints. These boards were complex and included almost every type of surface mount device typical of critical assemblies used for space flight applications: X-ray radiography; X-ray laminography; Ultrasonic Imaging; Optical Imaging; Laser Imaging; and Infrared Inspection. Vendors, representative of the different technologies, inspected the test boards with their particular machine. The results of the evaluation showed limitations of AIS. Furthermore, none of the AIS technologies evaluated proved to meet all of the inspection criteria for use in high-reliability applications. It was found that certain inspection systems could supplement but not replace manual inspection for low-volume, high-reliability, surface mount solder joints.

  14. Automated inspection of solder joints for surface mount technology

    NASA Astrophysics Data System (ADS)

    Savage, Robert M.; Park, Hyun Soo; Fan, Mark S.

    1993-03-01

    Researchers at NASA/GSFC evaluated various automated inspection systems (AIS) technologies using test boards with known defects in surface mount solder joints. These boards were complex and included almost every type of surface mount device typical of critical assemblies used for space flight applications: X-ray radiography; X-ray laminography; Ultrasonic Imaging; Optical Imaging; Laser Imaging; and Infrared Inspection. Vendors, representative of the different technologies, inspected the test boards with their particular machine. The results of the evaluation showed limitations of AIS. Furthermore, none of the AIS technologies evaluated proved to meet all of the inspection criteria for use in high-reliability applications. It was found that certain inspection systems could supplement but not replace manual inspection for low-volume, high-reliability, surface mount solder joints.

  15. Application of CO2 laser for electronic components soldering

    NASA Astrophysics Data System (ADS)

    Mascorro-Pantoja, J.; Soto-Bernal, J. J.; Nieto-Pérez, M.; Gonzalez-Mota, R.; Rosales-Candelas, I.

    2011-10-01

    Laser provides a high controllable and localized spot for soldering joint formation and this is a valuable tool in Sn/Pb Soldering process on electronic industry, in recent years, laser beam welding has become an emerging welding technique, the use of laser in welding area is a high efficiency method. A 60 Watts CO2 continuous laser was used on this study, during welding experimental results indicated the laser could significantly improve speed and weld quality. In this work, the welding interactions of CO2 laser with Sn/Pb wire have been investigated in details through varying the energy ratios of laser. And at the same time, the effect of distance from laser spot to material.

  16. Role of Ag in the formation of interfacial intermetallic phases in Sn-Zn soldering

    NASA Astrophysics Data System (ADS)

    Song, Jenn-Ming; Liu, Pei-Chi; Shih, Chia-Ling; Lin, Kwang-Lung

    2005-09-01

    This study explored the effect of Ag as the substrate or alloying element of solders on the interfacial reaction in Sn-Zn soldering. Results show that instead of Ag-Sn compounds, ζ-AgZn and γ-Ag5Zn8 form at the Sn-Zn/Ag interface. The addition of Ag in Sn-Zn solders leads to the precipitation of ɛ-AgZn3 from the liquid solder on preformed interfacial intermetallics. The morphology of this additional AgZn3 is closely related to the solidification process of Ag-Zn intermetallics and the under intermetallic layer.

  17. Solder joint fatigue analysis under low temperature Martian conditions

    NASA Technical Reports Server (NTRS)

    Tudryn, Carissa

    2006-01-01

    Electronics, without requiring heater power or enclosure in a centralized 'warm electronics box,' will need to survive mean surface temperatures of -120 degrees Celsius to +20 degrees Celsius for an extended Martian mission and an operational temperature up to 85 degrees Celsisus. Since these electronics will need to survive extended cycles under these conditions, fatigue is a significant concern. The solder joint reliability of connectors on a printed wiring board was investigated.

  18. Predicted ball grid array thermal response during reflow soldering

    SciTech Connect

    Voth, T.E.; Bergman, T.L.

    1995-12-31

    A numerical model is developed to predict the detailed thermomechanical response of a BGA assembly during reflow soldering. The governing coupled solid mechanics and heat diffusion equations are solved using a commercially available finite element package. Reported predictions illustrate the system`s sensitivity to both thermal and mechanical processing conditions, as well as component thermal properties. Specifically, assemblies with components of high thermal conductivity show the greatest sensitivity to mechanical loading conditions.

  19. Mechanisms of Soldering Formation on Coated Core Pins

    NASA Astrophysics Data System (ADS)

    Song, Jie; Denouden, Tony; Han, Qingyou

    2012-02-01

    Die soldering is one of the major casting defects during the high-pressure die casting (HPDC) process, causing dimensional inaccuracy of the castings and increased downtimes of the HPDC machine. In this study, we analyzed actually failed core pins to determine the mechanism of soldering and its procedures. The results show that the soldering process starts from a local coating failure, involves a series of intermetallic phase formation from reactions between molten aluminum alloys and the H13 steel pin, and accelerates when an aluminum-rich, face-centered cubic (fcc) phase is formed between the intermetallic phases. It is the formation of the aluminum-rich fcc phase in the reaction region that joins the core pin with the casting, resulting in the sticking of the casting to the core pin. When undercuts are formed on the core pin, the ejection of castings from the die will lead to either a core pin failure or damages to the casting being ejected.

  20. Layer growth in Au-Pb/In solder joints

    SciTech Connect

    Yost, F.G.; Ganyard, F.P.; Karnowsky, M.M.

    1986-01-01

    The solid state reaction between a Pb-In solder alloy and thin film Au has been investigated at ten aging temperatures ranging from 70 to 170/sup 0/C. Also, bulk Au-solder samples were aged at 150/sup 0/C for metallographic analysis. No significant difference was found between the aging behavior of thin and bulk Au specimens. A thin single phase layer of Au/sub 9/In/sub 4/ was found adjacent to Au while a thick two-phase layer of AuIn/sub 2/ and Pb was found between Au/sub 9/In/sub 4/ and solder. The Pb phase was shown to have considerable mobility and able to ripen at room temperature. Peculiar planar interface instabilities and voids in the Au-Au/sub 9/In/sub 4/ interface were found. The total layer thickness was found to vary linearly with aging time, indicating an interface-controlled reaction. An activation energy of 14,000 calories per mole was found by regression analysis of the kinetic data.