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1

Transistor Level Reliability Estimation of Integrated Circuits  

NASA Astrophysics Data System (ADS)

The history of semiconductor chips has been characterized by a steady growth in the level of integration. Although this growth has given computer designers more capable circuits, it has become increasingly difficult to design highly reliable circuits. Until now, the reliability of semiconductor chips has been parametrized by the logic family; the operating voltage, temperature, and environment; and the level of integration of the component. Thus, to obtain highly reliable systems, it was often necessary to limit the number of transistors. An attractive and potentially important extension to the analysis of circuit reliability is to account for the connectivity of the individual internal components. For circuits in complementary metal oxide silicon (CMOS) technology, this reliability analysis is accomplished by modeling open and shorted transistors, "stuck-at" wires, and failed power and ground sources. Direct analysis of the reliability of a circuit by exhaustive enumeration of all fault combinations is prohibitive, however, due to the exponential growth of the number of states in circuits. A tractable approach for digital systems, that includes all transistor level faults and calculates the reliability of combinational circuits exactly, can be based on a hierarchical decomposition of the circuit into manageable sub-units. For each level of the hierarchy, units are simulated exhaustively and critical statistical data are gathered. At the highest level, the resulting statistical data are combined to generate the exact probability of correct operation for the whole circuit. Analysis of the reliability of a set of fault tolerant gates with this hierarchical approach illustrates that redundancy techniques alone are not successful at increasing circuit reliability; each section of the circuit that is modified must be replaced with a structure with higher reliability. Analysis of a triple modular redundancy system shows that single point and double point failures must be included in the analysis to ensure numerical precision. Considering higher multiplicities of failures is not critical because the probability of such fault configurations is typically insignificant.

Holmann, Edgar

1995-01-01

2

Integrated logic circuits using single-atom transistors.  

PubMed

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

2011-08-23

3

Heterostructure bipolar transistors and integrated circuits  

Microsoft Academic Search

A bipolar transmitter with a wide-gap emitter is presented. Examples of heterostructure implementations of IIL and ECL are discussed, and future device possibilities based on technological premises are considered. The concept and high-speed benefits of the widegap emitter are reviewed, including recent conceptual developments such as an inverted transistor design in which the collector is made smaller than the emitter

HERBERT KROEMER

1982-01-01

4

Integrated circuits based on bilayer MoS? transistors.  

PubMed

Two-dimensional (2D) materials, such as molybdenum disulfide (MoS(2)), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS(2) allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene's advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS(2) show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS(2) to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between 2 to 12 transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS(2). Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions. PMID:22862813

Wang, Han; Yu, Lili; Lee, Yi-Hsien; Shi, Yumeng; Hsu, Allen; Chin, Matthew L; Li, Lain-Jong; Dubey, Madan; Kong, Jing; Palacios, Tomas

2012-09-12

5

Total dose effects in conventional bipolar transistors and linear integrated circuits  

Microsoft Academic Search

Total dose damage is investigated for discrete bipolar transistors and linear integrated circuits that are fabricated with older processing technologies, but are frequently used in space applications. The Kirk effect limits the current density of discrete transistors with high collector breakdown voltage, increasing their sensitivity to ionizing radiation because they must operate low injection levels. Bias conditions during irradiation had

A. H. Johnston; G. M. Swift; B. G. Rax

1994-01-01

6

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors  

NASA Astrophysics Data System (ADS)

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22?cm2?V-1?s-1, current modulation >106 and subthreshold swing of 0.28?V?dec-1. We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Kim, David K.; Lai, Yuming; Diroll, Benjamin T.; Murray, Christopher B.; Kagan, Cherie R.

2012-11-01

7

CMOS-based carbon nanotube pass-transistor logic integrated circuits  

PubMed Central

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

8

Proton Irradiation Effects in Mos and Junction Field-Effect Transistors and Integrated Circuits  

Microsoft Academic Search

Because of the application of field-effect transistors, and integrated circuits in space electronic systems and the fact that proton irradiation data at energies typical of a space environment are not extensive, an experimental evaluation of these devices has been conducted. Thee important electrical parameters of these devices were measured before, during, and after irradiation at the Oak Ridge National Laboratory's

Floyd R. Bryant; Carl L. Fales; Roger A. Breckenridge

1966-01-01

9

Radiation effects on bipolar junction transistors and integrated circuits produced by different energy Br ions  

Microsoft Academic Search

The radiation responses of the NPN bipolar junction transistors (BJTs) and the TTL bipolar integrated circuits (ICs) have been examined using 20, 40 and 60MeV Br ions. Key electric parameter was measured and compared after each energy irradiation. Experimental results demonstrate that the degradation in electric parameters caused by the Br ions shows a common feature for the NPN BJTs

Xingji Li; Hongbin Geng; Chaoming Liu; Zhiming Zhao; Mujie Lan; Dezhuang Yang; Shiyu He

2009-01-01

10

Large-scale complementary integrated circuits based on organic transistors  

Microsoft Academic Search

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of

B. Crone; A. Dodabalapur; Y.-Y. Lin; R. W. Filas; Z. Bao; A. Laduca; R. Sarpeshkar; H. E. Katz; W. Li

2000-01-01

11

Organic thin-film transistors, integrated circuits, and light-emitting diodes  

NASA Astrophysics Data System (ADS)

This thesis reports high-performance organic thin film transistors on glass substrates and the fastest all-organic integrated circuits reported to date. In addition, a novel fully integrated all-organic light emitting diode/thin film transistor active pixel is reported. The process technology necessary to fabricate organic thin film transistors on arbitrary substrates was developed. Using the small-molecule hydrocarbon pentacene as the active material, thin film transistors were fabricated with field-effect mobility as large as 0.6 cm2/V-s, on/off current ratio as large as 108, and subthreshold slope as small as 0.7 V/decade. Building on the discrete thin film transistor results, simple pentacene integrated circuits were fabricated on glass substrates. Integrated level shifting was used with normally-on transistors and resulted in circuits with sub-75-musec propagation delay per inverter stage (measured using ring oscillators). These are the fastest all-organic integrated circuits reported to date. The low current level chosen for the level shifting limits the performance of these circuits; directly driven inverters have switching rise and fall time constants below 1 musec. A low-temperature, oxygen-free transparent contact was developed and used to fabricate organic thin film light emitting diodes. This contact avoids the possibility of oxygen injection into the organic active layer as can occur when conventional conductive metal oxide transparent contacts are used. In addition, metal oxide contacts require elevated process temperatures that are incompatible with inexpensive polymeric substrates. The low-temperature transparent contact uses an ultra-thin metal film deposited by ion-beam sputtering. Such films can have remarkably small surface roughness (typically near 1 A RMS) and become continuous and conductive at film thickness that allows more than 70% optical transmission. Using transparent palladium and aluminum contacts, organic light emitting diodes were fabricated using the small-molecule electroluminescent material 8-hydroxyquinoline aluminum and the small-molecule holetransport material tetraphenyldiamine for the organic active layers. Finally, a novel fully integrated all-organic active-matrix emissive pixel was developed. This all-organic active pixel uses a gate-controlled organic semiconductor layer to control carrier injection into the electroluminescent device and may provide important contact advantages in addition to a simplified organic light emitting diode/organic thin film transistor control structure.

Klauk, Hagen

1999-11-01

12

Silicon-on-insulator (SOI) integration for organic field effect transistor (OFET) based circuits  

Microsoft Academic Search

In this paper, we report the first silicon-on-insulator (SOI) integration technique for organic field effect transistor (OFET) based circuits. Proposed design flow relies on only basic micro-fabrication processes such as photolithography and physical vapor deposition. This novel fabrication technique allows patterning of conductive silicon gate islands on the subtrate and eases the via and interconnect patterning and deposition for a

Recep Ozgun; Byung J. Jung; Bal M. Dhar; Howard E. Katz; Andreas G. Andreou

2011-01-01

13

Organic field-effect transistors and all-polymer integrated circuits  

Microsoft Academic Search

Electrical properties of field-effect transistors made of different solution processable organic semiconductors are described. The temperature and gate-voltage dependence of the mobility is shown and theoretically described using a model based on the variable-range hopping of charge carriers in an exponential density of states. Furthermore, a technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of

M. Matters; D. M. de Leeuw; M. J. C. M. Vissenberg; C. M. Hart; P. T. Herwig; T. Geuns; C. M. J. Mutsaers; C. J. Drury

1999-01-01

14

SEMICONDUCTOR INTEGRATED CIRCUITS: A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology  

NASA Astrophysics Data System (ADS)

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 ?m CMOS technology. This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics. At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor, a flexible logic circuit is realized in this work, which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor. It turns out that MOS-NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.

Wei, Wang; Beiju, Huang; Zan, Dong; Weilian, Guo; Hongda, Chen

2010-05-01

15

Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies  

SciTech Connect

Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q. [Sandia National Labs., Albuquerque, NM (United States); Enquist, P.M. [Research Triangle Inst., Research Triangle Park, NC (United States)

1995-12-31

16

Pentacene thin film transistors and inverter circuits  

Microsoft Academic Search

Organic thin film transistors and simple electronic circuits have been fabricated using the fused-ring small-molecule aromatic hydrocarbon pentacene as the active material. Carrier field-effect mobilities greater than 0.2 cm2\\/V-s were obtained for thin film transistors fabricated on glass using low-temperature ion-beam deposited silicon dioxide as the gate dielectric and thermally evaporated pentacene as the active material. Using similar transistors, integrated

Hagen Klauk; Yen-Yi Lin; David J. Gundlach; Thomas N. Jackson

1997-01-01

17

Transistor sizing in CMOS circuits  

Microsoft Academic Search

The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

Mehmet A. Cirit

1987-01-01

18

A spiking neuron circuit based on a carbon nanotube transistor  

NASA Astrophysics Data System (ADS)

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions.

Chen, C.-L.; Kim, K.; Truong, Q.; Shen, A.; Li, Z.; Chen, Y.

2012-07-01

19

Polymer electronics: from discrete transistors to integrated circuits and active matrix displays  

Microsoft Academic Search

Transistors based on organic materials are lightweight, flexible, and potentially easy to manufacture. Since the temperature used in the production process is low, the substrate can be cheap and flexible plastic instead of glass. Still plastic transistors offer less performance than most of their inorganic counterparts. In order to fully exploit the potential of organic devices, the process technology must

E. Cantatore; G. H. Gelinck; D. M. de Leeuw

2002-01-01

20

Complementary GaAs junction-gated heterostructure field effect transistor fabrication for integrated circuits  

SciTech Connect

A new GaAs junction-gated complementary logic technology that integrates a modulation doped p-channel heterostructure field effect transistor (pHFET) and a fully ion implanted n-channel JFET has recently been fabricated. High-speed, low-power operation has been demonstrated with loaded ring oscillators that show gate delays of 179 ps/stage for a power-delay product of 28 fJ at 1.2 V operation and 320 ps/stage and 8.9 fJ at 0.8 V operation. The principal advantages of this technology include the ability to independently set the threshold voltage of n- and p-channel devices and to independently design the pHFET for high performance. A self-aligned refractory gate process based on tungsten and tungsten silicide gate metal has been used to fabricate the FETs. Novel aspects of the fabrication include the simultaneous formation of non-alloyed, refractory ohmic contacts for the junction gates and the formation of shallow p-n junctions by ion implantation.

Baca, A.G.; Zolper, J.C.; Sherwin, M.E.; Robertson, P.J.; Shul, R.J.; Howard, A.J.; Rieger, D.J.; Klem, J.F.

1994-10-01

21

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits  

Microsoft Academic Search

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors

Sotoudeh Hamedi-Hagh; Ahmet Bindal

2008-01-01

22

Design of analog circuits using organic field-effect transistors  

Microsoft Academic Search

Organic field-effect transistors (OFETs) can be manufactured at low temperatures, enabling the fabrication of integrated circuits on flexible plastic substrates and the coverage of large areas at potentially low cost. This paper evaluates state-of-the-art OFET technology from the perspective of the analog circuit designer. Specifically, we review important OFET device performance metrics in comparison to generic silicon CMOS transistors. In

Boris Murmann; Wei Xiong

2010-01-01

23

Fabrication of Thin-Film Transistor Integrated Circuits on Flexible Substrate by Transfer Technique of Carbon Nanotube Network Using Poly(vinyl alcohol)  

NASA Astrophysics Data System (ADS)

Flexible integrated circuits consisting of carbon nanotube thin-film transistors (CNTTFTs) were fabricated on a poly(ethylene naphthalate) (PEN) substrate by the transfer technique of the CNT network. The CNT network grown on a SiO2/p+-Si substrate by plasma-enhanced chemical vapor deposition was transferred onto the PEN substrate using poly(vinyl alcohol) (PVA). A delay time of 1.1 ?s/gate was realized for the ring oscillator with a channel length of 10 ?m. The present delay time is the best ever reported to our knowledge among CNTTFT flexible integrated circuits using transferred or printed CNT networks.

Ishii, Satoshi; Nishu, Mamoru; Kishimoto, Shigeru; Mizutani, Takashi

2013-10-01

24

SEMICONDUCTOR INTEGRATED CIRCUITS: Insulated gate bipolar transistor with trench gate structure of accumulation channel  

NASA Astrophysics Data System (ADS)

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simulation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K, respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.

Mengliang, Qian; Zehong, Li; Bo, Zhang; Zhaoji, Li

2010-03-01

25

Dynamics of Transistor Negative-Resistance Circuits  

Microsoft Academic Search

A general method is presented for calculating approximately the behavior of many nonlinear circuits by dividing the region of operation into subregions, within each of which the circuit may be considered linear to a good approximation. The method is applied to a high-speed transistor switching circuit as an illustrative example.

B. G. Farley

1952-01-01

26

Transistor sizing for low power CMOS circuits  

Microsoft Academic Search

A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area.

Manjit Borah; Robert Michael Owens; Mary Jane Irwin

1996-01-01

27

An MOS transistor model for analog circuit design  

Microsoft Academic Search

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in

A. I. A. Cunha; M. C. Schneider; C. Galup-Montoro

1998-01-01

28

Logic Circuits with Carbon Nanotube Transistors  

Microsoft Academic Search

We demonstrate logic circuits with field-effect transistors based on single carbon nanotubes. Our device layout features local gates that provide excellent capacitive coupling between the gate and nanotube, enabling strong electrostatic doping of the nanotube from p-doping to n-doping and the study of the nonconventional long-range screening of charge along the one-dimensional nanotubes. The transistors show favorable device characteristics such

Adrian Bachtold; Peter Hadley; Takeshi Nakanishi; Cees Dekker

2001-01-01

29

Gyrator circuit using field effect transistors  

NASA Technical Reports Server (NTRS)

Gyrator circuit is especially useful in integrated circuits for such purposes as simulating inductors with capacitors. Circuit is adaptable to semifloating and full floating configurations. It has excellent response, low power consumption, and high energy storage capacity.

Hochmair, E. S.

1973-01-01

30

High Performance Crystalline Organic Transistors and Circuit.  

National Technical Information Service (NTIS)

We have examined the best available small molecule crystalline organic semiconductors as active layers in thin-film transistors. We have optimized the field-induced conductance, a figure of merit that will relate directly to circuit speeds. A simple figur...

A. Dodabalapur

2011-01-01

31

Method for analyzing radiation sensitivity of integrated circuits  

NASA Technical Reports Server (NTRS)

A method for analyzing the radiation sensitivity of an integrated circuit is described to determine the components. The application of a narrow radiation beam to portions of the circuit is considered. The circuit is operated under normal bias conditions during the application of radiation in a dosage that is likely to cause malfunction of at least some transistors, while the circuit is monitored for failure of the irradiated transistor. When a radiation sensitive transistor is found, then the radiation beam is further narrowed and, using a fresh integrated circuit, a very narrow beam is applied to different parts of the transistor, such as its junctions, to locate the points of greatest sensitivity.

Gauthier, M. K.; Stanley, A. G. (inventors)

1979-01-01

32

Graphene radio frequency receiver integrated circuit.  

PubMed

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6?mm(2) area and fabricated on 200?mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal. PMID:24477203

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

33

Graphene radio frequency receiver integrated circuit  

NASA Astrophysics Data System (ADS)

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6?mm2 area and fabricated on 200?mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

34

Algorithms for automatic transistor sizing in CMOS digital circuits  

Microsoft Academic Search

This paper describes the algorithms for automatic transistor sizing (determination of device width and length) of CMOS digital circuits. In CMOS circuits, since power dissipation is small and not a limiting factor, the sizing algorithm is geared toward minimizing area. The program XTRAS (Xerox TRAnsistor Sizing Program) which determines transistor sizes as well as calculates path delays is described. Equations

William H. Kao; Nader Fathi; Chia-Hao Lee

1985-01-01

35

Adaptive logic circuits with doping-free ambipolar carbon nanotube transistors.  

PubMed

A CMOS-like inverter was integrated by using ambipolar carbon nanotube (CNT) transistors without doping. The ambipolar CNT transistors automatically configure themselves to play a role as an n-type or p-type transistor in a logic circuit depending on the supply voltage (V(DD)) and ground. A NOR (NAND) gate is adaptively converted to a NAND (NOR) gate. This adaptiveness of logic gates exhibiting two logic gate functions in a single logic circuit offers a new opportunity for designing logic circuits with high integration density for next generation applications. PMID:19281215

Yu, Woo Jong; Kim, Un Jeong; Kang, Bo Ram; Lee, Il Ha; Lee, Eun-Hong; Lee, Young Hee

2009-04-01

36

SLIC-A Simulator for Linear Integrated Circuits.  

National Technical Information Service (NTIS)

A computer program for the simulation of linear integrated circuits (SLIC) is described. The program formulates and solves nonlinear equations for dc node voltages and transistor operating points; generates linearized small-signal circuit models; and solv...

D. O. Pederson F. S. Jenkins T. E. Idleman W. J. McCalla

1971-01-01

37

Displacement Damage in Bipolar Linear Integrated Circuits  

NASA Technical Reports Server (NTRS)

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Rax, B. G.; Johnston, A. H.; Miyahira, T.

2000-01-01

38

Field-effect transistor self-electrooptic effect device: integrated photodiode, quantum well modulator and transistor  

Microsoft Academic Search

The authors propose and demonstrate the integration of a photodiode, a quantum-confined Stark-effect quantum-well optical modulator, and a metal-semiconductor field-effect transistor (MESFET) to make a field-effect transistor self-electrooptic effect device. This integration allows optical inputs and outputs on the surface of a GaAs-integrated circuit chip, compatible with standard MESFET processing. To provide an illustration of feasibility, the authors demonstrate signal

D. A. B. Miller; M. D. Feuer; T. Y. Chang; S. C. Shunk; J. E. Henry; D. J. Burrows; D. S. Chemla

1989-01-01

39

Temperature Compensation of Transistor Integrator.  

National Technical Information Service (NTIS)

It is shown that the temperature dependence of an inverted transistor can be very effectively used for temperature compensation. Conditions were derived for complete compensation of an integrator amplifier with emitter follower output and single-stage amp...

C. P. Wang

1964-01-01

40

SEMICONDUCTOR INTEGRATED CIRCUITS: Threshold voltage adjustment of organic thin film transistor by introducing a polysilicon floating gate  

NASA Astrophysics Data System (ADS)

The structure of organic thin film transistors (OTFTs) is optimized by introducing a floating gate into the gate dielectric to reduce the threshold voltage of OTFTs. Then the optimized device is simulated, and the simulation results show that the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way of reducing the threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacturing.

Chenglong, Wu; Jianhong, Yang; Xueyuan, Cai; Xiaofeng, Shan

2010-03-01

41

Integrated Circuits Laboratory  

NSDL National Science Digital Library

The Integrated Circuits Laboratory is software that is devoted to helping understand the processing of semiconductor materials. Manufacturing an IC involves a complex interaction of several highly developed technologies. This software is used to fabricate high-performance integrated circuits. In such areas as oxidation, diffusion, Ion implantation, Chemical etching, Photolithography, CVD, Ellipsometer, Plasma etching and Aluminum deposition. IC Lab software offers virtual opportunities to simulate the process of manufacturing a integrated circuit without going into a clean room. All the simulations represent processing steps that are as accurate as possible. This was part of the Learning Invention Labs that MATEC held. Visit the MATEC.org homepage for more information.

Lindor, Felicia

2013-01-01

42

Presettable Integrating Timing Circuit.  

National Technical Information Service (NTIS)

A presettable integrating timing circuit is capable of comparing the time-volt product of an input signal with a preset signal. Means, comprising an input and an output, integrate an electrical signal at the input into an integrated signal at the output. ...

J. R. McKinlay

1977-01-01

43

Monolithic integration of 1.3-?m InGaAs photodetectors and high-electron-mobility transistor (HEMT) electronic circuits on GaAs  

NASA Astrophysics Data System (ADS)

For the first time, monolithic optoelectronic receivers for a wavelength of 1.3 micrometers have been fabricated successfully on GaAs substrates using InGaAs metal-semiconductor-metal (MSM) photodiodes and AlGaAs/GaAs/AlGaAs high-electron-mobility transistors (HEMTs). Using molecular beam epitaxy (MBE), the photodetector layers were grown on top of a double (delta) -doped AlGaAs/GaAs/AlGaAs HEMT structure which allows the fabrication of enhancement and depletion field effect transistors. The photoabsorbing InGaAs layer was grown at 500 degree(s)C. To fabricate the optoelectronic receivers, first, an etch process using a combination of non-selective wet etching and selective reactive ion etching was applied to produce mesas for the photoconductors and to uncover the HEMT structure in all other areas. For the electronic circuits, our well-established HEMT process for 0.3-micrometers transistor gates was used which includes electron-beam lithography for gate definition and optical lithography for NiCr thin films resistors, capacitors, and inductors. The interdigitated MSM photodiode fingers were also fabricated using electron-beam lithography. For interconnecting the electronic circuits and the photodetectors, air bridges were employed. The entire process was performed on 2-inch wafers with more than 90% yield of functional receivers. The finished receiver--basically an MSM photodetector linked to a transimpedance amplifier--is operational at an incident wavelength of 1.3 micrometers at data rates up to 1.2 Gbit/s. The sensitivity of the detectors is 0.16 A/W at a 10 V bias.

Fink, Thomas; Hurm, Volker; Raynor, Brian; Koehler, Klaus; Benz, Willy; Ludwig, M.

1995-04-01

44

Single-photon transistor in circuit quantum electrodynamics.  

PubMed

We introduce a circuit quantum electrodynamical setup for a "single-photon" transistor. In our approach photons propagate in two open transmission lines that are coupled via two interacting transmon qubits. The interaction is such that no photons are exchanged between the two transmission lines but a single photon in one line can completely block or enable the propagation of photons in the other line. High on-off ratios can be achieved for feasible experimental parameters. Our approach is inherently scalable as all photon pulses can have the same pulse shape and carrier frequency such that output signals of one transistor can be input signals for a consecutive transistor. PMID:23971573

Neumeier, Lukas; Leib, Martin; Hartmann, Michael J

2013-08-01

45

A breakdown model for the bipolar transistor to be used with circuit simulators  

SciTech Connect

A breakdown model for the output characteristics of the bipolar transistor (bjt) has been developed. The behavioral modeling capability of PSPICE, a popular SPICE program (with Emphasis on Integrated circuits) was used to implement the macromodel. The model predicts bjt output characteristics under breakdown conditions. Experimental data was obtained to verify the macromodel. Good agreement exits between the measured and the simulated results.

Keshavarz, A.A. [Alliance Technologies, Inc., Albuquerque, NM (United States); Raney, C.W.; Campbell, D.C. [Sandia National Labs., Albuquerque, NM (United States)

1993-08-01

46

Bioluminescent bioreporter integrated circuit  

DOEpatents

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

2000-01-01

47

Integrated circuit reliability testing  

NASA Technical Reports Server (NTRS)

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

1990-01-01

48

Integrated circuit reliability testing  

NASA Technical Reports Server (NTRS)

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

Buehler, Martin G. (inventor); Sayah, Hoshyar R. (inventor)

1988-01-01

49

4.0-inch Active-Matrix Organic Light-Emitting Diode Display Integrated with Driver Circuits Using Amorphous In-Ga-Zn-Oxide Thin-Film Transistors with Suppressed Variation  

NASA Astrophysics Data System (ADS)

We have newly developed a 4.0-in. quarter video graphics array (QVGA) active-matrix organic light-emitting diode (AMOLED) display integrated with gate and source driver circuits using amorphous In-Ga-Zn-oxide (IGZO) thin-film transistors (TFTs). Focusing on a passivation layer in an inverted staggered bottom gate structure, the threshold voltage of the TFTs can be controlled to have “normally-off” characteristics with suppressed variation by using a SiOx layer formed by sputtering with a low hydrogen content. In addition, small subthreshold swing S/S of 0.19 V/decade, high field-effect mobility ?FE of 11.5 cm2 V-1 s-1, and threshold voltage Vth of 1.27 V are achieved. The deposition conditions of the passivation layer and other processes are optimized, and variation in TFT characteristics is suppressed, whereby high-speed operation in gate and source driver circuits can be achieved. Using these driver circuits, the 4.0-in. QVGA AMOLED display integrated with driver circuits can be realized.

Hiroki Ohara,; Toshinari Sasaki,; Kousei Noda,; Shunichi Ito,; Miyuki Sasaki,; Yuta Endo,; Shuhei Yoshitomi,; Junichiro Sakata,; Tadashi Serikawa,; Shunpei Yamazaki,

2010-03-01

50

Translinear circuits using subthreshold floating-gate MOS transistors  

Microsoft Academic Search

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and\\/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family

Bradley A. Minch; Chris Diorio; Paul Hasler; Carver A. Mead

1996-01-01

51

SLIC-a simulator for linear integrated circuits  

Microsoft Academic Search

A computer program for the simulation of linear integrated circuits (SLIC) is described. The program formulates and solves nonlinear equations for d.c. node voltages and transistor operating points; generates linearized small-signal circuit models; and solves for the poles, zeros, frequency response, and noise response of specified transfer functions. Temperature variations and operating point dependence can be effectively simulated.

THOMAS E. IDLEMAN; FRANCIS S. JENKINS; W. J. McCalla; D. O. Pederson

1971-01-01

52

A Unified Circuit Model for the Polysilicon Thin Film Transistor  

Microsoft Academic Search

This paper describes a unified approach to modelling the polysilicon thin film transistor (TFT) for the purposes of circuit design. The approach uses accurate methods of predicting the channel conductance and then fitting the resulting data with a polynomial. Two methods are proposed to find the channel conductance: a device model and measurement. The approach is suitable because the TFT

M. J. Izzard; P. Migliorato; W. I. Milne

1991-01-01

53

SEMICONDUCTOR INTEGRATED CIRCUITS: Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors  

NASA Astrophysics Data System (ADS)

The characteristics of radiation damage under a high or low dose rate in lateral PNP transistors with a heavily or lightly doped emitter is investigated. Experimental results show that as the total dose increases, the base current of transistors would increase and the current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects, especially the double effects of oxide trapped charge, is discussed in heavily or lightly doped transistors. Finally, through comparison between the high- and low-dose-rate response of the collector current in heavily doped lateral PNP transistors, the abnormal effect can be attributed to the annealing of the oxide trapped charge. The response of the collector current, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail.

Yuzhan, Zheng; Wu, Lu; Diyuan, Ren; Yiyuan, Wang; Zhikuan, Wang; Yonghui, Yang

2010-03-01

54

Transistor Logic Network Using Haven'S Delay Circuit.  

National Technical Information Service (NTIS)

The principle of operation of basic logic circuits is described, and their block diagrams are given. The operation of a simple logic network (modulo-7 counter) composed of the basic circuits described is discussed. The operation of a digital unit based on...

J. Bromirski A. Zasada A. Sielicki

1966-01-01

55

Simple bar-coating process for large-area, high-performance organic field-effect transistors and ambipolar complementary integrated circuits.  

PubMed

Large-area polymer FET arrays and integrated circuits (ICs) are successfully demonstrated via a simple wire-bar-coating process. Both a highly crystalline conjugated polymer layer and very smooth insulating polymer layer are formed by a consecutive wire-bar-coating process on a 4-inch plastic substrate with a short processing time for application as the active and dielectric layers of OFET arrays and ICs. PMID:23580467

Khim, Dongyoon; Han, Hyun; Baeg, Kang-Jun; Kim, Juhwan; Kwak, Sun-Woo; Kim, Dong-Yu; Noh, Yong-Young

2013-08-21

56

Flexible organic transistors and circuits with extreme bending stability  

NASA Astrophysics Data System (ADS)

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100?m. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5?m), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2010-12-01

57

A nonlinear macromodel of the bipolar integrated circuit operational amplifier for electromagnetic interference analysis  

Microsoft Academic Search

A nonlinear macromodel for the bipolar transistor integrated circuit operational amplifier is derived from the macromodel proposed by Boyle. The nonlinear macromodel contains only two nonlinear transistors in the input stage in a differential amplifier configuration. Parasitic capacitance effects are represented by capacitors placed at the collectors and emitters of the input transistors. The nonlinear macromodel is effective in predicting

G. K. C. Chen

1981-01-01

58

Integrated circuit cell library  

NASA Technical Reports Server (NTRS)

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

59

Three-dimensionally stacked flexible integrated circuit: Amorphous oxide/polymer hybrid complementary inverter using n-type a-In-Ga-Zn-O and p-type poly-(9,9-dioctylfluorene-co-bithiophene) thin-film transistors  

NASA Astrophysics Data System (ADS)

A three-dimensional vertically-stacked flexible integrated circuit is demonstrated based on hybrid complementary inverters made of n-type In-Ga-Zn-O (a-IGZO) amorphous oxide thin-film transistors (TFTs) and p-type poly-(9,9-dioctylfluorene-co-bithiophene) (F8T2) polymer TFTs, where all the fabrication processes were performed at temperatures <=120 °C. Saturation mobilities of the a-IGZO TFT and the F8T2 TFT are ~3.2 and ~1.7×10-3 cm2 V-1 s-1, respectively, from which we chose the appropriate dimensions of the TFTs so as to obtain a good balance for the inverter operation. The maximum voltage gain is ~67, which is better than those reported for organic/oxide hybrid complementary inverters.

Nomura, Kenji; Aoki, Takashi; Nakamura, Kiyoshi; Kamiya, Toshio; Nakanishi, Takashi; Hasegawa, Takayuki; Kimura, Mutsumi; Kawase, Takeo; Hirano, Masahiro; Hosono, Hideo

2010-06-01

60

A GaAs\\/AlGaAs double-heterojunction device functioning as a bipolar transistor and injection laser for optoelectronic integrated circuits  

Microsoft Academic Search

A GaAs\\/AlGaAs double-heterojunction bipolar transistor (DHBT) is developed which also functions as a transverse-injection laser. The epitaxial layers for the DHBT's are grown by metalorganic vapor phase epitaxy (MOVPE). Experimentation reveals a transistor current gain of ? 10 and a pulsed lasing threshold of 230 mA at room temperature.

Yuji Hasumi; Atsuo Kozen; Jiro Temmyo; Hajime Asahi

1987-01-01

61

SEMICONDUCTOR INTEGRATED CIRCUITS: An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process  

NASA Astrophysics Data System (ADS)

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 ?m CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

Peijun, Gao; J, Oh N.; Hao, Min

2009-08-01

62

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits  

Microsoft Academic Search

Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming

Yu Wang; Ku He; Rong Luo; Hui Wang; Huazhong Yang

2008-01-01

63

Integrating transistors on high-ohmic silicon  

Microsoft Academic Search

This paper presents a compatible technology for integrating both radiation detectors and transistors on the same high-ohmic silicon substrate. Using this technology, chips have been fabricated containing a number of test transistors (MOSFETs) with different geometries. Measurements on the devices showed a threshold voltage between 0 and -3 V, and a transconductance between 25 muA\\/V and 1.25 mA\\/V for aspect

S. E. Wouters; S. A. Audet; M. H. Kim; E. M. Schooneveld

1990-01-01

64

Amorphous silicon TFT circuit integration for OLED displays on glass and plastic  

Microsoft Academic Search

This paper reviews design considerations along with measurement results pertinent to amorphous silicon (a-Si:H) thin film transistor (TFT) drive circuits for active matrix organic light emitting diode (AMOLED) displays. We describe both pixel architectures and TFT circuit topologies that are amenable for vertically integrated, high aperture ratio pixels. Here, the OLED layer is integrated directly above the TFT circuit layer,

Arokia Nathan; Kapil Sakariya; A. Kumar; P. Servati; K. S. Karim; D. Striakhilev; A. Sazonov

2003-01-01

65

Integrated Circuit Study.  

National Technical Information Service (NTIS)

The possibility of replacing state-of-the-art multi-chip circuits currently used in the CP667 computer with newly developed monolithic circuits was investigated. Multi-chip units of the variety used in the CP667 from two manufacturers were investigated. T...

1964-01-01

66

Limitations on the maximum operating voltage of CMOS integrated circuits  

Microsoft Academic Search

A one-dimensional model has been developed to study the breakdown voltage behavior of an n-channel IGFET in a conventional CMOS integrated circuit. Two parasitic npn bipolar transistors intrinsic to the circuit which shunt the IGFET are found to limit the breakdown voltage below the intrinsic value of the drain\\/p-tub junction. Turn-on of the parasitics occurs as a result of hole

J. M. Dishman

1975-01-01

67

A new four-transistor poly-si pixel circuit for AMOLED  

Microsoft Academic Search

This paper presents a new poly-Si thin film transistor (TFT) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays. The pixel circuit has a simple four-transistor configuration and is controlled by two adjacent gate scan pulses, allowing a small circuit area and simple driving scheme. Simulation results show that this pixel circuit can provide the OLED with a current non-uniformity

Longyan Wang; Congwei Liao; Yinan Liang; Shengdong Zhang

2010-01-01

68

A sensor circuit using reference-based conductance switching in organic electrochemical transistors  

NASA Astrophysics Data System (ADS)

Using organic electrochemical transistors as sensors, the sample-receptor reaction often induces moderate changes only in the drain current dynamics as the gate voltage level is switched. Here, we report an electrochemical sensor circuit including electrochemical transistors based on poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate that puts out a static sensor response signal. The circuit includes a sample and a reference transistor that are both driven in the resistive mode at 0.1 V. Measurements were performed on aqueous salt electrolytes ranging from 100 to 500 mM concentrations. The signal-ON sensor circuit provides a tenfold increase in the sensitivity as compared to single transistor sensors.

Svensson, Per-Olof; Nilsson, David; Forchheimer, Robert; Berggren, Magnus

2008-11-01

69

Synthetic biology: integrated gene circuits.  

PubMed

A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits "from scratch" that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches are providing fundamental insights into the regulatory architecture, dynamics, and evolution of genetic circuits and enabling new levels of control across diverse biological systems. PMID:21885772

Nandagopal, Nagarajan; Elowitz, Michael B

2011-09-01

70

Synthetic Biology: Integrated Gene Circuits  

PubMed Central

A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits “from scratch” that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches are providing fundamental insights into the regulatory architecture, dynamics, and evolution of genetic circuits and enabling new levels of control across diverse biological systems.

Nandagopal, Nagarajan; Elowitz, Michael B.

2014-01-01

71

Low Cost Integrated Circuit Techniques.  

National Technical Information Service (NTIS)

An over-all process was developed for glass coating of silicon integrated circuit chips and batch attaching them to an appropriately processed substrate. The techniques developed were demonstrated by delivery of four 10-chip arrays consisting of glassed s...

S. Wagner W. L. Doelp

1967-01-01

72

Modules (Integrated Circuits) for Communications.  

National Technical Information Service (NTIS)

The application of integrated circuits in analog communications equipment was demonstrated by the development of the IF-video functional assembly of the Mark X IFF Transponder. The IF-video assembly utilizes a linear-logarithmic amplifier technique. Succe...

F. E. Farmar A. M. Hoque H. Groot

1966-01-01

73

Variational integrators for electric circuits  

SciTech Connect

In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

Ober-Blöbaum, Sina, E-mail: sinaob@math.upb.de [Computational Dynamics and Optimal Control, University of Paderborn (Germany)] [Computational Dynamics and Optimal Control, University of Paderborn (Germany); Tao, Molei [Courant Institute of Mathematical Sciences, New York University (United States)] [Courant Institute of Mathematical Sciences, New York University (United States); Cheng, Mulin [Applied and Computational Mathematics, California Institute of Technology (United States)] [Applied and Computational Mathematics, California Institute of Technology (United States); Owhadi, Houman; Marsden, Jerrold E. [Control and Dynamical Systems, California Institute of Technology (United States) [Control and Dynamical Systems, California Institute of Technology (United States); Applied and Computational Mathematics, California Institute of Technology (United States)

2013-06-01

74

Low-cost all-polymer integrated circuits  

Microsoft Academic Search

A technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of field-effect transistors in which the semiconducting, conducting and insulating parts are all made of polymers. The fabrication on flexible substrates uses spin-coating of electrically active precursors and patternwise exposure of the deposited films. In the whole process stack-integrity is maintained. Vertical interconnects are made mechanically.

C. M. Hart; D. M. de Leeuw; M. Matters; P. T. Herwig; C. M. J. Mutsaerts; C. J. Drury

1998-01-01

75

A hybrid nanomemristor/transistor logic circuit capable of self-programming  

PubMed Central

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

76

Integrated Circuit Charge Sensitive Preamplifier  

Microsoft Academic Search

An integrated circuit charge-sensitive preamplifier has been designed for use with gas filled proportional counters and\\/or silicon nuclear particle detectors. The circuit uses positive current feedback to achieve open loop voltage gains over 2000. The preamplifier noise with zero input capacitance is 1750 ion pairs (rms) which is equivalent to 14.3 kev (FWHM, silicon detector). The rms noise versus capacitance

Keith V. Warble; Norman J. Gri

1966-01-01

77

High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits  

NASA Astrophysics Data System (ADS)

The three-dimensional CMOS inverter with top-gate (TG) poly-Si thin film transistors (TFTs) vertically stacked on the bottom-gate (BG) poly-Si TFTs have been proposed to achieve high-performance characteristics via excimer laser crystallization (ELC) for the first time. Under an appropriate laser irradiation energy density, the silicon grain growth could be controlled from the sidewalls of the bottom-gate structure and thus the high-quality laterally grown poly-Si film with single perpendicular grain boundary in the channel would be formed for the BG TFTs. In addition, a simple ELC method was also utilized to the top-layered poly-Si film for TG TFTs as compared with solid-state-crystallized (SPC) ones. As a result, the field-effect mobilities of the proposed n-type BG and p-type TG TFTs could be significantly increased to be 390 and 131 cm2/V s, respectively, in contrast to 32.3 and 14.7 cm2/V s for the SPC ones, accordingly. Furthermore, such three-dimensional (3-D) TFT have also been employed to demonstrate the inverter devices and is suitable for future 3-D ICs as well as system-on-panel applications.

Lee, I.-Che; Tsai, Tsung-Che; Tsai, Chun-Chien; Yang, Po-Yu; Wang, Chao-Lung; Cheng, Huang-Chung

2012-11-01

78

Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits  

US Patent & Trademark Office Database

Circuits and methods for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices, which enable circuit designers to accurately measure and characterize random variations in device characteristics (such as transistor threshold voltage) between neighboring devices resulting from random sources such as dopant fluctuations and line edge roughness, for purposes of integrated circuit design and analysis. In one aspect, a method for characterizing random variations in device mismatch (e.g., threshold voltage mismatch) between a pair of device (e.g., transistors) is performed by obtaining subthreshold DC voltage characteristic data for the device pair, and then determining a distribution in voltage threshold mismatch for the device pair directly from the corresponding subthreshold DC voltage characteristic data. The voltage threshold mismatch distributions of different device pairs of a given circuit design can then be used to determine voltage threshold variations of the constituent circuit devices. The voltage threshold variation of the devices can be used to characterize the random variations of the given circuit.

2012-07-03

79

Control of exciton fluxes in an excitonic integrated circuit.  

PubMed

Efficient signal communication uses photons. Signal processing, however, uses an optically inactive medium, electrons. Therefore, an interconnection between electronic signal processing and optical communication is required at the integrated circuit level. We demonstrated control of exciton fluxes in an excitonic integrated circuit. The circuit consists of three exciton optoelectronic transistors and performs operations with exciton fluxes, such as directional switching and merging. Photons transform into excitons at the circuit input, and the excitons transform into photons at the circuit output. The exciton flux from the input to the output is controlled by a pattern of the electrode voltages. The direct coupling of photons, used in communication, to excitons, used as the device-operation medium, may lead to the development of efficient exciton-based optoelectronic devices. PMID:18566248

High, Alex A; Novitskaya, Ekaterina E; Butov, Leonid V; Hanson, Micah; Gossard, Arthur C

2008-07-11

80

An optical feedback compensation circuit with aSi:H thin-film transistors for active matrix organic light emitting diodes  

Microsoft Academic Search

We propose a novel compensation pixel circuit for active matrix organic light emitting diode (AMOLED) display using thin-film transistor (TFT) optical feedback circuit consisting of four switching TFTs, one driving TFT, one photo-sensor and one capacitor. The optical feedback pixel is operated with two gate signals and one scan signal. An integrated scan driver is used to make the scan

Moon Hyo Kang; Ji Ho Hur; Youn Duck Nam; Eun Ho Lee; Se Hwan Kim; Jin Jang

2008-01-01

81

Graphene-Dielectric Integration for Graphene Transistors  

PubMed Central

Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-? dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities.

Liao, Lei; Duan, Xiangfeng

2010-01-01

82

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.  

PubMed

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics. PMID:23590623

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

83

A synthetic neural integrated circuit  

Microsoft Academic Search

Integrated circuits are approaching biological complexity in device count. Biological systems are fault tolerant, adaptive, and trainable, and the possibility exists for similar characteristics in ICs. The authors report a limited-interconnect, highly layered synthetic neural network that implements these ideals. These networks are specifically designed to scale to tens of thousands of processing elements on current production size dies. A

L. A. Akers; M. Walker; R. Grondin; D. Ferry

1989-01-01

84

Non-hysteretic punchthrough impact ionization MOS (PIMOS) transistor: Application to abrupt inverter and NDR circuits  

Microsoft Academic Search

The recently proposed PIMOS transistor can offer, by appropriate operation, non-hysteretic abrupt off-on transitions due to impact ionization if the action of its parasitic bipolar transistor is minimized. This work proposes non-hysteretic abrupt inverter circuits based on <10 mV\\/decade room temperature current switching and a tunable negative differential resistance based on punch-through impact ionization MOS transistors (PIMOS) when parasitic bipolar

Vincent Pott; Kirsten E. Moselund; Adrian M. Ionescu

2008-01-01

85

Integrated aSi:H\\/pentacene inorganic\\/organic complementary circuits  

Microsoft Academic Search

We have developed a low-cost fabrication process for complementary circuits using integrated organic and inorganic thin film transistors (TFTs). In these circuits, a-Si:H TFTs are used as the n-channel and pentacene organic TFTs as the p-channel devices. These circuits show high switching gain and excellent logic level conservation, with very low off-currents during static operation. Gate delay of our circuits,

Mathias Bonse; Daniel B. Thomasson; Hagen Klauk; David J. Gundlach; Thomas N. Jackson

1998-01-01

86

Microfluidic Photonic Integrated Circuits  

PubMed Central

We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled two-dimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1–10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments.

Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S.; Lo, Yu-Hwa

2010-01-01

87

Delay locked loop integrated circuit.  

SciTech Connect

This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

Brocato, Robert Wesley

2007-10-01

88

Compact modeling of vertical ESD protection NPN transistors for RF circuits  

Microsoft Academic Search

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

Sopan Joshi; Elyse Rosenbaum

2002-01-01

89

Bioluminescent bioreporter integrated circuits (BBICs)  

NASA Astrophysics Data System (ADS)

As the workhorse of the integrated circuit (IC) industry, the capabilities of CMOS have been expanded well beyond the original applications. The full spectrum of analog circuits from switched-capacitor filters to microwave circuit blocks, and from general-purpose operational amplifiers to sub- nanosecond analog timing circuits for nuclear physics experiments have been implemented in CMOS. This technology has also made in-roads into the growing area of monolithic sensors with devices such as active-pixel sensors and other electro-optical detection devices. While many of the processes used for MEMS fabrication are not compatible with the CMOS IC process, depositing a sensor material onto a previously fabricated CMOS circuit can create a very useful category of sensors. In this work we report a chemical sensor composed of bioluminescent bioreporters (genetically engineered bacteria) deposited onto a micro-luminometer fabricated in a standard CMOS IC process. The bioreporter used for this work emitted 490-nm light when exposed to toluene. This luminescence was detected by the micro- luminometer giving an indication of the concentration of toluene. Other bioluminescent bioreporters sensitive to explosives, mercury, and other organic chemicals and heavy metals have been reported. These could be incorporated (individually or in combination) with the micro-luminometer reported here to form a variety of chemical sensors.

Simpson, Michael L.; Sayler, Gary S.; Nivens, David; Ripp, Steve; Paulus, Michael J.; Jellison, Gerald E.

1998-07-01

90

Self-integration of nanowires into circuits via guided growth  

PubMed Central

The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom–up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel “self-integration” of NWs into electronic circuits and functional systems based on guided growth.

Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

2013-01-01

91

Self-integration of nanowires into circuits via guided growth.  

PubMed

The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom-up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel "self-integration" of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

2013-09-17

92

Scalable fabrication of self-aligned graphene transistors and circuits on glass  

PubMed Central

High frequency graphene transistors with the intrinsic cut-off frequency up to 300 gigahertz (GHz) have been demonstrated for radio frequency (RF) applications. However, functional graphene RF circuits such as frequency doublers and mixers operating in the gigahertz range is yet to demonstrated. Here we report a scalable approach to fabricate self-aligned graphene transistors and circuits that can operate in gigahertz regime. The devices are fabricated through a self-aligned aligned process on glass substrate using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows to achieving unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/?m. With the minimization of parasitic capacitance on insulating substrate, the resulting graphene transistors exhibit a record high extrinsic cut-off frequency (> 50 GHz) achieved in graphene transistors to date. The excellent extrinsic cut-off frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1–10 GHz regime, a significant advancement over previous report (~20 MHz). The studies open a pathway to scalable fabrication of high speed graphene transistors and functional circuits, and represent a significant step forward to graphene based radio frequency devices.

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2011-01-01

93

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress  

NASA Technical Reports Server (NTRS)

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Mclyman, W. T. (inventor)

1981-01-01

94

Integrated acoustooptic circuits and applications.  

PubMed

The recent development of titanium-indiffusion proton-exchange (TIPE) microlenses and lens arrays has made possible the construction of a variety of single- and multichannel integrated acoustooptic (AO) and acoustooptic-electrooptic (EO) circuits in LiNbO(3) channel-planar waveguides 0.1x1.0x2.0 cm(3) in size. These hybrid AO and AO-EO circuits can be fabricated through compatible and well-established technologies. The most recent realization of ion-milled microlenses and lens arrays together with the recent development of gigahertz AO Bragg modulators and EO Bragg modulator arrays have also paved the way for construction of similar but monolithic AO and AO-EO GaAs/GaAlAs waveguides of comparable size. Both types of integrated AO and AO-EO circuits suggest versatile applications in communications signal processing, and computing. Efficient and simultaneous excitation of the channel waveguide array using an ion-milled planar microlens array has facilitated the demonstration of some of these applications. PMID:18267666

Tsai, C S

1992-01-01

95

Analytical modeling of device-circuit interactions for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The device-circuit interactions of the power insulated gate bipolar transistor (IGBT) for a series resistor-inductor load, both with and without a snubber, are simulated. An analytical model for the transient operation of the IGBT, previously developed, is used in conjunction with the load circuit state equations for the simulations. The simulated results are compared with experimental results for all conditions.

1990-01-01

96

A Digital Computer Analysis and Synthesis of Insulated Gate Field Effect Transistor Complementary Circuits.  

National Technical Information Service (NTIS)

A digital model of the insulated gate field effect transistor was proposed and used in the solution of two and three-element circuits. A number of circuits with desired characteristics were obtained by the method of variation of parameters in the model. (...

L. J. Harrell

1969-01-01

97

Organic thin-film transistors: Characterization and integration on low temperature substrates for flexible electronics  

NASA Astrophysics Data System (ADS)

In this work pentacene thin-film transistors (TFTs) are fabricated and characterized on low temperature substrates for flexible electronic applications. Maximum processing temperature is <120°C. Pentacene transistors are optimized by varying the deposition conditions, thickness ratio of source-drain metal contact to pentacene film. By using parylene as the gate dielectric film, pentacene TFTs with low threshold voltage (VT) and low V T variation are fabricated. Gate-last integration technique is presented enabling integration of pentacene p-type TFTs with a:Si:H n-type TFTs to form hybrid complementary metal-oxide-semiconductor (CMOS) circuits on polyethylene naphthalate (PEN). Circuits evaluated are inverters, 2-input NAND and NOR logic gates. Parylene gate dielectric reliability and gate bias stress analysis of TFTs and hybrid CMOS circuit is also presented.

Gowrisanker, Srinivas

98

New platforms for electronic devices: N-channel organic field-effect transistors, complementary circuits, and nanowire transistors  

Microsoft Academic Search

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized alpha,o-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N'-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric\\/electrode surface treatment on the response of bottom-contact devices was also examined

Byungwook Yoo

2007-01-01

99

On the generation of multiplexer circuits for pass transistor logic  

Microsoft Academic Search

Pass Transistor Logic (PTL) has attracted more and more interest during recent years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, performance and power consumption. Existing automatic PTL synthesis tools use a direct mapping of (decomposed) BDDs to pass transistors. Thereby, structural properties of BDDs like the ordering restriction and the

Christoph Scholl; Bernd Becker

2000-01-01

100

Low voltage pentacene OTFT integration for smart sensor control circuits  

NASA Astrophysics Data System (ADS)

The past decade has witnessed remarkable progress in Organic electronics and Organic sensor technology on flexible substrates. Temperature and strain sensors for wireless active health monitoring systems have been tested and demonstrated. These sensors need control circuits to condition and transmit the measurand to the data acquisition system. The control circuits have to be incorporated on to the same substrate as the sensing element. So far, Pentacene based Organic Thin-Film Transistors (OTFTs) have been the most promising candidates for integrated circuit applications. To this end, optimization of the OTFT fabrication process is needed to obtain reliable and reproducible transistor performance in terms of mobility, threshold voltage, drive currents, minimal supply voltage and minimal leakage currents. The objective here is to minimize the leakage losses and the voltage required to drive this circuitry while maintaining process compatibility. The choice of dielectric material has been proven to be a key factor influencing all the desirable characteristics stated above. This paper investigates the feasibility of using a High K/Low K, Tantalum Pentoxide/Poly (4-vinyl phenol) (PVP) hybrid dielectric in Pentacene-based OTFTs to lower the operating voltages. Inverters and simple logic gates like 2-input NAND are simulated with these OTFTs. The results indicate that these OTFTs can indeed be used to build large scale integrated circuits with reproducibility.

Kumar, Prashanth S.; Rai, Pratyush; Mathur, Gyanesh N.; Varadan, Vijay K.

2010-03-01

101

Ultra-low power microwave CHFET integrated circuit development  

SciTech Connect

This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

Baca, A.G.; Hietala, V.M.; Greenway, D.; Sloan, L.R.; Shul, R.J.; Muyshondt, G.P.; Dubbert, D.F.

1998-04-01

102

Plasma processing for integrated circuits  

SciTech Connect

The steady advance of integrated circuit technology is one of the most remarkable technology trends in this era of technological revolution. For example, the 64-k memory chips of the early 1980s are now being replaced by 4-M and even 16-M chips. This trend is expected to continue with chips at the giga-bit level being available in a decade. The needs for ultraviolet and then X-ray lithography to define the submicron features needed for these larger, denser chips have been widely discussed. However, in parallel, the equipment (referred to as tools in the industry) and related processes to carry out the deposition and etching steps needed to actually produce devices in the tenth-micron range also require significant development. This paper summarizes present and anticipated contributions of magnetic fusion plasma theory and diagnostics and plasma production technology at Oak Ridge National Laboratory (ORNL) for the development of integrated circuit production technology. The discussion is introduced with a review of past technology evolution and of the present economic context for manufacturing.

Berry, L.A.

1994-10-01

103

Complementary Circuit with Self-Alignment Organic/Oxide Thin-Film Transistors  

NASA Astrophysics Data System (ADS)

Complementary logic circuits with self-alignment organic/oxide thin-film transistors (TFTs) were investigated. The layout and process steps of a self-alignment bottom-contact-type organic TFT and a top-contact type oxide TFT with a common layout pattern of the gate, source, and drain electrodes were proposed, and an integrated circuit was realized. The estimated field-effect mobilities, threshold voltages, and on-off ratios of the organic and oxide TFTs were 0.16 and 2.2 cm2 V-1 s-1, 2.2 and 2 V, and 3× 103 and 5.2× 106, respectively. From the complementary inverter characteristics, the voltage gain was 13 and the logic swing was 9.8 V at an applied voltage of 10 V. From the switching characteristics of the inverter, the rise and fall times were 18 and 46 ?s, respectively. The operations of the NAND and NOR logic circuit configurations were confirmed, and the maximum operational frequency of NAND logic was estimated to be over 100 kHz.

Takeda, Fumio; Sato, Ryuichi; Naka, Shigeki; Okada, Hiroyuki

2012-02-01

104

Innovative Voltage Driving Pixel Circuit Using Organic Thin-Film Transistor for AMOLEDs  

Microsoft Academic Search

In this work, we propose a novel active-matrix organic light-emitting diode displays (AMOLED) pixel circuit based on organic thin-film transistor (OTFT) architecture, which consisted of four switches, one driving transistor, and a capacitor. The pentacene-based OTFT device possesses a field-effect mobility of 0.1 cm2\\/V ldr s, a threshold voltage of -1.5 V, subthreshold slope of 1.8 V\\/decade and an on\\/off

Po-Tsun Liu; Li-Wei Chu

2009-01-01

105

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes  

NASA Astrophysics Data System (ADS)

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 µA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 µA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented.

Gutiérrez-Heredia, G.; González, L. A.; Alshareef, H. N.; Gnade, B. E.; Quevedo-López, M.

2010-11-01

106

Infrared FPA readout circuit based on current mirroring integration  

NASA Astrophysics Data System (ADS)

This paper reports an improved Current Mirroring Integration (CMI) unit cell and a new readout structure based on it. The new structure combines the benefits of the current mirroring direct injection and switch current integration structures, satisfying the requirements for the high resolution and high performance IR FPA readouts. The improved CMI readout circuit provides very high injection efficiency, almost-zero detector bias, and large dynamic range, while it can be implemented in a small pixel area. the circuit provides a maximum charge storage capacity of 5.25 X 107 electrons and a maximum transimpedence of 6 X 107 (Omega) for a 5V power supply and a 2pF integration capacitance, which is paled outside the unit cell. The unit cell employs only nine MOS transistors and occupies an area of 20micrometers X 25 micrometers in a 0.8 micrometers CMOS process.

Kulah, Haluk; Akin, Tayfun

1999-07-01

107

Integrated Circuit Electromagnetic Immunity Handbook  

NASA Astrophysics Data System (ADS)

This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

Sketoe, J. G.

2000-08-01

108

Integrated circuit generating 3- and 5-scroll attractors  

NASA Astrophysics Data System (ADS)

This paper introduces the experimental realization of the first integrated circuit of a multi-scroll continuous chaotic oscillator showing 3- and 5-scroll attractors. It is based on a variant of the Chua's system. The most relevant issue is the implementation of a saw-tooth-like nonlinear function, which is designed by using floating gate MOS (FGMOS) transistors. Therefore, the realization of a voltage-to-current nonlinear cell by a piecewise-linear approach allows us to have only two external control inputs instead of numerous external voltage references, as usually done in current circuit realizations. Experimental results of the proposed integrated multi-scroll oscillator along with its corner analysis are provided.

Trejo-Guerra, R.; Tlelo-Cuautle, E.; Jiménez-Fuentes, J. M.; Sánchez-López, C.; Muñoz-Pacheco, J. M.; Espinosa-Flores-Verdad, G.; Rocha-Pérez, J. M.

2012-11-01

109

A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors  

Microsoft Academic Search

This paper presents a circuit-compatible compact model for short channel length (5 nm~100 nm), quasi-ballistic single wall carbon nanotube field-effect transistors (CNFETs). For the first time, a universal circuit-compatible CNFET model was implemented with HSPICE. This model includes practical device non-idealities, e.g. the quantum confinement effects in both circumferential and channel length direction, the acoustical\\/optical phonon scattering in channel region

J. Deng; H.-S. P. Wong

2006-01-01

110

Total Dose and Dose Rate Models for Bipolar Transistors in Circuit Simulation.  

National Technical Information Service (NTIS)

The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on...

P. M. Campbell S. D. Wix

2013-01-01

111

Organic thin-film transistors modeling; simulation and design of a fully organic AMOLED pixel circuit  

Microsoft Academic Search

In this paper we implement the simulation and design of a fully organic AMOLED pixel in which OLED current driving and pixel selection is performed by organic thin-film transistors (OTFTs). An empirical SPICE-like OTFT model has been developed. A pixel with sandwich structure in which the OLED is deposited on top of the rest of the circuit has been simulated

Omid Yaghmazadeh; Yvan Bonnassieux; Amar Saboundji; Gilles Horowitz; B. Geffroy; D. Tondelier

2008-01-01

112

Circuit Techniques for Improving the Switching Loci of Transistor Switches in Switching Regulators  

Microsoft Academic Search

The use of switching regulator circuits at high power levels and high frequencies requires careful examination and control of the power dissipation during switching, which may be the dominant loss. In this paper it is shown that it is possible to remove most of the switching losses from the switching transistor with two networks, each containing three components: an inductor

E. T. Calkin; B. H. Hamilton

1976-01-01

113

Power transistor models with temperature dependent parasitic effects for SPICE-like circuit simulation  

Microsoft Academic Search

New SPICE-like simulation models for a power MOSFET containing a dynamic link between electrical and thermal component descriptions were described. The designed electro-thermal MOSFET model consists of several parts which represent different transistor behavior at different conditions as reverse bias, avalanche breakdown, thermal burning and others. Modified thermal equivalent circuit diagrams were designed taking into account thermal dependence of thermal

A. Chvala; D. Donoval; J. Marek; P. Pribytny; M. Molnar

2012-01-01

114

A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors  

Microsoft Academic Search

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors

Narender Hanchate; Nagarajan Ranganathan

2004-01-01

115

Direct extraction of the AlGaAs\\/GaAs heterojunction bipolar transistor small-signal equivalent circuit  

Microsoft Academic Search

The authors describe a novel, direct technique for determining the small-signal equivalent circuit of a heterojunction bipolar transistor (HBT). The parasitic elements are largely determined from measurements of test structures, reducing the number of elements determined from measurements of the transistor. The intrinsic circuit elements are evaluated from y-parameter data, which are DC-embedded from the known parasitics. The equivalent-circuit elements

Damian Costa; William U. Liu; James S. Harris

1991-01-01

116

Field Effect Transistor /FET/ circuit for variable gin amplifiers  

NASA Technical Reports Server (NTRS)

Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

Spaid, G. H.

1969-01-01

117

Integrated circuits and logic operations based on single-layer MoS2.  

PubMed

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced. PMID:22073905

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

118

Thermionic integrated circuit program: Final report  

SciTech Connect

This report describes the development of an operational amplifier using radiation hardened Thermionic Integrated Circuits (TICs). The report is written as a tutorial to cover all aspects of the fabrication process and circuit development as well as the process and circuit modifications required to meet the integration requirements of the operational amplifier. Recent experimental results are discussed in which both devices and test circuit data are compared to theoretical computer code predictions. The development of compatible high-temperature thin-film resistors is also presented. Because the project is being terminated prior to the completion of the amplifier, suggestions are made for additional advance development.

Wilde, D.K.; Lynn, D.K.; Hamilton, D.

1988-05-01

119

Synthetic Biology: Integrated Gene Circuits  

Microsoft Academic Search

A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits ``from scratch'' that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic

Nagarajan Nandagopal; Michael B. Elowitz

2011-01-01

120

Models for total dose degradation of linear integrated circuits  

SciTech Connect

Mechanisms for total dose degradation of linear circuits are discussed, including bulk effects, oxide charge buildup and recombination at the Si-SiO/sub 2/ interface. The dependence of damage on bias, dose, particle type and energy is used in conjunction with two-dimensional modeling to identify the failure mechanism in a specific linear device type. The importance of surface recombination is demonstrated along with the absence of bias dependence. Bulk damage is shown to be important for high energy electron irradiation because of wide-base pnp transistors. This causes substantial differences in device failure between electron and cobalt-60 environments that need to be taken into account for test standards and data bases that include commercial bipolar integrated circuits. Valid test methodologies for linear device must consider the energy and particle type present in the actual environment.

Johnston, A.H.; Plaag, R.E.

1987-12-01

121

Nonlinear oscillations in a unijunction transistor (UJT) circuit  

NASA Astrophysics Data System (ADS)

Phenomena such as plasma wavesootnotetextT Tsuru, Nonlinear resonance phenomena of elect. plasma oscillations by beam modulation, J. Phys. Soc. Japan, 40, 548, 1976. and oscillations in electric circuits which employ a plasma componentootnotetextM Wendt, I Axnas, S Torven, Amplitude collapse of nonlinear double-layer oscillations, Phys. Rev. E, 57, 4638, 1998. can be described by a differential equation with nonlinear dissipative and restoring force terms. The UJT oscillator circuit developed by Koepke and HartleyootnotetextME Koepke, DM Hartley, Experimental verification of periodic pulling in a nonlinear electronic oscillator, Phys. Rev. A, 44, 6877, 1991 is also described by a similar equation. During the past year efforts have been made to understand the following aspects of this circuit's operation: 1) Determining conditions which lead to oscillation onset and termination (amplitude collapse). 2) Analytic and numerical modeling. 3) Characterizing the capacitances associated with the emitter-base junctions. 4) Exploring the relationship between this circuit and astable multivibrators.

Zielinski, John

2005-10-01

122

Analog MOS integrated circuits for signal processing  

Microsoft Academic Search

Theoretical and practical aspects of analog MOS integrated circuits are discussed. The basic properties of these circuits are described, providing necessary background material in mathematics and semiconductor device physics and technology. The operation and design of such important circuits as switched-capacitor filters, analog-to-digital and digital-to-analog converters, amplifiers, modulators, and oscillators. Practical problems encountered in design are discussed, solutions are provided,

R. Gregorian; G. C. Temes

1986-01-01

123

Reusable vibration resistant integrated circuit mounting socket  

SciTech Connect

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Evans, C.N.

1993-12-31

124

Reusable vibration resistant integrated circuit mounting socket  

DOEpatents

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Evans, Craig N. (Irwin, PA)

1995-01-01

125

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits  

NASA Technical Reports Server (NTRS)

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

1972-01-01

126

Inductive Fault Analysis of MOS Integrated Circuits  

Microsoft Academic Search

Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types

John Shen; W. Maly; F. J. Ferguson

1985-01-01

127

Modularized construction of general integrated circuits on individual carbon nanotubes.  

PubMed

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future. PMID:24796796

Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

2014-06-11

128

V.DMOS transistor modeling for simulation of power electronic circuits  

NASA Astrophysics Data System (ADS)

A nonlinear, short channel model of a power V.DMOS transistor, the elements of which depend only on physical and technological data, is presented. By an analysis of the active regions of the V.DMOS structure, in order to study switching modes, this model is simplified to a topology compatible with the SPICE circuit simulator. Parameter extraction methods and validation programs are described. A software library of the SPICE models is created by testing the transistors (N and P channels) covering the available current handling capability 2A to 50A and blocking range 50V to 1000V. A V.DMOS unified model is presented. It requires establishment of two parameters: drain source breakdown voltage, and silicon chip area. An established program linked in Hypercard with SPICE, gives an exact model for characterizing transistors as well as a model for new devices. This modeling takes into account the crystal temperature and several validation tests. Adaptation of the model for irradiation applications is pointed out by comparison between measured and computed characteristics. Use of this model to analyze bridge leg circuit properties and comparison between simulated results and measured data, confirms its application in power electronic circuits. Some problems associated with parasitic elements in these circuits are described.

Napieralska, Malgorzata

1991-08-01

129

SLIC - Symbolic Layout of Integrated Circuits  

Microsoft Academic Search

The purpose of this paper is to introduce a symbolic layout technique for MOS integrated circuits. We will give a description of symbolic layout, talk about its potential and briefly describe the symbolic layout system we have developed at AMI.

Dave Gibson; Scott Nance

1976-01-01

130

Modeling of Integrated Circuit Effectiveness (Mice).  

National Technical Information Service (NTIS)

A Stress Survival Matrix Test (SSMT) and Physical Effects Analysis (PEA) program was conducted on a type of monolithic silicon integrated circuit from two vendors. The purposes of the program were to identify the basic reliability characteristics of integ...

B. F. Tiger D. I. Troxel

1967-01-01

131

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.  

PubMed

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates). PMID:24923382

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-01-01

132

Integrated Circuit Stellar Magnitude Simulator  

ERIC Educational Resources Information Center

Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

Blackburn, James A.

1978-01-01

133

Surface passivation of lnP/ln0.53Ga0.47As heterojunction bipolar transistors for opto-electronic integration  

NASA Astrophysics Data System (ADS)

We report for the first time, a surface passivation technique for InP/In0.53Ga0.47As heterojunction bipolar transistors that is suitable for optoelectronic integrated circuits. The combination of buffered hydrofluoric acid with high temperature annealing of the surface causes significant increase of the gain at low input currents. Using this technique, transistors were integrated with photodetectors and other optoelectronic devices and had current gains as high as 400 even at nanoampere base currents.

Kim, Dong-Su; Chao, Chih-Ping; Beyzavi, Kian; Burrows, Paul E.; Forrest, Stephen R.

1996-03-01

134

Single Transistor Digital Logic Circuits based on Gate-controlled 2D-2D Resonant Tunneling  

NASA Astrophysics Data System (ADS)

We have fabricated a new quantum device, the double electron layer tunneling transistor (DELTT),(J. A. Simmons et al., 1998 March Meeting abstract.) in an MBE-grown highly density-imbalanced AlGaAs/GaAs double quantum well heterostructure for higher operating temperature. Unlike other resonant tunneling devices, the DELTT is implemented in planar configuration, enabling ease in fabrication. It operates based on 2D-2D resonant tunneling, yielding strong negative differential resistance (NDR) in its source-drain I-V, which can be controlled by surface Schottky gate. we illustrate the multifunctionality of a single DELTT at 77K by demonstrating digital logic circuits such as XOR and NAND gates. These circuits use considerably fewer transistors than their conventional counterparts.

Moon, J. S.; Simmons, J. A.; Blount, M. A.; Baca, W. E.; Reno, J. L.; Hafich, M. J.

1998-03-01

135

Low Temperature Polycrystalline Silicon Thin Film Transistor Pixel Circuits for Active Matrix Organic Light Emitting Diodes  

Microsoft Academic Search

A new pixel design and driving method for active matrix organic light emitting diode (AMOLED) displays that use low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with a voltage programming method are proposed and verified using the SPICE simulator. We had employed an appropriate TFT model in SPICE simulation to demonstrate the performance of the pixel circuit. The OLED anode voltage variation

Ching-Lin Fan; Yu-Sheng Lin; Yan-Wei Liu

2010-01-01

136

High-performance and stable organic transistors and circuits with patterned polypyrrole electrodes.  

PubMed

High performance p-/n-type transistors and complementary inverter circuits are demonstrated using patterned polypyrrole (PPY) as pure electrodes. Strikingly, these devices show good stability under continuous operation and long-term storage conditions. Furthermore, PPY electrodes also exhibit good applicability in solution-processed and flexible devices. All these results indicate the great potential of PPY electrodes in solution-processed, all-organic, flexible, transparent, and low-power electronics. PMID:22431264

Li, Liqiang; Jiang, Lin; Wang, Wenchong; Du, Chuan; Fuchs, Harald; Hu, Wenping; Chi, Lifeng

2012-04-24

137

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design.  

National Technical Information Service (NTIS)

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. T...

E. J. Kennedy G. T. Alley C. L. Britton P. L. Skubic B. Gray

1990-01-01

138

Handbook of microwave integrated circuits  

NASA Astrophysics Data System (ADS)

The design and operation of ICs for use in the 0.5-20-GHz range are described in an introductory and reference work for industrial engineers. Chapters are devoted to an overview of microwave IC (MIC) technology, general stripline characteristics, microwave transmission line (MTL) parameters for microstrips with isotropic dielectric substrates, higher-order modes on a microstrip, the effects of metallic enclosure on MTL transmission parameters, losses in microstrips, the measurement of MTL parameters, and MTLs on anisotropic dielectric substrates. Consideration is given to coupled microstrips on dielectric substrates, microstrip discontinuities, radiation from microstrip circuits, MTL variations, coplanar MTLs, slotlines, and spurious modes in MTL circuits. Diagrams, drawings, graphs, and a glossary of symbols are provided.

Hoffmann, Reinmut K.

139

Integrated circuit tester evaluation study  

NASA Astrophysics Data System (ADS)

The primary AIMD test requirements for a small, inexpensive, commercially available, digital IC tester could be met by only one tester. This was the Automatic Fault Isolation Tester (AFIT) model 2050 manufactured by Testline Co. Many other testers were available that had the basic testing capability but were outside the price constraints or that were edge board testers. Bed-of-nails testers were not considered for AIMD use. The AFIT was submitted for technical and User Evaluations and demonstrated that it could detect faulty IC's on PC boards not coated with a conformal moisture-proofing compound. This fault detection ability was demonstrated for both the in-circuit and out-of-circuit modes of operation.

Stevens, P.

1980-03-01

140

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.  

PubMed

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits. PMID:19940239

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

141

Gyrator employing field effect transistors  

NASA Technical Reports Server (NTRS)

A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Hochmair, E. S. (inventor)

1973-01-01

142

Design methodologies for silicon photonic integrated circuits  

NASA Astrophysics Data System (ADS)

This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.

Chrostowski, Lukas; Flueckiger, Jonas; Lin, Charlie; Hochberg, Michael; Pond, James; Klein, Jackson; Ferguson, John; Cone, Chris

2014-03-01

143

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits  

NASA Technical Reports Server (NTRS)

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

1975-01-01

144

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz  

NASA Technical Reports Server (NTRS)

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

145

Test Structures For Bumpy Integrated Circuits  

NASA Technical Reports Server (NTRS)

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Buehler, Martin G.; Sayah, Hoshyar R.

1989-01-01

146

Single-charge transistor based on the charge-phase duality of a superconducting nanowire circuit.  

PubMed

We propose a transistorlike circuit including two serially connected segments of a narrow superconducting nanowire joint by a wider segment with a capacitively coupled gate in between. This circuit is made of amorphous NbSi film and embedded in a network of on-chip Cr microresistors ensuring a sufficiently high external electromagnetic impedance. Assuming a virtual regime of quantum phase slips (QPS) in two narrow segments of the wire, leading to quantum interference of voltages on these segments, this circuit is dual to the dc SQUID. Our samples demonstrated appreciable Coulomb blockade voltage (analog of critical current of the SQUIDs) and periodic modulation of this blockade by an electrostatic gate (analog of flux modulation in the SQUIDs). The model of this QPS transistor is discussed. PMID:22463659

Hongisto, T T; Zorin, A B

2012-03-01

147

Terminal modeling of hardened integrated circuits  

NASA Astrophysics Data System (ADS)

Kleiner et al. (1979) have reported modeling and test verification techniques used to develop medium-scale, dielectrically isolated integrated circuits (DIIC). The current investigation is concerned with the approaches employed in modeling the new circuits for applications studied by design and radiation hardening engineers. The described technique improves significantly the cost-effective application of computer programs such as SYSCAP II. The terminal model offers the designer of radiation-hardened electronic circuits a method for evaluating the effects of radiation transients on single or multiple piece-part response at the circuit board level. Although the models presented were intended for TREE design and analysis, it is possible to extend the technique to EMP and SGEMP evaluations.

Kleiner, C. T.; Haas, R.; Peacock, M.; Mandel, G.; Messenger, G. C.; Weakley, D.; Demartino, V.

1981-12-01

148

Polymer gate dielectric pentacene TFTs and circuits on flexible substrates  

Microsoft Academic Search

We have fabricated organic thin film transistors (TFTs) and integrated circuits on flexible polymeric substrates with solution-processed polymer gate dielectric layers and obtained transistors with excellent electrical characteristics, as well as 5-stage ring oscillators with signal propagation delay as low as 22 ?sec per stage. To our knowledge, these are the fastest integrated circuits with organic transistors on flexible substrates

Hagen Klauk; Marcus Halik; Ute Zschieschang; Giinter Schmid; Wolfgang Radlik; Ralf Brederlow; Sylvain Briole; Christian Pacha; Roland Thewes; Werner Weber

2002-01-01

149

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.  

PubMed

Ambipolar ?-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (?4.1 eV) compared to that of a pristine Au electrode (?4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ?0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ?0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ?12 kHz) based on a solution-processed ambipolar polymer are demonstrated. PMID:21805991

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

150

Microwave integrated circuit for Josephson voltage standards  

NASA Technical Reports Server (NTRS)

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

Holdeman, L. B.; Toots, J.; Chang, C. C. (inventors)

1980-01-01

151

A CCD integrated circuit for transient recorders  

NASA Technical Reports Server (NTRS)

A 50 MHz CCD integrated circuit is described that was developed for use in transient analog signal recorders to sample and time expand transient signals. The integrated circuit achieves an effective 200 MHz sample rate by using four 32 stage peristaltic CCDs to sample the transient signal four times each clock period. Dual frequency, 4 phi clocking is used to sample and time expand the sampled data. The output signals of the four CCDs are multiplexed on chip into a single low frequency output data line. When operated with 50 MHz/165 KHz 4 phi clocks, this circuit has a 200 MHz sample rate, a record length of 640 nanoseconds, a time expansion factor of 303, and overall signal to noise ratio of 40:1. The signal to noise ratio is limited by fixed pattern noise of the four CCDs.

Balch, J. W.; Mcconaghy, C. F.

1976-01-01

152

Healing Voids In Interconnections In Integrated Circuits  

NASA Technical Reports Server (NTRS)

Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

1989-01-01

153

Towards an EMC roadmap for Integrated Circuits  

Microsoft Academic Search

The following document gathers a collection of information and trends about integrated circuit (IC) technology to build a tentative roadmap for ElectroMagnetic Compatibility (EMC) of ICs until year 2020, with focus on embedded system-on-chip (SoC) for automotive and consumer electronics applications.

M. Ramdani; E. Sicard; S. Ben Dhia; J. Catrysse

2008-01-01

154

Nanotechnology High-speed integrated nanowire circuits  

Microsoft Academic Search

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate

Robin S. Friedman; Michael C. McAlpine; David S. Ricketts; Donhee Ham; Charles M. Lieber

2005-01-01

155

The development of Taiwan's integrated circuit industry  

Microsoft Academic Search

The development of Taiwan's integrated circuit (IC) industry is discussed in four sections covering the history of industry. The performance of the industry, the trends and development activities, and the future challenges. The latest data describing the industry are provided by Taiwan ERSO\\/ITRI ITIS project. The data cover the operations, marketing and technology indices, industry development goals, and investment trends

Michael M. K. Lin; Charles V. Trappey

1997-01-01

156

Package Holds Five Monolithic Microwave Integrated Circuits  

NASA Technical Reports Server (NTRS)

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

157

Assembly and packaging technology for integrated circuits  

Microsoft Academic Search

The electrical interconnections of semiconductor integrated circuit devices are manufactured by bonding fine-diameter wires to peripherally located thin film pads of aluminum, which make ohmic contact with the functional structures of the semiconductor. The aluminum or gold bonded wires are attached to their bond pads by ultrasonic, thermocompression or thermosonic techniques, and their outer ends are similarly bonded to a

A. S. Rose

1982-01-01

158

Thin Ferrite Devices for Microwave Integrated Circuits  

Microsoft Academic Search

This paper is intended as a review of developments which allow ferrite materials in a planar geometry to be used in the realization of magnetic devices which are compatible in form with other microwave integrated circuits. These devices include phase shifters (reciprocal and nonreciprocal), latching circulators, isolators, and phase and amplitude modulators. The application of some of these devices is

G. T. Roome; H. A. Hair

1968-01-01

159

Thin ferrite devices for microwave integrated circuits  

Microsoft Academic Search

This paper is intended as a review of developments which allow ferrite materials in a planar geometry to be used in the realization of magnetic devices which are compatible in form with other microwave integrated circuits. These devices include phase shifters (reciprocal and nonreciprocal), latching circulators, isolators, and phase and amplitude modulators. The application of some of these devices is

G. T. Roome; H. A. Hair

1968-01-01

160

Integrated optical interconnections on printed circuit boards  

Microsoft Academic Search

The development of integrated optical interconnections (IOIs) represents a quantum leap for the functionality of printed circuit boards (PCBs). This new technology will allow highly complex product features and hence, higher product added value. PCBs with optical interconnections will be used where applications call either for very high data streams between components, modules or functional units (e.g. backplanes or multiprocessor

Markus Riester; Gregor Langer; Günther Leising

2007-01-01

161

Radiation effects on power integrated circuits  

Microsoft Academic Search

A study was initiated to investigate the effects of gamma (total ionizing dose), prompt gamma (gamma dot), and neutron radiation on commercially available power integrated circuits (PIC's). A Dielectric Isolated (DI) Bipolar-CMOS-DMOS (BCDMOS) technology developed at AT and T Bell Laboratories was selected for this characterization. Total ionizing dose testing resulted in device failure at 30 krads (Si). Gamma dot

M. N. Darwish; M. C. Dolly; C. A. Goodwin; J. L. Titus

1988-01-01

162

Failure Analysis of Minuteman Integrated Circuit Failures.  

National Technical Information Service (NTIS)

This program was devoted to the determination of the failure modes and to a study of the failure mechanisms in integrated circuits used in the Minuteman II control and guidance system. In-depth failure analyses were performed on 114 rejects from system eq...

P. J. Besser A. B. Menefee P. H. Eisenberg

1968-01-01

163

Electromigration tests on Sandia integrated circuits  

SciTech Connect

Accelerated aging studies have been conducted on a Sandia produced integrated circuit, the ELA II test chip, to identify relevant aluminum metallization failure modes, and to delineate operating conditions which can adversely affect high reliability operation. Results from dc, ac and pulsed current tests show no significant long term reliability problems, and that the Sandia product is comparable to that produced by industry.

Arzigian, J.S.

1983-03-01

164

An Integrated Circuit for Remote Control Receivers  

Microsoft Academic Search

A monolithic silicon integrated circuit has been developed to perform the amplifier function in ultrasonic remote control systems. The integrated three-stage amplifier provides 120 dB gain in the 40 kHz range with excellent stability, low noise and desirable limiting properties. Internal biasing is used to achieve temperature and voltage stability while external interstage coupling capacitors enable design of the overall

L. A. Harwood

1967-01-01

165

Four-Thin Film Transistor Pixel Electrode Circuits for Active-Matrix Organic Light-Emitting Displays  

Microsoft Academic Search

Constant-current, four-thin-film-transistor (TFT) pixel electrode circuits, based on hydrogenated amorphous silicon (a-Si:H) TFT technology for active-matrix organic light-emitting displays (AM-OLEDs), have been designed, fabricated, and characterized. Experimental results indicate that continuous pixel electrode excitation can be achieved with these circuits. The pixel electrode circuits use a current driver to automatically adjust their current level for threshold voltage shifts of both

Yi He; Reiji Hattori; Jerzy Kanicki

2001-01-01

166

Electrothermal Analysis of Three-Dimensional Integrated Circuits  

NASA Astrophysics Data System (ADS)

Transient electro-thermal simulation of a three dimensional integrated circuit (3DIC) is reported that uses a cell-based simulation to provide a selected transistor thermal profile while providing advantages of hierarchical simulation. Due to CPU and memory limitations, full transistor electro-thermal simulations on a useful scale are not possible. Standard cells are considered on a per-instance basis and modeled with electro-thermal macro-models developed in a multi-physics simulator. Simulations are compared favorably to measurements for a token-generating 3DIC clocking at a maximum of 1 GHz. The 3DIC, which is composed of 9 by 3 layers of repetitive frequency multipliers and dividers, was fabricated with the Massachusetts Institute of Technology Lincoln Laboratory (MITLL) 3DIC process. Measurements indicated a linear rise in temperature of the active areas over a range of applied background ambient temperatures. An average of 7.5 K change in temperature was measured across dense areas of circuitry. For thermal simulation, the physical characteristics of the 3DIC were extracted from flattened OpenAccess layout files. Material parameters, connections, and geometries were considered in order to create a more physically accurate resistive thermal mesh. Physical thermal networks extracted with resolutions of 10 mum and 5 mum connect thermal terminals of the electrothermal macromodel cell elements to active layers yielding temporal and spatial simulated dynamic thermal results in three dimensions. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.

Harris, Theodore Robert

167

SEMICONDUCTOR INTEGRATED CIRCUITS: Realization of an analog predistortion circuit for RF optical fiber links  

NASA Astrophysics Data System (ADS)

This paper presents an analog predistortion circuit for RF optical fiber links. The circuit consists of two source-coupled differential transconductance amplifiers which could provide linear and nonlinear transfer characteristics by adjusting the bias voltage and the transistor sizes. The circuit was designed and realized in a standard 0.18-?m CMOS technology of SMIC. The chip occupies 0.48 × 0.24 mm2. The DC supply is 3.3 V. Using this circuit, the third-order intermodulation distortion (IMD) suppression of a directly modulated RF optical fiber link can be improved by 9-16 dBc at relatively low cost.

Xuenong, Tian; Zhigong, Wang; Wei, Li

2009-11-01

168

Ambipolar MoTe2 transistors and their applications in logic circuits.  

PubMed

We report ambipolar charge transport in ?-molybdenum ditelluride (MoTe2 ) flakes, whereby the temperature dependence of the electrical characteristics was systematically analyzed. The ambipolarity of the charge transport originated from the formation of Schottky barriers at the metal/MoTe2 contacts. The Schottky barrier heights as well as the current on/off ratio could be modified by modulating the electrostatic fields of the back-gate voltage (Vbg) and drain-source voltage (Vds). Using these ambipolar MoTe2 transistors we fabricated complementary inverters and amplifiers, demonstrating their feasibility for future digital and analog circuit applications. PMID:24692079

Lin, Yen-Fu; Xu, Yong; Wang, Sheng-Tsung; Li, Song-Lin; Yamamoto, Mahito; Aparecido-Ferreira, Alex; Li, Wenwu; Sun, Huabin; Nakaharai, Shu; Jian, Wen-Bin; Ueno, Keiji; Tsukagoshi, Kazuhito

2014-05-28

169

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors  

Microsoft Academic Search

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance\\u000a (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate\\u000a ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron\\u000a Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate

Vinay Saripalli; Vijay Narayanan; Suman Datta

2009-01-01

170

Total dose and dose rate models for bipolar transistors in circuit simulation.  

SciTech Connect

The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

Campbell, Phillip Montgomery; Wix, Steven D.

2013-05-01

171

A mixed-level modeling and simulation for digital MOS integrated circuits  

Microsoft Academic Search

This dissertation deals with techniques of a fast and accurate simulation tool for digital integrated circuits composed of metal-oxide-semiconductor (MOS) transistors. The demand for high performance and accuracy of digital logic simulation has led to the development of a logic simulator that is capable of handling two levels of models: gate and switch. This mixed-level approach attempts to high performance,

Kong

1989-01-01

172

Integrated-Circuit Active Digital Filter  

NASA Technical Reports Server (NTRS)

Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

Nathan, R.

1986-01-01

173

Stretchable and Foldable Silicon Integrated Circuits  

NASA Astrophysics Data System (ADS)

We have developed a simple approach to high-performance, stretchable, and foldable integrated circuits. The systems integrate inorganic electronic materials, including aligned arrays of nanoribbons of single crystalline silicon, with ultrathin plastic and elastomeric substrates. The designs combine multilayer neutral mechanical plane layouts and “wavy” structural configurations in silicon complementary logic gates, ring oscillators, and differential amplifiers. We performed three-dimensional analytical and computational modeling of the mechanics and the electronic behaviors of these integrated circuits. Collectively, the results represent routes to devices, such as personal health monitors and other biomedical devices, that require extreme mechanical deformations during installation/use and electronic properties approaching those of conventional systems built on brittle semiconductor wafers.

Kim, Dae-Hyeong; Ahn, Jong-Hyun; Choi, Won Mook; Kim, Hoon-Sik; Kim, Tae-Ho; Song, Jizhou; Huang, Yonggang Y.; Liu, Zhuangjian; Lu, Chun; Rogers, John A.

2008-04-01

174

Estimation Of Charge Transport Parameters And Equivalent Circuit For Poly Alkyl Thiophene Field-Effect Transistors  

NASA Astrophysics Data System (ADS)

The small signal ac response is measured across the source-drain terminals of organic field-effect transistors (OFET) under dc bias to obtain the equivalent circuit parameters of poly (2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT) and poly(3-hexyl thiophene) (P3HT) based devices. The numerically simulated response based on these parameters is in good agreement with the experimental data for PBTTT-FET except at low frequencies, while the P3HT-FET data show significant deviations. This indicates that the interface with the metal electrode is rather complex for the latter, involving additional circuit elements arising from contact impedance or charge injection processes. Such an investigation can help in identifying the operational bottlenecks and to improve the performance of OFETs.

Sangeeth, C. S. Suchand; Jaiswal, Manu; Menon, Reghu

2010-12-01

175

Functional integration of membrane proteins with nanotube and nanowire transistor devices.  

PubMed

Biological molecules perform a sophisticated array of transport and signaling functions that rival anything that the modern electronics industry can create. Incorporating such building blocks into nanoelectronic devices could enable new generations of electronic circuits that use biomimetics to perform complicated tasks. Such types of circuits could ultimately blur the interface between living biological organisms and synthetic structures. Our laboratory has recently developed a versatile and flexible platform for integrating ion channels and pumps into single-walled carbon nanotube (SWNT) and silicon nanowire (SiNW) transistor devices, in which membrane proteins are embedded in a lipid bilayer shell covering the nanotube or nanowire component. In this chapter, we provide details for the fabrication of these devices and outline procedures for incorporating biological molecules into them. In addition, we also provide several examples of the use of these devices to couple biological transport to electronic signaling. PMID:21674353

Noy, Aleksandr; Artyukhin, Alexander B; Huang, Shih-Chieh; Martinez, Julio A; Misra, Nipun

2011-01-01

176

N p n bipolar-junction-transistor detector with integrated p n p biasing transistor—feasibility study, design and first experimental results  

NASA Astrophysics Data System (ADS)

We propose a novel n-p-n BJT radiation detector on high-resistivity silicon with integrated p-n-p transistor providing the quiescent base current of the detector. The dc operational limits of the proposed detector are analysed by means of numerical device simulations, pointing out that, by properly distancing the base of the p-n-p transistor from the emitter of the n-p-n detector, the latch-up of the parasitic thyristor embedded within the detector-plus-biasing-transistor structure takes place at relatively high current levels, where detector operation should anyway be avoided in order to prevent the associated current-gain loss. Numerical simulations provides insight about the bias dependence of charge-collection waveforms, indicating that minimization of the collecting time requires the detector quiescent current to be adjusted at the highest value still allowing high-injection effects to be avoided. A small-signal equivalent circuit of the proposed structure is also derived, allowing the impact of p-n-p biasing transistor and load resistance on the charge-collecting time constant to be evaluated. First experimental results show that fabricated structures are immune from the latch-up of the parasitic thyristor throughout their high-current-gain operating region and feature a minimum charge-collecting time constant of 35 µs, as tested by pulsed laser illumination.

Verzellesi, Giovanni; Bergamini, Davide; Dalla Betta, Gian-Franco; Piemonte, Claudio; Boscardin, Maurizio; Bosisio, Luciano; Bettarini, Stefano; Batignani, Giovanni

2006-02-01

177

Applying analog integrated circuits for HERO protection  

NASA Technical Reports Server (NTRS)

One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

Willis, Kenneth E.; Blachowski, Thomas J.

1994-01-01

178

Tomographic reconstruction of an integrated circuit interconnect  

SciTech Connect

An Al{endash}W-silica integrated circuit interconnect sample was thinned to several {mu}m and scanned across a 200 nm focal spot of a Fresnel zone plate operating at photon energy of 1573 eV. The experiment was performed on beamline 2-ID-B of the Advanced Photon Source, a third-generation synchrotron facility. Thirteen scanned projections of the sample were acquired over the angular range {plus_minus}69.2{degree}. At least 301{times}301 pixels were acquired at each angle with a step size of 77{times}57 nm. A three-dimensional image with an approximate uncertainty of 400 nm was reconstructed from projection data using a standard algorithm. The two layers of the integrated circuit and the presence of the focused ion beam markers on the surface of the sample are clearly shown in the reconstruction. {copyright} {ital 1999 American Institute of Physics.}

Levine, Z.H. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States)] [National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Kalukin, A.R. [Physics Department, Rensselaer Polytechnic Institute, Troy, New York 12180-3590 (United States)] [Physics Department, Rensselaer Polytechnic Institute, Troy, New York 12180-3590 (United States); Frigo, S.P.; McNulty, I. [Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois 60439 (United States)] [Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois 60439 (United States); Kuhn, M. [Digital Equipment Corporation, Hudson, Massachusetts 01749 (United States)] [Digital Equipment Corporation, Hudson, Massachusetts 01749 (United States)

1999-01-01

179

Robotic workcell for wire wrapping integrated circuits  

NASA Astrophysics Data System (ADS)

A robotic workcell was developed that electrically shorts the leads of integrated circuits by weaving a 0.005-in. copper wire around individual leads. This workcell has the capability to manipulate 13 different integrated circuit body styles including 14- to 64-lead flatpacks, 14- to 40-pin dual inline packages, and 3- to 10-pin cans. Features of the system include automatic program selection based on the particular body style provided, combined with automatic modification of the program to compensate for subtle differences between components supplied by various manufacturers of a given body style. Additionally, the workcell prepared and packages devices for storage by placing conductive foam on the leads of the device, inserting the device/foam into a plastic bag, and heat sealing the bag.

Law, D. O.

1992-05-01

180

Thermal analysis of vertically integrated circuits  

Microsoft Academic Search

In this paper, a thermal analysis of Vertically Integrated Circuits (VIC) is presented for the first time. Based on a 1-D model, temperature differences in VICs of less than 10°C are evaluated for most practical applications. Detailed 3-D investigations show that self-heating of MOSFETs in the upper chip-layers of a VIC is more pronounced than in bulk CMOS and that

M. B. Kleiner; S. A. Kuhn; P. Ramm; W. Weber

1995-01-01

181

Radiation effects on power integrated circuits  

Microsoft Academic Search

A study was initiated to investigate the effects of gamma (total ionizing dose), prompt gamma (gamma-dot), and neutron radiation on commercially available power integrated circuits. A dielectric-isolated bipolar-CMOS-DMOS (BCDMOS) technology was selected for this characterization. Total-ionizing-dose testing resulted in device failure at 30 krad(Si). Gamma-dot testing (30-ns pulsewidth) resulted in device failure due to transient upset of the CMOS logic

Mohamed N. Darwish; Martin C. Dolly; Charles A. Goodwin; Jeffrey L. Titus

1988-01-01

182

Top-down pass-transistor logic design  

Microsoft Academic Search

The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with

K. Yano; Y. Sasaki; K. Rikino; K. Seki

1996-01-01

183

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

184

Single-Event Upset and Snapback in Silicon-on-Insulator Devices and Integrated Circuits  

SciTech Connect

The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

DODD,PAUL E.; SHANEYFELT,MARTY R.; WALSH,DAVID S.; SCHWANK,JAMES R.; HASH,GERALD L.; LOEMKER,RHONDA ANN; DRAPER,BRUCE L.; WINOKUR,PETER S.

2000-08-15

185

The Future of Integrated Circuits: A Survey of Nanoelectronics  

Microsoft Academic Search

While most of the electronics industry is dependent on the ever-decreasing size of lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits built with components on the scale of 10 nm) seem to be the most promising successor to lithographic based ICs. Molecular-scale devices including diodes, bistable switches, carbon nanotubes, and nanowires have been fabricated and characterized in chemistry labs.

Michael Haselman; Scott Hauck

2010-01-01

186

Power system with an integrated lubrication circuit  

DOEpatents

A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

Hoff, Brian D. (East Peoria, IL) [East Peoria, IL; Akasam, Sivaprasad (Peoria, IL) [Peoria, IL; Algrain, Marcelo C. (Peoria, IL) [Peoria, IL; Johnson, Kris W. (Washington, IL) [Washington, IL; Lane, William H. (Chillicothe, IL) [Chillicothe, IL

2009-11-10

187

A new pixel circuit for driving organic light-emitting diode with low temperature polycrystalline silicon thin-film transistors  

Microsoft Academic Search

A new pixel circuit design for active matrix organic light-emitting diode (AMOLED), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. Threshold voltage compensation pixel circuit consisting of four n-type TFTs, one p-type TFT, one additional control signal, and one storage capacitor is used to enhance display image quality. The simulation results show

Ya-Hsiang Tai; Bo-Ting Chen; Yu-Ju Kuo; Chun-Chien Tsai; Ko-Yu Chiang; Ying-Jyun Wei; Huang-Chung Cheng

2005-01-01

188

Four-Thin-Film-Transistor Pixel Circuit for Amorphous-Silicon Active-Matrix Organic Light-Emitting Diode Displays  

Microsoft Academic Search

Voltage-controlled pixel circuit with four thin-film-transistor (TFT) for amorphous-silicon (a-Si) active-matrix organic light-emitting diode (AM-OLED) displays has been designed, simulated and evaluated. Deviation and aging of the properties of the driver-TFT cause image sticking or degradation of image quality. These problems require compensation for high-quality display applications, and a pixel-level compensation circuit is one of the solutions. In this paper,

Shinya Ono; Yoshinao Kobayashi

2004-01-01

189

Vacuum die attach for integrated circuits  

DOEpatents

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

190

Vacuum die attach for integrated circuits  

DOEpatents

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

Schmitt, Edward H. (Livermore, CA); Tuckerman, David B. (Livermore, CA)

1991-01-01

191

General electromagnetic compatibility analysis for nonlinear microwave integrated circuits  

Microsoft Academic Search

The paper proposes a new solution to the standard electromagnetic compatibility problem for nonlinear RF\\/microwave integrated circuits. Radiation from the given circuit is first numerically analysed by means of electromagnetic simulation. Under the assumption of a uniform plane wave incident on the circuit, the reciprocity theorem is then used to characterize the linear subnetwork by a Norton equivalent circuit. Finally,

Vittorio Rizzoli; Alessandra Costanzo; Giuseppina Monti

2004-01-01

192

Integrating voice recognition technology with inspection of integrated circuits  

Microsoft Academic Search

Applying voice recognition technology to a manufacturing environment has provided an advanced and practical means of data collection. Accurate real-time data are gathered without the use of labor-intensive paperwork and data entry. In the manufacturing of integrated circuits at Motorola, voice technology has proved to be beneficial in the inspection process, where hands and eyes remain busy performing the primary

P. Gavaskar; E. Maass; L. Weldy; H. Nguyen

1990-01-01

193

Sequential circuit design for radiation hardened multiple voltage integrated circuits  

DOEpatents

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

2009-11-24

194

Vertically integrated silicon-germanium nanowire field-effect transistor  

NASA Astrophysics Data System (ADS)

We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ~ 1.2 × 1013 cm-2 eV-1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.

Rosaz, G.; Salem, B.; Pauc, N.; Potié, A.; Gentile, P.; Baron, T.

2011-11-01

195

Electro-optical Probing Of Terahertz Integrated Circuits  

NASA Technical Reports Server (NTRS)

Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

1990-01-01

196

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television  

NASA Astrophysics Data System (ADS)

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

Han, Sang-Kug; Choi, Hoon; Moon, Kyo-Ho; Choi, Young-Seok; Jeong, Kyung-Deuk; Park, Kwang-Mook; Choi, Sie-Young

2012-04-01

197

3D packaging for integrated circuit systems  

SciTech Connect

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

Chu, D.; Palmer, D.W. [eds.

1996-11-01

198

Integrated-Circuit Broadband Infrared Sources  

NASA Technical Reports Server (NTRS)

Microscopic devices consume less power, run hotter, and are more reliable. Simple, compact, lightweight, rapidly-responding reference sources of broadband infrared radiation made available by integrated-circuit technology. Intended primarily for use in calibration of remote-sensing infrared instruments, devices eventually replace conventional infrared sources. New devices also replace present generation of miniature infrared sources. Self-passivating nature of poly-crystalline silicon adds to reliability of devices. Maximum operating temperature is 1,000 K, and power dissipation is only one-fourth that of prior devices.

Lamb, G.; Jhabvala, M.; Burgess, A.

1989-01-01

199

Nobel Laureate e-Museum: Integrated Circuits  

NSDL National Science Digital Library

Nobel Laureate e-Museum's Educational section provides historical and scientific background information on inventions by those who have been honored with the Nobel Laureates in physics, chemistry, medicine, literature and peace over the years. For example, from this website, visitors can read about Nobel Laureate Jack Kilby and his part in the invention of integrated circuits, which are found in a variety of modern electrical device, including computers, cars, television sets, CD players, and cellular phones. A game called Techville is also free to download. A "walk through" will help you out if you get stuck on the game.

200

Low Temperature Polycrystalline Silicon Thin Film Transistor Pixel Circuits for Active Matrix Organic Light Emitting Diodes  

NASA Astrophysics Data System (ADS)

A new pixel design and driving method for active matrix organic light emitting diode (AMOLED) displays that use low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with a voltage programming method are proposed and verified using the SPICE simulator. We had employed an appropriate TFT model in SPICE simulation to demonstrate the performance of the pixel circuit. The OLED anode voltage variation error rates are below 0.35% under driving TFT threshold voltage deviation (? Vth =± 0.33V). The OLED current non-uniformity caused by the OLED threshold voltage degradation (? VTO =+0.33V) is significantly reduced (below 6%). The simulation results show that the pixel design can improve the display image non-uniformity by compensating for the threshold voltage deviation in the driving TFT and the OLED threshold voltage degradation at the same time.

Fan, Ching-Lin; Lin, Yu-Sheng; Liu, Yan-Wei

201

Pyroelectric/Integrated Circuit Infrared Imaging Array Development.  

National Technical Information Service (NTIS)

Progress made toward the development of pyroelectric/integrated circuit thermal imaging area arrays and their associated address and sense circuits is described. The processing techniques and steps required to form two-dimensional arrays of thin film trig...

A. Boornard D. Hall E. Herrmann R. D. Larrabee P. D. Southgate

1972-01-01

202

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design  

SciTech Connect

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents {le}1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier.

Kennedy, E.J. (Tennessee Univ., Knoxville, TN (USA) Oak Ridge National Lab., TN (USA)); Alley, G.T.; Britton, C.L. Jr. (Oak Ridge National Lab., TN (USA)); Skubic, P.L. (Oklahoma Univ., Norman, OK (USA)); Gray, B.; Wu, A. (Tennessee Univ., Knoxville, TN (USA))

1990-01-01

203

Integrated circuits and electrode interfaces for noninvasive physiological monitoring.  

PubMed

This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications. PMID:24759282

Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

2014-05-01

204

Si\\/SiGe epitaxial-base transistors. I. Materials, physics, and circuits  

Microsoft Academic Search

A detailed review of SiGe epitaxial base technology is presented, which chronicles the progression of research from materials deposition through device and integration demonstrations, culminating in the first SiGe integrated circuit application. In part I of this paper, the requirements and processes for high-quality SiGe film preparation are discussed, with emphasis on fundamental principles. A detailed overview of SiGe HBT

D. L. Harame; J. H. Comfort; J. D. Cressler; E. F. Crabbe; J. Y.-C. Sun; B. S. Meyerson; T. Tice

1995-01-01

205

Accurate pattern registration for integrated circuit tomography  

SciTech Connect

As part of an effort to develop high resolution microtomography for engineered structures, a two-level copper integrated circuit interconnect was imaged using 1.83 keV x rays at 14 angles employing a full-field Fresnel zone plate microscope. A major requirement for high resolution microtomography is the accurate registration of the reference axes in each of the many views needed for a reconstruction. A reconstruction with 100 nm resolution would require registration accuracy of 30 nm or better. This work demonstrates that even images that have strong interference fringes can be used to obtain accurate fiducials through the use of Radon transforms. We show that we are able to locate the coordinates of the rectilinear circuit patterns to 28 nm. The procedure is validated by agreement between an x-ray parallax measurement of 1.41{+-}0.17 {mu}m and a measurement of 1.58{+-}0.08 {mu}m from a scanning electron microscope image of a cross section.

Levine, Zachary H.; Grantham, Steven; Neogi, Suneeta; Frigo, Sean P.; McNulty, Ian; Retsch, Cornelia C.; Wang, Yuxin; Lucatorto, Thomas B.

2001-07-15

206

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets  

NASA Technical Reports Server (NTRS)

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Zoutendyk, John A. (inventor)

1991-01-01

207

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets  

NASA Astrophysics Data System (ADS)

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Zoutendyk, John A.

1991-12-01

208

Fabrication of a logic gate circuit based on ambipolar field-effect transistors with thin films of C 60 and pentacene  

NASA Astrophysics Data System (ADS)

Ambipolar field-effect transistor (FET) devices were fabricated with a heterostructure of C 60 and pentacene, and their p- and n-channel field-effect mobilities were studied as a function of thickness of pentacene thin-films. The observed dependences of the ? values were interpreted in terms of the morphology of the thin films and the band structure of C 60/pentacene heterostructure. A complementary metal-oxide-semiconductor (CMOS) circuit was fabricated by integration of two ambipolar FETs, aiming at realization of a new CMOS inverter circuit composed of FETs with the same device structure. The gain of four, the threshold voltage of 85 V, and the complex output characteristics were explained on the basis of the properties of the component FET devices.

Kuwahara, Eiji; Kusai, Haruka; Nagano, Takayuki; Takayanagi, Toshio; Kubozono, Yoshihiro

2005-09-01

209

Post irradiation effects (PIE) in integrated circuits  

NASA Technical Reports Server (NTRS)

Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

1991-01-01

210

Assembly and packaging technology for integrated circuits  

NASA Astrophysics Data System (ADS)

The electrical interconnections of semiconductor integrated circuit devices are manufactured by bonding fine-diameter wires to peripherally located thin film pads of aluminum, which make ohmic contact with the functional structures of the semiconductor. The aluminum or gold bonded wires are attached to their bond pads by ultrasonic, thermocompression or thermosonic techniques, and their outer ends are similarly bonded to a metal lead frame or to metallized substrates which achieve the circuitry's expansion from micro to macro dimensions. The metallurgical considerations affecting bond quality and reliability are related to the potential formation of intermetallic compounds and grain boundary deterioration in the wires and interfaces. The packaging used after the assembly operations described is primarily conducted in plastic or ceramic formats.

Rose, A. S.

1982-08-01

211

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits  

NASA Astrophysics Data System (ADS)

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Es-Sakhi, Azzedin D.

212

Integrated optical interconnections on printed circuit boards  

NASA Astrophysics Data System (ADS)

The development of integrated optical interconnections (IOIs) represents a quantum leap for the functionality of printed circuit boards (PCBs). This new technology will allow highly complex product features and hence, higher product added value. PCBs with optical interconnections will be used where applications call either for very high data streams between components, modules or functional units (e.g. backplanes or multiprocessor boards) or for a space-saving design for interconnection paths (e.g. mobile applications). We discuss the different approaches towards integrating optical waveguides into PCBs and analyze the prerequisites for a transfer to a product. Application scenarios for different markets are presented and steps proposed for required action to deliver solutions that can be driven into a market. In a second section a new and innovative concept for the integration of an optical interconnection system in PCBs is presented. This revolutionary concept is highly supporting the worldwide trend towards miniaturization of not only electronic but also optoelectronic systems in PCBs. The alignment of the optoelectronic components to the waveguides has been addressed by this concept. It is shown that the process will allow the tolerances incurred in the manufacturing processes to be dealt with in a separate process step, allowing existing standard methods for the production of electronic interconnection systems to be used.

Riester, Markus; Langer, Gregor; Leising, Günther

2007-03-01

213

Automatic establishment of equivalent circuits for integrated power devices  

Microsoft Academic Search

A computerized method of creating equivalent electrical circuits is presented for semiconductor structures, unit devices or integrated circuits. First, it is shown that in the case where only circuit topology is considered, a limited number of physical primitives (insulator, conductor, N or P semiconductors) and electrical primitives (diode, resistor, current sources) suffice to describe the structure and establish the functional

Veronique Liberos

1989-01-01

214

Integrated photo-responsive metal oxide semiconductor circuit  

NASA Technical Reports Server (NTRS)

An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

Jhabvala, Murzban D. (inventor); Dargo, David R. (inventor); Lyons, John C. (inventor)

1987-01-01

215

Subminiature deflection circuit operates integrated sweep circuits in TV camera  

NASA Technical Reports Server (NTRS)

Small magnetic sweep deflection circuits operate a hand-held lunar television camera. They convert timing signals from the synchronizer into waveforms that provide a raster on the vidicon target. Raster size remains constant and linear during wide voltage and temperature fluctuations.

Schaff, F. L.

1967-01-01

216

A semi-custom multi-channel preamplifier integrated circuit for nuclear instrumentation  

SciTech Connect

A monolithic eight-channel preamplifter for spaceborne nuclear instrumentation is being developed using a semi-custom Application Specific Integrated Circuit (ASIC) based on bipolar tile-array technology, This general purpose charge sensitive preamplifier was designed using a complimentary current mirror approach so that it would be useful for amplifying both positive-going and negative-going input pulses while consuming low to moderate power. The input stages employ a common-collector/common-base topology for good bandwidth and slew characteristics. The output stages employ power devices configured as class AB and are capable of driving 50-ohm loads. Each of the eight channels can be biased or enabled separately. The design is implemented with dielectrically isolated, vertical geometry transistors. Such devices are inherently radiation-hard and have PNP transistors whose performance is superior to the lateral geometry types. This paper describes a unique aspect of the design and computer simulation results of the ASIC.

Fuller, K.R.

1992-01-01

217

A semi-custom multi-channel preamplifier integrated circuit for nuclear instrumentation  

SciTech Connect

A monolithic eight-channel preamplifter for spaceborne nuclear instrumentation is being developed using a semi-custom Application Specific Integrated Circuit (ASIC) based on bipolar tile-array technology, This general purpose charge sensitive preamplifier was designed using a complimentary current mirror approach so that it would be useful for amplifying both positive-going and negative-going input pulses while consuming low to moderate power. The input stages employ a common-collector/common-base topology for good bandwidth and slew characteristics. The output stages employ power devices configured as class AB and are capable of driving 50-ohm loads. Each of the eight channels can be biased or enabled separately. The design is implemented with dielectrically isolated, vertical geometry transistors. Such devices are inherently radiation-hard and have PNP transistors whose performance is superior to the lateral geometry types. This paper describes a unique aspect of the design and computer simulation results of the ASIC.

Fuller, K.R.

1992-12-01

218

Plug-in integrated/hybrid circuit  

NASA Technical Reports Server (NTRS)

Hybrid circuitry can be installed into standard round bayonet connectors, to eliminate wiring from connector to circuit. Circuits can be connected directly into either section of connector pair, eliminating need for hard wiring to that section.

Stringer, E. J.

1974-01-01

219

50-200 GHz Silicon-Germanium Heterojunction Bipolar Transistor BICMOS Technology and a Computer-Aided Design Environment for 2--50+ GHz Very Large-Scale Integration Mixed-Signal ICs  

Microsoft Academic Search

Silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BICMOS technology is a stable, ultra-high performance, semiconductor technology capable of supporting mixed-signal, very large-scale integration (VLSI) circuit designs for a variety of emerging communication applications. This technology is supported by a computer-aided design (CAD) system that supports a variety of high-performance circuit designs, mixed-signal circuit block reuse, and the ability to accurately predict

Seshadri Subbanna; Gregory Freeman; Jae-Sung Rieh; David Ahlgren; Kenneth Stein; Carl Dickey; James Mecke; Peter Bacon; Robert Groves; Mounir Meghelli; Mehmet Soyuer; Basanth Jagannathan; Kathryn Schonenberg; Shwu-Jen Jeng; Alvin Joseph; Douglas Coolbaugh; Richard Volant; David Greenberg; Huajie Chen; Kevin Brelsford; David Harame; James Dunn; Lawrence Larson; Dean Herman Jr.; Bernard Meyerson

2002-01-01

220

SEMICONDUCTOR INTEGRATED CIRCUITS: A novel charge pump drive circuit for power MOSFETs  

NASA Astrophysics Data System (ADS)

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 ?m BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.

Songlin, Wang; Bo, Zhou; Qiang, Ye; Hui, Wang; Wangrui, Guo

2010-04-01

221

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits  

NASA Astrophysics Data System (ADS)

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 µm2 for the two-input NAND gate and 0.049 µm2 for the full adder circuits.

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2006-09-01

222

Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory  

NASA Astrophysics Data System (ADS)

A novel 7-transistor/2-magnetic-tunnel-junction (7 T-2MTJ) cell circuit is proposed for a high-speed and compact nonvolatile ternary content-addressable memory (TCAM). Since critical path for switching in the TCAM cell circuit, which determines the performance of the TCAM, is only a single MOS transistor, switching delay of the TCAM word circuit is minimized. As a result, 270 ps of switching delay in 144-bit TCAM word circuit is achieved under a 90 nm CMOS/MTJ technology with magneto-resistance ratio of 100%, which is about two times faster than a conventional CMOS-based TCAM.

Matsunaga, Shoun; Katsumata, Akira; Natsui, Masanori; Endoh, Tetsuo; Ohno, Hideo; Hanyu, Takahiro

2012-04-01

223

High-throughput high-density mapping and spectrum analysis of transistor gate length variations in SRAM circuits  

Microsoft Academic Search

High-throughput high-density mapping of gate length variations using static random-access memory (SRAM) as electronic test structures is reported. In the experiments, direct measurements of bit-line currents revealed the individual transistor gate length variations within every memory cell. With SRAM and its fast addressing circuits we can measure CD variations with measurement time as fast as 5 ?s per data point

Xu Ouyang; Tim Deeter; C. Neil Berglund; R. F. W. Pease; J. Lee; M. A. McCord

2001-01-01

224

Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic\\/Inorganic Double-Layer Insulator  

Microsoft Academic Search

Pentacene-based organic thin-film transistors (OTFTs) and organic circuits are fabricated using a plasma-enhanced chemical vapor deposition (PECVD) SiO2\\/cross-linked poly(vinyl alcohol) (PVA) double-layer insulator. A considerable reduction in hysteresis is achieved by optimizing the double-layer insulator thickness. The main mechanism of a low hysteresis is attributed to the balance of the injected electrons and induced holes at the interface. The fabricated

Dong-Wook Park; Cheon An Lee; Keum-Dong Jung; Byeong-Ju Kim; Byung-Gook Park; Hyungcheol Shin; Jong Duk Lee

2007-01-01

225

Four-Thin-Film-Transistor Pixel Circuit for Amorphous-Silicon Active-Matrix Organic Light-Emitting Diode Displays  

NASA Astrophysics Data System (ADS)

Voltage-controlled pixel circuit with four thin-film-transistor (TFT) for amorphous-silicon (a-Si) active-matrix organic light-emitting diode (AM-OLED) displays has been designed, simulated and evaluated. Deviation and aging of the properties of the driver-TFT cause image sticking or degradation of image quality. These problems require compensation for high-quality display applications, and a pixel-level compensation circuit is one of the solutions. In this paper, we propose a novel and suitable circuit for a-Si AM-OLED displays. The circuit is composed of four TFTs and a storage capacitor, and its driving scheme has four periods: preparation, programming threshold voltage (VT), writing data, and emission. It is possible to set a long detection time for the threshold-voltage of driver-TFT in each pixel, so it can compensate precisely for deviations and the aging of the threshold voltage.

Ono, Shinya; Kobayashi, Yoshinao

2004-12-01

226

A TDC integrated circuit for drift chamber readout  

Microsoft Academic Search

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start\\/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 ?m CMOS technology, with 1 ns LSB realized using a

M. Passaseo; E. Petrolo; S. Veneziano

1995-01-01

227

Nanowire transistor arrays for mapping neural circuits in acute brain slices.  

PubMed

Revealing the functional connectivity in natural neuronal networks is central to understanding circuits in the brain. Here, we show that silicon nanowire field-effect transistor (Si NWFET) arrays fabricated on transparent substrates can be reliably interfaced to acute brain slices. NWFET arrays were readily designed to record across a wide range of length scales, while the transparent device chips enabled imaging of individual cell bodies and identification of areas of healthy neurons at both upper and lower tissue surfaces. Simultaneous NWFET and patch clamp studies enabled unambiguous identification of action potential signals, with additional features detected at earlier times by the nanodevices. NWFET recording at different positions in the absence and presence of synaptic and ion-channel blockers enabled assignment of these features to presynaptic firing and postsynaptic depolarization from regions either close to somata or abundant in dendritic projections. In all cases, the NWFET signal amplitudes were from 0.3-3 mV. In contrast to conventional multielectrode array measurements, the small active surface of the NWFET devices, approximately 0.06 microm(2), provides highly localized multiplexed measurements of neuronal activities with demonstrated sub-millisecond temporal resolution and, significantly, better than 30 microm spatial resolution. In addition, multiplexed mapping with 2D NWFET arrays revealed spatially heterogeneous functional connectivity in the olfactory cortex with a resolution surpassing substantially previous electrical recording techniques. Our demonstration of simultaneous high temporal and spatial resolution recording, as well as mapping of functional connectivity, suggest that NWFETs can become a powerful platform for studying neural circuits in the brain. PMID:20133836

Qing, Quan; Pal, Sumon K; Tian, Bozhi; Duan, Xiaojie; Timko, Brian P; Cohen-Karni, Tzahi; Murthy, Venkatesh N; Lieber, Charles M

2010-02-01

228

Post irradiation effects (PIE) in integrated circuits [MOS  

Microsoft Academic Search

Post Irradiation Effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. These variations indicate that a rebound or PIE `recipe' used for radiation hardness assurance must be chosen with care. This paper provides examples of PIE in a variety of integrated circuits of importance to spacecraft electronics

C. E. Barnes; D. M. Fleetwood; D. C. Shaw; P. S. Winokur

1991-01-01

229

Investigation of quantum effects in monolithic integrated circuits based on RTDs and HEMTs with a quantum hydrodynamic transport model  

Microsoft Academic Search

This paper describes the first reported numerical simulations of monolithic integrated circuits of resonant tunneling structures and high electron mobility transistors based on In0.53Ga0.47As\\/In0.52Al0.48As\\/InP with a quantum hydrodynamic transport model (QHD-Model). For the numerical investigations the device simulator SIMBA is used, which is capable to handle complex device geometries as well as various physical models represented by certain sets of

J. Hontschel; W. Klix; R. Stenzel

2003-01-01

230

A Lithographic Process for Integrated Organic Field-Effect Transistors  

Microsoft Academic Search

This paper reports a photolithographic process for fabricating organic field-effect transistors which provides two layers of metal with arbitrary via placement, and optionally allows for subtractive lithographic patterning of the transistor active layer. The demonstrated pentacene transistors have a field-effect mobility of 0.1±0.05 cm2\\/(V·s). Parylene-C is used both as the gate dielectric and an encapsulation layer which allows for subtractive

Ioannis Kymissis; Akintunde Ibitayo Akinwande; Vladimir Bulovic

2005-01-01

231

Integrated capacitors for conductive lithographic film circuits  

Microsoft Academic Search

This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielectric layer, which separates the printed

Paul M. Harrey; Peter S. A. Evans; David J. Harrison

2001-01-01

232

Thin-Film Microwave Integrated Circuits  

Microsoft Academic Search

There has been an increase in the use of thin-film technology for the preparation of microwave circuits since it permits the realization of very complex circuitry with precision, reliability, and economy. The requirements for the realization of such circuits have made it necessary to extend the state of the art of the hybrid technology in many areas. Two new substrate

VICTOR S. ARAMATI; J. SAMUEL BITLER; ARNOLD PFAHNL; C. C. SHIFLETT

1976-01-01

233

Practical applications of digital integrated circuits. Part 4: Hybrid digital integrated circuits  

NASA Technical Reports Server (NTRS)

The 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Clock generators, waveform generation, signal shaping and conditioning, digital to analog conversion, and analog to digital conversion are discussed.

1974-01-01

234

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits.  

PubMed

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at V(DD) = 80 V (70% of 1/2V(DD)) and a gain of 85. Additionally, robust SWNT complementary metal-oxide-semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C-K; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-04-01

235

Experimental determination of single-event upset (SEU) as a function of collected charge in bipolar integrated circuits  

NASA Technical Reports Server (NTRS)

Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.

Zoutendyk, J. A.; Malone, C. J.; Smith, L. S.

1984-01-01

236

SEMICONDUCTOR INTEGRATED CIRCUITS: 4 GHz bit-stream adder based on ?? modulation  

NASA Astrophysics Data System (ADS)

The conventional circuit model of a bit-stream adder based on sigma delta (??) modulation is improved with pipeline technology to make it work correctly at high frequencies. The integrated circuit (IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency. The IC is fabricated in TSMC's 0.18-?m CMOS process. The chip area is 475 × 570 ?m2. A fully digital ?? signal generator is designed with a field programmable gate array to test the chip. Experimental results show that the chip meets the function and performance demand of the design, and the chip can work at a frequency of higher than 4 GHz. The noise performance of the adder is analyzed and compared with both theory and experimental results.

Yong, Liang; Zhigong, Wang; Qiao, Meng; Xiaodan, Guo

2010-08-01

237

Nanophotonic integrated circuits from nanoresonators grown on silicon.  

PubMed

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits. PMID:24999601

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-01-01

238

W-band multiport substrate-integrated waveguide circuits  

Microsoft Academic Search

Millimeter-wave passive circuits that are designed and fabricated in the form of substrate-integrated waveguide (SIW) are presented in this paper. A W-band SIW 90° hybrid coupler and multiport SIW circuit are made and synthesized on alumina substrate using metallized slot arrays. In order to connect the SIW circuits with WR-10 standard rectangular waveguides for measurement purposes, a new transition is

Emilia Moldovan; Renato G. Bosisio; Ke Wu

2006-01-01

239

A survey of optimization techniques for integrated-circuit design  

NASA Astrophysics Data System (ADS)

Contemporary optimization techniques are surveyed and related to optimization problems which arise in the design of integrated circuits. Theory, algorithms, and programs are reviewed, and an assessment is made of the impact optimization has had and will have on integrated-circuit design. Integrated circuits are characterized by complex tradeoffs between multiple nonlinear objectives with multiple nonlinear and sometimes nonconvex constraints. Function and gradient evaluations require the solution of very large sets of nonlinear differential equations; consequently they are inaccurate and extremely expensive. Futhermore, the parameters to be optimized are subject to inherent statistical fluctuations. Particular emphasis is given to those multiobjective constrained optimization techniques which are appropriate to this environment.

Brayton, R. K.; Hachtel, G. D.; Sangiovanni-Vincentelli, A. L.

1981-10-01

240

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...  

Federal Register 2010, 2011, 2012, 2013

...Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and products...States after importation of certain semiconductor integrated circuit devices and...

2012-05-01

241

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...  

Federal Register 2010, 2011, 2012, 2013

...TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and Products...received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and...

2012-03-29

242

77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...  

Federal Register 2010, 2011, 2012, 2013

...No. 337-TA-848] Certain Radio Frequency Integrated Circuits and Devices...after importation of certain radio frequency integrated circuits and devices...after importation of certain radio frequency integrated circuits and...

2012-06-13

243

Modeling of amorphous-silicon thin-film transistors for circuit simulations with SPICE  

Microsoft Academic Search

A static and dynamic model for amorphous silicon thin-film transistors is presented. The theory is based on an assumed exponential distribution of the deep states and the tail states in the energy gap. Expressions are derived that link the density of the localized states and the temperature to the drain current and the distribution of the charge in the transistor

Karim Khakzar; Ernst H. Lueder

1992-01-01

244

Integrated electrochemical transistor as a fast recoverable gas sensor.  

PubMed

A new design of conductometric chemical sensors based on conducting polymers as chemosensitive elements was suggested. The sensor includes six electrodes. Four inner electrodes coated by chemosensitive polymer are used for simultaneous two- and four-point resistance measurements thus providing information on the bulk polymer resistance and on the resistance of the polymer/electrode contacts. Two outer electrodes wired to inner electrodes by polymeric electrolyte are used for electrical control of redox state of the chemosensitive polymer. The outer electrodes are connected to potentiostat as reference and counter electrodes. It allows us to control redox state of the inner (working) electrodes. This new measurement configuration, resembling chemosensitive electrochemical transistors, provides an internal test of the sensor integrity and an electrically driven sensor regeneration. It was tested as a sensor for the detection of nitrogen dioxide. Polythiophene or polyaniline was used as receptors. Cyclic voltammograms of these polymers on the sensor surface measured in air atmosphere were very similar to that measured in aqueous electrolyte. A control of conductivity of these chemosensitive polymers by electrical potential applied vs. incorporated reference electrode was demonstrated. This effect was used for the regeneration of the chemosensitive material after exposure to nitrogen dioxide: in comparison to usual chemiresistors displaying an irreversible behavior in such test even in the time scale of hours, a completely reversible sensor regeneration within few minutes was observed. PMID:21241841

Lange, Ulrich; Mirsky, Vladimir M

2011-02-14

245

Fully printed separated carbon nanotube thin film transistor circuits and its application in organic light emitting diode control.  

PubMed

The advantages of printed electronics and semiconducting single-walled carbon nanotubes (SWCNTs) are combined for the first time for display electronics. Conductive silver ink and 98% semiconductive SWCNT solutions are used to print back-gated thin film transistors with high mobility, high on/off ratio, and high current carrying capacity. In addition, with printed polyethylenimine with LiClO4 as the gating material, fully printed top-gated devices have been made to work as excellent current switches for organic light emitting diodes (OLEDs). An OLED driving circuit composed of two top-gated fully printed transistors has been fabricated, and the successful control over external OLED is demonstrated. Our work demonstrates the significant potential of using printed carbon nanotube electronics for display backplane applications. PMID:22050730

Chen, Pochiang; Fu, Yue; Aminirad, Radnoosh; Wang, Chuan; Zhang, Jialu; Wang, Kang; Galatsis, Kosmas; Zhou, Chongwu

2011-12-14

246

Refined method for the genomic integration of complex synthetic circuits  

Microsoft Academic Search

Genetic reconstruction of regulatory gene circuits is currently applied in systematic dynamics and structure–function studies of intact cellular networks in systems biology. We present a modified procedure for the integration of complex genetic circuits into the Escherichia coli genome, to provide an efficient synthetic approach for stochastic study and the artificial engineering of genetic networks. Linear artificial sequences of various

Bei-Wen Ying; Yoichiro Ito; Yoshihiro Shimizu; Tetsuya Yomo

2010-01-01

247

Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip  

NASA Astrophysics Data System (ADS)

Biomolecule detection was achieved using a Si single-electron transistor (SET) for highly-sensitive detection. A multiple-island channel-structure was used for the SET to enable room-temperature operation and to increase sensitivity. Coulomb oscillation shifted against the gate voltage due to biotin-streptavidin binding. Coulomb oscillation has a possibility to increase transconductance (gm), and a higher gm leads to greater sensitivity to a charged target. Since a Si structure is important for integrating label-free-biomolecule and/or ion sensors into large-scale-integrated circuits, a Si SET with multiple islands should enable the integration of a sensor system on a single chip for multiplexed detections and simultaneous diagnoses.

Kudo, Takashi; Nakajima, Anri

2012-01-01

248

Current-Writing Active-Matrix Circuit for Organic Light-Emitting Diode Display Using aSi:H Thin-Film-Transistors  

Microsoft Academic Search

SUMMARY In this letter, we describe a four thin-film- transistor (TFT) pixel circuit based on hydrogenated amorphous silicon (a-Si:H) technology for the active-matrix organic light- emitting diode (AMOLED) display applications. The circuit uses current-writing mechanism and can automatically adjust the threshold-voltage shifts of both the organic light-emitting diodes (OLEDs) and the TFTs induced by the circuit aging or process variations.

Reiji HATTORI; Tsutomu TSUKAMIZU; Ryusuke TSUCHIYA; Kazunori MIYAKE; Jerzy KANICKI

2000-01-01

249

Cryogenic readout integrated circuits for submillimeter-wave camera  

NASA Astrophysics Data System (ADS)

The development of cryogenic readout circuits for Superconducting Tunneling Junction (STJ) direct detectors for submillimeter wave is presented. A SONY n-channel depletion-mode GaAs Junction Field Effect Transistor (JFET) is a candidate for circuit elements of the preamplifier. We measured electrical characteristics of the GaAs JFETs in the temperature range between 0.3 and 4.2 K, and found that the GaAs JFETs work with low power consumption of a few microwatts, and show good current-voltage characteristics without cryogenic anomalies such as kink phenomena or hysteresis behaviors. Furthermore, measurements at 0.3 K show that the input referred noise is as low as 0.6 ?V/?{Hz} at 1 Hz. Based on these results and noise calculations, we estimate that a Capacitive Transimpedance Amplifier with the GaAs JFETs will have low noise and STJ detectors will operate below background noise limit.

Nagata, H.; Kobayashi, J.; Matsuo, H.; Akiba, M.; Fujiwara, M.

2006-04-01

250

Structured Application-Specific Integrated Circuit (ASIC) Study.  

National Technical Information Service (NTIS)

Many of the digital electronic subsystems in defense applications require the small-size and power efficiency of application-specific integrated circuits (ASICs). Unfortunately, the high price and long design time of ASICs make them prohibitively expensiv...

D. Black-Schaffer J. Balfour P. Hartke W. Dally

2008-01-01

251

Integrated prepulse circuits for efficient excitation of gas lasers  

NASA Technical Reports Server (NTRS)

Efficient impedance-matched gas laser excitation circuits integrally employ prepulse power generators. Magnetic switches are employed to both generate the prepulse and switch the prepulse onto the laser electrodes.

Rothe, Dietmar E. (Inventor)

1990-01-01

252

LEC GaAs for integrated circuit applications  

NASA Technical Reports Server (NTRS)

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

253

Technological Process Synthesis in the Manufacture of Integrated Circuits.  

National Technical Information Service (NTIS)

Formalized schematics of manufacturing process in the production of integrated circuits are examined and a schematic of manufacturing operators is evolved. Concept of the scale of schematic of manufacturing operators is introduced, and principles of a ste...

L. N. Kolesov

1971-01-01

254

Method of improving contact bonds in silicon integrated circuits  

NASA Technical Reports Server (NTRS)

Fabrication method produces stable and reliable metallic systems for interconnections, contact pads, and bonded leads in silicon planar integrated circuits. The method is based on substrate isolation of the interconnection metal from the contact pad and bonded wire.

Lytle, W. J.; Schuster, M. A.

1967-01-01

255

Chemical etching for automatic processing of integrated circuits  

NASA Technical Reports Server (NTRS)

Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

Kennedy, B. W.

1981-01-01

256

Fabricating Microbolometer Array on Unplanar Readout Integrated Circuit  

Microsoft Academic Search

In this paper, the integration of an experimental 32 × 32 uncooled IR microbolometer array with an unplanar CMOS Readout Integrated Circuit (ROIC) is presented. A vanadium oxide film fabricated by low temperature reactive ion beam sputtering is utilized as thermal-sensitive material in the bolometric detectors Before the integration, the unplanar ROIC for commercial use is first planarized by bisbenzocyclobutene

Hongchen Wang; Xinjian Yi; Jianjun Lai; Yi Li

2005-01-01

257

Heterojunction bipolar transistor technology for data acquisition and communication  

NASA Technical Reports Server (NTRS)

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

258

Analysis of Transmission Lines on Integrated-Circuit Chips  

Microsoft Academic Search

The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern

I. T. Ho; S. K. Mullick

1967-01-01

259

Integration of silk protein in organic and light-emitting transistors  

PubMed Central

We present the integration of a natural protein into electronic and optoelectronic devices by using silk fibroin as a thin film dielectric in an organic thin film field-effect transistor (OFET) ad an organic light emitting transistor device (OLET) structures. Both n- (perylene) and p-type (thiophene) silk-based OFETs are demonstrated. The measured electrical characteristics are in agreement with high-efficiency standard organic transistors, namely charge mobility of the order of 10-2 cm2/Vs and on/off ratio of 104. The silk-based optolectronic element is an advanced unipolar n-type OLET that yields a light emission of 100nW.

Capelli, R.; Amsden, J. J.; Generali, G.; Toffanin, S.; Benfenati, V.; Muccini, M.; Kaplan, D. L.; Omenetto, F. G.; Zamboni, R.

2012-01-01

260

Single-electron counting statistics and its circuit application in nanoscale field-effect transistors at room temperature.  

PubMed

A circuit utilizing single electrons is demonstrated at room temperature. Individual electrons randomly passing through the nanoscale silicon-on-insulator metal-oxide-semiconductor field-effect transistor (MOSFET) are monitored by an electrometer in real time. Such a random behavior of single electrons is used for high-quality random-number generation suitable for data processing which stochastically extracts the most preferable pattern among various ones. MOSFET-based random-number generation allows fast operation as well as high controllability, which leads to flexible extraction of the preferable pattern. PMID:19420585

Nishiguchi, K; Fujiwara, A

2009-04-29

261

Single-electron counting statistics and its circuit application in nanoscale field-effect transistors at room temperature  

NASA Astrophysics Data System (ADS)

A circuit utilizing single electrons is demonstrated at room temperature. Individual electrons randomly passing through the nanoscale silicon-on-insulator metal-oxide-semiconductor field-effect transistor (MOSFET) are monitored by an electrometer in real time. Such a random behavior of single electrons is used for high-quality random-number generation suitable for data processing which stochastically extracts the most preferable pattern among various ones. MOSFET-based random-number generation allows fast operation as well as high controllability, which leads to flexible extraction of the preferable pattern.

Nishiguchi, K.; Fujiwara, A.

2009-04-01

262

Study on Si integrated circuits operating up to 462°C  

Microsoft Academic Search

In order to develop a silicon IC operating up to and above 450°C, integrated injection logic (IIL) was chosen for its peculiar characteristics to high temperature operation. New structures for the IIL were designed through the experimental and theoretical studies of p-n junctions, transistors, and IILs at high temperature. We made Si ICs consisting of nine-stage ILL ring-oscillators by fabrication

Masatoshi Migitaka

1998-01-01

263

Processing of Image Data by Integrated Circuits  

NASA Technical Reports Server (NTRS)

Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.

Armstrong, R. W.

1985-01-01

264

Design Tools for Integrated Asynchronous Electronic Circuits.  

National Technical Information Service (NTIS)

The objective of this Phase-I study was to demonstrate the feasibility of a suite of industrial CAD tools for the design of high-performance, energy-efficient, asynchronous VLSI circuits based on the Caltech technology. Situs Logic's general strategy in t...

A. J. Martin M. Nystroem C. G. Wong

2003-01-01

265

Fabrication and characterization of 3Dimensional MOS transistor tip integrated micro cantilever  

Microsoft Academic Search

We fabricate and characterize a three-dimensional (3-D) MOS (metal–oxide–semiconductor) transistor tip integrated micro cantilever\\u000a to measure the surface properties. The 3-D MOS transistor tip is fabricated on the front side end of the cantilever, and the\\u000a cantilever itself works as a tip. These features make the device possible to investigate hard-detecting parts such as the\\u000a deep trenches and the sidewalls

Sang H. Lee; Pan K. Kim; Wonkyu Moon; Geunbae Lim

2007-01-01

266

Inverted process for graphene integrated circuits fabrication.  

PubMed

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB. PMID:24745037

Lv, Hongming; Wu, Huaqiang; Liu, Jinbiao; Huang, Can; Li, Junfeng; Yu, Jiahan; Niu, Jiebin; Xu, Qiuxia; Yu, Zhiping; Qian, He

2014-06-01

267

Inverted process for graphene integrated circuits fabrication  

NASA Astrophysics Data System (ADS)

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB.CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB. Electronic supplementary information (ESI) available: Optical images and Raman spectrum of graphene, AFM image of the buried gate stack. See DOI: 10.1039/c3nr06904d

Lv, Hongming; Wu, Huaqiang; Liu, Jinbiao; Huang, Can; Li, Junfeng; Yu, Jiahan; Niu, Jiebin; Xu, Qiuxia; Yu, Zhiping; Qian, He

2014-05-01

268

Preventing Simultaneous Conduction In Switching Transistors  

NASA Technical Reports Server (NTRS)

High voltage spikes and electromagnetic interference suppressed. Power-supply circuit including two switching transistors easily modified to prevent simultaneous conduction by both transistors during switching intervals. Diode connected between collector of each transistor and driving circuit for opposite transistor suppresses driving signal to transistor being turned on until transistor being turned off ceases to carry current.

Mclyman, William T.

1990-01-01

269

Microwave GaAs Integrated Circuits On Quartz Substrates  

NASA Technical Reports Server (NTRS)

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

270

SEMICONDUCTOR INTEGRATED CIRCUITS: A high precision high PSRR bandgap reference with thermal hysteresis protection  

NASA Astrophysics Data System (ADS)

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 ?m 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm2. Simulation and testing results show that the temperature coefficient is 13.7ppm/K with temperature ranging from -40 to 150 °C, the power supply rejection ratio is -98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.

Yintang, Yang; Yani, Li; Zhangming, Zhu

2010-09-01

271

(In)AlGaN Heterojunction Field Effect Transistors and Circuits for High-Power Applications at Microwave and Millimeter-Wave Frequencies  

NASA Astrophysics Data System (ADS)

The suitability of the AlGaN/GaN heterostructure for applications up to 20 GHz is demonstrated based on a technically mature process. A broadband power amplifier integrated circuit is designed and fabricated in order to monitor the technology performance. Further, a 100 W power transistor for mobile communications is realized with an efficiency of 70% and an operation frequency of up to 3 GHz. We also demonstrate the performance of a 60 W switch-mode power amplifier module with 75% efficiency for industrial, scientific and medical applications at 2.4 GHz. To push the technology towards higher millimeter-wave frequencies an InAlGaN-based heterostructure was developed. This structure yields high sheet carrier concentration and mobility of 1.9× 1013 cm-2 and 1590 cm2 V-1 s-1, respectively. An excellent fT of 110 GHz and fmax of 190 GHz were achieved with HFETs with a gate length of 100 nm. This allowed the realization of InAlGaN-based power amplifier monolithic microwave integrated circuits (MMICs) operating at millimeter-wave frequencies of 60 and 94 GHz.

Maroldt, Stephan; Quay, Rüdiger; Dennler, Philippe; Schwantuschke, Dirk; Musser, Markus; Dammann, Michael; Aidam, Rolf; Waltereit, Patrick; Tessmann, Axel; Ambacher, Oliver

2013-08-01

272

Complementary junction heterostructure field-effect transistor  

DOEpatents

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Baca, Albert G. (Albuquerque, NM); Drummond, Timothy J. (Albuquerque, NM); Robertson, Perry J. (Albuquerque, NM); Zipperian, Thomas E. (Albuquerque, NM)

1995-01-01

273

Complementary junction heterostructure field-effect transistor  

DOEpatents

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

274

Printed circuit board integrated fluxgate sensor  

Microsoft Academic Search

We have developed a cheap and simple trilayer printed circuit board (PCB)-based technology, adapted for the fabrication of fluxgate magnetic sensors. The two outer layers of the PCB stack comprise the electrical windings of the fluxgate, while the inner layer is made of patterned amorphous magnetic core with extremely high relative magnetic permeability (?r?100,000). The output voltage and the sensitivity

O. Dezuari; E. Belloy; S. E. Gilbert; M. A. M. Gijs

2000-01-01

275

Efficient design of photonic integrated circuits (PICs) by combining device- and circuit- level simulation tools  

NASA Astrophysics Data System (ADS)

This work addresses a versatile modeling of complex photonic integrated circuits (PICs). We introduce a co-simulation solution for combining the efficient modeling capabilities of a circuit-level simulator, based on analytical models of PIC sub-elements and frequency-dependent scattering matrix (S-matrix) description, and an accurate electromagnetic field simulator that implements the finite element method (FEM) for solving photonic structures with complicated geometries. This is exemplified with the model of a coupled-resonator induced transparency (CRIT), where resonator elements are first modeled in the field simulator. Afterwards, the whole structure is created at a circuit level and statistical analysis of tolerances is investigated.

Arellano, C.; Mingaleev, S.; Koltchanov, I.; Richter, A.; Pomplun, J.; Burger, S.; Schmidt, F.

2013-03-01

276

New adders using hybrid circuit consisting of three-gate single-electron transistors (TG-SETs) and MOSFETs.  

PubMed

A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 microm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs. PMID:18047132

Yu, YunSeop; Choi, JungBum

2007-11-01

277

State-Variable Synthesis for Insensitive Integrated Circuit Transfer Functions  

Microsoft Academic Search

Using state-variable flow graphs and simple operational configurations suitable for integration, a theory for insensitive transfer function realization in terms of integrated circuits is discussed. The theory emphasizes the decomposition into second-order systems that are developed, following state-space concepts, with special reference to their sensitivity which is shown to be very low for high operational amplifier gains.

W. J. Kerwin; L. P. Huelsman; R. W. Newcomb

1967-01-01

278

Method of Making a Millimeter Wave Monolithic Integrated Circuit.  

National Technical Information Service (NTIS)

The general object of this invention is to provide a method of making a millimeter monolithic integrated circuit. A more specific object of the invention is to provide such a method that allows for device isolation during epitaxial growth and integral hea...

A. Paolella

1989-01-01

279

Simulation of proton-induced energy deposition in integrated circuits  

NASA Technical Reports Server (NTRS)

A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

Fernald, Kenneth W.; Kerns, Sherra E.

1988-01-01

280

Development of thermionic integrated circuits for applications in hostile environments  

SciTech Connect

This report describes a class of devices known as thermionic integrated circuits (TICs) that are capable of extended operation in ambient temperatures up to 500/sup 0/C and in high radiation environments. The evolution of the TIC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time.

McCormik, J.B.; Lynn, D.K.; Wilde, D.; Cowan, R.; Hamilton, D.J.; Kerwin, W.; Dooley, R.

1984-04-10

281

An investigation of delta-I noise on integrated circuits  

Microsoft Academic Search

Delta-I noise is the voltage induced between the power conductors (e.g. the ground and the Vcc planes) when a circuit connected between them switches from one state to another. The authors show that the physics of the noise is more complex, and that it is related to wave propagation effects. Delta-I noise should be present not only in integrated circuits

Antonije R. DjordjeviC; Tapan Kumar Sarkar

1993-01-01

282

Integrated Optical Circuits for RF Spectrum Analysis.  

National Technical Information Service (NTIS)

The development of a feasibility model for an integrated optic real-time rf spectrum analyzer is reported. The integrated optic spectrum analyzer consists of an injection laser diode, a thin-film optical waveguide incorporated onto a substrate with geodes...

T. R. Ranganath T. R. Joseph J. Y. Lee

1980-01-01

283

Majority carrier type conversion in solution-processed organic transistors and flexible complementary logic circuits  

NASA Astrophysics Data System (ADS)

We report on the realization of high performance solution-processed ambipolar organic transistors based on a quinoidal oligothiophene derivative. The devices show hole and electron field-effect mobilities in air as high as 0.1 and 0.006 cm2 V-1 s-1, respectively, and can be converted from ambipolar p-type dominant to n-type transistors by thermal annealing. The conversion of the majority carrier type is assigned to strong variations in molecular packing. The demonstration of complementary flexible inverters suggests an effective strategy for patterning lateral pn-bipolar structures in solution-processed thin films made from a monolithic ambipolar organic semiconductor.

Ribierre, J. C.; Watanabe, S.; Matsumoto, M.; Muto, T.; Aoyama, T.

2010-02-01

284

Single Event Transients in Linear Integrated Circuits  

NASA Technical Reports Server (NTRS)

On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed to transients. In some cases, such events produced resets by falsely triggering circuits designed to protect against over- voltage or over-current. On at least three occasions, transients caused satellites to switch into "safe mode" in which most of the systems on board the satellites were powered down for an extended period. By the time the satellites were reconfigured and returned to full operational state, much scientific data had been lost. Fortunately, no permanent damage occurred in any of the systems and they were all successfully re-activated.

Buchner, Stephen; McMorrow, Dale

2005-01-01

285

Integrated circuit ceramic ball grid array package antenna  

Microsoft Academic Search

The recent advances in such highly integrated RF transceivers as radio system-on-chip and radio system-in-package have called for the parallel development of compact and efficient antennas. This paper addresses the development of a new type of dielectric chip antenna known as integrated circuit package antenna (ICPA) for highly integrated RF transceivers. A compact ICPA of this type has, for the

Y. P. Zhang

2004-01-01

286

Silica Integrated Optical Circuits Based on Glass Photosensitivity  

NASA Technical Reports Server (NTRS)

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Abushagur, Mustafa A. G.

1999-01-01

287

Fabrication of integrated electrodes of molecular transistor by lithographic techniques and electromigration  

NASA Astrophysics Data System (ADS)

Integrated electrodes of molecular transistor were obtained. Electrodes includes thin-film Au strips with a 2 - 3 nm gap between them and Al gate electrode covered by Al2O3 oxide. The gap formation were made by electromigration technique and self-breaking process. Small (3 - 5 nm) gold nanoparticle were placed into the gap by self assembling. IV curves were measured at room temperature. These IV curves demonstrated single-electron conductivity of system. Such integrated system of electrodes is suitable to be the source-drain electrodes of planar single-electron transistors based on nano-particles or molecules.

Stepanov, A. S.; Soldatov, E. S.; Snigirev, O. V.

2013-01-01

288

Method for double-sided processing of thin film transistors  

DOEpatents

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Yuan, Hao-Chih (Madison, WI); Wang, Guogong (Madison, WI); Eriksson, Mark A. (Madison, WI); Evans, Paul G. (Madison, WI); Lagally, Max G. (Madison, WI); Ma, Zhenqiang (Middleton, WI)

2008-04-08

289

A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays  

Microsoft Academic Search

A new current-driving pixel circuit for active-matrix organic light-emitting diodes (AMOLEDs), composed of four organic thin-film transistors (OTFTs) and one capacitor, is proposed using a current scaling method. Designing pixel circuits with OTFTs has many problems due to the instability of the OTFT parameters with the material characteristics still unknown. Despite the problems in using OTFTs to drive the pixel

Aram Shin; Sang Jun Hwang; Seung Woo Yu; Man Young Sung

2007-01-01

290

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking  

Microsoft Academic Search

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the

Jie Deng; H.-S. Philip Wong

2007-01-01

291

Programmable delay unit incorporating a semi-custom integrated circuit  

SciTech Connect

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given.

Linstadt, E.

1985-04-01

292

3D circuit integration for Vertex and other detectors  

SciTech Connect

High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

Yarema, Ray; /Fermilab

2007-09-01

293

Thermally-induced voltage alteration for integrated circuit analysis  

DOEpatents

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Cole, Jr., Edward I. (Albuquerque, NM)

2000-01-01

294

Dynamic circuit motifs underlying rhythmic gain control, gating and integration.  

PubMed

Brain circuitry processes information by rapidly and selectively engaging functional neuronal networks. The dynamic formation of networks is often evident in rhythmically synchronized neuronal activity and tightly correlates with perceptual, cognitive and motor performances. But how synchronized neuronal activity contributes to network formation and how it relates to the computation of behaviorally relevant information has remained difficult to discern. Here we structure recent empirical advances that link synchronized activity to the activation of so-called dynamic circuit motifs. These motifs explicitly relate (1) synaptic and cellular properties of circuits to (2) identified timescales of rhythmic activation and to (3) canonical circuit computations implemented by rhythmically synchronized circuits. We survey the ubiquitous evidence of specific cell and circuit properties underlying synchronized activity across theta, alpha, beta and gamma frequency bands and show that their activation likely implements gain control, context-dependent gating and state-specific integration of synaptic inputs. This evidence gives rise to the dynamic circuit motifs hypothesis of synchronized activation states, with its core assertion that activation states are linked to uniquely identifiable local circuit structures that are recruited during the formation of functional networks to perform specific computational operations. PMID:25065440

Womelsdorf, Thilo; Valiante, Taufik A; Sahin, Ned T; Miller, Kai J; Tiesinga, Paul

2014-08-01

295

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The drive circuit requirements of the OGBT are explained with the aid of an analytical model. This model can be used to describe the turn-on and turn-off, gate and anode, current and voltage waveforms for general external drive, load, and feedback circuits. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of

1990-01-01

296

A mixed-level modeling and simulation for digital MOS integrated circuits  

SciTech Connect

This dissertation deals with techniques of a fast and accurate simulation tool for digital integrated circuits composed of metal-oxide-semiconductor (MOS) transistors. The demand for high performance and accuracy of digital logic simulation has led to the development of a logic simulator that is capable of handling two levels of models: gate and switch. This mixed-level approach attempts to high performance, approaching that of a gate-level simulator (by using logic gate models) and switch-level accuracy, by developing a new algebraic structure to handle gate- and switch-level models in a consistent way. A digital MOS integrated circuit is described as an interconnection of nodes, switches, and logic gates in a mixed manner. This MOS network is partitioned into a set of logical MOS gates and bidirectional switchlevel subnetworks (BiNets), which are externally unidirectional. The signal at each node is represented in terms of levels and strengths. Over the signal strength, a new algebraic structure, consisting of two algebras at the gate- and switch-level, is developed to consistently deal with signal strength values of logical MOS gates and BiNets with linear switch-level accuracy. Based on the algebras, two evaluation algorithms are developed for mixed-level simulation. The models and algorithms, presented in this dissertation, have been implemented in a simulation tool, called MIXMOS. With the simulation results so far, the performance, in accuracy and computation cost, of MIXMOS meets with our expectations, namely; (1) linear switch-level accuracy to resolve the MOS peculiarities of bidirectional pass transistor logics, sneak paths, dynamic storage, ratioed logic, clock skews, and driving capability, etc., and (2) noticeable savings in space requirement and computation cost.

Kong, J.H.

1989-01-01

297

Dielectric isolation for power integrated circuits.  

National Technical Information Service (NTIS)

Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called 'sma...

D. Zerrouk

1997-01-01

298

Modeling of opto-electronics in complex photonic integrated circuits  

NASA Astrophysics Data System (ADS)

This work addresses a versatile modeling of complex photonic integrated circuits (PICs) including optical and electrical sub-elements. We introduce a new family of electrical elements, together with a novel electronic-photonic co-design, that complements current capabilities of photonic circuit simulators. This is illustrated with the modeling of complex electric circuits contained in photonic devices. Simulations of the interaction between electrical and optical parts allow the analysis of unwanted effects such as reflections due to impedance mismatching, as well as the optimization of the PIC as a whole. We illustrate the functionalities of our approach through application examples. As a use case, we present a model of the electrical driver for a monolithically-integrated InP transmitter developed in frame of the European research project MIRTHE and the analysis of the driver and the EA-Modulator interplay.

Arellano, C.; Mingaleev, S.; Koltchanov, I.; Richter, A.

2014-03-01

299

ON PLACEMENT AND SIZING OF SLEEP TRANSISTORS IN LEAKAGE CRITICAL CIRCUITS  

Microsoft Academic Search

Leakage power is increasingly gaining importance with tech nology scaling. Multi-Threshold CMOS (MTCMOS) technology has bec ome a popular technique for standby power reduction. Sleep tran sistor in- sertion in circuits is an effective application of MTCMOS te chnology for reducing leakage power. In this paper we present a fine gra ined approach where each gate in the circuit is

Vishal Khandelwal; Ankur Srivastava

300

Healing of voids in the aluminum metallization of integrated circuit chips  

NASA Technical Reports Server (NTRS)

The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas R.

1990-01-01

301

A New Low Temperature Polycrystalline Silicon Thin Film Transistor Pixel Circuit for Active Matrix Organic Light Emitting Diode  

NASA Astrophysics Data System (ADS)

This study presents one novel compensation pixel design and driving method for active matrix organic light-emitting diode (AMOLED) displays that use low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with a voltage feed-back method and the simulation results are proposed and verified by SPICE simulator. The measurement and simulation of LTPS TFT characteristics demonstrate the good fitting result. The proposed circuit consists of four TFTs and two capacitors with an additional signal line. The error rates of OLED anode voltage variation are below 0.3% under the threshold voltage deviation of driving TFT (? VTH = ± 0.33 V). The simulation results show that the pixel design can improve the display image non-uniformity by compensating the threshold voltage deviation of driving TFT and the degradation of OLED threshold voltage at the same time.

Ching-Lin Fan,; Yi-Yan Lin,; Jyu-Yu Chang,; Bo-Jhang Sun,; Yan-Wei Liu,

2010-06-01

302

Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator  

NASA Astrophysics Data System (ADS)

Pentacene-based organic thin-film transistors (OTFTs) and organic circuits are fabricated using a plasma-enhanced chemical vapor deposition (PECVD) SiO2/cross-linked poly(vinyl alcohol) (PVA) double-layer insulator. A considerable reduction in hysteresis is achieved by optimizing the double-layer insulator thickness. The main mechanism of a low hysteresis is attributed to the balance of the injected electrons and induced holes at the interface. The fabricated devices have several advantages including low hysteresis characteristics and a stable performance. On the basis of the proposed OTFTs, an electrically stable organic inverter and a buffer working at a frequency as high as 1 kHz are fabricated.

Park, Dong-Wook; Lee, Cheon An; Jung, Keum-Dong; Kim, Byeong-Ju; Park, Byung-Gook; Shin, Hyungcheol; Lee, Jong Duk

2007-04-01

303

Pentacene organic thin-film transistors for circuit and display applications  

Microsoft Academic Search

We have fabricated organic thin-film transistors (TFT's) using the small-molecule polycyclic aromatic hydrocarbon pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam deposited silicon dioxide as the gate dielectric, ion-beam deposited palladium for the source and drain contacts, and vacuum-evaporated pentacene to form the active layer. Excellent electrical characteristics were obtained, including carrier mobility as

Hagen Klauk; David J. Gundlach; Jonathan A. Nichols; Thomas N. Jackson

1999-01-01

304

Modeling of Bipolar Junction Transistor in FDTD Simulation of PrintedCircuit Board  

Microsoft Academic Search

Abstract—A simple and ecient,approximate method to incorporate nonlinear bipolar junction transistor (BJT) into Finite-Dierence Time-Domain (FDTD) framework is presented. This method applies Taylor expansion on the nonlinear transport equations of the BJT based on Gummel-Poon model,[5]. The results are two coupled one-step explicit finite dierence,schemes for the electromagnetic fields in the vicinity of the BJT, which can be solved easily.

F. Kung; H. T. Chuah

2002-01-01

305

Analytical Model for Circuit Simulation with Quarter Micron Metal Oxide Semiconductor Field Effect Transistors: Subthreshold Characteristics  

Microsoft Academic Search

For deep submicron MOSFETs short-channel effects dominate the transistor characteristics. This is due to the increase of the lateral electric field. This paper provides a new simple model which includes the gradient of the lateral electric field in an analytical way. The model describes the subthreshold characteristics relating to short-channel effects correctly down to 0.1 mum effective channel length Leff

Mitiko Miura-Mattausch; Hermann Jacobs

1990-01-01

306

DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit  

Microsoft Academic Search

Silicon-based nanowire field effect transistors (FETs) are potentially next-generation candidates for achieving high-performance targets of the International Roadmap for Semiconductors due to their superior reduction of the short-channel effects and excellent compatibility with planar complementary metal oxide semiconductor (CMOS) fabrication process. In this work, we for the first time numerically explore the dc baseband and high-frequency characteristics, and the design

Yiming Li; Chih-Hong Hwang

2009-01-01

307

Source-Gated Transistors for Versatile Large Area Electronic Circuit Design and Fabrication  

Microsoft Academic Search

Source-gated transistors (SGTs) comprise a blocking contact or potential\\u000a barrier at the source, which control the current. The paper describes\\u000a how SGTs can be optimized for particular applications and for specific\\u000a semiconductor material systems. It is shown how the saturation voltage\\u000a can be designed to be an order of magnitude smaller than in equivalent\\u000a FETs to give power savings of

R. A. Sporea; X. Guo; J. M. Shannon; S. R. P. Silva

2011-01-01

308

Radio-frequency integrated circuits for portable communications  

Microsoft Academic Search

A new market has emerged in the form of portable wireless communications devices, operating in the 900 MHz to 2 GHz range, where miniaturization and low-energy operation is sought through the aggressive large-scale integration typical of silicon ICs, yet the circuit design style at times resembles MMICs. Early indications suggest that silicon will be the technology of choice in this

Asad A. Abidi

1994-01-01

309

Chemical vapor deposition for automatic processing of integrated circuits  

NASA Technical Reports Server (NTRS)

Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

Kennedy, B. W.

1980-01-01

310

Evaluation of Flip/Chip Integrated Circuit Interconnections.  

National Technical Information Service (NTIS)

The objective of this program is to perform a critical evaluation of the Flip-Chip approach to interconnecting integrated chip circuits within a common package. The aluminum-to-aluminum ultrasonic bonding matrix experiment has been completed. A thermal so...

1966-01-01

311

DARPA'S EPIC program: electronic and photonic integrated circuits on Si  

Microsoft Academic Search

This paper discusses the goals and achievements of the electronic and photonic integrated circuits (EPIC) program, which exploits an extraordinary opportunity to create a seamless interface between electronics and photonics. EPIC chips find significant applications in communications, sensors, RF photonics, and wherever photonics and electronics intersect.

J. Shah

2005-01-01

312

Thermal analysis of integrated circuit devices and packages  

Microsoft Academic Search

The integrated circuit device is modeled as a four-layer structure with multiple heat sources located on the surface of the first layer and with the fourth layer representing the device package. Each layer is assumed to have the same rectangular dimensions. Using the separation of variables, an analytical solution for the temperature at any location inside and on the boundaries

C. C. Lee; A. L. Palisoc; Y. J. Min

1989-01-01

313

1998 technology roadmap for integrated circuits used in critical applications  

SciTech Connect

Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

Dellin, T.A.

1998-09-01

314

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Myers, D.R.

1988-04-20

315

An Integrated Automated Layout Generation System for DSP Circuits  

Microsoft Academic Search

An integrated CAD system for the automated design of digital signal-processing (DSP) circuits for audio and telecommunication applications is described. The system uses as unique input a symbolic description of algorithm. This representation is translated into an actual layout using a two-step process. First, the symbolic input is mapped into the target architecture, which consists basically of a set of

Jan M. Rabaey; Stephen P. Pope; Robert W. Brodersen

1985-01-01

316

Performance of digital integrated circuit technologies at very high temperatures  

SciTech Connect

Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

1980-01-01

317

A CMOS integrated circuit for pulse-shaped discrimination  

Microsoft Academic Search

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the

S. S. Frank; M. N. Ericson; M. L. Simpson; R. A. Todd; D. P. Hutchinson

1995-01-01

318

Adaptive fuzzy process control of integrated circuit wire bonding  

Microsoft Academic Search

One step in the assembly of integrated circuits is wire bonding, requiring expert knowledge to optimize critical process characteristics. This paper describes a fuzzy logic controller which sets parameters for the wire bonding process for gold ball wire bonds, specifically controlling bonded ball diameter and shear strength density. While the focus is on control of ball bonds, the method is

Clark D. Kinnaird; Alireza Khotanzad

1999-01-01

319

Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia  

SciTech Connect

Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

2007-04-24

320

Ferrite-Eielectric Composite Integrated Microwave Circuit Development  

Microsoft Academic Search

The Arc Plasma Spray process (APS) makes possible the fabrication of complex ferrite\\/dielectric composite structures suitable for use as substrates for microwave integrated circuits. A typical two layered microstrip geometry is shown in the insert of Fig. 2. The usual microstrip design problems are now complicated because of the choice possible in the selection of the ferrite and dielectric material

C. G. Aumiller; D. H. Harris; M. C. Willson; Y. S. Wu; F. J. Rosenbaum; D. L. LaCombe

1971-01-01

321

Single-Event Transients in Bipolar Linear Integrated Circuits  

Microsoft Academic Search

Single-event transients (SETs) in linear integrated circuits have caused anomalies in a number of spacecraft. The consequences of these anomalies have spurred efforts to better understand SETs, including the mechanisms responsible for their generation, the best approaches for testing, how data should be analyzed and presented, and approaches for mitigation

Stephen Buchner; Dale McMorrow

2006-01-01

322

Monolithic Microwave Integrated Circuit (MMIC) Technology for Space Communications Applications.  

National Technical Information Service (NTIS)

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MM...

D. J. Connolly K. B. Bhasin R. R. Romanofsky

1987-01-01

323

An Optical Phase-Locked Loop Photonic Integrated Circuit  

Microsoft Academic Search

We present the design, fabrication, and results from the first monolithically integrated optical phase-locked loop (OPLL) photonic integrated circuit (PIC) suitable for a variety of homodyne and offset phase locking applications. This InP-based PIC contains two sampled-grating distributed reflector (SG-DBR) lasers, semiconductor optical amplifiers (SOAs), phase modulators, balanced photodetectors, and multimode interference (MMI)-couplers and splitters. The SG-DBR lasers have more

Sasa Ristic; Ashish Bhardwaj; Mark J. Rodwell; Larry A. Coldren; Leif A. Johansson

2010-01-01

324

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers  

NASA Astrophysics Data System (ADS)

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized

Hsu, Yu-Jen

325

Automated Cell Synthesis of Analog Integrated Circuit Layout Anasyn.  

NASA Astrophysics Data System (ADS)

This thesis describes a novel model to automate cell generation for the design of analog integrated circuits and the conclusions about important features that such automation should include. This research represents the first attempt to address this problem by analyzing relevant issues of what constitutes an analog cell and how a technique can be implemented to generate these cells automatically. Our motivation for doing this is the critical limitations to circuit performance which arise from cell design. This thesis defines unique construction properties for the layout of some commonly used analog circuit topologies or cells. This thesis defines the physical layout of analog circuit cells beyond simple geometrical description. Each cell is an independent object that can be interfaced and communicated with. This thesis has extended the concept of an analog cell even further by incorporating synthesis rules into the cell definition. These rules are used to dynamically construct the optimized layout that will satisfy many of the options encountered in actual analog circuit design such as area, matching, tolerance, element rationing and parasitic components. This model can construct complex geometric shapes such as common-centroids, waffles, interdigitated, cascode etc. that are optimized at device level with the precise models for parasitic components. Furthermore, Object-Oriented implementation used in this thesis allow for easy integration of this work into other CAD tools. To demonstrate the feasibility and correctness of the ideas described in this thesis, a CAD tool ANASYN has been written. To test and demonstrate the utility and the performance developed, a variety of test cells have been generated. Data presented clearly demonstrate the uniqueness, flexibility, and precision of the analog circuit layout cells implemented in this research thesis. In addition, one test chip and one design chip have been laid out using cells generated by ANASYN and fabricated at the Defense Advanced Research Project Agency (DARPA) silicon foundry referred to as MOSIS. Data are presented which show good agreement between developed cell models and the circuits actually produced.

Stanojevich, Bob Srbislav

326

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor  

NASA Astrophysics Data System (ADS)

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M.

2013-11-01

327

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor  

SciTech Connect

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M., E-mail: muhammadmustafa.hussain@kaust.edu.sa [Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical Mathematical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia)

2013-11-25

328

Organic thin-film transistors for circuits in a foundry: process, charge transport phenomena and device library  

NASA Astrophysics Data System (ADS)

For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.

Pankalla, Sebastian; Ganz, Simone; Spiehl, Dieter; Dörsam, Edgar; Glesner, Manfred

2013-09-01

329

Integration of silk protein in organic and light-emitting transistors.  

PubMed

We present the integration of a natural protein into electronic and optoelectronic devices by using silk fibroin as a thin film dielectric in an organic thin film field-effect transistor (OFET) ad an organic light emitting transistor device (OLET) structures. Both n- (perylene) and p-type (thiophene) silk-based OFETs are demonstrated. The measured electrical characteristics are in agreement with high-efficiency standard organic transistors, namely charge mobility of the order of 10(-2) cm(2)/Vs and on/off ratio of 10(4). The silk-based optolectronic element is an advanced unipolar n-type OLET that yields a light emission of 100nW. PMID:22899899

Capelli, R; Amsden, J J; Generali, G; Toffanin, S; Benfenati, V; Muccini, M; Kaplan, D L; Omenetto, F G; Zamboni, R

2011-07-01

330

Quantum dot rolled-up microtube optoelectronic integrated circuit.  

PubMed

A rolled-up microtube optoelectronic integrated circuit operating as a phototransceiver is demonstrated. The microtube is made of a InGaAs/GaAs strained bilayer with InAs self-organized quantum dots inserted in the GaAs layer. The phototransceiver consists of an optically pumped microtube laser and a microtube photoconductive detector connected by an a-Si/SiO2 waveguide. The loss in the waveguide and responsivity of the entire phototransceiver circuit are 7.96 dB/cm and 34 mA/W, respectively. PMID:23938911

Bhowmick, Sishir; Frost, Thomas; Bhattacharya, Pallab

2013-05-15

331

Refined method for the genomic integration of complex synthetic circuits.  

PubMed

Genetic reconstruction of regulatory gene circuits is currently applied in systematic dynamics and structure-function studies of intact cellular networks in systems biology. We present a modified procedure for the integration of complex genetic circuits into the Escherichia coli genome, to provide an efficient synthetic approach for stochastic study and the artificial engineering of genetic networks. Linear artificial sequences of various lengths were easily integrated into the bacterial genome at one time. Comparison of the cellular concentrations of proteins encoded by genes carried on plasmids or the genome indicated that genome recombination could minimize the copy number noise in the genetic circuit, allowing precise design and interpretation of the cellular network. The refined recombination procedure allowed efficient construction of a single copy of a complex genetic circuit in cells, and the resultant reduced fluctuation in copy number led to accurate phenotypic behaviour of the genome-integrated synthetic switch corresponding to the design principle. The availability of long-fragment insertions makes the reconstruction of complex networks easy on the genome, and provides a powerful tool for precise engineering in synthetic and systems biology. PMID:20646959

Ying, Bei-Wen; Ito, Yoichiro; Shimizu, Yoshihiro; Yomo, Tetsuya

2010-11-01

332

Conductus makes high-T sub c integrated circuit  

SciTech Connect

This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step.

Not Available

1991-01-01

333

Design and characterization of integrated front-end transistors in a micro-strip detector technology  

NASA Astrophysics Data System (ADS)

We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.

Simi, G.; Angelini, C.; Batignani, G.; Bettarini, S.; Bondioli, M.; Boscardin, M.; Bosisio, L.; Dalla Betta, G.-F.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Morganti, M.; Pignatel, G. U.; Ratti, L.; Re, V.; Rizzo, G.; Speziali, V.; Zorzi, N.

2002-06-01

334

Watching chips work: picosecond hot electron light emission from integrated circuits  

NASA Astrophysics Data System (ADS)

The picosecond pulses of hot carrier luminescence that are observed from individual submicron FETs in CMOS circuits can be used to describe the internal operation of integrated circuits. To effectively use the weak emission pulses, we have developed a method called picosecond integrated circuit analysis (PICA) which simultaneously images and time resolves the emission. PICA has been used to characterize the operation of integrated circuits from simple ring oscillators to a full microprocessors. Examples of circuit characterization and fault diagnosis are presented.

Kash, J. A.; Tsang, J. C.

2000-03-01

335

Aerospace Sensor Component and Subsystem Investigation and Innovation-2 Component Exploration and Development (ASCII-2 CED). Delivery Order 0002: Volume 2. Reconfigurable Aperture Antenna Virtual Prototyping (Wideband Lumped Circuit Models for Integrated Spiral Inductors).  

National Technical Information Service (NTIS)

As the speed of transistors has risen in recent years, acquiring accurate models for the passive devices used in integrated circuits has become a greater challenge. Current device speeds are in the tens of GHz, and at these frequencies the parasitic effec...

A. W. Buurma R. G. Rojas

2005-01-01

336

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...  

Federal Register 2010, 2011, 2012, 2013

...COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same...sale within the United States after importation of certain semiconductor integrated circuit devices and products containing...

2012-10-04

337

System-Level Integrated Circuit (SLIC) Development for Phased Array Antenna Applications.  

National Technical Information Service (NTIS)

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio freq...

K. A. Shalkhauser C. A. Raquet

1991-01-01

338

75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...  

Federal Register 2010, 2011, 2012, 2013

...337-TA-648] Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing Same; Notice of Commission...importation of certain semiconductor integrated circuits using tungsten metallization and products containing the same by reason...

2010-12-06

339

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications  

NASA Astrophysics Data System (ADS)

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

1987-10-01

340

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications  

NASA Astrophysics Data System (ADS)

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

341

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations  

PubMed Central

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ?1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ?140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

2008-01-01

342

The transition to Cu, damascene and low-K dielectrics for integrated circuit interconnects, impacts on the industry.  

NASA Astrophysics Data System (ADS)

This paper will briefly describe impacts of the transition to Cu and low-K dielectrics: why we want them, how close we are to fulfilling the want, and how they will impact the microelectronics industry. The improvements of microelectronic performance that fostered these innovations where in the past paced by our ability to build smaller, and therefore faster, transistors. Today the pace of innovation is being governed by our ability to build interconnections between these ever smaller and exponentially more numerous transistors. As a result the entire industry is embarking on the first major revision of integrated circuit interconnect technology since the original Robert Noyce invention of over 30 years ago. This transition calls for a change in all of the materials used to fabricate integrated circuit interconnects as well as the tools and methods by which we build them. In short, we plan to change everything. The short history and the current status of the technology transition will be reviewed. The core technology will be discussed, but this paper will also discuss other impacts of the transition, such as the equipment business and of course, metrology. Changing everything in the technology is not simply going to impact the end products; it will also impact the entire industry and infrastructure of semiconductor manufacturing. .

Monnig, Kenneth A.

2001-01-01

343

Si\\/SiGe HBT technology for low-cost monolithic microwave integrated circuits  

Microsoft Academic Search

This silicon-based microwave integrated-circuit technology is suitable for implementation of high-performance low-cost active circuits from 5-25 GHz. This technology promises to dramatically reduce the cost of microwave integrated circuit technology by utilizing manufacturable, high-yield, silicon IC processing, and at the same time enable more highly integrated implementations of microwave transceiver components. A variety of microwave integrated circuits implemented in this

Lawrence Larson; Michael Case; Steven Rosenbaum; David Rensch; Perry MacDonald; Mehran Matloubian; Mary Chen; David Harame; John Malinowski; Bernard Meyerson; Monica Gilbert; Stephen Maas

1996-01-01

344

Extended life testing evaluation of complementary MOS integrated circuits  

NASA Technical Reports Server (NTRS)

The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

Brosnan, T. E.

1972-01-01

345

Novel glass compositions and fabrication technologies for photonic integrated circuits  

Microsoft Academic Search

Heavy metal fluoride, chalcogenide, and fluoro-tellurite glasses proffer photonic integrated circuit functionality over a wide wavelength range, and combine high optical non-linearity with the ability to incorporate active dopants. The ability to access a range of glass compositions offers great flexibility in both design and processing. In this paper, we present fabrication methodologies for producing such novel glass-based waveguide components.

T. M. Benson; A. Vukovic; P. Sewell; A. Loni; Y. Zhang; W. Pan; D. Zhang; M. D. O'Donnell; J. Lousteau; D. Furniss; A. B. Seddon

2005-01-01

346

Thermal resistance of VCSELs bonded to integrated circuits  

Microsoft Academic Search

The thermal resistance of vertical-cavity surface-emitting lasers (VCSELs) flip chip bonded to GaAs substrates and CMOS integrated circuits has been measured. The measurements on GaAs show that if the bonding is done properly, the bonding does not add significantly to the thermal resistance. However, the SiO2 under the CMOS bonding pad can double the thermal resistance unless measures are taken

Rui Pu; Carl W. Wilmsen; Kent M. Geib; Kent D. Choquette

1999-01-01

347

A CMOS integrated circuit for pulse-shape discrimination  

Microsoft Academic Search

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a monitoring system for stored nuclear materials. The method extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a zero-crossing discriminator to determine the zero crossing

S. S. Frank; M. N. Ericson; M. L. Simpson; D. P. Hutchinson; R. A. Todd

1995-01-01

348

Microwave integrated Schottky-barrier-diode mixer circuits  

Microsoft Academic Search

The paper gives attention to the design and electrical properties of different types of hybrid microwave integrated mixers, with special consideration given to broadband single and double balance mixers. The basic characteristics of Schottky-barrier mixer diodes are reviewed. It is found that complex phase-suppression circuits can be used along with narrowband filters to suppress the reception mirror-channel. An analytical study

N. P. Banshchikov; A. M. Zubkov

1977-01-01

349

Focal plane infrared readout circuit  

NASA Technical Reports Server (NTRS)

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

Pain, Bedabrata (Inventor)

2002-01-01

350

System-Level Integrated Circuit (SLIC) development for phased array antenna applications  

Microsoft Academic Search

A microwave\\/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the

K. A. Shalkhauser; C. A. Raquet

1991-01-01

351

A new patterning process concept for large-area transistor circuit fabrication without using an optical mask aligner  

Microsoft Academic Search

A new concept to produce large thin film transistor liquid crystal displays (TFT-LCD's) without using an optical mask aligner is proposed which emphasizes patterning technology. Some experimental thin film transistors (TFT's) are fabricated according to the concept and operated like conventional transistors fabricated by using an optical mask aligner. The concept includes improvement of printing technology and development of a

Yoshiro Mikami; Yoshiharu Nagae; Yuji Mori; Kazuhiro Kuwabara; Takeshi Saito; H. Hayama; H. Asada; Y. Akimoto; M. Kobayashi; S. Okazaki; K. Asaka; H. Matsui; K. Nakamura; E. Kaneko

1994-01-01

352

A CMOS integrated circuit for pulse-shaped discrimination  

SciTech Connect

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the zero crossing of the shaped signal. The circuit is designed to interface with two photomultiplier tubes -- one for pulse processing and one for coincidence detection. Two Outputs from the IC, a start and stop, can be used with a high speed timing system for pulse characterization with minimal external control. The circuit was fabricated in Orbit 1.2{mu}m CMOS and operates from a 5-V supply. Specifics of the design including overall topology, charge sensitive preamplifier and CFD characteristics, shaping method and time constant selections, system timing, and implementation are discussed. Circuit performance is presented including dynamic range, timing walk, system dead time, and power consumption.

Frank, S.S.; Ericson, M.N.; Simpson, M.L.; Todd, R.A.; Hutchinson, D.P.

1995-06-01

353

Pneumatic oscillator circuits for timing and control of integrated microfluidics  

PubMed Central

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

2013-01-01

354

Pneumatic oscillator circuits for timing and control of integrated microfluidics.  

PubMed

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-01

355

A PWM transistor inverter for an ac electric vehicle drive  

NASA Technical Reports Server (NTRS)

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Slicker, J. M.

1981-01-01

356

A PWM transistor inverter for an ac electric vehicle drive  

NASA Astrophysics Data System (ADS)

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Slicker, J. M.

1981-10-01

357

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates  

Microsoft Academic Search

We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950°C. The substrates were 0.2-mm thick steel foil coated with 0.5-?m thick SiO2. We employed silicon crystallization times ranging from 6 h (600°C) to 20 s (950°C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO2

Ming Wu; Xiang-Zheng Bo; James C. Sturm; Sigurd Wagner

2002-01-01

358

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-?m SiGe heterojunction bipolar transistors and circuits  

Microsoft Academic Search

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this

Robert A. Reed; Paul W. Marshall; James C. Pickel; Martin A. Carts; Bryan Fodness; Guofu Niu; Karl Fritz; Gyorgy Vizkelethy; Paul E. Dodd; Tim Irwin; John D. Cressler; Ramkumar Krithivasan; Pamela Riggs; Jason Prairie; Barbara Randall; Barry Gilbert; Kenneth A. LaBel

2003-01-01

359

Device and Circuit Codesign Strategy for Application to Low-Noise Amplifier Based on Silicon Nanowire MetalOxideSemiconductor Field Effect Transistors  

Microsoft Academic Search

In this study, a full-range approach from device level to circuit level design is performed for RF application of silicon nanowire (SNW) metal-oxide-semiconductor field effect transistors (MOSFETs). Both DC and AC analyses have been conducted to confirm the advantages of an SNW MOSFET over the conventional planar (CPL) MOSFET device having dimensional equivalence. Besides the intrinsic characteristic parameters, the extrinsic

Seongjae Cho; Hee-Sauk Jhon; Jung Hoon Lee; Se Hwan Park; Hyungcheol Shin; Byung-Gook Park

2010-01-01

360

Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators  

Microsoft Academic Search

A large-area, flexible, and lightweight sheet-type Braille display has been successfully fabricated on a plastic film by integrating high-quality organic transistors and soft actuators. An array of rectangular plastic actuators is mechanically processed from a perfluorinated polymer electrolyte membrane. A small semisphere, which projects upward from the rubberlike surface of the display, is attached to the tip of each rectangular

Yusaku Kato; Tsuyoshi Sekitani; Makoto Takamiya; Masao Doi; Kinji Asaka; Takayasu Sakurai; Takao Someya

2007-01-01

361

The large-scale integration of high-performance silicon nanowire field effect transistors  

Microsoft Academic Search

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on\\/off current ratio (>107). The subthreshold swing is as small as 45 mV\\/dec, which is substantially beyond the thermodynamic limit (60 mV\\/dec) of conventional planar MOSFETs. These excellent

Qiliang Li; Xiaoxiao Zhu; Yang Yang; Dimitris E Ioannou; Hao D Xiong; Doo-Won Kwon; John S Suehle; Curt A Richter

2009-01-01

362

Integrating anatomy and function for zebrafish circuit analysis.  

PubMed

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

Arrenberg, Aristides B; Driever, Wolfgang

2013-01-01

363

InP-based three-dimensional photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure. This additional beam routing flexibility allows significant size reduction and process simplification without sacrificing device performance. This innovative 3-D PIC technology platform can be easily extended to create surface-emitting lasers integrated with power monitoring detectors, micro-lenses, external modulators, amplifiers, and other passive and active components. Such added functionality can produce cost--effective solutions for the highest-end laser transmitters required for datacom and short range telecom networks, as well as fiber channels and other cost and performance sensitive applications. We present results for 1310 nm photonic IC surface-emitting laser transmitters operating at 2.5 Gbps without active thermal electric cooling.

Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

364

Synthetic circuits integrating logic and memory in living cells.  

PubMed

Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications. PMID:23396014

Siuti, Piro; Yazbek, John; Lu, Timothy K

2013-05-01

365

Advances in integrated photonic circuits for packet-switched interconnection  

NASA Astrophysics Data System (ADS)

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8? space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

366

SEMICONDUCTOR INTEGRATED CIRCUITS: Soft error generation analysis in combinational logic circuits  

NASA Astrophysics Data System (ADS)

Reliability is expected to become a big concern in future deep sub-micron integrated circuits design. Soft error rate (SER) of combinational logic is considered to be a great reliability problem. Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects, but they failed to achieve enough insights. In this paper, an analytical glitch generation model is proposed. This model shows that after an inflexion point the collected charge has an exponential relationship with glitch duration and the model only introduces an estimation error of on average 2.5%.

Qian, Ding; Yu, Wang; Rong, Luo; Hui, Wang; Huazhong, Yang

2010-09-01

367

Analyzing integrated circuits at work with a picosecond time-gated imager  

NASA Astrophysics Data System (ADS)

A system based on a picosecond time-gated image intensifier is proposed for non-contact testing of CMOS circuits. The apparatus allows one to record the temporal evolution of the luminescence emitted during transistor switching as a function of the position inside the chip. The system is characterized by an intrinsic parallelism in the spatial dimensions. This feature is noticeable for studying wide sections of complex circuits, like microprocessors and random access memories, where multiple electrical events occur simultaneously. Experiments on a CMOS inverter chain and on a static memory have been carried out, in order to demonstrate the applicability of a picosecond time-gated imager to circuit analysis.

Comelli, D.; D'Andrea, C.; Valentini, G.; Cubeddu, R.; Casiraghi, R.; Cantarelli, D.

2005-12-01

368

Conception d'un circuit d'etouffement pour photodiodes a avalanche en mode geiger pour integration heterogene 3d  

NASA Astrophysics Data System (ADS)

Le Groupe de Recherche en Appareillage Medical de Sherbrooke (GRAMS) travaille actuellement sur un programme de recherche portant sur des photodiodes a avalanche mono-photoniques (PAMP) operees en mode Geiger en vue d'une application a la tomographie d'emission par positrons (TEP). Pour operer dans ce mode; la PAMP, ou SPAD selon l'acronyme anglais (Single Photon Avalanche Diode), requiert un circuit d'etouffement (CE) pour, d'une part, arreter l'avalanche pouvant causer sa destruction et, d'autre part. la reinitialiser en mode d'attente d'un nouveau photon. Le role de ce CE comprend egalement une electronique de communication vers les etages de traitement avance de signaux. La performance temporelle optimale du CE est realisee lorsqu'il est juxtapose a la PAMP. Cependant, cela entraine une reduction de la surface photosensible ; un element crucial en imagerie. L'integration 3D, a base d'interconnexions verticales, offre une solution elegante et performante a cette problematique par l'empilement de circuits integres possedant differentes fonctions (PAMP, CE et traitement avance de signaux). Dans l'approche proposee, des circuits d'etouffement de 50 pm x 50 pm realises sur une technologie CMOS 130 mn 3D Tezzaron, contenant chacun 112 transistors, sont matrices afin de correspondre a une matrice de PAMP localisee sur une couche electronique superieure. Chaque circuit d'etouffement possede une gigue temporelle de 7,47 ps RMS selon des simulations faites avec le logiciel Cadence. Le CE a la flexibilite d'ajuster les temps d'etouffement et de recharge pour la PAMP tout en presentant une faible consommation de puissance (~ 0,33 mW a 33 Mcps). La conception du PAMP necessite de supporter des tensions superieures aux 3,3 V de la technologie. Pour repondre a ce probleme, des transistors a drain etendu (DEMOS) ont ete realises. En raison de retards de production par Ies fabricants, les circuits n'ont pu etre testes physiquement par des mesures. Les resultats de ce memoire sont par consequent bases sur des resultats de simulations avec le logiciel Cadence. Mots-cles : Circuit d'etouffement, Photodiodes a avalanche monophotoniques (PAMP), Single Photon Avalanche Diode (SPAD), Integration 3D heterogene, Drain-Extended MOS (DEMOS), CMOS 130 nm 3D Tezzaron/Chartered, Tomographie d'emission par positrons (TEP)

Boisvert, Alexandre

369

An application of carbon nanotubes for integrated circuit interconnects  

NASA Astrophysics Data System (ADS)

Integrated circuits fabrication is soon reaching strong limitations. Help could come from using carbon nanotubes as conducting wires for interconnects. Although this solution was proposed six years ago, researchers still come up with many obstacles such as localization, low temperature growth on copper, contacting and reproducibility. The integration processes exposed here intend to meet the industrial requirements. Two approaches are then possibly followed. Either using densely packed single wall (SWCNT) (or very tiny multiwall) nanotubes, or filling up the whole interconnect diameter with a single large multiwall (MWCNT) nanotube. In this work, we focus on the integration of multiwall vertical interconnects. Densely packed MWCNTs are grown in via holes by CVD. Alternatively, we have developed a method to obtain a single large nanofibre grown by PECVD (MWCNF) in each via hole. Electrical measurements are performed on CVD and PECVD grown carbon nanotubes. The role of electron-phonon interaction in these devices is also briefly discussed.

Coiffic, J. C.; Foa Torres, L. E.; Le Poche, H.; Fayolle, M.; Roche, S.; Maitrejean, S.; Roualdes, S.; Ayral, A.

2008-09-01

370

Development of the Equipment and Technique for Welding the Leads of Integrated Circuits to Printed Circuit Boards.  

National Technical Information Service (NTIS)

At the present time, solder with a low melting point and flux is used for attaching integrated circuits leads to printed circuit plates in industrial procedures. However, a number of difficulties are involved in this method, and there is a tendency to rep...

A. P. Isaev, G. D. Bitsoev, V. N. Atamanov

1972-01-01

371

Bioluminescent-bioreporter integrated circuits form novel whole-cell biosensors  

Microsoft Academic Search

The bioluminescent-bioreporter integrated circuit represents a new advance in the development of whole-cell biosensors, consisting of a genetically engineered bioreporter organism interfaced with an integrated circuit. The bioreporter is engineered to luminesce when a targeted substance is encountered, with the circuit being designed to detect this luminescence, process the signal and communicate the results. The bioreporters are thus available to

Michael L. Simpson; Gary S. Sayler; Bruce M. Applegate; Steven Ripp; David E. Nivens; Michael J. Paulus; Gerald E. Jellison

1998-01-01

372

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

Cole, E.I. Jr.; Soden, J.M.

1995-07-04

373

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

1995-01-01

374

Thermal resistance of VCSEL's bonded to integrated circuits  

SciTech Connect

The thermal resistance of vertical-cavity surface-emitting lasers (VCSEL's) flip chip bonded to GaAs substrates and CMOS integrated circuits has been measured. The measurements on GaAs show that if the bonding is done properly, the bonding does not add significantly to the thermal resistance. However, the SiO{sub 2} under the CMOS bonding pad can double the thermal resistance unless measures are taken to improve the thermal conductance of these layers. Finite element simulations indicate that the thermal resistance of bonded VCSEL's increases rapidly as the solder bond size and the aperture size decrease below {approximately}10 {micro}m.

Pu, R.; Wilmsen, C.W.; Geib, K.M.; Choquette, K.D.

1999-12-01

375

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Creighton, J. Randall (Albuquerque, NM); Dominguez, Frank (Albuquerque, NM); Johnson, A. Wayne (Albuquerque, NM); Omstead, Thomas R. (Albuquerque, NM)

1997-01-01

376

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

377

Optical interconnects for future high performance integrated circuits  

NASA Astrophysics Data System (ADS)

Miniaturization paradigm leads to a rapid performance deterioration of Copper wires in the future, despite lower dielectric constant materials between the lines. This work examines optical interconnects as an alternative for high performance silicon integrated circuits, and compares it with future metal interconnects. Both global signaling and clock distribution applications are considered. For clocking, power dissipation, where as, for global signaling, both power and delay are compared with metal-based interconnects. We show that for high switching activity, long global signaling wires, it is favorable to switch to optical interconnects on both power and delay account. Whereas, a metal-based interconnect system is more favorable for shorter links.

Kapur, Pawan; Saraswat, Krishna C.

2003-03-01

378

SiGe/Si Monolithically Integrated Amplifier Circuits  

NASA Technical Reports Server (NTRS)

With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

Katehi, Linda P. B.; Bhattacharya, Pallab

1998-01-01

379

Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors.  

PubMed

Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. PMID:24965261

Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; Li, Liang; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I; Alshareef, H N; Zhang, Yafei; Zhang, X X

2014-07-10

380

Stainless Steel NaK Circuit Integration and Fill Submission  

NASA Technical Reports Server (NTRS)

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Garber, Anne E.

2006-01-01

381

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit  

Microsoft Academic Search

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well\\/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal

Michael L Simpson; Gary S Sayler; Greg Patterson; David E Nivens; Eric K Bolton; James M Rochelle; James C Arnott; Bruce M Applegate; Steven Ripp; Michael A Guillorn

2001-01-01

382

Integrated detectors for embedded optical interconnections on electrical boards, modules, and integrated circuits  

Microsoft Academic Search

Significant opportunities exist for optical interconnections at the board, module, and chip level if compact, low-loss, high-data-rate optical interconnections can be integrated into these electrical interconnection systems. To create such an integrated optoelectronic\\/electronic microsystem, mask-based alignment of the optical interconnection waveguide, optoelectronic active devices, and interface circuits is attractive from a packaging alignment standpoint. This paper describes an integration process

Sang-Yeon Cho; Sang-Woo Seo; Martin A. Brooke; Nan M. Jokerst

2002-01-01

383

Circuits  

NSDL National Science Digital Library

Students are introduced to several key concepts of electronic circuits. They learn about some of the physics behind circuits, the key components in a circuit and their pervasiveness in our homes and everyday lives. Students learn about Ohm's law and how it is used to analyze circuits.

Integrated Teaching And Learning Program

384

Effect of defects localised in the oxide of submicrometer NMOS transistor on substrate and drain currents  

Microsoft Academic Search

The increase of the MOS integration scale entails the presence of the strong electrical fields in the MOS channel transistor, which cause the injection of hot carriers in the gate oxide and create defects at the Si\\/SiO2 interface and in the oxide layer. These defects induce leakage currents and are responsible for degradation of circuit performances and transistor ageing. The

A. Bouhdada; A. Nouacry; S. Bakkali; A. Touhami; R. Marrakh

1999-01-01

385

Effect of circuital currents on the speed and efficiency of picosecond-range switching in a GaAs avalanche transistor  

NASA Astrophysics Data System (ADS)

Ultrafast (picosecond range) switching of a GaAs-based BJT (bipolar junction transistor) in the avalanche mode has recently been demonstrated experimentally. It was found to be caused by the formation and spread of ultra-high amplitude multiple Gunn domains, which cause extremely powerful avalanching in the volume of the switching filaments. Unavoidable parasitic impedance of an external circuit limits the rate of avalanche carrier generation in the channels, however, which slows down the switching and increases the residual voltage across the switch. We present here the results of simulations which show that the switching transient can be significantly accelerated and the residual voltage reduced due to the supporting of a higher current density in the channels by the charge stored in the barrier capacitance of the non-switched part of the structure. The corresponding circuital currents are confined in low-inductance loops inside the structure and are not critically affected by the parameters of the external circuit. This provides very fast and effective reduction in the collector voltage, provided the parameters of the semiconductor layers and the geometry of the device are selected properly. Particularly significant in this process is the effect of circuital current saturation in the lightly doped collector region of the non-switched part of the transistor. The results of the simulations with the barrier capacitance included in the model are in excellent agreement with the experimental data.

Vainshtein, Sergey; Yuferev, Valentin; Kostamovaara, Juha

2005-04-01

386

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits  

Microsoft Academic Search

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication

Ahmet Bindal; Sotoudeh Hamedi-Hagh

2006-01-01

387

Silicon Bipolar Integrated Circuits for Multi-GB\\/s Optical Communication Systems  

Microsoft Academic Search

The authors discuss several important circuits for fiber-optic transmission, implemented in an advanced silicon bipolar integrated circuit technology. Specifically, the authors discuss the design considerations and measured performance of a 2:1 multiplexer, front end receiver, limiting amplifier, and decision circuit IC. Also discussed are three hybrid circuit modules: a 2:1 multiplexer, 1:2 demultiplexer, and parallel processing decision circuit. These ICs

Klaus Runge; Mehran Bagheri; James L. Gimlett; D. Clawin; Nim K. Cheung; Daniel J. Millicker; Detlef Daniel; C. Snapp

1991-01-01

388

Designs and Applications of Three-Dimensional Integrated Circuits  

NASA Astrophysics Data System (ADS)

Three dimensional integrated circuits (3D IC) have recently been getting an attention among researchers and IC designers as an emerging technology to help overcome the interconnect delay and power limitations. Tight integration of multiple silicon tiers using vertical 3D vias as interconnect offers reduction in interconnect length, capacitance and resistance, which results in reduction in power and delay. This dissertation discusses 3D IC design considerations and methodologies including partitioning methods in the case of TCAM designs. 3D TCAMs are designed and implemented using single-tier, 2-tiers and 3-tiers in an available 180 nm 3D IC process. The comparison shows that a 40% matchline capacitance reduction, a 32% matchline power reduction, and a 21% total TCAM core power reduction can be achieved with a proposed partitioning scheme in a 3-tier design compared to those in a single-tier design. In addition, it also shows a 25% reduction in precharge time in TCAM core design with 3 tiers compared to that with a single tier. The benefit of 3D IC circuits depends highly on the technology parameters such as the number of wafer stacks, 3D via size, alignment precision as well as partitioning method of circuit design and partitioning strategy of interconnect into multiple tiers. This dissertation expands the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impacts of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order are evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs.

Oh, Eun Chu

389

Mixed signal custom integrated circuit development for physics instrumentation  

SciTech Connect

The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

1998-10-01

390

Monolithically integrated, flexible display of polymer-dispersed liquid crystal driven by rubber-stamped organic thin-film transistors  

Microsoft Academic Search

This letter describes the monolithic integration of rubber-stamped thin-film organic transistors with polymer-dispersed liquid crystals (PDLCs) to create a multipixel, flexible display with plastic substrates. We report the electro-optic switching behavior of the PDLCs as driven by the organic transistors, and we show that our displays operate robustly under flexing and have a contrast comparable to that of newsprint.

P. Mach; S. J. Rodriguez; R. Nortrup; P. Wiltzius; J. A. Rogers

2001-01-01

391

Monolithically integrated, flexible display of polymer-dispersed liquid crystal driven by rubber-stamped organic thin-film transistors  

SciTech Connect

This letter describes the monolithic integration of rubber-stamped thin-film organic transistors with polymer-dispersed liquid crystals (PDLCs) to create a multipixel, flexible display with plastic substrates. We report the electro-optic switching behavior of the PDLCs as driven by the organic transistors, and we show that our displays operate robustly under flexing and have a contrast comparable to that of newsprint. {copyright} 2001 American Institute of Physics.

Mach, P.; Rodriguez, S. J.; Nortrup, R.; Wiltzius, P.; Rogers, J. A.

2001-06-04

392

Development of optical packet and circuit integrated ring network testbed.  

PubMed

We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. PMID:22274025

Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

2011-12-12

393

Graphene/Si CMOS Hybrid Hall Integrated Circuits.  

PubMed

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

394

Graphene/Si CMOS Hybrid Hall Integrated Circuits  

PubMed Central

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

395

Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits  

ScienceCinema

Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

396

A monolithic lead sulfide-silicon MOS integrated-circuit structure  

NASA Technical Reports Server (NTRS)

A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

Jhabvala, M. D.; Barrett, J. R.

1982-01-01

397

Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida  

NASA Astrophysics Data System (ADS)

A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

1984-07-01

398

EKV3 compact modeling of MOS transistors from a 0.18 ?m CMOS technology for mixed analog-digital circuit design at low temperature  

NASA Astrophysics Data System (ADS)

The standard version of the EKV3 compact model is evaluated for simulation of mixed analog-digital circuits working at low temperature (77-200 K). This evaluation is performed on a dual gate oxide CMOS technology with 0.18 ?m/1.8 V and 0.35 ?m/3.3 V MOSFET transistors. A detailed temperature analysis of some physical effects is performed. Specific effects, such as anomalous narrow channel effect, freeze-out in Lightly Doped drain (LDD) regions or quantization of the inversion charge, are observed at low or intermediate temperature. Some improvements of this compact model will allow a more accurate description of MOS transistors at low temperature.

Martin, P.; Cavelier, M.; Fascio, R.; Ghibaudo, G.; Bucher, M.

2009-11-01

399

Integration and manufacture of multifunctional planar lightwave circuits  

NASA Astrophysics Data System (ADS)

The demands of exponentially growing Internet traffic, coupled with the advent of Dense Wavelength Division Multiplexing (DWDM) fiber optic systems to meet those demands, have triggered a revolution in the telecommunications industry. This dramatic change has been built upon, and has driven, improvements in fiber optic component technology. The next generation of systems for the all optical network will require higher performance components coupled with dramatically lower costs. One approach to achieve significantly lower costs per function is to employ Planar Lightwave Circuits (PLC) to integrate multiple optical functions in a single package. PLCs are optical circuits laid out on a silicon wafer, and are made using tools and techniques developed to extremely high levels by the semi-conductor industry. In this way multiple components can be fabricated and interconnected at once, significantly reducing both the manufacturing and the packaging/assembly costs. Currently, the predominant commercial application of PLC technology is arrayed-waveguide gratings (AWG's) for multiplexing and demultiplexing multiple wavelength channels in a DWDM system. Although this is generally perceived as a single-function device, it can be performing the function of more than 100 discrete fiber-optic components and already represents a considerable degree of integration. Furthermore, programmable functions such as variable-optical attenuators (VOAs) and switches made with compatible PLC technology are now moving into commercial production. In this paper, we present results on the integration of active and passive functions together using PLC technology, e.g. a 40 channel AWG multiplexer with 40 individually controllable VOAs.

Lipscomb, George F.; Ticknor, Anthony J.; Stiller, Marc A.; Chen, Wenjie; Schroeter, Paul

2001-11-01

400

Integrated circuit for processing a low-frequency signal from a seismic detector  

SciTech Connect

Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex 'Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

2011-12-15

401

Novel Current-Scaling Current-Mirror Hydrogenated Amorphous Silicon Thin-Film Transistor Pixel Electrode Circuit with Cascade Capacitor for Active-Matrix Organic Light-Emitting Devices  

Microsoft Academic Search

We proposed the hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with current-scaling function which is suitable for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current-mirror circuit, this circuit with the cascaded storage capacitors can provide a high data-to-organic light-emitting device (OLED) current ratio without increasing the a-Si:H TFT size. Moreover, since the number of

Hojin Lee; Juhn S. Yoo; Chang-Dong Kim; In-Jae Chung; Jerzy Kanicki

2007-01-01

402

Investigation of failure mechanisms in integrated vacuum circuits  

NASA Technical Reports Server (NTRS)

The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

Rosengreen, A.

1972-01-01

403

Wireless multichannel biopotential recording using an integrated FM telemetry circuit.  

PubMed

This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB. PMID:16200750

Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

2005-09-01

404

Integrated circuit-based instrumentation for microchip capillary electrophoresis.  

PubMed

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars. PMID:20726675

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

405

Basic structures of integrated photonic circuits for smart biosensor applications  

NASA Astrophysics Data System (ADS)

The breadth of opportunities for applied technologies for optical sensors ranges from environmental and biochemical control, medical diagnostics to process regulation. Thus the specified usage of the optical sensor system requires a particular design and functionalization. Especially biochemical sensors incorporate electronic and photonic devices for the detection of harmful substances e.g. in drinking water. Here we present recent developments in the integration of a Si-based light emitting device (LED) [1-3, 8] into a photonic circuit for an optical waveguide-based biodetection system. This concept includes the design, fabrication and characterization of the dielectric high contrast waveguide as an important component, beside the LED, in the photonic system circuit. First approaches involve simulations of Si3N4/SiO2-waveguides with the finite element method (FEM) and their fabrication by plasma enhanced chemical vapour deposition (PECVD), optical lithography and reactive ion etching (RIE). In addition, we characterized the deposited layers via ellipsometry and the etched structures by scanning electron microscopy (SEM). The obtained results establish a basis for optimized Si-based LED waveguide butt-coupling with adequate coupling efficiency, low attenuation loss and a high optical power throughput.

Germer, S.; Cherkouk, C.; Rebohle, L.; Helm, M.; Skorupa, W.

2013-05-01

406

77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...  

Federal Register 2010, 2011, 2012, 2013

...INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-848] Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial...

2012-11-14

407

Plasmonic nanopatch array for optical integrated circuit applications  

PubMed Central

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

Qu, Shi-Wei; Nie, Zai-Ping

2013-01-01

408

Wireless Neural Recording With Single Low-Power Integrated Circuit  

PubMed Central

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-?m 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

409

Plasmonic nanopatch array for optical integrated circuit applications  

NASA Astrophysics Data System (ADS)

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

Qu, Shi-Wei; Nie, Zai-Ping

2013-11-01

410

Control of CVD precursor purity for integrated circuit manufacture  

NASA Astrophysics Data System (ADS)

Chemical vapor deposition, CVD, has assumed an increasing share of the processes utilized in the manufacture of submicron integrated circuits. In addition to the conventional CVD materials such as silicon oxide, nitride and polysilicon, an array of new materials for both dielectric and conductive material applications are in development. For films like BPSG or tungsten, convenient volatile precursor sources exist, however, in other cases temperature sensitive, lower volatility liquids and solids are utilized. The quality and consistency of these molecular precursors can have a marked impact on the film forming process. The application of SPC methodology to precursor manufacture provides an effective metric for controlling both the quality and the consistency of the precursors.

Roberts, David A.; Graf, Hans J.; Halberstadt, Michael J.

1995-09-01

411

Graphene-based plasmonic photodetector for photonic integrated circuits.  

PubMed

We developed a planar-type graphene-based plasmonic photodetector (PD) for the development of all-graphene photonic-integrated-circuits (PICs). By configuring the graphene plasmonic waveguide and PD structure all-in-one, the proposed graphene PD detects horizontally incident light. The photocurrent profile with opposite polarity is the maximum at graphene-electrode interfaces due to a Schottky-like barrier effect at the interface. The photocurrent amplitude increases with an increase of the graphene-metal interface length. Obtaining time constants of less than 39.7 ms for the time response, we concluded that the proposed graphene PD could be exploited further for application in all graphene-based PICs. PMID:24515039

Kim, Jin Tae; Yu, Young-Jun; Choi, Hongkyw; Choi, Choon-Gi

2014-01-13

412

Monolithic microwave integrated circuit devices for active array antennas  

NASA Technical Reports Server (NTRS)

Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

Mittra, R.

1984-01-01

413

Universal application-specific integrated circuit for bioelectric data acquisition.  

PubMed

Use of highly integrated application specific circuits (ASICs) in bioelectric data acquisition systems promise important new insights into the origin of a large variety of health problems by providing light-weight, low-power, low-cost medical measurement devices that allow long-term studies. They also promise significant cost reduction in medical care, as patients in principle become mobile and do not have to be hospitalized for observation. We report on the development and successful implementation of a universal ASIC, designed to meet key characteristics of a broad variety of bioelectric signals in terms of their dynamic range, sampling rate and input referred noise; e.g. electrocardiogram (ECG), electroencephalogram (EEG) and, most constringently, evoked potentials (EPs). Our approach for the first time makes cost-effective use of state-of-the-art microelectronics in medical measurement equipment, thus offering to replace discrete, single application devices used at present. PMID:12460729

Fuchs, Bernhard; Vogel, Sven; Schroeder, Dietmar

2002-12-01

414

Apparatus and method for defect testing of integrated circuits  

DOEpatents

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

2000-01-01

415

SEMICONDUCTOR INTEGRATED CIRCUITS: An ultra-high-speed direct digital frequency synthesizer implemented in GaAs HBT technology  

NASA Astrophysics Data System (ADS)

This paper presents a 10-GHz 8-bit direct digital synthesizer (DDS) microwave monolithic integrated circuit implemented in 1 ?m GaAs HBT technology. The DDS takes a double-edge-trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC-based ROM-less architecture, which can maximize the utilization ratio of the GaAs HBT's high-speed potential. With an output frequency up to 5 GHz, the DDS gives an average spurious free dynamic range of 23.24 dBc through the first Nyquist band, and consumes 2.4 W of DC power from a single -4.6 V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 × 2.0 mm2.

Gaopeng, Chen; Danyu, Wu; Zhi, Jin; Xinyu, Liu

2010-06-01

416

Funneling single photons into ridge-waveguide photonic integrated circuits  

NASA Astrophysics Data System (ADS)

The generation, manipulation and detection of single photons enable quantum communication, simulation and potentially computing protocols. However scaling to several qubits requires the integration of these functionalities in a single chip. A promising approach to the integration of single-photon sources in a chip is the use of single quantum dots embedded in photonic crystal waveguides or cavities. To this aim, efficient coupling of the emission from single quantum dots in photonic crystal cavities to low-loss ridge-waveguide (RWG) circuits is needed. This is usually hampered by the large mode mismatch between the two systems. In this work the emission of a photonic crystal (PhC) cavity realized on a GaAs/AlGaAs membrane and pumped by quantum dots has been effectively coupled and transferred through a long RWG (~1mm). By continuous tapering in both horizontal and vertical direction, transmission values (fiber-in, fiber-out) around 0.16 and 0.08% for RWG and coupled PhC waveguide-RWG have been achieved, respectively. This corresponds to about 2.8% coupling efficiency between the center of the PhC waveguide and the single-mode output fiber, a value much higher than what is achieved by top collection. It further shows that around 70% of the light in the PhC waveguide is coupled to the RWG. The emission from quantum dots in the cavity has been clearly identified by exciting from the top and collecting the photoluminescence from the cleaved facet of the device 1mm away from the cavity which enables the efficient coupling of single photons to RWG and detector circuits.

Fattah poor, S.; Midolo, L.; Li, L. H.; Linfield, E. H.; Schouwenberg, J. F. P.; Xia, T.; van Otten, F. W. M.; Hoang, T. B.; Fiore, A.

2013-02-01

417

Planar resonant multi-output transformer for printed circuit board integration  

Microsoft Academic Search

A converter with printed circuit board integrated transformer to supply 16 similar isolated loads is designed and manufactured. The transformer of the power converter is constructed as planar device consisting of printed circuit board spiral windings and ferrite polymer compound plates as magnetic core, which can be laminated to the printed circuit board. The design consists of one large primary

Eberhard Waffenschmidt; Joep Jacobs

2008-01-01

418

Time-resolved optical characterization of electrical activity in integrated circuits  

Microsoft Academic Search

If the rate of improvement in the performance of advanced silicon integrated circuits is to be sustained, new techniques for the measurement of electrical waveforms in operating circuits are needed. Critical factors dictating this requirement include the increased speed and complexity of circuits, the growing importance of faults that appear only during high-speed operation, and the use of flip-chip packaging

JAMES C. TSANG; JEFFREY ALAN KASH; DAVID P. VALLETT

2000-01-01

419

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits  

Microsoft Academic Search

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a

David K. Su; Marc J. Loinaz; Shoichi Masui; Bruce A. Wooley

1993-01-01

420

CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600°C  

Microsoft Academic Search

CMOS shift registers, buffers, and gray-scale representation circuits for integrated peripheral drive circuits of poly-Si TFT LCDs were fabricated at temperatures below 600°C on a glass substrate. The maximum operation frequency of the CMOS shift register was 1.25 MHz. The total power consumption of the 10 stage CMOS shift registers at a clock frequency of 46.8 kHz and a power

M. Takabatake; J. Ohwada; Y. A. Ono; K. Ono; A. Mimura; N. Konishi

1991-01-01

421

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20 um SiGe heterojunction bipolar transistors and circuits.  

SciTech Connect

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallele-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

Fritz, Karl (Mayo Foundation, Rochester, MN); Irwin, Timothy J. (Jackson & Tull Chartered Engineers, Washington, DC); Niu, Guofu (Auburn University, Auburn, AL); Fodness, Bryan (SGT, Inc., Greenbelt, MD); Carts, Martin A. (Raytheon ITSS, Greenbelt, MD); Marshall, Paul W. (Brookneal, VA); Reed, Robert A. (NASA/GSFC, Greenbelt, MD); Gilbert, Barry (Mayo Foundation, Rochester, MN); Randall, Barbara (Mayo Foundation, Rochester, MN); Prairie, Jason (Mayo Foundation, Rochester, MN); Riggs, Pam (Mayo Foundation, Rochester, MN); Pickel, James C. (PR& T, Inc., Fallbrook, CA); LaBel, Kenneth (NASA/GSFC, Greenbelt, MD); Cressler, John D. (Georgia Institute of Technology, Atlanta, GA); Krithivasan, Ramkumar (Georgia Institute of Technology, Atlanta, GA); Dodd, Paul Emerson; Vizkelethy, Gyorgy

2003-09-01

422

Relation between the leakage currents and the defects created in the oxide and at the interface in a short channel NMOS transistor  

Microsoft Academic Search

The problems associated with the defects in a MOS transistor become significant with increase of integration scale. These problems entail a degradation of the integrated circuit reliability, reduction of their lifetime and can be repeated on the transistor ageing. The defects can be translated by leakage currents such as substrate current Isub and gate current Ig. The aim of this

A. Bouhdada; S. Bakkali; A. Nouaçry; A. Touhami

1997-01-01

423

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.  

PubMed

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc. PMID:24441981

Gao, Pingqi; Zhang, Qing

2014-02-14

424

Lateral DMOS transistor optimized for high voltage BIMOS applications  

Microsoft Academic Search

Optimal placement of buried layer under a LDMOS transistor extends the usefulness of the device in high voltage BIMOS integrated circuits. Coupling the resurf effect and gate-underlaid concept results in a LDMOS transistor with uncompromised high voltage characteristics: Source-drain avalanche breakdown greater than 300 V and channel-substrate punchthrough breakdown greater than 200 V. The process utilized to fabricate the high

A. R. Alvarez; R. M. Roop; K. I. Ray; G. R. Getterneyer

1983-01-01

425

The Transistorized BH Loop Tracer and the Asteroid Curve Tracer  

Microsoft Academic Search

A transistorized B-H loop tracer was constructed in order to suppress the noises from the power supplies and the heater supplies. The C-R coupled integrator was employed to reduce the flicker noises from transistors. By use of the B-H loop circuits, the asteroid curve of magnetic thin films, which defines the switching threshold, as a function of longitudinal and transversal

Gen Matsumoto; Moriji Mizoguchi; Shuichi Iida

1966-01-01

426

Precision measurement technique of integrated MOS capacitor mismatching using a simple on-chip circuit  

Microsoft Academic Search

A precision measurement technique of the capacitor mis- matchings of integrated circuits has been required, that is insensitive to parasitic capacitors on the chip, stray capacitors in measuremmt circuits, and external noises. A new ac measurement technique is tle- veloped here that uses an on-chip source-follower circuit and a simple algorithm. The source-follower circuit lowers the output impedance and thereby

MASAKAZU FURUKAWA; H. Hatano; K. Hanihara

1986-01-01

427

Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits  

Microsoft Academic Search

Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic insertion of sleep transistors for power-gating. In particular, we propose a novel, layout-aware methodology that facilitates sleep transistor insertion and virtual-ground routing

Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino

2011-01-01

428

Design and fabrication of high-performance polycrystalline silicon thin-film transistor circuits on flexible steel foils  

Microsoft Academic Search

This paper discusses in detail the design and fabrication process for the realization of high-performance polycrystalline silicon thin-film transistors and digital CMOS circuitry on thin flexible stainless steel foils. A comprehensive approach to substrate preparation is first presented. For transistor fabrication, distinct processing approaches are examined, such as solid-phase and excimer laser crystallization for the active semiconductor region, thermal growth

Themistokles Afentakis; Miltiadis Hatalis; Apostolos T. Voutsas; John Hartzell

2006-01-01

429

Thermal coupling in integrated circuits: application to thermal testing  

Microsoft Academic Search

The power dissipated by the devices of a circuit can be construed as a signature of the circuit's performance and state. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements of the silicon die surface via built-in differential temperature sensors. In this paper, dynamic and spatial thermal behavioral characterization of VLSI MOS devices is presented

Josep Altet; Antonio Rubio; Emmanuel Schaub; Stefan Dilhaire; Wilfrid Claeys

2001-01-01

430

SEMICONDUCTOR INTEGRATED CIRCUITS: A 4 W K-band GaAs MMIC power amplifier with 22 dB gain  

NASA Astrophysics Data System (ADS)

A 4 W K-band AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) high power amplifier (PA) is reported. This amplifier is designed to fully match for a 50 ? input and output impedance based on the 0.15 ?m power PHEMT process. Under the condition of 5.6 V and 2.6 A DC bias, the amplifier has achieved a 22 dB small-signal gain, better than a 13 dB input return loss, and 36 dBm saturation power with 25% PAE from 19 to 22 GHz.

Zhengliang, Huang; Faxin, Yu; Yao, Zheng

2010-03-01

431

Integrated conditional teleportation and readout circuit based on a photonic crystal single chip  

NASA Astrophysics Data System (ADS)

We demonstrate the design of an integrated conditional quantum teleportation circuit and a readout circuit using a two-dimensional photonic crystal single chip. Fabrication and testing of the proposed quantum circuit can be accomplished with current or near future semiconductor process technology and experimental techniques. The readout part of our device can also be used on its own or integrated with other compatible optical circuits to achieve atomic state detection. Further improvement of the device in terms of compactness and robustness could be achieved by integrating it with sources and detectors in the optical regime.

Güney, Durdu Ö.; Meyer, David A.

2007-02-01

432

Focused ion beam damage to MOS integrated circuits  

SciTech Connect

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

FLEETWOOD,D.M.; CAMPBELL,ANN N.; HEMBREE,CHARLES E.; TANGYUNYONG,PAIBOON; JESSING,JEFFREY R.; SODEN,JERRY M.

2000-05-10

433

The large-scale integration of high-performance silicon nanowire field effect transistors.  

PubMed

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale. PMID:19755723

Li, Qiliang; Zhu, Xiaoxiao; Yang, Yang; Ioannou, Dimitris E; Xiong, Hao D; Kwon, Doo-Won; Suehle, John S; Richter, Curt A

2009-10-14

434

A NLTL-Based Integrated Circuit for a 70-200 GHz VNA System  

Microsoft Academic Search

We present an integrated circuit, based on nonlinear transmission lines (NLTL), for network analysis within 70-200 GHz. This is the first integrated circuit containing all elements of a S-Parameter test set: A multiplier to generate the RF signal, couplers to separate the incident and reflected waves, and a pair of high speed sampling circuits for down-converting the signals to lower

O. Wohigemuth; B. Agarwal; R. Pullela; D. Mensa; Q. Lee; J. Guthrie; M. J. W. Rodwell; R. Reuter; J. Braunstein; M. Schlechtweg; T. Krems; K. Kohler

1998-01-01

435

A complete monolithically-integrated circuit for all-optical generation of millimeter-wave frequencies  

SciTech Connect

An optoelectronic integrated circuit for generating mm-wave frequencies is demonstrated and design issues detailed. A monolithically integrated ring laser, optical amplifier, and photodiode generate electrical signals up to 85.2 GHz.

Vawter, G.A.; Mar, A.; Hietala, V.; Zolper, J.

1997-02-01

436

MultiChannel Integrated Circuits For Use In Research With Radioactive Ion Beams  

Microsoft Academic Search

The Integrated Circuits Design Research Laboratory at Southern Illinois University Edwardsville (SIUE) has been collaborating over the past several years with the Nuclear Reactions Group at Washington University (WU) on the development of a family of custom, multi-channel Integrated Circuits (ICs). To date, the collaboration has successfully produced two micro-chips. The first was an analog shaped and peak sensing chip

G. L. Engel; V. Vangapally; N. Duggireddi; L. G. Sobotka; J. M. Elson; R. J. Charity

2011-01-01

437

High electric stress and insulation challenges in integrated microelectronic circuits  

Microsoft Academic Search

The insulating layer in the transistor has decreased from 100 nm in the early 1970s to only a few nanometers today. This thin insulating layer gives rise to very high electric fields approaching 1000 kV\\/mm for an operating voltage of 1 V. Degradation of the insulation during ageing takes place due to the high field and may eventually lead to

Frøydis Oldervoll

2002-01-01

438

Performance and applications of gallium-nitride monolithic microwave integrated circuits (GaN MMICs)  

NASA Astrophysics Data System (ADS)

The evolution of wide-bandgap semiconductor transistor technology is placed in historical context with other active device technologies. The relative rapidity of GaN transistor development is noted and is attributed to the great parallel activity in the lighting sector and the historical experience and business model from the III-V compound semiconductor sector. The physical performance expectations for wide-bandgap technologies such as Gallium-Nitride Field-Effect Transistors (GaN FETs) are reviewed. We present some device characteristics. Challenges met in characterising, and prospects for modeling GaN FETs are described. Reliability is identified as the final remaining hurdle facing would-be foundries. Evolutionary and unsurprising applications as well as novel and revolutionary applications are suggested. Novel applications include wholly monolithic switchmode power supplies, simplified tools for ablation and diathermy in tissue, and very wide dynamic range circuits for audio or low phase noise signal generation. We conclude that now is the time to embark on circuit design of MMICs in wide-bandgap technology. The potential for fabless design groups to capitalise upon design IP without strong geopraphic advantage is noted.

Scott, Jonathan B.; Parker, Anthony E.

2007-12-01

439

Volatile general anesthetic sensing with organic field-effect transistors integrating phospholipid membranes.  

PubMed

The detailed action mechanism of volatile general anesthetics is still unknown despite their effect has been clinically exploited for more than a century. Long ago it was also assessed that the potency of an anesthetic molecule well correlates with its lipophilicity and phospholipids were eventually identified as mediators. As yet, the direct effect of volatile anesthetics at physiological relevant concentrations on membranes is still under scrutiny. Organic field-effect transistors (OFETs) integrating a phospholipid (PL) functional bio inter-layer (FBI) are here proposed for the electronic detection of archetypal volatile anesthetic molecules such as diethyl ether and halothane. This technology allows to directly interface a PL layer to an electronic transistor channel, and directly probe subtle changes occurring in the bio-layer. Repeatable responses of PL FBI-OFET to anesthetics are produced in a concentration range that reaches few percent, namely the clinically relevant regime. The PL FBI-OFET is also shown to deliver a comparably weaker response to a non-anesthetic volatile molecule such as acetone. PMID:22921091

Daniela Angione, Maria; Magliulo, Maria; Cotrone, Serafina; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Gobeljic, Danka; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2013-02-15

440

An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED  

NASA Astrophysics Data System (ADS)

Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is proposed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the parameters of LTPS TFTs were extracted from the LTPS TFTs made in our lab. The simulation results indicate that the circuit can fulfill the driving function.

Zhao, Li-Qing; Wu, Chun-Ya; Hao, Da-Shou; Yao, Ying; Meng, Zhi-Guo; Xiong, Shao-Zhen

2009-03-01

441

A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation  

Microsoft Academic Search

,4Mruct—A class of accurateanafog CMOS circuits is presented which relieson the square-law characteristic of MOStransistorsoperating in the saturated region. 'fIds class of circuits includes voltage multipliers, current multipliers, linear V-Z convertors (LVIC'S), linearZ- V convertors (LfVC's),current squaring circuits (CSC'S), and current divider circuits (DfVC's). Typicalfor thesecircuitsis an independent control of the sum as well as the difference between two gate-source

KLAAS BULT; ANDHANS WALLINGA

1987-01-01

442

Integrated circuits protection with the Langmuir-Blodgett Films.  

PubMed

Integrated circuits (ICs) can be protected from the environment with the encapsulating polymer layer. Protection properties of such a polymer barrier-layer depend strongly from the structure of thin region where polymer stays in direct contact with the IC surface. One of the interesting questions is how thick should this interphase film be to assure good environmental protection to the IC conductor lines, preventing from their corrosion and failure. In order to answer this question a set of electronic testers with Al conductor lines were modified with 1, 20, 50 multilayers of stearic acid molecules deposited in the Langmuir-Blodgett (LB) transfer method. Next, the electronic testers were subjected to the highly accelerated aging conditions (100% relative humidity (RH), 100 degrees C) for a period of up to 800 h and conductor lines resistivity changes were monitored. Electronic testers modified with 20 multilayers of stearic acid were better protected from the accelerated aging conditions than the testers modified with 1 monolayer or 50 multilayers. Obtained results suggest that the thickness of the interphase region separating IC surface and polymeric film should be in the range of 10 nm. PMID:15833702

Fabianowski, Wojciech; Jachowicz, Ryszard; Karpi?ska, Aleksandra; Azgin, Zbigniew

2005-04-01

443

Reactor protection system design using application specific integrated circuits  

SciTech Connect

Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed.

Battle, R.E.; Bryan, W.L.; Kisner, R.A.; Wilson, T.L. Jr.

1992-08-01

444

Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)  

NASA Astrophysics Data System (ADS)

Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

2000-03-01

445

Aesop: a tool for automated transistor sizing  

Microsoft Academic Search

This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area

Kye S. Hedlund

1987-01-01

446

Soft-error generation due to heavy-ion tracks in bipolar integrated circuits  

NASA Technical Reports Server (NTRS)

Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

Zoutendyk, J. A.

1984-01-01

447

Bridge fault simulation strategies for CMOS integrated circuits  

Microsoft Academic Search

Abstract Unfaulted Circuit Faulted Circuit X X After introducing the Primitive Bridge Function , a char - acteristic function describing the behavior of bridged com - ponents, we present a theorem for detecting feedback bridge faults We discuss two di erent methods of bridge fault simu - lation, one of which is new, and present experimental results relating the relative

Brian Chess; Tracy Larrabee

1993-01-01

448

Organic nanofibers integrated by transfer technique in field-effect transistor devices  

PubMed Central

The electrical properties of self-assembled organic crystalline nanofibers are studied by integrating these on field-effect transistor platforms using both top and bottom contact configurations. In the staggered geometries, where the nanofibers are sandwiched between the gate and the source-drain electrodes, a better electrical conduction is observed when compared to the coplanar geometry where the nanofibers are placed over the gate and the source-drain electrodes. Qualitatively different output characteristics were observed for top and bottom contact devices reflecting the significantly different contact resistances. Bottom contact devices are dominated by contact effects, while the top contact device characteristics are determined by the nanofiber bulk properties. It is found that the contact resistance is lower for crystalline nanofibers when compared to amorphous thin films. These results shed light on the charge injection and transport properties for such organic nanostructures and thus constitute a significant step forward toward a nanofiber-based light-emitting device.

2011-01-01

449

Electrical integrity of state-of-the-art 0.13 ?m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication  

Microsoft Academic Search

We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

K. W. Guarini; A. W. Topol; M. Ieong; R. Yu; L. Shi; M. R. Newport; D. J. Frank; D. V. Singh; G. M. Cohen; S. V. Nitta; D. C. Boyd; P. A. O'Neil; S. L. Tempest; H. B. Pogge; S. Purushothaman; W. E. Haensch

2002-01-01

450

Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment  

NASA Technical Reports Server (NTRS)

Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

1998-01-01

451

An Integrated Circuit for the in Situ Characterization of CMOS Best-Process Micromachining  

Microsoft Academic Search

We have developed an integrated circuit for in situ monitoring and characterization of CMOS post-process micromachining. In our demonstration, the circuit provides automated readout of N-well resistors surrounding each of 140 micromachining test structures at up to 14,000 samples per second per device during the post-process silicon etch. We use this circuit to examine the effect of pit size, surrounding

Brett Warneke; Kristofer S. J. Pister

2000-01-01

452

Materials integration and device fabrication of active matrix thin film transistor arrays for intracellular gene delivery  

NASA Astrophysics Data System (ADS)

Materials and process integration of a thin film transistor array for intra/extracellular probing are described in this study. A combinatorial rf magnetron sputter deposition technique was employed to investigate the electrical characteristics and micro-structural properties of molybdenum tungsten (MoW) high temperature electrodes as a function of the binary composition. In addition to the composition, the effect of substrate bias and temperature was investigated. The electrical resistivity of MoW samples deposited at room temperature with zero bias followed the typical Nordheim's rule as a function of composition. The resistivity of samples deposited with substrate bias is uniformly lower and obeyed the rule of mixtures as a function of composition. The metastable beta-W phase was not observed in the biased films even when deposited at room temperature. High resolution scanning electron microscopy revealed a more dense structure for the biased films, which correlated to the significantly lower film resistivity. In order to overcome deficiencies in sputtered silicon dioxide (SiO2 ) films the rf magnetron sputtering process was optimized by using a full factorial design of experiment (DOE). The optimized SiO2 film has a 5.7 MV/cm breakdown field and a 6.2 nm/min deposition rate at 10 W/cm 2 RF power, 3 mTorr pressure, 300°C substrate temperature, and 56 V substrate bias. Thin film transistors (TFTs) were also fabricated and characterized to show the prospective applications of the optimized SiO 2 films. The effect that direct current (DC) substrate bias has on radio frequency (RF)-sputter-deposited amorphous silicon (a-Si) films was also investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFT) that were completely sputter-deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film. (Abstract shortened by UMI.)

Jun, Seung-Ik

453

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)  

Microsoft Academic Search

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer

L. Mathew; Y. Du; A. V.-Y. Thean; M. Sadd; A. Vandooren; C. Parker; T. Stephens; R. Mora; R. Rai; M. Zavala; D. Sing; S. Kalpat; J. Hughes; R. Shimer; S. Jallepalli; G. Workman; W. Zhang; J. G. Fossum; B. E. White; B.-Y. Nguyen; J. Mogab

2004-01-01

454

Insulated-gate field-effect transistor strain sensor  

NASA Technical Reports Server (NTRS)

Strain sensors that can be switched on and off were fabricated from p-channel IGFET on thin filament n-type silicon crystals with silicon dioxide layer sputtered over transistor for passivation. Applications include integration with microelectronic circuits for multiplexing.

Gross, C.

1972-01-01

455

On the development of an integrated circuit for parallel processing of digital filter flow-diagrams  

Microsoft Academic Search

In various areas of application of digital filtering there is interest in a flexible integrated circuit for digital filtering which is easily programmable and operates fast enough for real time applications. The most important characteristics of such a circuit, such as: Structure, Types of instructions, Speed of operation in parallel processing Number of pins, etc., are discussed. In the case

R. Nouta

1980-01-01

456

Vibrating RF MEMS technology: fuel for an integrated micromechanical circuit revolution?  

Microsoft Academic Search

Having produced devices with sufficient Q, thermal stability, and manufacturability, for component-level use in present-day wireless handsets, vibrating RF MEMS technology is now poised to take its next logical steps: higher levels of circuit complexity and integration. In particular, as vibrating RF MEMS devices are perceived more as circuit building blocks than as standalone devices, and as the frequency processing

Clark T.-C. Nguyen

2005-01-01

457

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation  

Microsoft Academic Search

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be

Ming-Dou Ker; Cheng-Cheng Yen; Pi-Chia Shih

2008-01-01

458

Circuits  

NSDL National Science Digital Library

Contains 5 Physlets designed to solve the common AC and DC circuit problems. In addition to the usual RC and LRC simulations, there is an applet to plot non-linear I vs V response and an applet to plot frequency response.

Christian, Wolfgang; Belloni, Mario

2008-02-09

459

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications  

NASA Astrophysics Data System (ADS)

In this work we explore several doping schemes for aggressively scaled multi-gate field-effect transistor devices with the conduction channels wrapped around silicon fins (FinFETs) (HFin˜ 37 nm, WFin? 10 nm, Lg? 30 nm), using conventional ion implantation (I/I), and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, single-sided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher six transistors-static random access memory (6T-SRAM) static noise margin (SNM) values. Key advantages of the extension-less approach are: reduced cost and cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Si-epitaxial raised source/drain (SEG), and up to 20× lower IOFF. It, however, requires a tight spacer critical dimension (CD) control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins.

Veloso, Anabela; Keersgieter, An De; Brus, Stephan; Horiguchi, Naoto; Absil, Philippe P.; Hoffmann, Thomas

2011-04-01

460

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.  

PubMed

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-01-01

461

Call for papers second international workshop on compact thin-film transistor (TFT) modeling for circuit simulation  

Microsoft Academic Search

In recent years, the increasing use of active matrix flat-panel displays and bio-medical imagers in commercial electronic products has drawn a significant attention to thin-film transistors (TFT) and technologies. TFTs on amorphous- and poly-silicon as well as newly emerging organic, transparent metal oxide and nano-composite semiconductor technologies are becoming increasingly common. For example, flat panel displays are finding widespread use

Arokia Nathan; Bill Milne; Piero Migliorato; Maria Merlyne De Souza; Benjamin Iniguez; Norbert Fruehauf; Samar Saha; Jamal Deen; Reza Chaji; James B. Kuo; Hyun Jae Kim; Zhou Xing

2009-01-01

462

Sub30ps ECL circuits using high-fT Si and SiGe epitaxial base SEEW transistors  

Microsoft Academic Search

A high-performance bipolar technology is presented which involves Si and SiGe epitaxial base formation in a selective epitaxy emitter window (SEEW) structure. Si transistors have cut-off frequencies (f T) of 35-53 GHz while the fT of SiGe devices ranges from 45 GHz to 63 GHz. The SEEW structure allowed emitter width reduction to 0.35 ?m using optical lithography with 0.8

J. N. Burghartz; J. H. Comfort; G. L. Patton; J. D. Cressler; B. S. Meyerson; J. M. C. Stork; J. Y.-C. Sun; G. Scilla; J. Warnock; B. J. Ginsberg; K. Jenkins; K.-Y. Toh; D. L. Harame; S. R. Mader

1990-01-01

463

Novel Current-Scaling Current-Mirror Hydrogenated Amorphous Silicon Thin-Film Transistor Pixel Electrode Circuit with Cascade Capacitor for Active-Matrix Organic Light-Emitting Devices  

NASA Astrophysics Data System (ADS)

We proposed the hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with current-scaling function which is suitable for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current-mirror circuit, this circuit with the cascaded storage capacitors can provide a high data-to-organic light-emitting device (OLED) current ratio without increasing the a-Si:H TFT size. Moreover, since the number of signal line is reduced in the proposed pixel electrode circuit, the pixel electrode layout and the driving scheme can be simplified in comparison to previously reported cascade capacitor circuit. Finally, the proposed circuit can compensate for the threshold voltage variation of the driving TFT as well as the device geometric size mismatch and temperature effect.

Lee, Hojin; Yoo, Juhn S.; Kim, Chang-Dong; Chung, In-Jae; Kanicki, Jerzy

2007-03-01

464

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth  

NASA Astrophysics Data System (ADS)

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 ?m CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

465

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.  

ERIC Educational Resources Information Center

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

Muyskens, Mark A.

1997-01-01

466

Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers - 2nd Pass Correction.  

National Technical Information Service (NTIS)

Frequency multiplier microwave monolithic integrated circuits (MMICs) can be used for a variety of radio frequency (RF) and microwave systems. Several frequency doublers were designed using a 0.13-m gallium arsenide (GaAs) pseudomorphic high electron mobi...

J. E. Penn

2013-01-01

467

Potential Impact of MMICS (Monolithic Microwave Integrated Circuits) on Future Satellite Communications: Executive Summary.  

National Technical Information Service (NTIS)

This Executive Summary presents the results of a 17-month study on the future trends and requirments for Monolithic Microwave Integrated circuits (MMIC) for space communication application. Specifically this report identifies potential space communication...

V. E. Dunn

1988-01-01

468

Semiconductor Measurement Technology: ARPA/NBS Workshop I. Measurement Problems in Integrated Circuit Processing and Assembly.  

National Technical Information Service (NTIS)

The dual purpose of the workshop was (1) to announce and describe the new effort, 'Advancement of Reliability, Processing, and Automation for Integrated Circuits with the National Bureau of Standards,' sponsored by the Defense Advanced Research Projects A...

H. A. Schafft

1974-01-01

469