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1

Radiation-hardened transistor and integrated circuit  

DOEpatents

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Ma, Kwok K. (Albuquerque, NM)

2007-11-20

2

Heterostructure bipolar transistors and integrated circuits  

Microsoft Academic Search

A bipolar transmitter with a wide-gap emitter is presented. Examples of heterostructure implementations of IIL and ECL are discussed, and future device possibilities based on technological premises are considered. The concept and high-speed benefits of the widegap emitter are reviewed, including recent conceptual developments such as an inverted transistor design in which the collector is made smaller than the emitter

HERBERT KROEMER

1982-01-01

3

From The Lab to The Fab: Transistors to Integrated Circuits  

NASA Astrophysics Data System (ADS)

Transistor action was experimentally observed by John Bardeen and Walter Brattain in n-type polycrystalline germanium on December 16, 1947 (and subsequently polycrystalline silicon) as a result of the judicious placement of gold-plated probe tips in nearby single crystal grains of the polycrystalline material (i.e., the point-contact semiconductor amplifier, often referred to as the point-contact transistor).The device configuration exploited the inversion layer as the channel through which most of the emitted (minority) carriers were transported from the emitter to the collector. The point-contact transistor was manufactured for ten years starting in 1951 by the Western Electric Division of AT&T. The a priori tuning of the point-contact transistor parameters, however, was not simple inasmuch as the device was dependent on the detailed surface structure and, therefore, very sensitive to humidity and temperature as well as exhibiting high noise levels. Accordingly, the devices differed significantly in their characteristics and electrical instabilities leading to "burnout" were not uncommon. With the implementation of crystalline semiconductor materials in the early 1950s, however, p-n junction (bulk) transistors began replacing the point-contact transistor, silicon began replacing germanium and the transfer of transistor technology from the lab to the lab accelerated. We shall review the historical route by which single crystalline materials were developed and the accompanying methodologies of transistor fabrication, leading to the onset of the Integrated Circuit (IC) era. Finally, highlights of the early years of the IC era will be reviewed from the 256 bit through the 4M DRAM. Elements of IC scaling and the role of Moore's Law in setting the parameters by which the IC industry's growth was monitored will be discussed.

Huff, Howard R.

2003-09-01

4

Total dose effects in conventional bipolar transistors and linear integrated circuits  

Microsoft Academic Search

Total dose damage is investigated for discrete bipolar transistors and linear integrated circuits that are fabricated with older processing technologies, but are frequently used in space applications. The Kirk effect limits the current density of discrete transistors with high collector breakdown voltage, increasing their sensitivity to ionizing radiation because they must operate low injection levels. Bias conditions during irradiation had

A. H. Johnston; G. M. Swift; B. G. Rax

1994-01-01

5

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.  

PubMed

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics. PMID:23169057

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

6

CMOS-based carbon nanotube pass-transistor logic integrated circuits  

PubMed Central

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

7

Large-scale complementary integrated circuits based on organic transistors  

Microsoft Academic Search

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of

B. Crone; A. Dodabalapur; Y.-Y. Lin; R. W. Filas; Z. Bao; A. Laduca; R. Sarpeshkar; H. E. Katz; W. Li

2000-01-01

8

Fabrication of InP-based Optoelectronic Integrated Circuit (OEIC) Photoreceivers Using Shared Layer Integration of Heterojunction Bipolar Transistors  

E-print Network

Fabrication of InP-based Optoelectronic Integrated Circuit (OEIC) Photoreceivers Using Shared LayerP-based monolithic photoreceivers have been fabricated using a shared layer integration scheme of refracting-facet photodiodes (RFPDs) and heterojunction bipolar transistors (HBTs). An HBT was fabricated using a self

Yang, Kyounghoon

9

Dual-gate thin-film transistors, integrated circuits and sensors.  

PubMed

The first dual-gate thin-film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a-Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the first gate. The main advantage is that the threshold voltage can be set as a function of the applied second gate bias. The shift depends on the ratio of the capacitances of the two gate dielectrics. Here we review the fast growing field of DGTFTs. We summarize the reported operational mechanisms, and the application in logic gates and integrated circuits. The second emerging application of DGTFTs is sensitivity enhancement of existing ion-sensitive field-effect transistors (ISFET). The reported sensing mechanism is discussed and an outlook is presented. PMID:21671446

Spijkman, Mark-Jan; Myny, Kris; Smits, Edsger C P; Heremans, Paul; Blom, Paul W M; de Leeuw, Dago M

2011-08-01

10

Logic circuit function realization by one transistor.  

PubMed

Bottom-up nanowires are very attractive building blocks for functional devices due to their controllable properties. Meanwhile, assembling nanowires into large-scale integrated circuits is a daunting challenge because for the present circuits diverse nanowires are needed to grow simultaneously together closely. Here, a nanowire trigate transistor structure is proposed which can accomplish the functions of the logic gate circuits. By adding one channel-electrode junction as the output, this interesting one-channel structure is used to realize inverter and OR logic gates. In this way, logic circuits could shrink into a single transistor. PMID:23075033

Dai, Mingzhi; Dai, Ning

2012-11-14

11

THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development,  

E-print Network

THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit Scientific Abstract--We examine the feasibility of developing bipolar transistors with current-gain and power-frequency performance limits of InP-based bipolar transistors, and their potential for operation at low THz frequencies

Rodwell, Mark J. W.

12

Development of high-performance printed organic field-effect transistors and integrated circuits.  

PubMed

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications. PMID:25057765

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2014-07-24

13

Transistor sizing in CMOS circuits  

Microsoft Academic Search

The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

Mehmet A. Cirit

1987-01-01

14

Improved chopper circuit uses parallel transistors  

NASA Technical Reports Server (NTRS)

Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage.

1966-01-01

15

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide  

NASA Astrophysics Data System (ADS)

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

Liang, Shibo; Zhang, Zhiyong; Si, Jia; Zhong, Donglai; Peng, Lian-Mao

2014-08-01

16

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide  

SciTech Connect

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2?V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

2014-08-11

17

431 531 Class Notes 5 5 Transistors and Transistor Circuits  

E-print Network

431 531 Class Notes 5 5 Transistors and Transistor Circuits Although I will not follow the text in detail for the discussion of transistors, I will follow the text's philosophy. Unless one gets into device fabrication, it is generally not important to understand the inner workings of transistors

Frey, Raymond E.

18

Complementary GaAs junction-gated heterostructure field effect transistor fabrication for integrated circuits  

Microsoft Academic Search

A new GaAs junction-gated complementary logic technology that integrates a modulation doped p-channel heterostructure field effect transistor (pHFET) and a fully ion implanted n-channel JFET has recently been fabricated. High-speed, low-power operation has been demonstrated with loaded ring oscillators that show gate delays of 179 ps\\/stage for a power-delay product of 28 fJ at 1.2 V operation and 320 ps\\/stage

A. G. Baca; J. C. Zolper; M. E. Sherwin; P. J. Robertson; R. J. Shul; A. J. Howard; D. J. Rieger; J. F. Klem

1994-01-01

19

Evolvable circuit with transistor-level reconfigurability  

NASA Technical Reports Server (NTRS)

An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

2004-01-01

20

A Bonded-Micro-Platform Technology for Modular Merging of RF MEMS and Transistor Circuits  

E-print Network

A Bonded-Micro-Platform Technology for Modular Merging of RF MEMS and Transistor Circuits Ark µmechanical filters with integrated BiCMOS transistor circuits while attempting to preserve the Q of mounted are then released (together with devices) and compression bonded onto a transistor circuit wafer, making electrical

Nguyen, Clark T.-C.

21

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits  

Microsoft Academic Search

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors

Sotoudeh Hamedi-Hagh; Ahmet Bindal

2008-01-01

22

Inverter Circuits using Pentacene and ZnO Transistors  

Microsoft Academic Search

We report two types of integrated circuits based on a pentacene static-induction transistor (SIT), a pentacene thin-film transistor (TFT) and a zinc oxide (ZnO) TFT. The operating characteristics of a p-p inverter using pentacene SITs and a complementary inverter using a p-channel pentacene TFT and an n-channel ZnO TFT are described. The basic operation of logic circuits at a low

Hiroyuki Iechi; Yasuyuki Watanabe; Kazuhiro Kudo

2007-01-01

23

Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors  

SciTech Connect

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Blalock, Benjamin J [ORNL; Islam, Syed K [ORNL

2010-01-01

24

Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits  

NASA Astrophysics Data System (ADS)

Indium oxide (In2O3) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm2V-1s-1 and 16 cm2V-1s-1 for coplanar and staggered architectures, respectively. Integration of In2O3 transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (?250 °C) of In2O3 also allowed transistor fabrication on free-standing 50 ?m-thick polyimide foils. The resulting flexible In2O3 transistors exhibit good characteristics and remain fully functional even when bent to tensile radii of 4 mm.

Petti, Luisa; Faber, Hendrik; Münzenrieder, Niko; Cantarella, Giuseppe; Patsalas, Panos A.; Tröster, Gerhard; Anthopoulos, Thomas D.

2015-03-01

25

Modeling Advanced Avalanche Effects for Bipolar Transistor Circuit Design  

E-print Network

Modeling Advanced Avalanche Effects for Bipolar Transistor Circuit Design Vladimir Milovanovi operating frequency and high output power of modern bipolar transistor circuits increase, designers are trying to exploit transistor operating regions where they would be able satisfy both conditions, namely

Technische Universiteit Delft

26

An MOS transistor model for analog circuit design  

Microsoft Academic Search

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in

A. I. A. Cunha; M. C. Schneider; C. Galup-Montoro

1998-01-01

27

A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits.  

PubMed

Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process. PMID:21811011

Ghavami, Behnam; Raji, Mohsen; Pedram, Hossein

2011-08-26

28

Pass-transistor very large scale integration  

NASA Technical Reports Server (NTRS)

Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements.

Maki, Gary K. (Inventor); Bhatia, Prakash R. (Inventor)

2004-01-01

29

Physical modelling of vertical DMOS power transistors for circuit simulation  

NASA Astrophysics Data System (ADS)

A physical model for vertical DMOS power transistors is presented. The model takes into account various short channel effects in the DMOS channel region and the velocity saturation and the exact device geometry in the drift region. The model, aimed at computer aided design of power integrated circuits, has been implemented in the APLAC circuit simulator. A good agreement between the measured and simulated results for vertical DMOSTs is demonstrated.

Andersson, M.; Kuivalainen, P.

1994-01-01

30

Logic Circuits with Carbon Nanotube Transistors  

Microsoft Academic Search

We demonstrate logic circuits with field-effect transistors based on single carbon nanotubes. Our device layout features local gates that provide excellent capacitive coupling between the gate and nanotube, enabling strong electrostatic doping of the nanotube from p-doping to n-doping and the study of the nonconventional long-range screening of charge along the one-dimensional nanotubes. The transistors show favorable device characteristics such

Adrian Bachtold; Peter Hadley; Takeshi Nakanishi; Cees Dekker

2001-01-01

31

RF SMALL SIGNAL AVALANCHE CHARACTERIZATION AND REPERCUSSIONS ON BIPOLAR TRANSISTOR CIRCUIT DESIGN  

E-print Network

RF SMALL SIGNAL AVALANCHE CHARACTERIZATION AND REPERCUSSIONS ON BIPOLAR TRANSISTOR CIRCUIT DESIGN transistor circuits, electronic circuit designers are exploring regimes of transistor operation that meet on some important transistor properties like unilateral and maximum available power gain, as well

Technische Universiteit Delft

32

TFEL optoelectronic integrated circuit on Si  

NASA Astrophysics Data System (ADS)

A unique optoelectronic integrated circuit fabricated with AC thin film electroluminescent (TEL) devices directly onto the drain of an Si DMOS transistor is demonstrated. DMOS switching controls the high voltage ratio between the TFEL device and DMOS transistor. Active matrix addressing for electroluminescent devices is demonstrated using CMOS circuitry.

Thomas, C. B.; McClean, I. P.; Stevens, R.; Cranton, W. M.

1994-08-01

33

Transistor circuit increases range of logarithmic current amplifier  

NASA Technical Reports Server (NTRS)

Circuit increases the range of a logarithmic current amplifier by combining a commercially available amplifier with a silicon epitaxial transistor. A temperature compensating network is provided for the transistor.

Gilmour, G.

1966-01-01

34

High-performance top-gated monolayer SnS2 field-effect transistors and their integrated logic circuits.  

PubMed

Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm(2) V(-1) s(-1), much higher than that of the back-gated counterparts (~1 cm(2) V(-1) s(-1)). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics. PMID:23989804

Song, H S; Li, S L; Gao, L; Xu, Y; Ueno, K; Tang, J; Cheng, Y B; Tsukagoshi, K

2013-10-21

35

Modeling and simulation of insulated-gate field-effect transistor switching circuits  

Microsoft Academic Search

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET

HAROLD SHICHMAN; DAVID A. HODGES

1968-01-01

36

Displacement Damage in Bipolar Linear Integrated Circuits  

NASA Technical Reports Server (NTRS)

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Rax, B. G.; Johnston, A. H.; Miyahira, T.

2000-01-01

37

Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign  

E-print Network

EE134 1 Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and Design of text. EE134 6 Last LectureLast Lecture ! Last lecture " Moore's Law " Challenges in digital IC design in complexity of ICsSummarizes progress in complexity of ICs 1971 P4 2000 2,300 transistors 108 KHz operation 42

38

4.0-inch Active-Matrix Organic Light-Emitting Diode Display Integrated with Driver Circuits Using Amorphous In-Ga-Zn-Oxide Thin-Film Transistors with Suppressed Variation  

Microsoft Academic Search

We have newly developed a 4.0-in. quarter video graphics array (QVGA) active-matrix organic light-emitting diode (AMOLED) display integrated with gate and source driver circuits using amorphous In-Ga-Zn-oxide (IGZO) thin-film transistors (TFTs). Focusing on a passivation layer in an inverted staggered bottom gate structure, the threshold voltage of the TFTs can be controlled to have ``normally-off'' characteristics with suppressed variation by

Hiroki Ohara; Toshinari Sasaki; Kousei Noda; Shunichi Ito; Miyuki Sasaki; Yuta Endo; Shuhei Yoshitomi; Junichiro Sakata; Tadashi Serikawa; Shunpei Yamazaki

2010-01-01

39

Transistor Level Circuit Experiments using Evolvable Hardware  

NASA Technical Reports Server (NTRS)

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

2005-01-01

40

Control of Exciton Fluxes in an Excitonic Integrated Circuit  

Microsoft Academic Search

Efficient signal communication uses photons. Signal processing, however, uses an optically inactive medium, electrons. Therefore, an interconnection between electronic signal processing and optical communication is required at the integrated circuit level. We demonstrated control of exciton fluxes in an excitonic integrated circuit. The circuit consists of three exciton optoelectronic transistors and performs operations with exciton fluxes, such as directional switching

Alex A. High; Ekaterina E. Novitskaya; Leonid V. Butov; Micah Hanson; Arthur C. Gossard

2008-01-01

41

Nonlinear Oscillations in a Unijunction Transistor Circuit  

NASA Astrophysics Data System (ADS)

Many interesting nonlinear behaviors have been studied in distributed (glow-discharge and Q-machine plasmas) and non-distributed (nonlinear electronic oscillators) nonlinear systems that can be modeled by the van der Pol equation.footnotetextPhys. Plasmas 3, 4421 (1996).^,footnotetextGeophys. Res. Lett., 21, 1011 (1994).^,footnotetextPhys. Rev. A 44, 6877 (1991). This work describes an experimental, theoretical and computational investigation of two nonlinear electronic oscillators which have a unijunction transistor as a nonlinear element. The circuits that are examined in this paper are a sine wave oscillator and a relaxation oscillator. The functioning of the unijunction transistor is explained in detail. A full derivation of the differential equation describing the sine wave oscillator is made, and the results of numerical simulations based on this differential equation are compared to experimental data. Descriptions and explanations of two types of non-autonomous (driven) phenomena, entrainment and periodic pulling will be given. [1] Present affiliation: Univ. of Notre Dame, [2] Present affiliation: SUNY Oswego

Christopher, Steven; Zielinski, John; Koepke, Mark

2012-10-01

42

High-Resolution Inkjet Printing of All-Polymer Transistor Circuits  

Microsoft Academic Search

Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and

H. Sirringhaus; T. Kawase; R. H. Friend; T. Shimoda; M. Inbasekaran; W. Wu; E. P. Woo

2000-01-01

43

Testing tri-state and pass transistor circuit structures  

E-print Network

effort for tristate and pass transistor structures. We do circuit level modeling to help develop and validate gate level models, which can be used in production ATPG. We study the two primary effects of interest, capacitive coupling and leakage...

Parikh, Shaishav Shailesh

2005-11-01

44

Integration of Cell Membranes and Nanotube Transistors  

E-print Network

Integration of Cell Membranes and Nanotube Transistors Keith Bradley, Alona Davis, Jean. As the nanoelectronic device, we use a nanotube network transistor, which incorporates many individual nanotubes as transistors, and that the two systems interact. Further, we use the interaction to study the charge

Gruner, George

45

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization  

Microsoft Academic Search

Abstract: this paper.Given the MOS circuit topology, the delay can be controlled byvarying the sizesof transistors in the circuit. Here, the size of a transistor is measured in terms of its channelwidth, since the channel lengths in a digital circuit are generally uniform. Roughly speaking,the sizes of certain transistors can be increased to reduce the circuit delay at the expense

Sachin S. Sapatnekar; Vasant B. Rao; Pravin M. Vaidya; Sung-mo Kang

1993-01-01

46

Parallel transistor level circuit simulation using domain decomposition methods  

Microsoft Academic Search

This paper presents an efficient parallel transistor level full-chip circuit simulation tool with SPICE-accuracy. The new approach partitions the circuit into a linear domain and several non-linear domains based on circuit non-linearity and connectivity. The linear domain is solved by parallel fast linear solver while nonlinear domains are parallelly distributed into different processors and solved by direct solver. Parallel domain

He Peng; Chung-kuan Cheng

2009-01-01

47

Ultra-low power microwave CHFET integrated circuit development  

Microsoft Academic Search

This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 μm gate nJFETs

A. G. Baca; V. M. Hietala; D. Greenway; L. R. Sloan; R. J. Shul; G. P. Muyshondt; D. F. Dubbert

1998-01-01

48

Single-photon transistor in circuit quantum electrodynamics.  

PubMed

We introduce a circuit quantum electrodynamical setup for a "single-photon" transistor. In our approach photons propagate in two open transmission lines that are coupled via two interacting transmon qubits. The interaction is such that no photons are exchanged between the two transmission lines but a single photon in one line can completely block or enable the propagation of photons in the other line. High on-off ratios can be achieved for feasible experimental parameters. Our approach is inherently scalable as all photon pulses can have the same pulse shape and carrier frequency such that output signals of one transistor can be input signals for a consecutive transistor. PMID:23971573

Neumeier, Lukas; Leib, Martin; Hartmann, Michael J

2013-08-01

49

A "Single-Photon" Transistor in Circuit Quantum Electrodynamics  

E-print Network

We introduce a circuit quantum electrodynamical setup for a "single-photon" transistor. In our approach photons propagate in two open transmission lines that are coupled via two interacting transmon qubits. The interaction is such that no photons are exchanged between the two transmission lines but a single photon in one line can completely block respectively enable the propagation of photons in the other line. High on-off ratios can be achieved for feasible experimental parameters. Our approach is inherently scalable as all photon pulses can have the same pulse shape and carrier frequency such that output signals of one transistor can be input signals for a consecutive transistor.

Lukas Neumeier; Martin Leib; Michael J. Hartmann

2013-07-26

50

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature  

NASA Technical Reports Server (NTRS)

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

51

GaAs Optoelectronic Integrated-Circuit Neurons  

NASA Technical Reports Server (NTRS)

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

52

6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design  

E-print Network

6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design Prof. Joel L;6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design Prof. Joel L. Dawson Page 2's move on to the matter of biasing a transistor circuit. What does this mean, and what constitutes a good

Goldwasser, Shafi

53

An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization  

E-print Network

An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization topology, the delay can be controlled by varying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit

Sapatnekar, Sachin

54

Bioluminescent bioreporter integrated circuit  

DOEpatents

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

2000-01-01

55

Hybrid integrated circuits: A survey  

Microsoft Academic Search

Two proximity fuzes under development at the Harry Diamond Laboratories use thick-film hybrid integrated circuits. A survey of the hybrid integrated circuit industry was conducted to determine its capability to produce these circuits in volume within the continental United States. The circuits as complex as those used in XM587 and XM734 fuzes are in volume production using certain types of

P. Ingersoll

1977-01-01

56

L.DMOS devices for high voltage integrated circuits  

NASA Astrophysics Data System (ADS)

The lateral double-diffused MOS (metal oxide semiconductors) transistor (L.DMOS) technique for the fabrication of switches for power integrated circuits is described. The device is compatible with low voltage circuits, is easy to process, shows a high voltage handling capacity, and good insulating properties. Investigation of the design and insulation parameters of these transistors versus various geometrical and physical parameters is made on the basis of simplified analytical and two dimensional numerical methods. Diodes and transistors of this type are made which validate the findings of this research.

Nezar, Azzouz

57

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 693 Buffer Minimization in Pass Transistor Logic  

E-print Network

2001 693 Buffer Minimization in Pass Transistor Logic Hai Zhou and Adnan Aziz Abstract--With shrinking feature sizes and increasing transistor counts on chips, demands for higher speed and lower power make metal­oxide­semiconductors. Among them, pass transistor logic (PTL) is of great promise. Since delay

Zhou, Hai

58

Bipolar transistor modeling of avalanche generation for computer circuit simulation  

Microsoft Academic Search

An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.

R. W. Dutton

1975-01-01

59

Nonlinear system analysis in bipolar integrated circuits  

NASA Astrophysics Data System (ADS)

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio frequency (AF) voltage at the IC amplifier output terminal caused by an amplitude modulated (AM) RF signal at the IC amplifier input terminal was calculated and compared to measured values. Two broadband IC amplifiers were investigated: (1) a cascode circuit using a CA3026 dual differential pair; (2) a unity gain voltage follower circuit using a micro A741 operational amplifier (op amp). Before using NCAP for RFI analysis, the model parameters for each bipolar junction transistor (BJT) in the integrated circuit were determined. Probe measurement techniques, manufacturer's data, and other researcher's data were used to obtain the required NCAP BJT model parameter values. An important contribution included in this effort is a complete set of NCAP BJT model parameters for most of the transistor types used in linear IC's.

Fang, T. F.; Whalen, J. J.

1980-01-01

60

The Integrated Circuit Game  

NSDL National Science Digital Library

Integrated circuits can be found in almost every modern electrical device; such as computers, cars, television sets, CD players, cell phones, and so on. But what is an integrated circuit and what is the history behind it? Learn about Nobel Laureate Jack Kilby and his part in the invention that is the basis of all modern technology. In the beginning of this game you have to take the quiz consisting of four questions, otherwise you will not be able to move on in this game. The answers to the questions are found in the museum. As "Maria" you walk around in the fantasy town "Techville" in Texas. At some points you have to give the right answers or figure out something before you can move on. You will pass a portal that takes you back in time to Nobel Laureate Jack Kilby's lab in 1958, among other things. The challenge in this game is to make it to the end.

61

Monolithic Optoelectronic Integrated Circuit  

NASA Technical Reports Server (NTRS)

Monolithic optoelectronic integrated circuit (OEIC) receives single digitally modulated input light signal via optical fiber and converts it into 16-channel electrical output signal. Potentially useful in any system in which digital data must be transmitted serially at high rates, then decoded into and used in parallel format at destination. Applications include transmission and decoding of control signals to phase shifters in phased-array antennas and also communication of data between computers and peripheral equipment in local-area networks.

Bhasin, Kul B.; Walters, Wayne; Gustafsen, Jerry; Bendett, Mark

1990-01-01

62

Flexible organic transistors and circuits with extreme bending stability  

NASA Astrophysics Data System (ADS)

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100?m. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5?m), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2010-12-01

63

Analog and digital circuits using organic thin-film transistors on polyester substrates  

Microsoft Academic Search

We have fabricated and characterized analog and digital circuits using organic thin-film transistors on polyester film substrates. These are the first reported dynamic results for organic circuits fabricated on polyester substrates. The high-performance pentacene transistors yield circuits with the highest reported clock frequencies for organic circuits

M. G. Kane; J. Campi; M. S. Hammond; F. P. Cuomo; B. Greening; C. D. Sheraw; J. A. Nichols; D. J. Gundlach; J. R. Huang; C. C. Kuo; L. Jia; H. Klauk; T. N. Jackson

2000-01-01

64

Heat Generation and Transport in Nanometer-Scale Transistors Heat problems in ever-smaller integrated circuits include hot-spots at transistor drain areas, reduced heat conduction in new devices and higher thermal resistance at material boundaries  

Microsoft Academic Search

As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin

Eric Pop; Sanjiv Sinha; Kenneth E. Goodson

65

Rapid evolution of analog circuits configured on a field programmable transistor array  

NASA Technical Reports Server (NTRS)

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

66

Run-Time Programming of Analog Circuits Using Floating-Gate Transistors  

E-print Network

Run-Time Programming of Analog Circuits Using Floating-Gate Transistors David W. Graham Lane of floating-gate (FG) transistors provides programmability to analog circuitry and, hence, the ability to recalibrate an analog system. If the FG transistors are programmed indirectly by using a second transistor

Graham, David W.

67

Chapter II MOS Transistor Modelling for MMW Circuits ChapterChapterChapterChapter IIIIIIII  

E-print Network

Chapter II MOS Transistor Modelling for MMW Circuits 15 ChapterChapterChapterChapter IIIIIIII MOS transistor model and layout issues One of the most important design issues in millimeter wave circuit design in modern MOS technologies is active devices and related parasitic elements modeling. The MOS transistor

Paris-Sud XI, Université de

68

Extraction of Gate Level Models from Transistor Circuits by FourValued Symbolic Analysis  

E-print Network

Extraction of Gate Level Models from Transistor Circuits by Four­Valued Symbolic Analysis Randal E­level representation of an MOS transistor circuit. The resulting model contains only four­valued unit and zero delay transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones

Bryant, Randal E.

69

Transistor Sizing of Energy-DelayEfficient Circuits Paul I. Penzes, Mika Nystrom, Alain J. Martin  

E-print Network

Transistor Sizing of Energy-Delay­Efficient Circuits Paul I. P´enzes, Mika Nystr¨om, Alain J,mika,alain¡ @async.caltech.edu Abstract This paper studies the problem of transistor sizing of CMOS circuits transistor sizes. We then study an efficient iteration procedure that can further improve the original

70

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis  

NASA Technical Reports Server (NTRS)

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

2008-01-01

71

Integrated circuit cell library  

NASA Technical Reports Server (NTRS)

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

72

A high performance CMOS readout integrated circuit for IRFPA  

Microsoft Academic Search

A high performance, 128×128 pixel, snapshot Readout Integrated Circuit (ROIC) for IRFPA has been fabricated with 0.5mum Double Poly Double Metal (DPDM) n-well CMOS process. The pixel cell circuit uses an improved direct injection structure with only four transistors to maintain large enough integration capacitror. One pixel cell occupies an area of 50×50mum2. Each row's pixel signals are readout to

Xiaojuan Xia; Liang Xie; Weifeng Sun

2008-01-01

73

Atomtronic Circuits of Diodes and Transistors  

SciTech Connect

We illustrate that open quantum systems composed of neutral, ultracold atoms in one-dimensional optical lattices can exhibit behavior analogous to semiconductor electronic circuits. A correspondence is demonstrated for bosonic atoms, and the experimental requirements to realize these devices are established. The analysis follows from a derivation of a quantum master equation for this general class of open quantum systems.

Pepino, R. A.; Cooper, J.; Anderson, D. Z.; Holland, M. J. [JILA, National Institute of Standards and Technology and Department of Physics, University of Colorado, Boulder, Colorado 80309 (United States)

2009-10-02

74

Atomtronic circuits of diodes and transistors.  

PubMed

We illustrate that open quantum systems composed of neutral, ultracold atoms in one-dimensional optical lattices can exhibit behavior analogous to semiconductor electronic circuits. A correspondence is demonstrated for bosonic atoms, and the experimental requirements to realize these devices are established. The analysis follows from a derivation of a quantum master equation for this general class of open quantum systems. PMID:19905552

Pepino, R A; Cooper, J; Anderson, D Z; Holland, M J

2009-10-01

75

High-voltage (100 V) ChipfilmTM single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays  

NASA Astrophysics Data System (ADS)

System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (<10 ?m) substrate. A breakdown voltage of more than 100 volts with drain-to-source saturation current Ids(sat)?85 ?A/?m for N-LDMOS and Ids(sat)?20 ?A/?m for P-LDMOS is predicted through process and device simulations.

Asif, A.; Richter, H.; Burghartz, J. N.

2009-05-01

76

Confinement-modulated junctionless nanowire transistors for logic circuits.  

PubMed

We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices. PMID:25297836

Vaurette, François; Leturcq, Renaud; Lepilliet, Sylvie; Grandidier, Bruno; Stiévenard, Didier

2014-11-21

77

Confinement-modulated junctionless nanowire transistors for logic circuits  

NASA Astrophysics Data System (ADS)

We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices.

Vaurette, François; LeturcqPresent Address: Crp Gabriel Lippmann, Département Science Et Analyse Des Matériaux, 41, Rue Du Brill-4422 Belvaux-Luxembourg., Renaud; Lepilliet, Sylvie; Grandidier, Bruno; Stiévenard, Didier

2014-10-01

78

Amorphous silicon TFT circuit integration for OLED displays on glass and plastic  

Microsoft Academic Search

This paper reviews design considerations along with measurement results pertinent to amorphous silicon (a-Si:H) thin film transistor (TFT) drive circuits for active matrix organic light emitting diode (AMOLED) displays. We describe both pixel architectures and TFT circuit topologies that are amenable for vertically integrated, high aperture ratio pixels. Here, the OLED layer is integrated directly above the TFT circuit layer,

Arokia Nathan; Kapil Sakariya; A. Kumar; P. Servati; K. S. Karim; D. Striakhilev; A. Sazonov

2003-01-01

79

SEMICONDUCTOR INTEGRATED CIRCUITS: An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process  

NASA Astrophysics Data System (ADS)

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 ?m CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

Peijun, Gao; J, Oh N.; Hao, Min

2009-08-01

80

Thermoelectricity from wasted heat of integrated circuits  

NASA Astrophysics Data System (ADS)

We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systems-on-chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

Fahad, Hossain; Hasan, Md.; Li, Guodong; Hussain, Muhammad

2013-06-01

81

Photonic integrated circuits for optical logic applications  

E-print Network

The optical logic unit cell is the photonic analog to transistor-transistor logic in electronic devices. Active devices such as InP-based semiconductor optical amplifiers (SOA) emitting at 1550 nm are vertically integrated ...

Williams, Ryan Daniel

2007-01-01

82

Four-gate transistor analog multiplier circuit  

NASA Technical Reports Server (NTRS)

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

2011-01-01

83

SiC JFET Transistor Circuit Model for Extreme Temperature Range  

NASA Technical Reports Server (NTRS)

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.

2008-01-01

84

Flexible Black Phosphorus Ambipolar Transistors, Circuits and AM Demodulator.  

PubMed

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles. PMID:25715122

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

85

Silicon integrated circuit technology from past to future  

Microsoft Academic Search

Tremendous progress of the silicon integrated circuits (ICs) has been driven by the downsizing of their components such as MOS field effect transistors (MOSFETs) over 30 years. In order to maintain the progress for future, every dimension of the MOSFETs has to be shrunk continuously with almost the same ratio. However, the dimensions are now close to their limit of

Hiroshi Iwai; Shun'ichiro Ohmi

2002-01-01

86

Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint  

E-print Network

Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint Manjit University Park, PA 16802 Mary Jane Irwin Abstract We consider the problem of transistor sizing in a static that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption

He, Lei

87

431 531 Class Notes 8 5.8 More on Transistor Circuits  

E-print Network

431 531 Class Notes 8 5.8 More on Transistor Circuits 5.8.1 Intrinsic Emitter Resistance One consequenceof the Ebers-Moll equation, which wewill discuss later, is that the transistor emitter has an e ective resistance is just the usual parallel resistance of R1, R2, and the transistor input impedance RE

Frey, Raymond E.

88

54 IRE TRANSACTIONS-CIRCUIT THEORY March Solution of a Transistor Transient Response Problem*  

E-print Network

54 IRE TRANSACTIONS-CIRCUIT THEORY March Solution of a Transistor Transient Response Problem-frequency and switching applications of transistors. A single transient response measure- ment can, in principle, yield of the device allows its response to any other driving curve-shape to be calculated.' Calculation of transistor

Macdonald, James Ross

89

CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers  

E-print Network

radar, distance sensor, through wall radar to high speed, short distance communications. The CMOS integrated circuit is an attractive, low cost approach for implementing UWB technology. The improving cut-off frequency of the transistor in CMOS process...

Xu, Rui

2010-10-12

90

Recent progress on ZnO-based metal-semiconductor field-effect transistors and their application in transparent integrated circuits.  

PubMed

Metal-semiconductor field-effect transistors (MESFETs) are widely known from opaque high-speed GaAs or high-power SiC and GaN technology. For the emerging field of transparent electronics, only metal-insulator-semiconductor field-effect transistors (MISFETs) were considered so far. This article reviews the progress of high-performance MESFETs in oxide electronics and reflects the recent advances of this technique towards transparent MESFET circuitry. We discuss design prospects as well as limitations regarding device performance, reliability and stability. The presented ZnO-based MESFETs and inverters have superior properties compared to MISFETs, i.e., high channel mobilities and on/off-ratios, high gain, and low uncertainty level at comparatively low operating voltages. This makes them a promising approach for future low-cost transparent electronics. PMID:20878625

Frenzel, Heiko; Lajn, Alexander; von Wenckstern, Holger; Lorenz, Michael; Schein, Friedrich; Zhang, Zhipeng; Grundmann, Marius

2010-12-14

91

Transistor sizing of custom high-performance digital circuits with parametric yield considerations  

Microsoft Academic Search

Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. Due to the increasing importance of process variations in deep sub-micron circuits, nominal circuit tuning is not sufficient, and the sizing problem warrants revisiting. This paper addresses the sizing problem statistically in which transistor sizes are automatically adjusted to maximize parametric yield at a

Daniel K. Beece; Jinjun Xiong; Chandu Visweswariah; Vladimir Zolotov; Yifang Liu

2010-01-01

92

Printed Sub-2 V Gel-Electrolyte-Gated Polymer Transistors and Circuits  

E-print Network

Printed Sub-2 V Gel-Electrolyte-Gated Polymer Transistors and Circuits By Yu Xia, Wei Zhang and characterization of low voltage, printed polymer transistors and circuits that employ a novel high capacitance gel electrolyte as the gate insulator. The gel electrolyte, a so-called ion gel, comprises a room temperature

Kim, Chris H.

93

Variational integrators for electric circuits  

SciTech Connect

In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

Ober-Blöbaum, Sina, E-mail: sinaob@math.upb.de [Computational Dynamics and Optimal Control, University of Paderborn (Germany)] [Computational Dynamics and Optimal Control, University of Paderborn (Germany); Tao, Molei [Courant Institute of Mathematical Sciences, New York University (United States)] [Courant Institute of Mathematical Sciences, New York University (United States); Cheng, Mulin [Applied and Computational Mathematics, California Institute of Technology (United States)] [Applied and Computational Mathematics, California Institute of Technology (United States); Owhadi, Houman; Marsden, Jerrold E. [Control and Dynamical Systems, California Institute of Technology (United States) [Control and Dynamical Systems, California Institute of Technology (United States); Applied and Computational Mathematics, California Institute of Technology (United States)

2013-06-01

94

A hybrid nanomemristor/transistor logic circuit capable of self-programming  

PubMed Central

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

95

MOS Field Effect Transistors (MOSFETs), Part II The purpose of this lab is to build and test several MOSFET-based circuits. Two MOSFET  

E-print Network

EE321 Lab MOS Field Effect Transistors (MOSFETs), Part II The purpose of this lab is to build and test several MOSFET-based circuits. Two MOSFET packages will be used: the CMOS 4007 integrated circuit that contains 6 MOSFET's (3 n-channel and 3 p-channel), and an IRF710 single MOSFET (n-channel, high

Wedeward, Kevin

96

A New Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor and Lateral Diode Employing the Separated Schottky Anode for a Power Integrated Circuit  

NASA Astrophysics Data System (ADS)

A new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) and lateral diode employing the separated Schottky anode (SSCA) is proposed and verified by the two dimensional numerical simulation based on experimental results. The Schottky barrier between the aluminum and lightly doped n-type silicon (Al/n-Si) of SSCA provides the potential difference between the n- anode contact and p+ anode to enhance the hole injection of p+ anode, which improves the forward current-voltage (I-V) characteristics. The anode region of SSCA-LIGBT is successfully decreased without negative differential resistance (NDR) regime and sacrificing the switching speed by employing contact. The SSCA structure applied to the diode also considerably improves the reverse recovery compared to the conventional p-i-n diode and reverse blocking capability compared to conventional Schottky diode.

Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo

2007-04-01

97

Mouldable all-carbon integrated circuits  

NASA Astrophysics Data System (ADS)

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027cm2V-1s-1 and an ON/OFF ratio of 105. The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Sun, Dong-Ming; Timmermans, Marina Y.; Kaskela, Antti; Nasibulin, Albert G.; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I.; Ohno, Yutaka

2013-08-01

98

Graphene-Dielectric Integration for Graphene Transistors  

PubMed Central

Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-? dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities. PMID:21278913

Liao, Lei; Duan, Xiangfeng

2010-01-01

99

Graphene-Dielectric Integration for Graphene Transistors.  

PubMed

Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-? dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities. PMID:21278913

Liao, Lei; Duan, Xiangfeng

2010-11-22

100

Control of Exciton Fluxes in an Excitonic Integrated Circuit  

NASA Astrophysics Data System (ADS)

Efficient signal communication uses photons. Signal processing, however, uses an optically inactive medium, electrons. Therefore, an interconnection between electronic signal processing and optical communication is required at the integrated circuit level. We demonstrated control of exciton fluxes in an excitonic integrated circuit. The circuit consists of three exciton optoelectronic transistors and performs operations with exciton fluxes, such as directional switching and merging. Photons transform into excitons at the circuit input, and the excitons transform into photons at the circuit output. The exciton flux from the input to the output is controlled by a pattern of the electrode voltages. The direct coupling of photons, used in communication, to excitons, used as the device-operation medium, may lead to the development of efficient exciton-based optoelectronic devices.

High, Alex A.; Novitskaya, Ekaterina E.; Butov, Leonid V.; Hanson, Micah; Gossard, Arthur C.

2008-07-01

101

Vertically Integrated Circuits at Fermilab  

SciTech Connect

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

2009-01-01

102

The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Circuits  

Microsoft Academic Search

Transistor size optimization is one method to reduce the power dissipation of CMOS VLSI circuits. Analysis shows that parasitic capacitances and velocity saturation of submicron technologies favor wider than minimum transistor sizes. The reason is that they allow for a larger reduction of the supply voltage which results in more substantial power savings. Spice simulation of prescalers with differently scaled

Robert Rogenmoser; Hubert Kaeslin; Norbert Felber

1996-01-01

103

Integrated circuit tester using interferometric imaging  

SciTech Connect

An interferometric imaging technique can provide time-resolved diagnostics of semiconductor integrated circuits. The semiconductor device is placed in one arm of an interferometer and illuminated with a picosecond pulse from a sub-bandgap infrared laser. As the laser passes through the semiconductor, it samples local variations in the index of refraction. These variations are caused by a number of physical phenomena including dopants in the material such as those used to form device structures, heating due to the flow of electrical currents, and changes in carrier concentration due to injection. These variations have both static and dynamic components. The dynamic components are associated with the normal device operation and are the most interesting. To separate the components, the device is first imaged in a quiescent state, and then a second image is taken after the device enters a known voltage state. Differences between the two images determine where the local index of refraction has changed and by how much. A third image taken with the reference arm of the interferometer blocked, allows device structures to be associated with particular changes in the index of refraction. Activation of the voltage state is synchronized with the pulsed illumination source, and the time delay between the application of the voltage and the laser probe pulse allows us to take a series of images that map the time evolution of the interferogram. This technique offers an exciting new diagnostic for semiconductor integrated circuits. The technique is noninvasive and compatible with high-speed operation of integrated circuits. The picosecond resolution enables us to either characterize specific logic states or watch an individual device turn on. This imaging technique is sensitive to all of the index of refraction changes that can be associated with IC`s. These include heating due to current flowing through narrow wires and charge injection into the depletion region of a transistor.

Donaldson, W.R.; Michaels, E.M.R.; Akowuah, K. [and others

1997-04-01

104

Self-integration of nanowires into circuits via guided growth  

PubMed Central

The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom–up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel “self-integration” of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

2013-01-01

105

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress  

NASA Technical Reports Server (NTRS)

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Mclyman, W. T. (inventor)

1981-01-01

106

Solution methods for very highly integrated circuits  

Microsoft Academic Search

While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog\\/digital circuit components as well as the full system. When the integrated

Ryan Nong; Heidi K. Thornquist; Yao Chen; Ting Mei; Keith R. Santarelli; Raymond Stephen Tuminaro

2010-01-01

107

Integrating micromachined circuits to submillimeter systems  

Microsoft Academic Search

Micromachining techniques have been shown to have the necessary precision to fabricate accurate submillmeter circuits and structures; however, few submillimeter circuits created by these techniques have been integrated into existing systems. This article builds on previous lithographic micromachining techniques to fabricate and integrate submillimeter waveguide circuits with existing conventionally machined systems.

James R. Stanec; Charles H. Smith; N. Scott Barker

2010-01-01

108

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The drive circuit requirements of the insulated gate bipolar transistor (IGBT) are explained with the aid of an analytical model. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of anode voltage. Model results are compared with measured turn-on and turn-off waveforms for different drive, load, and feedback circuits, and for different

1991-01-01

109

Ultra-low power microwave CHFET integrated circuit development  

SciTech Connect

This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

Baca, A.G.; Hietala, V.M.; Greenway, D.; Sloan, L.R.; Shul, R.J.; Muyshondt, G.P.; Dubbert, D.F.

1998-04-01

110

Complementary Circuit with Self-Alignment Organic/Oxide Thin-Film Transistors  

NASA Astrophysics Data System (ADS)

Complementary logic circuits with self-alignment organic/oxide thin-film transistors (TFTs) were investigated. The layout and process steps of a self-alignment bottom-contact-type organic TFT and a top-contact type oxide TFT with a common layout pattern of the gate, source, and drain electrodes were proposed, and an integrated circuit was realized. The estimated field-effect mobilities, threshold voltages, and on-off ratios of the organic and oxide TFTs were 0.16 and 2.2 cm2 V-1 s-1, 2.2 and 2 V, and 3×103 and 5.2×106, respectively. From the complementary inverter characteristics, the voltage gain was 13 and the logic swing was 9.8 V at an applied voltage of 10 V. From the switching characteristics of the inverter, the rise and fall times were 18 and 46 µs, respectively. The operations of the NAND and NOR logic circuit configurations were confirmed, and the maximum operational frequency of NAND logic was estimated to be over 100 kHz.

Takeda, Fumio; Sato, Ryuichi; Naka, Shigeki; Okada, Hiroyuki

2012-02-01

111

Parallelism in integrated fluidic circuits  

NASA Astrophysics Data System (ADS)

Many research groups around the world are working on integrated microfluidics. The goal of these projects is to automate and integrate the handling of liquid samples and reagents for measurement and assay procedures in chemistry and biology. Ultimately, it is hoped that this will lead to a revolution in chemical and biological procedures similar to that caused in electronics by the invention of the integrated circuit. The optimal size scale of channels for liquid flow is determined by basic constraints to be somewhere between 10 and 100 micrometers . In larger channels, mixing by diffusion takes too long; in smaller channels, the number of molecules present is so low it makes detection difficult. At Caliper, we are making fluidic systems in glass chips with channels in this size range, based on electroosmotic flow, and fluorescence detection. One application of this technology is rapid assays for drug screening, such as enzyme assays and binding assays. A further challenge in this area is to perform multiple functions on a chip in parallel, without a large increase in the number of inputs and outputs. A first step in this direction is a fluidic serial-to-parallel converter. Fluidic circuits will be shown with the ability to distribute an incoming serial sample stream to multiple parallel channels.

Bousse, Luc J.; Kopf-Sill, Anne R.; Parce, J. W.

1998-04-01

112

High-performance organic transistors for printed circuits  

NASA Astrophysics Data System (ADS)

This presentation focuses on recent development of key technologies for printed LSIs which can provide future low-cost platforms for RFID tags, AD converters, data processors, and sensing circuitries. Such prospect bears increasing reality because of recent research innovations in the field of material chemistry, charge transport physics, and solution processes of printable organic semiconductors. Achieving band transport in state-of-the-art printable organic semiconductors, carrier mobility is elevated above 15 cm2/Vs, so that reasonable speed in moderately integrated logic circuits can be available. With excellent chemical and thermal stability for such compounds, we are developing simple integrated devices based on CMOS using p-type and n-type printed organic FETs. Particularly important are new processing technologies for continuous growth of inch-size organic single-crystalline semiconductor "wafers" from solution and for lithographical patterning of semiconductors and metal electrodes. Successful rectification and identification are demonstrated at 13.56 MHz with printed organic CMOS circuits for the first time.

Takeya, J.

2014-10-01

113

A circuit-compatible model of ballistic carbon nanotube field-effect transistors  

Microsoft Academic Search

Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V

Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy

2004-01-01

114

Sub-Circuit Based SPICE Model for High Voltage LDMOS Transistors  

NASA Astrophysics Data System (ADS)

High voltage lateral DMOS transistors are very difficult to model due to the complex structure. As a result of complexity and the range of variation in transistor structure no general LDMOS model exists. Standard SPICE models of MOSFETs, JFETs together with a resistor have been used in the sub-circuit model. Self-heating effects have been included in a specially design unit. The model shows good overall accuracy.

Ankarcrona, J.; Olsson, J.

115

Infrared FPA readout circuit based on current mirroring integration  

NASA Astrophysics Data System (ADS)

This paper reports an improved Current Mirroring Integration (CMI) unit cell and a new readout structure based on it. The new structure combines the benefits of the current mirroring direct injection and switch current integration structures, satisfying the requirements for the high resolution and high performance IR FPA readouts. The improved CMI readout circuit provides very high injection efficiency, almost-zero detector bias, and large dynamic range, while it can be implemented in a small pixel area. the circuit provides a maximum charge storage capacity of 5.25 X 107 electrons and a maximum transimpedence of 6 X 107 (Omega) for a 5V power supply and a 2pF integration capacitance, which is paled outside the unit cell. The unit cell employs only nine MOS transistors and occupies an area of 20micrometers X 25 micrometers in a 0.8 micrometers CMOS process.

Kulah, Haluk; Akin, Tayfun

1999-07-01

116

A miniature microcontroller curve tracing circuit for space flight testing transistors  

NASA Astrophysics Data System (ADS)

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Prokop, N.; Greer, L.; Krasowski, M.; Flatico, J.; Spina, D.

2015-02-01

117

Analyzing threshold pressure limitations in microfluidic transistors for self-regulated microfluidic circuits  

NASA Astrophysics Data System (ADS)

This paper reveals a critical limitation in the electro-hydraulic analogy between a microfluidic membrane-valve (?MV) and an electronic transistor. Unlike typical transistors that have similar on and off threshold voltages, in hydraulic ?MVs, the threshold pressures for opening and closing are significantly different and can change, even for the same ?MVs depending on overall circuit design and operation conditions. We explain, in particular, how the negative values of the closing threshold pressures significantly constrain operation of even simple hydraulic ?MV circuits such as autonomously switching two-valve microfluidic oscillators. These understandings have significant implications in designing self-regulated microfluidic devices.

Kim, Sung-Jin; Yokokawa, Ryuji; Takayama, Shuichi

2012-12-01

118

e bipolar junction transistor (BJT) is historically the first solid-state analog amplifier and digital switch, and formed the basis of integrated circuits (IC) in the 1970s. Starting in the early 1980s, the  

E-print Network

9-1 e bipolar junction transistor (BJT) is historically the first solid-state analog amplifier, the invention of silicon­germanium base heterojunction bipolar transistor (SiGe HBT) brought the bipolar are injected from the emitter to base, 9 Bipolar Junction Transistor 9.1 Ebers­Moll Model

Wilamowski, Bogdan Maciej

119

Integrated circuit generating 3- and 5-scroll attractors  

NASA Astrophysics Data System (ADS)

This paper introduces the experimental realization of the first integrated circuit of a multi-scroll continuous chaotic oscillator showing 3- and 5-scroll attractors. It is based on a variant of the Chua's system. The most relevant issue is the implementation of a saw-tooth-like nonlinear function, which is designed by using floating gate MOS (FGMOS) transistors. Therefore, the realization of a voltage-to-current nonlinear cell by a piecewise-linear approach allows us to have only two external control inputs instead of numerous external voltage references, as usually done in current circuit realizations. Experimental results of the proposed integrated multi-scroll oscillator along with its corner analysis are provided.

Trejo-Guerra, R.; Tlelo-Cuautle, E.; Jiménez-Fuentes, J. M.; Sánchez-López, C.; Muñoz-Pacheco, J. M.; Espinosa-Flores-Verdad, G.; Rocha-Pérez, J. M.

2012-11-01

120

Printed inorganic transistors  

E-print Network

Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

Ridley, Brent (Brent Alan), 1974-

2003-01-01

121

The resonant gate transistor  

Microsoft Academic Search

A device is described which permits high-Qfrequency selection to be incorporated into silicon integrated circuits. It is essentially an electrostatically excited tuning fork employing field-effect transistor \\

HARVEY C. NATHANSON; WILLIAM E. NEWELL; ROBERT A. WICKSTROM

1967-01-01

122

Ion-implanted complementary MOS transistors in low-voltage circuits  

Microsoft Academic Search

Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT\\/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.

RICHARD M. SWANSON; JAMES D. MEINDL

1972-01-01

123

Integrated circuits and logic operations based on single-layer MoS2.  

PubMed

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced. PMID:22073905

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

124

Direct extraction of the AlGaAs\\/GaAs heterojunction bipolar transistor small-signal equivalent circuit  

Microsoft Academic Search

The authors describe a novel, direct technique for determining the small-signal equivalent circuit of a heterojunction bipolar transistor (HBT). The parasitic elements are largely determined from measurements of test structures, reducing the number of elements determined from measurements of the transistor. The intrinsic circuit elements are evaluated from y-parameter data, which are DC-embedded from the known parasitics. The equivalent-circuit elements

Damian Costa; William U. Liu; James S. Harris

1991-01-01

125

Design Considerations for Digital Circuits Using Organic Thin Film Transistors on a Flexible Substrate  

E-print Network

-frequency identification (RFID) tags and large area flexible display. An ultra-low- cost all-printed RFID system is underDesign Considerations for Digital Circuits Using Organic Thin Film Transistors on a Flexible and systems on a flexible substrate. Our studies show that, complementary design logic (CMOS), which is most

Qiu, Qinru

126

Protective Socket For Integrated Circuits  

NASA Technical Reports Server (NTRS)

Socket for intergrated circuits (IC's) protects from excessive voltages and currents or from application of voltages and currents in wrong sequence during insertion or removal. Contains built-in switch that opens as IC removed, disconnecting leads from signals and power. Also protects other components on circuit board from transients produced by insertion and removal of IC. Makes unnecessary to turn off power to entire circuit board so other circuits on board continue to function.

Wilkinson, Chris; Henegar, Greg

1988-01-01

127

The Future of Integrated Circuits: A Survey of Nano-electronics  

E-print Network

. One possible heir to lithography based integrated circuits is nanotechnology and the nano to include things such as larger caches to speed up memory accesses and floating-point units to speed up-effect transistor (MOSFET) has been the building block for most computing devices for the last several decades

Hochberg, Michael

128

Sizing and Placement of Charge Recycling Transistors in MTCMOS Circuits  

E-print Network

in large row-based standard cell layouts while achieving nearly the full potential of this power was proposed to reduce the large amount of energy consumption that occurs during the mode transitions in power and placement of charge- recycling transistors is key to achieving the maximum power saving. In this paper, we

Pedram, Massoud

129

Transistors  

NSDL National Science Digital Library

How does a transistor work ? History of semi-conductors Visit the museum of how the transistor was developed. Transistor history The Transistor Museum How stuff works Visit this site and follow through a short course on how a semi-conductor works. How stuff works PBS site Visit the PBS site of transistors and semi-conductors. Watch shorth videos on the development of the transistor. Timeline pbs ...

Mr. Blackburn

2004-07-05

130

A wide range charge-balancing circuit using floating-gate transistors.  

PubMed

A CMOS circuit has been designed to produce charge-balanced biphasic current pulses for electrical stimulation of neurons. The circuit uses synaptic current source to generate discharging current pulses for stimulating current with amplitude ranging from 100pA to 110nA and period ranging from 0.2s to 1s. The amplitude and duration of the discharging current is controlled using programmable floating-gate transistors. The circuit has high stimulation efficiency and can be used in various neural microstimulators. PMID:18003305

Hu, Jingzhen; Gordon, Christal

2007-01-01

131

Field Effect Transistor /FET/ circuit for variable gin amplifiers  

NASA Technical Reports Server (NTRS)

Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

Spaid, G. H.

1969-01-01

132

Reliability of CMOS/SOS integrated circuits  

NASA Astrophysics Data System (ADS)

Reliability data for silicon-gate integrated circuits of various types are summarized. Included are failure rates for devices ranging from plastic-encapsulated commercial products to high-reliability hermetically-sealed integrated circuits for military and aerospace applications. Data are presented on devices fabricated by the original CMOS/SOS silicon-gate process and on devices prepared by advanced processes. These include lower wafer-process temperatures and improved wafer-processing techniques that permit thinner gate dielectrics and smaller feature sizes. Because they have fewer possible failure modes, CMOS/SOS integrated circuits have demonstrated a reliability at least equal to that achieved by bulk-MOS ICs.

Veloric, H.; Dugan, M. P.; Morris, W.; Denning, R.; Schnable, G.

1984-06-01

133

Inductive Fault Analysis of MOS Integrated Circuits  

Microsoft Academic Search

Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types

John Shen; W. Maly; F. J. Ferguson

1985-01-01

134

V.DMOS transistor modeling for simulation of power electronic circuits  

NASA Astrophysics Data System (ADS)

A nonlinear, short channel model of a power V.DMOS transistor, the elements of which depend only on physical and technological data, is presented. By an analysis of the active regions of the V.DMOS structure, in order to study switching modes, this model is simplified to a topology compatible with the SPICE circuit simulator. Parameter extraction methods and validation programs are described. A software library of the SPICE models is created by testing the transistors (N and P channels) covering the available current handling capability 2A to 50A and blocking range 50V to 1000V. A V.DMOS unified model is presented. It requires establishment of two parameters: drain source breakdown voltage, and silicon chip area. An established program linked in Hypercard with SPICE, gives an exact model for characterizing transistors as well as a model for new devices. This modeling takes into account the crystal temperature and several validation tests. Adaptation of the model for irradiation applications is pointed out by comparison between measured and computed characteristics. Use of this model to analyze bridge leg circuit properties and comparison between simulated results and measured data, confirms its application in power electronic circuits. Some problems associated with parasitic elements in these circuits are described.

Napieralska, Malgorzata

1991-08-01

135

Carbon nanotube synthesis for integrated circuit interconnects  

E-print Network

Based on their properties, carbon nanotubes (CNTs) have been identified as ideal replacements for copper interconnects in integrated circuits given their higher current density, inertness, and higher resistance to ...

Nessim, Gilbert Daniel

2009-01-01

136

Microwave Enginering Microwave Integrated Circuits  

E-print Network

deposition scheme as epitaxy, ion implantation, sputtering, evaporation, diffusion. · RF/MW MMIC circuits;Manufacturating steps of MMICs: Ref. Text book #12;InPGaAs Si or Sapphire SiProperty 0.680.460.461.5 Thermal

Iqbal, Sheikh Sharif

137

Reverse engineering of integrated circuits  

DOEpatents

Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

Chisholm, Gregory H. (Shorewood, IL); Eckmann, Steven T. (Colorado Springs, CO); Lain, Christopher M. (Pittsburgh, PA); Veroff, Robert L. (Albuquerque, NM)

2003-01-01

138

A Simple 2-Transistor Touch or Lick Detector Circuit  

ERIC Educational Resources Information Center

Contact or touch detectors in which a subject acts as a switch between two metal surfaces have proven more popular and arguably more useful for recording responses than capacitance switches, photocell detectors, and force detectors. Components for touch detectors circuits are inexpensive and, except for some special purpose designs, can be easily…

Slotnick, Burton

2009-01-01

139

Organic field-effect transistor circuits with electrode interconnections using reverse stamping  

NASA Astrophysics Data System (ADS)

We discuss a non-vacuum low-cost reverse stamping method for the realization of circuits based on top-gate organic field-effect transistors (OFETs) with a bi-layer gate dielectric. This method allows for patterning of high-k inorganic dielectric films produced by atomic layer deposition and consequently of the bilayer gate dielectric layers used in our top-gate OFETs. We demonstrate the fabrication and operation of logic inverters and ring oscillators following this approach.

Choi, Sangmoo; Fuentes-Hernandez, Canek; Yun, Minseong; Dindar, Amir; Khan, Talha M.; Wang, Cheng-Yin; Kippelen, Bernard

2014-10-01

140

A miniature microcontroller curve tracing circuit for space flight testing transistors.  

PubMed

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results. PMID:25725870

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

141

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits.  

PubMed

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Sporea, R A; Trainor, M J; Young, N D; Shannon, J M; Silva, S R P

2014-01-01

142

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits  

PubMed Central

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

143

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits  

NASA Astrophysics Data System (ADS)

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

144

Integrated circuit performance optimization with simulated annealing algorithm and SPICE-PAC circuit simulator  

Microsoft Academic Search

The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistor geometries . . .) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, etc.). This task is equivalent to a multidimensional and\\/or multi objective optimization problem: n-variables functions have to be minimized in an hyperrectangular domain: equality and\\/or

F. Durbin; J. Haussy; G. Berthiau; P. Siarry; W. M. Zuberek

1990-01-01

145

Broad spectrum period adding chaos in a transistor circuit  

Microsoft Academic Search

Period adding chaos, in which a driven system makes transitions such as period 2-chaos-period 3-chaos-period 4, is well known. In most cases, however, the frequency of the chaotic signal is close to the frequencies of the periodic signals. I have done expriments with a simple circuit in which the chaos has a very broad power spectrum, covering 6 orders of

Thomas Carroll

2006-01-01

146

Integrated Circuit Stellar Magnitude Simulator  

ERIC Educational Resources Information Center

Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

Blackburn, James A.

1978-01-01

147

Optimization of Integrated Transistors for Very High Frequency DC-DC Converters  

E-print Network

This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is ...

Sagneri, Anthony D.

148

Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign  

E-print Network

EE134 1 Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and Design " Reliability " Speed " Power #12;EE134 8 Total CostTotal Cost ! Cost per IC ! Variable cost Cost per IC = variable cost per IC + fixed cost volume Variable cost = cost of die + cost of die test + cost of packaging

149

Silicon/silicon germanium heterostructures: Materials, physics, quantum functional devices and their integration with heterostructure bipolar transistors  

NASA Astrophysics Data System (ADS)

With the advent of the first transistor in 1947, the integrated circuit (IC) industry has rapidly expanded with the tremendous advances in the development of IC technology. The driving force in the evolution of IC technology is the reduction of transistor sizes. Without a doubt, transistor miniaturization will face fundamental physical limitations imposed by further dimensional scaling of silicon transistors in the near future. According to the 2004 International Technology Roadmap for Semiconductors (ITRS), the width of a gate electrode for complementary metal-oxide-semiconductor (CMOS) is projected to be a mere 7 nm by the end of 2018. No further solutions have been found. Since the 2001 ITRS, tunneling devices have been evaluated as an emerging technology to augment silicon CMOS. Transistor circuitry incorporating tunneling devices realized using III-V semiconductors has exhibited superior performance over its transistor-only counterparts. However, due to fundamental differences in material properties, such technology is not readily compatible with the mainstream platforms (>95% market share of semiconductors) of CMOS and HBT technologies. Recently, we demonstrated the successful monolithic integration of Si-based resonant interband tunnel diodes (RITDs) with CMOS and SiGe HBT, which makes them more attractive than III-V based tunnel diodes for system level integration. This dissertation is concerned with the development of quantum functional tunneling devices, RITDs, and high-speed transistors, HBTs, using Si/SiGe heterostructures as well as material growth and electrical properties of Si/SiGe heterostructures. Emphasis is placed on the development of Si/SiGe-based RITDs, HBTs, and their monolithic integration for 3-terminal negative differential resistance (NDR) devices. The operating principles of Si-based RITDs and the integration of RITD with HBT are also discussed.

Chung, Sung-Yong

150

Single Event Upset in SOS Integrated Circuits  

Microsoft Academic Search

Single event upset (SEU) by argon and krypton ions has been observed in 1.25 micron CMOS-SOS integrated circuits. Mixed-mode PISCES-SPICE, circuit-device simulations were conducted and the calculated LET threshold compared favorably to experimental data. Analysis with the two-dimensional finite element PISCES code has revealed the upset charge collection mechanism involves charge multiplication due to bipolar action.

J. G. Rollins; J. Jr. Choma; W. A. Kolasinski

1987-01-01

151

Solution methods for very highly integrated circuits.  

SciTech Connect

While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator, both prominent world-class software tools.

Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

2010-12-01

152

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz  

NASA Technical Reports Server (NTRS)

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

153

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits  

NASA Technical Reports Server (NTRS)

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

1975-01-01

154

Package for integrated optic circuit and method  

DOEpatents

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

155

Package for integrated optic circuit and method  

DOEpatents

A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

1998-01-01

156

Control of threshold voltage in organic thin-film transistors by modifying gate electrode surface with MoOX aqueous solution and inverter circuit applications  

NASA Astrophysics Data System (ADS)

We controlled the threshold voltage of organic thin-film transistors (TFTs) by treating only the gate electrode surface with a MoOX aqueous solution and used them to build inverter circuits. The threshold voltage was changed by varying the concentration of the MoOX aqueous solution. A strong correlation between the work function of the gate electrode and the threshold voltage was observed. The threshold voltage of one of the two organic TFT devices in the inverter circuit was selectively changed by +2.3 V by reducing the concentration of the MoOx solution. We controlled the switching voltage of p-type organic inverter circuits and obtained excellent inverter characteristics. These results indicate that using a MoOx aqueous solution to control the threshold voltage is very useful for integrated circuits applications.

Shiwaku, Rei; Yoshimura, Yudai; Takeda, Yasunori; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-02-01

157

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1990-01-01

158

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1989-01-01

159

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

Hammond, R.B.; Bowman, D.R.

1989-04-11

160

Fabrication of nanoscale gaps in integrated circuits  

NASA Astrophysics Data System (ADS)

Nanosize objects such as metal clusters present an ideal system for the study of quantum phenomena and for the construction of practical quantum devices. Integrating these small objects in a macroscopic circuit is, however, a difficult task. So far, nanoparticles have been contacted and addressed by highly sophisticated techniques not suitable for large-scale integration in macroscopic circuits. We present an optical lithography method that allows for the fabrication of a network of electrodes separated by gaps of controlled nanometer size. The main idea is to control the gap size with subnanometer precision using a structure grown by molecular-beam epitaxy.

Krahne, Roman; Yacoby, Amir; Shtrikman, Hadas; Bar-Joseph, Israel; Dadosh, Tali; Sperling, Joseph

2002-07-01

161

Phase-controlled integrated photonic quantum circuits  

E-print Network

Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externally-controlled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms.

Brian J. Smith; Dmytro Kundys; Nicholas Thomas-Peter; P. G. R. Smith; I. A. Walmsley

2009-09-23

162

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics  

PubMed Central

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

163

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics  

NASA Astrophysics Data System (ADS)

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42?GHz and a maximum oscillation frequency fMAX up to 50?GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9?GHz, fMAX~1?GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-01

164

All-ion-implantation process for integrated circuits  

NASA Technical Reports Server (NTRS)

Simpler than diffusion fabrication, ion bombardment produces complementary-metal-oxide-semiconductor / silicon-on-sapphire (CMOS/SOS) circuits that are one-third faster. Ion implantation simplifies the integrated circuit fabrication procedure and produces circuits with uniform characteristics.

Woo, D. S.

1979-01-01

165

Top-down pass-transistor logic design  

Microsoft Academic Search

The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with

K. Yano; Y. Sasaki; K. Rikino; K. Seki

1996-01-01

166

Simultaneous characterization of mechanical and electrical performances of ultraflexible and stretchable organic integrated circuits  

Microsoft Academic Search

We report the simultaneous characterization of mechanical and electrical performances of ultraflexible and stretchable organic integrated circuits comprised of high-performance organic semiconductors, carbon nanotube-based elastic conductors, and self-assembled monolayers. By employing a high-precision mechanical stage that combines electrical functional terminals, the electrical performances of ultraflexible or stretchable organic transistors were measured after being bent to a 50 µm bending radius

Tsuyoshi Sekitania; Tomoyuki Yokotaa; Kazunori Kuribaraa; Takao Someyaa

2012-01-01

167

80 Gbit\\/s monolithically integrated clock and data recovery circuit with 1:2 DEMUX using InP-based DHBTs  

Microsoft Academic Search

An 80 Gbit\\/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is reported. The integrated circuit (IC) is manufactured using an InP double heterostructure bipolar transistor (DHBT) technology which features cut-off frequency values of more than 220 GHz for both fT and fmax. The CDR circuit is mainly composed of a half-rate linear phase detector including

R.-E. Makon; R. Driad; K. Schneider; M. Ludwig; R. Aidam; R. Quay; M. Schlechtweg; G. Weimann

2005-01-01

168

Microwave integrated circuit for Josephson voltage standards  

NASA Technical Reports Server (NTRS)

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

Holdeman, L. B.; Toots, J.; Chang, C. C. (inventors)

1980-01-01

169

Carbon nanotube circuit integration up to sub-20 nm channel lengths.  

PubMed

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 ?m device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes. PMID:24654597

Shulaker, Max Marcel; Van Rethy, Jelle; Wu, Tony F; Liyanage, Luckshitha Suriyasena; Wei, Hai; Li, Zuanyi; Pop, Eric; Gielen, Georges; Wong, H-S Philip; Mitra, Subhasish

2014-04-22

170

STRUCTURAL AND ELECTRICAL BEHAVIOR OF INTEGRATED DIAPHRAGM MICRO-PRESSURE-SENSOR BASED ON MOSFET TRANSISTOR  

Microsoft Academic Search

In this paper, the MOSFET transistor performance as sensible element and the structural and electrical behavior of integrated diaphragm micro-pressure-sensor has been described. ANSYS software has been used as a tool to design the mechanical properties and ANALOG INSYDES software has been used to predict the electrical behavior of transistors. The incorporation of MOSFET transistors on maxim stress regions has

B. S. Soto Cruz; F. López; Agustín L. Herrera

171

EMC test specification for integrated circuits  

Microsoft Academic Search

This paper presents a general EMC test specification for integrated circuits that is based on the internationally standardised test methods set out in IEC 61967 and IEC 62132 and specifies a generic procedure enabling a comparative characterisation of the EMC behaviour of different IC types. The specification contains general information about the test methods used, defines various IC function modules,

Frank Klotz

2007-01-01

172

Integrated circuit test sensors using semiconducting nanotubes  

Microsoft Academic Search

This paper describes unique research efforts relating, to the development of semiconducting nanotubes for use within integrated circuits as an aid in determining IC functionality and operational status. This is accomplished by assessing both the electrical and chemical properties of the device through the use of unique carbon nanotube-based sensors specially designed for this purpose. Theoretical issues associated with the

R. Glenn Wright; Larry V. Kirkland; M. Zgol; S. Keeton; D. Adebimbe

2001-01-01

173

Nanotechnology High-speed integrated nanowire circuits  

Microsoft Academic Search

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate

Robin S. Friedman; Michael C. McAlpine; David S. Ricketts; Donhee Ham; Charles M. Lieber

2005-01-01

174

Bioluminescent bioreporter integrated circuit detection methods  

DOEpatents

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

2005-06-14

175

The capacitance of integrated-circuit elements  

Microsoft Academic Search

The purpose of this note is to demonstrate that it is possible to modify a technique that was originally developed for calculations involving the scattering of electromagnetic waves from diverse-shaped objects and use it in calculations involving integrated-circuit elements. The technique is the “method of moments”, which was previously kept in the domain of researchers and graduate students in electromagnetic

K. E. Lonngren; Er-Wei Bai

1999-01-01

176

Electrical characterization of linear integrated circuits  

Microsoft Academic Search

This report covers the work performed by General Electric Ordnance Systems pertaining to the electrical characterization of linear integrated circuits. The period of report is July 1976 to June 1977. The effort was divided into three tasks: (1) New electrical characterization, (2) Resolution of problems with existing slash sheets, and (3) Rewrite of preliminary slash sheets. New characterization was performed

J. S. Kulpinski; J. Yaple; R. Paskowsky; T. Simonsen; H. Labb

1978-01-01

177

Large-scale photonic integrated circuits  

Microsoft Academic Search

100-Gb\\/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb\\/s on a DWDM wavelength grid. Optical system performance results across a

R. Nagarajan; C. H. Joyner; J. S. Bostak; T. Butrie; A. G. Dentai; V. G. Dominic; P. W. Evans; M. Kato; M. Kauffman; D. J. H. Lambert; S. K. Mathis; A. Mathur; R. H. Miles; M. L. Mitchell; M. J. Missey; S. Murthy; A. C. Nilsson; F. H. Peters; S. C. Pennypacker; J. L. Pleumeekers; R. A. Salvatore; R. K. Schlenker; R. B. Taylor; Huan-Shang Tsai; M. F. Van Leeuwen; J. Webjorn; M. Ziari; D. Perkins; J. Singh; S. G. Grubb; M. S. Reffle; D. G. Mehuys; F. A. Kish; D. F. Welch

2005-01-01

178

An efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry-save multiplier  

Microsoft Academic Search

This paper presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator circuit is designed using current mirror arrangement of pMOS and nMOS transistors. Complementary pass transistor adiabatic logic (CPAL) is chosen to implement an adiabatic carry save multiplier as it gives less energy dissipation per cycle than other logic families

P. Ranjith; Sushanta K. Mandal; Dipankar Nagchoudhuri

2009-01-01

179

Total dose and dose rate models for bipolar transistors in circuit simulation.  

SciTech Connect

The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

Campbell, Phillip Montgomery; Wix, Steven D.

2013-05-01

180

Ambipolar MoTe2 transistors and their applications in logic circuits.  

PubMed

We report ambipolar charge transport in ?-molybdenum ditelluride (MoTe2 ) flakes, whereby the temperature dependence of the electrical characteristics was systematically analyzed. The ambipolarity of the charge transport originated from the formation of Schottky barriers at the metal/MoTe2 contacts. The Schottky barrier heights as well as the current on/off ratio could be modified by modulating the electrostatic fields of the back-gate voltage (Vbg) and drain-source voltage (Vds). Using these ambipolar MoTe2 transistors we fabricated complementary inverters and amplifiers, demonstrating their feasibility for future digital and analog circuit applications. PMID:24692079

Lin, Yen-Fu; Xu, Yong; Wang, Sheng-Tsung; Li, Song-Lin; Yamamoto, Mahito; Aparecido-Ferreira, Alex; Li, Wenwu; Sun, Huabin; Nakaharai, Shu; Jian, Wen-Bin; Ueno, Keiji; Tsukagoshi, Kazuhito

2014-05-28

181

Development of 3D integrated circuits for HEP  

SciTech Connect

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

Yarema, R.; /Fermilab

2006-09-01

182

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

183

A test structure for the measurement and characterization of layout-induced transistor variation  

E-print Network

Transistor scaling has enabled us to design circuits with higher performance, lower cost, and higher density; billions of transistors can now be integrated onto a single die. However, this trend also magnifies the significance ...

Chang, Albert Hsu Ting

2009-01-01

184

Ion-implanted complementary MOS transistors in low-voltage circuits  

Microsoft Academic Search

Ion-implanted complementary MOS integrated circuits which can operate at supply voltages less than 0.4 V have been fabricated. Their behavior will be described by a new theory of MOST characteristics which is valid near threshold.

R. Swanson; J. Meindl

1972-01-01

185

Integrated-Circuit Active Digital Filter  

NASA Technical Reports Server (NTRS)

Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

Nathan, R.

1986-01-01

186

Transconductor and integrator circuits for integrated bipolar video frequency filters  

Microsoft Academic Search

A description is presented of novel transconductor and integrator circuits which can be used in integrated video frequency filters in bipolar technology. The transconductor consists of a parallel connection of a passive nominal transconductance and an active variable transconductance, resulting in good high-frequency performance up to 70 MHz and less than 1% linearity error for input signals up to 2V

W. J. A. de Heij; Evert Seevinck; K. Hoen

1989-01-01

187

\\\\Proc. IEEE 2004 Int. Conference on MicroelectronicTest Structures, Vol 17, March 2004. 127 A New Test Circuit for the Matching Characterization of npn Bipolar Transistors  

E-print Network

.3 A New Test Circuit for the Matching Characterization of npn Bipolar Transistors Jan Einfeld", Ulrich is presented for the mismatch characterization of npn bipolar transistors. The macro contains a CMOS circuit which serves for the selection of each bipolar device individually. For each bipolar device terminal

McNeill, John A.

188

Single-Event Upset and Snapback in Silicon-on-Insulator Devices and Integrated Circuits  

SciTech Connect

The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

DODD,PAUL E.; SHANEYFELT,MARTY R.; WALSH,DAVID S.; SCHWANK,JAMES R.; HASH,GERALD L.; LOEMKER,RHONDA ANN; DRAPER,BRUCE L.; WINOKUR,PETER S.

2000-08-15

189

Applying analog integrated circuits for HERO protection  

NASA Technical Reports Server (NTRS)

One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

Willis, Kenneth E.; Blachowski, Thomas J.

1994-01-01

190

Tunable resonant structures for photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Photonics is an evolving field allowing for optical devices to be made cost effectively using standard semiconductor fabrication techniques, which in turn enables integration with microelectronic chips. Chip scale photonics will play an increasing role in the future of communications as the demand for bandwidth and reduced power consumption per bit continues to grow. Tunable optical circuit components are one of the essential technologies in the development of photonic analogues for classical electronic devices, where tunable photonic resonant structures allow for altering of their electromagnetic spectrum and find applications in optical switching, filtering, buffering, lasers and biosensors. The scope of this work is focused on tunable resonant structures for photonic integrated circuits. Specifically, this work demonstrates active tuning of silicon photonic resonant structures using the properties of dye doped nematic liquid crystals, temperature stabilization of silicon photonics using the passive properties of liquid crystals, and the effects of low density plasma enhanced chemical vapor deposition (PECVD) claddings on ring resonator device performance.

Ptasinski, Joanna Nina

191

Niobium-based integrated circuit technologies  

Microsoft Academic Search

Metallurgical and electrical properties of Nb and NbN films for use as Josephson junction electrodes and wiring layers are investigated. The crystallographic and superconducting properties necessary for Nb-based integrated circuit processes are clarified. Tunnel barrier structures of NbN-Nb oxide-NbN (Pb alloy) and Nb-Al oxide-Nb Josephson junctions have been analyzed and correlated with junction characteristics and critical current unformity. It was

Yoshinobu Tarutani; Mikio Hirano; Ushio Kawabe

1989-01-01

192

Single event upset in SOS integrated circuits  

SciTech Connect

Single event upset (SEU) by argon and krypton ions has been observed in 1.25 micron CMOS-SOS integrated circuits. Mixed-mode PISCES-SPICE, circuity-device simulations were conducted and the calculated LET threshold compared favorably to experimental data. Analysis with the two-dimensional finite element PISCES code has revealed the upset charge collection mechanism involves charge multiplication due to bipolar action.

Rollins, J.G.; Choma, J. Jr.; Kolasinski, W.A.

1987-12-01

193

Integrated-Circuit Controller For Brushless dc Motor  

NASA Technical Reports Server (NTRS)

Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

Le, Dong Tuan

1994-01-01

194

Progress in radiation immune thermionic integrated circuits  

SciTech Connect

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

Lynn, D.K.; McCormick, J.B. (comps.)

1985-08-01

195

Microelectronic Devices and Circuits  

NSDL National Science Digital Library

The topics of this course include: modeling of microelectronic devices, basic microelectronic circuit analysis and design, physical electronics of semiconductor junction and MOS devices, relation of electrical behavior to internal physical processes, development of circuit models, and understanding the uses and limitations of various models. The course uses incremental and large-signal techniques to analyze and design bipolar and field effect transistor circuits, with examples chosen from digital circuits, single-ended and differential linear amplifiers, and other integrated circuits.

del Alamo, Jesus

196

Power system with an integrated lubrication circuit  

DOEpatents

A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

Hoff, Brian D. (East Peoria, IL); Akasam, Sivaprasad (Peoria, IL); Algrain, Marcelo C. (Peoria, IL); Johnson, Kris W. (Washington, IL); Lane, William H. (Chillicothe, IL)

2009-11-10

197

Vacuum die attach for integrated circuits  

DOEpatents

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

Schmitt, Edward H. (Livermore, CA); Tuckerman, David B. (Livermore, CA)

1991-01-01

198

Vacuum die attach for integrated circuits  

DOEpatents

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

199

Water-soluble thin film transistors and circuits based on amorphous indium-gallium-zinc oxide.  

PubMed

This paper presents device designs, circuit demonstrations, and dissolution kinetics for amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) comprised completely of water-soluble materials, including SiNx, SiOx, molybdenum, and poly(vinyl alcohol) (PVA). Collections of these types of physically transient a-IGZO TFTs and 5-stage ring oscillators (ROs), constructed with them, show field effect mobilities (?10 cm(2)/Vs), on/off ratios (?2 × 10(6)), subthreshold slopes (?220 mV/dec), Ohmic contact properties, and oscillation frequency of 5.67 kHz at supply voltages of 19 V, all comparable to otherwise similar devices constructed in conventional ways with standard, nontransient materials. Studies of dissolution kinetics for a-IGZO films in deionized water, bovine serum, and phosphate buffer saline solution provide data of relevance for the potential use of these materials and this technology in temporary biomedical implants. PMID:25805699

Jin, Sung Hun; Kang, Seung-Kyun; Cho, In-Tak; Han, Sang Youn; Chung, Ha Uk; Lee, Dong Joon; Shin, Jongmin; Baek, Geun Woo; Kim, Tae-Il; Lee, Jong-Ho; Rogers, John A

2015-04-22

200

Relationships among classes of self-oscillating transistor parallel inverters. [dc to square wave converter circuits for power conditioning  

NASA Technical Reports Server (NTRS)

A procedure is developed for classifying dc-to-square-wave two-transistor parallel inverters used in power conditioning applications. The inverters are reduced to equivalent RLC networks and are then grouped with other inverters with the same basic equivalent circuit. Distinction between inverter classes is based on the topology characteristics of the equivalent circuits. Information about one class can then be extended to another class using the basic oscillation theory and the concept of duality. Oscillograms from test circuits confirm the validity of the procedure adopted.

Wilson, T. G.; Lee, F. C. Y.; Burns, W. W., III; Owen, H. A., Jr.

1974-01-01

201

An integrated circuit floating point accumulator  

NASA Astrophysics Data System (ADS)

Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

Goldsmith, T. C.

1977-06-01

202

3D packaging for integrated circuit systems  

SciTech Connect

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

Chu, D.; Palmer, D.W. [eds.

1996-11-01

203

Nobel Laureate e-Museum: Integrated Circuits  

NSDL National Science Digital Library

Nobel Laureate e-Museum's Educational section provides historical and scientific background information on inventions by those who have been honored with the Nobel Laureates in physics, chemistry, medicine, literature and peace over the years. For example, from this website, visitors can read about Nobel Laureate Jack Kilby and his part in the invention of integrated circuits, which are found in a variety of modern electrical device, including computers, cars, television sets, CD players, and cellular phones. A game called Techville is also free to download. A "walk through" will help you out if you get stuck on the game.

204

An integrated circuit floating point accumulator  

NASA Technical Reports Server (NTRS)

Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

Goldsmith, T. C.

1977-01-01

205

Sequential circuit design for radiation hardened multiple voltage integrated circuits  

DOEpatents

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

2009-11-24

206

SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs  

SciTech Connect

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Huque, Mohammad A [ORNL; Tolbert, Leon M [ORNL; Blalock, Benjamin [University of Tennessee, Knoxville (UTK); Islam, Syed K [University of Tennessee, Knoxville (UTK)

2010-01-01

207

Technologies for highly parallel optoelectronic integrated circuits  

SciTech Connect

While summarily reviewing the range of optoelectronic integrated circuits (OEICs), this paper emphasizes technology for highly parallel optical interconnections. Market volume and integration suitability considerations highlight board-to-board interconnects within systems as an initial insertion point for large OEIC production. The large channel count of these intrasystem interconnects necessitates two-dimensional laser transmitter and photoreceiver arrays. Surface normal optoelectronic components are promoted as a basis for OEICs in this application. An example system is discussed that uses vertical cavity surface emitting lasers for optical buses between layers of stacked multichip modules. Another potentially important application for highly parallel OEICs is optical routing or packet switching, and examples of such systems based on smart pixels are presented.

Lear, K.L. [Sandia National Labs., Albuquerque, NM (United States). Photonics Research Dept.

1994-10-01

208

Packaging challenges for integrated silicon photonic circuits  

NASA Astrophysics Data System (ADS)

Cost-effective packaging of silicon photonic devices presents a significant bottleneck to commercialization of the technology. One way of addressing this packaging challenge is to use techniques that have been developed by the electronics industry and which also benefit from the use of advanced electronics assembly equipment. Even packaging processes such as fiber coupling can benefit from this approach, along with the hybrid integration of devices such as electronic components (e.g. modulator driver integrated circuits). In this paper, we will present developments made by our group towards achieving scalable fiber and electronic packaging processes that rely on electronic assembly techniques such as flip-chip assembly. We will also provide an overview of packaged prototypes being developed within our group for telecom and sensing applications and how these packaging technologies are now being made available to users through the ePIXfab foundry service.

Pavarelli, Nicola; Lee, Jun Su; O'Brien, Peter A.

2014-05-01

209

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets  

NASA Technical Reports Server (NTRS)

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Zoutendyk, John A. (inventor)

1991-01-01

210

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits  

NASA Astrophysics Data System (ADS)

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Es-Sakhi, Azzedin D.

211

Fully integrated nonlinear modeling and characterization system of microwave transistors with on-wafer pulsed measurements  

Microsoft Academic Search

A novel approach for nonlinear characterization and modeling of microwave transistors has been developed. The whole process is organized as a set of methods contained in the transistor database. This implies that characterization and modeling are performed in an integrated manner. I(V) and S-parameters are measured on wafer under pulsed conditions, suitable for MESFETs, HEMTs or HBTs as illustrated by

J. P. Teyssier; J. P. Viaud; J. J. Raoux; R. Quere

1995-01-01

212

Integrated photo-responsive metal oxide semiconductor circuit  

NASA Technical Reports Server (NTRS)

An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

Jhabvala, Murzban D. (inventor); Dargo, David R. (inventor); Lyons, John C. (inventor)

1987-01-01

213

Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration  

E-print Network

Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring ...

Sredojevi?, Ranko Radovin.

2008-01-01

214

Circuit design for embedded memory in low-power integrated circuits  

E-print Network

This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the ...

Qazi, Masood

2012-01-01

215

Integrated optical circuits for numerical computation  

NASA Technical Reports Server (NTRS)

The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

Verber, C. M.; Kenan, R. P.

1983-01-01

216

An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits  

Microsoft Academic Search

In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear $I_{D}$ versus $V_{{\\\\rm DS}}$ relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in

Elio Consoli; Gianluca Giustolisi; Gaetano Palumbo

2012-01-01

217

Experimental determination of single-event upset (SEU) as a function of collected charge in bipolar integrated circuits  

Microsoft Academic Search

Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks

J. A. Zoutendyk; C. J. Malone; L. S. Smith

1984-01-01

218

A general method in synthesis of pass-transistor circuits D. Markovica,*, B. Nikolicb  

E-print Network

gates in CPL, DPL and DVL. The method is general and can be extended to synthesize any pass logic families (Complementary pass-transistor logic (CPL), double pass-transistor logic (DPL), and dual [7], and those that use both NMOS and PMOS pass-transistors, DPL [5] and DVL [6]. 2.1. Complementary

Oklobdzija, Vojin G.

219

Material selection and nanofabrication techniques for electronic photonic integrated circuits  

E-print Network

Electronic-photonic integrated circuits have the potential to circumvent many of the performance bottlenecks of electronics. To achieve the full benefits of integrating photonics with electronics it is generally believed ...

Holzwarth, Charles W., III (Charles Willett)

2009-01-01

220

A TDC integrated circuit for drift chamber readout  

Microsoft Academic Search

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start\\/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 ?m CMOS technology, with 1 ns LSB realized using a

M. Passaseo; E. Petrolo; S. Veneziano

1995-01-01

221

Laser formed connections for integrated circuit chip personalization  

Microsoft Academic Search

The use of lasers for thermal processing of materials has been studied extensively [1,2]. Their use in integrated circuit processing has been limited mainly to material removal (resistor trimming, metal delineation, etc.) [3]. This paper describes a recently discovered process in which nanosecond dye laser pulses are used to form reliable low resistance ohmic contacts between conductors on integrated circuit

L. Kuhn; S. E. Schuster; P. S. Zory; P. W. Cook; R. J. von Gutfeld

1974-01-01

222

Plug-in integrated/hybrid circuit  

NASA Technical Reports Server (NTRS)

Hybrid circuitry can be installed into standard round bayonet connectors, to eliminate wiring from connector to circuit. Circuits can be connected directly into either section of connector pair, eliminating need for hard wiring to that section.

Stringer, E. J.

1974-01-01

223

Pentacene integrated thin-film transistors and circuits  

E-print Network

Organic semiconductors offer the potential of large-area, mechanically flexible electronics due to their low processing temperatures. We have developed a near-room-temperature (< 95°C) process flow to fabricate pentacene ...

Nausieda, Ivan Alexander

2009-01-01

224

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit  

PubMed Central

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10?MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

Nakazato, Kazuo

2014-01-01

225

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.  

PubMed

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10?MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

Nakazato, Kazuo

2014-03-28

226

Fluoropolymer coatings for improved carbon nanotube transistor device and circuit performance  

NASA Astrophysics Data System (ADS)

We report on the marked improvements in key device characteristics of single walled carbon nanotube (SWCNT) field-effect transistors (FETs) by coating the active semiconductor with a fluoropolymer layer such as poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE). The observed improvements include: (i) A reduction in off-current by about an order of magnitude, (ii) a significant reduction in the variation of threshold voltage, and (iii) a reduction in bias stress-related instability and hysteresis present in device characteristics. These favorable changes in device characteristics also enhance circuit performance and the oscillation amplitude, oscillation frequency, and increase the yield of printed complementary 5-stage ring oscillators. The origins of these improvements are explored by exposing SWCNT FETs to a number of vapor phase polar molecules which produce similar effects on the FET characteristics as the PVDF-TrFE. Coating of the active SWCNT semiconductor layer with a fluoropolymer will be advantageous for the adoption of SWCNT FETs in a variety of printed electronics applications.

Jang, Seonpil; Kim, Bongjun; Geier, Michael L.; Prabhumirashi, Pradyumna L.; Hersam, Mark C.; Dodabalapur, Ananth

2014-09-01

227

Heterojunction bipolar transistor technology for data acquisition and communication  

NASA Technical Reports Server (NTRS)

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

228

Programmable Logic Circuits for Functional Integrated Smart Plastic Systems  

E-print Network

In this paper, we present a functional integrated plastic system. We have fabricated arrays of organic thin-film transistors (OTFTs) and printed electronic components driving an electrophoretic ink display up to 70mm by 70mm on a single flexible...

Sou, Antony; Jung, Sungjune; Gili, Enrico; Pecuni, Vincenzo; Joimel, Jerome; Fichet, Guillaume; Sirringhaus, Henning

2014-09-12

229

77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Investigation No. 337-TA-848] Certain Radio Frequency Integrated Circuits and Devices Containing...States after importation of certain radio frequency integrated circuits and devices containing...States after importation of certain radio frequency integrated circuits and devices...

2012-06-13

230

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...  

Federal Register 2010, 2011, 2012, 2013, 2014

...TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and Products...received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and...

2012-03-29

231

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and products...States after importation of certain semiconductor integrated circuit devices and...

2012-05-01

232

Reduced 30% scanning time 3D multiplexer integrated circuit applied to large array format 20KHZ frequency inkjet print heads  

E-print Network

Enhancement of the number and array density of nozzles within an inkjet head chip is one of the keys to raise the printing speed and printing resolutions. However, traditional 2D architecture of driving circuits can not meet the requirement for high scanning speed and low data accessing points when nozzle numbers greater than 1000. This paper proposes a novel architecture of high-selection-speed three-dimensional data registration for inkjet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array inkjet printheads with nozzles numbering more than 1000. This IC (Integrated Circuit) architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection (S), address (A), and power supply (P), are employed toge...

Liou, J -C

2008-01-01

233

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits  

PubMed Central

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal?oxide?semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

234

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits.  

PubMed

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at V(DD) = 80 V (70% of 1/2V(DD)) and a gain of 85. Additionally, robust SWNT complementary metal-oxide-semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C-K; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-04-01

235

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology  

Microsoft Academic Search

This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective

Ahmet Bindal; Adithya Naresh; Pearl Yuan; Kim K. Nguyen; Sotoudeh Hamedi-Hagh

2007-01-01

236

Nanophotonic integrated circuits from nanoresonators grown on silicon  

NASA Astrophysics Data System (ADS)

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore’s law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D.; Li, Kun; Chang-Hasnain, Connie

2014-07-01

237

Integrated Circuit Implementation for a GaN HFETs Driver Circuit  

E-print Network

Integrated Circuit Implementation for a GaN HFETs Driver Circuit B. Wang (1) , M. Riva (2) , J for GaN HFETs. While the main elements of the topology were introduced in a previous work, here demonstrate the possibility to exploit the advantages of GaN devices by means of a smart and convenient

Bakos, Jason D.

238

Cmos-Compatible High Voltage Integrated Circuits.  

NASA Astrophysics Data System (ADS)

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 ?m CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS -bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT. The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.

Parpia, Zahir

239

A new aSi:H thin-film transistor pixel circuit for active-matrix organic light-emitting diodes  

Microsoft Academic Search

We propose a new pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), composed of three switching and one driving TFT, for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage source method. The circuit simulation results based on the measured threshold voltage shift of a-Si:H TFTs by gate-bias stress indicate that this circuit compensates for the threshold voltage shifts

Joon-Chul Goh; Jin Jang; Kyu-Sik Cho; Choong-Ki Kim

2003-01-01

240

Complementary junction heterostructure field-effect transistor  

DOEpatents

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

241

Complementary junction heterostructure field-effect transistor  

DOEpatents

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Baca, Albert G. (Albuquerque, NM); Drummond, Timothy J. (Albuquerque, NM); Robertson, Perry J. (Albuquerque, NM); Zipperian, Thomas E. (Albuquerque, NM)

1995-01-01

242

Cmos-Compatible High Voltage Integrated Circuits  

Microsoft Academic Search

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 mum CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50

Zahir Parpia

1988-01-01

243

35 GHz integrated circuit rectifying antenna with 33 percent efficiency  

NASA Technical Reports Server (NTRS)

A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

Yoo, T.-W.; Chang, K.

1991-01-01

244

Statistical timing for parametric yield prediction of digital integrated circuits  

Microsoft Academic Search

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of

Jochen A. G. Jess; K. Kalafala; Srinath R. Naidu; Ralph H. J. M. Otten; Chandramouli Visweswariah

2003-01-01

245

Improved method of dicing integrated circuit wafers into chips  

NASA Technical Reports Server (NTRS)

Method employing a pressure chamber is used for dicing semiconductor single-crystal wafers, containing integrated circuits, into small chips along pre-scribed lines. Uniform bending of the scribed wafer over the convex surface of a perforated hemisphere, breaks it cleanly into individual chips without damaging the circuits.

Litant, I.; Scapicchio, A. J.

1969-01-01

246

Nanoscale Transistors: Advanced VLSI Devices (Introductory Lecture)  

NSDL National Science Digital Library

Contributed by Mark Lundstrom of Purdue University, this introductory lecture to nanoscale transistors is available both as a Flash video with audio and as presentation slides in PDF form (the links to these are on the right hand side of the page). The lecture introduces the course, which "examines the device physics of advanced transistors and the process, device, circuit, and systems considerations that enter into the development of new integrated circuit technologies." This is a helpful resource for nanotechnology instructors looking to introduce the concept of nanoscale transistors into their classrooms. For more from this course (lectures, assignments, etc.) click the Course Information Website link.

Lundstrom, Mark

247

technologie transistor.  

E-print Network

�léments de technologie Les circuits intégrées c-MOS. L'élément de base est le transistor. Deux types de transistors complémentaires n-MOS et p-MOS. Avantages des c-MOS : #21; très grande intégration des impuretés. - plus récement : bombardement ionique. 2 #12; Transistor n-MOS (Metal

Hivert, Florent

248

Advanced modeling of planarization processes for integrated circuit fabrication  

E-print Network

Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing ...

Fan, Wei, Ph. D. Massachusetts Institute of Technology

2012-01-01

249

Design automation and analysis of three-dimensional integrated circuits  

E-print Network

This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical ...

Das, Shamik, 1977-

2004-01-01

250

LEC GaAs for integrated circuit applications  

NASA Technical Reports Server (NTRS)

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

251

Algorithms for design for quality of integrated circuits  

E-print Network

The main thesis objective is to develop new, efficient algorithms for designing high quality Integrated Circuits (ICs). The following three major areas of Design for Quality are studied: 1. Quality Measures and their applications. 2.Optimum...

Achab, Abdenour

1995-01-01

252

Integrated prepulse circuits for efficient excitation of gas lasers  

NASA Technical Reports Server (NTRS)

Efficient impedance-matched gas laser excitation circuits integrally employ prepulse power generators. Magnetic switches are employed to both generate the prepulse and switch the prepulse onto the laser electrodes.

Rothe, Dietmar E. (Inventor)

1990-01-01

253

Modeling of three dimensional defects in integrated circuits  

E-print Network

Although the majority of defects found in manufacturing lines of Integrated Circuits [ IC's] have predominantly 2- Dimensional [2D] effects, there are many situations in which 2D defect models do not suffice) e.g., tall layer bulks disrupting...

Dani, Sameer Manohar

1993-01-01

254

Polariton Condensate Transistor Switch  

E-print Network

A polariton condensate transistor switch is realized through optical excitation of a microcavity ridge with two beams. The ballistically ejected polaritons from a condensate formed at the source are gated using the 20 times weaker second beam to switch on and off the flux of polaritons. In the absence of the gate beam the small built-in detuning creates potential landscape in which ejected polaritons are channelled toward the end of the ridge where they condense. The low loss photon-like propagation combined with strong nonlinearities associated with their excitonic component makes polariton based transistors particularly attractive for the implementation of all-optical integrated circuits.

Gao, T; Liew, T C H; Tsintzos, S I; Stavrinidis, G; Deligeorgis, G; Hatzopoulos, Z; Savvidis, P G

2012-01-01

255

Laser rapid prototyping of photonic integrated circuits  

Microsoft Academic Search

In this paper, we will describe our work at Columbia in developing a laser prototyping system, in conjunction with computer simulation, to design, fabricate, and test novel waveguide circuits. The system is also useful for manufacturing small-run circuit designs. The fundamental technique uses a laser-induced photoelectrochemical process for etching GaAs and other III-V compounds. The technique is maskless and discretionary.

Louay Eldada; Miguel Levy; Robert Scarmozzino; Richard M. Osgood

1994-01-01

256

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model  

NASA Astrophysics Data System (ADS)

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

257

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design and Application Considerations for  

E-print Network

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design, and Seshadri Subbanna, Member, IEEE Invited Paper Abstract--SiGe HBT transistors achieving over 200 GHz and MAX--BiCMOS integrated circuits, bipolar transistors, heterojunctions, semiconductor devices. I. INTRODUCTION BIPOLAR

Rieh, Jae-Sung

258

Method for double-sided processing of thin film transistors  

DOEpatents

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Yuan, Hao-Chih (Madison, WI); Wang, Guogong (Madison, WI); Eriksson, Mark A. (Madison, WI); Evans, Paul G. (Madison, WI); Lagally, Max G. (Madison, WI); Ma, Zhenqiang (Middleton, WI)

2008-04-08

259

Metallization technology for tenth-micron range integrated circuits  

SciTech Connect

A critical step in the fabrication of integrated circuits is the deposition of metal layers which interconnect the various circuit elements that have been formed in earlier process steps. In particular, columns of copper several times higher than the characteristic dimension of the circuit elements was needed. Features with a diameter of a few tenths of a micron and a height of about one micron need to be filled at rates in the half to one micron per minute range. With the successful development of a copper deposition technology meeting these requirements, integrated circuits with simpler designs and higher performance could be economically manufactured. Several technologies for depositing copper were under development. No single approach had an optimum combination of performance (feature characteristics), cost (deposition rates), and manufacturability (integration with other processes and tool reliability). Chemical vapor deposition, plating, sputtering and ionized-physical vapor deposition (I-PVD) were all candidate technologies. Within this project, the focus was on I-PVD.

Berry, L.A.; Harper, M.E.

1996-11-27

260

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.  

PubMed

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries. PMID:24567478

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

261

Timing Verification of Adaptive Integrated Circuits  

E-print Network

analysis to each adap- 1 tivity mode. This approach is practical only if the adaptivity is coarse-grained and the number of adaptivity blocks are small. In this work, we attempt to find a general and practical approach to timing verification for adaptive... unit i.e. in a coarse grained manner or it can be applied to the different parts of the circuit differently i.e. in a fine grained manner as shown in Figure 1.2. In fine grained adaptivity the whole circuit is divided into certain number of blocks...

Kumar, Rohit

2014-08-01

262

Integrated-circuit balanced parametric amplifier  

NASA Technical Reports Server (NTRS)

Amplifier, fabricated on single dielectric substrate, has pair of Schottky barrier varactor diodes mounted on single semiconductor chip. Circuit includes microstrip transmission line and slot line section to conduct signals. Main features of amplifier are reduced noise output and low production cost.

Dickens, L. E.

1975-01-01

263

Heterojunction field effect transistors (HJFETs) for a readout circuit of a cryogenically cooled far-infrared detector  

NASA Astrophysics Data System (ADS)

Deep cryogenic field effect transistors (FETs) which are able to operate under liquid helium temperatures have significant advantages over conventional cryogenic Silicon- Junction-FETs or Si-metal-oxide-semiconductor-FETs as readout circuits of a far-IR focal plane array detector: simple operation, simple system structures, and large transconductance. We report the testing of an InGaAs-channel heterojunction field effect transistor (HJFET) operating at 4.2 K designed for a readout circuit of a cryogenically cooled far-IR detector. In this report, we present current- voltage characteristics, transconductance, low-frequency noise (LFN) characteristics, and the influence of the gate leakage current on the LFN characteristics of the HJFET. Input-referred noise voltage as low as a few hundred nanovolts at 1 Hz was measured for the HJFET with a 100 X 100 micrometers (superscript 2) gate area. We discuss further possibilities for the fabrication of HJFETs with an extremely small input current of less than 10(superscript -15) A.

Hosako, Iwao; Okumura, Kenichi; Yamashita-Yui, Yukari; Akiba, Makoto; Hiromoto, Norihisa

1998-08-01

264

Simulation of proton-induced energy deposition in integrated circuits  

NASA Technical Reports Server (NTRS)

A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

Fernald, Kenneth W.; Kerns, Sherra E.

1988-01-01

265

Application of Neural Networks for Integrated Circuit Modeling  

Microsoft Academic Search

\\u000a Application of feedforward neural networks for integrated circuit (IC) modeling is presented. In order to accurately describe\\u000a IC behaviors, a set of improved equations for dynamic feedforward neural networks has been utilized for IC modeling. The rationality\\u000a of the improved equations is elucidated by analyzing the relation between the circuits and the equation parameters. Through\\u000a some special choices of the

Xi Chen; Gao-Feng Wang; Wei Zhou; Qing-Lin Zhang; Jiang-feng Xu

2006-01-01

266

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

1992-01-01

267

An investigation of delta-I noise on integrated circuits  

Microsoft Academic Search

Delta-I noise is the voltage induced between the power conductors (e.g. the ground and the Vcc planes) when a circuit connected between them switches from one state to another. The authors show that the physics of the noise is more complex, and that it is related to wave propagation effects. Delta-I noise should be present not only in integrated circuits

Antonije R. DjordjeviC; Tapan Kumar Sarkar

1993-01-01

268

Development of thermionic integrated circuits for applications in hostile environments  

NASA Astrophysics Data System (ADS)

A class of devices known as thermionic integrated circuits (TICs) that are capable of extended operation in ambient temperatures up to 500 C and in high radiation environments are described. The evolution of the TIC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500 C environments for extended periods of time.

McCormick, J. B.; Lynn, D. K.; Wilde, D.; Cowan, R.; Hamilton, D. J.; Kerwin, W.; Dooley, R.

1984-04-01

269

Integrated Circuit For Simulation Of Neural Network  

NASA Technical Reports Server (NTRS)

Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

1988-01-01

270

Variance reduction and outlier identification for IDDQ testing of integrated chips using principal component analysis  

E-print Network

Integrated circuits manufactured in current technology consist of millions of transistors with dimensions shrinking into the nanometer range. These small transistors have quiescent (leakage) currents that are increasingly sensitive to process...

Balasubramanian, Vijay

2007-04-25

271

Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors, Non-volatile Memory and Circuits for Transparent Electronics  

NASA Astrophysics Data System (ADS)

The ability to make electronic devices, that are transparent to visible and near infrared wavelength, is a relatively new field of research in the development of the next generation of optoelectronic devices. A new class of inorganic thin-film transistor (TFT) channel material based on amorphous oxide semiconductors, that show high carrier mobility and high visual transparency, is being researched actively. The purpose of this dissertation is to develop amorphous oxide semiconductors by pulsed laser deposition, show their suitability for TFT applications and demonstrate other classes of devices such as non-volatile memory elements and integrated circuits such as ring oscillators and active matrix pixel elements. Indium gallium zinc oxide (IGZO) is discussed extensively in this dissertation. The influence of several deposition parameters is explored and oxygen partial pressure during deposition is found to have a profound effect on the electrical and optical characteristics of the IGZO films. By optimizing the deposition conditions, IGZO TFTs exhibit excellent electrical properties, even without any intentional annealing. This attribute along with the amorphous nature of the material also makes IGZO TFTs compatible with flexible substrates opening up various applications. IGZO TFTs with saturation field effect mobility of 12--16 cm 2 V-1 s-1 and subthreshold voltage swing of <200 mV decade-1 have been fabricated. By varying the oxygen partial pressure during deposition the conductivity of the channel was controlled to give a low off-state current ˜10 pA and a drain current on/off ratio of >1 x 108. Additionally, the effects of the oxygen partial pressure and the thickness of the semiconductor layer, the choice of the gate dielectric material and the device channel length on the electrical characteristics of the TFTs are explored. To evaluate IGZO TFT electrical stability, constant voltage bias stress measurements were carried out. The observed logarithmic dependence of the threshold voltage shift to the stress duration was modeled using a charge trapping/tunneling mechanism at the semiconductor/dielectric interface. By incorporating platinum nanoparticles in the dielectric layer of the TFT, non-volatile memory characteristics were achieved. The devices exhibited good memory behavior and up to 10% charge retention extrapolated over 10 years. The potential application for IGZO TFTs is examined by fabricating and characterizing 5- and 7-stage ring oscillators. The 5-stage ring oscillators operate at more than 2 MHz and have a sub 50 ns propagation delay at a supply voltage of 25 V. To the best of our knowledge these are the fastest all-transparent ring oscillators reported to date. As a practical demonstration, we integrated IGZO TFTs with a novel thin film electroluminescent phosphor to form an active matrix pixel element. The output intensity of the phosphor was successfully modulated by the TFT. These results demonstrate that IGZO TFTs are viable candidates for transparent circuits and display applications.

Suresh, Arun

272

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking  

Microsoft Academic Search

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the

Jie Deng; H.-S. Philip Wong

2007-01-01

273

Fabrication of integrated resistors in printed circuit boards  

Microsoft Academic Search

In order to utilize integrated passive technology in printed circuit boards (PCBs), manufacturing processing for integrated\\u000a resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment\\u000a were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 ?.\\u000a Six panel per

Shou-guo Wang; Ching-yuen Chan

2011-01-01

274

75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Certain Large Scale Integrated Circuit Semiconductor...certain large scale integrated circuit semiconductor...Semiconductor Xiqing Integrated Semiconductor Manufacturing...Semiconductor Innovation Center (``Freescale Innovation...Qiangxin (Tianjin) IC Design Co., Ltd. of...

2010-08-23

275

a-InGaZnO thin-film transistors for AMOLEDs: Electrical stability and pixel-circuit Charlene Chen (SID Student Member)  

E-print Network

amorphous-silicon (a-Si:H) thin-film transistors (TFTs) currently dominate the liquid-crystal-display (LCD on experimental data. Several active-matrix organic light-emit- ting-display (AMOLED) pixel circuits were light-emitting display (AMOLED). DOI # 10.1889/JSID17.6.525 1 Introduction Active-matrix organic light

Kanicki, Jerzy

276

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers  

NASA Astrophysics Data System (ADS)

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized

Hsu, Yu-Jen

277

3D circuit integration for Vertex and other detectors  

SciTech Connect

High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

Yarema, Ray; /Fermilab

2007-09-01

278

Electron mobility increase in submicronic transistors integrated on ultrathin silicon membranes subjected to high mechanical stress  

NASA Astrophysics Data System (ADS)

In this contribution we investigate an original method to apply high values of biaxial stress: The integration of submicronic fully depleted silicon on insulator transistors on ultrathin silicon membranes. The membranes are micromachined in the device substrate, the buried oxide facilitating the control of the membrane thickness below 1 ?m. High values of biaxial stress can thus be applied on the transistor channel without the drawbacks of conventional methods. The experimental results obtained using 750 nm thick membranes are presented. The piezoresistive longitudinal coefficient obtained for strained silicon on insulator wafer (240×10-12 Pa-1) is in good agreement with the results obtained by the four-probe bending method.

Bercu, Bogdan; Montès, Laurent; Rochette, Florent; Mouis, Mireille; Xin, Xu; Morfouli, Panagiota

2010-03-01

279

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor  

SciTech Connect

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M., E-mail: muhammadmustafa.hussain@kaust.edu.sa [Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical Mathematical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia)

2013-11-25

280

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks  

Microsoft Academic Search

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The

Zhanping Chen; Mark Johnson; Liqiong Wei; Kaushik Roy

1998-01-01

281

Abstract--The parametric shifts or circuit failures caused by transistor aging have become more severe with shrinking device  

E-print Network

), and Time Dependent Dielectric Breakdown (TDDB) have become more severe with shrinking transistor sizes Odometers that provide measurement data required to develop transistor degradation models. One such scheme

Kim, Chris H.

282

Thermally-induced voltage alteration for integrated circuit analysis  

DOEpatents

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Cole, Jr., Edward I. (Albuquerque, NM)

2000-01-01

283

Single Event Transients in Linear Integrated Circuits  

NASA Technical Reports Server (NTRS)

On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed to transients. In some cases, such events produced resets by falsely triggering circuits designed to protect against over- voltage or over-current. On at least three occasions, transients caused satellites to switch into "safe mode" in which most of the systems on board the satellites were powered down for an extended period. By the time the satellites were reconfigured and returned to full operational state, much scientific data had been lost. Fortunately, no permanent damage occurred in any of the systems and they were all successfully re-activated.

Buchner, Stephen; McMorrow, Dale

2005-01-01

284

MICROX-an all-silicon technology for monolithic microwave integrated circuits  

Microsoft Academic Search

An improved silicon-on-insulator (SOI) approach offers devices and circuits operating to 10 GHz by providing formerly unattainable capabilities in bulk silicon: reduced junction-to-substrate capacitances in FETs and bipolar transistors, inherent electrical isolation between devices, and low-loss microstrip lines. The concept, called MICROX (patent pending), is based on the SIMOX process, but uses very-high-resistivity (typically>10000 ?-cm) silicon substrates, MICROX NMOS transistors

Maurice H. Hanes; Anant K. Agarwal; T. W. O'Keeffe; H. M. Hobgood; John R. Szedon; T. J. Smith; R. R. Siergiej; Paul G. McMullin; H. C. Nathanson; Michael C. Driver; R. Noel Thomas

1993-01-01

285

Integral testing of relays and circuit breakers  

SciTech Connect

Among all equipment types considered for seismic qualification, relays have been most extensively studied through testing due to a wide variation of their designs and seismic capacities. A temporary electrical discontinuity or ``chatter`` is the common concern for relays. A chatter duration of 2 milliseconds is typically used as an acceptance criterion to determine the seismic capability of a relay. Many electrical devices, on the other hand, receiving input signals from relays can safely tolerate a chatter level much greater than 2 ms. In Phase I of a test program, Brookhaven National Laboratory performed testing of many relay models using the 2-ms chatter criterion. In Phase II of the program, the factors influencing the relay chatter criterion, and impacts of relay chatter on medium and low voltage circuit breakers and lockout relays were investigated. This paper briefly describes the Phase II tests and presents the important observations.

Bandyopadhyay, K.K.

1993-12-31

286

Experimental and Numerical Studies on dV\\/dt Robustness of 1200 V High-Voltage Integrated Circuits Using Self-Isolation Structure  

Microsoft Academic Search

Experimental results on the high-voltage level shifter and dV\\/dt robustness of 1200 V high voltage integrated circuits (HVICs) using a self-isolation (SI) structure are reported for the first time. Generally, because high dV\\/dt stress is applied to HVICs during insulated gate bipolar transistor (IGBT) switching, significant displacement current flows through a high-voltage isolation capacitance. This current acts as the base

Tomoyuki Yamazaki; Shin-ichi Jimbo; Naoki Kumagai; Akira Nishiura; Tatsuhiko Fujihira; Yasukazu Seki; Takashi Matsumoto

2006-01-01

287

High-Performance Poly-Si TFTs Using Ultrathin Gate Dielectric for Monolithic Three-Dimensional Integrated Circuits and System on Glass Applications  

Microsoft Academic Search

High-performance poly-Si thin-film transistors (TFTs) using an ultrathin high- ? metal gate stack with a subthreshold swing (SS) of 193 mV\\/dec when operating at room temperature and maximum thermal budget of 700°C are readily compatible with monolithic 3-D integrated circuits (3D-ICs) and silicon-on-glass (SOG) applications. The SS is reduced to 31 mV\\/dec, and the on\\/off current ratio is increased to

M. H. Lee; S. L. Wu; M.-J. Yang; K.-J. Chen; G.-L. Luo; L.-S. Lee; M.-J. Kao

2010-01-01

288

Healing of voids in the aluminum metallization of integrated circuit chips  

NASA Technical Reports Server (NTRS)

The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas R.

1990-01-01

289

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes  

NASA Astrophysics Data System (ADS)

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr05471g

Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng

2014-11-01

290

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation  

NASA Technical Reports Server (NTRS)

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

2011-01-01

291

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes.  

PubMed

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfO(x) thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ? 46.2 cm(2) V(-1) s(-1), 10(5) and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates. PMID:25363072

Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng

2014-12-21

292

1998 technology roadmap for integrated circuits used in critical applications  

SciTech Connect

Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

Dellin, T.A.

1998-09-01

293

EM Effects on Semiconductor Devices, Gates and Integrated Circuit  

E-print Network

Ionization & Breakdown -Gate Current and Oxide Breakdown #12;Device Modeling Probes Inside Device Where causes MOSFET oxide damage #12;MOSFET Gate Dielectric Breakdown: Formation of channels in oxide between on Semiconductor Devices, Gates and Integrated Circuit Interconnects Goal: Through modeling and experiment

Anlage, Steven

294

Single-Event Transients in Bipolar Linear Integrated Circuits  

Microsoft Academic Search

Single-event transients (SETs) in linear integrated circuits have caused anomalies in a number of spacecraft. The consequences of these anomalies have spurred efforts to better understand SETs, including the mechanisms responsible for their generation, the best approaches for testing, how data should be analyzed and presented, and approaches for mitigation

Stephen Buchner; Dale McMorrow

2006-01-01

295

NEWS FOR ECE ILLINOIS ALUMNI AND FRIENDS Integrated Circuit  

E-print Network

NEWS FOR ECE ILLINOIS ALUMNI AND FRIENDS FALL 2008 Integrated Circuit turns50 Also in this issue: Illinois home to new Microsoft- and Intel-funded parallel computing center Copper nanowires grown by new process create long-lasting displays Control, Thy Passion: The story of an eminent Illinois lab Department

Liu, Gang "Logan"

296

Performance of digital integrated circuit technologies at very high temperatures  

SciTech Connect

Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

1980-01-01

297

Hybrid Silicon Evanescent Photonic Integrated Circuit John E. Bowersa  

E-print Network

Hybrid Silicon Evanescent Photonic Integrated Circuit Technology John E. Bowersa , Alexander W, Israel Email: bowers@ece.ucsb.edu (Invited Paper) Abstract: The hybrid silicon evanescent device platform utilizes III-V gain materials bonded to passive silicon waveguides. In this paper, we discuss this device

Bowers, John

298

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Myers, D.R.

1988-04-20

299

Cooling of Integrated Circuits Using Droplet-Based Microfluidics  

E-print Network

Cooling of Integrated Circuits Using Droplet-Based Microfluidics Vamsee K. Pamula Duke University and microfluidics-based solutions were proposed in the past. We present a cooling method based on high spot, Cooling, Thermal Management, Heat Removal. 1. INTRODUCTION Decreasing feature sizes

Chakrabarty, Krishnendu

300

Automated failure population creation for validating integrated circuit diagnosis methods  

Microsoft Academic Search

Integrated circuit (IC) diagnosis typically analyzes failed chips by reasoning about their responses to test patterns to deduce what has gone wrong. Current trends use diagnosis as the first step in extracting valuable information from a large population of failing ICs that include, for example, design-feature failure rates and defect-occurrence statistics. However, it is difficult to examine the accuracy of

Wing Chiu Tam; Osei Poku

2009-01-01

301

Precision Capacitor Ratio Measurement Technique for Integrated Circuit Capacitor Arrays  

Microsoft Academic Search

The recent development of integrated circuit capacitor arrays and the growth of their applications have resulted in a need to perform precision testing as an aid to future design improvements. For reasons discussed in this paper, laboratory instruments such as capacitance bridges are not well-suited to this need. In order to test capacitor arrays accurately, a novel technique has been

James L. McCreary; David A. Sealer

1979-01-01

302

DNA chips --Integrated Chemical Circuits for DNADiagnosis and DNA computers  

E-print Network

DNA chips -- Integrated Chemical Circuits for DNADiagnosis and DNA computers Akira Suyama, Associate Professor Institute of Physics, Graduate School of Arts and Sciences, The University of Tokyo DNA chips are si l i con­ or glass­based smal l surfaces on which many DNA ol i gonuc l eotides are i

Hagiya, Masami

303

Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits  

E-print Network

Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits Aris Christou Materials of the failure rate of each component due to interaction effects of the failed components. The Monte Carlo failure rates become nonconstant. The Monte Carlo technique is an appropriate methodology used to treat

Rubloff, Gary W.

304

Analog Integrated Circuits Design for Processing Physiological Signals  

Microsoft Academic Search

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this

Yan Li; Carmen C. Y. Poon; Yuan-Ting Zhang

2010-01-01

305

Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia  

DOEpatents

Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

2007-04-24

306

An integrated circuit/packet switched videoconferencing system  

SciTech Connect

The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible videoconferencing system for use by high energy physics collaborations and others wishing to use videoconferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of videoconferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEP`s needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Videoconferencing Using PAckets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched videoconferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet videoconferencing interface. Augmentation is centered in another subsystem called MSB (Multiport multisession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system.

Kippenhan, H.A. Jr.; Lidinsky, W.P.; Roediger, G.A. [Fermi National Accelerator Lab., Batavia, IL (United States); Watts, T.A. [Rutgers Univ., Piscataway, NJ (United States). Busch Campus

1995-11-01

307

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Myers, David R. (Albuquerque, NM)

1989-01-01

308

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Myers, D.R.

1989-09-12

309

Transmitter development for cellular integrated circuits  

Microsoft Academic Search

This article reviews transmitter topologies for radio transceivers with emphasis on cellular applications. In the first section it discusses different architectures and the challenges in practical implementations. Then it presents a transmitter as part of a fully integrated transceiver for GSM\\/GPRS\\/EDGE.

Alireza Zolfaghari; Hooman Darabi; Henrik Jensen; John Leete; Behnam Mohammadi; Janice Chiu; Qiang Li; Zhimin Zhou; P. Lettieri; Yuyu Chang; A. Hadji-Abdolhamid; P. Chang; M. Nariman; I. Bhatti; A. Medi; L. Serrano; J. Welz; K. Shoarinejad; S. Hasan; J. Castaneda; J. Kim; H. Tran; P. Kilcoyne; R. Chen; B. Lee; B. Zhao; B. Ibrahim; M. Rofougaran; A. Rofougaran

2008-01-01

310

Laser Testing of Integrated Circuits (ELASTIC)  

NASA Astrophysics Data System (ADS)

The inadequacy of the stuck-at fault model has been well aired and documented.1 ,2 All studies agree that this model does not reflect the physical failures of real devices,3 principally because such failures do not exhibit a 1:1 mapping onto the logic domain.2 ,4 Circuit layouts which are based on stick diagrams do however reflect the physical domain in sufficient detail (see Fig. 1) to enable both structural defects, together with shorts and opens in metallic and non-metallic domains, to be detected and located. The author has proposed the adoption of a novel method which processes information obtained from a scanning laser beam reflected from a surface profile. Scanning may be of a raster nature over the surface, or follow a suitable path search along metal lines. The latter search type has been simulated in PROLOG. Such a topological approach to the testing problem offers a test structure for exploitation using a laser beam probe technique. In this paper the theory of reflectivity is described as it relates to the test method, and the results presented are based upon reflectance measurements obtained by raster scanning.

Jones, Robert H.

1990-01-01

311

Enhanced heterostructure field effect transistor CAD model suitable for simulation of mixed mode circuits  

Microsoft Academic Search

We describe a new enhanced model for deep submicron heterostructure field effect transistors (HFET's) suitable for implementation in computer aided design (CAD) software packages such as SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of both n- and p-channel deep submicron HFET's over the temperature range 250-450 K. The current-voltage (I-V) characteristics are described by a single, continuous,

Trond Ytterdal; Tor A. Fjeldly; Michael S. Shur; Steven M. Baier; R. Lucero

1999-01-01

312

Application of AlGaAs\\/GaAs ballistic collection transistors to multiplexer and preamplifier circuits  

Microsoft Academic Search

Ballistic collection transistors with a 'launcher' (L-BCTs) are applied to the fabrication of high-speed\\/broadband ICs. The L-BCTs, in which base widening is suppressed and the ballistic transport of electrons is utilized to reduce transit time without an increase in base collector capacitance, are combined with a novel self-alignment process technology that makes it possible to enlarge the cutoff frequency f

Y. Matsuoka; S. Yamahata; H. Ichino; E. Sano; T. Ishibashi

1991-01-01

313

Quantum functional devices - Resonant-tunneling transistors, circuits with reduced complexity, and multiple-valued logic  

Microsoft Academic Search

Recent advances in the area of quantum functional devices are discussed. After a discussion of the functional device concept, resonant-tunneling bipolar transistors (RTBTs) with a double barrier in the base region are described. Design considerations for RTBTs with ballistic injection and the first observation of minority-electron ballistic RT are presented. RTBTs using thermionic injection and exhibiting a high peak-to-valley ratio

Federico Capasso; Susanta Sen; Fabio Beltram; Leda M. Lunardi; Arvind S. Vengurlekar; P. R. Smith; N. J. Shah; R. J. Malik; A. Y. Cho

1989-01-01

314

Radiation damage in MOS integrated circuits, Part 1  

NASA Technical Reports Server (NTRS)

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Danchenko, V.

1971-01-01

315

A PWM transistor inverter for an ac electric vehicle drive  

NASA Astrophysics Data System (ADS)

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Slicker, J. M.

1981-10-01

316

A PWM transistor inverter for an ac electric vehicle drive  

NASA Technical Reports Server (NTRS)

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Slicker, J. M.

1981-01-01

317

Integrated optical detection circuit for magneto-optical drive  

NASA Astrophysics Data System (ADS)

An integrated optical circuit (IOC) combining all the detection functions of a standard magneto-optical reading head (MO reading, focus and tracking control) is presented. The reading function is achieved by means of a patented interferometric circuit. For tracking control, the well-known push-pull method has been applied and adapted to integrated optics. In this case, the role of the IOC is just to separate the beam reflected back from the disc in two halves in order to compare their intensity. For focus control, several principles have been tested: standard ones adapted to integrated optics (`wax-wane' method or Foucault knife-edge) and an original method based on multimode interferences, taking benefits of integrated optics specificity. The implemented technology is based on a silicon substrate with a silicon nitride core between two silica cladding layers (Si/SiO2/Si3N4/SiO2). This technology is a low cost technology well adapted for mass production. The optical components of the circuits are made by standard contact photolithography and reactive ion etching. Several wafers with about 50 devices each, have been processed and characterized. In particular, the detection signals have been compared with the detection signals delivered simultaneously by a Philips-IBM 128 MB MO drive. This experiment demonstrates the feasibility of an integrated detection device for MO drive.

Mottier, Patrick L.; Lapras, V.; Chabrol, C.

1995-02-01

318

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors  

E-print Network

industry. Circuit simulation time has been substantially reduced through algorithm improvement and hardware enhancement through high performance computing (HPC) platforms. Given its ‘industry standard’ status for computer aided design and analysis... to Prof. Razali Ismail for the advice and supports. I could not complete my study without the help and discussions with Chin Shin Liang, Desmond Chek, David Chuah and Caston Urayai. Their contributions in quantum physics and circuit simulation...

Tan, Michael Loong Peng

2011-06-07

319

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications  

NASA Technical Reports Server (NTRS)

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the switch and the inductor configuration. In the fault condition, both the resistor and the inductor react immediately. The resistor reacts by allowing more current to flow and dropping the voltage. Initially, the inductor reacts by dropping the voltage, and then by not allowing the current to change. When the comparator detects the drop in voltage, it opens the switch, thus preventing any further current flow. The inductor alone is not sufficient protection, because after the voltage drop has settled, the inductor would then allow the current to change, in this example, the current would be 3.7 A. In the fault condition, the resistor is flowing 200 mA until the fuse blows (anywhere from 1 ms to 100 s), while the switch and inductor combination is flowing about 2 A test current while monitoring for the fault to be corrected. Finally, as an additional safety feature, the circuit can be configured to hold the switch opened until both the load and source are disconnected.

Burns, Bradley M.; Blalock, Norman N.

2010-01-01

320

77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products Containing Same; Commission...of certain integrated circuit packages provided with multiple heat-conducting paths and products containing same by reason...

2012-12-12

321

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same...sale within the United States after importation of certain semiconductor integrated circuit devices and products containing...

2012-10-04

322

77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same...sale within the United States after importation of certain semiconductor integrated circuit devices and products containing...

2012-07-03

323

75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...  

Federal Register 2010, 2011, 2012, 2013, 2014

...337-TA-648] Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing Same; Notice of Commission...importation of certain semiconductor integrated circuits using tungsten metallization and products containing the same by reason...

2010-12-06

324

An analogue test technique for massively parallel integrated circuits and systems: An approach to neural networks circuits testing  

Microsoft Academic Search

\\u000a Abstract  The increase in integration density and in complexity of moderns integrated circuits and systems revealed the necessity to\\u000a consider the testability problem at the design level of circuits. One of the most active research areas in circuits design,\\u000a over the past decade, has been the implementation of neural networks as electronic VLSI chips. Especially, the implementation\\u000a of artificial neural networks

Kurosh Madani

1993-01-01

325

Focal plane infrared readout circuit  

NASA Technical Reports Server (NTRS)

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

Pain, Bedabrata (Inventor)

2002-01-01

326

The transition to Cu, damascene and low-K dielectrics for integrated circuit interconnects, impacts on the industry.  

NASA Astrophysics Data System (ADS)

This paper will briefly describe impacts of the transition to Cu and low-K dielectrics: why we want them, how close we are to fulfilling the want, and how they will impact the microelectronics industry. The improvements of microelectronic performance that fostered these innovations where in the past paced by our ability to build smaller, and therefore faster, transistors. Today the pace of innovation is being governed by our ability to build interconnections between these ever smaller and exponentially more numerous transistors. As a result the entire industry is embarking on the first major revision of integrated circuit interconnect technology since the original Robert Noyce invention of over 30 years ago. This transition calls for a change in all of the materials used to fabricate integrated circuit interconnects as well as the tools and methods by which we build them. In short, we plan to change everything. The short history and the current status of the technology transition will be reviewed. The core technology will be discussed, but this paper will also discuss other impacts of the transition, such as the equipment business¯ and of course, metrology. Changing everything in the technology is not simply going to impact the end products; it will also impact the entire industry and infrastructure of semiconductor manufacturing.

Monnig, Kenneth A.

2001-01-01

327

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations  

PubMed Central

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ?1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ?140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

2008-01-01

328

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.  

PubMed

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-01

329

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering  

SciTech Connect

Ambipolar semiconducting polymers, characterized by both high electron (?{sub e}) and hole (?{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with ?{sub h}?=?0.29 cm{sup 2}/V s and ?{sub e}?=?0.001 cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with ?{sub e}?=?0.12 cm{sup 2}/V s and ?{sub h}?=?8 ×?10{sup ?4}?cm{sup 2}/V?s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Dell'Erba, Giorgio; Natali, Dario [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano (Italy); Luzio, Alessandro; Caironi, Mario, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu [Heeger Center for Advanced Materials, School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwagiro, Buk-gu, Gwangju 500-712 (Korea, Republic of); Noh, Yong-Young, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Department of Energy and Materials Engineering, Dongguk University, 26 Pil-dong, 3-ga, Jung-gu, Seoul 100-715 (Korea, Republic of)

2014-04-14

330

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering  

NASA Astrophysics Data System (ADS)

Ambipolar semiconducting polymers, characterized by both high electron (?e) and hole (?h) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with ?h = 0.29 cm2/V s and ?e = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with ?e = 0.12 cm2/V s and ?h = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

2014-04-01

331

How to Build Electronic Circuits  

NSDL National Science Digital Library

This site offers a series of 41 videos about building electronic circuits. The videos include: -How Electron Flow Occurs in Electronic Circuits -Why Schematics are Used to Build Electronic Circuits -How Current is Determined by the Electronic Circuit -How Resistors Work in Electronic Circuits -Color Codes for Resistors in Electronic Circuits -How Capacitors Work in Electronic Circuits -How to Store a Charge in a Capacitor Inductors & Their Function -How to Measure Components in an Electronic Circuit -How Printed Circuit Boards Work -What Tools are Needed to Work with Electronics -Differences in Wire Gauges -How to Strip Wires Using Wire Strippers -How to Safely Work with Electronics -How to Power an Electronic Circuit -How to Measure Voltage in an Electronic Circuit -How to Measure Current in a Circuit -How to Measure Resistance in an Electronic Circuit -How Soldering Irons Work -How to Tin a Soldering Iron -How to Solder Electronic Leads Together -How to Use Perfboard to Make an Electronic Circuit -How to De-solder Electronic Connections -How to Diagnose Cold Solder Connections -How to Reflow a Connection in an Electronic Circuit -How to Use a Breadboard to Prototype a Circuit Board -How a Light Emitting Diode Works Uses & Operation of a Fuse -How to Use Integrated Circuits -How Transistors Work in an Electronic Circuit -How a Variable Resistor Works in an Electronic Circuit -How Does a Series Circuit Work -How to Compute Resistor Resistance in an Electronic Circuit -How Resistors Work in Parallel Circuits -How Schematics are Used in Electronics -How Switches Open & Close Circuits Electronic Circuits in Garage Door Openers -How to Make a Schematic for Your Electronic Circuit Project -How to Test a Prototype of Your Electronic Circuit -How to Use Perfboard to Build an Electronic Circuit and -Practical Operation of Electronic Circuit Indicators

Safronoff, Ross

332

Radiation Testing and Evaluation Issues for Modern Integrated Circuits  

NASA Technical Reports Server (NTRS)

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

LaBel, Kenneth A.; Cohn, Lew M.

2005-01-01

333

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications  

NASA Technical Reports Server (NTRS)

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

1987-01-01

334

A simple and robust niobium Josephson junction integrated circuit process  

Microsoft Academic Search

A simple and robust process for fabricating low-Tc Josephson junction integrated circuits has been developed. The process is designed around the Nb\\/Al2O3-Al\\/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed

A. T. Barfknecht; R. C. Ruby; H. L. Ko

1991-01-01

335

Approaches to isolation in high voltage integrated circuits  

Microsoft Academic Search

This paper reviews high voltage integrated circuits, their isolation methods, and device features. Conventional Junction Isolation can be used for voltage requirements >200 volts if special upward-downward diffusions are employed or if the RESURF principle is applied. Self Isolation is limited to common source arrays. Dielectric Isolation is most versatile and area efficient. MOS-Bipolar combination devices, complementary designs, and on-chip

H. W. Becke

1985-01-01

336

Automation of pre-cap visual inspection for integrated circuits  

NASA Astrophysics Data System (ADS)

The feasibility of an automatic inspection system which can perform a 100% internal visual inspection of integrated circuits (ICs) during production was investigated. Columbia Research Corporation (CRC) reviewed technical approaches and the feasibility of applying them to production. They also surveyed the companies currently developing automated IC inspection systems and found that no commercial contractor has installed equipment for routine inspection on a production basis. This project was terminated because the necessary equipment is still undergoing design and evaluation.

Flake, D.; Fisher, G.; Watson, P.; Niemiec, G.

1982-12-01

337

Advanced polymer systems for optoelectronic integrated circuit applications  

Microsoft Academic Search

An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness,

Louay A. Eldada; Kelly M. Stengel; Lawrence W. Shacklette; Robert A. Norwood; Chengzeng Xu; Chengjiu Wu; James T. Yardley

1997-01-01

338

Extended life testing evaluation of complementary MOS integrated circuits  

NASA Technical Reports Server (NTRS)

The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

Brosnan, T. E.

1972-01-01

339

Final Report on LDRD Project: Development of Quantum Tunneling Transistors for Practical Circuit Applications  

SciTech Connect

The goal of this LDRD was to engineer further improvements in a novel electron tunneling device, the double electron layer tunneling transistor (DELTT). The DELTT is a three terminal quantum device, which does not require lateral depletion or lateral confinement, but rather is entirely planar in configuration. The DELTT's operation is based on 2D-2D tunneling between two parallel 2D electron layers in a semiconductor double quantum well heterostructure. The only critical dimensions reside in the growth direction, thus taking full advantage of the single atomic layer resolution of existing semiconductor growth techniques such as molecular beam epitaxy. Despite these advances, the original DELTT design suffered from a number of performance short comings that would need to be overcome for practical applications. These included (i)a peak voltage too low ({approx}20 mV) to interface with conventional electronics and to be robust against environmental noise, (ii) a low peak current density, (iii) a relatively weak dependence of the peak voltage on applied gate voltage, and (iv) an operating temperature that, while fairly high, remained below room temperature. In this LDRD we designed and demonstrated an advanced resonant tunneling transistor that incorporates structural elements both of the DELTT and of conventional double barrier resonant tunneling diodes (RTDs). Specifically, the device is similar to the DELTT in that it is based on 2D-2D tunneling and is controlled by a surface gate, yet is also similar to the RTD in that it has a double barrier structure and a third collector region. Indeed, the device may be thought of either as an RTD with a gate-controlled, fully 2D emitter, or alternatively, as a ''3-layer DELTT,'' the name we have chosen for the device. This new resonant tunneling transistor retains the original DELTT advantages of a planar geometry and sharp 2D-2D tunneling characteristics, yet also overcomes the performance shortcomings of the original DELTT design. In particular, it exhibits the high peak voltages and current densities associated with conventional RTDs, allows sensitive control of the peak voltage by the control gate, and operates nearly at room temperature. Finally, we note under this LDRD we also investigated the use of three layer DELTT structures as long wavelength (Terahertz) detectors using photon-assisted tunneling. We have recently observed a narrowband (resonant) tunable photoresponse in related structures consisting of grating-gated double quantum wells, and report on that work here as well.

SIMMONS, JERRY A.; MOON, JUENG-SUN; BLOUNT, MARK; LYO, SUNGKWUN K.; BACA, WES E.; RENO, JOHN L.; LILLY, MICHAEL P.; WENDT, JOEL R.; WANKE, MICHAEL C.; PERALTA, X.G.; EISENSTEIN, J.P.; BURKE, P.J.

2002-07-01

340

Amorphous In–Ga–Zn–O Thin Film Transistor Current-Scaling Pixel Electrode Circuit for Active-Matrix Organic Light-Emitting Displays  

Microsoft Academic Search

In this paper, we analyze application of amorphous In-Ga-Zn-O thin film transistors (a-InGaZnO TFTs) to current-scaling pixel electrode circuit that could be used for 3-in. quarter video graphics array (QVGA) full color active-matrix organic light-emitting displays (AM-OLEDs). Simulation results, based on a-InGaZnO TFT and OLED experimental data, show that both device sizes and operational voltages can be reduced when compare

Charlene Chen; Katsumi Abe; Tze-Ching Fung; Hideya Kumomi; Jerzy Kanicki

2009-01-01

341

Integrated circuits for accurate linear analogue electric signal processing  

NASA Astrophysics Data System (ADS)

The main lines in the design of integrated circuits for accurate analog linear electric signal processing in a frequency range including DC are investigated. A categorization of universal active electronic devices is presented on the basis of the connections of one of the terminals of the input and output ports to the common ground potential. The means for quantifying the attributes of four types of universal active electronic devices are included. The design of integrated operational voltage amplifiers (OVA) is discussed. Several important applications in the field of general instrumentation are numerically evaluated, and the design of operatinal floating amplifiers is presented.

Huijsing, J. H.

1981-11-01

342

Neuromorphic opto-electronic integrated circuits for optical signal processing  

NASA Astrophysics Data System (ADS)

The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

2014-08-01

343

Integration of CMOS, single electron transistors, and quantumdot cellular automata  

Microsoft Academic Search

The physical limits associated with CMOS devices require the development of new computational architectures. Quantum-dot cellular automata (QCA) offers a low power, high-speed computational architecture. This paper demonstrates the integration of CMOS, QCA, and SET technologies on a single silicon die. A capacitive voltage divider is used to reduce standard CMOS logic voltage levels to millivolt control voltages for a

Aaron A. Prager; Alexei O. Orlov; Gregory L. Snider

2009-01-01

344

Time domain wave propagation in multilayered integrated circuits  

NASA Astrophysics Data System (ADS)

During this period, we have (1) modeled and calculated the impedance parameters and propagation characteristics of simple structures, (2) analyzed the transient response of signal transmission on strip lines with perpendicularly crossing strips geometry and (3) analyzed the transient response of point and line sources excitation in two-layer media, (4) generalized the method of characteristics for signal propagation on nonuniformly coupled transmission lines, and (5) studied the models for vias for interchip connections. Many integrated circuits contain strip lines at different heights that run parallel or perpendicular to each other. First the capacitances associated with two offset parallel strips at different heights between ground planes are computed using the conformal mapping approach. As an extension, a simplified circuit of parallel-plate lines with transverse ridges is introduced to model two parallel strips with perpendicularly crossing strips on top. It was treated as a distributed circuit of transmission lines segments with periodical capacitive loading. In order to calculate the coupling between two lines, this structure was reduced to two equivalent single line circuits.

Kong, J. A.

1987-01-01

345

Pneumatic oscillator circuits for timing and control of integrated microfluidics  

PubMed Central

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

2013-01-01

346

Conception d'un circuit d'etouffement pour photodiodes a avalanche en mode geiger pour integration heterogene 3d  

NASA Astrophysics Data System (ADS)

Le Groupe de Recherche en Appareillage Medical de Sherbrooke (GRAMS) travaille actuellement sur un programme de recherche portant sur des photodiodes a avalanche mono-photoniques (PAMP) operees en mode Geiger en vue d'une application a la tomographie d'emission par positrons (TEP). Pour operer dans ce mode; la PAMP, ou SPAD selon l'acronyme anglais (Single Photon Avalanche Diode), requiert un circuit d'etouffement (CE) pour, d'une part, arreter l'avalanche pouvant causer sa destruction et, d'autre part. la reinitialiser en mode d'attente d'un nouveau photon. Le role de ce CE comprend egalement une electronique de communication vers les etages de traitement avance de signaux. La performance temporelle optimale du CE est realisee lorsqu'il est juxtapose a la PAMP. Cependant, cela entraine une reduction de la surface photosensible ; un element crucial en imagerie. L'integration 3D, a base d'interconnexions verticales, offre une solution elegante et performante a cette problematique par l'empilement de circuits integres possedant differentes fonctions (PAMP, CE et traitement avance de signaux). Dans l'approche proposee, des circuits d'etouffement de 50 pm x 50 pm realises sur une technologie CMOS 130 mn 3D Tezzaron, contenant chacun 112 transistors, sont matrices afin de correspondre a une matrice de PAMP localisee sur une couche electronique superieure. Chaque circuit d'etouffement possede une gigue temporelle de 7,47 ps RMS selon des simulations faites avec le logiciel Cadence. Le CE a la flexibilite d'ajuster les temps d'etouffement et de recharge pour la PAMP tout en presentant une faible consommation de puissance (~ 0,33 mW a 33 Mcps). La conception du PAMP necessite de supporter des tensions superieures aux 3,3 V de la technologie. Pour repondre a ce probleme, des transistors a drain etendu (DEMOS) ont ete realises. En raison de retards de production par Ies fabricants, les circuits n'ont pu etre testes physiquement par des mesures. Les resultats de ce memoire sont par consequent bases sur des resultats de simulations avec le logiciel Cadence. Mots-cles : Circuit d'etouffement, Photodiodes a avalanche monophotoniques (PAMP), Single Photon Avalanche Diode (SPAD), Integration 3D heterogene, Drain-Extended MOS (DEMOS), CMOS 130 nm 3D Tezzaron/Chartered, Tomographie d'emission par positrons (TEP)

Boisvert, Alexandre

347

Hybrid III-V/silicon SOA for photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Silicon photonics has reached a considerable level of maturity, and the complexity of photonic integrated circuits (PIC) is steadily increasing. As the number of components in a PIC grows, loss management becomes more and more important. Integrated semiconductor optical amplifiers (SOA) will be crucial components in future photonic systems for loss compensation. In addition, there are specific applications, where SOAs can play a key role beyond mere loss compensation, such as modulated reflective SOAs in carrier distributed passive optical networks or optical gates in packet switching. It is, therefore, highly desirable to find a generic integration platform that includes the possibility of integrating SOAs on silicon. Various methods are currently being developed to integrate light emitters on silicon-on-insulator (SOI) waveguide circuits. Many of them use III-V materials for the hybrid integration on SOI. Various types of lasers have been demonstrated by several groups around the globe. In some of the integration approaches, SOAs can be implemented using essentially the same technology as for lasers. In this paper we will focus on SOA devices based on a hybrid integration approach where III-V material is bonded on SOI and a vertical optical mode transfer is used to couple light between SOI waveguides and guides formed in bonded III-V semiconductor layers. In contrast to evanescent coupling schemes, this mode transfer allows for a higher confinement factor in the gain material and thus for efficient light amplification over short propagation distances. We will outline the fabrication process of our hybrid components and present some of the most interesting results from a fabricated and packaged hybrid SOA.

Kaspar, P.; Brenot, R.; Le Liepvre, A.; Accard, A.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Duan, G.-H.; Olivier, S.; Jany, Christophe; Kopp, C.; Menezo, S.

2014-11-01

348

Integrating anatomy and function for zebrafish circuit analysis  

PubMed Central

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties—e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

Arrenberg, Aristides B.; Driever, Wolfgang

2013-01-01

349

Fully integrated circuit chip of microelectronic neural bridge  

NASA Astrophysics Data System (ADS)

Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-?m CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

Xiaoyan, Shen; Zhigong, Wang

2014-09-01

350

Development of Liquid Crystal Display Panel Integrated with Drivers Using Amorphous In-Ga-Zn-Oxide Thin Film Transistors  

Microsoft Academic Search

We designed, prototyped, and evaluated a liquid crystal panel integrated with a gate driver and a source driver using amorphous In-Ga-Zn-oxide thin film transistors (TFTs). Using bottom-gate bottom-contact (BGBC) thin film transistors, superior characteristics could be obtained. We obtained TFT characteristics with little variation even when the thickness of the gate insulator (GI) film was reduced owing to etching of

Takeshi Osada; Kengo Akimoto; Takehisa Sato; Masataka Ikeda; Masashi Tsubuku; Junichiro Sakata; Jun Koyama; Tadashi Serikawa; Shunpei Yamazaki

2010-01-01

351

Advances in integrated photonic circuits for packet-switched interconnection  

NASA Astrophysics Data System (ADS)

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8? space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

352

Observation and Circuit Application of Negative Differential Conductance in Silicon Single-Electron Transistors  

NASA Astrophysics Data System (ADS)

A conductance anomaly displaying large negative differential conductance (NDC) has been observed in a drain current vs. drain voltage curve of Si single-electron transistors (SETs) at 27 K. The NDC appears, mainly in the single-electron-tunneling regime, in such a way that it aligns parallel to the edges of Coulomb diamonds, strongly suggesting that it reflects the discrete nature of the dot states. We show that high-gain SETs, i.e., SETs with gate capacitance that is well larger than the junction capacitances, enable us to regulate the appearance of NDC and to accentuate the tunneling conditions only at the drain side because of the asymmetric sharing of the source-drain voltage between the two junctions. We also show, using high-gain SETs, that the NDC results in a hysteresis loop of drain output voltage as a function of gate voltage for a constant drain-current bias. This enables us to use the SET as a Schmitt-trigger with excellent noise immunity.

Ono, Yukinori; Takahashi, Yasuo

2002-04-01

353

Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits  

E-print Network

Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power ...

Nagarajan, Raghavan

2008-01-01

354

From transistor to nanotube  

NASA Astrophysics Data System (ADS)

We present here the main steps in the evolution of the transistor, since the tremendous invention of such a device and the introduction of the integrated circuit. We will then recall the main steps of Moore's law development. Nanotechnology began at the very beginning of the 21st century. Two aspects are presented in this article: the first, called 'More Moore', consists in continuing the laws of scale up to the physical limits; the second aspect, called 'beyond CMOS' explores new concepts such as spintronics, moletronics, nanotronics and other types of molecular electronics. To cite this article: J.-C. Boudenot, C. R. Physique 9 (2008).

Boudenot, Jean-Claude

2008-01-01

355

Integrated circuits: Resistless processing simplifies production and cuts costs  

SciTech Connect

Reducing the complexity and cost of producing deep-submicrometer integrated circuits (ICs) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today`s industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, ``cluster`` processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

Weiner, K.

1993-03-25

356

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

1995-01-01

357

SiGe/Si Monolithically Integrated Amplifier Circuits  

NASA Technical Reports Server (NTRS)

With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

Katehi, Linda P. B.; Bhattacharya, Pallab

1998-01-01

358

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Creighton, J. Randall (Albuquerque, NM); Dominguez, Frank (Albuquerque, NM); Johnson, A. Wayne (Albuquerque, NM); Omstead, Thomas R. (Albuquerque, NM)

1997-01-01

359

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

360

Universal nondestructive mm-wave integrated circuit test fixture  

NASA Technical Reports Server (NTRS)

Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

Romanofsky, Robert R. (inventor); Shalkhauser, Kurt A. (inventor)

1990-01-01

361

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

Cole, E.I. Jr.; Soden, J.M.

1995-07-04

362

Methodology for analysis of TSV stress induced transistor variation and circuit performance  

E-print Network

As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal ...

Yu, Li

363

Air-Stable Conversion of Separated Carbon Nanotube Thin-Film Transistors from P-type to N-type Using Atomic Layer Deposition of High-? Oxide and Its Application in CMOS Logic Circuits  

NASA Astrophysics Data System (ADS)

Pre-separated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable N-type nanotube TFTs with industry compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the P-type TFTs using pre-separated semiconducting nanotubes into air-stable N-type transistors by adding a high-? oxide passivation layer using atomic layer deposition (ALD). The N-type devices exhibit symmetric electrical performance compared with the P-type devices in terms of on-current, on/off ratio and mobility. Various factors affecting the conversion process including ALD temperature, metal contact material, channel length, have also been systematically studied. A complementary metal-oxide-semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.

Zhang, Jialu; Wang, Chuan; Fu, Yue; Che, Yuchi; Zhou, Chongwu

2011-03-01

364

A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor  

E-print Network

We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

2010-08-28

365

Lateral DMOS transistor optimized for high voltage BIMOS applications  

Microsoft Academic Search

Optimal placement of buried layer under a LDMOS transistor extends the usefulness of the device in high voltage BIMOS integrated circuits. Coupling the resurf effect and gate-underlaid concept results in a LDMOS transistor with uncompromised high voltage characteristics: Source-drain avalanche breakdown greater than 300 V and channel-substrate punchthrough breakdown greater than 200 V. The process utilized to fabricate the high

A. R. Alvarez; R. M. Roop; K. I. Ray; G. R. Getterneyer

1983-01-01

366

Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit  

NASA Astrophysics Data System (ADS)

Graphene transistors were fabricated by a wafer-scale “top-down” process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.

Nakaharai, Shu; Iijima, Tomohiko; Ogawa, Shinichi; Yagi, Katsunori; Harada, Naoki; Hayashi, Kenjiro; Kondo, Daiyu; Takahashi, Makoto; Li, Songlin; Tsukagoshi, Kazuhito; Sato, Shintaro; Yokoyama, Naoki

2015-04-01

367

Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits  

SciTech Connect

Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

Keast, Craig (M.I.T. Lincoln Laboratory) [M.I.T. Lincoln Laboratory

2007-02-28

368

Mixed signal custom integrated circuit development for physics instrumentation  

SciTech Connect

The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

1998-10-01

369

Integrated circuit amplifiers for multi-electrode intracortical recording.  

PubMed

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified. PMID:19139560

Jochum, Thomas; Denison, Timothy; Wolf, Patrick

2009-02-01

370

TUTORIAL: Integrated circuit amplifiers for multi-electrode intracortical recording  

NASA Astrophysics Data System (ADS)

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

Jochum, Thomas; Denison, Timothy; Wolf, Patrick

2009-02-01

371

Local and nonlocal optically induced transparency effects in graphene-silicon hybrid nanophotonic integrated circuits.  

PubMed

Graphene is well-known as a two-dimensional sheet of carbon atoms arrayed in a honeycomb structure. It has some unique and fascinating properties, which are useful for realizing many optoelectronic devices and applications, including transistors, photodetectors, solar cells, and modulators. To enhance light-graphene interactions and take advantage of its properties, a promising approach is to combine a graphene sheet with optical waveguides, such as silicon nanophotonic wires considered in this paper. Here we report local and nonlocal optically induced transparency (OIT) effects in graphene-silicon hybrid nanophotonic integrated circuits. A low-power, continuous-wave laser is used as the pump light, and the power required for producing the OIT effect is as low as ?0.1 mW. The corresponding power density is several orders lower than that needed for the previously reported saturated absorption effect in graphene, which implies a mechanism involving light absorption by the silicon and photocarrier transport through the silicon-graphene junction. The present OIT effect enables low power, all-optical, broadband control and sensing, modulation and switching locally and nonlocally. PMID:25372937

Yu, Longhai; Zheng, Jiajiu; Xu, Yang; Dai, Daoxin; He, Sailing

2014-11-25

372

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance  

NASA Astrophysics Data System (ADS)

Organic reset–set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V?1 s?1 in the saturation region and a threshold voltage (VTH) of ?2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

373

Circuits  

NSDL National Science Digital Library

Students are introduced to several key concepts of electronic circuits. They learn about some of the physics behind circuits, the key components in a circuit and their pervasiveness in our homes and everyday lives. Students learn about Ohm's law and how it is used to analyze circuits.

Integrated Teaching and Learning Program,

374

Long-wavelength photonic integrated circuits and avalanche photodetectors  

NASA Astrophysics Data System (ADS)

Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve InGaAs/Si APDs with much greater potential than the traditional InGaAs/InP APDs. Preliminary results on their performance will be presented.

Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

375

Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays  

Microsoft Academic Search

This paper presents a novel CMOS charge transfer readout circuit for X-ray time delay and integration (TDI) arrays with a depth of 64. The proposed circuit uses a charge transfer readout similar to CCD; thus, the summing of the signal charges can be implemented easily compared with other typical CMOS readout circuits for TDI arrays. The weakness of TDI arrays

Chul Bum Kim; Byung-Hyuk Kim; Yong Soo Lee; Han Jung; Hee Chul Lee

2006-01-01

376

Time-resolved optical characterization of electrical activity in integrated circuits  

Microsoft Academic Search

If the rate of improvement in the performance of advanced silicon integrated circuits is to be sustained, new techniques for the measurement of electrical waveforms in operating circuits are needed. Critical factors dictating this requirement include the increased speed and complexity of circuits, the growing importance of faults that appear only during high-speed operation, and the use of flip-chip packaging

JAMES C. TSANG; JEFFREY ALAN KASH; DAVID P. VALLETT

2000-01-01

377

A functional validation methodology based on error models for measuring the quality of digital integrated circuits  

Microsoft Academic Search

Functional validation plays an important role in the design cycle of digital integrated circuits. The generation of good test benches is required for checking the complete circuit behaviour. Early location of design errors could highly reduce the development time and cost for these circuits. There are several initiatives for the development of methods that enhance the functional validation of a

Celia Lopez-Ongil; Luis Entrena-Arrontes; Teresa Riesgo-Alcaide; Javier Uceda-Antolin

2005-01-01

378

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.  

PubMed

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc. PMID:24441981

Gao, Pingqi; Zhang, Qing

2014-02-14

379

The large-scale integration of high-performance silicon nanowire field effect transistors.  

PubMed

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale. PMID:19755723

Li, Qiliang; Zhu, Xiaoxiao; Yang, Yang; Ioannou, Dimitris E; Xiong, Hao D; Kwon, Doo-Won; Suehle, John S; Richter, Curt A

2009-10-14

380

Integration of monolithic microwave integrated circuits into phased array antenna systems  

NASA Astrophysics Data System (ADS)

Monolithic Microwave Integrated Circuit (MMIC) technology will have a dramatic impact upon future radar, electronic warfare, and communication systems which utilize phased arrays. Systems in both the commercial and defense industries which require large quantities of densely packed circuitry will become the prime benefactors of MMIC technology. The microwave and antenna engineers responsible for the integration of MMICs into these new systems must develop compatible radiating elements, feed networks, and module configurations as well as techniques for satisfying electrical, mechanical, and thermal interfaces in the array. This paper discusses techniques that have been developed for interfacing MMIC modules to phased array systems. Radiating elements suitable for integration with monolithic circuitry including some novel implementations of classic radiators are presented. Examples of monolithic circuits as well as mounting and packaging methods for complete transmit/receive modules are given.

Edward, B. J.

1984-03-01

381

Investigation of failure mechanisms in integrated vacuum circuits  

NASA Technical Reports Server (NTRS)

The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

Rosengreen, A.

1972-01-01

382

Plasmonic nanopatch array for optical integrated circuit applications  

NASA Astrophysics Data System (ADS)

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

Qu, Shi-Wei; Nie, Zai-Ping

2013-11-01

383

Plasmonic nanopatch array for optical integrated circuit applications.  

PubMed

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

Qu, Shi-Wei; Nie, Zai-Ping

2013-01-01

384

Development of a plan for automating integrated circuit processing  

NASA Technical Reports Server (NTRS)

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

1971-01-01

385

Plasmonic nanopatch array for optical integrated circuit applications  

PubMed Central

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

Qu, Shi-Wei; Nie, Zai-Ping

2013-01-01

386

Apparatus and method for defect testing of integrated circuits  

SciTech Connect

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Cole, E.I. Jr.; Soden, J.M.

2000-02-29

387

Apparatus and method for defect testing of integrated circuits  

DOEpatents

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

2000-01-01

388

Aesop: a tool for automated transistor sizing  

Microsoft Academic Search

This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area

Kye S. Hedlund

1987-01-01

389

Volatile general anesthetic sensing with organic field-effect transistors integrating phospholipid membranes.  

PubMed

The detailed action mechanism of volatile general anesthetics is still unknown despite their effect has been clinically exploited for more than a century. Long ago it was also assessed that the potency of an anesthetic molecule well correlates with its lipophilicity and phospholipids were eventually identified as mediators. As yet, the direct effect of volatile anesthetics at physiological relevant concentrations on membranes is still under scrutiny. Organic field-effect transistors (OFETs) integrating a phospholipid (PL) functional bio inter-layer (FBI) are here proposed for the electronic detection of archetypal volatile anesthetic molecules such as diethyl ether and halothane. This technology allows to directly interface a PL layer to an electronic transistor channel, and directly probe subtle changes occurring in the bio-layer. Repeatable responses of PL FBI-OFET to anesthetics are produced in a concentration range that reaches few percent, namely the clinically relevant regime. The PL FBI-OFET is also shown to deliver a comparably weaker response to a non-anesthetic volatile molecule such as acetone. PMID:22921091

Daniela Angione, Maria; Magliulo, Maria; Cotrone, Serafina; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Gobeljic, Danka; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2013-02-15

390

Charge collection in GaAs MESFET circuits using a high energy microbeam  

Microsoft Academic Search

The mechanisms responsible for single event upsets can be studied more realistically in transistors that are part of an integrated test circuit than in single isolated test transistors with fixed biases on all the nodes. Both energetic, heavy ions and focused, pulsed laser light were used to generate transient voltages at a number of different nodes in a GaAs MESFET

S. Buchner; A. B. Campbell; T. Weatherford; A. Knudson; P. McDonald; D. McMorrow; B. Fischer; S. Metzger; M. Schloegl

1996-01-01

391

Optoelectronic system integration on silicon: Waveguides, photodetectors, and VLSI CMOS circuits on one chip  

NASA Astrophysics Data System (ADS)

Optical waveguides, photodetectors, and VLSI CMOS circuits are integrated monolithically in different ways: In a combined integration technique the light-guiding film is deposited and covered with a SiO2 layer replacing standard PSG as the dielectric insulation of polysilicon and metallization. In a stacked method the waveguide fabrication starts after metallization and test of the CMOS circuits. Electrooptical coupling is performed by butt-, leaky wave-, or mirror-coupling of waveguides and photodetectors. To fabricate the system, SWAMI LOCOS technique is applied for monolithic integration of both integrated optical devices and microelectronic circuits. This paper discusses the integration technology and the results of static and dynamic measurements.

Hilleringmann, U.; Goser, K.

1995-05-01

392

Materials and devices for optical switching and modulation of photonic integrated circuits  

E-print Network

The drive towards photonic integrated circuits (PIC) necessitates the development of new devices and materials capable of achieving miniaturization and integration on a CMOS compatible platform. Optical switching: fast ...

Seneviratne, Dilan Anuradha

2007-01-01

393

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET  

E-print Network

AbstractThe performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well...

Tan, Michael Loong P; Lentaris, Georgios; Amaratunga AJ, Gehan

2012-08-19

394

Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits  

Microsoft Academic Search

Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic insertion of sleep transistors for power-gating. In particular, we propose a novel, layout-aware methodology that facilitates sleep transistor insertion and virtual-ground routing

Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino

2011-01-01

395

Two-Transistor Active Pixel Sensor Readout Circuits in Amorphous Silicon Technology for High-Resolution Digital Imaging Applications  

Microsoft Academic Search

Active pixel sensor (APS) architectures using two transistors per pixel are reported in this paper for high-resolution low-noise digital imaging applications. The fewer number of on-pixel elements and reduced pixel complexity result in a smaller pixel pitch and increased pixel gain, which makes the two-transistor (2T) APS architectures promising for high-resolution, low-noise, and high-speed digital imaging including emerging medical imaging

Farhad Taghibakhsh; Karim S. Karim

2008-01-01

396

Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview  

E-print Network

Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview@rice.edu ABSTRACT This paper presents an overview of hardware and Integrated Circuits (IC) metering methods. IC metering or hardware metering refers to tools, methodologies, and protocols that enable post

397

Effective Cooling of Integrated Circuits Using Liquid Alloy Electrowetting Kamran Mohseni  

E-print Network

Effective Cooling of Integrated Circuits Using Liquid Alloy Electrowetting Kamran Mohseni of air. Such liquid heat sinks, often referred to as cold plates, operate very similarly to air cooled droplets of liquid met- als/alloys for active heat management of Integrated Circuits (ICs) and removal

Mohseni, Kamran

398

A method for measuring collector series-resistance of an integrated circuit from module pins  

Microsoft Academic Search

It is virtually impossible for a user to measure the collector series-resistance RCSof an integrated circuit by probing the chip without opening the package. This letter describes a method for measuring the RCSof a current-switch emitter-follower integrated circuit from module pins within 3.5 percent accuracy.

W. W. Wu

1968-01-01

399

Design structure for in-system redundant array repair in integrated circuits  

DOEpatents

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

400

Integration of single-electron transistors using field-emission-induced electromigration.  

PubMed

A novel technique for the integration of planar-type single-electron transistors (SETs) composed of nanogaps is presented. This technique is based on the electromigration procedure, which is caused by a field emission current. The technique is called "activation." By applying the activation to the nanogaps, SETs can be easily obtained. Furthermore, the charging energy of the SETs can be controlled by adjusting the magnitude of the applied current during the activation process. The integration of two SETs was achieved by passing a field emission current through two series-connected initial nanogaps. The current-voltage (I(D)-V(D)) curves of the simultaneously activated devices exhibited clear electrical-current suppression at a low-bias voltage at 16 K, which is known as the Coulomb blockade. The Coulomb blockade voltage of each device was also obviously modulated by the gate voltage. In addition, the two SETs, which were integrated by the activation procedure, exhibited similar electrical properties, and their charging energy decreased uniformly with increasing the preset current during the activation. These results indicate that the activation procedure allows the simple and easy integration of planar-type SETs. PMID:22121697

Ueno, Shunsuke; Tomoda, Yusuke; Kume, Watari; Hanada, Michinobu; Takiya, Kazutoshi; Shirakashi, Jun-ichi

2011-07-01

401

Focused ion beam damage to MOS integrated circuits  

SciTech Connect

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

FLEETWOOD,D.M.; CAMPBELL,ANN N.; HEMBREE,CHARLES E.; TANGYUNYONG,PAIBOON; JESSING,JEFFREY R.; SODEN,JERRY M.

2000-05-10

402

A comparative characterization analysis of various probing technologies for area array integrated circuits  

NASA Astrophysics Data System (ADS)

This comparative analysis evaluates various probing technologies and proposes an interconnection technology as a test platform to simulate actual probing conditions for manufacturing and implementing the technologies in cost-effective commercial probe card form, specifically for area array bumped "flip chip" integrated circuits. Integrated circuits (IC) continue to increase in size, density of transistors and increased electrical performance with a corresponding increase in the number of input/outputs requiring connections. The semiconductor industry has responded with area array solder bump interconnection technologies which place the connection points across the entire bottom surface to provide the IC more I/Os and shorter routes than present peripheral wirebonding to aluminum pads. However, present cantilever and buckling beam probing methods to electrically test "flip chip" die have been limited in electrical performance and/or have had difficulty accessing the interior of the IC. Probing is essentially determined by three (3) first-order factors: electrical resistance of the physical junction between the probe tip and the bump being probed; alignment of the probe to the bump; and the ability to repeatedly perform the former tasks for all pins for every contact made with a bump. These and other requirements are based on SEMATECH specifications desired by major domestic semiconductor manufacturers anticipated test needs into the next century. The test platform or experimental probe card appeared to be a manufacturable and feasible format in terms of providing the probes a method of interconnection from the high density pattern to a low-density tester interface in probe card form. The 40Pb/60Sn deformed less than the 95Pb/5Sn bump composition under similar vertical loads. Each of the probe concepts exhibited a range of forces and deflection for minimum electrical contact resistances. The concepts which approached the bump vertically required more force (10-12 gms) to minimize electrical resistance as compared to those probe concepts which "scrubbed" or "twisted," (4-6 gms). Most concepts exhibited limited deflection ranges based on planarity and dimensional data but adequate positional accuracy. Electrical properties, specifically ampacity, were found to be limited in concepts which used a spring component. Two experimental concepts appeared to be competitive to present "buckling beam" probing technologies, if further developed.

Armendariz, Norman Jesus

403

A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation  

Microsoft Academic Search

,4Mruct—A class of accurateanafog CMOS circuits is presented which relieson the square-law characteristic of MOStransistorsoperating in the saturated region. 'fIds class of circuits includes voltage multipliers, current multipliers, linear V-Z convertors (LVIC'S), linearZ- V convertors (LfVC's),current squaring circuits (CSC'S), and current divider circuits (DfVC's). Typicalfor thesecircuitsis an independent control of the sum as well as the difference between two gate-source

KLAAS BULT; ANDHANS WALLINGA

1987-01-01

404

High electric stress and insulation challenges in integrated microelectronic circuits  

Microsoft Academic Search

The insulating layer in the transistor has decreased from 100 nm in the early 1970s to only a few nanometers today. This thin insulating layer gives rise to very high electric fields approaching 1000 kV\\/mm for an operating voltage of 1 V. Degradation of the insulation during ageing takes place due to the high field and may eventually lead to

Frøydis Oldervoll

2002-01-01

405

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 6, NO. 2, APRIL 2012 101 A Multichannel Integrated Circuit for Electrical  

E-print Network

Integrated Circuit for Electrical Recording of Neural Activity, With Independent Channel Programmability interfaces, to get more insight in the activity of neuronal networks. The need for higher temporal acquisition system for in vitro and in vivo recording of neural activity. The ASIC consists of 16 low

406

Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS  

NASA Technical Reports Server (NTRS)

Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful performance of experimental, proof-of-concept MMIC K/Ka-band arrays developed with U.S. industry in field demonstrations with ACTS indicates that high density MMIC integration at 20 and 30 GHz is indeed feasible. The successful development and demonstration of the MMIC array systems was possible only because of significant intergovernmental and Government/industry cooperation and the high level of teamwork within Lewis. The results provide a strong incentive for continuing the focused development of MMIC-array technology for satellite communications applications, with emphasis on packaging and cost issues, and for continuing the planning and conducting of other appropriate demonstrations or experiments of phased-array technology with ACTS. Given the present pressures on reducing funding for research and development in Government and industry, the extent to which this can be continued in a cooperative manner will determine whether MMIC array technology will make the transition from the proof-of-concept level to the operational system level.

1996-01-01

407

Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits  

NASA Technical Reports Server (NTRS)

As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

2011-01-01

408

PETRIC - A positron emission tomography readout integrated circuit  

SciTech Connect

We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

2000-11-05

409

Laser Micromachining of Active and Passive Photonic Integrated Circuits  

E-print Network

This thesis describes the development of advanced laser resonators and applications of laserinduced micromachining for photonic circuit fabrication. Two major advantages of laserinduced micromachining are direct patterning ...

Cho, Seong-Ho

2006-06-28

410

Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)  

NASA Astrophysics Data System (ADS)

Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

2000-03-01

411

Analytic models for the kinetics of generating a voltage contrast signal from contact plugs used in integrated circuits  

NASA Astrophysics Data System (ADS)

Electron beams are commonly used to inspect wafers for defective contact plugs during the manufacturing of semiconductor integrated circuits. The plugs form a part of the overall electrical connection to the transistors. These plugs can fail to make adequate electrical contact to the underlying circuitry. They may also be connected to faulty circuits. As a result, the voltage from such defective plugs evolves differently upon irradiation by an electron beam. The paths of the secondary electrons emitted from a defective plug respond to this voltage, thereby modifying the fraction of the emitted current that reaches a detector as compared to the fraction obtained from a healthy contact plug. This paper analyzes the fundamental kinetics that ultimately produces this contrast in a scanning electron microscope designed for wafer inspection. In particular, the paper investigates the kinetics of secondary electron emission from an isolated, biased plug embedded in a charge-neutral dielectric. It presents analytic models for the dependence of the electron collection efficiency with the plug voltage and an applied vertical field at the wafer. The analytic results are compared with those from numerical simulations to test the assumptions that enter the models. The mathematical derivations may ultimately be used to estimate the signal that can be extracted from plugs at dissimilar potentials.

Shadman, K.; De, I.

2007-03-01

412

Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment  

NASA Technical Reports Server (NTRS)

Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

1998-01-01

413

Planar lightwave circuit platform with coplanar waveguide for opto-electronic hybrid integration  

Microsoft Academic Search

We propose a planar lightwave circuit (PLC) platform constructed on a silica-on-terraced-silicon (STS) substrate for opto-electronic hybrid integration. This platform consists of an embedded silica PLC region, a terraced silicon region for optical device assembly, and a high-speed electrical circuit region. In the electrical circuit region, the coplanar waveguides (CPW) are prepared on a thick-silica\\/silicon substrate. This structure reduces the

S. Mono; K. Yoshino; Y. Yamada; T. Terui; M. Yasu; K. Moriwaki

1995-01-01

414

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator  

Microsoft Academic Search

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with VTH=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum

Chi Yat Leung; Philip K. T. Mok; Ka Nang Leung; Mansun Chan

2005-01-01

415

Method for producing a hybridization of detector array and integrated circuit for readout  

NASA Technical Reports Server (NTRS)

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Fossum, Eric R. (inventor); Grunthaner, Frank J. (inventor)

1993-01-01

416

Preliminary specification File under Integrated Circuits, IC11  

E-print Network

linear or Pulse Width Modulation (PWM) spindle mode · Provide spindle active dynamic braking mode. Voice · Brake after park circuitry. Power monitor and retract circuit · +5 V and +12 V power monitor threshold warning circuit · Output active 15 °C before general thermal shutdown. APPLICATIONS · Hard disk drive

Ida, Nathan

417

Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section  

E-print Network

circuits offer exceptional radiation hardness. For automotive or geological applications, GaAs can work in wide temperature ranges between -200°C and +200°C and with improved fabrication up to 400°C. Ga layered crystal wafer by a Molecular Beam Epitaxy (MBE) process. This limits the type of circuit

418

Aerosol-Jet-Printed, 1 Volt HBridge Drive Circuit on Plastic with Integrated Electrochromic Pixel  

E-print Network

for the field of organic electronics.1-5 Printing is an additive processing operation in which valuableAerosol-Jet-Printed, 1 Volt HBridge Drive Circuit on Plastic with Integrated Electrochromic Pixel, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer

Kim, Chris H.

419

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement  

ERIC Educational Resources Information Center

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

420

Rapid design and fabrication of new photonic integrated circuits for lightwave systems  

Microsoft Academic Search

In this paper we will review our efforts in developing both design and fabrication capabilities for photonic integrated circuits. Design is based on software for CAD and beam propagation simulation of planar waveguide circuits. Fabrication is based on a laser-based rapid prototyping system for patterning and processing waveguide materials.

Robert Scarmozzino; Richard M. Osgood; Louay Eldada; Martin Hu; John Huang; David S. Levy; Peter Marbach; Miguel Levy

1995-01-01

421

Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview  

Microsoft Academic Search

This paper is an overview of the concepts and methodologies used to predict soft-error rates (SER) due to cosmic and high-energy particle radiation in integrated circuit chips. The paper emphasizes the need for the SER simulation using the actual chip circuit model which includes device, process, and technology parameters as opposed to using either the discrete device simulation or generic

G. R. Srinivasan

1996-01-01

422

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.  

PubMed

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (?) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of ? ? 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. PMID:23761043

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

423

A new pixel level digital read out integrated circuits for ultraviolet imaging sensors  

NASA Astrophysics Data System (ADS)

The ultraviolet imaging sensors consist of two important parts: the array of detectors and the read out integrated circuits. Along with the demand for the fine resolution, large input dynamic range and high integration degree of the imaging sensors, the functions of read out integrated circuits are becoming more and more important. The on chip analog to digital conversion is the main directions of research on this area. In this paper, we presented a new digital read out integrated circuits for ultraviolet imaging sensors. The proposed circuits have an analog to digital converter in each pixel, which enable the parallel analog to digital conversion of the whole pixel array. The developed circuits have a 50um×50um pixel area with a 128×128 size, and are designed in a 0.35um four metal double poly mixed signal CMOS process. The simulation results show that the designed analog to digital converter has an accuracy of 0.2mV and can achieve the dynamic range of 88dB. The proposed circuits realize the low noise and high speed digital output of read out integrated circuits for ultraviolet imaging sensors.

Xu, Bin; Lan, Tian-yi; Yuan, Yong-gang; Li, Xiang-yang

2014-11-01

424

Highly stable amorphous silicon thin film transistors and integration approaches for reliable organic light emitting diode displays on clear plastic  

Microsoft Academic Search

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are currently in widespread production for integration with liquid crystals as driver devices. Liquid crystal displays are driven in AC with very low duty cycles and therefore fairly insensitive to the TFT threshold voltage rise which is well-known in a-Si:H devices. Organic light-emitting diodes (OLEDs) are a future technology choice for flexible displays

Bahman Hekmatshoar

2010-01-01

425

High-speed silicon electro-optic modulator for electronic photonic integrated circuits  

E-print Network

The development of future electronic-photonic integrated circuits (EPIC) based on silicon technology critically depends on the availability of CMOS-compatible high-speed modulators that enable the interaction of electronic ...

Gan, Fuwan

2007-01-01

426

Thermal and Optical Characterization of Photonic Integrated Circuits by Thermoreflectance Microscopy  

E-print Network

We report high resolution, non-invasive, thermal and optical characterization of semiconductor optical amplifiers (SOAs) and SOA-based photonic integrated circuits (PICs) using thermoreflectance microscopy. Chip-scale ...

Hudgings, Janice A.

427

A Top-down, Constraint-driven Design Methodology For Analog Integrated Circuits  

Microsoft Academic Search

We describe a top-down, constraint-driven design methodology for Analog Circuits. We delineate some of the tools that support it. Finally, we conclude with examples to better illustrate tlie methodology and its integration with the tool set.

H. Chang; A. Sangiovanlli-Vincentelli; F. Balarin; E. Charbon; U. Choudhury; G. Jusuf; E. Liu; E. Malavasi; R. Neff; P. R. Gray

1992-01-01

428

Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications  

E-print Network

Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade ...

Fariborzi, Hossein

2013-01-01

429

Characterization and modeling of plasma etch pattern dependencies in integrated circuits  

E-print Network

A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent ...

Abrokwah, Kwaku O

2006-01-01

430

GeSi photodetectors and electro-absorption modulators for Si electronic-photonic integrated circuits  

E-print Network

The silicon electronic-photonic integrated circuit (EPIC) has emerged as a promising technology to break through the interconnect bottlenecks in telecommunications and on-chip interconnects. High performance photonic ...

Liu, Jifeng, Ph. D. Massachusetts Institute of Technology

2007-01-01

431

Stresa, Italy, 25-27 April 2007 AN INTEGRATED CIRCUIT COMPATIBLE COMPACT PACKAGE FOR THERMAL GAS  

E-print Network

micrometric heaters and temperature probes. The package is based on a Polymethyl-Methacrylate (PMMA) adapter packages for integrated circuits is possible. The result of tests performed in nitrogen demonstrates [12] made up of a heater placed bet

Paris-Sud XI, Université de

432

Genetically Increased Cell-Intrinsic Excitability Enhances Neuronal Integration into Adult Brain Circuits  

E-print Network

New neurons are added to the adult brain throughout life, but only half ultimately integrate into existing circuits. Sensory experience is an important regulator of the selection of new neurons but it remains unknown whether ...

Lin, Chia-Wei

433

Broad Beam and Ion Microprobe Studies of Single-Event Upsets in High Speed 0.18micron Silicon Germanium Heterojunction Bipolar Transistors and Circuits  

NASA Technical Reports Server (NTRS)

SiGe based technology is widely recognized for its tremendous potential to impact the high speed microelectronic industry, and therefore the space industry, by monolithic incorporation of low power complementary logic with extremely high speed SiGe Heterojunction Bipolar Transistor (HBT) logic. A variety of studies have examined the ionizing dose, displacement damage and single event characteristics, and are reported. Accessibility to SiGe through an increasing number of manufacturers adds to the importance of understanding its intrinsic radiation characteristics, and in particular the single event effect (SEE) characteristics of the high bandwidth HBT based circuits. IBM is now manufacturing in its 3rd generation of their commercial SiGe processes, and access is currently available to the first two generations (known as and 6HP) through the MOSIS shared mask services with anticipated future release of the latest (7HP) process. The 5 HP process is described and is characterized by a emitter spacing of 0.5 micron and a cutoff frequency ff of 50 GHz, whereas the fully scaled 7HP HBT employs a 0.18 micron emitter and has an fT of 120 GHz. Previous investigations have the examined SEE response of 5 HP HBT circuits through both circuit testing and modeling. Charge collection modeling studies in the 5 H P process have also been conducted, but to date no measurements have been reported of charge collection in any SiGe HBT structures. Nor have circuit models for charge collection been developed in any version other than the 5 HP HBT structure. Our investigation reports the first indications of both charge collection and circuit response in IBM s 7HP-based SiGe process. We compare broad beam heavy ion SEU test results in a fully function Pseudo-Random Number (PRN) sequence generator up to frequencies of 12 Gbps versus effective LET, and also report proton test results in the same circuit. In addition, we examine the charge collection characteristics of individual 7HP HBT structures and map out the spatial sensitivities using the Sandia Focused Heavy Ion Microprobe Facility s Ion Beam Induced Charge Collection (IBICC) technique. Combining the two data sets offers insights into the charge collection mechanisms responsible for circuit level response and provides the first insights into the SEE characteristics of this latest version of IBM s commercial SiGe process.

Reed, Robert A.; Marshall, Paul W.; Pickel, Jim; Carts, Martin A.; Irwin, TIm; Niu, Guofu; Cressler, John; Krithivasan, Ramkumar; Fritz, Karl; Riggs, Pam

2003-01-01

434

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed  

NASA Technical Reports Server (NTRS)

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Ponchak, George E.

2002-01-01

435

Laser micromachining of active and passive photonic integrated circuits  

E-print Network

This thesis describes the development of advanced laser resonators and applications of laser-induced micromachining for photonic circuit fabrication. Two major advantages of laser-induced micromachining are direct patterning ...

Cho, Seong-Ho, 1966-

2004-01-01

436

A time-delay-integration CMOS readout circuit for IR scanning  

Microsoft Academic Search

This paper presents a CMOS readout circuit for an infrared focal plane arrays (FPA). The time delay and integration (TDI) technique is applied to increase the integration time and the signal-to-noise ratio of the readout circuit. By detecting the impedance of the photovoltaic mercury cadmium telluride (HgCdTe-MCT) photodiodes, the faulty photodiodes can be detected. Then the photocurrent at the faulty

Fu-Kai Tsai; Hong-Yi Huang; Li-Kuo Dai; Cheng-Der Chiang; Ping-Kuo Weng; Yung-Chung Chin

2002-01-01

437

Integrated circuit mask generation using a raster scanned laser trimming system  

E-print Network

INTEGRATED CIRCUIT MASK GENERATION USING A RASTER SCANNED LASER TRIMMING SYSTEM A Thesis by KEVIN DWAYNE GOURLEY Submitted to the Graduate College of Texas AA M University in partial fulfillment of the requirement for the degree of MASTER... OF SCIENCE May 1982 Major Subject: Electrical Engineering INTEGRATED CIRCUIT MASK GENERATION USING A RASTER SCANNED LASER TRIMMING SYSTEM A Thesis by KEVIN DWAYNE GOURLEY Approved as to style and content by: hair ma ommittee Dr . Dou as M. Green 4...

Gourley, Kevin Dwayne

1982-01-01

438

A control and signal Processing integrated circuit for the JPL-boeing micromachined gyroscopes  

Microsoft Academic Search

A special-purpose integrated circuit that accomplishes the real-time control and filtering tasks for the JPL-Boeing micromachined gyroscopes using a flexible, low-power implementation is presented. Our exposition focuses on the integration of the circuit and a prototype sensor, the synthesis and implementation of the control filters, and the subsequent performance of the closed-loop system. Identified sensor models are also presented because

Yen-Cheng Chen; Robert T. M'Closkey; Tuan A. Tran; Brent Blaes

2005-01-01

439

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET  

PubMed Central

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

2012-01-01

440

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.  

PubMed

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-01-01

441

The stabilized supralinear network: a unifying circuit motif underlying multi-input integration in sensory cortex.  

PubMed

Neurons in sensory cortex integrate multiple influences to parse objects and support perception. Across multiple cortical areas, integration is characterized by two neuronal response properties: (1) surround suppression--modulatory contextual stimuli suppress responses to driving stimuli; and (2) "normalization"--responses to multiple driving stimuli add sublinearly. These depend on input strength: for weak driving stimuli, contextual influences facilitate or more weakly suppress and summation becomes linear or supralinear. Understanding the circuit operations underlying integration is critical to understanding cortical function and disease. We present a simple, general theory. A wealth of integrative properties, including the above, emerge robustly from four cortical circuit properties: (1) supralinear neuronal input/output functions; (2) sufficiently strong recurrent excitation; (3) feedback inhibition; and (4) simple spatial properties of intracortical connections. Integrative properties emerge dynamically as circuit properties, with excitatory and inhibitory neurons showing similar behaviors. In new recordings in visual cortex, we confirm key model predictions. PMID:25611511

Rubin, Daniel B; Van Hooser, Stephen D; Miller, Kenneth D

2015-01-21

442

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth  

NASA Astrophysics Data System (ADS)

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 ?m CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

443

Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics  

E-print Network

In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. ...

Chung, Jinwook W. (Jinwook Will)

2011-01-01

444

Investigation of hot carrier effects on RF CMOS integrated circuits  

Microsoft Academic Search

With the continual down-scaling of the channel length of MOSFETs, CMOS technology is being increasingly used for the implementation of radio frequency (RF) circuits and systems. However, with technological scale down of dimensions, the supply voltage is not reduced in the same proportion as the channel length, leading to the presence of strong electric fields in the device. Carriers which

Sasan Naseh

2005-01-01

445

Active parallel redundancy for electronic integrator-type control circuits  

NASA Technical Reports Server (NTRS)

Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

Peterson, R. A.

1971-01-01

446

IEEE Communications Magazine February 20022 Distributed Integrated Circuits  

E-print Network

projects and tasks defined at multiple levels of abstraction. This approach has been quite successful spanning architecture, circuits, devices, and electromagnetic levels of abstraction. INTRODUCTION "Divide in an environment where a large number of people with different types and levels of expertise work together

Hajimiri, Ali

447

SEMICONDUCTOR INTEGRATED CIRCUITS: Circuit design of a novel FPGA chip FDP2008  

NASA Astrophysics Data System (ADS)

A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18 ?m CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.

Fang, Wu; Yabin, Wang; Liguang, Chen; Jian, Wang; Jinmei, Lai; Yuan, Wang; Jiarong, Tong

2009-11-01

448

Extreme ultraviolet lithography and three dimensional integrated circuit-A review  

NASA Astrophysics Data System (ADS)

Extreme ultraviolet lithography (EUVL) and three dimensional integrated circuit (3D IC) were thoroughly reviewed. Since proposed in 1988, EUVL obtained intensive studies globally and, after 2000, became the most promising next generation lithography method even though challenges were present in almost all aspects of EUVL technology. Commercial step-and-scan tools for preproduction are installed now with full field capability; however, EUV source power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 200 W in-band power at IF, current tools can supply only approximately 40-55 W. EUVL resist has improved significantly in the last few years, with 13 nm line/space half-pitch resolution being produced with approximately 3-4 nm line width roughness (LWR), but LWR needs 2× improvement. Creating a defect-free EUVL mask is currently an obstacle. Actual adoption of EUVL for 22 nm and beyond technology nodes will depend on the extension of current optical lithography (193 nm immersion lithography, combined with multiple patterning techniques), as well as other methods such as 3D IC. Lithography has been the enabler for IC performance improvement by increasing device density, clock rate, and transistor rate. However, after the turn of the century, IC scaling resulted in short-channel effect, which decreases power efficiency dramatically, so clock frequency almost stopped increasing. Although further IC scaling by lithography reduces gate delay, interconnect delay and memory wall are dominant in determining the IC performance. 3D IC technology is a critical technology today because it offers a reasonable route to further improve IC performance. It increases device density, reduces the interconnect delay, and breaks memory wall with the application of 3D stacking using through silicon via. 3D IC also makes one chip package have more functional diversification than those enhanced only by shrinking the size of the features. The main advantages of 3D IC are the smaller form factor, low energy consumption, high speed, and functional diversification. EUVL, if adopted, will continue to enable IC performance improvement at a slower rate, but 3D IC provides an alternative way to improve the system performance. The best scenario is the adoption of both EUVL and 3D IC. However, the possible further delay of EUVL could enhance the realization of 3D IC for IC system improvement.

Wu, Banqiu; Kumar, Ajay

2014-03-01

449

A correlated nickelate synaptic transistor.  

PubMed

Inspired by biological neural systems, neuromorphic devices may open up new computing paradigms to explore cognition, learning and limits of parallel computation. Here we report the demonstration of a synaptic transistor with SmNiO?, a correlated electron system with insulator-metal transition temperature at 130°C in bulk form. Non-volatile resistance and synaptic multilevel analogue states are demonstrated by control over composition in ionic liquid-gated devices on silicon platforms. The extent of the resistance modulation can be dramatically controlled by the film microstructure. By simulating the time difference between postneuron and preneuron spikes as the input parameter of a gate bias voltage pulse, synaptic spike-timing-dependent plasticity learning behaviour is realized. The extreme sensitivity of electrical properties to defects in correlated oxides may make them a particularly suitable class of materials to realize artificial biological circuits that can be operated at and above room temperature and seamlessly integrated into conventional electronic circuits. PMID:24177330

Shi, Jian; Ha, Sieu D; Zhou, You; Schoofs, Frank; Ramanathan, Shriram

2013-01-01

450

A correlated nickelate synaptic transistor  

NASA Astrophysics Data System (ADS)

Inspired by biological neural systems, neuromorphic devices may open up new computing paradigms to explore cognition, learning and limits of parallel computation. Here we report the demonstration of a synaptic transistor with SmNiO3, a correlated electron system with insulator-metal transition temperature at 130°C in bulk form. Non-volatile resistance and synaptic multilevel analogue states are demonstrated by control over composition in ionic liquid-gated devices on silicon platforms. The extent of the resistance modulation can be dramatically controlled by the film microstructure. By simulating the time difference between postneuron and preneuron spikes as the input parameter of a gate bias voltage pulse, synaptic spike-timing-dependent plasticity learning behaviour is realized. The extreme sensitivity of electrical properties to defects in correlated oxides may make them a particularly suitable class of materials to realize artificial biological circuits that can be operated at and above room temperature and seamlessly integrated into conventional electronic circuits.

Shi, Jian; Ha, Sieu D.; Zhou, You; Schoofs, Frank; Ramanathan, Shriram

2013-10-01

451

Optoelectronic integrated circuits using the InGaAsP\\/InP system  

Microsoft Academic Search

Recent developments in opto-electronic integrated circuits (OEICs) using the InGaAsP\\/InP system which is monolithically integrated with opto-electronic and electronic devices are discussed. The technological problems for the development of the OEICs are explained by reviewing recent developments in OEICs.

Jun Shibata; Takao Kajiwara

1988-01-01

452

Diode-Clamped Multilevel Converters with Integrable Gate-Driver Power-Supply Circuits  

E-print Network

Diode-Clamped Multilevel Converters with Integrable Gate-Driver Power-Supply Circuits S. Busquets integration». Abstract Recent contributions in pulse width modulations (PWM) for multilevel diode and low power applications. Among multilevel topologies, diode-clamped converters are especially

Boyer, Edmond

453

Integrated Printed Circuit Board Device for Cell Lysis and Nucleic Acid Extraction  

E-print Network

Integrated Printed Circuit Board Device for Cell Lysis and Nucleic Acid Extraction Lewis A and an isotachophoresis assay for sample preparation of nucleic acids from biological samples. The device has integrated two 15 L reservoirs. We demonstrated this device by extracting pathogenic nucleic acids from 1 L

Santiago, Juan G.

454

6-1 Research Centers MTL Annual Research Report 2008 Center for Integrated Circuits and Systems  

E-print Network

, Intel, IBM, Linear Technology, Marvell Technology Group, Maxim Integrated Products, Media Tek, National to facilitate communication between MIT faculty and students and industry. We hold two informal technical believe that it will have a lasting impact on the field of integrated circuits and systems. Research

Reif, Rafael

455

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits  

NASA Technical Reports Server (NTRS)

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Buehler, M. G. (inventor)

1985-01-01

456

Local CRH signaling promotes synaptogenesis and circuit integration of adult-born neurons.  

PubMed

Neural activity either enhances or impairs de novo synaptogenesis and circuit integration of neurons, but how this activity is mechanistically relayed in the adult brain is largely unknown. Neuropeptide-expressing interneurons are widespread throughout the brain and are key candidates for conveying neural activity downstream via neuromodulatory pathways that are distinct from classical neurotransmission. With the goal of identifying signaling mechanisms that underlie neuronal circuit integration in the adult brain, we have virally traced local corticotropin-releasing hormone (CRH)-expressing inhibitory interneurons with extensive presynaptic inputs onto new neurons that are continuously integrated into the adult rodent olfactory bulb. Local CRH signaling onto adult-born neurons promotes and/or stabilizes chemical synapses in the olfactory bulb, revealing a neuromodulatory mechanism for continued circuit plasticity, synapse formation, and integration of new neurons in the adult brain. PMID:25199688

Garcia, Isabella; Quast, Kathleen B; Huang, Longwen; Herman, Alexander M; Selever, Jennifer; Deussing, Jan M; Justice, Nicholas J; Arenkiel, Benjamin R

2014-09-29

457

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications  

DOEpatents

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Schwank, James R. (Albuquerque, NM); Shaneyfelt, Marty R. (Albuquerque, NM); Draper, Bruce L. (Albuquerque, NM); Dodd, Paul E. (Tijeras, NM)

2001-01-01

458

Highly stable amorphous silicon thin film transistors and integration approaches for reliable organic light emitting diode displays on clear plastic  

NASA Astrophysics Data System (ADS)

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are currently in widespread production for integration with liquid crystals as driver devices. Liquid crystal displays are driven in AC with very low duty cycles and therefore fairly insensitive to the TFT threshold voltage rise which is well-known in a-Si:H devices. Organic light-emitting diodes (OLEDs) are a future technology choice for flexible displays with several advantages over liquid crystals. In contrast to liquid crystal displays, however, OLEDs are driven in DC and thus far more demanding in terms of the TFT stability requirements. Therefore the conventional thinking has been that a-Si:H TFTs are too unstable for driving OLEDs and the more expensive poly-Si or alternative TFT technologies are required. This thesis defies the conventional thinking by demonstrating that the knowledge of the degradation mechanisms in a-Si:H TFTs may be used to enhance the drive current half-life of a-Si:H TFTs from lower than a month to over 1000 years by modifying the growth conditions of the channel and the gate dielectric. Such high lifetimes suggest that the improved a-Si:H TFTs may qualify for driving OLEDs in commercial products. Taking advantage of industry-standard growth techniques, the improved a-Si:H TFTs offer a low barrier for industry insertion, in stark contrast with alternative technologies which require new infrastructure development. Further support for the practical advantages of a-Si:H TFTs for driving OLEDs is provided by a universal lifetime comparison framework proposed in this work, showing that the lifetime of the improved a-Si:H TFTs is well above those of other TFT technologies reported in the literature. Manufacturing of electronic devices on flexible plastic substrates is highly desirable for reducing the weight of the finished products as well as increasing their ruggedness. In addition, the flexibility of the substrate allows manufacturing bendable, foldable or rollable electronic systems which is not possible with conventional rigid substrates. The most reliable TFTs require a temperature higher than that possible with existing clear flexible plastic substrates. Successful integration of a-Si:H TFTs with OLEDs on new high temperature flexible clear plastic substrates, capable of being processed at 300°C, is presented in this thesis. Controlling the mechanical stress and adhesion of the layers is found to be critical at high process temperatures to avoid cracking and delamination on clear plastic, and TFTs with a lifetime of 100 years on clear plastic have been achieved. In addition, a new "inverted" integration technique is demonstrated both on glass and clear plastic to allow the programming of standard bottom-emission OLEDs with a-Si:H TFTs independent of the OLED characteristics which may change over time and vary from device to device in manufacturing. This technique also enhances the pixel drive current by nearly an order of magnitude for the same programming voltage. Finally, an approach for the design of reliable pixels is presented. Based on the individual TFT and OLED device stability, a guideline to the overall circuit configuration that will provide the most stable light emission is provided.

Hekmatshoar, Bahman

459

GaAs transferred electron devices and field effect transistors in monolithic integrated circuits  

Microsoft Academic Search

Analog-to-digital conversion is being extended to data rates of up to a few giga-samples per second, by advancements in materials, device and process technology. Specific improvements in the material are the result of improved substrate qualification procedures. The primary process improvements include improved annealing and capping for repeatability in ion implantation and selective implantation for reduced contact resistance in ohmic

T. G. Mills

1979-01-01

460

Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth  

NASA Astrophysics Data System (ADS)

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

Tomioka, Katsuhiro; Fukui, Takashi

2014-10-01

461

40 Gb\\/s integrated clock and data recovery circuit in a silicon bipolar technology  

Microsoft Academic Search

An integrated clock and data recovery circuit (CDR) applying the PLL technique has been developed for future optical transmission systems. It is fabricated in a 0.5 ?m\\/50 GHz fT double-polysilicon bipolar technology using only production-like process steps. The circuit operates up to 40 Gb\\/s, which is the highest operating speed to date for this type of IC in a silicon

M. Wurzer; J. Bock; W. Zirwasx; H. Knapp; F. Schumann; A. Felder; L. Treitinger

1998-01-01

462

A circuit method to integrate metamaterial and graphene in absorber design  

NASA Astrophysics Data System (ADS)

We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

2014-10-01

463

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.

1980-01-01

464

Reliability of High Temperature I2L Integrated Circuits  

Microsoft Academic Search

Silicon based I2 L circuits have survived a life test for over 5000 hours at 340°C without degradation. These chips used aluminum metallization with current densities below 10,000 amp\\/sq.cm to avoid electromigration failures. The need for a gold based metal system for high temperature applications has lead to the development of Ti-W diffusion barriers which have withstood temperatures of 360°C

D. C. Dening; D. J. LaCombe; A. Christou

1984-01-01

465

Massively multi-topology sizing of analog integrated circuits  

Microsoft Academic Search

This paper demonstrates a system that performs multi-objective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, MOJITO, which searches through 3500 topologies defined by a hierarchically-organized set of 30 analog blocks. This paper improves MOJITO's results quality via three key extensions. First, it enlarges the block library to enable symmetrical transconductance amplifiers

Pieter Palmers; Trent McConnaghy; Michiel Steyaert; Georges G. E. Gielen

2009-01-01

466

High-Q MEMS for wireless integrated circuits  

Microsoft Academic Search

While integration technology has steadily improved size and performance for wireless baseband circuitry, quality factor and frequency limitations still limit RF front-end circuitry to many large discrete components. Integration solutions for two such RF components are described. Silicon MEMS techniques are used to create self-assembled inductors with reduced losses and improved high frequency characteristics compared with conventional integrated inductors. The

Victor M. Lubecke; Bradley P. Barber; Linus A. Fetter

2001-01-01

467

Extremely bendable, high-performance integrated circuits using semiconducting carbon nanotube networks for digital, analog, and radio-frequency applications.  

PubMed

Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns the organic semiconductor materials. In this work, we report the use of semiconductor-enriched carbon nanotubes for high-performance integrated circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance with on-current and transconductance up to 15 ?A/?m and 4 ?S/?m. By performing capacitance-voltage measurements, the gate capacitance of the nanotube TFT is precisely extracted and the corresponding peak effective device mobility is evaluated to be around 50 cm(2)V(-1)s(-1). Using such devices, digital logic gates including inverters, NAND, and NOR gates with superior bending stability have been demonstrated. Moreover, radio frequency measurements show that cutoff frequency of 170 MHz can be achieved in devices with a relatively long channel length of 4 ?m, which is sufficient for certain wireless communication applications. This proof-of-concept demonstration indicates that our platform can serve as a foundation for scalable, low-cost, high-performance flexible electronics. PMID:22313389

Wang, Chuan; Chien, Jun-Chau; Takei, Kuniharu; Takahashi, Toshitake; Nah, Junghyo; Niknejad, Ali M; Javey, Ali

2012-03-14

468

C. T.-C. Nguyen, "Integrated micromechanical circuits for RF front ends," Proceedings of the 36th European Solid-State Device Research Confer-  

E-print Network

C. T.-C. Nguyen, "Integrated micromechanical circuits for RF front ends," Proceedings of the 36th-16. Integrated Micromechanical Circuits for RF Front Ends Clark T.-C. Nguyen Dept. of Electrical Engineering circuits they enable become larger and more complex, the makings of an integrated micromechanical circuit

Nguyen, Clark T.-C.

469

Method and apparatus for in-system redundant array repair on integrated circuits  

DOEpatents

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

2007-12-18

470

Method and apparatus for in-system redundant array repair on integrated circuits  

DOEpatents

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

2008-07-08

471

An assessment of the impact of the Department of Defense very high speed integrated circuit program  

NASA Astrophysics Data System (ADS)

The technical and economic effects of the Department of Defense's (DoD) development program for very-high-speed integrated circuits (VHSIC) are examined. The probable effects of this program on the domestic aspects and international position of the integrated-circuit (IC) industry as they relate to the interests of the general public and the DoD are considered. The report presents a review of the unique DoD needs that motivate VHSIC research and development; an estimate of the degree of which these needs are likely to be met by the VHSIC program; a discussion of the effects of the program's demands for manpower, materials, and design and processing technologies; the problems connected with the program's technology export controls; and an assessment of the impact of the program on the structure of the U.S. integrated-circuit industry, its continued development and production of civilian consumer products, and its international competitive position.

1982-01-01

472

System-Level Integrated Circuit (SLIC) development for phased array antenna applications  

NASA Technical Reports Server (NTRS)

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

473

Substrate Integrated Circuits (SICs) for Terahertz Electronics and Photonics: Current Status and Future Outlook  

NASA Astrophysics Data System (ADS)

This paper attempts to provide a panoramic picture of research and development of substrate integrated circuits (SICs), presumably the next generation of integrated circuits for GHz and THz electronics and photonics. Current status and future outlook of SICs-related research and development are briefly discussed with focus on THz. WITH interest in low-cost and matured cmos and si-related technologies, we examine the possibility of developing innovative SICs within such platforms. This may be enabled by rapid deployment of through-silicon via (TSV) processes and related 3-D silicon stacking techniques as well as material research progress such as nanostructured techniques in this way, SICs may allow us to anticipate and extrapolate the trends of their applications towards the THz frequency range where no tangible integrated circuits technology is available yet to date. Challenging issues and future directions are considered, pointing to a potentially cost-effective and performance-promising ICs solution for mass commercial applications.

Wu, Ke

2011-09-01

474

Photonic crystal ring resonator based optical filters for photonic integrated circuits  

NASA Astrophysics Data System (ADS)

In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 ?m × 11.4 ?m which is highly suitable of photonic integrated circuits.

Robinson, S.

2014-10-01

475

Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits  

DOEpatents

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

Campbell, Ann. N. (13170-B Central SE #188, Albuquerque, NM 87123); Anderson, Richard E. (2800 Tennessee NE, Albuquerque, NM 87110); Cole, Jr., Edward I. (2116 White Cloud NE, Albuquerque, NM 87112)

1995-01-01

476

Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits  

DOEpatents

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits are disclosed. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits. 17 figs.

Campbell, A.N.; Anderson, R.E.; Cole, E.I. Jr.

1995-11-07

477

Photonic crystal ring resonator based optical filters for photonic integrated circuits  

SciTech Connect

In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 ?m × 11.4 ?m which is highly suitable of photonic integrated circuits.

Robinson, S., E-mail: mail2robinson@gmail.com [Department of Electronics and Communication Engineering, Mount Zion College of Engineering and Technology, Pudukkottai-622507, Tamil Nadu (India)

2014-10-15

478

Molten-Caustic-Leaching (MCL or Gravimelt) System Integration Project. Topical report for test circuit operation  

SciTech Connect

This is a report of the results obtained from the operation of an integrated test circuit for the Molten-Caustic-Leaching (MCL or Gravimelt) process for the desulfurization and demineralization of coal. The objectives of operational testing of the 20 pounds of coal per hour integrated MCL test circuit are: (1) to demonstrate the technical capability of the process for producing a demineralized and desulfurized coal that meets New Source Performance Standards (NSPS); (2) to determine the range of effective process operation; (3) to test process conditions aimed at significantly lower costs; and (4) to deliver product coal.

Not Available

1990-11-01

479

Sleep Transistor Sizing and Control for Resonant Supply  

E-print Network

1 Sleep Transistor Sizing and Control for Resonant Supply Noise Damping Jie Gu, Hanyong Eom@ece.umn.edu www.umn.edu/~chriskim/ #12;2 Outline · Introduction · Conventional Sizing of Sleep Transistors · Sleep Transistor Sizing Considering Resonant Supply Damping · Adaptive Sleep Transistor Circuit · Conclusions #12

Kim, Chris H.

480

Self-protecting transistor oscillator for treating animal tissues  

DOEpatents

A transistor oscillator circuit wherein the load current applied to animal tissue treatment electrodes is fed back to the transistor. Removal of load is sensed to automatically remove feedback and stop oscillations. A thermistor on one treatment electrode senses temperature, and by means of a control circuit controls oscillator transistor current.

Doss, James D. (Los Alamos, NM)

1980-01-01

481

Circuits Archive  

NSDL National Science Digital Library

A database for electrical engineering students and professionals, the Circuits Archive provides diagrams of radio, computer, and other miscellaneous circuits (ASCII, .gif, and HTML formats). The archive is just one part of this metasite housed at the University of Washington's Electrical Engineering site. In addition to the circuit diagrams, a searchable database of transistor cross-references, a component reference page (both in the Data Sheets section), and links to models and microprocessors are featured. Other useful tools included are the Reading Capacitors page and links to software sites. Diagrams and links are voluntarily contributed and seem to be updated regularly. Note: the site includes a page on software in the Circuits Archive.

482

Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies  

E-print Network

Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and ...

del Alamo, Jesus A.

483

Benchmarking nanotechnology for high-performance and low-power logic transistor applications  

Microsoft Academic Search

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronics applications. In particular, several novel nanoelectronic devices such as carbon-nanotube field effect transistor (FET), Si nanowire FET, and planar III-V compound semiconductor FET, all hold promise as device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending

Robert Chau

2004-01-01

484

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits  

NASA Technical Reports Server (NTRS)

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

1991-01-01

485

New dynamic FET logic and serial memory circuits for VLSI GaAs technology  

NASA Technical Reports Server (NTRS)

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of