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1

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits  

Microsoft Academic Search

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers

Laleh Rabieirad; Edgar J. Martinez; Saeed Mohammadi

2009-01-01

2

Integrated circuits based on bilayer MoS? transistors.  

PubMed

Two-dimensional (2D) materials, such as molybdenum disulfide (MoS(2)), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS(2) allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene's advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS(2) show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS(2) to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between 2 to 12 transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS(2). Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions. PMID:22862813

Wang, Han; Yu, Lili; Lee, Yi-Hsien; Shi, Yumeng; Hsu, Allen; Chin, Matthew L; Li, Lain-Jong; Dubey, Madan; Kong, Jing; Palacios, Tomas

2012-09-12

3

Gigahertz flexible graphene transistors for microwave integrated circuits.  

PubMed

Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations. PMID:25062282

Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

2014-08-26

4

CMOS-based carbon nanotube pass-transistor logic integrated circuits  

PubMed Central

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

5

CMOS-based carbon nanotube pass-transistor logic integrated circuits.  

PubMed

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

6

Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board  

NASA Technical Reports Server (NTRS)

Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

Seaward, R. C.

1967-01-01

7

Organic field-effect transistors and all-polymer integrated circuits  

Microsoft Academic Search

Electrical properties of field-effect transistors made of different solution processable organic semiconductors are described. The temperature and gate-voltage dependence of the mobility is shown and theoretically described using a model based on the variable-range hopping of charge carriers in an exponential density of states. Furthermore, a technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of

M. Matters; D. M. de Leeuw; M. J. C. M. Vissenberg; C. M. Hart; P. T. Herwig; T. Geuns; C. M. J. Mutsaers; C. J. Drury

1999-01-01

8

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker  

Microsoft Academic Search

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f? complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination.

I. Kipnis; H. Spieler; T. Collins

1994-01-01

9

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates  

NASA Astrophysics Data System (ADS)

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports pentacene organic thin film transistors fabricated on flexible polymeric substrates with record performance, the fastest photolithographically patterned organic TFT integrated circuits on polymeric substrates reported to date, and the fabrication of the organic TFT backplanes used to build the first organic TFT-driven active matrix liquid crystal display (AMLCD), also the first AMLCD on a flexible substrate, ever reported. In addition, the first investigation of functionalized pentacene derivatives used as the active layer in organic thin film transistors is reported. A low temperature (<110°C) process technology was developed allowing the fabrication of high performance organic TFTs, integrated circuits, and large TFT arrays on flexible polymeric substrates. This process includes the development of a novel water-based photolithographic active layer patterning process using polyvinyl alcohol that allows the patterning of organic semiconductor materials for elimination of active layer leakage current without causing device degradation. The small molecule aromatic hydrocarbon pentacene was used as the active layer material to fabricate organic TFTs on the polymeric material polyethylene naphthalate with field-effect mobility as large as 2.1 cm2/V-s and on/off current ratio of 108. These are the best values reported for organic TFTs on polymeric substrates and comparable to organic TFTs on rigid substrates. Analog and digital integrated circuits were also fabricated on polymeric substrates using pentacene TFTs with propagation delay as low as 38 musec and clocked digital circuits that operated at 1.1 kHz. These are the fastest photolithographically patterned organic TFT circuits on polymeric substrates reported to date. Finally, 16 x 16 pentacene TFT pixel arrays were fabricated on polymeric substrates and integrated with polymer dispersed liquid crystal to build an AMLCD. The pixel arrays showed good optical response to changing data signals when standard quarter-VGA display waveforms were applied. This result marks the first organic TFT-driven active matrix liquid crystal display ever reported as well as the first active matrix liquid crystal display on a flexible polymeric substrate. Lastly, functionalized pentacene derivatives were used as the active layer in organic thin film transistor materials. Functional groups were added to the pentacene molecule to influence the molecular ordering so that the amount of pi-orbital overlap would be increased allowing the potential for improved field-effect mobility. The functionalization of these materials also improves solubility allowing for the possibility of solution-processed devices and increased oxidative stability. Organic thin film transistors were fabricated using five different functionalized pentacene active layers. Devices based on the pentacene derivative triisopropylsilyl pentacene were found to have the best performance with field-effect mobility as large as 0.4 cm 2/V-s.

Sheraw, Christopher Duncan

2003-10-01

10

Improved methods of forming monolithic integrated circuits having complementary bipolar transistors  

NASA Technical Reports Server (NTRS)

Two new processes form complementary transistors in monolithic semiconductor circuits, require fewer steps /infusions/ than previous methods, and eliminate such problems as nonuniform h sub FE distribution, low yield, and large device formation.

Bohannon, R. O., Jr.; Cashion, W. F.; Stehlin, R. A.

1971-01-01

11

Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies  

SciTech Connect

Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q. [Sandia National Labs., Albuquerque, NM (United States); Enquist, P.M. [Research Triangle Inst., Research Triangle Park, NC (United States)

1995-12-31

12

Logic circuit function realization by one transistor.  

PubMed

Bottom-up nanowires are very attractive building blocks for functional devices due to their controllable properties. Meanwhile, assembling nanowires into large-scale integrated circuits is a daunting challenge because for the present circuits diverse nanowires are needed to grow simultaneously together closely. Here, a nanowire trigate transistor structure is proposed which can accomplish the functions of the logic gate circuits. By adding one channel-electrode junction as the output, this interesting one-channel structure is used to realize inverter and OR logic gates. In this way, logic circuits could shrink into a single transistor. PMID:23075033

Dai, Mingzhi; Dai, Ning

2012-11-14

13

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker  

SciTech Connect

Since 1989 the Solenoidal Detector Collaboration (SDC) has been developing a general purpose detector to be operated at the Superconducting Super Collider (SSC). A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDS silicon tracker. The IC was designed and tested at LBL and was fabricated using AT and T's CBIC-U2, 4 GHz f[sub T] complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 [mu]m pitch double-sided silicon strip detector. The chip measures 6.8 mm [times] 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a [phi] = 10[sup 14] protons/cm[sup 2] have been performed on the JC, demonstrating the radiation hardness of the complementary bipolar process.

Kipnis, I.; Spieler, H.; Collins, T. (Lawrence Berkeley Lab., CA (United States))

1994-08-01

14

Development of high-performance printed organic field-effect transistors and integrated circuits.  

PubMed

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications. PMID:25057765

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2014-07-24

15

Improved chopper circuit uses parallel transistors  

NASA Technical Reports Server (NTRS)

Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage.

1966-01-01

16

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide  

NASA Astrophysics Data System (ADS)

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

Liang, Shibo; Zhang, Zhiyong; Si, Jia; Zhong, Donglai; Peng, Lian-Mao

2014-08-01

17

Evolvable circuit with transistor-level reconfigurability  

NASA Technical Reports Server (NTRS)

An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

2004-01-01

18

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out  

Microsoft Academic Search

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

2008-01-01

19

Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors  

SciTech Connect

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Blalock, Benjamin J [ORNL; Islam, Syed K [ORNL

2010-01-01

20

Fabrication of Thin-Film Transistor Integrated Circuits on Flexible Substrate by Transfer Technique of Carbon Nanotube Network Using Poly(vinyl alcohol)  

NASA Astrophysics Data System (ADS)

Flexible integrated circuits consisting of carbon nanotube thin-film transistors (CNTTFTs) were fabricated on a poly(ethylene naphthalate) (PEN) substrate by the transfer technique of the CNT network. The CNT network grown on a SiO2/p+-Si substrate by plasma-enhanced chemical vapor deposition was transferred onto the PEN substrate using poly(vinyl alcohol) (PVA). A delay time of 1.1 µs/gate was realized for the ring oscillator with a channel length of 10 µm. The present delay time is the best ever reported to our knowledge among CNTTFT flexible integrated circuits using transferred or printed CNT networks.

Ishii, Satoshi; Nishu, Mamoru; Kishimoto, Shigeru; Mizutani, Takashi

2013-10-01

21

THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development,  

E-print Network

THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit-gain cutoff frequencies of 1-3 THz. High bandwidths are obtained by scaling; the critical limits for the 64 nm scaling geneation (1 THz f, 2 THz fmax) have been developed. We here examine the high

Rodwell, Mark J. W.

22

Computer-aided identification of complete constitution model of transistor structure for design of subnanosecond large-scale-integrated circuits  

NASA Astrophysics Data System (ADS)

Conputer programs were developed for two dimensional modeling of transistor structures with planar contact configuration in order to facilitate the design of LSI circuits with minimization of geometrical dimensions and identification of static and dynamic electrical characteristics throughout the technological process. These programs, TRAN 2 and TRAN 2M, are concerned with a transistor not only in the normal active mode but also in inversion and saturation states. Another specific application is subnanosecond LSI of emitter coupled logic in the unsaturated state. Electron and hole concentrations as variable in the TRAN 2 program were replaced with the exponents of electron and hole Fermi quasi potentials, which symmetrizes with diagnol predominance the matrices of discretized continuity equations and thus facilitates the solution of the latter. Both programs yield all necessary current-voltage and capacitance-voltage characteristics as well as the dependence of the collector-emitter time constant and of the current transfer ratio on the collector voltage.

Bubennikov, A. N.; Sadovnikov, A. D.

1985-03-01

23

Transistor Characteristics for Direct-Coupled Transistor Logic Circuits  

Microsoft Academic Search

The basic requirement for stability of a direct-coupled transistor logic (dctl) circuit is that a voltage margin exist between the maximum collect-emitter voltage of an ``on'' unit in the system environment and the minimum base-emitter voltage required for a transistor to be sufficiently ``off.'' This margin has been expressed in terms of the fundamental device parameters: commonbase forward and inverse

James W. Easley

1958-01-01

24

Field-effect transistor replaces bulky transformer in analog-gate circuit  

NASA Technical Reports Server (NTRS)

Metal-oxide semiconductor field-effect transistor /MOSFET/ analog-gate circuit adapts well to integrated circuits. It provides better system isolation than a transformer, while size and weight are appreciably reduced.

1965-01-01

25

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.  

SciTech Connect

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

2008-08-01

26

Thermionic integrated circuits  

SciTech Connect

Thermionic integrated circuits combine vacuum-tube technology with integrated-circuit techniques to form integrated vacuum circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

MacRoberts, M.; Brown, D.R.; Dooley, R.; Lemons, R.; Lynn, D.; McCormick, B.; Mombourquette, C.; Sinah, D.

1986-01-01

27

Modeling and simulation of insulated-gate field-effect transistor switching circuits  

Microsoft Academic Search

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET

HAROLD SHICHMAN; DAVID A. HODGES

1968-01-01

28

Displacement Damage in Bipolar Linear Integrated Circuits  

NASA Technical Reports Server (NTRS)

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Rax, B. G.; Johnston, A. H.; Miyahira, T.

2000-01-01

29

High-Resolution Inkjet Printing of All-Polymer Transistor Circuits  

Microsoft Academic Search

Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and

H. Sirringhaus; T. Kawase; R. H. Friend; T. Shimoda; M. Inbasekaran; W. Wu; E. P. Woo

2000-01-01

30

STABILITY OF AMORPHOUS SILICON THIN FILM TRANSISTORS AND CIRCUITS  

E-print Network

STABILITY OF AMORPHOUS SILICON THIN FILM TRANSISTORS AND CIRCUITS Ting Liu A DISSERTATION PRESENTED by Ting Liu. All rights reserved #12;Abstract i Hydrogenated amorphous silicon thin-film transistors (a to the breaking of weak bonds in the amorphous silicon. It can be modeled with a "unified stretched exponential

31

Testing tri-state and pass transistor circuit structures  

E-print Network

effort for tristate and pass transistor structures. We do circuit level modeling to help develop and validate gate level models, which can be used in production ATPG. We study the two primary effects of interest, capacitive coupling and leakage...

Parikh, Shaishav Shailesh

2005-11-01

32

New DT(sup)2L system of large-scale integrated circuit described  

Microsoft Academic Search

A simplified gate circuit and trigger is presented based on existing transistor-transistor logic (TTL) circuits to create a new series. It is not only suited to China's existing technological level and package cooling technology, but also improves integration and speed and provides experimental proposals for developing China's own medium and large scale integrated circuit series.

Y. Li

1986-01-01

33

Integration of Cell Membranes and Nanotube Transistors  

E-print Network

Integration of Cell Membranes and Nanotube Transistors Keith Bradley, Alona Davis, Jean. As the nanoelectronic device, we use a nanotube network transistor, which incorporates many individual nanotubes as transistors, and that the two systems interact. Further, we use the interaction to study the charge

Gruner, George

34

Integrated Circuits Laboratory  

NSDL National Science Digital Library

The Integrated Circuits Laboratory is software that is devoted to helping understand the processing of semiconductor materials. Manufacturing an IC involves a complex interaction of several highly developed technologies. This software is used to fabricate high-performance integrated circuits. In such areas as oxidation, diffusion, Ion implantation, Chemical etching, Photolithography, CVD, Ellipsometer, Plasma etching and Aluminum deposition. IC Lab software offers virtual opportunities to simulate the process of manufacturing a integrated circuit without going into a clean room. All the simulations represent processing steps that are as accurate as possible. This was part of the Learning Invention Labs that MATEC held. Visit the MATEC.org homepage for more information.

Lindor, Felicia

2013-01-01

35

Parallel transistor level circuit simulation using domain decomposition methods  

Microsoft Academic Search

This paper presents an efficient parallel transistor level full-chip circuit simulation tool with SPICE-accuracy. The new approach partitions the circuit into a linear domain and several non-linear domains based on circuit non-linearity and connectivity. The linear domain is solved by parallel fast linear solver while nonlinear domains are parallelly distributed into different processors and solved by direct solver. Parallel domain

He Peng; Chung-kuan Cheng

2009-01-01

36

A breakdown model for the bipolar transistor to be used with circuit simulators  

SciTech Connect

A breakdown model for the output characteristics of the bipolar transistor (bjt) has been developed. The behavioral modeling capability of PSPICE, a popular SPICE program (with Emphasis on Integrated circuits) was used to implement the macromodel. The model predicts bjt output characteristics under breakdown conditions. Experimental data was obtained to verify the macromodel. Good agreement exits between the measured and the simulated results.

Keshavarz, A.A. [Alliance Technologies, Inc., Albuquerque, NM (United States); Raney, C.W.; Campbell, D.C. [Sandia National Labs., Albuquerque, NM (United States)

1993-08-01

37

Heterogeneous photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Photonic Integrated Circuits (PICs) have been dichotomized into circuits with high passive content (silica and silicon PLCs) and high active content (InP tunable lasers and transceivers) due to the trade-off in material characteristics used within these two classes. This has led to restrictions in the adoption of PICs to systems in which only one of the two classes of circuits are required to be made on a singular chip. Much work has been done to create convergence in these two classes by either engineering the materials to achieve the functionality of both device types on a single platform, or in epitaxial growth techniques to transfer one material to the next, but have yet to demonstrate performance equal to that of components fabricated in their native substrates. Advances in waferbonding techniques have led to a new class of heterogeneously integrated photonic circuits that allow for the concurrent use of active and passive materials within a photonic circuit, realizing components on a transferred substrate that have equivalent performance as their native substrate. In this talk, we review and compare advances made in heterogeneous integration along with demonstrations of components and circuits enabled by this technology.

Fang, Alexander W.; Fish, Gregory; Hall, Eric

2012-01-01

38

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature  

NASA Technical Reports Server (NTRS)

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

39

GaAs Optoelectronic Integrated-Circuit Neurons  

NASA Technical Reports Server (NTRS)

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

40

6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design  

E-print Network

6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design Prof. Joel L;6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design Prof. Joel L. Dawson Page 2's move on to the matter of biasing a transistor circuit. What does this mean, and what constitutes a good

Goldwasser, Shafi

41

6.301 Solid State Circuits Recitation 3: AC Coupling, and Single-Transistor Amplifiers  

E-print Network

6.301 Solid State Circuits Recitation 3: AC Coupling, and Single-Transistor Amplifiers Prof. Joel L z1 z2 z3 #12;6.301 Solid State Circuits Recitation 3: AC Coupling, and Single-Transistor Amplifiers + - RL + - V0 #12;6.301 Solid State Circuits Recitation 3: AC Coupling, and Single-Transistor Amplifiers

Goldwasser, Shafi

42

Testing of metal gate PMOS digital integrated circuits  

Microsoft Academic Search

Many universities use the metal gate PMOS process for educational laboratory projects in the fabrication of integrated circuits. A semiconductor parameter analyzer is often used for testing the transistors, resistors and inverters on their test chips. The semiconductor parameter analyzer cannot be used for testing a digital circuit with a large number of inputs and outputs. A low cost digital

Lynn F. Fuller; K. Hoomkwap; S. Shakya; S. Yenrudee

2003-01-01

43

Bioluminescent bioreporter integrated circuit  

DOEpatents

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

2000-01-01

44

Bipolar transistor modeling of avalanche generation for computer circuit simulation  

Microsoft Academic Search

An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.

R. W. Dutton

1975-01-01

45

The Integrated Circuit Game  

NSDL National Science Digital Library

Integrated circuits can be found in almost every modern electrical device; such as computers, cars, television sets, CD players, cell phones, and so on. But what is an integrated circuit and what is the history behind it? Learn about Nobel Laureate Jack Kilby and his part in the invention that is the basis of all modern technology. In the beginning of this game you have to take the quiz consisting of four questions, otherwise you will not be able to move on in this game. The answers to the questions are found in the museum. As "Maria" you walk around in the fantasy town "Techville" in Texas. At some points you have to give the right answers or figure out something before you can move on. You will pass a portal that takes you back in time to Nobel Laureate Jack Kilby's lab in 1958, among other things. The challenge in this game is to make it to the end.

2013-06-20

46

Integrated Circuit Immunity  

NASA Technical Reports Server (NTRS)

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Sketoe, J. G.; Clark, Anthony

2000-01-01

47

Monolithic Optoelectronic Integrated Circuit  

NASA Technical Reports Server (NTRS)

Monolithic optoelectronic integrated circuit (OEIC) receives single digitally modulated input light signal via optical fiber and converts it into 16-channel electrical output signal. Potentially useful in any system in which digital data must be transmitted serially at high rates, then decoded into and used in parallel format at destination. Applications include transmission and decoding of control signals to phase shifters in phased-array antennas and also communication of data between computers and peripheral equipment in local-area networks.

Bhasin, Kul B.; Walters, Wayne; Gustafsen, Jerry; Bendett, Mark

1990-01-01

48

Monolithically integrated bacteriorhodopsin-GaAs field-effect transistor photoreceiver.  

PubMed

We have applied the large photovoltage developed across a layer of selectively deposited bacteriorhodopsin to the gate terminal of a monolithically integrated GaAs-based modulation-doped field-effect transistor, which delivers an amplified photoinduced current signal. The integrated biophotoreceiver device exhibits a responsivity of 3.8 A/W. The optoelectronic integrated circuit is achieved by molecular-beam epitaxy of the field-effect transistor's heterostructure, photolithography, and selective-area bacteriorhodopsin electrodeposition. PMID:18007945

Bhattacharya, Pallab; Xu, Jian; Váró, Gyorgy; Marcy, Duane L; Birge, Robert R

2002-05-15

49

Susceptibility of Integrated Circuits to Electrostatic Discharge  

NASA Astrophysics Data System (ADS)

The components that are considered fairly rugged can be damaged by electrostatic discharge (ESD). Bipolar transistors, the earliest of the solid state amplifiers, are not immune to ESD, though less susceptible. Devices manufactured using metal oxide semiconductor (MOS) technology can be easily damaged due to ESD but some of the newer high speed components can be ruined with as little as 3 volts. The integrated circuits (IC) are susceptible to ESD due to its small size and unavailability of larger area to dissipate the excess energy. The susceptibility of ICís can be determined by various ESD stress tests. The different ESD stress modes on an input or output pin which is Pin-to-VSS, Pin-to-VDD are used to test an IC. The IC after ESD stresses may undergo damage not only in the input/output circuits or devices, but also in the internal circuits. The effects of ESD on various logic gates belonging to both transistor-transistor logic (TTL) and Complementary MOS (CMOS) logic families have been studied. The comparison between TTL and CMOS logic gates reveal that CMOS devices are more susceptible to ESD than TTL devices.

Narendra, Rajashree; Sudheer, M. L.; Pande, D. C.

2012-09-01

50

Integrated circuit cell library  

NASA Technical Reports Server (NTRS)

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

51

High-voltage (100 V) ChipfilmTM single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays  

NASA Astrophysics Data System (ADS)

System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (<10 ?m) substrate. A breakdown voltage of more than 100 volts with drain-to-source saturation current Ids(sat)?85 ?A/?m for N-LDMOS and Ids(sat)?20 ?A/?m for P-LDMOS is predicted through process and device simulations.

Asif, A.; Richter, H.; Burghartz, J. N.

2009-05-01

52

Confinement-modulated junctionless nanowire transistors for logic circuits  

NASA Astrophysics Data System (ADS)

We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices.

Vaurette, François; LeturcqPresent Address: Crp Gabriel Lippmann, Département Science Et Analyse Des Matériaux, 41, Rue Du Brill-4422 Belvaux-Luxembourg., Renaud; Lepilliet, Sylvie; Grandidier, Bruno; Stiévenard, Didier

2014-10-01

53

Atomtronic circuits of diodes and transistors.  

PubMed

We illustrate that open quantum systems composed of neutral, ultracold atoms in one-dimensional optical lattices can exhibit behavior analogous to semiconductor electronic circuits. A correspondence is demonstrated for bosonic atoms, and the experimental requirements to realize these devices are established. The analysis follows from a derivation of a quantum master equation for this general class of open quantum systems. PMID:19905552

Pepino, R A; Cooper, J; Anderson, D Z; Holland, M J

2009-10-01

54

Integrated coherent matter wave circuits  

E-print Network

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then propagate freely in waveguides where they can be switched, divided, recombined, and detected. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. Here we report experiments demonstrating integrated matter wave circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly-moving, tightly-focused laser beam exerts forces on atoms through their electrical polarizability. The source of coherent matter waves is a Bose-Einstein condensate (BEC). We launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These developments open the door to creating arbitrary and dynamic coherent matter wave circuits.

C. Ryu; M. G. Boshier

2014-10-31

55

SiC JFET Transistor Circuit Model for Extreme Temperature Range  

NASA Technical Reports Server (NTRS)

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.

2008-01-01

56

Circuit Theory for Analysis and Design of Spintronic Integrated Circuits  

E-print Network

We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The proposed formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We derive the circuit models for vector spin conduction in non-magnetic and magnetic components. We then propose an extension to the modified nodal analysis for the analysis of spin circuits. We demonstrate the applicability of the proposed theory using an example spin logic circuit.

Manipatruni, Sasikanth; Young, Ian A

2011-01-01

57

A superconductive integrated circuit foundry  

NASA Astrophysics Data System (ADS)

A foundry has been established for production of superconductive integrated circuits, modeled after semiconductor application-specific integrated circuit (IC) production. The foundry supports and improves standardized Nb-based IC processing, and develops advanced processes such as a novel NbN-based process. The authors discuss the operation of the foundry, standardized process technologies, design rules, process flows, in-line product tracking, statistical process control, and automated parametric testing. The advantages of fine-line lithography and a class 10/100 environment are presented. Internal and external customer support with standard layout and circuit design tools enables reliable, quick turnaround production of a wide range of circuits. Finally, the authors present examples of concurrent device and process development towards improved, denser circuits, while maintaining a disciplined foundry environment.

Abelson, L. A.; Thomasson, S. L.; Murduck, J. M.; Elmadjian, R.; Akerling, G.; Kono, R.; Chan, H. W.

1993-03-01

58

Low-cost all-polymer integrated circuits  

Microsoft Academic Search

A technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of field-effect transistors in which the semiconducting, conducting and insulating parts are all made of polymers. The fabrication on flexible substrates uses spin-coating of electrically active precursors and patternwise exposure of the deposited films. In the whole process stack-integrity is maintained. Vertical interconnects are made mechanically.

C. M. Hart; D. M. de Leeuw; M. Matters; P. T. Herwig; C. M. J. Mutsaerts; C. J. Drury

1998-01-01

59

Graphene-Dielectric Integration for Graphene Transistors  

PubMed Central

Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-? dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities. PMID:21278913

Liao, Lei; Duan, Xiangfeng

2010-01-01

60

Radiation hardness test of preamplifier circuits composed of commercial bipolar transistors  

NASA Astrophysics Data System (ADS)

In general, radiation-hardened transistors are very expensive and it is sometimes not easy to acquire proper ones for application. In this study, we designed a front-end electronic circuit for high-rate neutron counters installed in a high-level ?-radiation hot cell. All the transistors adopted for this circuit are not radiation-hardened ones, i.e. commercial ones not specifically processed for a radiation resistance. The aim of our study was to seek more radiation-resistant transistors from among the commercial ones and to verify the radiation hardness of the circuit composed of these transistors. The circuit includes a preamplifier, a comparator, and a monostable multivibrator. To realize the radiation hardness of this circuit with commercial transistors, the transistors were categorized into two groups: general speed and high-speed transistors. After a 100 Mrad irradiation from a 60Co ?-ray source, the reduction of the current gain of the general speed transistors was over 80% and that of the high-speed transistors was below 68%. The signal-to-noise ( S/ N) ratio of the preamplifier output voltage was reduced by 66% for the former and by 36% for the latter.

Lee, Tae-hoon; Kim, Ho-dong

2007-08-01

61

Mouldable all-carbon integrated circuits  

NASA Astrophysics Data System (ADS)

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027cm2V-1s-1 and an ON/OFF ratio of 105. The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Sun, Dong-Ming; Timmermans, Marina Y.; Kaskela, Antti; Nasibulin, Albert G.; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I.; Ohno, Yutaka

2013-08-01

62

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits  

NASA Astrophysics Data System (ADS)

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of ?hin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

Gu, Jian

63

Shielded silicon gate complementary MOS integrated circuit.  

NASA Technical Reports Server (NTRS)

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.; Halsor, J. L.; Hayes, P. J.

1972-01-01

64

Weaving integrated circuits into textiles  

Microsoft Academic Search

In this paper, we present and demonstrate a technology for integrating electronic functionality at the yarn level of woven textiles. The technology principles are compliant with commercial weaving processes and suitable for large scale manufacturing. Thin-film devices, interconnect lines and contact pads are patterned and silicon-based integrated circuits are attached to flexible plastic substrates. The substrates are cut into electronic

Christoph Zysset; Kunigunde Cherenack; Thomas Kinkeldei; G. Troster

2010-01-01

65

Transistorized Marx bank pulse circuit provides voltage multiplication with nanosecond rise-time  

NASA Technical Reports Server (NTRS)

Base-triggered avalanche transistor circuit used in a Marx bank pulser configuration provides voltage multiplication with nanosecond rise-time. The avalanche-mode transistors replace conventional spark gaps in the Marx bank. The delay time from an input signal to the output signal to the output is typically 6 nanoseconds.

Jung, E. A.; Lewis, R. N.

1968-01-01

66

SITCAP -- A simulator of bipolar transistors for computer-aided circuit analysis programs  

Microsoft Academic Search

A fast computer program for the calculation of the para-meterset of circuit models for bipolar transistors, based on processing data, will be presented. Program makes use of a new transport theory permitting accurate current gain prediction.

H. J. DeMan; R. Mertens

1973-01-01

67

High-voltage (100 V) ChipfilmTM single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays  

Microsoft Academic Search

System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage

A. Asif; H. Richter; J. N. Burghartz

2009-01-01

68

Vertically Integrated Circuits at Fermilab  

SciTech Connect

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

2009-01-01

69

Vertically Integrated Circuits at Fermilab  

SciTech Connect

The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

2010-01-01

70

Low-power integrated-circuit driver for ferrite-memory word lines  

NASA Technical Reports Server (NTRS)

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Katz, S.

1970-01-01

71

Thermal macromodelling of integrated circuits  

Microsoft Academic Search

Most of the existing macromodels for integrated circuits (ICs) today have characteristics that are independent of temperature. The macromodels usually assume the IC operates at a fixed temperature, frequently taken to be a defined nominal temperature representing room temperature. This is in spite of the fact that IC characteristics are strongly dependent on the temperature of the device. In this

K. V. Noren; A. Tarakji

2000-01-01

72

Integrated circuit tester using interferometric imaging  

SciTech Connect

An interferometric imaging technique can provide time-resolved diagnostics of semiconductor integrated circuits. The semiconductor device is placed in one arm of an interferometer and illuminated with a picosecond pulse from a sub-bandgap infrared laser. As the laser passes through the semiconductor, it samples local variations in the index of refraction. These variations are caused by a number of physical phenomena including dopants in the material such as those used to form device structures, heating due to the flow of electrical currents, and changes in carrier concentration due to injection. These variations have both static and dynamic components. The dynamic components are associated with the normal device operation and are the most interesting. To separate the components, the device is first imaged in a quiescent state, and then a second image is taken after the device enters a known voltage state. Differences between the two images determine where the local index of refraction has changed and by how much. A third image taken with the reference arm of the interferometer blocked, allows device structures to be associated with particular changes in the index of refraction. Activation of the voltage state is synchronized with the pulsed illumination source, and the time delay between the application of the voltage and the laser probe pulse allows us to take a series of images that map the time evolution of the interferogram. This technique offers an exciting new diagnostic for semiconductor integrated circuits. The technique is noninvasive and compatible with high-speed operation of integrated circuits. The picosecond resolution enables us to either characterize specific logic states or watch an individual device turn on. This imaging technique is sensitive to all of the index of refraction changes that can be associated with IC`s. These include heating due to current flowing through narrow wires and charge injection into the depletion region of a transistor.

Donaldson, W.R.; Michaels, E.M.R.; Akowuah, K. [and others

1997-04-01

73

Self-integration of nanowires into circuits via guided growth  

PubMed Central

The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom–up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel “self-integration” of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

2013-01-01

74

Scalable fabrication of self-aligned graphene transistors and circuits on glass  

PubMed Central

High frequency graphene transistors with the intrinsic cut-off frequency up to 300 gigahertz (GHz) have been demonstrated for radio frequency (RF) applications. However, functional graphene RF circuits such as frequency doublers and mixers operating in the gigahertz range is yet to demonstrated. Here we report a scalable approach to fabricate self-aligned graphene transistors and circuits that can operate in gigahertz regime. The devices are fabricated through a self-aligned aligned process on glass substrate using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows to achieving unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/?m. With the minimization of parasitic capacitance on insulating substrate, the resulting graphene transistors exhibit a record high extrinsic cut-off frequency (> 50 GHz) achieved in graphene transistors to date. The excellent extrinsic cut-off frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1–10 GHz regime, a significant advancement over previous report (~20 MHz). The studies open a pathway to scalable fabrication of high speed graphene transistors and functional circuits, and represent a significant step forward to graphene based radio frequency devices. PMID:21648419

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2011-01-01

75

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress  

NASA Technical Reports Server (NTRS)

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Mclyman, W. T. (inventor)

1981-01-01

76

Bioluminescent bioreporter integrated circuits (BBICs)  

NASA Astrophysics Data System (ADS)

As the workhorse of the integrated circuit (IC) industry, the capabilities of CMOS have been expanded well beyond the original applications. The full spectrum of analog circuits from switched-capacitor filters to microwave circuit blocks, and from general-purpose operational amplifiers to sub- nanosecond analog timing circuits for nuclear physics experiments have been implemented in CMOS. This technology has also made in-roads into the growing area of monolithic sensors with devices such as active-pixel sensors and other electro-optical detection devices. While many of the processes used for MEMS fabrication are not compatible with the CMOS IC process, depositing a sensor material onto a previously fabricated CMOS circuit can create a very useful category of sensors. In this work we report a chemical sensor composed of bioluminescent bioreporters (genetically engineered bacteria) deposited onto a micro-luminometer fabricated in a standard CMOS IC process. The bioreporter used for this work emitted 490-nm light when exposed to toluene. This luminescence was detected by the micro- luminometer giving an indication of the concentration of toluene. Other bioluminescent bioreporters sensitive to explosives, mercury, and other organic chemicals and heavy metals have been reported. These could be incorporated (individually or in combination) with the micro-luminometer reported here to form a variety of chemical sensors.

Simpson, Michael L.; Sayler, Gary S.; Nivens, David; Ripp, Steve; Paulus, Michael J.; Jellison, Gerald E.

1998-07-01

77

Microfluidic Photonic Integrated Circuits.  

PubMed

We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled two-dimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1-10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments. PMID:20428483

Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S; Lo, Yu-Hwa

2008-11-18

78

Microfluidic photonic integrated circuits  

NASA Astrophysics Data System (ADS)

We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled twodimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1- 10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments.

Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S.; Lo, Yu-Hwa

2008-11-01

79

Cramming More Components onto Integrated Circuits  

E-print Network

Cramming More Components onto Integrated Circuits GORDON E. MOORE, LIFE FELLOW, IEEE With unit cost, thin-film structures, and semiconductor integrated circuits. Reprinted from Gordon E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, pp. 114­117, April 19, 1965. Publisher Item

DeHon, André

80

Stability of amorphous silicon thin film transistors and circuits  

NASA Astrophysics Data System (ADS)

Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used for the active-matrix addressing of flat panel displays, optical scanners and sensors. Extending the application of the a-Si TFTs from switches to current sources, which requires continuous operation such as for active-matrix organic light-emitting-diode (AMOLED) pixels, makes stability a critical issue. This thesis first presents a two-stage model for the stability characterization and reliable lifetime prediction for highly stable a-Si TFTs under low gate-field stress. Two stages of the threshold voltage shift are identified from the decrease of the drain saturation current under low-gate field. The first initial stage dominates up to hours or days near room temperature. It can be characterized with a stretched-exponential model, with the underlying physical mechanism of charge trapping in the gate dielectric. The second stage dominates in the long term and then saturates. It corresponds to the breaking of weak bonds in the amorphous silicon. It can be modeled with a "unified stretched exponential fit," in which a thermalization energy is used to unify experimental measurements of drain current decay at different temperatures into a single curve. Two groups of experiments were conducted to reduce the drain current instability of a-Si TFTs under prolonged gate bias. Deposition conditions for the silicon nitride (SiNx) gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive ion etching steps, or with all wet etching steps, the latter in a new process. The two-stage model that unites charge trapping in the SiNx gate dielectric and defect generation in the a-Si channel was used to interpret the experimental results. We identified the optimal substrate temperature, gas flow ratios, and RF deposition power densities. The stability of the a-Si channel depends also on the deposition conditions for the underlying SiNx gate insulator. TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% decay time of the drain current of back channel passivated dry-etched TFTs under continuous operation at 20°C from 3.3 x 104 sec (9.2 hours) to 4.4 x 107 sec (1.4 years). The 50% lifetime can be further improved by ˜2 times through wet etching process. Two assumptions in the two-stage model were revisited. First, the distribution of the gap state density in a-Si was obtained with the field-effect technique. The redistribution of the gap state density after low-gate field stress supports the idea that defect creation in a-Si dominates in the long term. Second, the drain-bias dependence of drain current degradation was measured and modeled. The unified stretched exponential was validated for a-Si TFTs operating in saturation. Finally, a new 3-TFT voltage-programmed pixel circuit with an in-pixel current source is presented. This circuit is largely insensitive to the TFT threshold voltage shift. The fabricated pixel circuit provides organic light-emitting diode (OLED) currents ranging from 25 nA to 2.9 microA, an on/off ratio of 116 at typical quarter graphics display resolution (QVGA) display timing. The overall conclusion of this thesis research is that the operating life of a-Si TFTs can be quite long, and that these transistors can expect to find yet more applications in large area electronics.

Liu, Ting

81

Transient modelling of single-electron transistors for efficient circuit simulation by SPICE  

E-print Network

Transient modelling of single-electron transistors for efficient circuit simulation by SPICE Y simulation by SPICE. The developed model is based on a linearised equivalent circuit and the solution of a master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several

Hwang, Sung Woo

82

Loss compensation in Metamaterials through embedding of active transistor based negative differential resistance circuits  

E-print Network

This paper presents an all-electronic approach for loss compensation in metamaterials. This is achieved by embedding active-transistors based negative differential resistance (NDR) circuits in each unit cell of the metamaterial lattice. NDR circuits provide tunable loss compensation over a broad frequency range limited only by the maximum operating frequency of transistors that is reaching terahertz values in newer semiconductor processes. Design, simulation and experimental results of metamaterials composed of split ring resonators (SRR) with and without loss compensation circuits are presented.

Xu, Wangren; Sonkusale, Sameer

2012-01-01

83

New platforms for electronic devices: N-channel organic field-effect transistors, complementary circuits, and nanowire transistors  

Microsoft Academic Search

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized alpha,o-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N'-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric\\/electrode surface treatment on the response of bottom-contact devices was also examined

Byungwook Yoo

2007-01-01

84

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The drive circuit requirements of the insulated gate bipolar transistor (IGBT) are explained with the aid of an analytical model. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of anode voltage. Model results are compared with measured turn-on and turn-off waveforms for different drive, load, and feedback circuits, and for different

1991-01-01

85

Ultra-low power microwave CHFET integrated circuit development  

SciTech Connect

This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

Baca, A.G.; Hietala, V.M.; Greenway, D.; Sloan, L.R.; Shul, R.J.; Muyshondt, G.P.; Dubbert, D.F.

1998-04-01

86

Flexible high-performance carbon nanotube integrated circuits  

NASA Astrophysics Data System (ADS)

Carbon nanotube thin-film transistors are expected to enable the fabrication of high-performance, flexible and transparent devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases). Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated, but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 µm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm2 V-1 s-1 and an on/off ratio of 6 × 106. We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master-slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques.

Sun, Dong-Ming; Timmermans, Marina Y.; Tian, Ying; Nasibulin, Albert G.; Kauppinen, Esko I.; Kishimoto, Shigeru; Mizutani, Takashi; Ohno, Yutaka

2011-03-01

87

Flexible high-performance carbon nanotube integrated circuits.  

PubMed

Carbon nanotube thin-film transistors are expected to enable the fabrication of high-performance, flexible and transparent devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases). Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated, but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 µm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm(2) V(-1) s(-1) and an on/off ratio of 6 × 10(6). We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master-slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques. PMID:21297625

Sun, Dong-ming; Timmermans, Marina Y; Tian, Ying; Nasibulin, Albert G; Kauppinen, Esko I; Kishimoto, Shigeru; Mizutani, Takashi; Ohno, Yutaka

2011-03-01

88

VHSIC /very high speed integrated circuits/ - Technologies and tradeoffs  

NASA Astrophysics Data System (ADS)

Very high speed integrated circuits (VHSIC) are large-scale digital integrated circuits with typical logic-gate propagation delays below 1 nanosecond. Bipolar technology was first to enter into this speed range. However, MOS and GaAs technologies are now also available. Attention is given to emitter-coupled logic, integrated injection logic, n-channel MOS logic, complementary MOS logic, depletion-mode GaAs logic, and enhancement-mode GaAs logic. Gate arrays are considered, taking into account the basic structure, capacitances, propagation delays, transistor sizes, and a comparison of propagation delays. Advantages and limitations of custom logic and functional cells are examined, and questions of power dissipation and chip complexity are investigated.

Barna, A.

89

High-performance organic transistors for printed circuits  

NASA Astrophysics Data System (ADS)

This presentation focuses on recent development of key technologies for printed LSIs which can provide future low-cost platforms for RFID tags, AD converters, data processors, and sensing circuitries. Such prospect bears increasing reality because of recent research innovations in the field of material chemistry, charge transport physics, and solution processes of printable organic semiconductors. Achieving band transport in state-of-the-art printable organic semiconductors, carrier mobility is elevated above 15 cm2/Vs, so that reasonable speed in moderately integrated logic circuits can be available. With excellent chemical and thermal stability for such compounds, we are developing simple integrated devices based on CMOS using p-type and n-type printed organic FETs. Particularly important are new processing technologies for continuous growth of inch-size organic single-crystalline semiconductor "wafers" from solution and for lithographical patterning of semiconductors and metal electrodes. Successful rectification and identification are demonstrated at 13.56 MHz with printed organic CMOS circuits for the first time.

Takeya, J.

2014-10-01

90

InP HBTs for THz Frequency Integrated Circuits M. Urteaga1  

E-print Network

InP HBTs for THz Frequency Integrated Circuits M. Urteaga1 , M.Seo1 , J. Hacker1 , Z. Griffith1 , A process has been developed for THz frequency integrated circuits. A 0.25x4m2 HBT exhibits an extrapolated ft/fmax of 430GHz/1.03THz at IC =11mA, VCE= 1.8V. The transistors achieve this performance while main

Rodwell, Mark J. W.

91

Ion-implanted complementary MOS transistors in low-voltage circuits  

Microsoft Academic Search

Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT\\/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.

RICHARD M. SWANSON; JAMES D. MEINDL

1972-01-01

92

A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors  

Microsoft Academic Search

This paper presents a circuit-compatible compact model for short channel length (5 nm~100 nm), quasi-ballistic single wall carbon nanotube field-effect transistors (CNFETs). For the first time, a universal circuit-compatible CNFET model was implemented with HSPICE. This model includes practical device non-idealities, e.g. the quantum confinement effects in both circumferential and channel length direction, the acoustical\\/optical phonon scattering in channel region

J. Deng; H.-S. P. Wong

2006-01-01

93

Plenary, 2008 IEEE-CSIC Symposium, October 12, 2008 THz Bipolar Transistor Circuits  

E-print Network

Plenary, 2008 IEEE-CSIC Symposium, October 12, 2008 THz Bipolar Transistor Circuits: Technical;Simple Device Physics: Fringing Capacitance + 5.1 WC functionvarying-slowlyC + 5.1 TL plate 4:1 reduce width 4:1, keep constant length increase current density 4:1 #12;Bi lBipolar T i

Rodwell, Mark J. W.

94

Speed and voltage regulation of d.c. shunt machines using power transistor in field circuit  

Microsoft Academic Search

A simple method for speed and voltage regulation of d.c. shunt machines is presented. The method is based on the use of a power transistor circuit which automatically adjusts the field current Such that the Speed or output voltage, as the case may be, is maintained constant with increasing load on the machine. An added advantage of this inothod is

VIMAL SINGH; S. K. KAK

1974-01-01

95

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.  

PubMed

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates). PMID:24923382

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-01-01

96

Asynchronous sequential circuit design using pass transistor iterative logic arrays  

NASA Technical Reports Server (NTRS)

The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

Liu, M. N.; Maki, G. K.; Whitaker, S. R.

1991-01-01

97

Field Effect Transistor /FET/ circuit for variable gin amplifiers  

NASA Technical Reports Server (NTRS)

Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

Spaid, G. H.

1969-01-01

98

InP heterojunction bipolar transistor decision circuits  

Microsoft Academic Search

We have designed and built 30 Gb\\/s master-slave D-flip-flop circuits using InGaAs-InAlAs HBT's. The HBT devices have a ? of 30, and fmax and f, of 160 and 106 GHz, respectively. We discuss methods of testing decision circuits when bit error rate testing is not available at high data rates

L. Samoska; R. Pullela; B. Agarwal; D. Mensa; Q. Lee; V. Kaman; J. Guthrie; M. J. Rodwell

1998-01-01

99

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits  

NASA Technical Reports Server (NTRS)

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

1972-01-01

100

Analog MOS integrated circuits for signal processing  

Microsoft Academic Search

Theoretical and practical aspects of analog MOS integrated circuits are discussed. The basic properties of these circuits are described, providing necessary background material in mathematics and semiconductor device physics and technology. The operation and design of such important circuits as switched-capacitor filters, analog-to-digital and digital-to-analog converters, amplifiers, modulators, and oscillators. Practical problems encountered in design are discussed, solutions are provided,

R. Gregorian; G. C. Temes

1986-01-01

101

Gyrator employing field effect transistors  

NASA Technical Reports Server (NTRS)

A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Hochmair, E. S. (inventor)

1973-01-01

102

Reusable vibration resistant integrated circuit mounting socket  

SciTech Connect

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Evans, C.N.

1993-12-31

103

Reusable vibration resistant integrated circuit mounting socket  

DOEpatents

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Evans, Craig N. (Irwin, PA)

1995-01-01

104

Modularized construction of general integrated circuits on individual carbon nanotubes.  

PubMed

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future. PMID:24796796

Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

2014-06-11

105

Inductive Fault Analysis of MOS Integrated Circuits  

Microsoft Academic Search

Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types

John Shen; W. Maly; F. J. Ferguson

1985-01-01

106

Integrated circuit model development for EMP  

Microsoft Academic Search

The response of Integrated Circuits (IC) to pulsed and gated sine-wave stimuli was used to develop reasonably accurate device models for EMP assessment. These IC models were then used in conjunction with circuit and transfer function models to determine the failure threshold (upset and burnout) to postulated EMP disturbance. This paper describes the model development and test verification of IC

C. Kleiner; J. Nelson; F. Vassallo; E. Heaton

1974-01-01

107

Carbon nanotube synthesis for integrated circuit interconnects  

E-print Network

Based on their properties, carbon nanotubes (CNTs) have been identified as ideal replacements for copper interconnects in integrated circuits given their higher current density, inertness, and higher resistance to ...

Nessim, Gilbert Daniel

2009-01-01

108

Reverse engineering of integrated circuits  

DOEpatents

Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

Chisholm, Gregory H. (Shorewood, IL); Eckmann, Steven T. (Colorado Springs, CO); Lain, Christopher M. (Pittsburgh, PA); Veroff, Robert L. (Albuquerque, NM)

2003-01-01

109

Abstract--Dual-gate junction field-effect transistors (JFETs) are integrated in a substrate transfer process called back-wafer  

E-print Network

, among other things, has been exploited in read-out circuitry for high-resolution silicon radiation) technology for integrated circuit processing have been recognized and the technology has been used in high1 Abstract--Dual-gate junction field-effect transistors (JFETs) are integrated in a substrate

Technische Universiteit Delft

110

High-performance and stable organic transistors and circuits with patterned polypyrrole electrodes.  

PubMed

High performance p-/n-type transistors and complementary inverter circuits are demonstrated using patterned polypyrrole (PPY) as pure electrodes. Strikingly, these devices show good stability under continuous operation and long-term storage conditions. Furthermore, PPY electrodes also exhibit good applicability in solution-processed and flexible devices. All these results indicate the great potential of PPY electrodes in solution-processed, all-organic, flexible, transparent, and low-power electronics. PMID:22431264

Li, Liqiang; Jiang, Lin; Wang, Wenchong; Du, Chuan; Fuchs, Harald; Hu, Wenping; Chi, Lifeng

2012-04-24

111

External electro-optic probing of millimeter-wave integrated circuits  

NASA Technical Reports Server (NTRS)

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.; Valdmanis, J. A.; Jackson, T. A.; Bhasin, K. B.; Romanofsky, Robert R.; Mourou, G. A.

1989-01-01

112

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits  

PubMed Central

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

113

High Performance Low-Noise 128Channel Readout Integrated Circuit for Flat Panel X-ray Detector Systems  

Microsoft Academic Search

ABSTRACT A silicon mixed-signal integrated circuit is needed to extract and process x-ray induced signals from a coated flat panel thin film transistor array (TFT) in order to generate a digital x-ray image. Indigo Systems Corporation has designed, fabricated, and tested such a readout integrated circuit (ROIC), the ISC9717. This off-the-shelf, high performance, low- noise, 128-channel device is fully programmable

Eric Beuville; Mark Belding; Adrienne Costello; Randy Hansen; Susan Petronio

114

Integration hybride de transistors a un electron sur un noeud technologique CMOS  

NASA Astrophysics Data System (ADS)

This study deals with the hybrid integration of single electron transistors (SET) on a CMOS technology nod. SET devices possess a high potential, especially regarding energy efficiency, but aren't fit to completely replace CMOS components in electrical circuits. However, this problem can be solved through hybrid combination of SETs and MOS, leading to very low operating power circuits, and high integration density. This thesis investigates the use of the nanodamascene process, developed by C. Dubuc, for back-end-of-line (BEOL) SET fabrication, meaning creation of SETs in the oxide encapsulating CMOS devices. The assets the nanodamascene process presents are quite interesting: fabrication of SETs with a large operation margin, high repeatability, and potential for BEOL fabrication. This last point, in particular, makes this process promising. Indeed, it opens the path to the fabrication of numerous layers of SETs, stacked one upon the other, and forming 3D circuits, created on top of 2D CMOS layer. Thus a high gain to existing CMOS wafers could be generated. Devices created through the use of the nanodamascene process, adapted for BEOL SET fabrication, are presented. Limits and improvement perspectives of the technique's transfer are discussed. Electrical characterizations of the devices are also presented. They have demonstrated the created devices functionality, thus validating the successful adaption of the nanodamascene process. They have also allowed for the identification of numerous traps located at the heart of fabricated devices. Fabricated SET devices potential for hybrid SET-CMOS circuits was studied through simulations. Possible architectures showing good potential for early hybrid circuits' realization were identified. Keywords: MOSFET, single electron transistor (SET), nanotechnology, microfabrication, nanodamascene, electrical characterization.

Jouvet, Nicolas

115

Design methodologies for silicon photonic integrated circuits  

NASA Astrophysics Data System (ADS)

This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.

Chrostowski, Lukas; Flueckiger, Jonas; Lin, Charlie; Hochberg, Michael; Pond, James; Klein, Jackson; Ferguson, John; Cone, Chris

2014-03-01

116

Solution methods for very highly integrated circuits.  

SciTech Connect

While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator, both prominent world-class software tools.

Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

2010-12-01

117

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits  

NASA Technical Reports Server (NTRS)

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

1975-01-01

118

Package for integrated optic circuit and method  

DOEpatents

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

119

Package for integrated optic circuit and method  

DOEpatents

A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

1998-01-01

120

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

Hammond, R.B.; Bowman, D.R.

1989-04-11

121

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1989-01-01

122

Fabrication of nanoscale gaps in integrated circuits  

NASA Astrophysics Data System (ADS)

Nanosize objects such as metal clusters present an ideal system for the study of quantum phenomena and for the construction of practical quantum devices. Integrating these small objects in a macroscopic circuit is, however, a difficult task. So far, nanoparticles have been contacted and addressed by highly sophisticated techniques not suitable for large-scale integration in macroscopic circuits. We present an optical lithography method that allows for the fabrication of a network of electrodes separated by gaps of controlled nanometer size. The main idea is to control the gap size with subnanometer precision using a structure grown by molecular-beam epitaxy.

Krahne, Roman; Yacoby, Amir; Shtrikman, Hadas; Bar-Joseph, Israel; Dadosh, Tali; Sperling, Joseph

2002-07-01

123

Phase-controlled integrated photonic quantum circuits  

E-print Network

Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externally-controlled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms.

Brian J. Smith; Dmytro Kundys; Nicholas Thomas-Peter; P. G. R. Smith; I. A. Walmsley

2009-05-18

124

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.  

PubMed

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42?GHz and a maximum oscillation frequency fMAX up to 50?GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9?GHz, fMAX~1?GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

125

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics  

PubMed Central

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

126

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics  

NASA Astrophysics Data System (ADS)

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42?GHz and a maximum oscillation frequency fMAX up to 50?GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9?GHz, fMAX~1?GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-01

127

Nano-technology-device prospects: quantum dots and transistors for ultracompact integration and terahertz analogue applications  

Microsoft Academic Search

Nanometric-sized transistors can be employed to control the charge transfer from one quantum dot (QD) to another one. The charge in a QD can also be used to control the transistor current. In principle here then electronics is not related to currents but due to charges. It is of interest, not only to apply this to ultracompact digital circuits, but

H. L. Hartnagel

1998-01-01

128

High-speed Josephson integrated circuit technology  

SciTech Connect

Josephson junctions with Nb/AlOx/Nb structures exhibit excellent characteristics with a low leakage current, and are stable with respect to thermal cycling and long term storage. The authors used niobium junctions in a variety of high-speed circuits. This paper describes recent progress with high-speed integrated circuits using niobium junctions. First, the authors briefly describe the circuit fabrication proceeds, and then they introduce their Modified Varialbe Threshold Logic (MVTL) gate family. The lowest experimentally obtained MVTL-OR gate delay was only 2.5 ps with a power consumption of 17 ..mu..Wgate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (Arithmetic Logic Unit), and 4-bit microprocessors. They confirmed the high speed operation of less than 10 ps per gate on average for these circuits. They also developed a new high-sensitivity magnetic sensor using the SQUID (Superconducting QUantum Interference Device). It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature in a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself.

Hassuo, S.

1989-03-01

129

Simultaneous characterization of mechanical and electrical performances of ultraflexible and stretchable organic integrated circuits  

Microsoft Academic Search

We report the simultaneous characterization of mechanical and electrical performances of ultraflexible and stretchable organic integrated circuits comprised of high-performance organic semiconductors, carbon nanotube-based elastic conductors, and self-assembled monolayers. By employing a high-precision mechanical stage that combines electrical functional terminals, the electrical performances of ultraflexible or stretchable organic transistors were measured after being bent to a 50 µm bending radius

Tsuyoshi Sekitania; Tomoyuki Yokotaa; Kazunori Kuribaraa; Takao Someyaa

2012-01-01

130

Development of thin film diamond based integrated circuit technology  

NASA Astrophysics Data System (ADS)

In the portion of this project funded by BMDO/IST, we have been developing the elements of a diamond based semiconductor technology for high temperature applications. The approach is centered around incorporating a Schottky barrier contact and MOS field effect transistor using diamond films prepared by microwave plasma chemical vapor deposition (MPACVD). The experimental basis for this research is the successful fabrication in our laboratory of the world's first Schottky diodes with PACVD diamond base. These devices have characteristics similar to their counterparts fabricated using single crystal synthetic diamond prepared by high pressure methods. This has required a detailed understanding and control of the deposition process at it relates to the chemical purity and structural perfection of the resulting single crystal diamond films, in addition, detailed characterization of the films has allowed for meaningful preparation characterization electronic property relations. The ultimate goal of the proposed research is to fabricate transistors on single crystal heteroepitaxial diamond and to fabricate small scale integrated circuit operational at 400-500 C.

Badzian, Andrzej; Gildenblat, Gennady

1994-12-01

131

Power monitoring in integrated circuits  

E-print Network

Power monitoring is needed in most electrical systems, and is crucial for ensuring reliability in everything from industrial and telecom applications, to automotive and consumer electronics. Power monitoring of integrated ...

Al Bastami, Anas Ibrahim

2014-01-01

132

Microwave integrated circuit for Josephson voltage standards  

NASA Technical Reports Server (NTRS)

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

Holdeman, L. B.; Toots, J.; Chang, C. C. (inventors)

1980-01-01

133

A CCD integrated circuit for transient recorders  

NASA Technical Reports Server (NTRS)

A 50 MHz CCD integrated circuit is described that was developed for use in transient analog signal recorders to sample and time expand transient signals. The integrated circuit achieves an effective 200 MHz sample rate by using four 32 stage peristaltic CCDs to sample the transient signal four times each clock period. Dual frequency, 4 phi clocking is used to sample and time expand the sampled data. The output signals of the four CCDs are multiplexed on chip into a single low frequency output data line. When operated with 50 MHz/165 KHz 4 phi clocks, this circuit has a 200 MHz sample rate, a record length of 640 nanoseconds, a time expansion factor of 303, and overall signal to noise ratio of 40:1. The signal to noise ratio is limited by fixed pattern noise of the four CCDs.

Balch, J. W.; Mcconaghy, C. F.

1976-01-01

134

Silicon Vertically Integrated Nanowire Field Effect Transistors  

E-print Network

of the threshold voltage is commonly observed due to the presence of surface and interface charge-trapping states. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field challenging issues such as short-channel effects (SCEs), scaling of gate oxide thickness, and increasing power

Yang, Peidong

135

Integrated Circuits in the Introductory Electronics Laboratory  

ERIC Educational Resources Information Center

Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

English, Thomas C.; Lind, David A.

1973-01-01

136

Healing Voids In Interconnections In Integrated Circuits  

NASA Technical Reports Server (NTRS)

Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

1989-01-01

137

Extracting secret keys from integrated circuits  

Microsoft Academic Search

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, sophisticated tampering methods have been devised to extract secret keys stored in digital integrated circuits (ICs) from conditional access systems such as smartcards and ATMs. Arbiter-based Physical Unclonable Functions (PUFs) is proposed to exploit the statistical delay variation

Daihyun Lim; Jae W. Lee; Blaise Gassend; G. Edward Suh; Marten Van Dijk; Srinivas Devadas

2005-01-01

138

Harnessing optical forces in integrated photonic circuits  

Microsoft Academic Search

The force exerted by photons is of fundamental importance in light-matter interactions. For example, in free space, optical tweezers have been widely used to manipulate atoms and microscale dielectric particles. This optical force is expected to be greatly enhanced in integrated photonic circuits in which light is highly concentrated at the nanoscale. Harnessing the optical force on a semiconductor chip

Mo Li; W. H. P. Pernice; C. Xiong; T. Baehr-Jones; M. Hochberg; H. X. Tang

2008-01-01

139

Integrated Circuit / Microfluidic Chips for Dielectric Manipulation  

E-print Network

Integrated Circuit / Microfluidic Chips for Dielectric Manipulation A THESIS PRESENTED BY THOMAS Manipulation Thomas Peter Hunt Advisor: Robert M. Westervelt This thesis describes the development the surrounding medium can be manipulated with DEP. #12;iv We initially fabricated an array of microscale post

Heller, Eric

140

Integrated Circuit Tester Using Interferometric Imaging  

Microsoft Academic Search

An interferometric imaging technique can provide time-resolved diagnostics of semiconductor integrated circuits. The semiconductor device is placed in one arm of an interferometer and illuminated with a picosecond pulse from a sub-bandgap infrared laser. As the laser passes through the semiconductor, it samples local variations in the index of refraction. These variations are caused by a number of physical phenomena

W. R. Donaldson; E. M. R. Michaels; K. Akowuah; R. A. Falk

1997-01-01

141

Integrated circuit tester using interferometric imaging  

Microsoft Academic Search

Summary form only given. An interferometric imaging technique can provide time-resolved diagnostics of semiconductor integrated circuits. The semiconductor device is placed in one arm of an interferometer and illuminated with a picosecond pulse from a sub-bandgap infrared laser. As the laser passes through the semiconductor, it samples local variations in the index of refraction. These variations are caused by a

W. R. Donaldson; E. M. R. Michaels; K. Akowuah; R. A. Falk

1997-01-01

142

Total dose and dose rate models for bipolar transistors in circuit simulation.  

SciTech Connect

The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

Campbell, Phillip Montgomery; Wix, Steven D.

2013-05-01

143

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors  

Microsoft Academic Search

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance\\u000a (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate\\u000a ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron\\u000a Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate

Vinay Saripalli; Vijay Narayanan; Suman Datta

2009-01-01

144

Equivalent circuit for an organic field-effect transistor from impedance measurements under dc bias  

NASA Astrophysics Data System (ADS)

The output and forward transfer impedance of an organic field-effect transistor have been measured by a lock-in amplifier technique. The small-signal ac response of a pentacene FET, under dc bias, is used to construct the equivalent circuit. The output impedance parameters are numerically simulated using Bode plot analysis and the deviations at low frequency are modeled with contact impedance of the source-drain channel. The ac current generator at the output is estimated along with the gate capacitances.

Jaiswal, Manu; Menon, Reghu

2006-03-01

145

Development of 3D integrated circuits for HEP  

SciTech Connect

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

Yarema, R.; /Fermilab

2006-09-01

146

Data readout system utilizing photonic integrated circuit  

NASA Astrophysics Data System (ADS)

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Stopi?ski, S.; Malinowski, M.; Piramidowicz, R.; Smit, M. K.; Leijtens, X. J. M.

2013-10-01

147

Integrated-Circuit Active Digital Filter  

NASA Technical Reports Server (NTRS)

Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

Nathan, R.

1986-01-01

148

Three-Dimensional Integration of Integrated Circuits—an Introduction  

Microsoft Academic Search

\\u000a Three-dimensional (3D) stacking of ultra-thin integrated circuits (ICs) is identified as an inevitable solution for future\\u000a system miniaturization and functional diversification. 3D integration offers a long list of benefits in terms of system form\\u000a factor, density scaling and multiplication, reduced interconnection latency and power consumption, bandwidth enhancement,\\u000a and heterogeneous integration of disparate technologies. In this 3D implementation, thinned IC layers

Chuan Seng Tan

149

IEEE Communications Magazine February 20022 Distributed Integrated Circuits  

E-print Network

and electrodynamics. This process of breaking down the ultimate objective into smaller, more manageable projects, the overspecialization and short time spans asso- ciated with today's design cycles sometimes result in suboptimal (e.g., transistor-level circuit design). This explains why most of today's research activ- ities

Hajimiri, Ali

150

Integrated-Circuit Controller For Brushless dc Motor  

NASA Technical Reports Server (NTRS)

Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

Le, Dong Tuan

1994-01-01

151

The Future of Integrated Circuits: A Survey of Nanoelectronics  

Microsoft Academic Search

While most of the electronics industry is dependent on the ever-decreasing size of lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits built with components on the scale of 10 nm) seem to be the most promising successor to lithographic based ICs. Molecular-scale devices including diodes, bistable switches, carbon nanotubes, and nanowires have been fabricated and characterized in chemistry labs.

Michael Haselman; Scott Hauck

2010-01-01

152

Tomographic reconstruction of an integrated circuit interconnect  

SciTech Connect

An Al{endash}W-silica integrated circuit interconnect sample was thinned to several {mu}m and scanned across a 200 nm focal spot of a Fresnel zone plate operating at photon energy of 1573 eV. The experiment was performed on beamline 2-ID-B of the Advanced Photon Source, a third-generation synchrotron facility. Thirteen scanned projections of the sample were acquired over the angular range {plus_minus}69.2{degree}. At least 301{times}301 pixels were acquired at each angle with a step size of 77{times}57 nm. A three-dimensional image with an approximate uncertainty of 400 nm was reconstructed from projection data using a standard algorithm. The two layers of the integrated circuit and the presence of the focused ion beam markers on the surface of the sample are clearly shown in the reconstruction. {copyright} {ital 1999 American Institute of Physics.}

Levine, Z.H. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States)] [National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Kalukin, A.R. [Physics Department, Rensselaer Polytechnic Institute, Troy, New York 12180-3590 (United States)] [Physics Department, Rensselaer Polytechnic Institute, Troy, New York 12180-3590 (United States); Frigo, S.P.; McNulty, I. [Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois 60439 (United States)] [Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois 60439 (United States); Kuhn, M. [Digital Equipment Corporation, Hudson, Massachusetts 01749 (United States)] [Digital Equipment Corporation, Hudson, Massachusetts 01749 (United States)

1999-01-01

153

An Analog Integrated-Circuit Vocal Tract  

Microsoft Academic Search

We present the first experimental integrated-circuit vocal tract by mapping fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The 275 muW analog vocal tract chip includes a 16-stage cascade of two-port pi-elements that forms a tunable transmission line, electronically variable impedances, and a current source as the

Keng Hoong Wee; Lorenzo Turicchia; Rahul Sarpeshkar

2008-01-01

154

Progress in radiation immune thermionic integrated circuits  

SciTech Connect

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

Lynn, D.K.; McCormick, J.B. (comps.)

1985-08-01

155

7.5 Gb\\/s monolithically integrated clock recovery circuit using PLL and 0.3-micron gate length quantum well HEMT's  

Microsoft Academic Search

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement\\/depletion AlGaAs\\/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 micron has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz

Zhi-Gong Wang; Manfred Berroth; Ulrich Nowotny; Peter Hofmann; Axel Huelsmann; Klaus Koehler; Brian Raynor; Joachim Schneider

1994-01-01

156

Selective remanent ambipolar charge transport in polymeric field-effect transistors for high-performance logic circuits fabricated in ambient.  

PubMed

Ambipolar polymeric field-effect transistors can be programmed into a p- or n-type mode by using the remanent polarization of a ferroelectric gate insulator. Due to the remanent polarity, the device architecture is suited as a building block in complementary logic circuits and in CMOS-compatible memory cells for non-destructive read-out operations. PMID:25284119

Fabiano, Simone; Usta, Hakan; Forchheimer, Robert; Crispin, Xavier; Facchetti, Antonio; Berggren, Magnus

2014-11-26

157

Abstract--The parametric shifts or circuit failures caused by transistor aging have become more severe with shrinking device  

E-print Network

much of the performance benefit gained by traditional device scaling. In particular, the parametricAbstract-- The parametric shifts or circuit failures caused by transistor aging have become more. Finally, technology scaling has led to a massive increase in the number of operating conditions devices

Kim, Chris H.

158

Power system with an integrated lubrication circuit  

DOEpatents

A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

Hoff, Brian D. (East Peoria, IL); Akasam, Sivaprasad (Peoria, IL); Algrain, Marcelo C. (Peoria, IL); Johnson, Kris W. (Washington, IL); Lane, William H. (Chillicothe, IL)

2009-11-10

159

Electro-optical Probing Of Terahertz Integrated Circuits  

NASA Technical Reports Server (NTRS)

Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

1990-01-01

160

Processing techniques for refractory integrated circuits  

NASA Astrophysics Data System (ADS)

Processing techniques have been developed to increase yields and uniformity in superconductor integrated circuits fabricated with refractory materials. An eight-level process was used to define a ground plane, ground plane insulator, Josephson junction base and counterelectrodes, a second insulator layer, superconductor interconnections, resistors, and gold contact pads. Every layer, except the gold, was patterned by reactive ion etching (RIE). A resistor structure was developed that included an etch stop layer. The formation of polymers, which occurs with etch gases containing carbon, was inhibited by the addition of oxygen to the plasma. RIE of insulator vias was accomplished with a mixture of NF3 and Ar that gave good selectivity for silicon dioxide over niobium. Stress-free films of niobium, molybdenum, and silicon dioxide were obtained by adjusting the sputtering gas pressure. Molybdenum resistors, deposited as a top layer, were trimmed by RIE as a posttesting step to improve circuit performance.

Przybysz, John X.; Blaugher, R. D.; Buttyan, J.

1989-03-01

161

Relationships among classes of self-oscillating transistor parallel inverters. [dc to square wave converter circuits for power conditioning  

NASA Technical Reports Server (NTRS)

A procedure is developed for classifying dc-to-square-wave two-transistor parallel inverters used in power conditioning applications. The inverters are reduced to equivalent RLC networks and are then grouped with other inverters with the same basic equivalent circuit. Distinction between inverter classes is based on the topology characteristics of the equivalent circuits. Information about one class can then be extended to another class using the basic oscillation theory and the concept of duality. Oscillograms from test circuits confirm the validity of the procedure adopted.

Wilson, T. G.; Lee, F. C. Y.; Burns, W. W., III; Owen, H. A., Jr.

1974-01-01

162

High-performance low-noise 128-channel readout-integrated circuit for flat-panel x-ray detector systems  

Microsoft Academic Search

A silicon mixed-signal integrated circuit is needed to extract and process x-ray induced signals from a coated flat panel thin film transistor array (TFT) in order to generate a digital x-ray image. Indigo Systems Corporation has designed, fabricated, and tested such a readout integrated circuit (ROIC), the ISC9717. This off-the-shelf, high performance, low-noise, 128-channel device is fully programmable with a

Eric J. Beuville; Mark Belding; Adrienne N. Costello; Randy Hansen; Susan M. Petronio

2004-01-01

163

A wafer-scale 3-D circuit integration technology  

Microsoft Academic Search

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

James A. Burns; Brian F. Aull; Chenson K. Chen; Chang-Lee Chen; Craig L. Keast; Jeffrey M. Knecht; V. Suntharalingam; K. Warner; P. W. Wyatt; D.-R. W. Yost

2006-01-01

164

Study of Contact Resistances in Integrated Circuits  

NASA Technical Reports Server (NTRS)

Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.

Buehler, M. G.; Lambe, J.; Suszko, S. F.

1985-01-01

165

Testing Fixture For Microwave Integrated Circuits  

NASA Technical Reports Server (NTRS)

Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

Romanofsky, Robert; Shalkhauser, Kurt

1989-01-01

166

Nobel Laureate e-Museum: Integrated Circuits  

NSDL National Science Digital Library

Nobel Laureate e-Museum's Educational section provides historical and scientific background information on inventions by those who have been honored with the Nobel Laureates in physics, chemistry, medicine, literature and peace over the years. For example, from this website, visitors can read about Nobel Laureate Jack Kilby and his part in the invention of integrated circuits, which are found in a variety of modern electrical device, including computers, cars, television sets, CD players, and cellular phones. A game called Techville is also free to download. A "walk through" will help you out if you get stuck on the game.

167

3D packaging for integrated circuit systems  

SciTech Connect

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

Chu, D.; Palmer, D.W. [eds.

1996-11-01

168

An integrated circuit floating point accumulator  

NASA Technical Reports Server (NTRS)

Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

Goldsmith, T. C.

1977-01-01

169

Sequential circuit design for radiation hardened multiple voltage integrated circuits  

DOEpatents

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

2009-11-24

170

SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs  

SciTech Connect

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Huque, Mohammad A [ORNL; Tolbert, Leon M [ORNL; Blalock, Benjamin [University of Tennessee, Knoxville (UTK); Islam, Syed K [University of Tennessee, Knoxville (UTK)

2010-01-01

171

Technologies for highly parallel optoelectronic integrated circuits  

SciTech Connect

While summarily reviewing the range of optoelectronic integrated circuits (OEICs), this paper emphasizes technology for highly parallel optical interconnections. Market volume and integration suitability considerations highlight board-to-board interconnects within systems as an initial insertion point for large OEIC production. The large channel count of these intrasystem interconnects necessitates two-dimensional laser transmitter and photoreceiver arrays. Surface normal optoelectronic components are promoted as a basis for OEICs in this application. An example system is discussed that uses vertical cavity surface emitting lasers for optical buses between layers of stacked multichip modules. Another potentially important application for highly parallel OEICs is optical routing or packet switching, and examples of such systems based on smart pixels are presented.

Lear, K.L. [Sandia National Labs., Albuquerque, NM (United States). Photonics Research Dept.

1994-10-01

172

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits  

NASA Astrophysics Data System (ADS)

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Es-Sakhi, Azzedin D.

173

Harnessing optical forces in integrated photonic circuits.  

PubMed

The force exerted by photons is of fundamental importance in light-matter interactions. For example, in free space, optical tweezers have been widely used to manipulate atoms and microscale dielectric particles. This optical force is expected to be greatly enhanced in integrated photonic circuits in which light is highly concentrated at the nanoscale. Harnessing the optical force on a semiconductor chip will allow solid state devices, such as electromechanical systems, to operate under new physical principles. Indeed, recent experiments have elucidated the radiation forces of light in high-finesse optical microcavities, but the large footprint of these devices ultimately prevents scaling down to nanoscale dimensions. Recent theoretical work has predicted that a transverse optical force can be generated and used directly for electromechanical actuation without the need for a high-finesse cavity. However, on-chip exploitation of this force has been a significant challenge, primarily owing to the lack of efficient nanoscale mechanical transducers in the photonics domain. Here we report the direct detection and exploitation of transverse optical forces in an integrated silicon photonic circuit through an embedded nanomechanical resonator. The nanomechanical device, a free-standing waveguide, is driven by the optical force and read out through evanescent coupling of the guided light to the dielectric substrate. This new optical force enables all-optical operation of nanomechanical systems on a CMOS (complementary metal-oxide-semiconductor)-compatible platform, with substantial bandwidth and design flexibility compared to conventional electrical-based schemes. PMID:19037311

Li, Mo; Pernice, W H P; Xiong, C; Baehr-Jones, T; Hochberg, M; Tang, H X

2008-11-27

174

Coaxial inverted geometry transistor having buried emitter  

NASA Technical Reports Server (NTRS)

The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

Hruby, R. J.; Cress, S. B.; Dunn, W. R. (inventors)

1973-01-01

175

Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration  

E-print Network

Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring ...

Sredojevi?, Ranko Radovin.

2008-01-01

176

Design for manufacturability with regular fabrics in digital integrated circuits  

E-print Network

Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the ...

Gazor, Mehdi (Seyed Mehdi)

2005-01-01

177

Indium phosphide based photonic integrated circuits  

NASA Astrophysics Data System (ADS)

The continued advancement of growth and processing technology in compound semiconductor materials has opened up new possibilities for the creation of complex photonic devices and circuits. This dissertation discusses the design and development of a photonic circuit based on the monolithic integration of a widely tunable laser with an on chip wavelength monitor. The widely tunable laser is a four-section device with a pair of sampled grating distributed Bragg reflector mirrors. This enables it to use a Vernier effect tuning mechanism to overcome the Deltan/n characteristic which limits the wavelength range of conventional injection tuned semiconductor lasers. Index tuning in the laser is improved by using a thick low band gap waveguide with an optimized grating etch and regrowth technique. A record 22 nm quasi-continuous tuning range has been demonstrated for a ridge waveguide device. For even greater tuning range, a buried heterostructure device was developed that is capable of tuning over more than 47 nm, enabling it to cover almost 60 DWDM wavelength channels. The complexity of the tuning mechanism in these devices makes it desirable to have a wavelength monitor to provide feedback for control of the laser. In this work, we have developed a compact integrated wavelength monitor that can be fabricated on chip with the tunable sampled grating DBR laser. The wavelength monitor takes advantage of two-mode interference in a semiconductor waveguide to create a wavelength dependent splitter. Monitors based on this principle have been successfully integrated with both ridge waveguide and buried heterostructure sampled grating DBR lasers. This dissertation reviews all of the aspects of the design, growth, processing and packaging of these devices.

Mason, Thomas Gordon Beck

178

Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits  

NASA Astrophysics Data System (ADS)

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

Sutton, Akil K.

179

Integrated photo-responsive metal oxide semiconductor circuit  

NASA Technical Reports Server (NTRS)

An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

Jhabvala, Murzban D. (inventor); Dargo, David R. (inventor); Lyons, John C. (inventor)

1987-01-01

180

Characterization of Schottky barrier carbon nanotube transistors and their applications to digital circuit design  

E-print Network

The difficulty in shrinking silicon transistors past a certain feature size has been acknowledged for years. Carbon nanotubes (CNTs) offer a technology with an exciting solution to the scaling issues of transistors and ...

Cline, Julia Van Meter, 1979-

2004-01-01

181

Integrated circuit metrology by multilevel patterning technology  

NASA Astrophysics Data System (ADS)

A low cost, high accuracy method is described in detail for measuring image placement in integrated circuit manufacture. The method measures both the overlay between levels and the absolute placement of features in a single level. The overlay is measured by a technique which views multiple levels separately. The absolute distances between features on a test wafer are measured by comparing the features to precision gratings. Optical imaging techniques are described for viewing and analyzing the grating images, as well as for measuring distortions in the observing microscope and a video camera. These techniques permit image placement measurements to be made to an accuracy limited by that of available gratings, at present about 2 nm. In addition they were applied to a prototype encoder system, demonstrating the potential improvement in commercial encoders by a factor of more than 100.

Jiang, Li

182

Automatic defect classification for integrated circuits  

NASA Astrophysics Data System (ADS)

While initial detection of defects is the most critical function of inspection, automatic classification of detected defects is becoming increasingly desirable. The key to better process control is reliable process measurement. The classification of defects provides valuable process diagnosis information. The hope is that machines can perform this task more reliably than humans. However, there are many problems in automating defect classification, and many of these are related to the central problems in artificial intelligence, such as knowledge representation, inferencing, and dealing with uncertainty. In this paper we pay special attention to the issues arising in the Automatic Defect Classification (ADC) of integrated circuits. We first discuss technical and system requirements, followed by an outline of the technical challenges to be overcome to develop flexible and powerful ACD tools which can be quickly customized on a user level for diverse applications.

Chou, Paul B.; Rao, A. Ravishankar; Sturzenbecker, Martin C.; Brecher, Virginia H.

1993-05-01

183

W88 integrated circuit shelf life program  

SciTech Connect

The W88 Integrated Circuit Shelf Life Program was created to monitor the long term performance, reliability characteristics, and technological status of representative WR ICs manufactured by the Allied Signal Albuquerque Microelectronics Operation (AMO) and by Harris Semiconductor Custom Integrated Circuits Division. Six types of ICs were used. A total of 272 ICs entered two storage temperature environments. Electrical testing and destructive physical analysis were completed in 1995. During each year of the program, the ICs were electrically tested and samples were selected for destructive physical analysis (DPA). ICs that failed electrical tests or DPA criteria were analyzed. Fifteen electrical failures occurred, with two dominant failure modes: electrical overstress (EOS) damage involving the production test programs and electrostatic discharge (ESD) damage during analysis. Because of the extensive handling required during multi-year programs like this, it is not unusual for EOS and ESD failures to occur even though handling and testing precautions are taken. The clustering of the electrical test failures in a small subset of the test operations supports the conclusion that the test operation itself was responsible for many of the failures and is suspected to be responsible for the others. Analysis of the electrical data for the good ICs found no significant degradation trends caused by the storage environments. Forty-six ICs were selected for DPA with findings primarily in two areas: wire bonding and die processing. The wire bonding and die processing findings are not surprising since these technology conditions had been documented during manufacturing and were determined to present acceptable risk. The current reliability assessment of the W88 stockpile assemblies employing these and related ICs is reinforced by the results of this shelf life program. Data from this program will aid future investigation of 4/3 micron or MNOS IC technology failure modes.

Soden, J.M.; Anderson, R.E.

1998-01-01

184

A TDC integrated circuit for drift chamber readout  

Microsoft Academic Search

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start\\/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 ?m CMOS technology, with 1 ns LSB realized using a

M. Passaseo; E. Petrolo; S. Veneziano

1995-01-01

185

Linearity Improvement of a Power Amplifier Using a Series LC Resonant Circuit  

Microsoft Academic Search

A radio frequency power amplifier microwave monolithic integrated circuit with a series LC resonant circuit as well as a bias control circuit for wide-band code division multiple access application is presented. The linearizer that consists of a series LC resonant circuit and base-emitter junction of a bias transistor operates as a diode rectifier circuit. A comparison between the circuits with

Ji Hoon Kim; Ki Young Kim; Chul Soon Park

2008-01-01

186

Clock and Power Distribution Networks for 3-D Integrated Circuits  

Microsoft Academic Search

Global interconnect design for three- dimensional integrated circuits is a crucial task. Despite the importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal within a multi-plane integrated system are discussed in this pa- per. The design of two 3-D test circuits addressing these issues is described.

Ioannis Savidis; Eby G. Friedman; Vasilis F. Pavlidis; Giovanni De Micheli

187

Computer aided engineering of semi-conductor integrated circuits  

Microsoft Academic Search

The objectives of this program are to remove the empiricism associated with the design and manufacturing of custom integrated circuits for military applications and to reduce the cost of these circuits by devising improved computer-aided engineering techniques. Efforts of research covered by this report are Part I, Semiconductor Device Modeling conducted by the University of Florida and, Part II, Integrated

D. P. Kennedy

1977-01-01

188

Plug-in integrated/hybrid circuit  

NASA Technical Reports Server (NTRS)

Hybrid circuitry can be installed into standard round bayonet connectors, to eliminate wiring from connector to circuit. Circuits can be connected directly into either section of connector pair, eliminating need for hard wiring to that section.

Stringer, E. J.

1974-01-01

189

Heterojunction bipolar transistor technology for data acquisition and communication  

NASA Technical Reports Server (NTRS)

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

190

Recent advances in photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Some recent advances in photonic integrated circuits are presented, including an InP-based monolithically integrated optical channel monitor, an arrayed waveguide grating (AWG) triplexer and a novel design of polarization insensitive AWGs. The optical channel monitor comprises a flat-field echelle grating and a slab photodetector array. The channel passband is flattened and widened without loss penalty. The shape of the slab waveguide detectors and the layer structure are optimized to obtain low crosstalk and low polarization dependence. It also has a smaller size due to the elimination of output waveguides. For triplexers in fiber access networks, a cross-order AWG design is proposed to overcome the device layout difficulty due to the wide spectral range of the wavelength channels. The spectral periodicity of the grating is utilized to reduce the free spectral range requirement. Consequently, the AWG can operate at a higher diffraction order with a smaller overall size. Finally, a novel design of a polarization insensitive arrayed waveguide grating is presented. Unlike conventional AWGs where the optical path length difference is obtained only in the arrayed channel waveguides, we design the star coupler regions according to Rowland circle construction with an oblique incidence/diffraction angle. As a result, the optical path length difference is produced in both the channel waveguides and the slab waveguide regions. By using the birefringence difference between the channel waveguide and the slab waveguide, a polarization dispersion compensated AWG is realized without any additional fabrication step.

He, Jian-Jun

2006-09-01

191

How will photonic integrated circuits develop?  

NASA Astrophysics Data System (ADS)

This paper explores issues associated with Photonic Integrated Circuit (PIC) research and development - with an overall goal of initiating a discussion of how PIC technology should develop and eventually be deployed with high impact. Significant research and development programs have focused on PICs for routing and switching, and computer interconnects. Most recently, the application domain of PICs has diversified greatly, and now includes analog signal processing, remote sensing, biological and chemical sensing, neural interfacing, and solar cells. A key feature of PIC technology growth has been the exploitation of high-density fabrication and packaging technology originally developed for the Silicon IC industry. PIC foundry services are emerging - and there has been a natural attempt to ascribe a "Moore's Law" to PIC scaling. Analogies to Silicon electronic scaling, however, should be used with caution. PIC complexity scaling may be driven more by the ability to access the degrees-of-freedom offered by PIC-based optical domain signal processing, rather than increasing device count. Specific examples of PIC research in chip-scale computer interconnects and integrated micro-concentrators for solar cells are highlighted.

Haney, Michael W.

2013-02-01

192

Fluoropolymer coatings for improved carbon nanotube transistor device and circuit performance  

NASA Astrophysics Data System (ADS)

We report on the marked improvements in key device characteristics of single walled carbon nanotube (SWCNT) field-effect transistors (FETs) by coating the active semiconductor with a fluoropolymer layer such as poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE). The observed improvements include: (i) A reduction in off-current by about an order of magnitude, (ii) a significant reduction in the variation of threshold voltage, and (iii) a reduction in bias stress-related instability and hysteresis present in device characteristics. These favorable changes in device characteristics also enhance circuit performance and the oscillation amplitude, oscillation frequency, and increase the yield of printed complementary 5-stage ring oscillators. The origins of these improvements are explored by exposing SWCNT FETs to a number of vapor phase polar molecules which produce similar effects on the FET characteristics as the PVDF-TrFE. Coating of the active SWCNT semiconductor layer with a fluoropolymer will be advantageous for the adoption of SWCNT FETs in a variety of printed electronics applications.

Jang, Seonpil; Kim, Bongjun; Geier, Michael L.; Prabhumirashi, Pradyumna L.; Hersam, Mark C.; Dodabalapur, Ananth

2014-09-01

193

Experimental determination of single-event upset (SEU) as a function of collected charge in bipolar integrated circuits  

NASA Technical Reports Server (NTRS)

Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.

Zoutendyk, J. A.; Malone, C. J.; Smith, L. S.

1984-01-01

194

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node  

NASA Astrophysics Data System (ADS)

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

2015-01-01

195

Reduced 30% scanning time 3D multiplexer integrated circuit applied to large array format 20KHZ frequency inkjet print heads  

E-print Network

Enhancement of the number and array density of nozzles within an inkjet head chip is one of the keys to raise the printing speed and printing resolutions. However, traditional 2D architecture of driving circuits can not meet the requirement for high scanning speed and low data accessing points when nozzle numbers greater than 1000. This paper proposes a novel architecture of high-selection-speed three-dimensional data registration for inkjet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array inkjet printheads with nozzles numbering more than 1000. This IC (Integrated Circuit) architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection (S), address (A), and power supply (P), are employed toge...

Liou, J -C

2008-01-01

196

Dual threshold voltage organic thin-film transistor technology  

E-print Network

A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The nearroom-temperature (<; 95 °C) process produces ...

Nausieda, Ivan A.

197

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...  

Federal Register 2010, 2011, 2012, 2013, 2014

...TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and Products...received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and...

2012-03-29

198

75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Certain Large Scale Integrated Circuit Semiconductor Chips and Products Containing Same...certain large scale integrated circuit semiconductor chips and products containing same...certain large scale integrated circuit semiconductor chips or products containing the...

2010-05-05

199

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and products...States after importation of certain semiconductor integrated circuit devices and...

2012-05-01

200

78 FR 16533 - Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation...  

Federal Register 2010, 2011, 2012, 2013, 2014

...337-TA-873] Certain Integrated Circuit Devices and Products Containing the Same...after importation of certain integrated circuit devices and products containing the same...after importation of certain integrated circuit devices and products containing the...

2013-03-15

201

75 FR 43553 - In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...importation of certain encapsulated integrated circuit devices and products containing same in...importation of certain encapsulated integrated circuit devices and products contains same...

2010-07-26

202

78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Docket No. 2938] Certain Integrated Circuit Devices and Products Containing the Same...complaint entitled Certain Integrated Circuit Devices and Products Containing the Same...after importation of certain integrated circuit devices and products containing the...

2013-02-14

203

77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...  

Federal Register 2010, 2011, 2012, 2013, 2014

...337-TA-786] Certain Integrated Circuits, Chipsets, and Products Containing...products that were adjudicated in Integrated Circuits I are precluded under the doctrine of...and MediaTek's infringing integrated circuits, chipsets, and products...

2012-09-18

204

77 FR 66481 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...  

Federal Register 2010, 2011, 2012, 2013, 2014

...337-TA-822] Certain Integrated Circuits, Chipsets, and Products Containing...after importation of certain integrated circuits, chipsets, and products containing...the completion of Certain Integrated Circuits, Chipsets, and Products...

2012-11-05

205

Preventing Simultaneous Conduction In Switching Transistors  

NASA Technical Reports Server (NTRS)

High voltage spikes and electromagnetic interference suppressed. Power-supply circuit including two switching transistors easily modified to prevent simultaneous conduction by both transistors during switching intervals. Diode connected between collector of each transistor and driving circuit for opposite transistor suppresses driving signal to transistor being turned on until transistor being turned off ceases to carry current.

Mclyman, William T.

1990-01-01

206

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits.  

PubMed

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at V(DD) = 80 V (70% of 1/2V(DD)) and a gain of 85. Additionally, robust SWNT complementary metal-oxide-semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C-K; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-04-01

207

Terahertz responsivity of field effect transistors versus their static channel conductivity and loading effects  

E-print Network

effects related to capacitive, inductive, and resistive coupling of the detector to the read-out circuit important ones due to low production costs and the ease of integration in electrical circuits. Recently by all studied III-V (GaAs, GaN) and silicon based transistors. Field effect transistors were recently

Levelut, Claire

208

Nanophotonic integrated circuits from nanoresonators grown on silicon.  

PubMed

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits. PMID:24999601

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-01-01

209

Nanophotonic integrated circuits from nanoresonators grown on silicon  

NASA Astrophysics Data System (ADS)

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore’s law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D.; Li, Kun; Chang-Hasnain, Connie

2014-07-01

210

Nanoscale Transistors: Advanced VLSI Devices (Introductory Lecture)  

NSDL National Science Digital Library

Contributed by Mark Lundstrom of Purdue University, this introductory lecture to nanoscale transistors is available both as a Flash video with audio and as presentation slides in PDF form (the links to these are on the right hand side of the page). The lecture introduces the course, which "examines the device physics of advanced transistors and the process, device, circuit, and systems considerations that enter into the development of new integrated circuit technologies." This is a helpful resource for nanotechnology instructors looking to introduce the concept of nanoscale transistors into their classrooms. For more from this course (lectures, assignments, etc.) click the Course Information Website link.

Lundstrom, Mark

211

Timing Verification of Adaptive Integrated Circuits  

E-print Network

timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo...

Kumar, Rohit

2014-08-01

212

Practical applications of digital integrated circuits. Part 4: Hybrid digital integrated circuits  

NASA Technical Reports Server (NTRS)

The 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Clock generators, waveform generation, signal shaping and conditioning, digital to analog conversion, and analog to digital conversion are discussed.

1974-01-01

213

Modeling of amorphous-silicon thin-film transistors for circuit simulations with SPICE  

Microsoft Academic Search

A static and dynamic model for amorphous silicon thin-film transistors is presented. The theory is based on an assumed exponential distribution of the deep states and the tail states in the energy gap. Expressions are derived that link the density of the localized states and the temperature to the drain current and the distribution of the charge in the transistor

Karim Khakzar; Ernst H. Lueder

1992-01-01

214

The Design of Integrated Circuits to Observe Brain Activity  

Microsoft Academic Search

The ability to monitor the simultaneous electrical activity of multiple neurons in the brain enables a wide range of scientific and clinical endeavors. Recent efforts to merge miniature multielectrode neural recording arrays with integrated electronics have revealed significant circuit design challenges. Weak neural signals must be amplified and filtered using low-noise circuits placed close to the electrodes themselves, but power

Reid R. Harrison

2008-01-01

215

Design Approaches to Field-Programmable Analog Integrated Circuits  

Microsoft Academic Search

The drive towards shorter design cycles for analog integrated circuits has given impetus to several developments in the area of Field-Programmable Analog Arrays (FPAAs). Various approaches have been taken in implementing structural and parametric programmability of analog circuits. Recent extensions of this work have married FPAAs to their digital counterparts (FPGAs) along with data conversion interfaces, to form Field- Programmable

DEAN R. D'MELLO; P. GLENN GULAK

1998-01-01

216

A Low Noise Readout Circuit for Integrated Electrochemical Biosensor Arrays  

E-print Network

A Low Noise Readout Circuit for Integrated Electrochemical Biosensor Arrays Jichun Zhang, Nicholas electrochemical interface circuit that is tuned to the needs of protein-based biosensor arrays and compatible biosensor output currents from 10pA to 10 A to suit a wide range of sensitivities and electrode areas

Mason, Andrew

217

Modulated pulse audio power amplifiers for integrated circuits  

Microsoft Academic Search

Silicon monolithic circuits are best suited for applications with low power dissipation. Conventional approaches to audio power amplifiers have a rather limited efficiency, and are therefore not necessarily the best choice for integrated circuits. Pulse-width modulation, however, promises an efficiency of up to 100 percent and has several other advantages. Three approaches to amplitude to pulse-width conversion are discussed and

H. Camenzind

1966-01-01

218

A CMOS Integrated Circuit for Silicon Strip Detector Readout  

Microsoft Academic Search

A system for reading out silicon strip detectors has been fabricated on a single integrated circuit. The chip consists of an array of 128 amplifiers with a single multiplexed output. Each amplifier channel has an input pad connected to a low power charge sensitive preamplifier together with a correlated double sampling circuit. The outputs of these channels are read out

P. Seller

1987-01-01

219

Deformable interconnects for conformal integrated circuits Stphanie Prichon Lacour1  

E-print Network

with the flexibility of plastic substrates. Once circuits are fabricated onto a deformable substrate, stretchable on the Au film thickness h, the Young's moduli E1 and E2 and the Poisson ratios 1 and 2 = 0.5 of goldDeformable interconnects for conformal integrated circuits Stéphanie Périchon Lacour1 , Zhenyu

Huang, Zhenyu

220

LEC GaAs for integrated circuit applications  

NASA Technical Reports Server (NTRS)

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

221

Modeling of three dimensional defects in integrated circuits  

E-print Network

Although the majority of defects found in manufacturing lines of Integrated Circuits [ IC's] have predominantly 2- Dimensional [2D] effects, there are many situations in which 2D defect models do not suffice) e.g., tall layer bulks disrupting...

Dani, Sameer Manohar

2012-06-07

222

Integrated prepulse circuits for efficient excitation of gas lasers  

NASA Technical Reports Server (NTRS)

Efficient impedance-matched gas laser excitation circuits integrally employ prepulse power generators. Magnetic switches are employed to both generate the prepulse and switch the prepulse onto the laser electrodes.

Rothe, Dietmar E. (Inventor)

1990-01-01

223

Advanced modeling of planarization processes for integrated circuit fabrication  

E-print Network

Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing ...

Fan, Wei, Ph. D. Massachusetts Institute of Technology

2012-01-01

224

Characterization and Modeling of TSV Based 3-D Integrated Circuits  

E-print Network

Characterization and Modeling of TSV Based 3-D Integrated Circuits Speaker: Prof. Ioannis Savidis Ioannis Savidis received a B.S.E. degree in Electrical and Computer Engineering and Biomedical Engineering

225

Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach  

E-print Network

Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach Yousra security problems. The new method leverages nondestructive gate-level characterization of ICs post. Characterization is done in a nondestructive way, without the need for additional circuitry or special processes

Potkonjak, Miodrag

226

Photonic integrated circuit elements (PIC) for phased array steering systems  

NASA Astrophysics Data System (ADS)

Progress will be presented regarding circuit elements to be eventually incorporated into a Photonic Integrated Circuit (PIC). Data from elements such as phase modulators and couplers will be reviewed. They have been developed employing ridge waveguides in MBE grown GaAs/AlGaAs material structures. A general approach to PICs will be discussed as well as their incorporation into optical frequency translation (OFT) modulation circuits for coherent optical systems. Detailed theoretical discussion of one, two, and four-arm phase-modulator-based OFT circuits is included.

Vawter, G. A.; Hietala, V. M.; Kravitz, S. H.; Carson, R. F.; Armendariz, M. G.; Meyer, W. J.

1992-12-01

227

Integrated circuits and systems Laboratory Programmable Gigabit Ethernet  

E-print Network

Store Comp = Comp! = Comp > Results IEEE 802.3/802.2 SNAP Encapsulation (RFC 1042) L2 Parser 4233266 CR1 Integrated circuits and systems Laboratory Programmable Gigabit Ethernet Packet processor Session Integrated Switch Integrated Switch Implementat- ion DSL T1 Ether, ATM, DSL, T1,.... All ATM (&) All Ethernet

Verbauwhede, Ingrid

228

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design and Application Considerations for  

E-print Network

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design, and Seshadri Subbanna, Member, IEEE Invited Paper Abstract--SiGe HBT transistors achieving over 200 GHz and MAX--BiCMOS integrated circuits, bipolar transistors, heterojunctions, semiconductor devices. I. INTRODUCTION BIPOLAR

Rieh, Jae-Sung

229

Above-threshold drain current model including band tail states in nanocrystalline silicon thin-film transistors for circuit implementation  

NASA Astrophysics Data System (ADS)

A simple analytical expression for the above threshold voltage drain current is derived in nanocrystalline silicon thin-film transistors (TFTs), based on an exponential energy distribution of band tail states. When the characteristic temperature distribution of the band tails is equal to 1.5 times the lattice temperature, the derived expression leads to the basic "quadratic" metal-oxide-semiconductor current expression. By including the impact ionization effect and using the same trap distribution parameters, the model describes adequately the output characteristics of TFTs with different channel dimensions, making the proposed model suitable for the design of circuits with nc-Si TFTs.

Pappas, I.; Dimitriadis, C. A.; Templier, F.; Oudwan, M.; Kamarinos, G.

2007-04-01

230

Method for double-sided processing of thin film transistors  

DOEpatents

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Yuan, Hao-Chih (Madison, WI); Wang, Guogong (Madison, WI); Eriksson, Mark A. (Madison, WI); Evans, Paul G. (Madison, WI); Lagally, Max G. (Madison, WI); Ma, Zhenqiang (Middleton, WI)

2008-04-08

231

RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates  

Microsoft Academic Search

We present dc and RF characterization of InAs nanowire field-effect transistors (FETs) heterogeneously in- tegrated on Si substrates in a geometry suitable for circuit applications. The FET consists of an array of 182 vertical InAs nanowires with about 6-nm HfO high- gate dielectric and a wrap-gate length of250nm. Thetransistor hasatransconductance of 155 mS\\/mm and an on-current of 550 mA\\/mm at

Sofia Johansson; Mikael Egard; Sepideh Gorji Ghalamestani; B. Mattias Borg; Martin Berg; Lars-Erik Wernersson; Erik Lind

2011-01-01

232

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.  

PubMed

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries. PMID:24567478

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

233

Study on Si integrated circuits operating up to 462°C  

Microsoft Academic Search

In order to develop a silicon IC operating up to and above 450°C, integrated injection logic (IIL) was chosen for its peculiar characteristics to high temperature operation. New structures for the IIL were designed through the experimental and theoretical studies of p-n junctions, transistors, and IILs at high temperature. We made Si ICs consisting of nine-stage ILL ring-oscillators by fabrication

Masatoshi Migitaka

1998-01-01

234

Metallization technology for tenth-micron range integrated circuits  

SciTech Connect

A critical step in the fabrication of integrated circuits is the deposition of metal layers which interconnect the various circuit elements that have been formed in earlier process steps. In particular, columns of copper several times higher than the characteristic dimension of the circuit elements was needed. Features with a diameter of a few tenths of a micron and a height of about one micron need to be filled at rates in the half to one micron per minute range. With the successful development of a copper deposition technology meeting these requirements, integrated circuits with simpler designs and higher performance could be economically manufactured. Several technologies for depositing copper were under development. No single approach had an optimum combination of performance (feature characteristics), cost (deposition rates), and manufacturability (integration with other processes and tool reliability). Chemical vapor deposition, plating, sputtering and ionized-physical vapor deposition (I-PVD) were all candidate technologies. Within this project, the focus was on I-PVD.

Berry, L.A.; Harper, M.E.

1996-11-27

235

Microwave GaAs Integrated Circuits On Quartz Substrates  

NASA Technical Reports Server (NTRS)

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

236

An organic thin-film transistor circuit for large-area temperature-sensing  

E-print Network

This thesis explores the application of organic thin-film transistors (OTFTs) for temperature-sensing. The goal of this work is twofold: the understanding of the OTFT's electrical characteristics' temperature dependence, ...

He, David Da

2008-01-01

237

Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign  

E-print Network

''s Laws Law # In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 transistors 1.5 GHz operation ~ 15,000 x Automotive comparison: SF to NY in 13 seconds. EE134 18 MooreMoore months #12;EE134 19 MooreMoore''s Laws Law 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962

238

Organic thin-film transistors: flexible low-voltage organic complementary circuits: finding the optimum combination of semiconductors and monolayer gate dielectrics (adv. Mater. 2/2015).  

PubMed

The observation that n-channel organic semiconductors perform better when deposited onto fluoroalkyl self-assembled monolayers (SAMs) while p-channel semiconductors perform better on alkyl SAMs raises the question as to which SAM to employ in complementary circuits. As U. Kraft and co-workers describe on page 207, the answer depends on the transistor's contact resistance and hence the channel length. Here, a signal delay of 3.1 ?s is measured in -circuits based on transistors with a channel length of 1 ?m. PMID:25572849

Kraft, Ulrike; Sejfi?, Mirsada; Kang, Myeong Jin; Takimiya, Kazuo; Zaki, Tarek; Letzkus, Florian; Burghartz, Joachim N; Weber, Edwin; Klauk, Hagen

2015-01-01

239

Integrated Power Divider for Superconducting Digital Circuits  

Microsoft Academic Search

We present design, analys is and test of as upercon- ducting microwave power divider for a new superconducting Reciprocal Quantum Logic (RQL). The RQL logic family, using combination of AC power and SFQ data encoding, allows scalable superconducting digital circuits with zero static power dissipa- tion. The Wilkinson 1:8 power splitter\\/combiner based on resonators has been analyzed for geometric series

Oliver T. Oberg; Quentin P. Herr; Alexander G. Ioannidis; Anna Y. Herr

2011-01-01

240

Inverted process for graphene integrated circuits fabrication.  

PubMed

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB. PMID:24745037

Lv, Hongming; Wu, Huaqiang; Liu, Jinbiao; Huang, Can; Li, Junfeng; Yu, Jiahan; Niu, Jiebin; Xu, Qiuxia; Yu, Zhiping; Qian, He

2014-06-01

241

Inverted process for graphene integrated circuits fabrication  

NASA Astrophysics Data System (ADS)

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB.CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB. Electronic supplementary information (ESI) available: Optical images and Raman spectrum of graphene, AFM image of the buried gate stack. See DOI: 10.1039/c3nr06904d

Lv, Hongming; Wu, Huaqiang; Liu, Jinbiao; Huang, Can; Li, Junfeng; Yu, Jiahan; Niu, Jiebin; Xu, Qiuxia; Yu, Zhiping; Qian, He

2014-05-01

242

Leak Detection of Integrated Circuits and Other Semiconductor Devices on Multilayer Circuit Boards  

Microsoft Academic Search

The radioisotope leak test has been modified to detect leaks, in integrated circuits and other devices mounted onto multilayer circuit boards, over the entire range from 10¿1 to 10¿8 atm. cc per second. The method combines radiation shielding techniques with three sequential tests using krypton-85. The test program has succeeded in detecting a significant number of leaky components on electronic

A. G. Stanley; C. M. Rader; G. Neff

1974-01-01

243

Database Structure and Discovery Tools for Integrated Circuit Reliability Evaluation  

Microsoft Academic Search

The reliability performance of integrated circuits is described by means of a large amount of quantitative and qualitative data that require computer tools for effective management. The author describes some design solutions in the implementation of these tools, in particular stressing the integration of different points of view to model reliability performance; the structure of the failure database that, following

Paola Mauri

1992-01-01

244

Simulation of proton-induced energy deposition in integrated circuits  

NASA Technical Reports Server (NTRS)

A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

Fernald, Kenneth W.; Kerns, Sherra E.

1988-01-01

245

A NOVEL LEAKAGE-TOLERANT DOMINO LOGIC CIRCUIT WITH FEEDBACK FROM FOOTER TRANSISTOR IN ULTRA  

E-print Network

SUBMICRON CMOS F. MORADI 1 , A. PEIRAVI 2 , H. MAHMOODI 3 1 ISLAMIC AZAD UNIVERSITY (ISLAM SHAHR UNIT), IRAN proposed circuit increases the noise immunity by least 2X compared to previous circuits. INTRODUCTION

Mahmoodi, Hamid

246

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon  

E-print Network

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon K. Pangal,a) J. C. Sturm, and S. Wagner Department of Electrical Engineering 1999 Selective exposure of a hydrogenated amorphous silicon a-Si:H film to a room-temperature hydrogen

247

Advanced tools for integrated circuit design  

E-print Network

processing. 2. The language of the data processor should be easy to understand and simple to use, to circuit designers who are usually not exposed to complicated program- ming techniques. 10 3. It should be able to perform all scientific mathematical... descriptions about the various statements in Name of the Vector Type Size Pointer to Contents CONTENTS OF MEMORY MANAGER TABLE ELEMENT vector 1 vector 2 vector 3 vector n vector (n + I) TABLE ORGANIZATION OF VECTORS ACTUAL MEMORY Fig. 2...

Dubagunta, Sai Kumar

2012-06-07

248

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

2012-06-07

249

Current-source aSi:H thin-film transistor circuit for active-matrix organic light-emitting displays  

Microsoft Academic Search

In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as ?3 V, the output current variations can be less than 1

Yi He; Reiji Hattori; Jerzy Kanicki

2000-01-01

250

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking  

Microsoft Academic Search

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the

Jie Deng; H.-S. Philip Wong

2007-01-01

251

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers  

NASA Astrophysics Data System (ADS)

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized

Hsu, Yu-Jen

252

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor  

SciTech Connect

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M., E-mail: muhammadmustafa.hussain@kaust.edu.sa [Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical Mathematical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia)

2013-11-25

253

Photonic integrated circuits based on silica and polymer PLC  

NASA Astrophysics Data System (ADS)

Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

Izuhara, T.; Fujita, J.; Gerhardt, R.; Sui, B.; Lin, W.; Grek, B.

2013-03-01

254

76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Certain Large Scale Integrated Circuit Semiconductor Chips and Products Containing the Same...certain large scale integrated circuit semiconductor chips and products containing same...including the following: Freescale Semiconductor Xiqing Integrated Semiconductor...

2011-03-17

255

High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel  

NASA Astrophysics Data System (ADS)

Polycrystalline silicon thin-film transistors (TFTs) integrating sputtered Al2O3 gate dielectric with bridged-grain active channel are demonstrated. The proposed TFTs exhibit excellent device performance in terms of smaller threshold voltage, steeper subthreshold swing and higher on-current/off-current ratio. More importantly, the mobility of the proposed TFT is 5.5 times that of conventional TFTs with SiO2 gate dielectric. All of these results suggest that the proposed TFT is a good choice for low-power and high-speed driving circuits in display application.

Zhang, Meng; Zhou, Wei; Chen, Rongsheng; Wong, Man; Kwok, Hoi-Sing

2013-11-01

256

Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign  

E-print Network

MooreMoore''s Laws Law # In 1965, Gordon Moore noted that the number of transistors on a chip doubled of text. EE134 6 Last LectureLast Lecture ! Last lecture " Moore's Law " Challenges in digital IC design for next decade ! Today " Review of Moore's Law " Design metrics #12;EE134 7 Summarizes progress

257

Integration of self-assembled carbon nanotube transistors: statistics and gate engineering at the wafer scale  

Microsoft Academic Search

We present a full process based on chemical vapour deposition that allows fabrication and integration at the wafer scale of carbon-nanotube-based field effect transistors. We make a statistical analysis of the integration yield that allows assessment of the parameter fluctuations of the titanium-nanotube contact obtained by self-assembly. This procedure is applied to raw devices without post-process. Statistics at the wafer

L. Marty; A. Bonhomme; A. Iaia; E. André; E. Rauwel; C. Dubourdieu; A. Toffoli; F. Ducroquet; A. M. Bonnot; V. Bouchiat

2006-01-01

258

3D circuit integration for Vertex and other detectors  

SciTech Connect

High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

Yarema, Ray; /Fermilab

2007-09-01

259

Programmable delay unit incorporating a semi-custom integrated circuit  

NASA Astrophysics Data System (ADS)

The synchronization of Stanford Linear Collider (SLC) accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given.

Linstadt, E.

1985-04-01

260

Thermally-induced voltage alteration for integrated circuit analysis  

DOEpatents

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Cole, Jr., Edward I. (Albuquerque, NM)

2000-01-01

261

Single Event Transients in Linear Integrated Circuits  

NASA Technical Reports Server (NTRS)

On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed to transients. In some cases, such events produced resets by falsely triggering circuits designed to protect against over- voltage or over-current. On at least three occasions, transients caused satellites to switch into "safe mode" in which most of the systems on board the satellites were powered down for an extended period. By the time the satellites were reconfigured and returned to full operational state, much scientific data had been lost. Fortunately, no permanent damage occurred in any of the systems and they were all successfully re-activated.

Buchner, Stephen; McMorrow, Dale

2005-01-01

262

Healing of voids in the aluminum metallization of integrated circuit chips  

NASA Technical Reports Server (NTRS)

The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas R.

1990-01-01

263

Control technology for integrated circuit fabrication at MicroCircuit Engineering, Incorporated, West Palm Beach, Florida  

Microsoft Academic Search

A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching,

G. I. Mihlan; R. I. Mitchell; R. K. Smith

1984-01-01

264

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes  

NASA Astrophysics Data System (ADS)

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr05471g

Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng

2014-11-01

265

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems  

NASA Astrophysics Data System (ADS)

This interim technical report presents results of research on the computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems. A specific objective is to extend the state-of-the-art of the Computer Aided Design (CAD) of the monolithic microwave and millimeter wave integrated circuits (MIMIC). In this reporting period, we have derived a new model for the high electron mobility transistor (HEMT) based on a nonlinear charge control formulation which takes into consideration the variation of the 2DEG distance offset from the heterointerface as a function of bias. Pseudomorphic InGaAs/GaAs HEMT devices have been successfully fabricated at UCSD. For a 1 micron gate length, a maximum transconductance of 320 mS/mm was obtained. In cooperation with TRW, devices with 0.15 micron and 0.25 micron gate lengths have been successfully fabricated and tested. New results on the design of ultra-wideband distributed amplifiers using 0.15 micron pseudomorphic InGaAs/GaAs HEMT's have also been obtained. In addition, two-dimensional models of the submicron MESFET's, HEMT's and HBT's are currently being developed for the CRAY X-MP/48 supercomputer. Preliminary results obtained are also presented in this report.

Ku, Walter H.

1987-08-01

266

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes.  

PubMed

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfO(x) thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ? 46.2 cm(2) V(-1) s(-1), 10(5) and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates. PMID:25363072

Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng

2014-12-21

267

Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits  

E-print Network

Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits Aris Christou Materials of the failure rate of each component due to interaction effects of the failed components. The Monte Carlo failure rates become nonconstant. The Monte Carlo technique is an appropriate methodology used to treat

Rubloff, Gary W.

268

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Myers, D.R.

1989-09-12

269

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess  

E-print Network

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault of the two methods. We con­ clude that the new simulation method, Wire Memory bridge fault simulation

Larrabee, Tracy

270

Hybrid Silicon Evanescent Photonic Integrated Circuit John E. Bowersa  

E-print Network

Hybrid Silicon Evanescent Photonic Integrated Circuit Technology John E. Bowersa , Alexander W, Israel Email: bowers@ece.ucsb.edu (Invited Paper) Abstract: The hybrid silicon evanescent device platform utilizes III-V gain materials bonded to passive silicon waveguides. In this paper, we discuss this device

Bowers, John

271

Side face excited microstructured fibers for photonic integrated circuits formations  

E-print Network

In the paper, we propose the new technology for mass production of the photonic crystal devices and all-optical integrated circuits. We carry out the brief analysis of positive and negative sides paying attention to recent advances in silicon fibers fabrication which is crucial moment in the proposed technology.

Guryev, Igor V; Lucio, J -A Andrade; Alvarado-Mendez, E

2010-01-01

272

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Myers, David R. (Albuquerque, NM)

1989-01-01

273

DNA chips --Integrated Chemical Circuits for DNADiagnosis and DNA computers  

E-print Network

DNA chips -- Integrated Chemical Circuits for DNADiagnosis and DNA computers Akira Suyama, Associate Professor Institute of Physics, Graduate School of Arts and Sciences, The University of Tokyo DNA chips are si l i con­ or glass­based smal l surfaces on which many DNA ol i gonuc l eotides are i

Hagiya, Masami

274

Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia  

DOEpatents

Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

2007-04-24

275

Analog Integrated Circuits Design for Processing Physiological Signals  

Microsoft Academic Search

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this

Yan Li; Carmen C. Y. Poon; Yuan-Ting Zhang

2010-01-01

276

Floating gate power supply of multilevel converters for circuit integration  

Microsoft Academic Search

There is the possibility of the intrinsic elimination of harmonics and electromagnetic interference (EMI) by introducing multilevel converters with a large number of levels. As the number of levels increases, the number of the main switching devices on their higher side increases, and their floating gate power supplies become larger scale circuits. Because it is necessary to integrate the floating

Masamu Kamaga; Kyungmin Sung; Jin Xu; Yukihiko Sato; Hiromichi Ohashi

2009-01-01

277

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Myers, D.R.

1988-04-20

278

Performance Trend in Three-Dimensional Integrated Circuits Author list  

E-print Network

silicon on insulator (FDSOI) process [10]. This flow uses carefully designed scripts to fill the gap between 2D methodologies and 3D designs. We examine wire-length, timing, clock skew, and total power dissipation, along with temperature, of two benchmark circuits implemented in both 2D and 3D integration. We

Davis, Rhett

279

Gas Cooling Enhancement Technology for Integrated Circuit Chips  

Microsoft Academic Search

New approaches are described for increasing the capability of forced gas convection cooling for integrated circuit chips, using an enhanced heat transfer technique and a higher gas flow velocity in a closed-cycle flow. A turbulence promoting fin with low pressure loss has been developed and enhancement of the heat transfer coefficient using gas flow velocities up to 50 m\\/s is

TOHRU KISHIMOTO; ETSURO SASAKI; KUNIO MORIYA

1984-01-01

280

Integrated Micromechanical Circuits Fueled By Vibrating RF MEMS Technology  

Microsoft Academic Search

Having now produced devices with sufficient Q, thermal stability, aging stability, and manufacturability, vi- brating RF MEMS technology is already finding its way into next generation timing and wireless applications. At this junc- ture, the technology is now poised to take its next logical steps: higher levels of circuit complexity and integration. In particu- lar, as vibrating RF MEMS devices

Clark T.-C. Nguyen

2006-01-01

281

1998 technology roadmap for integrated circuits used in critical applications  

SciTech Connect

Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

Dellin, T.A.

1998-09-01

282

An Optical Phase-Locked Loop Photonic Integrated Circuit  

Microsoft Academic Search

We present the design, fabrication, and results from the first monolithically integrated optical phase-locked loop (OPLL) photonic integrated circuit (PIC) suitable for a variety of homodyne and offset phase locking applications. This InP-based PIC contains two sampled-grating distributed reflector (SG-DBR) lasers, semiconductor optical amplifiers (SOAs), phase modulators, balanced photodetectors, and multimode interference (MMI)-couplers and splitters. The SG-DBR lasers have more

Sasa Ristic; Ashish Bhardwaj; Mark J. Rodwell; Larry A. Coldren; Leif A. Johansson

2010-01-01

283

Enhanced heterostructure field effect transistor CAD model suitable for simulation of mixed mode circuits  

Microsoft Academic Search

We describe a new enhanced model for deep submicron heterostructure field effect transistors (HFET's) suitable for implementation in computer aided design (CAD) software packages such as SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of both n- and p-channel deep submicron HFET's over the temperature range 250-450 K. The current-voltage (I-V) characteristics are described by a single, continuous,

Trond Ytterdal; Tor A. Fjeldly; Michael S. Shur; Steven M. Baier; R. Lucero

1999-01-01

284

Organic thin-film transistors for circuits in a foundry: process, charge transport phenomena and device library  

NASA Astrophysics Data System (ADS)

For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.

Pankalla, Sebastian; Ganz, Simone; Spiehl, Dieter; Dörsam, Edgar; Glesner, Manfred

2013-09-01

285

A PWM transistor inverter for an ac electric vehicle drive  

NASA Technical Reports Server (NTRS)

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Slicker, J. M.

1981-01-01

286

A PWM transistor inverter for an ac electric vehicle drive  

NASA Astrophysics Data System (ADS)

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Slicker, J. M.

1981-10-01

287

Radiation damage in MOS integrated circuits, Part 1  

NASA Technical Reports Server (NTRS)

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Danchenko, V.

1971-01-01

288

Integrated optical detection circuit for magneto-optical drive  

NASA Astrophysics Data System (ADS)

An integrated optical circuit (IOC) combining all the detection functions of a standard magneto-optical reading head (MO reading, focus and tracking control) is presented. The reading function is achieved by means of a patented interferometric circuit. For tracking control, the well-known push-pull method has been applied and adapted to integrated optics. In this case, the role of the IOC is just to separate the beam reflected back from the disc in two halves in order to compare their intensity. For focus control, several principles have been tested: standard ones adapted to integrated optics (`wax-wane' method or Foucault knife-edge) and an original method based on multimode interferences, taking benefits of integrated optics specificity. The implemented technology is based on a silicon substrate with a silicon nitride core between two silica cladding layers (Si/SiO2/Si3N4/SiO2). This technology is a low cost technology well adapted for mass production. The optical components of the circuits are made by standard contact photolithography and reactive ion etching. Several wafers with about 50 devices each, have been processed and characterized. In particular, the detection signals have been compared with the detection signals delivered simultaneously by a Philips-IBM 128 MB MO drive. This experiment demonstrates the feasibility of an integrated detection device for MO drive.

Mottier, Patrick L.; Lapras, V.; Chabrol, C.

1995-02-01

289

Millimeter-wave and terahertz integrated circuit antennas  

NASA Technical Reports Server (NTRS)

This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

Rebeiz, Gabriel M.

1992-01-01

290

Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators  

Microsoft Academic Search

A large-area, flexible, and lightweight sheet-type Braille display has been successfully fabricated on a plastic film by integrating high-quality organic transistors and soft actuators. An array of rectangular plastic actuators is mechanically processed from a perfluorinated polymer electrolyte membrane. A small semisphere, which projects upward from the rubberlike surface of the display, is attached to the tip of each rectangular

Yusaku Kato; Tsuyoshi Sekitani; Makoto Takamiya; Masao Doi; Kinji Asaka; Takayasu Sakurai; Takao Someya

2007-01-01

291

77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...  

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...COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same...sale within the United States after importation of certain semiconductor integrated circuit devices and products containing...

2012-07-03

292

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...  

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...Investigation No. 337-TA-665] In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...sale within the United States after importation of certain semiconductor integrated circuits and products containing same by...

2010-02-04

293

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...  

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...COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same...sale within the United States after importation of certain semiconductor integrated circuit devices and products containing...

2012-10-04

294

75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Investigation No. 337-TA-648] Certain Semiconductor Integration Circuits Using Tungsten...States after importation of certain semiconductor integrated circuits using tungsten...remained in the investigation: Tower Semiconductor, Ltd. of Israel; Jazz...

2010-12-06

295

77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...  

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...Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products Containing Same; Commission...of certain integrated circuit packages provided with multiple heat-conducting paths and products containing same by reason...

2012-12-12

296

77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Investigation No. 337-TA-786] Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions...specifically a limited exclusion order against certain integrated circuits, chipsets, and products containing the same including...

2012-07-20

297

Focal plane infrared readout circuit  

NASA Technical Reports Server (NTRS)

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

Pain, Bedabrata (Inventor)

2002-01-01

298

Thermoreflectance temperature imaging of integrated circuits: calibration technique and quantitative comparison with integrated sensors and simulations  

Microsoft Academic Search

Camera-based thermoreflectance microscopy is a unique tool for high spatial resolution thermal imaging of working integrated circuits. However, a calibration is necessary to obtain quantitative temperatures on the complex surface of integrated circuits. The spatial and temperature resolutions reached by thermoreflectance are excellent (360 nm and 2.5 × 10-2 K in 1 min here), but the precision is more difficult

G. Tessier; M.-L. Polignano; S. Pavageau; C. Filloy; D. Fournier; F. Cerutti; I. Mica

2006-01-01

299

An analogue test technique for massively parallel integrated circuits and systems: An approach to neural networks circuits testing  

Microsoft Academic Search

\\u000a Abstract  The increase in integration density and in complexity of moderns integrated circuits and systems revealed the necessity to\\u000a consider the testability problem at the design level of circuits. One of the most active research areas in circuits design,\\u000a over the past decade, has been the implementation of neural networks as electronic VLSI chips. Especially, the implementation\\u000a of artificial neural networks

Kurosh Madani

1993-01-01

300

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering  

SciTech Connect

Ambipolar semiconducting polymers, characterized by both high electron (?{sub e}) and hole (?{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with ?{sub h}?=?0.29 cm{sup 2}/V s and ?{sub e}?=?0.001 cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with ?{sub e}?=?0.12 cm{sup 2}/V s and ?{sub h}?=?8 ×?10{sup ?4}?cm{sup 2}/V?s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Dell'Erba, Giorgio; Natali, Dario [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano (Italy); Luzio, Alessandro; Caironi, Mario, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu [Heeger Center for Advanced Materials, School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwagiro, Buk-gu, Gwangju 500-712 (Korea, Republic of); Noh, Yong-Young, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Department of Energy and Materials Engineering, Dongguk University, 26 Pil-dong, 3-ga, Jung-gu, Seoul 100-715 (Korea, Republic of)

2014-04-14

301

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations  

PubMed Central

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ?1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ?140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

2008-01-01

302

Attachment method for stacked integrated circuit (IC) chips  

DOEpatents

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Bernhardt, Anthony F. (Berkeley, CA); Malba, Vincent (Livermore, CA)

1999-01-01

303

Attachment method for stacked integrated circuit (IC) chips  

DOEpatents

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Bernhardt, A.F.; Malba, V.

1999-08-03

304

77 FR 1505 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...  

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...337-TA-822] Certain Integrated Circuits, Chipsets, and Products Containing...importation of certain integrated circuits, chipsets, and products containing...importation of certain integrated circuits, chipsets, and products containing...Irvine, CA 92618. Sanyo Electric Co., Ltd., 5-5...

2012-01-10

305

76 FR 41521 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...  

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...Matter of Certain Integrated Circuits, Chipsets, and Products Containing...importation of certain integrated circuits, chipsets, and products containing...importation of certain integrated circuits, chipsets, and products containing...complaint is to be served: Funai Electric Co., Ltd., 7-7-1...

2011-07-14

306

76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...  

Federal Register 2010, 2011, 2012, 2013, 2014

...DN 2860] Certain Integrated Circuits, Chipsets, and Products Containing...entitled In Re Certain Integrated Circuits, Chipsets, And Products Containing...importation of certain integrated circuits, chipsets, and products containing...Inc. of Irvine, CA; Sanyo Electric Co., Ltd. of Japan;...

2011-12-07

307

The 11th International Symposium on Wireless Personal Multimedia Communications (WPMC 2008) DEVELOPMENT OF THZ TRANSISTORS  

E-print Network

) DEVELOPMENT OF THZ TRANSISTORS AND (300-3000 GHZ) SUB-MM-WAVE INTEGRATED CIRCUITS Mark Rodwell, E. Lobisser, M of 1-3 THz. High bandwidths are obtained by scaling; the critical limits to such scaling maxf and 324 GHz amplifiers have been demonstrated. Transistors with target maxf over 1 THz

Rodwell, Mark J. W.

308

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications  

NASA Technical Reports Server (NTRS)

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

1987-01-01

309

Aperture efficiency of integrated-circuit horn antennas  

NASA Technical Reports Server (NTRS)

The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent at 93 GHz. This is sufficient for use in many applications which now use machined waveguide horns.

Guo, Yong; Lee, Karen; Stimson, Philip; Potter, Kent; Rutledge, David

1991-01-01

310

Extended life testing evaluation of complementary MOS integrated circuits  

NASA Technical Reports Server (NTRS)

The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

Brosnan, T. E.

1972-01-01

311

High performance CMOS integrated circuits for optical receivers  

E-print Network

to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Aydin Karsilayan Committee Members, Jose Silva-Martinez Reza Langari... Prasad Enjeti Head of Department, Costas Georghiades December 2006 Major Subject: Electrical Engineering iii ABSTRACT High Performance CMOS Integrated Circuits for Optical Receivers. (December 2006) MohammadReza SamadiBoroujeni, B...

SamadiBoroujeni, MohammadReza

2009-05-15

312

Integrated circuits for data transmission over twisted-pair channels  

Microsoft Academic Search

This paper discusses typical architectures and challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are discussed-high-bit-rate digital subscriber loop (HDSL) and fast-Ethernet. Although these two applications have orders of magnitude difference in their bit rates, they share many common building blocks including line-drivers, 24 wire hybrids, echo

David A. Johns; Daniel Essig

1997-01-01

313

Aperture efficiency of integrated-circuit horn antennas  

Microsoft Academic Search

The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent

Yong Guo; Karen Lee; Philip Stimson; Kent Potter; David Rutledge

1991-01-01

314

Monolithic microwave integrated circuit technology for advanced space communication  

NASA Technical Reports Server (NTRS)

Future Space Communications subsystems will utilize GaAs Monolithic Microwave Integrated Circuits (MMIC's) to reduce volume, weight, and cost and to enhance system reliability. Recent advances in GaAs MMIC technology have led to high-performance devices which show promise for insertion into these next generation systems. The status and development of a number of these devices operating from Ku through Ka band will be discussed along with anticipated potential applications.

Ponchak, George E.; Romanofsky, Robert R.

1988-01-01

315

Advanced polymer systems for optoelectronic integrated circuit applications  

Microsoft Academic Search

An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness,

Louay A. Eldada; Kelly M. Stengel; Lawrence W. Shacklette; Robert A. Norwood; Chengzeng Xu; Chengjiu Wu; James T. Yardley

1997-01-01

316

Microwave integrated Schottky-barrier-diode mixer circuits  

Microsoft Academic Search

The paper gives attention to the design and electrical properties of different types of hybrid microwave integrated mixers, with special consideration given to broadband single and double balance mixers. The basic characteristics of Schottky-barrier mixer diodes are reviewed. It is found that complex phase-suppression circuits can be used along with narrowband filters to suppress the reception mirror-channel. An analytical study

N. P. Banshchikov; A. M. Zubkov

1977-01-01

317

An integrated circuit for reading out signals of silicon detectors  

Microsoft Academic Search

An integrated circuit (IC) for recording signals and studying characteristics of silicon detectors is designed and experimentally\\u000a checked. The basic purpose of the IC is to use it in test setups with sources of ionizing radiation and on accelerators for\\u000a studying silicon detectors of a new geometry (layout). The IC allows evaluation of the operation of the “silicon detector-readout\\u000a electronics”

E. V. Atkin; A. G. Voronin; Yu. A. Volkov; A. D. Klyuev; A. Yu. Pakhomov; A. S. Silaev

2010-01-01

318

Evaluation of AlGaN\\/GaN Heterostructure Field-Effect Transistors on Si Substrate in Power Factor Correction Circuit  

Microsoft Academic Search

A new device of high-power AlGaN\\/GaN heterostructure field-effect transistors (HFETs) fabricated on a Si substrate is proposed. Its application of the power factor correction (PFC) circuit is presented for the first time. The AlGaN\\/GaN HFETs fabricated on the Si substrate with a gate width of 152 mm exhibited a breakdown voltage of more than 800 V, an on-resistance of 65

Shinichi Iwakami; Osamu Machida; Yoshimichi Izawa; Ryohei Baba; Masataka Yanagihara; Toshihiro Ehara; Nobuo Kaneko; Hirokazu Goto; Akio Iwabuchi

2007-01-01

319

Miniaturized ultrasound imaging probes enabled by CMUT arrays with integrated frontend electronic circuits  

Microsoft Academic Search

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement

B. T. Khuri-Yakub; Ömer Oralkan; A. Nikoozadeh; I. O. Wygant; S. Zhuang; M. Gencel; Jung Woo Choe; D. N. Stephens; A. de la Rama; P. Chen; Feng Lin; A. Dentinger; D. Wildes; K. Thomenius; K. Shivkumar; A. Mahajan; Chi Hyung Seo; M. O'Donnell; Uyen Truong; D. J. Sahn

2010-01-01

320

InGaAs/InP heterojunction bipolar transistors for ultra-low power circuit applications  

SciTech Connect

For many modern day portable electronic applications, low power high speed devices have become very desirable. Very high values of f{sub T} and f{sub MAX} have been reported with InGaAs/InP heterojunction bipolar transistors (HBTs), but only under high bias and high current level operating conditions. An InGaAs/InP ultra-lowpower HBT with f{sub MAX} greater than 10 GHz operating at less than 20 {micro}A has been reported for the first time in this work. The results are obtained on a 2.5 x 5 {micro}m{sup 2} device, corresponding to less than 150 A/cm{sup 2} of current density. These are the lowest current levels at which f{sub MAX} {ge} 10 GHz has been reported.

Chang, P.C.; Baca, A.G.; Hafich, M.J.; Ashby, C.I.

1998-08-01

321

A new patterning process concept for large-area transistor circuit fabrication without using an optical mask aligner  

Microsoft Academic Search

A new concept to produce large thin film transistor liquid crystal displays (TFT-LCD's) without using an optical mask aligner is proposed which emphasizes patterning technology. Some experimental thin film transistors (TFT's) are fabricated according to the concept and operated like conventional transistors fabricated by using an optical mask aligner. The concept includes improvement of printing technology and development of a

Yoshiro Mikami; Yoshiharu Nagae; Yuji Mori; Kazuhiro Kuwabara; Takeshi Saito; H. Hayama; H. Asada; Y. Akimoto; M. Kobayashi; S. Okazaki; K. Asaka; H. Matsui; K. Nakamura; E. Kaneko

1994-01-01

322

High density vertical interconnects for 3-D integration of silicon integrated circuits  

Microsoft Academic Search

This paper describes a technology platform being developed for three-dimensional (3-D) integration of thin stacked silicon integrated circuits (ICs). 3-D integration technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator array devices hybridized with silicon read-out electronics. Currently, advanced 3-D integrated infrared focal plane array detectors are being developed within the DARPA vertically

C. A. Bower; D. Malta; D. Temple; J. E. Robinson; P. R. Coffinan; M. R. Skokan; T. B. Welch

2006-01-01

323

Neuromorphic opto-electronic integrated circuits for optical signal processing  

NASA Astrophysics Data System (ADS)

The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

2014-08-01

324

Boron nitride housing cools transistors  

NASA Technical Reports Server (NTRS)

Boron nitride ceramic heat sink cools transistors in r-f transmitter and receiver circuits. Heat dissipated by the transistor is conducted by the boron nitride housing to the metal chassis on which it is mounted.

1965-01-01

325

Pneumatic oscillator circuits for timing and control of integrated microfluidics  

PubMed Central

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

2013-01-01

326

A CMOS integrated circuit for pulse-shaped discrimination  

NASA Astrophysics Data System (ADS)

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the zero crossing of the shaped signal. The circuit is designed to interface with two photomultiplier tubes -- one for pulse processing and one for coincidence detection. Two Outputs from the IC, a start and stop, can be used with a high speed timing system for pulse characterization with minimal external control. The circuit was fabricated in Orbit 1.2 micrometer CMOS and operates from a 5-V supply. Specifics of the design including overall topology, charge sensitive preamplifier and CFD characteristics, shaping method and time constant selections, system timing, and implementation are discussed. Circuit performance is presented including dynamic range, timing walk, system dead time, and power consumption.

Frank, S. S.; Ericson, M. N.; Simpson, M. L.; Todd, R. A.; Hutchinson, D. P.

327

Hybrid III-V/silicon SOA for photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Silicon photonics has reached a considerable level of maturity, and the complexity of photonic integrated circuits (PIC) is steadily increasing. As the number of components in a PIC grows, loss management becomes more and more important. Integrated semiconductor optical amplifiers (SOA) will be crucial components in future photonic systems for loss compensation. In addition, there are specific applications, where SOAs can play a key role beyond mere loss compensation, such as modulated reflective SOAs in carrier distributed passive optical networks or optical gates in packet switching. It is, therefore, highly desirable to find a generic integration platform that includes the possibility of integrating SOAs on silicon. Various methods are currently being developed to integrate light emitters on silicon-on-insulator (SOI) waveguide circuits. Many of them use III-V materials for the hybrid integration on SOI. Various types of lasers have been demonstrated by several groups around the globe. In some of the integration approaches, SOAs can be implemented using essentially the same technology as for lasers. In this paper we will focus on SOA devices based on a hybrid integration approach where III-V material is bonded on SOI and a vertical optical mode transfer is used to couple light between SOI waveguides and guides formed in bonded III-V semiconductor layers. In contrast to evanescent coupling schemes, this mode transfer allows for a higher confinement factor in the gain material and thus for efficient light amplification over short propagation distances. We will outline the fabrication process of our hybrid components and present some of the most interesting results from a fabricated and packaged hybrid SOA.

Kaspar, P.; Brenot, R.; Le Liepvre, A.; Accard, A.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Duan, G.-H.; Olivier, S.; Jany, Christophe; Kopp, C.; Menezo, S.

2014-11-01

328

Fully integrated circuit chip of microelectronic neural bridge  

NASA Astrophysics Data System (ADS)

Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-?m CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

Xiaoyan, Shen; Zhigong, Wang

2014-09-01

329

Design and status of the RF-digitizer integrated circuit  

NASA Technical Reports Server (NTRS)

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

330

Integrating anatomy and function for zebrafish circuit analysis  

PubMed Central

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties—e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

Arrenberg, Aristides B.; Driever, Wolfgang

2013-01-01

331

A bipolar analog front-end integrated circuit for the SDC silicon tracker  

SciTech Connect

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT&T`s CBIC-U2, 4 GHz f{sub T} complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 {mu}m pitch double-sided silicon strip detector. The chip measures 6.8 mm {times} 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a {Phi}=10{sup 14} protons/cm{sup 2} have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

332

Predictive CDM simulation approach based on tester, package and full integrated circuit modeling  

Microsoft Academic Search

The ESD sensitivity of integrated circuits with respect to the CDM is strongly dependent on the IC package, the substrate resistivity and the effectiveness of the ESD protection network. This paper presents a predictive CDM circuit simulation method based on tester, package and full integrated circuit modeling approach.

Dolphin Abessolo-Bidzo; Theo Smedes; Albert Jan Huitsing

2011-01-01

333

Integrated Circuit Implementation of a Cortical Neuron Jayawan H. B. Wijekoon and Piotr Dudek  

E-print Network

-scale massively parallel VLSI networks that closely resemble the circuits of the cortex. While it remains an openIntegrated Circuit Implementation of a Cortical Neuron Jayawan H. B. Wijekoon and Piotr Dudek-mail: jayawan@ieee.org, p.dudek@manchester.ac.uk. Abstract-- This paper presents an analogue integrated circuit

Dudek, Piotr

334

Advances in integrated photonic circuits for packet-switched interconnection  

NASA Astrophysics Data System (ADS)

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8? space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

335

The design of a regulated variable power supply for transistor circuits  

E-print Network

Circuit D-C Amp1ifi:er Auxiliary D-C Voltage Supply System Considerations Experimental Results 12 15 19 27 CONCLUSIONS APPENDIX BIBLIOGRAPHY 30 47 LIST OF FIGURES FIGURE PAGE 1. Shunt-Type Regulator 2. Series- Type Regulator 3. Block... the breaMown-diode voltage regulator which will be di. scussed. later in connection with auxiliary voltage supplies (page 18) ~ The reference voltage or non-linear device is shown as a battery Er in series with s resistor Rb. In practice, this may...

Graham, Oscar David

1959-01-01

336

Integrated detectors for embedded optical interconnections on electrical boards, modules, and integrated circuits  

Microsoft Academic Search

Significant opportunities exist for optical interconnections at the board, module, and chip level if compact, low-loss, high-data-rate optical interconnections can be integrated into these electrical interconnection systems. To create such an integrated optoelectronic\\/electronic microsystem, mask-based alignment of the optical interconnection waveguide, optoelectronic active devices, and interface circuits is attractive from a packaging alignment standpoint. This paper describes an integration process

Sang-Yeon Cho; Sang-Woo Seo; Martin A. Brooke; Nan M. Jokerst

2002-01-01

337

A High-Speed and Low-Power Inverter Circuit Using p-Channel Metal Oxide Semiconductor Low-Temperature Polycrystalline Silicon Thin Film Transistors  

NASA Astrophysics Data System (ADS)

Whereas p-channel metal oxide semiconductor (PMOS) thin film transistor (TFT) circuits can reduce the fabrication cost because of the smaller number of masks and simpler process steps compared with the complementary metal oxide semiconductor (CMOS) counterparts, the circuit performance is very limited and power consumption is an issue. A previously reported PMOS TFT inverter circuit can alleviate the issues encountered in the conventional PMOS TFT circuits such as high power consumption and limited output dynamic range. However, the circuit uses an auxiliary negative supply voltage for full output dynamic range, requiring an additional DC-DC converter. We newly propose a PMOS TFT inverter circuit that eliminates an auxiliary negative supply voltage and provides high-speed operation and low power consumption. The circuit intentionally creates a delay of the input signal to generate a negative voltage for turning on the pull-down PMOS TFTs and allowing the output to drop to ground level. The rising and falling times are reduced to 35.5 and 15.6% of those of the previous PMOS TFT inverter, and the power consumption is also reduced to 55.6%.

Hong, Seunghun; Kim, Jaehwan; Choi, Byong-Deok

2009-03-01

338

A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor  

E-print Network

We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

2010-08-28

339

Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits  

E-print Network

Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power ...

Nagarajan, Raghavan

2008-01-01

340

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Creighton, J. Randall (Albuquerque, NM); Dominguez, Frank (Albuquerque, NM); Johnson, A. Wayne (Albuquerque, NM); Omstead, Thomas R. (Albuquerque, NM)

1997-01-01

341

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

342

SiGe/Si Monolithically Integrated Amplifier Circuits  

NASA Technical Reports Server (NTRS)

With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

Katehi, Linda P. B.; Bhattacharya, Pallab

1998-01-01

343

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

1995-01-01

344

Implementation of Large Scale Integrated (LSI) circuit design software  

NASA Technical Reports Server (NTRS)

Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) circuit design programs were modified and upgraded. Major modifications were made to the Mask Analysis Program in the form of additional operating commands and file processing options. Modifications were also made to the Artwork Interactive Design System to correct some deficiencies in the original program as well as to add several new command features related to improving the response of AIDS when dealing with large files. The remaining work was concerned with updating various programs within CADAT to incorporate the silicon on sapphire silicon gate technology.

Kuehlthau, R. L.; Pitts, E. R.

1976-01-01

345

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits  

Microsoft Academic Search

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication

Ahmet Bindal; Sotoudeh Hamedi-Hagh

2006-01-01

346

Methodology for analysis of TSV stress induced transistor variation and circuit performance  

E-print Network

As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal ...

Yu, Li

347

Stainless Steel NaK Circuit Integration and Fill Submission  

NASA Technical Reports Server (NTRS)

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Garber, Anne E.

2006-01-01

348

Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperatures over 100 K  

E-print Network

Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors of lithographically defined nanoscale silicon quantum-dot transistors that operate at temperatures over 100 K semiconductors instead of Si--the backbone material of the integrated circuit IC industry. To make the quantum

349

LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability  

Microsoft Academic Search

Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM, which is pervasive in modern CMOS integrated circuits. Here, a six transistor SRAM cell is presented that does not suffer from reduced stability when reading. The cell also resides in a low leakage, voltage collapsed, low standby power mode when not being accessed. The cell

Sayeed A. Badrudduza; Giby Samson; Lawrence T. Clark

2007-01-01

350

Recent patents on Cu/low-k dielectrics interconnects in integrated circuits.  

PubMed

In past decades, the development of microelectronics has moved along with constant speed of scaling to maximize transistor density as driven by the need for electrical and functional performance. For further development, the propagation velocity of electromagnetic waves becomes increasingly important due to their unyielding constraints on interconnect delay. To minimize it, it was forced to the introduction of the Cu/low-k dielectric interconnects to very large scale integrated circuits (VLSI) where k denotes the dielectric constant. In addition, reliable barrier structures, which are the thinnest part among the device parts to maximize space availability for the actual Cu IWs, are required to prevent penetration of different materials. In light of the above statements, this review will focus recent patents and some studies on Cu interconnects including Cu interconnect wires, low-k dielectrics and related barrier materials as well manufacturing techniques in VLSI, which are one of the most essential concerns in microelectronic industry and decides the further development of VLSI. In addition, possible future development in this field is considered. PMID:19076033

Jiang, Qing; Zhu, Yong F; Zhao, Ming

2007-01-01

351

Graphene/Si CMOS Hybrid Hall Integrated Circuits  

PubMed Central

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

352

Development of optical packet and circuit integrated ring network testbed.  

PubMed

We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. PMID:22274025

Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

2011-12-12

353

Manufacturing issues for 3D integrated active circuits into organic laminate substrates  

Microsoft Academic Search

The three dimensional integration of active circuits, thinned or in standard thickness, into polymeric substrates challenges current substrate manufacturing processes in an unprecedented way. In order to overcome the risks associated with this 3D integration technology, the issues must be carefully studied and assessed. For the direct integration of ultrathin chips into dielectric build up layers of multi-layer printed circuit

Erik Jung; Dirk Wojakowski; Alexander Neumann; Andreas Ostmann; Rolf Aschenbrenner; Herbert Reichl

2003-01-01

354

Integrated circuit for processing a low-frequency signal from a seismic detector  

SciTech Connect

Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex 'Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

2011-12-15

355

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.  

PubMed

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc. PMID:24441981

Gao, Pingqi; Zhang, Qing

2014-02-14

356

Time-resolved optical characterization of electrical activity in integrated circuits  

Microsoft Academic Search

If the rate of improvement in the performance of advanced silicon integrated circuits is to be sustained, new techniques for the measurement of electrical waveforms in operating circuits are needed. Critical factors dictating this requirement include the increased speed and complexity of circuits, the growing importance of faults that appear only during high-speed operation, and the use of flip-chip packaging

JAMES C. TSANG; JEFFREY ALAN KASH; DAVID P. VALLETT

2000-01-01

357

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits  

Microsoft Academic Search

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a

David K. Su; Marc J. Loinaz; Shoichi Masui; Bruce A. Wooley

1993-01-01

358

SEMICONDUCTOR INTEGRATED CIRCUITS: A 4 W K-band GaAs MMIC power amplifier with 22 dB gain  

NASA Astrophysics Data System (ADS)

A 4 W K-band AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) high power amplifier (PA) is reported. This amplifier is designed to fully match for a 50 ? input and output impedance based on the 0.15 ?m power PHEMT process. Under the condition of 5.6 V and 2.6 A DC bias, the amplifier has achieved a 22 dB small-signal gain, better than a 13 dB input return loss, and 36 dBm saturation power with 25% PAE from 19 to 22 GHz.

Zhengliang, Huang; Faxin, Yu; Yao, Zheng

2010-03-01

359

Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida  

NASA Astrophysics Data System (ADS)

A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

1984-07-01

360

INTRODUCTION TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN  

Microsoft Academic Search

Up to now the evolution of digital microelectronics is characterized by the exponential growth of the number of transistors\\u000a per chip which results in an exponential increase of computing power. In 1965 Gordon Moore noted that the number of transistors\\u000a per chip will double every 18 to 24 month. This famous prediction which is known as Moore’s Law has become

Stephan Henzler

361

A kind of integrated method discuss of fOG signal processing circuit  

NASA Astrophysics Data System (ADS)

In view of the circuit miniaturization need in project application of fiber optic gyroscope(FOG), a new integrated technical scheme adopting system in package(SIP) for signal processing circuit of FOG was put forward. At first, the principle on signal processing circuit of FOG was analyzed, and the technical scheme adopting SIP based on low-temperature co-fired substrate technology was presented according to circuit characteristic and actual condition. Secondly, under the prerequisite of the concept introduction of SIP and LTCC, the SIP prototype of signal processing circuit of FOG was trialed produced - and it passed through the debug test. This SIP modular is an overall circuit complete integrated the signal processing circuit of FOG, and only a potentiometer and EPROM do not case outside. The testing results indicate that SIP is a kind of feasible scheme that carries out miniaturization for signal processing circuit of FOG.

Lu, Jun; Pan, Xin; Ying, Jiaju; Liu, Jie

2014-12-01

362

Volatile general anesthetic sensing with organic field-effect transistors integrating phospholipid membranes.  

PubMed

The detailed action mechanism of volatile general anesthetics is still unknown despite their effect has been clinically exploited for more than a century. Long ago it was also assessed that the potency of an anesthetic molecule well correlates with its lipophilicity and phospholipids were eventually identified as mediators. As yet, the direct effect of volatile anesthetics at physiological relevant concentrations on membranes is still under scrutiny. Organic field-effect transistors (OFETs) integrating a phospholipid (PL) functional bio inter-layer (FBI) are here proposed for the electronic detection of archetypal volatile anesthetic molecules such as diethyl ether and halothane. This technology allows to directly interface a PL layer to an electronic transistor channel, and directly probe subtle changes occurring in the bio-layer. Repeatable responses of PL FBI-OFET to anesthetics are produced in a concentration range that reaches few percent, namely the clinically relevant regime. The PL FBI-OFET is also shown to deliver a comparably weaker response to a non-anesthetic volatile molecule such as acetone. PMID:22921091

Daniela Angione, Maria; Magliulo, Maria; Cotrone, Serafina; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Gobeljic, Danka; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2013-02-15

363

Investigation of failure mechanisms in integrated vacuum circuits  

NASA Technical Reports Server (NTRS)

The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

Rosengreen, A.

1972-01-01

364

Integrated Circuit Design in US High-Energy Physics  

E-print Network

This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

G. De Geronimo; D. Christian; C. Bebek; M. Garcia-Sciveres; H. Von der Lippe; G. Haller; A. A. Grillo; M. Newcomer

2013-07-15

365

Basic structures of integrated photonic circuits for smart biosensor applications  

NASA Astrophysics Data System (ADS)

The breadth of opportunities for applied technologies for optical sensors ranges from environmental and biochemical control, medical diagnostics to process regulation. Thus the specified usage of the optical sensor system requires a particular design and functionalization. Especially biochemical sensors incorporate electronic and photonic devices for the detection of harmful substances e.g. in drinking water. Here we present recent developments in the integration of a Si-based light emitting device (LED) [1-3, 8] into a photonic circuit for an optical waveguide-based biodetection system. This concept includes the design, fabrication and characterization of the dielectric high contrast waveguide as an important component, beside the LED, in the photonic system circuit. First approaches involve simulations of Si3N4/SiO2-waveguides with the finite element method (FEM) and their fabrication by plasma enhanced chemical vapour deposition (PECVD), optical lithography and reactive ion etching (RIE). In addition, we characterized the deposited layers via ellipsometry and the etched structures by scanning electron microscopy (SEM). The obtained results establish a basis for optimized Si-based LED waveguide butt-coupling with adequate coupling efficiency, low attenuation loss and a high optical power throughput.

Germer, S.; Cherkouk, C.; Rebohle, L.; Helm, M.; Skorupa, W.

2013-05-01

366

Germanium on silicon to enable integrated photonic circuits  

NASA Astrophysics Data System (ADS)

Electronic circuits alone cannot fully meet future requirements for speed, size, and weight of many sensor systems, such as digital radar technology and as a result, interest in integrated photonic circuits (IPCs) and the hybridization of electronics with photonics is growing. However, many IPC components such as photodetectors are not presently ideal, but germanium has many advantages to enable higher performance designs that can be better incorporated into an IPC. For example, Ge photodetectors offer an enormous responsivity to laser wavelengths near 1.55?m at high frequencies to 40GHz, and they can be easily fabricated as part of a planar silicon processing schedule. At the same time, germanium has enormous potential for enabling 1.55 micron lasers on silicon and for enhancing the performance of silicon modulators. Our new effort has begun by studying the deposition of germanium on silicon and beginning to develop methods for processing these films. In initial experiments comparing several common chemical solutions for selective etching under patterned positive photoresist, it was found that hydrogen peroxide (H2O2) at or below room temperature (20 C) produced the sharpest patterns in the Ge films; H2O2 at a higher temperature (50 C) resulted in the greatest lateral etching.

Hopkins, F. Kenneth; Walsh, Kevin M.; Benken, Alexander; Jones, John; Averett, Kent; Diggs, Darnell E.; Tan, Loon-Seng; Mou, Shin; Grote, James G.

2013-09-01

367

Development of a plan for automating integrated circuit processing  

NASA Technical Reports Server (NTRS)

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

1971-01-01

368

Monolithic microwave integrated circuit devices for active array antennas  

NASA Technical Reports Server (NTRS)

Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

Mittra, R.

1984-01-01

369

Wireless Neural Recording With Single Low-Power Integrated Circuit  

PubMed Central

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-?m 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

370

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET  

E-print Network

AbstractThe performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well...

Tan, Michael Loong P; Lentaris, Georgios; Amaratunga AJ, Gehan

2012-08-19

371

Materials and devices for optical switching and modulation of photonic integrated circuits  

E-print Network

The drive towards photonic integrated circuits (PIC) necessitates the development of new devices and materials capable of achieving miniaturization and integration on a CMOS compatible platform. Optical switching: fast ...

Seneviratne, Dilan Anuradha

2007-01-01

372

Characterization and requirements for Cu-Cu bonds for three-dimensional integrated circuits  

E-print Network

Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and reduces global RC delay by increasing the device density per unit chip area. ...

Tadepalli, Rajappa, 1979-

2007-01-01

373

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits  

Microsoft Academic Search

Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) integrated circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for resistance, capacitance and inductance of various TSV structures. Further, a reduced-order electrical circuit model is

Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen; Li-Rong Zheng

2009-01-01

374

Organic nanofibers integrated by transfer technique in field-effect transistor devices  

PubMed Central

The electrical properties of self-assembled organic crystalline nanofibers are studied by integrating these on field-effect transistor platforms using both top and bottom contact configurations. In the staggered geometries, where the nanofibers are sandwiched between the gate and the source-drain electrodes, a better electrical conduction is observed when compared to the coplanar geometry where the nanofibers are placed over the gate and the source-drain electrodes. Qualitatively different output characteristics were observed for top and bottom contact devices reflecting the significantly different contact resistances. Bottom contact devices are dominated by contact effects, while the top contact device characteristics are determined by the nanofiber bulk properties. It is found that the contact resistance is lower for crystalline nanofibers when compared to amorphous thin films. These results shed light on the charge injection and transport properties for such organic nanostructures and thus constitute a significant step forward toward a nanofiber-based light-emitting device. PMID:21711821

2011-01-01

375

AN IMPROVED METHOD AND APPARATUS FOR AUTOMATED DESIGN AND VERIFICATON OF INTEGRATED CIRCUITS  

Microsoft Academic Search

Electronic Design Automation (EDA) tools have always played an important role in Very Large Scale Integrated (VLSI) Circuit development. Two major linked roles are to reduce total design cycle time of Integrated Circuits (ICs) and increase profitability. Profitability can significantly be increased through quicker development and shorter time to market which in turn can be achieved through design automation. In

Dragomir M. Nikolic

2005-01-01

376

A comparative characterization analysis of various probing technologies for area array integrated circuits  

NASA Astrophysics Data System (ADS)

This comparative analysis evaluates various probing technologies and proposes an interconnection technology as a test platform to simulate actual probing conditions for manufacturing and implementing the technologies in cost-effective commercial probe card form, specifically for area array bumped "flip chip" integrated circuits. Integrated circuits (IC) continue to increase in size, density of transistors and increased electrical performance with a corresponding increase in the number of input/outputs requiring connections. The semiconductor industry has responded with area array solder bump interconnection technologies which place the connection points across the entire bottom surface to provide the IC more I/Os and shorter routes than present peripheral wirebonding to aluminum pads. However, present cantilever and buckling beam probing methods to electrically test "flip chip" die have been limited in electrical performance and/or have had difficulty accessing the interior of the IC. Probing is essentially determined by three (3) first-order factors: electrical resistance of the physical junction between the probe tip and the bump being probed; alignment of the probe to the bump; and the ability to repeatedly perform the former tasks for all pins for every contact made with a bump. These and other requirements are based on SEMATECH specifications desired by major domestic semiconductor manufacturers anticipated test needs into the next century. The test platform or experimental probe card appeared to be a manufacturable and feasible format in terms of providing the probes a method of interconnection from the high density pattern to a low-density tester interface in probe card form. The 40Pb/60Sn deformed less than the 95Pb/5Sn bump composition under similar vertical loads. Each of the probe concepts exhibited a range of forces and deflection for minimum electrical contact resistances. The concepts which approached the bump vertically required more force (10-12 gms) to minimize electrical resistance as compared to those probe concepts which "scrubbed" or "twisted," (4-6 gms). Most concepts exhibited limited deflection ranges based on planarity and dimensional data but adequate positional accuracy. Electrical properties, specifically ampacity, were found to be limited in concepts which used a spring component. Two experimental concepts appeared to be competitive to present "buckling beam" probing technologies, if further developed.

Armendariz, Norman Jesus

377

Focused ion beam damage to MOS integrated circuits  

SciTech Connect

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

FLEETWOOD,D.M.; CAMPBELL,ANN N.; HEMBREE,CHARLES E.; TANGYUNYONG,PAIBOON; JESSING,JEFFREY R.; SODEN,JERRY M.

2000-05-10

378

Development of microwave and millimeter-wave integrated-circuit stepped-frequency radar sensors for surface and subsurface profiling  

E-print Network

Two new stepped-frequency continuous wave (SFCW) radar sensor prototypes, based on a coherent super-heterodyne scheme, have been developed using Microwave Integrated Circuits (MICs) and Monolithic Millimeter-Wave Integrated Circuits (MMICs...

Park, Joongsuk

2005-02-17

379

Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits  

NASA Technical Reports Server (NTRS)

As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

2011-01-01

380

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip  

PubMed Central

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 ?m2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

381

Wireless amperometric neurochemical monitoring using an integrated telemetry circuit.  

PubMed

An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order Delta Sigma modulator (Delta Sigma M) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 microm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of approximately 250 fA, approximately 1.5 pA, approximately 4.5 pA, and approximately 17 pA were achieved for input currents in the range of +/-5, +/-37, +/-150, and +/-600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 microM wirelessly over a transmission distance of approximately 0.5 m in flow injection analysis experiments. PMID:18990633

Roham, Masoud; Halpern, Jeffrey M; Martin, Heidi B; Chiel, Hillel J; Mohseni, Pedram

2008-11-01

382

Scheduling revisited workstations in integrated-circuit fabrication  

NASA Technical Reports Server (NTRS)

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

Kline, Paul J.

1992-01-01

383

Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)  

NASA Astrophysics Data System (ADS)

Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

2000-03-01

384

Laser Micromachining of Active and Passive Photonic Integrated Circuits  

E-print Network

This thesis describes the development of advanced laser resonators and applications of laserinduced micromachining for photonic circuit fabrication. Two major advantages of laserinduced micromachining are direct patterning ...

Cho, Seong-Ho

2006-06-28

385

PAMM Proc. Appl. Math. Mech. 11, 783 784 (2011) / DOI 10.1002/pamm.201110380 Variational integrators for electric circuits  

E-print Network

integrators for electric circuits Sina Ober-Blöbaum1, , Molei Tao2, , and Houman Owhadi2, 1 Computational of mechanical systems. In this work, we develop a variational integrator for the simulation of electric circuits for the simulation of the electric circuit. In this way, a variational integrator is constructed that gains several

Ober-Blöbaum, Sina

386

Interfacial electronic effects in functional biolayers integrated into organic field-effect transistors  

PubMed Central

Biosystems integration into an organic field-effect transistor (OFET) structure is achieved by spin coating phospholipid or protein layers between the gate dielectric and the organic semiconductor. An architecture directly interfacing supported biological layers to the OFET channel is proposed and, strikingly, both the electronic properties and the biointerlayer functionality are fully retained. The platform bench tests involved OFETs integrating phospholipids and bacteriorhodopsin exposed to 1–5% anesthetic doses that reveal drug-induced changes in the lipid membrane. This result challenges the current anesthetic action model relying on the so far provided evidence that doses much higher than clinically relevant ones (2.4%) do not alter lipid bilayers’ structure significantly. Furthermore, a streptavidin embedding OFET shows label-free biotin electronic detection at 10 parts-per-trillion concentration level, reaching state-of-the-art fluorescent assay performances. These examples show how the proposed bioelectronic platform, besides resulting in extremely performing biosensors, can open insights into biologically relevant phenomena involving membrane weak interfacial modifications. PMID:22493224

Angione, Maria Daniela; Cotrone, Serafina; Magliulo, Maria; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Fratini, Emiliano; Baglioni, Piero; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2012-01-01

387

Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment  

NASA Technical Reports Server (NTRS)

Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

1998-01-01

388

Review and Analysis of the Radiation-Induced Degradation Observed for the Input Bias Current of Linear Integrated Circuits  

Microsoft Academic Search

It is shown that the variety of shapes of the input current versus dose curve observed in several ICs is due to circuit effects, depending on the architecture, the value of the currents and the bias conditions. When stages are cascaded, the degradation of the second stage may add or subtract current to the collector current of the input transistor.

Laurent Dusseau; Muriel Bernard; Jérôme Boch; Yago Gonzalez Velo; Nicolas Roche; Eric Lorfevre; Françoise Bezerra; Philippe Calvel; Ronan Marec; Frédéric Saigne

2008-01-01

389

ALC crystal oscillators based pressure and temperature measurement integrated circuit for high temperature oil well applications.  

PubMed

An application specific integrated circuit for the pressure and temperature measurement at the high temperature oil well bottom conditions is presented in this paper. The circuit is mainly composed of three high performance automatic level controlled (ALC) oscillator circuits, which drive three external crystals (the sensitive elements), as well as mixing and filtering stages. The integrated circuit was successfully tested up to 220 degrees C, showing a frequency resolution of 0.0003 ppm (0.0007 psi, for the pressure measurement) and a drift of 1.5 Hz/month (0.5 psi/month) concerning, respectively, the short- and long-term measurement stability. A drastic reduction of the whole measurement tool size and cost was then allowed by means of this application specific BiCMOS integrated circuit. PMID:18238666

Bianchi, N A; Karam, J M; Courtois, B

2000-01-01

390

A field emitter array monolithically integrated with a thin-film transistor on glass for display applications  

Microsoft Academic Search

We have fabricated a field emitter array (FEA) monolithically integrated with a thin-film-transistor (TFT), called a TFT-FEA, on glass and characterized its emission properties. Fabrication of the TFT-FEA on glass was conducted through low-temperature processes of less than 350°C. From experimental results, it was found that the emission current was well controlled by the TFT drain current and consequently became

H. Gamo; S Kanemaru; J Itoh

1999-01-01

391

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement  

ERIC Educational Resources Information Center

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

392

A combination of quasistatic approach with an integral method for the characterization of microwave planar circuits  

Microsoft Academic Search

We propose the modelling of elements of small dimensions (at least one dimension small by respect to the wavelength) in a planar circuit by a quasistatic approach, and the rest of the circuit by a rigorous integral method including sources. This mixed method is applied to the study of a MIM (Metal-Insulator-Metal) capacitor. Numerical results are in good agreement with

P. Taillardat; H. Aubert; H. Baudrand

1994-01-01

393

Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview  

Microsoft Academic Search

This paper is an overview of the concepts and methodologies used to predict soft-error rates (SER) due to cosmic and high-energy particle radiation in integrated circuit chips. The paper emphasizes the need for the SER simulation using the actual chip circuit model which includes device, process, and technology parameters as opposed to using either the discrete device simulation or generic

G. R. Srinivasan

1996-01-01

394

Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic  

Microsoft Academic Search

With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture. The problem is particularly acute for sequential circuits, where there are difficulties in setting and checking the state of the system.

M. J. Y. Williams; J. B. Angell

1973-01-01

395

A New Monolothic Integrated Circuit for Multiwire Proportional Chamber (MWPC) Read-Out System  

Microsoft Academic Search

A new monolithic 8-channel PMOS integrated circuit has been developed for an experiment to be carried out on the CERN 300 GeV accelerator. The circuit, read-out electronics and tests performed on 12 large MWPC (total of 48 000 channels) are described and the results are presented.

P. Bareyre; P. Borgeaud; J. C. Brisson; B. Ollivier; J. Poinsignon; J. Borel; G. Merckel; P. Meunier; B. Billion; J. Prunier

1976-01-01

396

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.  

PubMed

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (?) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of ? ? 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. PMID:23761043

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

397

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications  

NASA Astrophysics Data System (ADS)

In this work we explore several doping schemes for aggressively scaled multi-gate field-effect transistor devices with the conduction channels wrapped around silicon fins (FinFETs) (HFin?37 nm, WFin?10 nm, Lg?30 nm), using conventional ion implantation (I/I), and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, single-sided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher six transistors-static random access memory (6T-SRAM) static noise margin (SNM) values. Key advantages of the extension-less approach are: reduced cost and cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Si-epitaxial raised source/drain (SEG), and up to 20× lower IOFF. It, however, requires a tight spacer critical dimension (CD) control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins.

Veloso, Anabela; De Keersgieter, An; Brus, Stephan; Horiguchi, Naoto; Absil, Philippe P.; Hoffmann, Thomas

2011-04-01

398

A new pixel level digital read out integrated circuits for ultraviolet imaging sensors  

NASA Astrophysics Data System (ADS)

The ultraviolet imaging sensors consist of two important parts: the array of detectors and the read out integrated circuits. Along with the demand for the fine resolution, large input dynamic range and high integration degree of the imaging sensors, the functions of read out integrated circuits are becoming more and more important. The on chip analog to digital conversion is the main directions of research on this area. In this paper, we presented a new digital read out integrated circuits for ultraviolet imaging sensors. The proposed circuits have an analog to digital converter in each pixel, which enable the parallel analog to digital conversion of the whole pixel array. The developed circuits have a 50um×50um pixel area with a 128×128 size, and are designed in a 0.35um four metal double poly mixed signal CMOS process. The simulation results show that the designed analog to digital converter has an accuracy of 0.2mV and can achieve the dynamic range of 88dB. The proposed circuits realize the low noise and high speed digital output of read out integrated circuits for ultraviolet imaging sensors.

Xu, Bin; Lan, Tian-yi; Yuan, Yong-gang; Li, Xiang-yang

2014-11-01

399

Reliability-yield allocation for semiconductor integrated circuits: modeling and optimization  

E-print Network

This research develops yield and reliability models for fault-tolerant semiconductor integrated circuits and develops optimization algorithms that can be directly applied to these models. Since defects cause failures in microelectronics systems...

Ha, Chunghun

2005-11-01

400

Design and testing of a sensorless switched reluctance motor drive with a custom integrated circuit controller  

E-print Network

section circuits of an SRM drive integratable will make a large contribution to the SRM's acceptability by relieving design and application engineers of the burden of designing controls. Ile objective of this research is to develop an integrated control...

Zhang, Yingxia

1996-01-01

401

Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications  

E-print Network

Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade ...

Fariborzi, Hossein

2013-01-01

402

GeSi photodetectors and electro-absorption modulators for Si electronic-photonic integrated circuits  

E-print Network

The silicon electronic-photonic integrated circuit (EPIC) has emerged as a promising technology to break through the interconnect bottlenecks in telecommunications and on-chip interconnects. High performance photonic ...

Liu, Jifeng, Ph. D. Massachusetts Institute of Technology

2007-01-01

403

High-speed silicon electro-optic modulator for electronic photonic integrated circuits  

E-print Network

The development of future electronic-photonic integrated circuits (EPIC) based on silicon technology critically depends on the availability of CMOS-compatible high-speed modulators that enable the interaction of electronic ...

Gan, Fuwan

2007-01-01

404

77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...  

Federal Register 2010, 2011, 2012, 2013, 2014

...INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-806] Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice of Commission Determination Not To Review an Initial Determination Terminating...

2012-07-09

405

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.  

PubMed

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-01-01

406

Compound ring resonator circuit for integrated optics applications.  

PubMed

A signal interleaver/ deinterleaver based on ring resonators is proposed and analyzed with the transfer matrix and the Z-transform techniques. The proposed structure is composed of rings connected in a closed loop and is termed a "compound ring resonator circuit." The interleaver/deinterleaver circuit is designed to meet wavelength division multiplexing (WDM) specifications for two channels of spacing of 50 GHz, a channel free spectral range of 100 GHz, a crosstalk of -24 dB, and a maximum dispersion of +/-22 ps/nm over a +/-10 GHz bandwidth at a wavelength of 1.55 microm. Compared with previous circuits of this nature, this circuit possesses a smaller number of rings, a simpler design, does not require apodization, exhibits less dispersion, and offers a higher fabrication tolerance and density. PMID:19721688

Gad, Michael; Yevick, David; Jessop, Paul

2009-09-01

407

Laser micromachining of active and passive photonic integrated circuits  

E-print Network

This thesis describes the development of advanced laser resonators and applications of laser-induced micromachining for photonic circuit fabrication. Two major advantages of laser-induced micromachining are direct patterning ...

Cho, Seong-Ho, 1966-

2004-01-01

408

Double heterojunction GaAs-GaAlAs bipolar transistors grown by MOCVD for emitter coupled logic circuits  

Microsoft Academic Search

Double heterojonction N-p-N GaAlAs-GaAs-GaAlAs bipolar transistors (DHBT's) have been developed using MOCVD growth. We have investigated the influence of growth conditions on the d.c. characteristics of DHBT's. Devices with 0.2 µm base thichness and p = 2.1018cm-3exihibited common emitter current gain, ?, of up to 5500. The recombination current has been reduced such asbeta simeq 1for current densites as low

C. Dubon; R. Azoulay; P. Desrousseaux; J. Dangla; A. M. Duchenois; M. Hountondji; D. Ankri

1983-01-01

409

Design of a semi-custom integrated circuit for the SLAC SLC timing control system  

SciTech Connect

A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given.

Linstadt, E.

1984-10-01

410

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control  

E-print Network

of the requirements for the degree of DOCTOR OF PHILOSOPHY August 2009 Major Subject: Electrical Engineering DESIGN AND IMPLEMENTATION OF SWITCHING VOLTAGE INTEGRATED CIRCUITS BASED ON SLIDING MODE CONTROL A Dissertation by MIGUEL ANGEL ROJAS GONZ ?ALEZ Submitted.... Malav?e Head of Department, Costas N. Georghiades August 2009 Major Subject: Electrical Engineering iii ABSTRACT Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control. (August 2009) Miguel Angel Rojas Gonz...

Rojas Gonzalez, Miguel Angel

2010-10-12

411

A control and signal Processing integrated circuit for the JPL-boeing micromachined gyroscopes  

Microsoft Academic Search

A special-purpose integrated circuit that accomplishes the real-time control and filtering tasks for the JPL-Boeing micromachined gyroscopes using a flexible, low-power implementation is presented. Our exposition focuses on the integration of the circuit and a prototype sensor, the synthesis and implementation of the control filters, and the subsequent performance of the closed-loop system. Identified sensor models are also presented because

Yen-Cheng Chen; Robert T. M'Closkey; Tuan A. Tran; Brent Blaes

2005-01-01

412

Micromachined microwave actuator (MIMAC) technology-a new tuning approach for microwave integrated circuits  

Microsoft Academic Search

The authors describe a novel approach to the realization of tunable\\/variable III-V planar microwave integrated circuits, which uses micromachined electrostatically controlled actuator technology. This technology is potentially compatible with conventional MMIC (monolithic microwave integrated circuit) fabrication techniques, and allows precise positioning and re-positioning of metal conductors on an insulating substrate after fabrication is complete. A variety of structures has been

Lawrence E. Larson; Roy H. Hackett; Melissa A. Melendes; Ross F. Lohr

1991-01-01

413

Programmable Logic Circuits for Functional Integrated Smart Plastic Systems  

E-print Network

-IJ-050). Using our own custom soft- ware to interface between the computer aided design (CAD) system and the inkjet printer, we were able to reli- ably design and print interconnect patterns of up to 344 individually printed wires. Three of the circuits... . Micrograph of printed silver wires u Fig. 4. Process summaAnalyser (SPA) and an Owon PDS5022S portable digital storage oscilloscope. 3. Results and discussion To investigate different functions, 4 different circuits of increasing complexity were designed...

Sou, Antony; Jung, Sungjune; Gili, Enrico; Pecuni, Vincenzo; Joimel, Jerome; Fichet, Guillaume; Sirringhaus, Henning

2014-09-12

414

Clock distribution architectures for 3-D SOI integrated circuits  

Microsoft Academic Search

Three topologies to globally distribute a clock signal in 3-D circuits have been evaluated. A 3-D test circuit, based on the MITLL 3-D IC manufacturing process, has been designed, fabricated, and measured and is shown to operate at 1.4 GHz. Clock skew measurements indicate that a topology that combines the symmetry of an H-tree on the second plane and local

Vasilis F. Pavlidis; Ioannis Savidis; Eby G. Friedman

2008-01-01

415

A microwave GaAs FET power module with GaAs matching circuits - The M-FET (matched field effect transistor)  

NASA Astrophysics Data System (ADS)

A design approach for configuring microwave amplifier modules with GaAs circuit substrates is described. GaAs FET chips are used as active elements, with the input and output matching and bias circuits mounted on the GaAs chips. Lumped, matching and hybrid elements can be employed with the M-FETs, which have vertical integration. The features of a 6 GHz-FET with a 1 dB bandwidth are employed to illustrate the M-FET design and performance. Losses are noted to be a minimum at 0.1 dB with a 250 micron thick substrate in order to retain low impedance circuit elements. An eight-step process is used to manufacture the matching circuits. Trial results with an experimental M-FET are reported, demonstrating a 6.3 W output and 9 dB gain at a 550 MHz band.

Magalhaes, F. M.; Beccone, J. P.; Irvin, J. C.; Perelli, S. J.; Schlosser, W. O.

1985-05-01

416

Planarization techniques for vertically integrated metallic MEMS on silicon foundry circuits  

NASA Astrophysics Data System (ADS)

Various micromachining techniques exist to realize integrated microelectromechanical systems (MEMS), which include sensors, signal processing and/or driving circuits, and/or actuators in one small die. Post-processing techniques performed on foundry-fabricated circuits (e.g., MOSIS) are attractive since such an approach eliminates the need for an in-house integrated circuit fabrication line to produce integrated MEMS. A method based on the combination of metallic (e.g., electroplating) micromachining techniques with multichip module deposited (MCM-D) processes is a possible candidate to realize vertically-stacked integrated MEMS using the post-processing of integrated circuits (post-IC) approach. In order to realize such devices, planarization of the surface of foundry-fabricated circuit chips or wafers is often required. In such planarization layers, mechanical and chemical stability, as well as adhesion between the circuit-containing substrate and the micromachined devices, should be addressed. A PI/BCB/PI sandwich interlayer system, which utilizes both advantages of DuPont polyimide PI 2611 and Dow benzocyclobutene (BCB) Cyclotene 3022 series, was developed as a planarization interlayer for vertically integrated MEMS. The PI/BCB/PI interlayer system shows an over 95% degree of planarization (DOP) as well as passes the Method 107G Thermal Shock from the military standard MIL-STD-202F. A 0960-1317/7/2/002/img7 interlayer system was also developed as an alternative to the PI/BCB/PI system.

Lee, J.-B.; English, J.; Ahn, C.-H.; Allen, M. G.

1997-06-01

417

Radiation hardening of low-noise readout integrated circuit for infrared focal plane arrays  

NASA Astrophysics Data System (ADS)

A radiation-resistant readout integrated circuit for focal plane arrays was studied to improve the reliability of infrared image systems operating in a radioactive environment, such as in space or in the surroundings of a nuclear reactor. First, as radiation-hardened NMOSFET structure, which includes a layout modification technique, was proposed. The readout integrated circuit for infrared focal plane arrays was then designed on basis of the proposed NMOSFET layout. Commercial 0.35 um process technology was used to fabricate the proposed unit NMOSFET and the designed readout integrated circuit which is based on the proposed NMOSFET. The measured electrical characteristics of the fabricated unit NMOSFET and readout integrated circuit are in good agreement with the simulated results. For verification of the radiation tolerance, the fabricated chip was exposed to 1 Mrad (Si) of gamma radiation, which is high enough to guarantee reliable usage in space or in a very harsh radiation environment. While exposed to gamma radiation, the fabricated chip was connected to a power supply (3.3 V) for testing under the worst conditions. After being exposed to 1 Mrad of gamma radiation, the unit NMOSFET showed only a slight increment of a few picoamperes in the leakage current, and the designed readout integrated circuit showed little change at an output voltage of less than 10% of a proper output voltage. The changes in the characteristics of the unit NMOSFET and the designed readout infrared integrated circuit are at an allowable level in relation to process variation.

Lee, Min Su; Lee, Yong Soo; Lee, Hee Chul

2010-04-01

418

V-band low-noise integrated circuit receiver. [for space communication systems  

NASA Technical Reports Server (NTRS)

A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

1983-01-01

419

Fabrication of integrated circuits with high yield using ultra-thin resist processes  

Microsoft Academic Search

We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC\\/HM removal process was developed to enable the use of a thick ARC\\/HM.

Richard D. Peters; Sergei V. Postnikov; Jonathan L. Cobb; S. Dakshina-Murthy; Tab Stephens; Colita Parker; Eric Luckowski; Arturo M. Martinez Jr.; Wei Wu; Scott D. Hector

2003-01-01

420

Astrocyte-encoded positional cues maintain sensorimotor circuit integrity  

PubMed Central

SUMMARY Astrocytes, the most abundant cells in the central nervous system, promote synapse formation and help refine neural connectivity. Although they are allocated to spatially distinct regional domains during development, it is unknown whether region-restricted astrocytes are functionally heterogeneous. Here we show that postnatal spinal cord astrocytes express several region-specific genes, and that ventral astrocyte-encoded Semaphorin3a (Sema3a) is required for proper motor neuron and sensory neuron circuit organization. Loss of astrocyte-encoded Sema3a led to dysregulated ?–motor neuron axon initial segment orientation, markedly abnormal synaptic inputs, and selective death of ?–but not of adjacent ?–motor neurons. Additionally, a subset of TrkA+ sensory afferents projected to ectopic ventral positions. These findings demonstrate that stable maintenance of a positional cue by developing astrocytes influences multiple aspects of sensorimotor circuit formation. More generally, they suggest that regional astrocyte heterogeneity may help to coordinate postnatal neural circuit refinement. PMID:24776795

Molofsky, Anna V.; Kelley, Kevin W.; Tsai, Hui-Hsin; Redmond, Stephanie A.; Chang, Sandra M.; Madireddy, Lohith; Chan, Jonah R.; Baranzini, Sergio E.; Ullian, Erik M.; Rowitch, David H.

2014-01-01

421

76 FR 19174 - In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated Medical Resources...  

Federal Register 2010, 2011, 2012, 2013, 2014

...AND EXCHANGE COMMISSION File No. 500-1 In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated...current and accurate information concerning the securities of Circuit Systems, Inc. because it has not filed any periodic...

2011-04-06

422

Advancements in bipolar VLSI circuits and technologies  

NASA Astrophysics Data System (ADS)

This paper gives an overview on bipolar circuit/device techniques for VLSI logic and memories. Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are still mainly applied, but also new circuit technologies such as integrated injection logic or merged transistor logic (I2L/MTL) and Schottky transistor logic (STL) or integrated Schottky logic (ISL) have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected by technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 micron dimensions or below. Some experimental data and projections indicate the strong potentials of bipolar VLSI.

Wiedmann, S. K.

1984-06-01

423

Buffer direct injection readout integrated circuit design for dual band infrared focal plane array detector  

NASA Astrophysics Data System (ADS)

This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 ?m. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.

Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Tang, Shiang-Feng; Lin, Wen-Jen

2013-05-01

424

Heterogeneous GaSb/SOI mid-infrared photonic integrated circuits for spectroscopic applications  

NASA Astrophysics Data System (ADS)

Mid-infrared spectroscopy has gained significant importance in recent years as a detection technique for substances that absorb in this spectral region. Traditionally, a spectroscopic system consists of bulky equipment which is difficult to handle and incurs high cost. An integrated spectroscopic system would eliminate these disadvantages. GaSb-based active opto-electronic devices allow realizing mid-infrared light sources and detectors in the 2-3?m wavelength range for such integrated systems. Silicon photonics, based on Silicon-on-Insulator (SOI) waveguide circuits, on the other hand, is a well established technology based on high refractive index contrast waveguides, enabling ultra-compact passive integrated photonic circuits. Moreover, SOI waveguide circuit processing is compatible with CMOS processes. Hence, the integration of GaSb-based active devices onto SOI passive waveguide circuits potentially allows highly compact spectroscopic systems with a large degree of freedom in passive device design to improve the system performance. This approach has a high potential for several applications, e.g. an implantable glucose level monitor and gas sensing devices. In this paper, we report our work on the integration of GaSb-based epitaxy onto SOI waveguide circuits. The heterogeneous integration is based on an epitaxial layer transfer process using the polymer divinylsiloxanebenzocyclobutene (DVS-BCB) as a bonding agent. The process is performed by transferring the epitaxial layer to an SOI waveguide circuit wafer through a die-to-wafer bonding process. With this approach, a bonding layer of 150 nm thickness is easily achievable. We also report our results on the integration of waveguide-based GaSb p-i-n photodetectors coupled to SOI waveguide circuits using evanescent coupling, which show a responsivity higher than 0.4A/W. The design of active and passive structures and the overall fabrication process will also be discussed.

Hattasan, N.; Cerutti, L.; Rodriguez, J. B.; Tournié, E.; Van Thourhout, D.; Roelkens, G.

2011-01-01

425

Active parallel redundancy for electronic integrator-type control circuits  

NASA Technical Reports Server (NTRS)

Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

Peterson, R. A.

1971-01-01

426

Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth  

NASA Astrophysics Data System (ADS)

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

Tomioka, Katsuhiro; Fukui, Takashi

2014-10-01

427

III-V/silicon photonic integrated circuits for communication and sensing applications  

NASA Astrophysics Data System (ADS)

In this paper we review our work in the field of heterogeneous integration of III-V semiconductors and non-reciprocal optical materials on a silicon waveguide circuit. We elaborate on the heterogeneous integration technology based on adhesive DVS-BCB die-to-wafer bonding and discuss several device demonstrations. The presented devices are envisioned to be used in photonic integrated circuits for communication applications (telecommunications and optical interconnects) as well as in spectroscopic sensing systems operating in the short-wave infrared wavelength range.

Roelkens, Gunther; Keyvaninia, Shahram; Stankovic, Stevan; De Koninck, Yannick; Tassaert, Martijn; Mechet, Pauline; Spuesens, Thijs; Hattasan, N.; Gassenq, A.; Muneeb, M.; Ryckeboer, E.; Ghosh, Samir; Van Thourhout, D.; Baets, R.

2013-03-01

428

Long-term Electro-Magnetic Robustness of Integrated Circuits: EMRIC research project  

E-print Network

EMR in the scientific community and will contribute to develop EMR qualification procedures, EMR their lifetime, integrated circuits may be affected by harsh environmental conditions inducing internal. Integrating EMR models to simulation flow and developing EMR qualification procedures will help IC designer

Paris-Sud XI, Université de

429

Failures induced on analog integrated circuits by conveyed electromagnetic interferences: A review  

Microsoft Academic Search

Failures induced on analog integrated circuits by electromagnetic interference (EMI) will be analyzed with particular emphasis on integrated operational amplifiers built with different technologies. Additionally, the correlation found between EMI susceptibility and large-signal opamp behavior will be discussed. Some criteria for the design of low EMI susceptibility opamps will be derived. Finally, as an application example, the design of a

G. Masetti; S. Graffi; D. Golzio; Zs. M. Kovács-V

1996-01-01

430

Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits  

Microsoft Academic Search

Shorter interconnects and higher integration are among the benefits that 3D die-stacking is expected to bring to future integrated circuits. However, when stacking power- dissipating dies one on top of the other, the total power density increases accordingly. As a result, temperatures in 3DICs are exacerbated. TSVs are regarded as a solution since they are made of copper and have

Hadrien A. Clarke; Kazuaki Murakami

2011-01-01

431

A Fully Integrated Multi-channel Impedance Extraction Circuit for Biosensor Arrays  

E-print Network

A Fully Integrated Multi-channel Impedance Extraction Circuit for Biosensor Arrays Xiaowen Liu biosensors that utilize a combination of electrochemical reactions and electronic instrumentation are promising candidates for the next generation of integrated biosensors. They are well suited to characterize

Mason, Andrew

432

Integrated Printed Circuit Board Device for Cell Lysis and Nucleic Acid Extraction  

E-print Network

Integrated Printed Circuit Board Device for Cell Lysis and Nucleic Acid Extraction Lewis A and an isotachophoresis assay for sample preparation of nucleic acids from biological samples. The device has integrated two 15 L reservoirs. We demonstrated this device by extracting pathogenic nucleic acids from 1 L

Santiago, Juan G.

433

Circuits  

NSDL National Science Digital Library

Contains 5 Physlets designed to solve the common AC and DC circuit problems. In addition to the usual RC and LRC simulations, there is an applet to plot non-linear I vs V response and an applet to plot frequency response.

Christian, Wolfgang; Belloni, Mario

2008-02-09

434

Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology  

NASA Technical Reports Server (NTRS)

Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

1981-01-01

435

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits  

NASA Technical Reports Server (NTRS)

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Buehler, M. G. (inventor)

1985-01-01

436

High-Q MEMS for wireless integrated circuits  

Microsoft Academic Search

While integration technology has steadily improved size and performance for wireless baseband circuitry, quality factor and frequency limitations still limit RF front-end circuitry to many large discrete components. Integration solutions for two such RF components are described. Silicon MEMS techniques are used to create self-assembled inductors with reduced losses and improved high frequency characteristics compared with conventional integrated inductors. The

Victor M. Lubecke; Bradley P. Barber; Linus A. Fetter

2001-01-01

437

An intelligent design system for analogue integrated circuits  

Microsoft Academic Search

A new design methodology for the design of arbitrary analogue functional blocks (op amps, comparators...) is presented. The method combines symbolic simulation, numerical optimization and knowledge-based techniques and covers the whole design path from analytic modeling over optimal circuit sizing down to layout. This path is repeatedly passed through on different hierarchical levels for higher-level blocks.The main advantage of the

Georges G. E. Gielen; Koen Swings; Willy M. C. Sansen

1990-01-01

438

A parameterized functional cell design methodology for analog integrated circuits  

E-print Network

linear and nonlinear analog circuits, including filters, summing amplifiers, piecewise- linear functions, modulators, bistables, waveform generators, and A/D and D/A converters. The GPFC utilizes switched-capacitor (SC) techniques, and consists... Characteristics 2. 3. 2 The Unbuffered CMOS Op Amp 2. 3. 3 The 4, ? Q?Clock Multiplexer 2. 3. 4 Capacitors . Z. 3. 5 Input, Transfer and Feedback Switches 2. 3. 6 Practical Performance Limitations 2. 4 Geometrical Database 2. 4. 1 The Unprogrammed Cell 2...

Bily, Stephen Frank

2012-06-07

439

Integrated niobium thin film air bridges as variable capacitors for GHz tuning circuits  

NASA Astrophysics Data System (ADS)

Superconducting GHz electronics can be improved by variable tuning circuits. We present a low temperature (<150°C) process for the fabrication of niobium (Nb) thin film air bridges as variable capacitors, which can be integrated in Nb superconducting electronics. These elements can be applied for on-chip adjustment of filters, resonators and tuning circuits. Measurements and calculations of the electrostatic actuation of the bridges will be compared.

Schicke, M.; Schuster, K.-F.

2002-05-01

440

Integrated conditional teleportation and readout circuit based on a photonic crystal single chip  

Microsoft Academic Search

We demonstrate the design of an integrated conditional quantum teleportation\\u000acircuit and a readout circuit using a two-dimensional photonic crystal single\\u000achip. Fabrication and testing of the proposed quantum circuit can be\\u000aaccomplished with current or near future semiconductor process technology and\\u000aexperimental techniques. The readout part of our device, which has potential\\u000afor independent use as an atomic interferometer,

David A. Meyer

2007-01-01

441

A tunable CMOS read-out integrated circuit for carbon nanotube-based bio-sensors  

Microsoft Academic Search

A robust and tunable read-out integrated circuit architecture is presented for carbon nanotube-based bio-sensor with nano-amperes current measurement at 1ms to 16 minutes intervals. The circuit contains an on-chip 8-bit analog-to-digital convertor and a trans-impedance amplifier with tunable control parameters to accommodate not easily controlled single-walled nanotube sensor fabrication with a wide distribution of resistance ranges. For one of the

George Yu-Heng Lee; Saiyu Ren; Sang Nyon Kim; Rajesh R. Naik

2011-01-01

442

A circuit method to integrate metamaterial and graphene in absorber design  

NASA Astrophysics Data System (ADS)

We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

2014-10-01

443

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.

1980-01-01

444

A field emitter array monolithically integrated with a thin-film transistor on glass for display applications  

NASA Astrophysics Data System (ADS)

We have fabricated a field emitter array (FEA) monolithically integrated with a thin-film-transistor (TFT), called a TFT-FEA, on glass and characterized its emission properties. Fabrication of the TFT-FEA on glass was conducted through low-temperature processes of less than 350°C. From experimental results, it was found that the emission current was well controlled by the TFT drain current and consequently became stable. Emission was also turned on/off by the TFT function at a low voltage of 3 V. With this TFT-FEA, very stable emission currents with fluctuations of less than 2% have been demonstrated.

Gamo, H.; Kanemaru, S.; Itoh, J.

1999-05-01

445

"Double exposure method": a novel photolithographic process to fabricate flexible organic field-effect transistors and circuits.  

PubMed

A novel process called "double exposure method" has for the first time been developed to utilize common organic materials as insulating layers at low annealing temperature in the process of photolithography. In this method, organic dielectric layer will not dissolve in the final lift-off step by using developer to replace traditional acetone. Bottom-gate bottom-contact (BGBC) OFETs are fabricated on the flexible PET substrates with polystyrene (PS) and pentacene as dielectric layer and semiconductor layer, respectively. Transistors with mobility of 0.36 cm2 V(-1) s(-1) and logic inverter with gain of 9 on the plastic substrates have been fabricated, demonstrating the potential appliction of "double exposure method" in flexible organic electronics. PMID:23270576

Ji, Deyang; Jiang, Lang; Dong, Huanli; Meng, Qing; Wang, Zongrui; Zhang, Hantang; Hu, Wenping

2013-04-10

446

Fabrication of an Integrated Pixel with an Organic Light-Emitting Diode Driven by Copper Phthalocyanine Organic Thin Film Transistors  

NASA Astrophysics Data System (ADS)

An organic integrated pixel with organic light-emitting diodes (OLEDs) driven by organic thin film transistors (OTFTs) is fabricated by a greatly simplified processing. The OTFTs are based on copper phthalocyanine as the active medium and fabricated on indium-tin-oxide (ITO) glass with top-gate structure, thus an organic integrated pixel is easily made by integrating OLED with OTFT. The OTFTs show field-effect mobility of 0.4 cm2/Vs and on/off ratio of 103 order. The OLED is driven well and emits the brightness as large as 2100 cd/m2 at a current density of 14.6 ?A/cm2 at -19.7 V gate voltage. This simple device structure is promising in the future large-area flexible OLED displays.

Yu, Shun-Yang; Yi, Ming-Dong; Ma, Dong-Ge

2008-02-01

447

Wavelength Division Multiplexing Based Photonic Integrated Circuits on Silicon-on-Insulator Platform  

Microsoft Academic Search

We review recent advances in the development of silicon photonic integrated circuits for high-speed and high-capacity interconnect applications. We present detailed design, fabrication, and characterization of a silicon integrated chip based on wavelength division multiplexing. In such a chip, an array of eight high-speed silicon optical modulators is monolithically integrated with a silicon-based demultiplexer and a multiplexer. We demonstrate that

Ansheng Liu; Ling Liao; Yoel Chetrit; Juthika Basak; Hat Nguyen; Doron Rubin; Mario Paniccia

2010-01-01

448

Method and apparatus for in-system redundant array repair on integrated circuits  

DOEpatents

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

2008-07-08

449

Electron and optical beam testing of integrated circuits using CIVA, LIVA, and LECIVA  

NASA Astrophysics Data System (ADS)

Charge-induced voltage alteration (CIVA), light-induced voltage alteration (LIVA), and low energy CIVA (LECIVA) are three new failure analysis imaging techniques developed to quickly localize defects on IC's. All three techniques utilize the voltage fluctuations of a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA yield rapid localization of open interconnections on IC's. LIVA allows quick localization of open-circuited and damaged semiconductor junctions. LIVA can also be used to image transistor logic states and can be performed from the backside of IC's with an infrared laser source. The physics of signal generation for each technique and examples of their use in failure analysis are described.

Cole, E. I., Jr.

1995-08-01

450

Electron and optical beam testing of integrated circuits using CIVA, LIVA, and LECIVA  

SciTech Connect

Charge-Induced Voltage Alteration (CIVA), Light-Induced Voltage Alteration, (LIVA), and Low Energy CIVA (LECIVA) are three new failure analysis imaging techniques developed to quickly localize defects on ICs. All three techniques utilize the voltage fluctuations of a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA yield rapid localization of open interconnections on ICs. LIVA allows quick localization of open-circuited and damaged semiconductor junctions. LIVA can also be used to image transistor logic states and can be performed from the backside of ICs with an infrared laser source. The physics of signal generation for each technique and examples of their use in failure analysis are described.

Cole, E.I. Jr.

1995-09-01

451

An Integrated Design Automation System for VLSI Circuits  

Microsoft Academic Search

Our Integrated Design Automation System consists of an integrated design database, automated design processors, verification tools, and an interactive capture system. The automatic logic synthesis program, Angel, and the hierarchical layout system Champ\\/Alpha, have been particularly important in reducing the total design effort. A unified design language, HSL-FX, has been developed to broaden LSI design system coverage and to obtain

O. Karatsu; T. Hoshino; M. Endo; H. Kitazawa; T. Adachi; K. Ueda

1985-01-01

452

Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits  

DOEpatents

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits are disclosed. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits. 17 figs.

Campbell, A.N.; Anderson, R.E.; Cole, E.I. Jr.

1995-11-07

453

Molten-Caustic-Leaching (MCL or Gravimelt) System Integration Project. Topical report for test circuit operation  

SciTech Connect

This is a report of the results obtained from the operation of an integrated test circuit for the Molten-Caustic-Leaching (MCL or Gravimelt) process for the desulfurization and demineralization of coal. The objectives of operational testing of the 20 pounds of coal per hour integrated MCL test circuit are: (1) to demonstrate the technical capability of the process for producing a demineralized and desulfurized coal that meets New Source Performance Standards (NSPS); (2) to determine the range of effective process operation; (3) to test process conditions aimed at significantly lower costs; and (4) to deliver product coal.

Not Available

1990-11-01

454

Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits  

DOEpatents

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

Campbell, Ann. N. (13170-B Central SE #188, Albuquerque, NM 87123); Anderson, Richard E. (2800 Tennessee NE, Albuquerque, NM 87110); Cole, Jr., Edward I. (2116 White Cloud NE, Albuquerque, NM 87112)

1995-01-01

455

Neural circuits. Labeling of active neural circuits in vivo with designed calcium integrators.  

PubMed

The identification of active neurons and circuits in vivo is a fundamental challenge in understanding the neural basis of behavior. Genetically encoded calcium (Ca(2+)) indicators (GECIs) enable quantitative monitoring of cellular-resolution activity during behavior. However, such indicators require online monitoring within a limited field of view. Alternatively, post hoc staining of immediate early genes (IEGs) indicates highly active cells within the entire brain, albeit with poor temporal resolution. We designed a fluorescent sensor, CaMPARI, that combines the genetic targetability and quantitative link to neural activity of GECIs with the permanent, large-scale labeling of IEGs, allowing a temporally precise "activity snapshot" of a large tissue volume. CaMPARI undergoes efficient and irreversible green-to-red conversion only when elevated intracellular Ca(2+) and experimenter-controlled illumination coincide. We demonstrate the utility of CaMPARI in freely moving larvae of zebrafish and flies, and in head-fixed mice and adult flies. PMID:25678659

Fosque, Benjamin F; Sun, Yi; Dana, Hod; Yang, Chao-Tsung; Ohyama, Tomoko; Tadross, Michael R; Patel, Ronak; Zlatic, Marta; Kim, Douglas S; Ahrens, Misha B; Jayaraman, Vivek; Looger, Loren L; Schreiter, Eric R

2015-02-13

456

Characterization of temperature sensor using VT extractor circuit  

Microsoft Academic Search

The semiconductor (or IC for integrated circuit) temperature sensor is an electronic device fabricated in a similar way to other modern electronic semiconductor components such as microprocessors, diode, transistors, capacitors and etc. There are few temperature sensors being used in nowadays i.e diode type and threshold voltage (VT) extractor type. Normally hundreds or thousands of devices are formed on single

Hazian Mamat; Y. Yusoff; I. M. Yusof; W. Suradi; Tan Kong Yew

2009-01-01

457

Inverse staggered polycrystalline and amorphous silicon double structure thin film transistors  

Microsoft Academic Search

An active matrix (AMX) liquid crystal display (LCD) panel structure with peripheral driver circuits using inverse staggered poly-Si thin film transistors (TFTs) whose fabrication method was quite similar to that of the traditional a-Si:H TFTs was proposed. As a result, peripheral circuits integration can be obtained by only two additional laser annealing steps. The impact of XeCl laser energy on

Takashi Aoyama; Kazuhiro Ogawa; Yasuhiro Mochizuki; Nobutake Konishi

1995-01-01

458

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits  

NASA Technical Reports Server (NTRS)

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

1991-01-01

459

A UVLO Circuit in SiC Compatible with Power MOSFET Integration (pending entry)  

SciTech Connect

The design and test of the first undervoltage lock-out circuit implemented in a low-voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data show the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

Ericson, Milton Nance [ORNL; Frank, Steven Shane [ORNL; Glover, Dr. Michael [University of Arkansas; Britton, Charles [Oak Ridge National Laboratory (ORNL); Francis, Dr. Matt [University of Arkansas; Mantooth, Alan [University of Arkansas; Marlino, Laura D [ORNL; Mcnutt, Tyler [APEI, Inc.; Mudholkar, Dr. Mihir [University of Arkansas; Shepherd, Dr. Paul [University of Arkansas; Whitaker, Mr. Bret [APEI, Inc.; Barkley, Dr. Adam [APEI, Inc.; Lotstetter, Alex [APEI, Inc.

2014-01-01

460

A UVLO Circuit in SiC Compatible with Power MOSFET Integration  

SciTech Connect

The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data shows the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

Glover, Michael [APEI, Inc.; Shepherd, Paul [APEI, Inc.; Francis, Matt [APEI, Inc.; Mudholkar, Dr. Mihir [University of Arkansas; Mantooth, Alan [University of Arkansas; Ericson, Milton Nance [ORNL; Frank, Steven [ORNL; Britton Jr, Charles L [ORNL; Marlino, Laura D [ORNL; Mcnutt, Tyler [APEI, Inc.; Barkley, Dr. Adam [APEI, Inc.; Whitaker, Mr. Bret [APEI, Inc.; Lostetter, Dr. Alex [APEI, Inc.

2014-01-01

461

Integrated circuit failure analysis by low-energy charge-induced voltage alteration  

DOEpatents

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

Cole, Jr., Edward I. (2116 White Cloud St., NE., Albuquerque, NM 87112)

1996-01-01

462

Photonic Integrated Circuits fabricated by Deep UV and Hot Embossing  

Microsoft Academic Search

We review our work in the field of deep UV modification of methacrylate-based polymers. Planar and rib waveguide structures are presented. A method of integrating polymer waveguides with organic light sources into all-polymer systems is shown.

Mathias Bruendel; Yasuhisa Ichihashi; Juergen Mohr; Martin Punke; Dominik G. Rabus; Matthias Worgull; Volker Saile

2007-01-01

463

High-frequency signal-processing integrated circuits  

NASA Astrophysics Data System (ADS)

A new topology for maximum-bandwidth matched-impedance monolithic amplifiers has been synthesized, fabricated, and tested. Stage gain of 9.3 dB and bandwidth of 3.2 GHz were realized in a 9 GHz Si bipolar monolithic technology. A new variable-gain amplifier with maximum dynamic range has been devised, fabricated, and tested. This achieved 850 MHz bandwidth, 30 dB gain control range, and 25 dB maximum gain. Equivalent input noise resistance was 400 Ohm. The successful fabrication of on-chip inductors in Si monolithic circuits was demonstrated, with application to passive filters and bandpass amplifiers in the GHz frequency range. New high-performance monolithic voltage-controlled-oscillators and phase-locked loops were synthesized, built, and tested to verify new design procedures.

Meyer, R. G.; Pederson, D. O.

1991-08-01

464

High-performance low-noise 128-channel readout-integrated circuit for flat-panel x-ray detector systems  

NASA Astrophysics Data System (ADS)

A silicon mixed-signal integrated circuit is needed to extract and process x-ray induced signals from a coated flat panel thin film transistor array (TFT) in order to generate a digital x-ray image. Indigo Systems Corporation has designed, fabricated, and tested such a readout integrated circuit (ROIC), the ISC9717. This off-the-shelf, high performance, low-noise, 128-channel device is fully programmable with a multistage pipelined architecture and a 9 to 14-bit programmable A/D converter per channel, making it suitable for numerous X-ray medical imaging applications. These include high-resolution radiography in single frame mode and fluoroscopy where high frame rates are required. The ISC9717 can be used with various flat panel arrays and solid-state detectors materials: Selenium (Se), Cesium Iodide (CsI), Silicon (Si), Amorphous Silicon, Gallium Arsenide (GaAs), and Cadmium Zinc Telluride (CdZnTe). The 80-micron pitch ROIC is designed to interface (wire bonding or flip-chip) along one or two sides of the x-ray panel, where ROICs are abutted vertically, each reading out charge from pixels multiplexed onto 128 horizontal read lines. The paper will present the design and test results of the ROIC, including the mechanical and electrical interface to a TFT array, system performance requirements, output multiplexing of the digital signals to an off-board processor, and characterization test results from fabricated arrays.

Beuville, Eric J.; Belding, Mark; Costello, Adrienne N.; Hansen, Randy; Petronio, Susan M.

2004-05-01

465

Tunnel field-effect transistors as energy-efficient electronic switches.  

PubMed

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits. PMID:22094693

Ionescu, Adrian M; Riel, Heike

2011-11-17

466

A microfabricated fringing field capacitive pH sensor with an integrated readout circuit  

SciTech Connect

This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96?MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

Arefin, Md Shamsul, E-mail: md.arefin@monash.edu; Redoute, Jean-Michel; Rasit Yuce, Mehmet [Electrical and Computer Systems Engineering, Monash University, Melbourne (Australia); Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian [Mechanical and Aerospace Engineering, Monash University, Melbourne (Australia)

2014-06-02

467

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.  

PubMed

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W. PMID:17392901

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

468

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators  

NASA Technical Reports Server (NTRS)

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

1981-01-01

469

Integrated planar lightwave bio/chem OEIC sensors on Si CMOS circuits  

NASA Astrophysics Data System (ADS)

Optical sensing, and the integration of sensors and electronics into Sensor on a Chip and Sensor on a Package systems are an approach to the creation of miniaturized, portable, customizable, low cost sensor systems for rapid health diagnostics, medical research, environmental monitoring, and security monitoring. To integrate optical sensing systems that are autonomous, it is essential to integrate the sensor, light source, and light detection into a single substrate or chip. The integration of this optical system with signal control and processing electronics enable discrimination with individually customized sensors in sensor arrays, and high sensitivity levels. Thin film optoelectronic active device integration with planar optical passive devices is a heterogeneous integration method for fabricating planar lightwave integrated circuits at the chip level and planar lightwave integrated systems at the substrate and package level.

Jokerst, Nan M.; Brooke, Martin A.; Cho, Sang-Yeon; Thomas, Mikkel; Lillie, Jeffrey; Kim, Daeik; Ralph, Stephen; Dennis, Karla; Comeau, Benita; Henderson, Cliff

2005-03-01

470

RHIC (Radiation Hardened Integrated Circuit) 2 building deionized water system specification for Sandia National Laboratories, Albuquerque, NM  

Microsoft Academic Search

The specification for a 150 gpm ultrapure water system has been written to support the development of radiation tolerant submicron silicon integrated circuit technologies and designs of the 1990's in the new Radiation Hardened Integrated Circuit (RHIC) facility at Sandia National Laboratories, Albuquerque. The design, based on comprehensive analyses of the high silica (20 to 40 ppM) well water, the

J. P. Scofield; G. S. Fry; D. L. Weaver; N. E. Brown

1986-01-01

471

An integrated transcriptional regulatory circuit that reinforces the breast cancer stem cell state  

E-print Network

RNAs and their respective targets in samples from triple-negative breast cancer patients, providing evidenceRNAs progressively attenuates the growth of CSCs derived from triple-negative breast cancers. These observationsAn integrated transcriptional regulatory circuit that reinforces the breast cancer stem cell state

472

Integrating Multi-Modal Circuit Features within an Efficient Encryption System  

Microsoft Academic Search

The problem of the incorporation of pattern features with unusual distributions is well known within pattern recognition systems even if not easily addressed. The problem is more acute when features are derived from characteristics of given integrated electronic circuits. The current paper introduces novel efficient techniques for normalising sets of features which are highly multi-modal in nature, so as to

Evangelos Papoutsis; Gareth Howells; Andrew Hopkins; K. McDonald Maier

2007-01-01

473

Integrated circuits for sensing: compact models and implementation of silicon vision chips and vibrating MEMS  

E-print Network

Integrated circuits for sensing: compact models and implementation of silicon vision chips electronics is the ability to build on-chip complex heterogeneous systems. Designing systems incorporating sensors, analogue and digital electronics, and software is a complex task. Yet, verifying the correct

Baudoin, Geneviève

474

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits  

Microsoft Academic Search

Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very

Hao Hua; Christopher Mineo; Kory Schoenfliess; Ambarish M. Sule; Samson Melamed; Ravi Jenkal; W. Rhett Davis

2006-01-01

475

High-Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit\\/Microfluidic Chip  

Microsoft Academic Search

A hybrid integrated circuit (IC)\\/microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 times 61 array of pixels that are 30 times 38 mum2 in size, each

David Issadore; Thomas Franke; Keith A. Brown; Thomas P. Hunt; Robert M. Westervelt

2009-01-01

476

Utilizing Flexible Printed Circuit Board (FPCB) to realize passives integration in LLC resonant converter  

Microsoft Academic Search

There are altogether four passive components in the resonant tank of LLC resonant converter: the series resonant inductor, the resonant capacitor, the parallel inductor and the transformer. A new method utilizing the flexible printed circuit board (FPCB) to realize passives integration in LLC resonant converter is presented. The design process is provided, and the experimental results verify its feasibility. However,

Yanjun Zhang; Yi Chen; Dehong Xu; Kazuaki Mino; Yasuhiro Okuma

2008-01-01

477

6I-4 Integrated Micromechanical Circuits Fueled By Vibrating RF MEMS Technology (Invited)  

Microsoft Academic Search

Having now produced devices with sufficient Q, thermal stability, aging stability, and manufacturability, vibrating RF MEMS technology is already finding its way into next generation timing and wireless applications. At this juncture, the technology is now poised to take its next logical steps: higher levels of circuit complexity and integration. In particular, as vibrating RF MEMS devices are perceived more

Clark T.-C. Nguyen

2006-01-01

478

INTEGRATED MEMS STRUCTURES AND CMOS CIRCUITS FOR BIOELECTRONIC INTERFACE WITH SINGLE CELLS  

E-print Network

INTEGRATED MEMS STRUCTURES AND CMOS CIRCUITS FOR BIOELECTRONIC INTERFACE WITH SINGLE CELLS NMEMS system for confining and electrically interfacing to single cells for long-term studies. The system. Initial testing of these "cell clinics" with bovine aortic smooth muscle cells yields successful sensing

Maryland at College Park, University of

479

An integrated organic circuit array for flexible large-area temperature sensing  

E-print Network

An integrated organic temperature-sensing circuit array compatible with flexible and large-area substrates is presented. The array outputs an average value of 6.8 mV/A[over-carat][degree symbol]C, which is 22A[over-tilde] ...

He, David Da

480

Overview and Status of Numerical Electromagnetic Field Simulation Methods Applied to Integrated Circuits  

Microsoft Academic Search

We give a presentation on numerical electromagnetic field simulation methods applied to integrated circuits and discuss challenges of chip, package and board co- design. Different modeling techniques are introduced where especially the application and need for hybrid methods is stressed. Also the need for global methodologies in simulating digital and analog signal behavior of ICs is discussed and illustrated by

Peter Russer; Damienne Bajon; Sidina Wane; Nikolaus Fichtner

2009-01-01

481

Substrate integrated waveguide six-port broadband front-end circuit for millimeter-wave radio and radar systems  

Microsoft Academic Search

A novel multi-purpose integrated planar six-port front-end circuit combining both substrate integrated waveguide (SIW) technology and integrated loads is presented and demonstrated. The use of SIW technology allows a very compact circuit and very low radiation loss at millimeter frequencies. An integrated load is used to simplify the fabrication process and also reduce dimensions and cost. To validate the proposed

Tarek Djerafi; Maxim Daigle; Halim Boutayeb; Xiupu Zhang; Ke Wu

2009-01-01

482

Complementary MetalOxideSemiconductor Microelectromechanical Pressure Sensor Integrated with Circuits on Chip  

Microsoft Academic Search

This study investigates the fabrication of an integrated pressure sensor using the commercial 0.35 mum complementary metal-oxide-semiconductor (CMOS) process and a post-process. The main character of the pressure sensor is to integrate the circuits on a chip. The pressure sensor that is a capacitive type sensor is composed of 128 sensing cells in parallel, and each sensing cell contains a

Ching-Liang Dai; Mao-Chen Liu

2007-01-01

483

A quantum-well-intermixing process for wavelength-agile photonic integrated circuits  

Microsoft Academic Search

Wavelength-agile photonic integrated circuits are fabricated using a one-step ion implantation quantum-well intermixing process. In this paper, we discuss, the issues in processing optimized widely tunable multisection lasers using this technique and present the results achieved using this process. This quantum-well intermixing process is general in its application and can be used to monolithically integrate a wide variety of optoelectronic

Erik J. Skogen; Jonathon S. Barton; Steven P. Denbaars; Larry A. Coldren

2002-01-01

484

Optical interconnection module integrated on a flexible optical\\/electrical hybrid printed circuit board  

Microsoft Academic Search

An optical interconnection module directly integrated on a flexible optical\\/electrical hybrid printed circuit board (O\\/E hybrid PCB) is presented. A newly proposed polymeric optical waveguide plays roles in the optical path and in a platform as an O\\/E hybrid PCB integrated with various optical\\/electrical components. The fabricated flexible O\\/E hybrid PCB had sufficient optical characteristics such as a low bending

Woo-Jin Lee; Sung Hwan Hwang; Jung Woon Lim; Che Hyun Cho; Gye Won Kim; Byung Sup Rho

2009-01-01

485

Computer-aided design of analog and mixed-signal integrated circuits  

Microsoft Academic Search

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing

GEORGES G. E. GIELEN; ROB A. RUTENBAR

2000-01-01

486

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies  

Microsoft Academic Search

3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design (CAD) for 3-D integrated circuits (ICs). Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) memories, and a 8192-point fast Fourier transform (FFT) processor in order

William Rhett Davis; Eun Chu Oh; Ambarish M. Sule; Paul D. Franzon

2009-01-01

487

Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices.  

PubMed

We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs. PMID:25328156

Logoteta, Demetrio; Fiori, Gianluca; Iannaccone, Giuseppe

2014-01-01

488

Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices  

NASA Astrophysics Data System (ADS)

We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

Logoteta, Demetrio; Fiori, Gianluca; Iannaccone, Giuseppe

2014-10-01

489

Ultra-stable oscillator with complementary transistors  

NASA Technical Reports Server (NTRS)

A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bi-polar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form with the piezoelectric crystal being common to both circuits. By this configuration small changes in quiescent current are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.

Kleinberg, L. L. (inventor)

1974-01-01

490

Built-in self-test for high-speed integrated circuits  

NASA Astrophysics Data System (ADS)

The paper deals with testability analysis of differential ECL. The logic behavior and the drop in performance concerning a very detailed list of possible bipolar defects are examined. It is shown that at speed testing facilitates a rather high fault coverage of about 98% and that it is strictly necessary to test high speed integrated circuits at speed using BIST because automatic test equipment is only available up to clock frequencies of 660 MHz. The paper also deals with the design of high speed integrated circuits for test applications using differential ECL (emitter coupled logic). High operating speed can only be achieved if suitable circuit concepts (full custom designs) are chosen and the circuits themselves are carefully optimized. Circuits have been designed considering a low power consumption and a small overhead as they are used for testpattern generation (TPG) and signature analysis (SA) within a built-in self-test (BIST)-architecture. TPG and SA at datarates of several Gbit/s using LFSRs (linear feedback shift registers) are investigated.

Jorczyk, Udo; Daehn, Wilfried

1996-09-01

491

An analog integrated signal processing circuit for on-chip diffusion-based gas analysis  

NASA Astrophysics Data System (ADS)

In diffusion-based gas analysis, the transient of gas diffusion process is recorded by a generic gas sensor to serve as a fingerprint for qualitative and quantitative analysis of gaseous samples. Following the acquisition of these specific signals, any standalone gas analyzer requires a pattern recognition system for pattern classification. The classic digital pattern recognition methods require computing hardware of adequate computational throughput. In this paper, we have followed a straightforward mathematical procedure to relate the signals to their associated target gases. We have shown that the procedure can be implemented by a set of analog functions. Based on the results, we have designed an analog integrated circuit, in 0.18 µm standard CMOS process, for processing the diffusion-based transient signals. The main circuit components are a low-pass filter, the differentiator, the feature