Note: This page contains sample records for the topic transistor integrated circuit from Science.gov.
While these samples are representative of the content of Science.gov,
they are not comprehensive nor are they the most current set.
We encourage you to perform a real-time search of Science.gov
to obtain the most current and comprehensive results.
Last update: November 12, 2013.
1

MOS transistor modeling for RF integrated circuit design  

Microsoft Academic Search

The design of radio-frequency (RF) integrated circuits in deep-submicron CMOS processes requires accurate and scalable compact models of the MOS transistor that are valid in the GHz frequency range and even beyond. Unfortunately, the currently available compact models give inaccurate results if they are not modified adequately. This paper presents the basis of the modeling of the MOS transistor for

Christian Enz

2000-01-01

2

Integrated logic circuits using single-atom transistors.  

PubMed

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

2011-08-01

3

Optimizing bipolar transistor performance in RF integrated circuits  

Microsoft Academic Search

Bipolar transistors of a 0.6 ?m BiCMOS technology were optimized for better performance in high-frequency circuits. First the lateral and vertical properties of the seven available devices were studied and the effects of scaling were examined. According to the available literature a summary was created about what parasitic elements could be found in the structures. After that some modifications were

J. Katona

2003-01-01

4

Macroelectronic Integrated Circuits Using High-Performance Separated Carbon Nanotube Thin-Film Transistors  

Microsoft Academic Search

Macroelectronic integrated circuits are widely used in applications such as flat panel display, transparent electronics, as well as flexible and stretchable electronics. However, the challenge is to find the channel material that can simultaneously offer low temperature processing, high mobility, transparency and flexibility. Here in this paper, we report the application of high-performance separated nanotube thin-film transistors (TFTs) for macroelectronic

Chuan Wang; Jialu Zhang; Chongwu Zhou

2011-01-01

5

Fast All-Transparent Integrated Circuits Based on Indium Gallium Zinc Oxide Thin-Film Transistors  

Microsoft Academic Search

We describe the fabrication and characterization of visible transparent small-scale indium gallium zinc oxide (IGZO) integrated circuits. The IGZO channel and indium tin oxide (ITO) contacts and interconnects were pulsed laser deposited at room temperature. Low-temperature (200 ??C ) atomic-layer-deposited Al2O3 was used as the gate dielectric in bottom-gated thin-film transistors with field-effect mobility near 15 cm2\\/V??s. Logic inverters and

Arun Suresh; Patrick Wellenius; Vinay Baliga; Haojun Luo; Leda M. Lunardi; John F. Muth

2010-01-01

6

Physics and process-based bipolar transistor modeling for integrated circuit design  

Microsoft Academic Search

Many applications require circuits to be operated close to the performance limits of current silicon (production) processes to meet the required circuit specifications for, e.g., high speed, low noise, and low power consumption. Therefore, the circuits must be carefully optimized by selecting the individual transistor configurations. As a consequence, model parameters for a large variety of configurations (100 or more)

Michael Schroter; Hans-Martin Rein; Winfried Rabe; Reinhard Reimann; Hans-Joachim Wassener; Andreas Koldehoff

1999-01-01

7

The development of a power Darlington transistor and hybrid integrated circuit for a dc to dc converter  

Microsoft Academic Search

A power Darlington transistor Subscrete and hybrid integrated circuit consisting of two of these in parallel with a fast recovery diode are described. The integrated unit is used as a dc-to-dc converter or 'chopper' to control the acceleration and speed of an electric car motor and can deliver 450 A of armature current. The Subscrete form permits full testing and

S. Krishna; A. J. Yerman

1979-01-01

8

Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies  

SciTech Connect

Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q. [Sandia National Labs., Albuquerque, NM (United States); Enquist, P.M. [Research Triangle Inst., Research Triangle Park, NC (United States)

1995-12-31

9

Very high frequency GaAlAs laser field-effect transistor monolithic integrated circuit  

SciTech Connect

A very low threshold GaAlAs buried heterostructure laser has been monolithically integrated with a recessed structure metal-semiconductor field-effect transistor on a semi-insulating substrate. At cw operation, the device has a direct modulation bandwidth of at least 4 GHz.

Ury, I.; Lau, K.Y.; Bar-Chaim, N.; Yariv, A.

1982-07-15

10

Nanofluidic Transistor Circuits  

NASA Astrophysics Data System (ADS)

Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.

Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti

2012-02-01

11

A spiking neuron circuit based on a carbon nanotube transistor  

NASA Astrophysics Data System (ADS)

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions.

Chen, C.-L.; Kim, K.; Truong, Q.; Shen, A.; Li, Z.; Chen, Y.

2012-07-01

12

Polymer electronics: from discrete transistors to integrated circuits and active matrix displays  

Microsoft Academic Search

Transistors based on organic materials are lightweight, flexible, and potentially easy to manufacture. Since the temperature used in the production process is low, the substrate can be cheap and flexible plastic instead of glass. Still plastic transistors offer less performance than most of their inorganic counterparts. In order to fully exploit the potential of organic devices, the process technology must

E. Cantatore; G. H. Gelinck; D. M. de Leeuw

2002-01-01

13

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out  

Microsoft Academic Search

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

2008-01-01

14

Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors  

SciTech Connect

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Blalock, Benjamin J [ORNL; Islam, Syed K [ORNL

2010-01-01

15

SEMICONDUCTOR INTEGRATED CIRCUITS: Insulated gate bipolar transistor with trench gate structure of accumulation channel  

NASA Astrophysics Data System (ADS)

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simulation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K, respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.

Mengliang, Qian; Zehong, Li; Bo, Zhang; Zhaoji, Li

2010-03-01

16

Amorphous silicon logic integrated circuits  

Microsoft Academic Search

Amorphous silicon thin-film integrated circuits, with between 4 and 18 transistor functions per chip, have been fabricated on glass substrates. The amorphous silicon and the dielectric layers are deposited by rf glow discharge. The circuits have been designed to realize basic logic functions such as inverters, NAND and NOR gates, and addressable memory cells. For the first time, an amorphous

M. Böhm; S. Salamon; Z. Kiss

1988-01-01

17

Transistor Modeling using Advanced Circuit Simulator Technology  

Microsoft Academic Search

Abstract KRIPLANI NIKHIL, M. Transistor Modeling using advanced circuit simulator technology. (Under the direction of Michael B. Steer) The advanced MOSFET model based on the Berkeley Short Channel IGFET

NIKHIL M. KRIPLANI

18

Low-Voltage Driven P-Type Polycrystalline Silicon Thin-Film Transistor Integrated Gate Driver Circuits for Low-Cost Chip-on-Glass Panel  

Microsoft Academic Search

P-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) integrated driver circuits are proposed for low-cost chip-on-glass (COG) panel. In order to reduce the process cost of panel, gate driver employing level-shifter, shift register and DC-DC converter is integrated by p-type polycrystalline silicon (poly-Si) TFTs. The gate drivers are composed of the level-up and level-down voltage shifters and the robust two-clock

Woo-Jin Nam; Hye-Jin Lee; Hee-Sun Shin; Sang-Geun Park; Min-Koo Han

2006-01-01

19

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.  

SciTech Connect

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

2008-08-01

20

Electronic design with integrated circuits  

NASA Astrophysics Data System (ADS)

The book is concerned with the application of integrated circuits and presents the material actually needed by the system designer to do an effective job. The operational amplifier (op amp) is discussed, taking into account the electronic amplifier, the basic op amp, the practical op amp, analog applications, and digital applications. Digital components are considered along with combinational logic, digital subsystems, the microprocessor, special circuits, communications, and integrated circuit building blocks. Attention is given to logic gates, logic families, multivibrators, the digital computer, digital methods, communicating with a computer, computer organization, register and timing circuits for data transfer, arithmetic circuits, memories, the microprocessor chip, the control unit, communicating with the microprocessor, examples of microprocessor architecture, programming a microprocessor, the voltage-controlled oscillator, the phase-locked loop, analog-to-digital conversion, amplitude modulation, frequency modulation, pulse and digital transmission, the semiconductor diode, the bipolar transistor, and the field-effect transistor.

Comer, D. J.

21

Thermionic integrated circuits  

SciTech Connect

Thermionic integrated circuits combine vacuum-tube technology with integrated-circuit techniques to form integrated vacuum circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

MacRoberts, M.; Brown, D.R.; Dooley, R.; Lemons, R.; Lynn, D.; McCormick, B.; Mombourquette, C.; Sinah, D.

1986-01-01

22

Current monitoring circuit for fault detection in CMOS integrated circuit  

Microsoft Academic Search

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved.

Jeong Beom Kim

2008-01-01

23

Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation  

Microsoft Academic Search

A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors.

Sherif A. Tawfik; Volkan Kursun

2008-01-01

24

Simulation of Transistor Switching Circuits on the IBM 704  

Microsoft Academic Search

When the configuration of a circuit and the equivalent representations of the transistors are known, a computer program can be written to yield the performance of the circuit and the mean values of the circuit parameters. Nonlinearity of the transistors is accounted for by piece-wise linearization of an equivalent circuit. Rules of interconnection have been devised to combine this procedure

R. J. Domenico

1957-01-01

25

A Fixed-Voltage Power Supply for Transistor Circuits.  

National Technical Information Service (NTIS)

Fixed-voltage regulated power supplies are described for use with transistor circuits. Specific circuits are described for regulators supplying 13 to 31 volts at currents up to one ampere. Circuit modifications are given which make the basic regulators us...

D. W. Howell

1964-01-01

26

High-performance top-gated monolayer SnS2 field-effect transistors and their integrated logic circuits  

NASA Astrophysics Data System (ADS)

Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm2 V-1 s-1, much higher than that of the back-gated counterparts (~1 cm2 V-1 s-1). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics.Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm2 V-1 s-1, much higher than that of the back-gated counterparts (~1 cm2 V-1 s-1). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr01899g

Song, H. S.; Li, S. L.; Gao, L.; Xu, Y.; Ueno, K.; Tang, J.; Cheng, Y. B.; Tsukagoshi, K.

2013-09-01

27

High-performance top-gated monolayer SnS2 field-effect transistors and their integrated logic circuits.  

PubMed

Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm(2) V(-1) s(-1), much higher than that of the back-gated counterparts (?1 cm(2) V(-1) s(-1)). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics. PMID:23989804

Song, H S; Li, S L; Gao, L; Xu, Y; Ueno, K; Tang, J; Cheng, Y B; Tsukagoshi, K

2013-09-26

28

Technical Obstacles to Thin Film Transistor Circuits on Plastic  

NASA Astrophysics Data System (ADS)

Two main technical obstacles must be overcome to build a fruitful business in the nascent flexible microelectronics industry: the self-heating effect of thin film transistors (TFTs), and the thermal and mechanical durability of flexible devices. The self-heating effect is controlled through TFT shape, TFT electrical performance, dimensional reductions, and energy-efficient circuits. Plastic engineering is one of the keys to solving thermal and mechanical durability problems faced by flexible microelectronics devices. Once these obstacles are cleared, TFT circuits on plastic will spawn a new industry and markets for plastic large-scale integrations.

Miyasaka, Mitsutoshi; Hara, Hiroyuki; Karaki, Nobuo; Inoue, Satoshi; Kawai, Hideyuki; Nebashi, Satoshi

2008-06-01

29

Modeling and simulation of insulated-gate field-effect transistor switching circuits  

Microsoft Academic Search

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET

HAROLD SHICHMAN; DAVID A. HODGES

1968-01-01

30

Nonlinear Oscillations in a Unijunction Transistor Circuit  

NASA Astrophysics Data System (ADS)

Many interesting nonlinear behaviors have been studied in distributed (glow-discharge and Q-machine plasmas) and non-distributed (nonlinear electronic oscillators) nonlinear systems that can be modeled by the van der Pol equation.footnotetextPhys. Plasmas 3, 4421 (1996).^,footnotetextGeophys. Res. Lett., 21, 1011 (1994).^,footnotetextPhys. Rev. A 44, 6877 (1991). This work describes an experimental, theoretical and computational investigation of two nonlinear electronic oscillators which have a unijunction transistor as a nonlinear element. The circuits that are examined in this paper are a sine wave oscillator and a relaxation oscillator. The functioning of the unijunction transistor is explained in detail. A full derivation of the differential equation describing the sine wave oscillator is made, and the results of numerical simulations based on this differential equation are compared to experimental data. Descriptions and explanations of two types of non-autonomous (driven) phenomena, entrainment and periodic pulling will be given. [1] Present affiliation: Univ. of Notre Dame, [2] Present affiliation: SUNY Oswego

Christopher, Steven; Zielinski, John; Koepke, Mark

2012-10-01

31

Monolithic integration of light-emitting diodes and power metal-oxide-semiconductor channel high-electron-mobility transistors for light-emitting power integrated circuits in GaN on sapphire substrate  

NASA Astrophysics Data System (ADS)

We report the demonstration of monolithically integrated light-emitting diodes (LEDs) and power metal-oxide-semiconductor channel high-electron-mobility transistors (HEMTs) in GaN. The structure comprised a direct epitaxial integration of layers typical for a GaN-based LED grown directly on top of the layers of a GaN-based HEMT. The layers were then fabricated into a serially connected pair of GaN LED and metal-oxide-semiconductor-gated 0.3 ?m-channel HEMT by exposing the LED/HEMT epitaxial layers in selective area etching. The resulting monolithically integrated circuit shows a full gate voltage modulation of the light output power. This demonstrates compatibility of group-III nitride LED and HEMT processes.

Li, Z.; Waldron, J.; Detchprohm, T.; Wetzel, C.; Karlicek, R. F.; Chow, T. P.

2013-05-01

32

Wafer-scale graphene integrated circuit.  

PubMed

A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance. PMID:21659599

Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

2011-06-10

33

All inkjet printed self-aligned transistors and circuits applications  

Microsoft Academic Search

We fabricate devices and circuit blocks using a novel, fully-printed transistor process that self-aligns source\\/drain electrodes to gates, resulting in improved overlap capacitance. These are used with a self-aligned interconnect to realize fully-printed transistor arrays and inverters showing performance suitable for use in a range of low-cost electronics applications.

Huai-Yuan Tseng; Vivek Subramanian

2009-01-01

34

High-Resolution Inkjet Printing of All-Polymer Transistor Circuits  

Microsoft Academic Search

Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and

H. Sirringhaus; T. Kawase; R. H. Friend; T. Shimoda; M. Inbasekaran; W. Wu; E. P. Woo

2000-01-01

35

Trends in monolithic microwave integrated circuits  

NASA Astrophysics Data System (ADS)

Current trends in the fabrication of monolithic microwave integrated circuits (MMICs) are reviewed. The technologies developed predominantly make use of semi-insulating GaAs substrates, GaAs FET active elements, and lumped element circuits. An increasing number of MMIC designs incorporate innovative designs, including actively matched amplifiers and mixers, analog and digital functions, SAW circuits, and increased Q with lower resistance. A new generation of hybrid integrated circuits is also being developed which is expected to compete with conventional MMICs due to the potential for significant cost reduction. MMICs are considered to have the greatest potentials in applications requiring large quantities of similar circuits, circuits using large numbers of transistors or small areas for passive elements, and novel circuits such as SAWs monolithically combined with FETs.

Sterzer, F.

1981-11-01

36

TRANSISTORIZATION  

Microsoft Academic Search

Transistor and semiconductor diodes, compared with vacuum tubes in ; nucleonic instruments, offer the advantages of increased reliability, smaller ; size, and cooler operation. These elements are already replacing tubes ia all ; trigger and switching circuits in the field. Recently developed transistors open ; the way for transistorization of the remaining circuits basic a radiation ; detection systems. Problems

Goulding

1959-01-01

37

Fabrication of InP-based Optoelectronic Integrated Circuit (OEIC) Photoreceivers Using Shared Layer Integration of Heterojunction Bipolar Transistors and Refracting-Facet Photodiodes  

NASA Astrophysics Data System (ADS)

InP-based monolithic photoreceivers have been fabricated using a shared layer integration scheme of refracting-facet photodiodes (RFPDs) and heterojunction bipolar transistors (HBTs). An HBT was fabricated using a self-aligned emitter-base process and nonalloyed metallization of the emitter, base and collector ohmic contacts. The fabricated 2× 10 ?m2 emitter HBT exhibited a maximum current gain of 40. The maximum cutoff frequencies of this HBT were measured to be fT=79 GHz and fmax=143 GHz at IC=19 mA and VCE=1.5 V, respectively. An RFPD was fabricated using the base-collector junction layers of the HBT based on the selective wet chemical etching characteristics of InP and InGaAs layers. The fabricated RFPD showed a 37% increased optical responsivity of 0.48 A/W compared to the fabricated surface-illuminated photodiode using the same photoreceiver epitaxial layer. The full width at half maximum (FWHM) of the fabricated RFPD was determined to be 24 ps using the standard 50 ? system load. The fabricated three-stage transimpedance amplifier (TIA) showed a transimpedance gain of 46 dB? and a -3 dB bandwidth of 12 GHz. The fabricated monolithic RFPD/HBT photoreceiver has demonstrated a -3 dB optical bandwidth of 6.9 GHz.

Lee, Bangkeun; Yang, Kyounghoon

2004-04-01

38

Integrated Circuits Laboratory  

NSDL National Science Digital Library

The Integrated Circuits Laboratory is software that is devoted to helping understand the processing of semiconductor materials. Manufacturing an IC involves a complex interaction of several highly developed technologies. This software is used to fabricate high-performance integrated circuits. In such areas as oxidation, diffusion, Ion implantation, Chemical etching, Photolithography, CVD, Ellipsometer, Plasma etching and Aluminum deposition. IC Lab software offers virtual opportunities to simulate the process of manufacturing a integrated circuit without going into a clean room. All the simulations represent processing steps that are as accurate as possible. This was part of the Learning Invention Labs that MATEC held. Visit the MATEC.org homepage for more information.

Lindor, Felicia

2013-01-01

39

Encapsulation of integrated circuits  

Microsoft Academic Search

Integrated circuits mounted on ceramic substrates must be protected from moisture and from mechanical damage by an encapsulation system which must have the same long term stability as the device itself. For Bell System use, beam-lead silicon nitride protected circuits are subjected to greater than 300°C long term aging as well as to high temperature steam to accelerate failures; thus

M. L. White

1969-01-01

40

Transistor Sizing of Energy-Delay-Efficient Circuits.  

National Technical Information Service (NTIS)

This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Et(n) where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that re...

P. I. Penzes M. Nystrom A. J. Martin

2006-01-01

41

CMOS magnetic sensor integrated circuit with sectorial MAGFET  

Microsoft Academic Search

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6?m digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling

Guo Qing; Zhu Dazhong; Yao Yunruo

2006-01-01

42

Single-photon transistor in circuit quantum electrodynamics.  

PubMed

We introduce a circuit quantum electrodynamical setup for a "single-photon" transistor. In our approach photons propagate in two open transmission lines that are coupled via two interacting transmon qubits. The interaction is such that no photons are exchanged between the two transmission lines but a single photon in one line can completely block or enable the propagation of photons in the other line. High on-off ratios can be achieved for feasible experimental parameters. Our approach is inherently scalable as all photon pulses can have the same pulse shape and carrier frequency such that output signals of one transistor can be input signals for a consecutive transistor. PMID:23971573

Neumeier, Lukas; Leib, Martin; Hartmann, Michael J

2013-08-06

43

A breakdown model for the bipolar transistor to be used with circuit simulators  

NASA Astrophysics Data System (ADS)

A breakdown model for the output characteristics of the bipolar transistor (bjt) has been developed. The behavioral modeling capability of PSPICE, a popular SPICE program (with emphasis on integrated circuits) was used to implement the macromodel. The model predicts bjt output characteristics under breakdown conditions. Experimental data was obtained to verify the macromodel. Good agreement exists between the measured and the simulated results.

Keshavarz, A. A.; Raney, C. W.; Campbell, D. C.

44

Production engineering measure for hybrid integrated circuits for fuze applications. Part 1: Integrated arming and firing circuit. Part 2: Precision oscillator integrated circuit  

Microsoft Academic Search

The Integrated Arming and Firing Circuit involves the fabrication of a thick film circuit substrate, and attachment of transistors and capacitor components, and packaging. The program includes actual fabrication of test samples, a production run and performance of electrical, mechanical, and environmental tests as required.

T. Sciacca; H. G. Brandt

1974-01-01

45

Bioluminescent bioreporter integrated circuit  

DOEpatents

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

2000-01-01

46

Integrated circuit design with NEM relays  

Microsoft Academic Search

To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelectro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I\\/O that can significantly improve the

Fred Chen; Hei Kam; Dejan Markovic; Tsu-jae King Liu; Vladimir Stojanovic; Elad Alon

2008-01-01

47

What are MMIC's (Monolithic Microwave Integrated Circuits)?  

NASA Astrophysics Data System (ADS)

The development of Monolithic Microwave Integrated Circuits (MMICs) is described. MMICs combine microwave integrated circuit technology with fabrication of active devices, such as Schottky barrier diodes and field effect transistors, by batch processing on and in the substrate; the substrate must be composed of materials such as GaAs, and silicon which produce good active devices. The use of MMICs for consumer electronics, communications equipment, and military applications is discussed. The designs of the MMICs and microwave miniature active circuit, which is the basis for the MMIC, are explained. Circuits prepared for military and commercial systems, such as a multioctave bandwidth amplifier for ECM and general purpose application and a X-band MMIC low noise amplifier and converter for DBS receiver, are described.

Mahle, C.; Huang, H. C.

1985-09-01

48

On the Cyclostationary Noise Analysis in Large RF Integrated Circuits  

Microsoft Academic Search

This paper examines the issue of noise analysis in RF integrated circuits (RFICs). The complexity of the RFIC grows constantly, with transistor counts now into the thousands or tens of thousands. Since RFICs are driven by large-signal multitone excitations, the stochastic noise process in these circuits is cy- clostationary. This combination of large device count and noise cyclostationarity makes noise

Edouard Ngoya

2011-01-01

49

Integrated circuit inductors  

US Patent & Trademark Office Database

The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloys, and oxides. The inductor is compatible with integrated circuit manufacturing techniques and eliminates the need in many systems and circuits for large off chip inductors. A sense and measurement coil, which is fabricated on the same substrate as the inductor, provides the capability to measure the magnetic field or flux produced by the inductor. This on chip measurement capability supplies information that permits circuit engineers to design and fabricate on chip inductors to very tight tolerances.

Ahn; Kie Y. (Chappaqua, NY); Forbes; Leonard (Corvallis, OR)

2001-06-05

50

Nonlinear system analysis in bipolar integrated circuits  

NASA Astrophysics Data System (ADS)

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio frequency (AF) voltage at the IC amplifier output terminal caused by an amplitude modulated (AM) RF signal at the IC amplifier input terminal was calculated and compared to measured values. Two broadband IC amplifiers were investigated: (1) a cascode circuit using a CA3026 dual differential pair; (2) a unity gain voltage follower circuit using a micro A741 operational amplifier (op amp). Before using NCAP for RFI analysis, the model parameters for each bipolar junction transistor (BJT) in the integrated circuit were determined. Probe measurement techniques, manufacturer's data, and other researcher's data were used to obtain the required NCAP BJT model parameter values. An important contribution included in this effort is a complete set of NCAP BJT model parameters for most of the transistor types used in linear IC's.

Fang, T. F.; Whalen, J. J.

1980-01-01

51

Analog and digital circuits using organic thin-film transistors on polyester substrates  

Microsoft Academic Search

We have fabricated and characterized analog and digital circuits using organic thin-film transistors on polyester film substrates. These are the first reported dynamic results for organic circuits fabricated on polyester substrates. The high-performance pentacene transistors yield circuits with the highest reported clock frequencies for organic circuits

M. G. Kane; J. Campi; M. S. Hammond; F. P. Cuomo; B. Greening; C. D. Sheraw; J. A. Nichols; D. J. Gundlach; J. R. Huang; C. C. Kuo; L. Jia; H. Klauk; T. N. Jackson

2000-01-01

52

Susceptibility of Integrated Circuits to Electrostatic Discharge  

NASA Astrophysics Data System (ADS)

The components that are considered fairly rugged can be damaged by electrostatic discharge (ESD). Bipolar transistors, the earliest of the solid state amplifiers, are not immune to ESD, though less susceptible. Devices manufactured using metal oxide semiconductor (MOS) technology can be easily damaged due to ESD but some of the newer high speed components can be ruined with as little as 3 volts. The integrated circuits (IC) are susceptible to ESD due to its small size and unavailability of larger area to dissipate the excess energy. The susceptibility of ICís can be determined by various ESD stress tests. The different ESD stress modes on an input or output pin which is Pin-to-VSS, Pin-to-VDD are used to test an IC. The IC after ESD stresses may undergo damage not only in the input/output circuits or devices, but also in the internal circuits. The effects of ESD on various logic gates belonging to both transistor-transistor logic (TTL) and Complementary MOS (CMOS) logic families have been studied. The comparison between TTL and CMOS logic gates reveal that CMOS devices are more susceptible to ESD than TTL devices.

Narendra, Rajashree; Sudheer, M. L.; Pande, D. C.

2012-09-01

53

Dually active silicon nanowire transistors and circuits with equal electron and hole transport.  

PubMed

We present novel multifunctional nanocircuits built from nanowire transistors that uniquely feature equal electron and hole conduction. Thereby, the mandatory requirement to yield energy efficient circuits with a single type of transistor is shown for the first time. Contrary to any transistor reported up to date, regardless of the technology and semiconductor materials employed, the dually active silicon nanowire channels shown here exhibit an ideal symmetry of current-voltage device characteristics for electron (n-type) and hole (p-type) conduction as evaluated in terms of comparable currents, turn-on threshold voltages, and switching slopes. The key enabler to symmetry is the selective tunability of the tunneling transmission of charge carriers as rendered by the combination of the nanometer-scale dimensions of the junctions and the application of radially compressive strain. To prove the advantage of this concept we integrated dually active transistors into cascadable and multifunctional one-dimensional circuit strings. The nanocircuits confirm energy efficient switching and can further be electrically configured to provide four different types of operation modes compared to a single one when employing conventional electronics with the same amount of transistors. PMID:23919720

Heinzig, André; Mikolajick, Thomas; Trommer, Jens; Grimm, Daniel; Weber, Walter M

2013-08-14

54

Topics on GaAs integrated circuit: GaAs grown on Si substrates, field-effect transistors, and electro-optic probing technique  

SciTech Connect

The possibility of integrating GaAs devices with Si devices by means of heteroepitaxy growth on Si is considered. The GaAs films are grown on Si substrates by molecular beam epitaxy. The material defects and thermal-induced stress in GaAs films are two fundamental problems of particular interests. The defects are mainly due to the inclined interface dislocations and stacking faults. It was found that these defects can be reduced if GaAs is grown on a clean and double-stepped Si surface. Various kinds of field-effect transistors (FET's) are demonstrated and analyzed. The buried-gate junction FET made by a submicron self-aligned process achieves a transconductance of 180 mS/mm. Besides, no back-gating effect is observed in this kind of device. Another novel device named as top-back-gate FET is also reported. In order to characterize the GaAs material and device in a non-invasive way, the author developed the electro-optic probing technique. Because the refractive indices of GaAs are modified by electric fields, he could obtain the information about internal fields in GaAs devices or material from the phase retardation of a probing beam. The experimental results in potential profile probing of various device structures are reported.

Lo, Y.

1987-01-01

55

Monolithically integrated bacteriorhodopsin-GaAs field-effect transistor photoreceiver  

NASA Astrophysics Data System (ADS)

We have applied the large photovoltage developed across a layer of selectively deposited bacteriorhodopsin to the gate terminal of a monolithically integrated GaAs-based modulation-doped field-effect transistor, which delivers an amplified photoinduced current signal. The integrated biophotoreceiver device exhibits a responsivity of 3.8 A/W. The optoelectronic integrated circuit is achieved by molecular-beam epitaxy of the field-effect transistor's heterostructure, photolithography, and selective-area bacteriorhodopsin electrodeposition.

Bhattacharya, Pallab; Xu, Jian; Varo, Gyorgy; Marcy, Duane L.; Birge, Robert R.

2002-05-01

56

Thermionic integrated circuits: electronics for hostile environments  

SciTech Connect

Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

1985-01-01

57

Stability of polythiophene-based transistors and circuits  

NASA Astrophysics Data System (ADS)

Detailed investigations on shelf life and operation lifetime of polymer field-effect transistors (PFETs) and circuits are reported. All examined devices consisted entirely of polymer materials except the electrodes. Regioregular poly(3-alkylthiophene) was used as a semiconductor. Unencapsulated devices were produced, stored, and measured under ambient conditions. The performance of PFETs was maintained for more than 12 months after production. Even under extreme conditions of 85 °C and 85% relative humidity, a stable shelf life of more than 1400 h was measured. Transistors exceeded a continuous operation time of 1000 h. Operation lifetimes showed that the degradation did not follow the Arrhenius lifetime-temperature relationship. Similar results were found for ring oscillators.

Ficker, J.; Ullmann, A.; Fix, W.; Rost, H.; Clemens, W.

2003-08-01

58

Microwave integrated circuits procedures evaluation  

NASA Astrophysics Data System (ADS)

Microwave Integrated Circuits and Stripline Microwave Circuits are used widely in military ground, airborne, and spaceborne systems. The current military specifications which are invoked generally for hybrid circuits (MIL-STD-883B and MIL-M-38510) require either up-dating to encompass these two classes of microcircuits or new test methods need to be developed. New test methods have been developed for the screening, quality, and lot conformance testing of Microwave Integrated Circuits and Stripline Microwave Circuits. Pre-seal visual criteria for Stripline Microwave Circuits was also developed as well as an up-date to Method 2017, MIL-STD-883B for Microwave Integrated Circuits. Computer analysis of the various construction methods utilized by the industry was performance as a first step evaluation of the construction methods and the proposed criteria.

Belgin, M. F.; Mitchell, B. C.; Beahy, V. R.

1980-06-01

59

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers  

SciTech Connect

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.

Takano, H.; Hosogi, K.; Kato, T. [Mitsubishi Electric Corp., Itami (Japan)] [and others

1995-05-01

60

A hybrid nanomemristor/transistor logic circuit capable of self-programming.  

PubMed

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-01-26

61

A hybrid nanomemristor/transistor logic circuit capable of self-programming  

PubMed Central

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

62

A superconductive integrated circuit foundry  

Microsoft Academic Search

A foundry has been established for production of superconductive integrated circuits, modeled after semiconductor application-specific integrated circuit (IC) production. The foundry supports and improves standardized Nb-based IC processing, and develops advanced processes such as a novel NbN-based process. The authors discuss the operation of the foundry, standardized process technologies, design rules, process flows, in-line product tracking, statistical process control, and

L. A. Abelson; S. L. Thomasson; J. M. Murduck; R. Elmadjian; G. Akerling; R. Kono; H. W. Chan

1993-01-01

63

Mouldable all-carbon integrated circuits  

NASA Astrophysics Data System (ADS)

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027cm2V-1s-1 and an ON/OFF ratio of 105. The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Sun, Dong-Ming; Timmermans, Marina Y.; Kaskela, Antti; Nasibulin, Albert G.; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I.; Ohno, Yutaka

2013-08-01

64

Scalable fabrication of self-aligned graphene transistors and circuits on glass.  

PubMed

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/?m. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (?20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices. PMID:21648419

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2011-06-14

65

Weaving integrated circuits into textiles  

Microsoft Academic Search

In this paper, we present and demonstrate a technology for integrating electronic functionality at the yarn level of woven textiles. The technology principles are compliant with commercial weaving processes and suitable for large scale manufacturing. Thin-film devices, interconnect lines and contact pads are patterned and silicon-based integrated circuits are attached to flexible plastic substrates. The substrates are cut into electronic

Christoph Zysset; Kunigunde Cherenack; Thomas Kinkeldei; G. Troster

2010-01-01

66

Microwave circuit model of the three-port transistor laser  

NASA Astrophysics Data System (ADS)

Based on an earlier charge control analysis, we have constructed a microwave circuit model of a three-port quantum-well (QW) transistor laser (TL) by extending Kirchhoff's law to include electron-photon interaction, to yield an electrical-optical form of Kirchhoff's law. The TL circuit model includes both intrinsic device elements and extrinsic parasitic elements, and fits accurately measured microwave S-parameters upto 20 GHz and matches also measured eye-diagram data up to 13 Gb/s (equipment-limited). The TL model yields both electrical and optical device parameters as well as physical quantities such as QW charge density, nQW~1016 cm-3, which is useful in the analysis of the device physics of TL operation. The low density indicates that the base QW charge level is not as important as the current driving the QW and supplying electron-hole recombination, and implies that the quasi-Fermi level is discontinuous in the TL base. The model is used to simulate a directly modulated TL up to 40 Gb/s, for example, a TL employed in an optical communication link.

Then, H. W.; Feng, M.; Holonyak, N.

2010-05-01

67

Superconductor integrated circuit fabrication technology  

Microsoft Academic Search

Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates\\/cm2. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex

LYNN A. ABELSON; GEORGE L. KERBER

2004-01-01

68

Highly resolved spatial and temporal photoemission analysis of integrated circuits  

NASA Astrophysics Data System (ADS)

We develop an optical system for highly resolved photoemission analysis of integrated circuits. Photons emitted by switching transistors allow the operation of an integrated circuit to be observed by recording the individual photoemission acts. The ongoing feature size reduction makes the space-time-resolved detection of these extremely weak photoemissions challenging. We combine different optical and photonic solutions to achieve both a high spatial and temporal resolution in a compact analysis system. Imaging and detection modules capture photons through the substrate during normal chip operation and perform highly resolved optical analysis. We demonstrate the system capability by photoemission records of a real-world IC device.

Schlösser, Alexander; Dietz, Enrico; Frohmann, Sven; Orlic, Susanna

2013-03-01

69

Hybrid optoelectronic integrated circuit.  

PubMed

The distribution of optical signals to a monolithic array of GaAs photoconductors by means of ion-exchanged glass optical waveguides is demonstrated. In this hybrid technique both optical and electronic interconnections of semiconductor elements are achieved through the use of a metallic interconnect layer deposited on the surface of a glass substrate which has a mating waveguide pattern. The low optical loss, ease of fabrication, and low material cost of diffused glass waveguides with such layers permit relatively large optoelectronic circuit boards to be made, in which numerous semiconductor active optoelectronic devices can be included. The device reported here serves as the signal distribution and cross-point switching section of an optoelectronic switch matrix. PMID:20454231

Macdonald, R I; Lam, D K; Syrett, B A

1987-03-01

70

Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors  

Microsoft Academic Search

In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102dB DC gain, and a 37.6MHz unity gain bandwidth while driving a 2nF heavy capacitive load at a single 1.8V supply. In the comparison of power-bandwidth and

Yang Tian; Pak Kwong Chan

2010-01-01

71

Design automation for integrated circuits  

NASA Astrophysics Data System (ADS)

Consideration is given to the development status of the use of computers in automated integrated circuit design methods, which promise the minimization of both design time and design error incidence. Integrated circuit design encompasses two major tasks: error specification, in which the goal is a logic diagram that accurately represents the desired electronic function, and physical specification, in which the goal is an exact description of the physical locations of all circuit elements and their interconnections on the chip. Design automation not only saves money by reducing design and fabrication time, but also helps the community of systems and logic designers to work more innovatively. Attention is given to established design automation methodologies, programmable logic arrays, and design shortcuts.

Newell, S. B.; de Geus, A. J.; Rohrer, R. A.

1983-04-01

72

Vertically Integrated Circuits at Fermilab  

SciTech Connect

The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

2010-01-01

73

Gallium arsenide for devices and integrated circuits  

SciTech Connect

Gallium Arsenide has long been hailed as the material of the future and it is only in recent years that the technology associated with its growth and processing has matured to the point where IC production can be contemplated at the industrial level. This point has now been reached and the electronics industries in Europe, the USA and Japan are actively moving from research activities into product development using this and related material. The text is divided into 15 chapters: Gallium Arsenide: Physical and Transport Properties; Liquid phase and Vapour Phase Epitaxy of GaAs and Related Compounds; Expitaxial Growth and GaAs: MBE and MOCVD; Characterization of GaAs I: Electrical Techniques; Characterization of GaAsII: Ion Beam Analysis; Ion Implantation; Wet and Dry Processing GaAs; Microwave and Millimetre - Wave Diodes; GaAs Mesfet's and High Electron Mobility Transistors (HEMT); Optoelectronic Devices and Components; Gallium Arsenide Monolithic Microwave Integrated Circuits; GaAs Digital Integrated Circuits; III-V Semiconductors for Solar Cells.

Morgan, D.V.; Thomas, H.

1986-01-01

74

EMP Susceptibility of Integrated Circuits  

Microsoft Academic Search

This paper summarizes the results of a major test program which involved the measurement of the pulse power failure thresholds of 41 integrated circuit types, representing seven logic families. The pulse widths used in these tests range from 0.1 microsecond to 10 microseconds. The failure threshold data have been grouped by logic family and test terminal to form failure categories.

C. R. Jenkins; D. L. Durgin

1975-01-01

75

Integrated optical circuit engineering V  

SciTech Connect

These proceedings compile papers presented at a conference on the subject of integrated optical circuit engineering. Some of the papers' titles are: Low loss optical waveguides by direct Ti ion implantation in LiNbO/sub 3/; new method for measuring waveguide propagation losses; optical multiplexer-demultiplexer for the photonic streak camera; dual-mode laser/detector diode; and growth and application superlattices and quantum wells; and integrated optics for fiber systems.

Mentzer, M.A.

1987-01-01

76

Experimental study on short-circuit characteristics of the new protection circuit of insulated gate bipolar transistor  

NASA Astrophysics Data System (ADS)

A new protection circuit employing the collector to emitter voltage (VCE) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition.

Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik

2006-09-01

77

Scalable fabrication of self-aligned graphene transistors and circuits on glass  

PubMed Central

High frequency graphene transistors with the intrinsic cut-off frequency up to 300 gigahertz (GHz) have been demonstrated for radio frequency (RF) applications. However, functional graphene RF circuits such as frequency doublers and mixers operating in the gigahertz range is yet to demonstrated. Here we report a scalable approach to fabricate self-aligned graphene transistors and circuits that can operate in gigahertz regime. The devices are fabricated through a self-aligned aligned process on glass substrate using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows to achieving unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/?m. With the minimization of parasitic capacitance on insulating substrate, the resulting graphene transistors exhibit a record high extrinsic cut-off frequency (> 50 GHz) achieved in graphene transistors to date. The excellent extrinsic cut-off frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1–10 GHz regime, a significant advancement over previous report (~20 MHz). The studies open a pathway to scalable fabrication of high speed graphene transistors and functional circuits, and represent a significant step forward to graphene based radio frequency devices.

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2011-01-01

78

Delay locked loop integrated circuit.  

SciTech Connect

This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

Brocato, Robert Wesley

2007-10-01

79

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress  

SciTech Connect

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base emitter junction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharged the energy now stored in the inductor discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Frosch, R.A.; Mclyman, W.T.

1981-06-30

80

Self-integration of nanowires into circuits via guided growth.  

PubMed

The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom-up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel "self-integration" of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

2013-07-31

81

Phase noise in transistorized synchronized superhigh-frequency oscillators with dissipative circuits  

Microsoft Academic Search

We present a study of the parameters of dissipative circuits and their influence of the effectiveness of synchronization and the level of phase noise in a transistorized synchronized superhigh-frequency transfer-type oscillator. It is established that the utilization of dissipative matched circuits makes it possible to expand the synchronization band by a factor of approximately two without impairing the noise characteristics

V. G. Lopato; A. V. Khramov

1988-01-01

82

A set of transistor circuits for asynchronous, direct-coupled computers  

Microsoft Academic Search

Extensive operating experience with the ORDVAC and the ILLIAC has demonstrated to members of the University of Illinois Computer Laboratory the advantages of computers which are direct-coupled and operate asynchronously. This paper describes a set of building block circuits, which is the first result of a program to develop transistor circuits which would be suitable for an asynchronous machine.

R. A. KUDLICHf

1955-01-01

83

Analytical modeling of device-circuit interactions for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The device-circuit interactions of the power insulated gate bipolar transistor (IGBT) for a series resistor-inductor load, both with and without a snubber, are simulated. An analytical model for the transient operation of the IGBT, previously developed, is used in conjunction with the load circuit state equations for the simulations. The simulated results are compared with experimental results for all conditions.

1990-01-01

84

New platforms for electronic devices: N-channel organic field-effect transistors, complementary circuits, and nanowire transistors  

Microsoft Academic Search

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized alpha,o-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N'-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric\\/electrode surface treatment on the response of bottom-contact devices was also examined

Byungwook Yoo

2007-01-01

85

Novel integrated CMOS sensor circuits  

Microsoft Academic Search

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge

Stuart Kleinfelder; Fred Bieser; Yandong Chen; Robin Gareus; Howard S. Matis; Markus Oldenburg; Fabrice Retiere; H. G. Ritter; Howard H. Wieman; Eugene Yamamoto

2004-01-01

86

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The drive circuit requirements of the insulated gate bipolar transistor (IGBT) are explained with the aid of an analytical model. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of anode voltage. Model results are compared with measured turn-on and turn-off waveforms for different drive, load, and feedback circuits, and for different

1991-01-01

87

The Impact of On-Chip Interconnections on CMOS RF Integrated Circuits  

Microsoft Academic Search

Achieving power- and area-efficient fully integrated transceivers is one of the major challenges faced when designing high-frequency electronic circuits suitable for biomedical applications or wireless sensor networks. The power losses associated with the parasitics of on-chip inductors, transistors, and interconnections have posed design challenges in the full integration of power-efficient CMOS radio-frequency integrated circuits (RF ICs). In addition, the parasitics

Munir M. El-Desouki; Samar M. Abdelsayed; M. Jamal Deen; Natalia K. Nikolova; Yaser M. Haddara

2009-01-01

88

Macromodeling of integrated circuit operational amplifiers  

Microsoft Academic Search

A macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation. The model elements are those which are common to most circuit simulators. The macromodel is a factor of more than six times less complex than the original circuit, and provides simulated circuit responses that have run times which are an order of magnitude

G. R. Boyle; D. O. Pederson; B. M. Cohn; J. E. Solomon

1974-01-01

89

Complementary Circuit with Self-Alignment Organic/Oxide Thin-Film Transistors  

NASA Astrophysics Data System (ADS)

Complementary logic circuits with self-alignment organic/oxide thin-film transistors (TFTs) were investigated. The layout and process steps of a self-alignment bottom-contact-type organic TFT and a top-contact type oxide TFT with a common layout pattern of the gate, source, and drain electrodes were proposed, and an integrated circuit was realized. The estimated field-effect mobilities, threshold voltages, and on-off ratios of the organic and oxide TFTs were 0.16 and 2.2 cm2 V-1 s-1, 2.2 and 2 V, and 3× 103 and 5.2× 106, respectively. From the complementary inverter characteristics, the voltage gain was 13 and the logic swing was 9.8 V at an applied voltage of 10 V. From the switching characteristics of the inverter, the rise and fall times were 18 and 46 ?s, respectively. The operations of the NAND and NOR logic circuit configurations were confirmed, and the maximum operational frequency of NAND logic was estimated to be over 100 kHz.

Takeda, Fumio; Sato, Ryuichi; Naka, Shigeki; Okada, Hiroyuki

2012-02-01

90

Flexible organic transistors and circuits with extreme bending stability  

Microsoft Academic Search

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands

Tsuyoshi Sekitani; Ute Zschieschang; Hagen Klauk; Takao Someya

2010-01-01

91

An 8Channel DRAGO Readout Circuit for Silicon Detectors With Integrated Front-End JFET  

Microsoft Academic Search

We have developed a CMOS circuit to be used with Silicon Drift Detectors (SDDs) for X-ray spectroscopy and gamma-ray imaging applications. The circuit operates with the input transistor integrated directly on the detector wafer. The circuit is composed of 8 analog channels, each including a low-noise voltage preamplifier, a 6th order semi-Gaussian shaping amplifier, with four selectable peaking times from

C. Fiorini; M. Porro; T. Frizzi

2006-01-01

92

Ultra-low power microwave CHFET integrated circuit development  

SciTech Connect

This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

Baca, A.G.; Hietala, V.M.; Greenway, D.; Sloan, L.R.; Shul, R.J.; Muyshondt, G.P.; Dubbert, D.F.

1998-04-01

93

Trends in development of bipolar power transistors  

Microsoft Academic Search

Monolithic integrated circuit technology was applied to bipolar power transistors which included Darlington transistors with preamplification. They are produced with two stabilizing resistors and sometimes also with two diodes for higher switching speed and for overvoltage protection respectively. Darlington transistors have higher current gain than plain silicon transistors of the same size so that they are indispensable for inverters. The

V. A. Potapchuk

1984-01-01

94

Design of RF integrated circuits using SiGe bipolar technology  

Microsoft Academic Search

We report on design aspects and the implementation of radio-frequency integrated circuits using TEMIC's SiGe technology. The differences between the device parameters of silicon bipolar junction transistor and silicon germanium heterojunction bipolar transistor technology and their influence on IC design are discussed. Design and measurement results of RFICs, including low noise amplifier, power amplifier, and single-pole, double-throw antenna switch for

R. Gotzfried; Frank Beisswanger; Stephan Gerlach

1998-01-01

95

Identification of degradation mechanisms in a bipolar linear voltage comparator through correlations of transistor and circuit response  

SciTech Connect

The input bias current (I{sub IB}) of the National LM111 voltage comparator exhibits a non-monotonic response to total dose irradiations at various dose rates. At low total doses, below 100 krad(SiO{sub 2}), increased I{sub IB} is due primarily to gain degradation in the circuit's input transistors. At high total doses, above 100 krad(SiO{sub 2}), I{sub IB} shows a downward trend that indicates the influence of compensating circuit mechanisms. Through correlation of transistor and circuit response, the transistors responsible for these compensating mechanisms are identified. Non-input transistors in the circuit's input stage lower the emitter-base operating point voltage of the input device. Lower emitter-base voltages reduce the base current supplied by the input transistors, causing a moderate recovery in the circuit response.

Barnaby, H.J.; Schrimpf, R.D.; Pease, R.L. [and others

1999-12-01

96

A monolithic 5 Gb\\/s p-i-n\\/HBT integrated photoreceiver circuit realized from chemical beam epitaxial material  

Microsoft Academic Search

The authors report on a high performance monolithic photoreceiver fabricated from chemical beam epitaxy (CBE) grown InP\\/InGaAs heterostructures, incorporating a p-i-n photodetector followed by a transimpedance preamplifier circuit configured from heterojunction bipolar transistors (HBTs). The optoelectronic integrated circuit (OEIC) was fabricated on a semi-insulating Fe-doped InP substrate. Microwave on-wafer measurements of the frequency response of the transistors yielded unity current

S. Chandrasekhar; A. H. Gnauck; W. T. Tsang; F. S. Choa; G.J. Qua

1991-01-01

97

Dynamic circuits for ternary computation in carbon nanotube based field effect transistors  

Microsoft Academic Search

As we continue downscaling devices, a number of nanoscale materials have been proposed as replacements for Silicon based devices. Carbon nanotubes have attracted widespread attention and numerous researchers have shown that digital circuits can be created using the field-effect properties of these nanoscale devices. This work investigates the design of multi-valued computation in carbon nanotube based field effect transistor (CNTFET).

Kundan Nepal

2010-01-01

98

Double Integrator Magnetic Amplifier Output Circuit.  

National Technical Information Service (NTIS)

The magnetic amplifier has an integrating circuit adapted to produce a sinusoidal output voltage. Two properly rated integrating circuits are applied to the output of a push-pull magnetic amplifier. An output current may be provided flowing through the ex...

W. A. Geyher

1965-01-01

99

A 6GHz integrated phase-locked loop using AlGaAs\\/GaAs heterojunction bipolar transistors  

Microsoft Academic Search

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs\\/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking

Aaron W. Buchwald; Kenneth W. Martin; Aaron K. Oki; Kevin W. Kobayashi

1992-01-01

100

Green biomass integrated electronic circuits  

Microsoft Academic Search

In this communication we report the successful development of an audio frequency amplifier and an astable multivibrator in a branch (with a stem and leaves) of a live Plumeria rubra (Indian Champo plant) and a cactus plant using external active devices (two Philips transistors BC 107B) and an external power supply. The green leaf mass structure substitutes for passive electronic

Shiv Prasad Kosta; Vimal Patel; Govind Shukla; Shakti Kosta; Y. P. Kosta; Amit Patel; Hemant Patel; Padma Kunthe; Sadhana Karsolia; Kalpesh M. Patel; Kalpesh G. Patel; Chirag Patel

2004-01-01

101

On the temperature behavior of the logarithmic integrated circuit current source  

Microsoft Academic Search

The logarithmic constant current source in silicon integrated circuit form has been analyzed in detail. It is shown that the temperature behavior is critically dependent on the voltage developed across the emitter resistor of the source transistor. This resistor value can be chosen so as to over, under, or perfectly temperature compensate the current source. The results are used to

A. B. Glaser; G. E. Sharpe

1975-01-01

102

Integrated circuit technology options for RFICs-present status and future directions  

Microsoft Academic Search

This paper will summarize the technology tradeoffs that are involved in the implementation of radio frequency integrated circuits for wireless communications. Radio transceiver circuits have a very broad range of requirements-including noise figure, linearity, gain, phase noise, and power dissipation. The advantages and disadvantages of each of the competing technologies-Si CMOS and bipolar junction transistors (BJTs), Si\\/SiGe HBTs and GaAs

Lawrence E. Larson

1998-01-01

103

A Simple 2-Transistor Touch or Lick Detector Circuit  

ERIC Educational Resources Information Center

|Contact or touch detectors in which a subject acts as a switch between two metal surfaces have proven more popular and arguably more useful for recording responses than capacitance switches, photocell detectors, and force detectors. Components for touch detectors circuits are inexpensive and, except for some special purpose designs, can be easily…

Slotnick, Burton

2009-01-01

104

Reusable vibration resistant integrated circuit mounting socket  

SciTech Connect

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Evans, C.N.

1993-12-31

105

Inductive Fault Analysis of MOS Integrated Circuits  

Microsoft Academic Search

Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types

John Shen; W. Maly; F. J. Ferguson

1985-01-01

106

Nonlinear system analysis in bipolar integrated circuits  

Microsoft Academic Search

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio

T. F. Fang; J. J. Whalen

1980-01-01

107

Development of beam lead RF integrated circuits  

Microsoft Academic Search

This paper describes the design and development of a set of multifunction VHF\\/UHF integrated circuits aimed at providing a major improvement in spacecraft radio reliability through low stress operation and the processing of these circuits in beam-lead form. The methods evolved for the high frequency characterization of the devices are discussed together with the design of suitable test fixtures. Typical

A. J. Kline; A. W. Kermode

1975-01-01

108

Base-width modulation and the high-frequency equivalent circuit of junction transistors  

Microsoft Academic Search

The effect of base-width modulation on the exact small-signal, high-frequency equivalent circuit of p-n-p (and n-p-n) junction transistors is examined. It is found that (except for the effect on the base spreading resistance) base-width modulation only helps to determine the magnitude of one element. Failure to recognize this fact has resulted in the past in the \\

J. Zawels

1957-01-01

109

Complementary organic thin film transistor circuits fabricated directly on silicone substrates  

Microsoft Academic Search

The present work demonstrates organic circuits on a new class of substrate, silicone elastomers. The fabrication method relies on dry, additive processes performed at ultra-low substrate temperature (<100°C). P-type pentacene and n-type C60 organic thin-film transistors (TFTs) in a bottom gate, top contact architecture are prepared directly on polydimethylsiloxane (PDMS) membranes without any surface pre-treatment. Simple logic elements including complementary

Ingrid M. Graz; Stéphanie P. Lacour

2010-01-01

110

Flexible pentacene organic thin film transistor circuits fabricated directly onto elastic silicone membranes  

Microsoft Academic Search

We have fabricated flexible pentacene thin film transistors (OTFTs) and active load inverter circuits directly onto polydimethylsiloxane (PDMS) membranes. Gold electrodes, parylene C gate dielectric, and pentacene films are deposited using a room temperature and all-vapor phase process on spin-coated or cast PDMS. The channel stack on PDMS is wrinkled but crack-free. The devices have good electrical properties with saturation

Ingrid M. Graz; Stéphanie P. Lacour

2009-01-01

111

Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors  

Microsoft Academic Search

In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant,

Alexandre Schmid; Yusuf Leblebici

2004-01-01

112

Thin-film transistor circuits on large-area spherical surfaces  

Microsoft Academic Search

We report amorphous silicon (a-Si:H) thin-film transistors (TFTs) fabricated on a planar foil substrate, which is then permanently deformed to a spherical dome, where they are interconnected to inverter circuits. This dome subtends as much as 66° (~1 sr) with the tensile strain reaching a maximum value of ~6% on its top. Functional TFTs are obtained if design rules are

P. I. Hsu; R. Bhattacharya; H. Gleskova; Min Huang; Z. Xi; Zhigang Suo; S. Wagner; J. C. Sturm

2002-01-01

113

Flexible pentacene organic thin film transistor circuits fabricated directly onto elastic silicone membranes  

NASA Astrophysics Data System (ADS)

We have fabricated flexible pentacene thin film transistors (OTFTs) and active load inverter circuits directly onto polydimethylsiloxane (PDMS) membranes. Gold electrodes, parylene C gate dielectric, and pentacene films are deposited using a room temperature and all-vapor phase process on spin-coated or cast PDMS. The channel stack on PDMS is wrinkled but crack-free. The devices have good electrical properties with saturation mobilities up to 0.2 cm2/V s, and on/off current ratio of 5×104. The OTFT circuits on PDMS withstand modest repeated bending without electrical failure.

Graz, Ingrid M.; Lacour, Stéphanie P.

2009-12-01

114

Modeling of Integrated Circuit Effectiveness (Mice).  

National Technical Information Service (NTIS)

A Stress Survival Matrix Test (SSMT) and Physical Effects Analysis (PEA) program was conducted on a type of monolithic silicon integrated circuit from two vendors. The purposes of the program were to identify the basic reliability characteristics of integ...

B. F. Tiger D. I. Troxel

1967-01-01

115

Monolithic Microwave Integrated Circuit Water Vapor Radiometer.  

National Technical Information Service (NTIS)

A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valua...

L. M. Sukamto T. W. Cooley M. A. Janssen G. S. Parks

1991-01-01

116

Vacuum Microwave Integrated Circuits for radar  

Microsoft Academic Search

Vacuum microwave integrated circuits (VMIC) for radar applications is suggested for design of radars with high resistance against radioactivity and high power electromagnetic. We present design of the VMIC suggested and give preliminary results of its feasibility study and implementation.

K. A. Lukin; Gun-Sik Park

2008-01-01

117

Nonlinear System Analysis in Bipolar Integrated Circuits.  

National Technical Information Service (NTIS)

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibilit...

T. F. Fang J. J. Whalen

1980-01-01

118

Automated Integrated Circuit Processing and Assembly.  

National Technical Information Service (NTIS)

The report describes the results of a study on automated procedures for integrated circuit (IC) processing and assembly by the semiconductor industry. Emphasis is on automated IC production, especially processing of wafers and assembly of chips into devic...

H. G. Rudenberg

1975-01-01

119

Accessibility of Applications Specific Integrated Circuits.  

National Technical Information Service (NTIS)

Applications specific integrated circuits (ASICs) open new design opportunities in Sandia component applications. ASICs can be used to overcome many of the constraints that reduce system functionality in Sandia systems. Key constraints in our environment ...

D. R. Strip

1986-01-01

120

On the electrical SOA of integrated vertical DMOS transistors  

Microsoft Academic Search

The dependency of the electrical safe operating area (SOA) of an integrated vertical DMOS transistor on the layout as well as on the residual epitaxial thickness of the drift region, is experimentally investigated using transmission line pulsing experiments. Guidelines for optimizing the SOA without compromising the other device parameters are given.

P. Moens; K. Reynders

2005-01-01

121

Design of poly-Si TFT-LCD panel with integrated driver circuits for an HDTV\\/XGA projection system  

Microsoft Academic Search

Design techniques of 2.25-in. diagonal poly-Si TFT-LCD panel for an HDTV\\/XGA projection system are described, especially focusing on the driver circuits. The area-efficiency of the driver circuits is a very important design issue, because the integrated poly-Si driver circuits takes a very large area due to inferior device characteristics of single crystal-Si transistors. For area-efficiency, the pixel with a novel

Byong-Deok Choi; Heuisung Jang; Oh-Kyong Kwon; Hong-Gyu Kim; Myung-Jin Soh

2000-01-01

122

Integrated Circuit Stellar Magnitude Simulator  

ERIC Educational Resources Information Center

|Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)|

Blackburn, James A.

1978-01-01

123

Integrated gate driver circuit solutions  

Microsoft Academic Search

Power electronics systems are commonly used in motor drive, power supply and power conversion applications. They cover a wide output power spectrum: from several hundred watts in small drives up to megawatts in wind-power installations or large drive systems. Inside the system the gate driver circuit with its extensive control and monitoring functions forms the interface between the microcontroller and

R. Herzer

2010-01-01

124

Chemical field-effect transistor with constant-voltage constant-current drain-source readout circuit  

Microsoft Academic Search

Response of Chemical Field-Effect Transistor (CHEMFET) electrochemical sensors are taken from the output of a readout interface circuit that maintains constant drain-source voltage and current levels. We employ the readout circuit for the purpose of supervised learning training data collection. Sample solutions are prepared by keeping the main ion concentration constant while the activity of an interfering ion varied based

W. F. H. Abdullah; M. Othman; M. A. M. Ali

2009-01-01

125

Variability in 3-D integrated circuits  

Microsoft Academic Search

In recent years, there has been a trend among digital and analog circuit designers towards three-dimensional integration. There has been some debate regarding the applicability of 3-D technology to general logic circuits, especially with regard to thermal issues. We examine process variations on the same layer, across layers, and cross-chip variations. We show how the performance of each layer of

Filipp Akopyan; C. Otero; D. Fang; S. J. Jackson; R. Manohar

2008-01-01

126

Fully transparent pixel circuits driven by random network carbon nanotube transistor circuitry.  

PubMed

Optically transparent and mechanically flexible thin-film transistors have recently attracted attention for next generation transparent display technologies. Driving and switching transistors for transparent displays have challenging requirements such as high optical transparency, large-scale integration, suitable drive current (I(on)) in the microampere range, high on/off current ratio (I(on)/I(off)), high field-effect mobility, and uniform threshold voltage (V(th)). In this study, we demonstrate fully transparent high-performance and high-yield thin-film transistors based on random growth of a single-walled carbon nanotube (SWNT) network that are easy to fabricate. High-performance SWNT-TFTs exhibit optical transmission of 80% in visible wavelength, I(on)/I(off) higher than 10(3), and a high yield with reproducible electrical characteristics. PMID:20450163

Kim, Sunkook; Kim, Seongmin; Park, Jongsun; Ju, Sanghyun; Mohammadi, Saeed

2010-06-22

127

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

Hammond, R.B.; Bowman, D.R.

1989-04-11

128

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, R.B.; Bowman, D.R.

1986-07-22

129

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1990-01-01

130

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1989-01-01

131

Layout techniques for integrated circuits  

SciTech Connect

Several techniques are presented for solving circuit-layout problems. In particular, a channel-placement algorithm is first introduced to reduce the channel density (d) so that a channel router can complete the routing requirements in fewer tracks. A 4-layer channel-routing model is then formulated so that a general channel routing problem (CRP) with cyclic conflicts and long critical paths can be completed with d/2. Finally, the 4-layer, 2-dimensional switchbox routing problem needed to enhance the channel routing in general circuit layout is investigated from the graph-theoretical viewpoint. The channel-placement technique consists of two phases. Using the principle of decomposition, the initial placement phase effectively reduces the complexity of the problem and, therefore, improves the efficiency of the second phase, which is called the iterative improvement placement. The main feature of this phase is its hill-climbing ability to avoid being trapped at local minima. The combination of these two phases leads to an efficient technique for standard cell placement. To utilize multi-layer technology, a new 4-layer channel routing model is introduced to minimize the channel width of more-generalized CRP's. The 2-dimensional switchbox routing problem is transformed to an equivalent graph-theoretical problem.

Tsay, C.Y.

1986-01-01

132

Package for integrated optic circuit and method  

DOEpatents

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

133

Four-Thin Film Transistor Pixel Electrode Circuits for Active-Matrix Organic Light-Emitting Displays  

Microsoft Academic Search

Constant-current, four-thin-film-transistor (TFT) pixel electrode circuits, based on hydrogenated amorphous silicon (a-Si:H) TFT technology for active-matrix organic light-emitting displays (AM-OLEDs), have been designed, fabricated, and characterized. Experimental results indicate that continuous pixel electrode excitation can be achieved with these circuits. The pixel electrode circuits use a current driver to automatically adjust their current level for threshold voltage shifts of both

Yi He; Reiji Hattori; Jerzy Kanicki

2001-01-01

134

Papers on Integrated Circuit Synthesis.  

National Technical Information Service (NTIS)

The ten papers that constitute this report were presented as term papers by graduate students at Stanford University for the electrical engineering course EE 292Y, 'Active Integrated Network Synthesis,' Spring Quarter, 1966. The majority of papers contain...

R. W. Newcomb T. N. Rao

1966-01-01

135

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.  

PubMed

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced. PMID:19198377

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

136

Phase-controlled integrated photonic quantum circuits.  

PubMed

Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externallycontrolled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms. PMID:19654759

Smith, Brian J; Kundys, Dmytro; Thomas-Peter, Nicholas; Smith, P G R; Walmsley, I A

2009-08-01

137

Integrated interfacing circuit for capacitive sensors  

SciTech Connect

A CMOS integrated interfacing circuit for use in capacitive sensors was fabricated and tested. The unique features of this circuit are: (1) the sensitivity and null point of the output voltage can be programmed independently by two controlled voltage sources; (2) the insensitivity of the circuit to large fixed stray capacitance, making it useful in silicon-to-silicon capacitive transducers and the two-chips module approach of sensor packaging; and (3) a high output level, with a sensitivity of 4.6 V/pF is obtained from a dual in-line package. The principle, operation, and applications of this circuit are presented in this thesis. The applications such as pressure transducer, accelerometer, angle sensors, and flowmeter are given.

Yeh, G.J.

1987-01-01

138

Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display  

Microsoft Academic Search

A high-resolution low-temperature polysilicon thin-film transistor driven light emitting polymer display (LT p-Si TFT LEPD) with integrated drivers has been developed. We adopted conductance control of the TFT and optimized design and voltage in order to achieve good gray scale and simple pixel circuit. A p-channel TFT is used in order to guarantee reliability in dc bias. An inter-layer reduces

Mutsumi Kimura; Ichio Yudasaka; Sadao Kanbe; Hidekazu Kobayashi; Hiroshi Kiguchi; Shun-ichi Seki; Satoru Miyashita; Tatsuya Shimoda; Tokuro Ozawa; Kiyofumi Kitawada; Takashi Nakazawa; Wakao Miyazawa; Hiroyuki Ohshima

1999-01-01

139

Single epitaxial structure for the integration of lasers with heterojunction bipolar transistors  

NASA Astrophysics Data System (ADS)

Heterojunction bipolar transistors (HBTs) are capable of producing very high speed digital integrated circuits operating as high as 40 GHz. In this paper we introduce a potentially low cost technique of monolithically integrating in-plane lasers with HBT circuits. A multifunctional epitaxial structure is used which is essentially the same as that for a standard high-speed HBT with modifications made to allow for efficient light amplification. Unlike previous multifunctional epitaxial structures, compromise in the transistor's performance is minimal. The schematic energy band diagrams of the HBT/laser structure biased as an HBT and laser are depicted. Light amplification is achieved by forward biasing the HBT's base- collector junction. The optical gain media is placed in the GaAs collector and consists of strained InGaAs quantum wells (QWs). Under normal HBT operation, the base-collector junction is reverse biased and serves as a sink for electrons which have diffused across the base. To confine electronic carries to the gain region when this junction is forward biased, the subcollector and base consist of a wider bandgap AlGaAs relative to the GaAs collector.

Goyal, Anish K.; Miller, Mark S.; Long, Stephen I.; Leonard, Devin

1994-06-01

140

Nano-technology-device prospects: quantum dots and transistors for ultracompact integration and terahertz analogue applications  

Microsoft Academic Search

Nanometric-sized transistors can be employed to control the charge transfer from one quantum dot (QD) to another one. The charge in a QD can also be used to control the transistor current. In principle here then electronics is not related to currents but due to charges. It is of interest, not only to apply this to ultracompact digital circuits, but

H. L. Hartnagel

1998-01-01

141

Integrated infrared detectors and readout circuits  

Microsoft Academic Search

The standard process for manufacturing mercury cadmium telluride (MCT) infrared focal plane arrays (FPAs) involves hybridising detectors onto a readout integrated circuit (ROIC). Wafer scale processing is used to fabricate both the detector arrays and the ROICs. The detectors are usually made by growing epitaxial MCT on to a suitable substrate, which is then diced and hybridised on to the

John W. Cairns; Louise Buckle; Graham J. Pryce; Janet E. Hails; Jean Giess; Mark A. Crouch; David J. Hall; Alan Hydes; Andrew Graham; Andrew J. Wright; Colin J. Hollier; David J. Lees; Neil T. Gordon; Timothy Ashley

2006-01-01

142

EPIC: Ending Piracy of Integrated Circuits  

Microsoft Academic Search

As semiconductor manufacturing requires greater cap- ital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unau- thorized excess production. While only recently studied, IC piracy has now become a major challenge for the electron- ics and defense industries (6). We propose a novel comprehensive technique to end piracy of integrated circuits (EPIC). It

Jarrod A. Roy; Farinaz Koushanfar; Igor L. Markov

2008-01-01

143

Integrated optical interconnections on printed circuit boards  

Microsoft Academic Search

The development of integrated optical interconnections (IOIs) represents a quantum leap for the functionality of printed circuit boards (PCBs). This new technology will allow highly complex product features and hence, higher product added value. PCBs with optical interconnections will be used where applications call either for very high data streams between components, modules or functional units (e.g. backplanes or multiprocessor

Markus Riester; Gregor Langer; Günther Leising

2007-01-01

144

Large-scale photonic integrated circuits  

Microsoft Academic Search

100-Gb\\/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb\\/s on a DWDM wavelength grid. Optical system performance results across a

R. Nagarajan; C. H. Joyner; J. S. Bostak; T. Butrie; A. G. Dentai; V. G. Dominic; P. W. Evans; M. Kato; M. Kauffman; D. J. H. Lambert; S. K. Mathis; A. Mathur; R. H. Miles; M. L. Mitchell; M. J. Missey; S. Murthy; A. C. Nilsson; F. H. Peters; S. C. Pennypacker; J. L. Pleumeekers; R. A. Salvatore; R. K. Schlenker; R. B. Taylor; Huan-Shang Tsai; M. F. Van Leeuwen; J. Webjorn; M. Ziari; D. Perkins; J. Singh; S. G. Grubb; M. S. Reffle; D. G. Mehuys; F. A. Kish; D. F. Welch

2005-01-01

145

Neutron-Induced Latch-Up Immunity in Metal Gate CMOS Integrated Circuits  

Microsoft Academic Search

Neutron-induced latch-up immunity has been studied in metal gate CMOS integrated circuits as a function of neutron fluence by measuring both the current gain products (beta product) of parasitic NPN and PNP transistors, and the flash x-ray latch-up thresholds prior to and following irradiation and subsequent stabilization anneal. Correlations between the actual latch-up thresholds and the measured beta products are

C. E. Barnes; J. G. Rollins; D. Hachey

1987-01-01

146

CMOS Integrated Circuit with Improved Temperature Behavior Based on a Temperature Optimized Auto-Programmable Loop  

Microsoft Academic Search

A new auto-programmable superior-order curvature-corrected integrated nanostructure will be presented, based on the compensation of the gate-source voltage temperature nonlinearity by a suitable biasing of a MOS transistor at a PTATalpha current. In order to maximize the temperature behavior of the system, a thermal stabilization circuit and an auto-programmable loop will be designed to select the optimal values for the

Cosmin Popa

2007-01-01

147

Compact Decoder-Type Gate Driver Circuits with Hydrogenated Amorphous Silicon Thin Film Transistors for Active Matrix Displays  

NASA Astrophysics Data System (ADS)

In this paper, we propose an integrated hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) gate driver circuit with parallely connected TFTs to resolve problems of the large circuit area and large number of input signals which are founded in the previously reported decoder-type and demultiplexer-type integrated gate drivers. The proposed gate driver can alleviate the demerits of previous gate drivers while maintaining their advantages: reduction of the threshold voltage (Vth) shift of the a-Si:H TFTs with an AC-driving structure and provide a stable low-impedance output. The key idea is to construct a novel decoder based on parallely connected TFTs instead of serially connected ones that are very common for decoders. The simulation results show that the rising time and falling time are 1.27 and 1.63 ?s respectively with -5 to 30 V output voltage swing which are suitable for high resolution active-matrix displays.

Kim, Jong-Seok; Park, Gyu-Tae; Kim, Hyun-Woo; Choi, Byong-Deok

2013-03-01

148

Displacement damage in bipolar linear integrated circuits  

SciTech Connect

The effects of proton and gamma radiation are compared for several types of integrated circuits with complex internal design and failure modes that are not as straightforward as the input bias current mechanism that is frequently used to study damage effects in linear devices. New circuit failure mechanisms were observed in voltage regulators that cause them to fail at much lower levels when they are irradiated with protons compared to tests with gamma rays at equivalent total dose levels. Protons caused much larger changes in output voltage than tests with gamma rays, which limits the maximum radiation level of some types of voltage regulators in environments dominated by protons.

Rax, B.G.; Johnston, A.H.; Miyahira, T.

1999-12-01

149

Data readout system utilizing photonic integrated circuit  

NASA Astrophysics Data System (ADS)

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Stopi?ski, S.; Malinowski, M.; Piramidowicz, R.; Smit, M. K.; Leijtens, X. J. M.

2013-10-01

150

SEMICONDUCTOR INTEGRATED CIRCUITS: A snap-shot mode cryogenic readout circuit for QWIPIR FPAs  

Microsoft Academic Search

The design and measurement of a snap-shot mode cryogenic readout circuit (ROIC) for GaAs\\/AlGaAs QWIP FPAs was reported. CTIA input circuits with pixel level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array. Design optimization techniques for cryogenic and low power are analyzed. An experimental ROIC chip of a 128 × 128 array

Ma Wenlong; Shi Yin; Zhang Yaohui; Liu Hongbing; Xie Baojian

2010-01-01

151

Heterojunction Bipolar Transistor Technology for Data Acquisition and Communication.  

National Technical Information Service (NTIS)

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized...

C. Wang M. Chang S. Beccue R. Nubling P. Zampardi

1992-01-01

152

Integrated Circuit Chip that Supports through Chip Electromagnetic Communication.  

National Technical Information Service (NTIS)

One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an elect...

A. R. Zingherann A. V. Krishnamoorthy R. J. Drost

2005-01-01

153

Introduction: The OptoElectronic Integrated Circuit  

Microsoft Academic Search

The history, present status and future prospects of silicon-based opto-electronic integrated circuits (OEICs) are reviewed here in order to provide a framework for the state-of-the-art discussions in this book. Before beginning the survey, let's consider some of the terminology used in opto-electronics. The Optical Society of America decided, after much debate, to replace many usages of the historic term 'optical'

Richard Soref

2008-01-01

154

The Future of Integrated Circuits: A Survey of Nanoelectronics  

Microsoft Academic Search

While most of the electronics industry is dependent on the ever-decreasing size of lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits built with components on the scale of 10 nm) seem to be the most promising successor to lithographic based ICs. Molecular-scale devices including diodes, bistable switches, carbon nanotubes, and nanowires have been fabricated and characterized in chemistry labs.

Michael Haselman; Scott Hauck

2010-01-01

155

Progress in radiation immune thermionic integrated circuits  

SciTech Connect

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

Lynn, D.K.; McCormick, J.B. (comps.)

1985-08-01

156

Accessibility of applications specific integrated circuits  

SciTech Connect

Applications specific integrated circuits (ASICs) open new design opportunities in Sandia component applications. ASICs can be used to overcome many of the constraints that reduce system functionality in Sandia systems. Key constraints in our environment are power consumption, volume, weight, speed, and radiation-hardness. In addition, use of ASICs may reduce the costs of system design, acquisition, and life-cycle maintenance. Design tools for integrated circuits are rapidly simplifying the design of integrated circuits. Just as high level computer languages enabled applications-oriented computer users to take control of their own code development after assembly coding had limited the practicality of user design, in ICC design tools and approaches are enabling the applications-oriented user to design an ASIC with modest training and in a short time period. In order to demonstrate the state of the design systems, we have selected a representative application and, without any formal training or experience in IC design, have designed and fabricated an ASIC. This report details the steps that were followed and the time they took. It is important to emphasize that this project was the first chip designed start-to-finish on the Mentor design stations in Organization 2110; therefore most of the problems encountered were typical of a first pass through a new system. Most of the problems were quickly wrung out by the CAD tools staff; future users of the system should not expect to have the problems recur.

Strip, D.R.

1986-03-01

157

Circuit design with adjustable threshold using the independently controlled double gate feature of the Vertical Slit Field Effect Transistor (VESFET)  

NASA Astrophysics Data System (ADS)

The recently introduced Vertical Slit Field Effect Transistor allows for adjusting its threshold voltage through independent controllable gates. This feature can be applied to a broad range of circuits. In this paper two examples are presented. First, a ring oscillator with a wide frequency tuning range and second, a Schmitt trigger with a controllable hysteresis.

Weis, M.; Schmitt-Landsiedel, D.

2010-11-01

158

Sequential circuit design for radiation hardened multiple voltage integrated circuits  

SciTech Connect

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

2009-11-24

159

Design of Analog Integrated Circuits by Using Genetic Algorithm  

Microsoft Academic Search

This paper applies the Artificial Intelligence technique called Genetic Algorithm (GA) to perform analog integrated circuits design, synthesis and optimization in order to reduce the development time and increase precision of this kind of circuits. In this work an accurate method to determine the device sizes in an analog integrated circuit on the basis of genetic algorithm is presented. To

A. Jafari; M. Zekri; S. Sadri; A. R. Mallahzadeh

2010-01-01

160

The current status and the principal problems of developing microwave transistors \\/Review  

Microsoft Academic Search

The state-of-the-art of microwave transistors is reviewed with reference to published theoretical and experimental work in this field. In particular, attention is given to the development of bipolar and field transistors, hybrid integrated circuits, and monolithic integrated circuits including low-noise input devices, high-power circuits, digital logic circuits, and GaAs circuits combining digital and analytic signal processing. Finally, future prospects for

V. V. Muravev; N. M. Naumovich

1982-01-01

161

3D packaging for integrated circuit systems  

SciTech Connect

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

Chu, D.; Palmer, D.W. [eds.

1996-11-01

162

Nobel Laureate e-Museum: Integrated Circuits  

NSDL National Science Digital Library

Nobel Laureate e-Museum's Educational section provides historical and scientific background information on inventions by those who have been honored with the Nobel Laureates in physics, chemistry, medicine, literature and peace over the years. For example, from this website, visitors can read about Nobel Laureate Jack Kilby and his part in the invention of integrated circuits, which are found in a variety of modern electrical device, including computers, cars, television sets, CD players, and cellular phones. A game called Techville is also free to download. A "walk through" will help you out if you get stuck on the game.

163

Barium silicate films for integrated optical circuits.  

PubMed

This paper describes the preparation and properties of rf sputtered barium silicate films that are suitable for use as transmission media in integrated optical circuits. It is shown that the films, which can be produced with a wide range of refractive indices by suitable selection of the ratio of the target constituents, exhibit low optical attenuation. The techniques used to deposit the films and the effect on loss of a number of parameters including pressure, film thickness, and substrate bias are discussed. PMID:20125380

Goell, J E

1973-04-01

164

Further developments in integrated circuit assembling technology  

NASA Astrophysics Data System (ADS)

Recent developments aiming at full automation in the assembling technology of plastic encapsulated integrated circuits (IC) are described, covering die separation, chip adhesion and wire bonding. For IC die separation in individual chips, a diamond sawing procedure which replaces the traditional scratch and break technique is proposed. Die attachment by means of a silver-filled adhesive was extended to MOS and power devices. A half-automated universal chip adhesion machine was designed and tested. A positioning system based on chip edge pattern recognition was developed. The prototype of a fully automated wire bonding system was successfully tested. The technical and economical advantages of these improved technologies are discussed.

Ullrich, H.

1982-09-01

165

Transistor Sizing in the Design of High-Speed CMOS (Complementary-Symmetry Metal-Oxide-Semiconductor) Super Buffers.  

National Technical Information Service (NTIS)

An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor (CMOS) integrated circuit logic design using silicon gate enhancement mode Field-Effect Transistors (FET) is derived and implemented in software. The algorithm...

G. R. Steele

1988-01-01

166

The Analysis of Four Types of Fluidic Active Integration Circuits.  

National Technical Information Service (NTIS)

Linear system analysis techniques were used to analyze several proposed integration circuits. This approach involved use of the approximate fluidic-electrical analogy between circuit components as well as several simplifying assumptions. Among these were ...

K. L. Waters

1968-01-01

167

Technologies for highly parallel optoelectronic integrated circuits  

SciTech Connect

While summarily reviewing the range of optoelectronic integrated circuits (OEICs), this paper emphasizes technology for highly parallel optical interconnections. Market volume and integration suitability considerations highlight board-to-board interconnects within systems as an initial insertion point for large OEIC production. The large channel count of these intrasystem interconnects necessitates two-dimensional laser transmitter and photoreceiver arrays. Surface normal optoelectronic components are promoted as a basis for OEICs in this application. An example system is discussed that uses vertical cavity surface emitting lasers for optical buses between layers of stacked multichip modules. Another potentially important application for highly parallel OEICs is optical routing or packet switching, and examples of such systems based on smart pixels are presented.

Lear, K.L. [Sandia National Labs., Albuquerque, NM (United States). Photonics Research Dept.

1994-10-01

168

Harnessing optical forces in integrated photonic circuits.  

PubMed

The force exerted by photons is of fundamental importance in light-matter interactions. For example, in free space, optical tweezers have been widely used to manipulate atoms and microscale dielectric particles. This optical force is expected to be greatly enhanced in integrated photonic circuits in which light is highly concentrated at the nanoscale. Harnessing the optical force on a semiconductor chip will allow solid state devices, such as electromechanical systems, to operate under new physical principles. Indeed, recent experiments have elucidated the radiation forces of light in high-finesse optical microcavities, but the large footprint of these devices ultimately prevents scaling down to nanoscale dimensions. Recent theoretical work has predicted that a transverse optical force can be generated and used directly for electromechanical actuation without the need for a high-finesse cavity. However, on-chip exploitation of this force has been a significant challenge, primarily owing to the lack of efficient nanoscale mechanical transducers in the photonics domain. Here we report the direct detection and exploitation of transverse optical forces in an integrated silicon photonic circuit through an embedded nanomechanical resonator. The nanomechanical device, a free-standing waveguide, is driven by the optical force and read out through evanescent coupling of the guided light to the dielectric substrate. This new optical force enables all-optical operation of nanomechanical systems on a CMOS (complementary metal-oxide-semiconductor)-compatible platform, with substantial bandwidth and design flexibility compared to conventional electrical-based schemes. PMID:19037311

Li, Mo; Pernice, W H P; Xiong, C; Baehr-Jones, T; Hochberg, M; Tang, H X

2008-11-27

169

SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs  

SciTech Connect

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Huque, Mohammad A [ORNL; Tolbert, Leon M [ORNL; Blalock, Benjamin [University of Tennessee, Knoxville (UTK); Islam, Syed K [University of Tennessee, Knoxville (UTK)

2010-01-01

170

Monolithic microwave integrated circuit water vapor radiometer  

NASA Astrophysics Data System (ADS)

A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

1991-12-01

171

Assembly and packaging technology for integrated circuits  

NASA Astrophysics Data System (ADS)

The electrical interconnections of semiconductor integrated circuit devices are manufactured by bonding fine-diameter wires to peripherally located thin film pads of aluminum, which make ohmic contact with the functional structures of the semiconductor. The aluminum or gold bonded wires are attached to their bond pads by ultrasonic, thermocompression or thermosonic techniques, and their outer ends are similarly bonded to a metal lead frame or to metallized substrates which achieve the circuitry's expansion from micro to macro dimensions. The metallurgical considerations affecting bond quality and reliability are related to the potential formation of intermetallic compounds and grain boundary deterioration in the wires and interfaces. The packaging used after the assembly operations described is primarily conducted in plastic or ceramic formats.

Rose, A. S.

1982-08-01

172

Fluidic microchemomechanical integrated circuits processing chemical information.  

PubMed

Lab-on-a-chip (LOC) technology has blossomed into a major new technology fundamentally influencing the sciences of life and nature. From a systemic point of view however, microfluidics is still in its infancy. Here, we present the concept of a microfluidic central processing unit (CPU) which shows remarkable similarities to early electronic Von Neumann microprocessors. It combines both control and execution units and, moreover, the complete power supply on a single chip and introduces the decision-making ability regarding chemical information into fluidic integrated circuits (ICs). As a consequence of this system concept, the ICs process chemical information completely in a self-controlled manner and energetically self-sustaining. The ICs are fabricated by layer-by-layer deposition of several overlapping layers based on different intrinsically active polymers. As examples we present two microchips carrying out long-term monitoring of critical parameters by around-the-clock sampling. PMID:23038405

Greiner, Rinaldo; Allerdissen, Merle; Voigt, Andreas; Richter, Andreas

2012-12-01

173

W-band integrated circuit PIN switches  

NASA Astrophysics Data System (ADS)

Both single-pole single-throw (SPST) and single-pole double-throw (SPDT) PIN switches have been developed at W band using microstrip integrated circuits. In SPST configurations, these switches have less than 1 dB of insertion loss under forward-voltage conditions from 90 to 108 GHz. Isolation greater than 20 dB over 3 GHz and greater than 10 dB over 7 GHz has been achieved. In SPDT configurations, insertion loss of less than 2 dB and isolation of more than 15 dB over 10 GHz (90 to 110 GHz) have been achieved. Beam-lead PIN diodes were used. Major features included mechanical ruggedness, light weight, small size and low-cost manufacturing.

Tahim, R. S.; Pham, T.; Chang, K.

1986-12-01

174

Nanowire transistor arrays for mapping neural circuits in acute brain slices.  

PubMed

Revealing the functional connectivity in natural neuronal networks is central to understanding circuits in the brain. Here, we show that silicon nanowire field-effect transistor (Si NWFET) arrays fabricated on transparent substrates can be reliably interfaced to acute brain slices. NWFET arrays were readily designed to record across a wide range of length scales, while the transparent device chips enabled imaging of individual cell bodies and identification of areas of healthy neurons at both upper and lower tissue surfaces. Simultaneous NWFET and patch clamp studies enabled unambiguous identification of action potential signals, with additional features detected at earlier times by the nanodevices. NWFET recording at different positions in the absence and presence of synaptic and ion-channel blockers enabled assignment of these features to presynaptic firing and postsynaptic depolarization from regions either close to somata or abundant in dendritic projections. In all cases, the NWFET signal amplitudes were from 0.3-3 mV. In contrast to conventional multielectrode array measurements, the small active surface of the NWFET devices, approximately 0.06 microm(2), provides highly localized multiplexed measurements of neuronal activities with demonstrated sub-millisecond temporal resolution and, significantly, better than 30 microm spatial resolution. In addition, multiplexed mapping with 2D NWFET arrays revealed spatially heterogeneous functional connectivity in the olfactory cortex with a resolution surpassing substantially previous electrical recording techniques. Our demonstration of simultaneous high temporal and spatial resolution recording, as well as mapping of functional connectivity, suggest that NWFETs can become a powerful platform for studying neural circuits in the brain. PMID:20133836

Qing, Quan; Pal, Sumon K; Tian, Bozhi; Duan, Xiaojie; Timko, Brian P; Cohen-Karni, Tzahi; Murthy, Venkatesh N; Lieber, Charles M

2010-01-19

175

Nanowire transistor arrays for mapping neural circuits in acute brain slices  

PubMed Central

Revealing the functional connectivity in natural neuronal networks is central to understanding circuits in the brain. Here, we show that silicon nanowire field-effect transistor (Si NWFET) arrays fabricated on transparent substrates can be reliably interfaced to acute brain slices. NWFET arrays were readily designed to record across a wide range of length scales, while the transparent device chips enabled imaging of individual cell bodies and identification of areas of healthy neurons at both upper and lower tissue surfaces. Simultaneous NWFET and patch clamp studies enabled unambiguous identification of action potential signals, with additional features detected at earlier times by the nanodevices. NWFET recording at different positions in the absence and presence of synaptic and ion-channel blockers enabled assignment of these features to presynaptic firing and postsynaptic depolarization from regions either close to somata or abundant in dendritic projections. In all cases, the NWFET signal amplitudes were from 0.3–3 mV. In contrast to conventional multielectrode array measurements, the small active surface of the NWFET devices, ?0.06 ?m2, provides highly localized multiplexed measurements of neuronal activities with demonstrated sub-millisecond temporal resolution and, significantly, better than 30 ?m spatial resolution. In addition, multiplexed mapping with 2D NWFET arrays revealed spatially heterogeneous functional connectivity in the olfactory cortex with a resolution surpassing substantially previous electrical recording techniques. Our demonstration of simultaneous high temporal and spatial resolution recording, as well as mapping of functional connectivity, suggest that NWFETs can become a powerful platform for studying neural circuits in the brain.

Qing, Quan; Pal, Sumon K.; Tian, Bozhi; Duan, Xiaojie; Timko, Brian P.; Cohen-Karni, Tzahi; Murthy, Venkatesh N.; Lieber, Charles M.

2010-01-01

176

Energy-efficient neuron, synapse and STDP integrated circuits.  

PubMed

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively. PMID:23853146

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

177

A CMOS neuroelectronic interface based on two-dimensional transistor arrays with monolithically-integrated circuitry.  

PubMed

The ability to monitor and to elicit neural activity with a high spatiotemporal resolution has grown essential for studying the functionality of neuronal networks. Although a variety of microelectrode arrays (MEAs) has been proposed, very few MEAs are integrated with signal-processing circuitry. As a result, the maximum number of electrodes is limited by routing complexity, and the signal-to-noise ratio is degraded by parasitics and noise interference. This paper presents a single-chip neuroelectronic interface integrating oxide-semiconductor field-effect transistors (OSFETs) with signal-processing circuitry. After the chip was fabricated with the standard complementary-metal-oxide-semiconductor (CMOS) process, polygates of specific transistors were etched at die-level to form OSFETs, while metal layers were retained to connect the OSFETs into two-dimensional arrays. The complete removal of polygates was confirmed by high-resolution image scanners, and the reliability of OSFETs was examined by measuring their electrical characteristics. Through a gate oxide of only 7nm thick, each OSFET can record and stimulate neural activity extracellularly by capacitive coupling. The capability of the full chip in neural recording and stimulation was further experimented using the well-characterised escape circuit of the crayfish. Experimental results indicate that the OSFET-based neuroelectronic interface can be used to study neuronal networks as faithfully as conventional electrophysiological tools. Moreover, the proposed simple, die-level fabrication process of the OSFETs underpins the development of various field-effect biosensors on a large scale with on-chip circuitry. PMID:18951013

Chang, C H; Chang, S R; Lin, J S; Lee, Y T; Yeh, S R; Chen, H

2008-09-19

178

Quantum-Optical Integrated Circuits of Gallium Arsenide.  

National Technical Information Service (NTIS)

The report describes quantum-optical logic circuits of gallium arsenide, developed using methods of semiconductor integrated technology. Laser integrated modules were made with electron-hole junctions formed by the diffusion method. The modules are made a...

I. S. Goldobin A. S. Dobkin

1971-01-01

179

Silicon Carbide MOSFET Integrated Circuit Technology  

NASA Astrophysics Data System (ADS)

The research and development activities carried out to demonstrate the status of MOS planar technology for the manufacture of high temperature SiC ICs will be described. These activities resulted in the design, fabrication and demonstration of the World's first SiC analog IC - a monolithic MOSFET operational amplifier. Research tasks required for the development of a planar SiC MOSFET IC technology included characterization of the SiC/SiO2 interface using thermally grown oxides; high temperature (350 °C) reliability studies of thermally grown oxides; ion implantation studies of donor (N) and acceptor (B) dopants to form junction diodes; epitaxial layer characterization; N channel inversion and depletion mode MOSFETs; device isolation methods and finally integrated circuit design, fabrication and testing of the World's first monolithic SiC operational amplifier IC. These studies defined a SiC n-channel depletion mode MOSFET IC technology and outlined tasks required to improve all types of SiC devices. For instance, high temperature circuit drift instabilities at 350 °C were discovered and characterized. This type of instability needs to be understood and resolved because it affects the high temperature reliability of other types of SiC devices. Improvements in SiC wafer surface quality and the use of deposited oxides instead of thermally grown SiO2 gate dielectrics will probably be required for enhanced reliability. The slow reverse recovery time exhibited by n+-p diodes formed by N ion implantation is a problem that needs to be resolved for all types of planar bipolar devices. The reproducibility of acceptor implants needs to be improved before CMOS ICs and many types of power device structures will be manufacturable.

Brown, D. M.; Downey, E.; Ghezzo, M.; Kretchmer, J.; Krishnamurthy, V.; Hennessy, W.; Michon, G.

1997-07-01

180

Accurate Substrate-Related Packaged Transistor Modeling for 24GHz Circuit Design  

Microsoft Academic Search

S-parameter measurements of packaged transistors are performed in dedicated microwave test fixtures and they provide the S-parameters with respect to reference planes usually extending to the transistor capsule. Most packaged transistors have typically an extra piece\\/length of the metal leads extending further from those reference planes, underneath the capsule, to enable the connection of each of the leads with the

Veljko Napijalo; Vicentiu Cojocaru; Takeshi Yokoyama; Thomas Young

2006-01-01

181

Test diagnostics of RF effects in integrated circuits  

Microsoft Academic Search

The results are presented for an effort to measure the RF upset susceptibilities of CMOS and low power Schottky integrated circuits and to demonstrate a test probe methodology for measuring RF noise coupling, generation, and propagation into and upon these integrated circuits chips. RF interference used was continuous wave CW from 1MHz to 200MHz. This was combined with the digital

David D. Wilson; Stan Epshtein; Mark G. Rossi; Christine L. Proffitt

1990-01-01

182

Low power integrated circuits for wireless neural recording applications  

Microsoft Academic Search

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit,

Xu Zhang; Weihua Pei; Qiang Gui; Hongda Chen

2008-01-01

183

Depth profiling of integrated circuits with thermal wave electron microscopy  

Microsoft Academic Search

Nondestructive depth profiling of integrated circuits was performed with thermal wave electron microscopy at a 640 kHz modulation frequency. Images were obtained at both a shallow penetration (near surface) and a deep penetration (subsurface) phase setting. It is the deep penetration image that provides new data and the capability for the nondestructive detection of subsurface flaws in integrated circuits. It

A. Rosencwaig

1980-01-01

184

A low noise readout circuit for integrated electrochemical biosensor arrays  

Microsoft Academic Search

This paper presents a low noise electrochemical interface circuit that is tuned to the needs of protein-based biosensor arrays and compatible with the formation of fully integrated biochemical microsystems. The circuit includes an integrated potentiostat and highly sensitive amperometric readout amplifier. It achieves good noise performance while supporting biosensor output currents from 10 pA to 10 ?A to suit a

Jichun Zhang; Nicholas Trombly; Andrew Mason

2004-01-01

185

Integrated Circuit Biosensors Using Living Whole-Cell Bioreporters  

Microsoft Academic Search

A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic\\/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the

Syed K. Islam; Rajagopal Vijayaraghavan; Mo Zhang; Steven Ripp; Sam D. Caylor; Brandon Weathers; Scott Moser; Stephen Terry; Benjamin J. Blalock; Gary S. Sayler

2007-01-01

186

Report on Radon Transform IC (integrated circuit)  

SciTech Connect

The goal of this project is to build an integrated circuit to calculate the Radon Transform and the backprojection operation at a 10 MHz video input rate. In completing this goal there are two different issues to be addressed. One is the analysis of the implementation of the Radon Transform in hardware and the second is the design and layout of the chip itself. The first issue involves studying different implementation algorithms and determining which algorithm is best suited for implementation on a chip. Because of its ease of implementation and small data size as compared with the exact transformations, the Radon Transform using interpolation was chosen. Interpolation in the forward transform requires interpolation in the backprojection operation as part of the calculation of the Inverse Radon Transform. Three interpolation schemes were considered for the forward transform and two schemes were considered for the backprojection. Of all these choices, the line length interpolation of the pixels in the forward transform along with linear interpolation of the values on the discrete s-axis resulted in the lowest mean squared error for high resolution reconstruction. However, line length interpolation needs four multiplications every clock period while linear interpolation needs only one. Software simulations showed no significant visual difference in the test images between the complicated line length interpolation and the linear interpolation for most applications of interest. As a result, linear interpolation was chosen in both the forward transform as well as the backprojection to reduce the chip area.

Agi, I.

1989-11-22

187

Optical Integrated Circuits Theory and Design  

NASA Astrophysics Data System (ADS)

The first part of this work describes the main theory required for the analysis and design of optical integrated circuits which have the purpose of processing light signals carried on fiber optic cables. For ease of fabrication it is advantageous to design the light processing channels in a planar geometry. The analysis of the resulting dielectric structures requires computations of both the propagation constants of the modes of the structures and the inherent energy losses resulting from the geometry of the light guiding channels. The latter losses have two primary sources, (1) radiation losses due to leakage out of the guiding channels into the supporting substrates, and (2) curvature losses due to the necessary bending of the guiding channels required to separate the light signals. The results of this work is a computer program for the design of a computer generated CAD lithographic mask that can be used to fabricate a multiple channel waveguiding structure capable of dividing an input light signal into a set number of output channels carrying designated fractions of the input energy. In the last part of this thesis we then apply the theory developed in first part to the design of a TE -TM polarization splitter. The resulting design represents an improvement over previous design suggested by other groups, and makes it possible to obtain a nearly 100% separation between the two orthogonal polarization states of the fields in a waveguide. All of the work of this thesis has potential applications in the construction of the superhighway.

Li, Xiangshan

1995-01-01

188

Integrated Fluidic Circuits (IFCs) for digital PCR.  

PubMed

The Fluidigm Digital Array IFC is a nanofluidic biochip where digital PCR reactions can be performed with isolated individual DNA template molecules. This chip is part of a family of integrated fluidic circuits (IFC) and contains a network of fluid lines, NanoFlex™ valves and chambers. NanoFlex™ valves are made of an elastomeric material that deflects under pressure to create a tight seal and are used to regulate the flow of liquids in the IFC. Digital Arrays have enabled a different approach to digital PCR, by partitioning DNA molecules instead of diluting them. Single DNA molecules are randomly distributed into nanoliter volume reaction chambers and then PCR amplified in the presence of a fluorophore-containing probe. Positive fluorescent signal indicates the presence of a DNA molecule in a reaction chamber, while negative chambers are blank. IFC technology enables the delivery of very precise volumes of solutions in a simple, fast procedure, utilizing a minimum of sample and assay reagents. The development of the IFC technology and the Digital Array chip has revolutionized the field of biology, and has been utilized in gene copy number studies, absolute quantitation (molecule counting) of genomic DNA and cDNA, rare mutation detection, and digital haplotyping. PMID:23329458

Ramakrishnan, Ramesh; Qin, Jian; Jones, Robert C; Weaver, L Suzanne

2013-01-01

189

Cmos-Compatible High Voltage Integrated Circuits.  

NASA Astrophysics Data System (ADS)

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 ?m CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS -bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT. The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.

Parpia, Zahir

190

SEMICONDUCTOR INTEGRATED CIRCUITS: 4 GHz bit-stream adder based on ?? modulation  

NASA Astrophysics Data System (ADS)

The conventional circuit model of a bit-stream adder based on sigma delta (??) modulation is improved with pipeline technology to make it work correctly at high frequencies. The integrated circuit (IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency. The IC is fabricated in TSMC's 0.18-?m CMOS process. The chip area is 475 × 570 ?m2. A fully digital ?? signal generator is designed with a field programmable gate array to test the chip. Experimental results show that the chip meets the function and performance demand of the design, and the chip can work at a frequency of higher than 4 GHz. The noise performance of the adder is analyzed and compared with both theory and experimental results.

Yong, Liang; Zhigong, Wang; Qiao, Meng; Xiaodan, Guo

2010-08-01

191

Organic electronics integration technology and logic circuits  

NASA Astrophysics Data System (ADS)

Organic transistor technology has been the subject of intense research in the last decade paving the way for industrialization of organic electronics applications characterized by low fabrication costs, additive manufacturing processes at low-energy, high flexibility and application versatility. A dedicated technology platform has been developed at ST and fully characterized, which is devoted to the manufacturing of all-organic transistor devices with sub-micron feature size as multilayered structures, obtained through a sequential combination of deposition from solution and patterning steps through stamps. The design and manufacturing platform is actually being assessed through the development of the first all-organic 'reduced complexity' microprocessor. An outline of the architecture and major building blocks will be presented.

Occhipinti, L.; La Rosa, M.; Rizzotto, G.

2008-08-01

192

Submillimeter-Wave 90 Polarization Twists for Integrated Waveguide Circuits  

Microsoft Academic Search

We present a novel full-waveguide-band 90° polarization twist implemented in full-height rectangular waveguide suitable for use in submillimeter-wave and terahertz-integrated waveguide circuits. Combined benefits of simplified fabrication, suitability for silicon micromachining, suitability for integration with other components into integrated waveguide circuits without interconnecting flanges, and alleviation of waveguide associated losses and mismatches, make this component well-suited for submillimeter-wave applications. A

Goutam Chattopadhyay; John S. Ward; Nuria Llombert; Ken B. Cooper

2010-01-01

193

Integration of silk protein in organic and light-emitting transistors  

PubMed Central

We present the integration of a natural protein into electronic and optoelectronic devices by using silk fibroin as a thin film dielectric in an organic thin film field-effect transistor (OFET) ad an organic light emitting transistor device (OLET) structures. Both n- (perylene) and p-type (thiophene) silk-based OFETs are demonstrated. The measured electrical characteristics are in agreement with high-efficiency standard organic transistors, namely charge mobility of the order of 10-2 cm2/Vs and on/off ratio of 104. The silk-based optolectronic element is an advanced unipolar n-type OLET that yields a light emission of 100nW.

Capelli, R.; Amsden, J. J.; Generali, G.; Toffanin, S.; Benfenati, V.; Muccini, M.; Kaplan, D. L.; Omenetto, F. G.; Zamboni, R.

2012-01-01

194

A new aSi:H thin-film transistor pixel circuit for active-matrix organic light-emitting diodes  

Microsoft Academic Search

We propose a new pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), composed of three switching and one driving TFT, for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage source method. The circuit simulation results based on the measured threshold voltage shift of a-Si:H TFTs by gate-bias stress indicate that this circuit compensates for the threshold voltage shifts

Joon-Chul Goh; Jin Jang; Kyu-Sik Cho; Choong-Ki Kim

2003-01-01

195

76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...  

Federal Register 2010, 2011, 2012, 2013

...No. 337-TA-806] Certain Digital Televisions Containing Integrated Circuit Devices...after importation of certain digital televisions containing integrated circuit devices...after importation of certain digital televisions containing integrated circuit...

2011-09-19

196

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...  

Federal Register 2010, 2011, 2012, 2013

...TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and Products...received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products...States after importation of certain semiconductor integrated circuit devices and...

2012-03-29

197

77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...  

Federal Register 2010, 2011, 2012, 2013

...Certain Integrated Circuits, Chipsets, and Products...Decision To Review in Part a Final Initial Determination...infringing integrated circuits, chipsets, and products...review the final ID in part. Specifically, the...within an integrated circuit package...

2012-09-18

198

Integrated circuit ac mutual inductance bridge for magnetic susceptibility measurements  

Microsoft Academic Search

A versatile ac mutual inductance bridge is described which uses integrated circuit operational amplifiers (op-amps) for the measurement of magnetic susceptibilities of ferro-, ferri-, and para-magnetic samples. The circuit employs op-amps both for balancing the bridge and for detecting the differential signal from the sample coil. The response of the circuit is linear over a wide range of sample susceptibilities,

C. M. Brodbeck; R. R. Bukrey; J. T. Hoeksema

1978-01-01

199

W-band multiport substrate-integrated waveguide circuits  

Microsoft Academic Search

Millimeter-wave passive circuits that are designed and fabricated in the form of substrate-integrated waveguide (SIW) are presented in this paper. A W-band SIW 90° hybrid coupler and multiport SIW circuit are made and synthesized on alumina substrate using metallized slot arrays. In order to connect the SIW circuits with WR-10 standard rectangular waveguides for measurement purposes, a new transition is

Emilia Moldovan; Renato G. Bosisio; Ke Wu

2006-01-01

200

A switched-capacitor interface circuit for integrated sensor applications  

Microsoft Academic Search

A new switched-capacitor interface circuit with differential-input single-ended output (DISO) for integrated sensor applications is presented. The circuit adopts the correlated double sampling technique combined with the auxiliary amplifier structure to cancel the 1\\/f noise and to minimize the systematic offset and errors due to charge injection. The simulated results show that the circuit exhibits a DC offset of 7

P. K. Chan; H. L. Zhang

2001-01-01

201

The developing technologies of integrated optical waveguides in printed circuits  

Microsoft Academic Search

High density interconnect (HDI) printed circuits are now being designed in ever-increasing quantities for very high-speed applications. The challenge of opto-electronics and integration of photonics into the printed circuit has started to take off. In the next 7 years, expectations are that photonic printed circuit boards will grow to a $2.5 billion industry. This paper looks at the issues, materials

Happy T. Holden

2003-01-01

202

An integrated-circuit-based speech recognition system  

NASA Astrophysics Data System (ADS)

A high-performance, flexible, and potentially inexpensive speech recognition system is described. The system is based on two special-purpose integrated circuits that perform the speech recognition algorithms very efficiently. One of these integrated circuits is the front-end processor, which computes spectral coefficients from incoming speech. The second integrated circuit computes a dynamic-time-warp algorithm. The system can compare an input word with 1000-word templates and respond to user within 1/4 s. The system demonstrates that computational complexity need not be a major limiting factor in the design of speech recognition systems.

Murveit, Hy; Brodersen, Robert W.

1986-12-01

203

A New Voltage between Collector and Emitter (VCE) Sensing Scheme for Short-Circuit Withstanding Capability of the Insulated Gate Bipolar Transistor  

NASA Astrophysics Data System (ADS)

A new protection circuit employing a voltage between collector and emitter (VCE) sensing scheme for the short-circuit withstanding capability of insulated gate bipolar transistors (IGBTs) is proposed and verified on the basis of two-dimensional simulation and experimental results. Because the current path between the gate and the collector can be successfully eliminated in the proposed protection circuit, power consumption can be reduced and gate input impedance can be increased. The experimental results show that the proposed protection circuit can adjust the current saturation level of IGBTs and the short-circuit withstanding capability can be significantly enhanced.

Jeon, Byung-Chul; Ji, In-hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik

2004-04-01

204

Design of integrated CMOS circuits for parallel detection and storage of optical data  

NASA Astrophysics Data System (ADS)

A CMOS circuit capable of storing optically transmitted data from a holographic read only memory (ROM) is described. The investigation focuses on combining optical and electronic circuit technology to rapidly transfer data in parallel fashion from a ROM to an array of static random-access memory (SRAM) cells. The proposed optoelectronic SRAM cells have an optical detection component as well as electrical read and write functions. Development of the optoelectronic memory circuit is based on research in several areas. A design method is described which applies MOS inverter transfer characteristics to the six-transistor CMOS SRAM cell. Circuit diagrams, layouts, and models are presented for photodetection devices adapted to integrated CMOS circuits. These devices are fabricated in standard CMOS processes for silicon. Performance characteristics are provided for photodetection devices with different load circuits. The optical data transfer technology is extended to other systems in which high speed and parallelism are essential. An array of the optoelectronic cells and many related devices and circuits have been designed, fabricated, and tested. Simulation and experimental results are given for circuits applicable to optical detection and electronic storage of data. The optical data transfer concept has been verified with a 16-bit optoelectronic SRAM. Data contained in a parallel array of 16-bit optoelectronic SRAM. Data contained in a parallel array of 16 light beams with an average power of 3.35 microwatts per bit were successfully transferred to the SRAM. The Argon laser light pattern was formed by both a mask and a hologram. The storage of the optical information was verified by electrical addressing of each cell. This research is a fundamental component of a massively parallel optical-to-electronic data transfer system being developed. Data is to be transferred to a RAM from a page-oriented holographic ROM containing up to 10(exp 11) bits of volume-multiplexed data.

Sayles, Andre Harding

1990-08-01

205

An IGBT gate driver integrated circuit with full-bridge output stage and short circuit protections  

Microsoft Academic Search

This paper presents a monolithic IGBT gate driver design with an original full-bridge topology output stage, implemented with high voltage LDMOSFETS (36-160V\\/1A) for power integrated circuits using standard low cost 2.5□m CMOS technology and oriented for digital applications. Short circuit protections have been also integrated. The full-bridge topology allows obtaining positive and negative gate voltages using a single floating power

A. Perez; X. Jorda; P. Godignon; M. Vellvehi; J. L. Galvez; J. Millan

2003-01-01

206

Integrated circuit chip with integrated plastic thin film capacitor  

NASA Astrophysics Data System (ADS)

A capacitor located directly on the integrated circuit (IC) was developed using plasma polymerization and sputtering of aluminum, for miniaturization in solid state techniques, combined with decreasing operating voltages and increasing switching frequencies. Electrical contact between IC pad and capacitor was achieved by conducting tracks. The capacitor size can be neglected. A capacitor with an organic dielectric, as well as reliable electrical contact and sufficient resistance against heat and moisture was developed in the following steps: setting up of a cooled electrode system for plasma polymerization with a specific gas distribution; development of a monomer gas mixture of hydrocarbons and perfluorated hydrocarbons, and introduction of defined tempering cycles and of an aperture concept which resulted in a high amount of electrode and dielectric layers.

Fetzer, Juergen; Schadt, Franz; Wittmann, Rudolf; Fischer, Albert; Goeke, Heinrich; Michel, Hartmut; Kammermaier, Johann

1986-12-01

207

Multichannel neural cuff electrodes with integrated multiplexer circuit  

Microsoft Academic Search

In order to restore hand function in spinal cord injured people by functional electrical stimulation of arm nerves, the authors developed an 18polar neural cuff type electrode with integrated multiplexer circuit. This circuit reduces the number of necessary interconnection leads to a stimulator from twelve to four. Cable reduction was intended to reduce the risk of cable breakage which is

Martin Schuettler; Klaus Peter Koch; Thomas Stieglitz; Oliver Scholz; Werner Haberer; Ralf Keller; Joerg-Uwe Meyer

2000-01-01

208

Ultrafast Electric Force Microscope for Probing Integrated Circuits  

Microsoft Academic Search

Design and failure analysis engineers are often faced with the tough challenge of testing high frequency signals at internal points of an integrated circuit (IC). They want to verify why and under what conditions do their circuits fail. Accurate magnitude and timing measurements are becoming increasingly harder to perform as IC technology pushes toward 100-nm line widths and gigahertz operating

Alfred Samson Hou

1995-01-01

209

Bit error rate measurement system for RF integrated circuits  

Microsoft Academic Search

This paper proposes a bit error rate (BER) measurement system utilizing vector signal analyzer (VSA) instrument built-in analog digital converter (ADC) and ideal digital baseband receiver of VSA software for RF integrated circuits (RFICs) such as RF amplifier, RF mixer and RF receiver. Usually, BER performance is estimated in transceiver with built-in digital baseband circuits. In the past, RF designers

Hsu-Feng Hsiao; Shuw-Guann Lin; Sy-Haur Su; Chih-Ho Tu; Da-Chiang Chang; Ying-Zong Juang; Hwann-Kaeo Chiou

2012-01-01

210

High-frequency distortion analysis of analog integrated circuits  

Microsoft Academic Search

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequency domain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with

Piet Wambacq; Georges G. E. Gielen; Peter R. Kinget; Willy Sansen

1999-01-01

211

High-Frequency Distortion Analysis of Analog Integrated Circuits  

Microsoft Academic Search

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequency- domain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with

Piet Wambacq; Georges G. E. Gielen; Peter R. Kinget; Willy Sansen

1999-01-01

212

The Design of Integrated Circuits to Observe Brain Activity  

Microsoft Academic Search

The ability to monitor the simultaneous electrical activity of multiple neurons in the brain enables a wide range of scientific and clinical endeavors. Recent efforts to merge miniature multielectrode neural recording arrays with integrated electronics have revealed significant circuit design challenges. Weak neural signals must be amplified and filtered using low-noise circuits placed close to the electrodes themselves, but power

Reid R. Harrison

2008-01-01

213

Statistical timing for parametric yield prediction of digital integrated circuits  

Microsoft Academic Search

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of

Jochen A. G. Jess; K. Kalafala; Srinath R. Naidu; Ralph H. J. M. Otten; Chandramouli Visweswariah

2003-01-01

214

Equivalent circuit of radiating longitudinal slots in substrate integrated waveguide  

Microsoft Academic Search

This paper presents the equivalent circuit of radiating longitudinal slots in substrate integrated waveguide (SIW). The simulated results using a MoM simulator are compared with measured results. They are shown in good agreement. These equivalent circuit is later used in the design of an array antenna using these slots as radiating elements.

Hsin-Chia Lu; Tah-Hsiung Chu

2004-01-01

215

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits  

Microsoft Academic Search

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context

Jochen A. G. Jess; Kerim Kalafala; Srinath R. Naidu; Ralph H. J. M. Otten; Chandramouli Visweswariah

2006-01-01

216

Modulated pulse audio power amplifiers for integrated circuits  

Microsoft Academic Search

Silicon monolithic circuits are best suited for applications with low power dissipation. Conventional approaches to audio power amplifiers have a rather limited efficiency, and are therefore not necessarily the best choice for integrated circuits. Pulse-width modulation, however, promises an efficiency of up to 100 percent and has several other advantages. Three approaches to amplitude to pulse-width conversion are discussed and

H. Camenzind

1966-01-01

217

Attachment method for stacked integrated circuit (IC) chips  

Microsoft Academic Search

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and\\/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections

A. F. Bernhardt; V. Malba

1999-01-01

218

Fully integrated current-mode CMOS gated baseline restorer circuits  

SciTech Connect

Design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR for each of the three gated integrator channels is a differential current-in to single ended current-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on-chip capacitor using pole splitting techniques. The BLRs for the constant fraction discriminator (CFD) constant fraction and arming comparators are differential current-in to voltage-out circuits with correction bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF and 2.5 pF respectively. The BLR circuits are capable of correcting differential input current offsets of {+-}40 {micro}A for the gated integrator circuits, {+-}100 {micro}A for the CFD constant fraction comparator circuit, and {+-} 160 {micro}A for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signal processing channels to be dc coupled. The BLR circuits correct for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integration period. CFD constant fraction comparator input offset is maintained at sub millivolt levels, and arming comparator threshold is maintained at a 0--0.48 V level under on-board DAC control.

Rochelle, J.M. [Univ. of Tennessee, Knoxville, TN (United States). Electrical and Computer Engineering Dept.; Binkley, D.M.; Paulus, M.J. [CTI PET Systems, Inc., Knoxville, TN (United States)

1995-08-01

219

Failure Mechanisms in Monolithic Integrated Circuits Fejlmekanismer I Monolitiske IC.  

National Technical Information Service (NTIS)

An informative description is presented of the most common failure mechanisms which occur in monolithic integrated circuits, particularly in plastic encapsulated components. There is also a brief description of the precautions already being applied, or th...

B. Schneider

1974-01-01

220

Study of Integrated Thermionic Circuits for Aerospace Application.  

National Technical Information Service (NTIS)

This report describes the study of the applicability of Integrated Thermionic Circuits (ITC) to data processing applications for aerospace systems in which nuclear and high temperature environments may be encountered. The specific systems which were selec...

G. T. Sendzuk D. E. Berglund G. W. Francis

1973-01-01

221

Partitioning and Redundancy Model for Wafer-Scale Integrated Circuits.  

National Technical Information Service (NTIS)

A general, architecture independent model to calculate the required amount of redundancy and the necessary degree of partitioning of the circuit to achieve a maximum efficiency are presented. In wafer scale integration, a certain amount of redundancy is r...

M. F. Beusekamp

1991-01-01

222

Test Diagnostics of RF Effects in Integrated Circuits.  

National Technical Information Service (NTIS)

This report presents the results of an effort to measure the RF upset susceptibilities of CMOS and low power Schottky integrated circuits and to demonstrate a test probe methodology for measuring RF noise coupling, generation, and propagation into and upo...

C. L. Proffitt D. D. Wilson M. G. Rossi S. Epshtein

1990-01-01

223

Structured Application-Specific Integrated Circuit (ASIC) Study.  

National Technical Information Service (NTIS)

Many of the digital electronic subsystems in defense applications require the small-size and power efficiency of application-specific integrated circuits (ASICs). Unfortunately, the high price and long design time of ASICs make them prohibitively expensiv...

D. Black-Schaffer J. Balfour P. Hartke W. Dally

2008-01-01

224

(In)AlGaN Heterojunction Field Effect Transistors and Circuits for High-Power Applications at Microwave and Millimeter-Wave Frequencies  

NASA Astrophysics Data System (ADS)

The suitability of the AlGaN/GaN heterostructure for applications up to 20 GHz is demonstrated based on a technically mature process. A broadband power amplifier integrated circuit is designed and fabricated in order to monitor the technology performance. Further, a 100 W power transistor for mobile communications is realized with an efficiency of 70% and an operation frequency of up to 3 GHz. We also demonstrate the performance of a 60 W switch-mode power amplifier module with 75% efficiency for industrial, scientific and medical applications at 2.4 GHz. To push the technology towards higher millimeter-wave frequencies an InAlGaN-based heterostructure was developed. This structure yields high sheet carrier concentration and mobility of 1.9× 1013 cm-2 and 1590 cm2 V-1 s-1, respectively. An excellent fT of 110 GHz and fmax of 190 GHz were achieved with HFETs with a gate length of 100 nm. This allowed the realization of InAlGaN-based power amplifier monolithic microwave integrated circuits (MMICs) operating at millimeter-wave frequencies of 60 and 94 GHz.

Maroldt, Stephan; Quay, Rüdiger; Dennler, Philippe; Schwantuschke, Dirk; Musser, Markus; Dammann, Michael; Aidam, Rolf; Waltereit, Patrick; Tessmann, Axel; Ambacher, Oliver

2013-08-01

225

Analysis of Transmission Lines on Integrated-Circuit Chips  

Microsoft Academic Search

The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern

I. T. Ho; S. K. Mullick

1967-01-01

226

All-optical ACP-OPLL photonic integrated circuit  

Microsoft Academic Search

The optical-phase-locked-loop linear phase demodulator is the most critical component for a high dynamic range phase modulated RF\\/Photonic link. Due to the stringent loop latency requirement, the OPLL should be implemented as a photonic integrated circuit. In this paper we address the design and implementation of an all optical attenuation-counter- propagating (ACP) optical-phase-locked-loop photonic integrated circuit. The preliminary experimental results

Y. Li; A. Bhardwaj; R. Wang; S. Jin; L. Coldren; J. Bowers; P. Herczfeld

2011-01-01

227

Polymeric aperture masks for high performance organic integrated circuits  

Microsoft Academic Search

The use of polymeric aperture masks to fabricate high performance pentacene-based integrated circuits is presented. The aperture masks are fabricated using a laser ablation process with capabilities of generating 10 mum features. A mask set consisting of 4-6 aligned layers has been fabricated and has been used to demonstrate functional rf-powered integrated circuits with 20 mum gate lengths. Devices consisted

Dawn V. Muyres; Paul F. Baude; Steven Theiss; Michael Haase; Tommie W. Kelley; Patrick Fleming

2004-01-01

228

Layout Based 3D Thermal Simulations of Integrated Circuits Components  

Microsoft Academic Search

\\u000a In this paper a three-dimensional (3D) thermal simulations of basic integrated circuit (IC) components are presented. The\\u000a layout of the real Application Specific Integrated Circuit (ASIC) generated in CAD CADENCE software was loaded into the CFD-ACE\\u000a environment, where 3D thermal simulations were done. The influence of many heating points was considered in simulations. Comparison\\u000a among several cooling conditions was also

Krzysztof Slusarczyk; Marek Kaminski; Andrzej Napieralski

2004-01-01

229

Layout based thermal simulations of 3D integrated circuits  

Microsoft Academic Search

In this paper, a three-dimensional (3D) thermal simulations of basic integrated circuit (IC) components are presented. The layout of the real application specific integrated circuit (ASIC) generated in CAD CADENCE software were loaded into the CFD-ACE environment, where the 3D thermal simulation was done. The influence of many heating points was considered in simulations. Comparison among several cooling conditions was

K. Slusarczyk; M. Kaminski; A. Napieralski

2004-01-01

230

Analog integrated circuits design for processing physiological signals.  

PubMed

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed. PMID:22275203

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

231

Heterojunction field effect transistors (HJFETs) for a readout circuit of a cryogenically cooled far-infrared detector  

NASA Astrophysics Data System (ADS)

Deep cryogenic field effect transistors (FETs) which are able to operate under liquid helium temperatures have significant advantages over conventional cryogenic Silicon- Junction-FETs or Si-metal-oxide-semiconductor-FETs as readout circuits of a far-IR focal plane array detector: simple operation, simple system structures, and large transconductance. We report the testing of an InGaAs-channel heterojunction field effect transistor (HJFET) operating at 4.2 K designed for a readout circuit of a cryogenically cooled far-IR detector. In this report, we present current- voltage characteristics, transconductance, low-frequency noise (LFN) characteristics, and the influence of the gate leakage current on the LFN characteristics of the HJFET. Input-referred noise voltage as low as a few hundred nanovolts at 1 Hz was measured for the HJFET with a 100 X 100 micrometers (superscript 2) gate area. We discuss further possibilities for the fabrication of HJFETs with an extremely small input current of less than 10(superscript -15) A.

Hosako, Iwao; Okumura, Kenichi; Yamashita-Yui, Yukari; Akiba, Makoto; Hiromoto, Norihisa

1998-08-01

232

Depth profiling of integrated circuits with thermal wave electron microscopy  

NASA Astrophysics Data System (ADS)

Nondestructive depth profiling of integrated circuits was performed with thermal wave electron microscopy at a 640 kHz modulation frequency. Images were obtained at both a shallow penetration (near surface) and a deep penetration (subsurface) phase setting. It is the deep penetration image that provides new data and the capability for the nondestructive detection of subsurface flaws in integrated circuits. It is possible, with a knowledge of the thermal properties of the circuit elements, to measure at what depth a flaw or defect occurs.

Rosencwaig, A.

1980-11-01

233

Circuit-level input integration in bacterial gene regulation.  

PubMed

Gene regulatory circuits can receive multiple simultaneous inputs, which can enter the system through different locations. It is thus necessary to establish how these genetic circuits integrate multiple inputs as a function of their relative entry points. Here, we use the dynamic circuit regulating competence for DNA uptake in Bacillus subtilis as a model system to investigate this issue. Specifically, we map the response of single cells in vivo to a combination of (i) a chemical signal controlling the constitutive expression of key competence genes, and (ii) a genetic perturbation in the form of copy number variation of one of these genes, which mimics the level of stress signals sensed by the bacteria. Quantitative time-lapse fluorescence microscopy shows that a variety of dynamical behaviors can be reached by the combination of the two inputs. Additionally, the integration depends strongly on the relative locations where the two perturbations enter the circuit. Specifically, when the two inputs act upon different circuit elements, their integration generates novel dynamical behavior, whereas inputs affecting the same element do not. An in silico bidimensional bifurcation analysis of a mathematical model of the circuit offers good quantitative agreement with the experimental observations, and sheds light on the dynamical mechanisms leading to the different integrated responses exhibited by the gene regulatory circuit. PMID:23572583

Espinar, Lorena; Dies, Marta; Cagatay, Tolga; Süel, Gürol M; Garcia-Ojalvo, Jordi

2013-04-09

234

Monolithically fabricated germanium-on-SOI photodetector and Si CMOS circuit for integrated photonic applications  

NASA Astrophysics Data System (ADS)

In this paper, we report our design and fabrication approach towards realizing a monolithic integration of Ge photodetector and Si CMOS circuits on common SOI platform for integrated photonic applications. The approach, based on the Ge-on-SOI technology, enables the realization of high sensitivity and low noise photodetector that is capable of performing efficient optical-to-electrical encoding in the near-infrared wavelengths regime. When operated at a bias of -1.0V, a vertical PIN detector achieved a lower Idark of ~0.57?A as compared to a lateral PIN detector, a value that is below the typical ~1?A upper limit acceptable for high speed receiver design. Very high responsivity of ~0.92A/W was obtained in both detector designs for a wavelength of 1550nm, which corresponds to a quantum efficiency of ~73%. Impulse response measurements showed that a vertical PIN photodetector gives rise to a smaller FWHM of ~24.4ps, which corresponds to a -3dB bandwidth of ~11.3GHz where RC time delay is known to be the dominant factor limiting the speed performance. Eye patterns (PRBS 27-1) measurement further confirms the achievement of high speed and low noise photodetection at a bit-rate of 8.5Gb/s. In addition, we evaluate the DC characteristics of the monolithically fabricated Si CMOS inverter circuit. Excellent transfer and output characteristics were achieved by the integrated CMOS inverter circuits in addition to the well behaved logic functions. We also assess the impact of the additional thermal budget introduced by the Ge epitaxy growth on the threshold voltage variation of the short channel CMOS transistors and discuss the issues and potential for the seamless integration of electronic and photonic integrated circuits.

Ang, Kah-Wee; Liow, Tsung-Yang; Yu, Ming-Bin; Fang, Qing; Song, Junfeng; Lo, Guo Q.; Kwong, Dim-Lee

2010-04-01

235

Integrated optical circuits for space applications  

NASA Astrophysics Data System (ADS)

In this paper some recent advancements in functional guided- wave devices and circuits having high potential impact in the space applications are discussed. Particular attention is addressed to the fields of earth observation, telecommunications, radar surveillance, and remote sensing, since they represent specific fields in the space sector where guided-wave devices can produce a significant improvement.

Armenise, Mario N.; Matteo, Anna M.

1997-12-01

236

Spatial gradients and multidimensional dynamics in a neural integrator circuit  

PubMed Central

In a neural integrator, the variability and topographical organization of neuronal firing rate persistence can provide information about the circuit’s functional architecture. Here we use optical recording to measure the time constant of decay of persistent firing (“persistence time”) across a population of neurons comprising the larval zebrafish oculomotor velocity-to-position neural integrator. We find extensive persistence time variation (10-fold; coefficients of variation 0.58–1.20) across cells within individual larvae. We also find that the similarity in firing between two neurons decreased as the distance between them increased and that a gradient in persistence time was mapped along the rostrocaudal and dorsoventral axes. This topography is consistent with the emergence of persistence time heterogeneity from a circuit architecture in which nearby neurons are more strongly interconnected than distant ones. Collectively, our results can be accounted for by integrator circuit models characterized by multiple dimensions of slow firing rate dynamics.

Miri, Andrew; Daie, Kayvon; Arrenberg, Aristides B.; Baier, Herwig; Aksay, Emre; Tank, David W.

2011-01-01

237

Efficient design of photonic integrated circuits (PICs) by combining device- and circuit- level simulation tools  

NASA Astrophysics Data System (ADS)

This work addresses a versatile modeling of complex photonic integrated circuits (PICs). We introduce a co-simulation solution for combining the efficient modeling capabilities of a circuit-level simulator, based on analytical models of PIC sub-elements and frequency-dependent scattering matrix (S-matrix) description, and an accurate electromagnetic field simulator that implements the finite element method (FEM) for solving photonic structures with complicated geometries. This is exemplified with the model of a coupled-resonator induced transparency (CRIT), where resonator elements are first modeled in the field simulator. Afterwards, the whole structure is created at a circuit level and statistical analysis of tolerances is investigated.

Arellano, C.; Mingaleev, S.; Koltchanov, I.; Richter, A.; Pomplun, J.; Burger, S.; Schmidt, F.

2013-03-01

238

Substrate Parasitic Extraction for RF Integrated Circuits  

Microsoft Academic Search

Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 ?m SiGe BiCMOS technology), presented here, illustrates how measurements

Andreia Cathelin; D. Saias; Didier Belot; Y. Leclercq; F. R. J. Clement

2002-01-01

239

Printed circuit board integrated fluxgate sensor  

Microsoft Academic Search

We have developed a cheap and simple trilayer printed circuit board (PCB)-based technology, adapted for the fabrication of fluxgate magnetic sensors. The two outer layers of the PCB stack comprise the electrical windings of the fluxgate, while the inner layer is made of patterned amorphous magnetic core with extremely high relative magnetic permeability (?r?100,000). The output voltage and the sensitivity

O. Dezuari; E. Belloy; S. E. Gilbert; M. A. M. Gijs

2000-01-01

240

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks  

Microsoft Academic Search

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The

Zhanping Chen; Mark Johnson; Liqiong Wei; Kaushik Roy

1998-01-01

241

Final Report on LDRD Project: Development of Quantum Tunneling Transistors for Practical Circuit Applications  

Microsoft Academic Search

The goal of this LDRD was to engineer further improvements in a novel electron tunneling device, the double electron layer tunneling transistor (DELTT). The DELTT is a three terminal quantum device, which does not require lateral depletion or lateral confinement, but rather is entirely planar in configuration. The DELTT's operation is based on 2D-2D tunneling between two parallel 2D electron

JERRY A. SIMMONS; JUENG-SUN MOON; MARK BLOUNT; SUNGKWUN K. LYO; WES E. BACA; JOHN L. RENO; MICHAEL P. LILLY; JOEL R. WENDT; MICHAEL C. WANKE; X. G. PERALTA; J. P. EISENSTEIN; P. J. BURKE

2002-01-01

242

Current-source aSi:H thin-film transistor circuit for active-matrix organic light-emitting displays  

Microsoft Academic Search

In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as ?3 V, the output current variations can be less than 1

Yi He; Reiji Hattori; Jerzy Kanicki

2000-01-01

243

Linearisation for analogue optical links using integrated CMOS predistortion circuits  

NASA Astrophysics Data System (ADS)

The demand for high-speed communications is growing exponentially. Recent trends in the integration of entire systems-on-chip have spurred the development of Fibre-To-The-Home (FTTH) network for high-speed data and video services. This paper presents a predistortion circuit that integrates all of the functions necessary to implement a high linearity distribution point system for broadband optical fibre communications. The single CMOS chip includes a variable gain amplifier and a predistortion circuit. The circuits have been implemented with 0.35?m CMOS technology and simulation shows that the power consumption is 86mW with a 3.3V supply. The systems and circuits are detailed and their application to analogue optical links discussed.

Lin, Fu-Chuan; Holburn, David M.

2005-06-01

244

Equivalent circuit analysis of an RF integrated ferromagnetic inductor  

Microsoft Academic Search

Summary form only given. Equivalent circuit of the on-top magnetic film-type radio-frequency (RF) integrated spiral inductor has been derived to analyze the real contribution of the permeability of the magnetic film to the inductance, L, and the quality factor, Q, of the inductor. The separation of parasitic impedances was the most critical issue. The equivalent circuit will also be required

T. Kuribara; M. Yamaguchi; K.-I. Arai

2002-01-01

245

Switching Transistor  

NASA Astrophysics Data System (ADS)

Westinghouse Electric Corporation's D60T transistors are used primarily as switching devices for controlling high power in electrical circuits. It enables reduction in the number and size of circuit components and promotes more efficient use of energy. Wide range of application from a popcorn popper to a radio frequency generator for solar cell production.

1981-01-01

246

Integrated circuit ac mutual inductance bridge for magnetic susceptibility measurements.  

PubMed

A versatile ac mutual inductance bridge is described which uses integrated circuit operational amplifiers (op-amps) for the measurement of magnetic susceptibilities of ferro-, ferri-, and para-magnetic samples. The circuit employs op-amps both for balancing the bridge and for detecting the differential signal from the sample coil. The response of the circuit is linear over a wide range of sample susceptibilities, and is calibrated directly in absolute units (emu) using a multiturn digital potentiometer. The sensitivity of the instrument for weak paramagnetic samples (1 g) is +/-3x10(-7) emu. PMID:18699301

Brodbeck, C M; Bukrey, R R; Hoeksema, J T

1978-09-01

247

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The drive circuit requirements of the OGBT are explained with the aid of an analytical model. This model can be used to describe the turn-on and turn-off, gate and anode, current and voltage waveforms for general external drive, load, and feedback circuits. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of

1990-01-01

248

Molecular Annotation of Integrative Feeding Neural Circuits  

PubMed Central

SUMMARY The identity of higher-order neurons and circuits playing an associative role to control feeding is unknown. We injected pseudorabies virus, a retrograde tracer, into masseter muscle, salivary gland and tongue of BAC-transgenic mice expressing GFP in specific neural populations and identified several CNS regions that project multi-synaptically to the periphery. MCH and orexin neurons were identified in the lateral hypothalamus, and Nurr1 and Cnr1 in the amygdala and insular/rhinal cortices. Cholera Toxin-? tracing showed that insular Nurr1+ and Cnr1+ neurons project to the amygdala or lateral hypothalamus, respectively. Finally we show that cortical Cnr1+ neurons show increased Cnr1 mRNA and c-Fos expression after fasting, consistent with a possible role for Cnr1+ neurons in feeding. Overall, these studies define a general approach for identifying specific molecular markers for neurons in complex neural circuits. These markers now provide a means for functional studies of relevant neurons in feeding or other complex behaviors.

Perez, Cristian A.; Stanley, Sarah A.; Wysocki, Robert W.; Havranova, Jana; Ahrens-Nicklas, Rebecca; Onyimba, Frances; Friedman, Jeffrey M.

2012-01-01

249

The resonant body transistor.  

PubMed

This paper introduces the resonant body transistor (RBT), a silicon-based dielectrically transduced nanoelectromechanical (NEM) resonator embedding a sense transistor directly into the resonator body. Combining the benefits of FET sensing with the frequency scaling capabilities and high quality factors (Q) of internal dielectrically transduced bar resonators, the resonant body transistor achieves >10 GHz frequencies and can be integrated into a standard CMOS process for on-chip clock generation, high-Q microwave circuits, fundamental quantum-state preparation and observation, and high-sensitivity measurements. An 11.7 GHz bulk-mode RBT is demonstrated with a quality factor Q of 1830, marking the highest frequency acoustic resonance measured to date on a silicon wafer. PMID:20180594

Weinstein, Dana; Bhave, Sunil A

2010-04-14

250

Integrated circuit ceramic ball grid array package antenna  

Microsoft Academic Search

The recent advances in such highly integrated RF transceivers as radio system-on-chip and radio system-in-package have called for the parallel development of compact and efficient antennas. This paper addresses the development of a new type of dielectric chip antenna known as integrated circuit package antenna (ICPA) for highly integrated RF transceivers. A compact ICPA of this type has, for the

Y. P. Zhang

2004-01-01

251

Transistorized Radiation Monitors  

Microsoft Academic Search

The advantages of transistors over vacuum tubes in radiation instruments have long been realized but a somewhat different approach to circuit design must be followed in developing transistor instruments, as compared with that used in vacuum tube circuits, and this seems to have discouraged many from developing such circuits. The purpose of this paper is to describe in some detail

F. S. Goulding

1958-01-01

252

A CMOS integrated timing discriminator circuit for fast scintillation counters  

SciTech Connect

Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

Jochmann, M.W. [Forschungszentrum Juelich (Germany). Zentrallabor fuer Elektronik

1998-06-01

253

Process control for 0.25 um GaAs microwave monolithic integrated circuits  

NASA Astrophysics Data System (ADS)

Gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) are used in analog microwave monolithic integrated circuits (MMICs) because of their high frequency response. Common applications for MMICs include low noise and power amplifiers for use in satellite communication and missile guidance systems. The performance of MESFETs is improved with smaller gate lengths, but to consistently achieve the highest performance, control methods must be in place for the critical processes. Gate length control is the key parameter in maintaining the rf performance and a lack of gate pinch off is the major yield loss category. This paper describes the process and the tools that Texas Instruments uses to monitor the critical parameters. It also describes the control methods and reviews the major contributors to variations in the process.

Hudgens, Rick D.; Meyers, Shirley; Small, Bret A.; Salzman, Keith; Rhine, David; Class, Randy

1994-05-01

254

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers  

NASA Astrophysics Data System (ADS)

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized

Hsu, Yu-Jen

255

Cantilever couplers for fiber coupling to silicon photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Cantilever couplers for fiber coupling to silicon photonic integrated circuits are presented. The couplers consist of silicon inverse width tapers embedded within silicon dioxide cantilevers that are deflected out-of plane by residual stress. Coupling efficiencies of 1.6 dB per connection for TE polarization and 2 dB per connection for TM polarization are achieved. Finite difference time domain simulations are conducted to assess coupling loss as a function of cantilever geometry and fiber-to-cantilever misalignment. The cantilever couplers enable high efficiency propagation of light from optical fibers to photonic integrated circuits directly on a chip surface without dicing or cleaving.

Reano, Ronald M.; Sun, Peng

2010-02-01

256

3D circuit integration for Vertex and other detectors  

SciTech Connect

High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

Yarema, Ray; /Fermilab

2007-09-01

257

77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...  

Federal Register 2010, 2011, 2012, 2013

...No. 337-TA-848] Certain Radio Frequency Integrated Circuits...after importation of certain radio frequency integrated circuits...be obtained by accessing its internet server at http://www.usitc...after importation of certain radio frequency integrated...

2012-06-13

258

Ge photodetectors integrated in CMOS photonic circuits  

NASA Astrophysics Data System (ADS)

We describe our approach to the monolithic integration of Ge photodetectors in a photonics-enabled CMOS technology. Ge waveguide photodetectors allow fast and efficient conversion of optical signals in the near infrared (1.55?m) to the electrical domain thus enabling the fabrication of compact, high speed (10Gbps) receivers.

Masini, G.; Sahni, S.; Capellini, G.; Witzens, J.; White, J.; Song, D.; Gunn, C.

2008-02-01

259

Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature.  

PubMed

The wide bandgap and highly transparent inorganic compound copper(I) thiocyanate (CuSCN) is used for the first time to fabricate p-type thin-film transistors processed from solution at room temperature. By combining CuSCN with the high-k relaxor ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm(2) V(-1) s(-1) . By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. PMID:23280854

Pattanasattayavong, Pichaya; Yaacobi-Gross, Nir; Zhao, Kui; Ndjawa, Guy Olivier Ngongang; Li, Jinhua; Yan, Feng; O'Regan, Brian C; Amassian, Aram; Anthopoulos, Thomas D

2012-12-27

260

High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel  

NASA Astrophysics Data System (ADS)

Polycrystalline silicon thin-film transistors (TFTs) integrating sputtered Al2O3 gate dielectric with bridged-grain active channel are demonstrated. The proposed TFTs exhibit excellent device performance in terms of smaller threshold voltage, steeper subthreshold swing and higher on-current/off-current ratio. More importantly, the mobility of the proposed TFT is 5.5 times that of conventional TFTs with SiO2 gate dielectric. All of these results suggest that the proposed TFT is a good choice for low-power and high-speed driving circuits in display application.

Zhang, Meng; Zhou, Wei; Chen, Rongsheng; Wong, Man; Kwok, Hoi-Sing

2013-11-01

261

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit  

NASA Astrophysics Data System (ADS)

The silicon (Si) surrounding-gate metal-oxide-semiconductor field-effect transistor (MOSFET) has ultimate gate structures and is a potential candidate for use in next-generation high-performance nano-devices. However, because of limitations of the fabrication process, theoretically ideally round shape of the surrounding gate may not always guarantee. These limitations may lead to the formation of an ellipse-shaped surrounding gate with major (a) and minor (b) axes of different lengths. In this study, the effect of the geometry aspect ratio, a/b, on the dc and ac characteristics of the 16 nm gate ellipse-shaped surrounding-gate MOSFETs and circuits is examined by using a three-dimensional coupled device-circuit simulation technique. The dependences of electrical characteristics on the geometry aspect ratio are evaluated with reference to various device characteristics and the circuit properties, including the circuit gain, the 3 dB bandwidth, the unity-gain bandwidth, the rise/fall time and the delay time. In analog circuits, the device with an aspect ratio of less than 1 is promising because the short-channel effect is suppressed. However, for a digital circuit configuration, the transient response of the circuit relies on the charge/discharge capability of the transistor. Thus, a device with a large aspect ratio, such as 2, will be more suitable for digital applications.

Li, Yiming; Hwang, Chih-Hong

2009-09-01

262

Integrated circuit security techniques using variable supply voltage  

Microsoft Academic Search

This paper addresses integrated circuit (IC) security issues by using supply voltage based gate-level characterization (GLC). Our GLC scheme is capable of characterizing both manifestation and physical level properties of an IC accurately using variable supply voltage. We demonstrate that the proposed scheme can detect three types of IC attacks with low false positives and false negatives.

Sheng Wei; Miodrag Potkonjak

2011-01-01

263

Large-Value Monolithic Resistors for Micropower Integrated Circuits.  

National Technical Information Service (NTIS)

The minimum power dissipation of micropower integrated circuits is often limited by the availability of large-value monolithic resistors. In this paper two major types of field-effect resistor structures are examined and an analysis of the primary factors...

P. H. Hudson J. S. Kesperis J. D. Meindl

1971-01-01

264

Genetic applets: biological integrated circuits for cellular control  

Microsoft Academic Search

Technological advances in the biological sciences, coupled with increasing technical and economic challenges for silicon-based computing, generate interest in biocomputing. A genetic flip-flop and a genetic clock, recently implemented bacterial cells, may form the basic elements of a biochemical integrated circuit that operates in a living cell

T. S. Gardner

2001-01-01

265

Alcohol Modified RTV Silicone Encapsulation for Integrated Circuit Device Packaging  

Microsoft Academic Search

Room temperature vulcanized (RTV) silicone elastomer has been proven to be one of the most effective encapsulants for mechanical, moisture, electrical, and alpha particle protection of bipolar, metal--oxide semiconductor (MOS), and hybrid integrated circuit (IC) devices. This RTV material is also one of the few commercial polymer materials that meets Bell System encapsulant specifications. The chemistry of the silicone elastomer

Ching-Ping Wong; DENI M. ROSE

1983-01-01

266

Repair machine for integrated circuits using laser-induced microchemistry  

Microsoft Academic Search

Summary form only given. Design mistakes may appear during the validation steps of integrated circuits. Designers need a machine able to modify the interconnection network in an IC prototype during tests. A repair process by laser direct writing of microstructure was achieved via local decomposition of gases in submicron areas on IC chips. Experimental procedures for conductor (Ni) or insulator

J. J. Gerard

1988-01-01

267

Vacuum Microwave Integrated Circuits for radar RF front-end  

Microsoft Academic Search

A new innovative application of vacuum microwave electronics is suggested. Vacuum Microwave Integrated Circuits (VMIC) is suggested for design of radar front-end with high resistance against radioactivity and high power electromagnetic signals. We describe general approach to design of the VMIC suggested and give preliminary results of its possible implementation and future applications.

Konstantin A. Lukin; Gun-Sik Park

2009-01-01

268

K(a) Band Microwave Integrated Circuit SPDT Switch Development.  

National Technical Information Service (NTIS)

The report describes the design and development of a Ka-band (26.5 - 40 GHz) microstrip microwave integrated circuit SPDT switch with driver. The report describes the plated heat sink PIN diodes and the waveguide to microstrip transitions used in the desi...

C. Buntschun

1979-01-01

269

Ka-Band Microwave Integrated Circuit SPDT Switch Development.  

National Technical Information Service (NTIS)

The report describes the design and development of Ka-band (26.5 - 40 GHz) microstrip and finline microwave integrated circuit SPDT switches with drivers. The report describes the plated heat sink PIN diodes and the waveguide to microstrip and finline tra...

C. Buntschuh

1979-01-01

270

Modeling electromagnetic emission of integrated circuits for system analysis  

Microsoft Academic Search

In this contribution a new methodology for modeling elec- tromagnetic emission of integrated circuits in system anal- ysis is shown. By using a physical model based on a multi- pole expansion, the emitted fields can be well approximated in the space outside a component. This allows a conve- nient representation with a low number of model parame- ters which can

P. Kralicek; Werner John; Heyno Garbe

2001-01-01

271

Ferromagnetic RF integrated inductor with closed magnetic circuit structure  

Microsoft Academic Search

Closed magnetic circuit type ferromagnetic RF integrated inductors have been fabricated based on MEMS-like micro fabrication techniques. The taper etching process greatly helped to endure sufficient magnetic flux flow at the edge of the top and bottom magnetic layers. Air cores and three different sandwich type ferromagnetic inductors are also microfabricated. Measured results exhibited the quality factor Q=12, being highest

Masahiro Yamaguchi; Seok Bae; Ki Hyeon Kim; Kenji Tan; Takayuki Kusumi; Kiyoshi Yamakawa

2005-01-01

272

1998 technology roadmap for integrated circuits used in critical applications  

SciTech Connect

Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

Dellin, T.A.

1998-09-01

273

Focused Ion Beam as an Integrated Circuit Restructuring Tool.  

National Technical Information Service (NTIS)

One of the capabilities of focused ion beam systems is ion milling. The purpose of this work is to explore this capability as a tool for integrated circuit restructuring. Methods for cutting and joining conductors are needed. Two methods for joining condu...

J. Melngailis C. R. Musil E. H. Stevens M. Utlaut E. M. Kellog

1986-01-01

274

Integrated circuits for an implantable CW Doppler ultrasonic flowmeter  

Microsoft Academic Search

A totally implantable telemetry system for monitoring instantaneous blood flow in major arteries within animals has been developed. The system provides a new and necessary tool for accurate quantitative measurements in the study of cardiovascular disease. Low voltage micropower integrated circuits are essential in this application to achieve the low power consumption, small size, and high reliability required in an

DAVID M. DIPIETRO; JAMES D. MEINDL

1977-01-01

275

Distributed Processing Within an Integrated Circuit\\/Packet-Switching Node  

Microsoft Academic Search

Based on the premise that flexibility is a primary objective for future data networks, it is proposed to integrate circuit switching (CS) and packet switching (PS) in a single network. This paper addresses the switching node in such a network. A novel node concept is presented, imposing PS on a CS structure. Connection management and node control functions on the

CHRISTIAN J. JENNY; KARL KUMMERLE

1976-01-01

276

Radiation response of high speed CMOS integrated circuits  

SciTech Connect

This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis.

Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

1987-12-01

277

Isoperibolic Calorimetric Cell with Electronic Integrator Circuit for Temperature Measurement  

Microsoft Academic Search

An isoperibolic calorimetric cell, formed with double plastic insulation, is connected to a conventional Dewar glass. The cell has a lid on which are placed an electronic thermometer and an electric resistor to provide the cell with specific quantities of electrical work.The thermometer, built with an LM35 integrator circuit, presents an output potential signal which is proportional to the temperature

Paola Martínez; Liliana Giraldo; Edgar Vargas; Juan Carlos Moreno

2005-01-01

278

Life cycle assessment of an integrated circuit product  

Microsoft Academic Search

The use of integrated circuits (ICs) is continually increasing in any kind of industrial products and in particular in the electronic and information and communications technology products. The environmental impact related to the use and production phases of the ICs could be potentially very strong due to the high technological level of the process, the amount of energy and the

Fulvio Taiariol; Patrizia Fea; Claudio Papuzza; Raffaella Casalino; Enrico Galbiati; S. Zappa

2001-01-01

279

A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection  

Microsoft Academic Search

This paper presents a unified formal framework for integrated circuits (ICs) Trojan detection that can simultaneously employ multiple noninvasive side-channel measurement types (modalities). After formally defining the IC Trojan detection for each side-channel measurement and analyzing the complexity, we devise a new submodular formulation of the problem objective function. Based on the objective function properties, an efficient Trojan detection method

Farinaz Koushanfar; Azalia Mirhoseini

2011-01-01

280

Analog Integrated Circuits Design for Processing Physiological Signals  

Microsoft Academic Search

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this

Yan Li; Carmen C. Y. Poon; Yuan-Ting Zhang

2010-01-01

281

Technology and application trends of photonic integrated circuits  

Microsoft Academic Search

Research on photonic integrated circuits initially focused on the technical challenges of combining a variety of distinct optical waveguide elements with a minimum of fabrication and epitaxial complexity. The vehicles used to chronicle the progress in this technology have often preceded any real market opportunity, instead hoping to stimulate the development of applications that would rely on dramatic cost-savings that

T. L. Koch

1996-01-01

282

Testing methods for integrated circuit of phase locked loops  

Microsoft Academic Search

The conventional integrated circuit phase locked loop (PLL) has few output signals and offers limited testability. In an event where PLL function does not conform to the specifications, it is often hard and time consuming to debug the problems due to limited accessibility of the internal signals. In this paper we propose a testing structure which uses the existing PLL

Kai D. Feng; Anjali R. Malladi

2007-01-01

283

Total quality manufacturing at the RIT integrated circuit factory  

Microsoft Academic Search

RIT has received a five year grant from IBM through an IBM Total Quality Management (TQM) Competition. Among the several projects funded by this grant is a project entitled “Six Sigma Process Capability in Student-Run Integrated Circuit Factory”. The process capability baseline has been obtained from data collected for the past several years of student-run factory operation. A methodology to

L. F. Fuller; K. D. Hirschman; P. C. Waldrop

1995-01-01

284

Integrated circuit with dissipative layer for photogenerated carriers  

DOEpatents

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Myers, D.R.

1989-09-12

285

Is there a minimum linewidth in integrated circuits?  

Microsoft Academic Search

Reduction of linewidth is one of the most important problems in integrated circuit technology. The progress made is reviewed and the question whether there exists a minimum linewidth set by physical effects is discussed. It is suggested that two fundamental criteria exist which set such a limit. First, a minimum spot size, 2–3 rim, of the fabricating beam is determined

J. Torkel Wollmark

286

Is there a minimum linewidth in integrated circuits?  

Microsoft Academic Search

Reduction of linewidth is one of the most important problems in integrated circuit technology. The progress made is reviewed and the question whether there exists a minimum linewidth set by physical effects is discussed. It is suggested that two fundamental criteria exist which set such a limit. First, a minimum spot size, 2-3 rim, of the fabricating beam is determined

J. Torkel Wollmark

1980-01-01

287

Equivalent circuit analysis of an RF integrated ferromagnetic inductor  

Microsoft Academic Search

An RF integrated air-core inductor and a ferromagnetic thin-film inductor having a ferromagnetic film on top of the spiral have been microfabricated. An equivalent circuit of the RF integrated spiral inductor with ferromagnetic film has been derived to analyze the contribution of the permeability of the magnetic film to the inductance of the inductor. The scattering parameters (S-parameters) have been

Takashi Kuribara; Masahiro Yamaguchi; Ken-Ichi Arai

2002-01-01

288

Tantalum oxide capacitors for GaAs monolithic integrated circuits  

Microsoft Academic Search

The performance of a high-yield tantalum oxide capacitor for use in GaAs monolithic microwave integrated circuits is described. The integral metal-insulator-metal sandwich structure is reactively sputter-deposited at low temperatures, compatible with a photoresist lift-off process, on semi-insulating GaAs substrate. Dielectric constants of 20-25 were achieved in the capacitors fabricated. An initial application of this process as an interstage coupling capacitor

M. E. Elta; A. Chu; L. J. Mahoney; R. T. Cerretani; W. E. Courtney

1982-01-01

289

Design and simulation tools for integrated optic circuits  

NASA Astrophysics Data System (ADS)

In this paper we will present the recent trends in the development of design and simulation tools for integrated optical circuits. We will address the relevant design steps, required to finish a typical design cycle, such as technology simulations, optical simulations, and mask layout, as well as the vertical integration of these steps. A specific example is given with respect to the design process for a thermo-optical switch.

van der Vliet, Marcel F.; Beelen, Gunter

1999-03-01

290

Production Engineering Measure for Hybrid Integrated Circuits for Fuze Applications. Volume 2. Precision Oscillator Integrated Circuit.  

National Technical Information Service (NTIS)

Breadboard circuit construction showed a need for certain changes to the specifications in regard to component selection. Initial construction of the devices was accomplished with two thin film bonded substrates. This was later changed to a single substra...

T. Sciacca H. Brandt

1974-01-01

291

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions  

NASA Astrophysics Data System (ADS)

A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.

Suzuki, D.; Natsui, M.; Endoh, T.; Ohno, H.; Hanyu, T.

2012-04-01

292

Imaging material components of an integrated circuit interconnect  

NASA Astrophysics Data System (ADS)

Two regions of interest on a copper/tungsten integrated circuit interconnect were imaged using two techniques: (a) the absorption spectrum was measured at 15 x-ray energies between 1687 and 1897 eV, and (b) the x-ray fluorescence spectrum was recorded with incident photon energies of 1822, 1797, and 1722 eV. The energies were chosen to optionally excite tungsten and tantalum above their M5 edges yet stay below the silicon K edge. Four materials in the circuits, tantalum, tungsten, silica, and copper were mapped using both techniques. The two sets of images agree in their main features, but differ for finer features.

Levine, Zachary H.; Grantham, Steven; Paterson, David J.; McNulty, Ian; Noyan, I. C.; Levin, T. M.

2004-01-01

293

Competitive Learning in Asynchronous-Pulse-Density Integrated Circuits  

Microsoft Academic Search

\\u000a This paper introduces MOS circuits for the integrated implementation of competitive learning. A single-layer competitive network\\u000a architecture composed of asynchronous-pulse-coded processing elements is employed. The processing elements perform analog\\u000a computations and communicate via asynchronous-pulse-density-modulated signals which encode continuous-time signal information\\u000a using discrete binary values. The specific focus is upon the design and simulation of an adaptive synapse circuit which combines

David A. Watola; Jack L. Meador

294

InGaAs/InP heterojunction bipolar transistors for ultra-low power circuit applications  

SciTech Connect

For many modern day portable electronic applications, low power high speed devices have become very desirable. Very high values of f{sub T} and f{sub MAX} have been reported with InGaAs/InP heterojunction bipolar transistors (HBTs), but only under high bias and high current level operating conditions. An InGaAs/InP ultra-lowpower HBT with f{sub MAX} greater than 10 GHz operating at less than 20 {micro}A has been reported for the first time in this work. The results are obtained on a 2.5 x 5 {micro}m{sup 2} device, corresponding to less than 150 A/cm{sup 2} of current density. These are the lowest current levels at which f{sub MAX} {ge} 10 GHz has been reported.

Chang, P.C.; Baca, A.G.; Hafich, M.J.; Ashby, C.I.

1998-08-01

295

Next-generation silicon analysis tools for RF integrated-circuits  

Microsoft Academic Search

This paper introduces new circuit analysis technology targeted to address the growing gap between what current circuit verification technology can deliver for today's analog and RF integrated circuit designs, compared to what is observed and measured in silicon. We present key powerful new techniques for the precise and fast analysis and verification of RF integrated circuits. We also provide an

Amit Mehrotra; Amit Narayan; Ravi Subramanian

2006-01-01

296

New Developments in Integrated Circuits for Television and Other Consumer Systems  

Microsoft Academic Search

When T.V. setmakers first started using integrated circuits in 1970 their approach was naturally cautious. One or two circuits were tried initially in small signal low voltage areas of the receiver in order to gain confidence. This start was made with the sound i.f. and signal processing (jungle) circuits. The reliability of integrated circuits as far as the setmaker was

B. E. Buckingham

1975-01-01

297

Developments in Transistor Electronics†  

Microsoft Academic Search

The design theory of point-contact and junction transistors is reviewed in this paper. Selected examples illustrate the small-signal and large-signal properties of junction transistors. These phenomena are related to the theory of p— n junctions. Also, it is indicated how circuit engineers benefit from a certain know-ledge of transistor theory.

L. B. Valdes

1958-01-01

298

Integrated design for integrated photonics: from the physical to the circuit level and back  

NASA Astrophysics Data System (ADS)

Silicon photonics is maturing rapidly on a technology basis, but design challenges are still prevalent. We discuss these challenges and explain how design of photonic integrated circuits needs to be handled on both the circuit as on the physical level. We also present a number of tools based on the IPKISS design framework.

Bogaerts, Wim; Li, Yanlu; Pathak, Shibnath; Ruocco, Alfonso; Fiers, Martin; Ribeiro, Antonio; Lambert, Emmanuel; Dumon, Pieter

2013-05-01

299

Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators  

Microsoft Academic Search

A large-area, flexible, and lightweight sheet-type Braille display has been successfully fabricated on a plastic film by integrating high-quality organic transistors and soft actuators. An array of rectangular plastic actuators is mechanically processed from a perfluorinated polymer electrolyte membrane. A small semisphere, which projects upward from the rubberlike surface of the display, is attached to the tip of each rectangular

Yusaku Kato; Tsuyoshi Sekitani; Makoto Takamiya; Masao Doi; Kinji Asaka; Takayasu Sakurai; Takao Someya

2007-01-01

300

Attachment method for stacked integrated circuit (IC) chips  

DOEpatents

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Bernhardt, Anthony F. (Berkeley, CA); Malba, Vincent (Livermore, CA)

1999-01-01

301

Integration of a receiver front-end in multilayer ceramic integrated circuit (MCIC) technology  

Microsoft Academic Search

In the commercial wireless industry significant progress has been made in the integration and size reduction of frequency processing functions in semiconductor products, but the integration of frequency selective devices that require many passive components has lagged. Efforts are underway to integrate passive components into organic printed circuit boards but frequency selective devices, such as VCOs and filters, require higher

John Estes; R. Kommrusch; Rong Fong Huang

1997-01-01

302

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...  

Federal Register 2010, 2011, 2012, 2013

...COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same...sale within the United States after importation of certain semiconductor integrated circuit devices and products containing...

2012-10-04

303

75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...  

Federal Register 2010, 2011, 2012, 2013

...Investigation No. 337-TA-648] Certain Semiconductor Integration Circuits Using Tungsten...States after importation of certain semiconductor integrated circuits using tungsten...remained in the investigation: Tower Semiconductor, Ltd. of Israel; Jazz...

2010-12-06

304

77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...  

Federal Register 2010, 2011, 2012, 2013

...Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products Containing Same; Commission Determination...integrated circuit packages provided with multiple heat-conducting paths and products containing same by reason of...

2012-12-12

305

High Performance RF Integrated Circuits using the Silicon Based RE Integrated Passive Device (RFIPD)  

Microsoft Academic Search

In this paper, we introduce the high performance RF circuits using the RF integrated passive device (RFIPD). RFIPD is made by a low-cost manufacturing technology and a high-performance process technology of electro-chemically forming thick oxide layer on silicon wafer and processing Cu thick metal and BCB. Several RF integrated passive circuits and RF module such as LPF, BPF, balun and

Choong-Mo Nam; In-Ho Jung

2005-01-01

306

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits  

Microsoft Academic Search

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power

P. Pant; R. K. Roy; A. Chattejee

2001-01-01

307

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations  

PubMed Central

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ?1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ?140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

2008-01-01

308

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.  

PubMed

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-11-17

309

Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof  

US Patent & Trademark Office Database

A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

Risch; Lothar (Neubiberg, DE); Vogelsang; Thomas (Munich, DE); Hofmann; Franz (Munich, DE); Hofmann; Karl (Wennigsen, DE)

1996-09-24

310

Indium Phosphide-Based Heterojunction Bipolar Transistor Technology for High-Speed Devices and Circuits.  

NASA Astrophysics Data System (ADS)

The theoretical predictions for the performance of Heterojunction Bipolar Transistors (HBTs) have been largely based on models devised for silicon bipolar junction transistors (BJT). A careful inspection of the DC forward and reverse injection properties of HBTs has revealed that they are not reciprocal because of the heterojunction. The RF characteristics derived from an advanced network model indicated that f_{t} and f_{max} must be redefined since h_{21} and U can no longer be considered single pole functions. A variety of InP-based HBTs have been fabricated and characterized. The layer structures were grown by conventional molecular beam epitaxy (MBE) and by chemical beam epitaxy (CBE). A totally self-aligned base and emitter metal process was developed to characterize their DC and RF performances. The CBE grown structures included InAlAs/InGaAs and InP/InGaAs single HBTs and InAlAs/InGaAs/InGaAsP double HBTs. The various structures showed comparable current gains (beta~ 100) but the different injecting and collecting junctions resulted in variations in turn-on voltages, ideality factors and offset voltages. Because of the large bandgap InGaAsP collector in the double HBT, its breakdown voltage (8V) is significantly larger than that of the single HBTs (2.5V). The microwave performance of all these HBTs is dominated by parasitics. The low doping efficiency of the CBE significantly increases the base resistance and the emitter access resistance. The MBE grown HBT was a conventional InAlAs/InGaAs HBT with very heavily doped contact layers. The DC measurements showed lower current gain (beta~ 60) due to high base doping but demonstrated excellent Gummel and breakdown characteristics. Microwave measurements yielded an f_{t} and f_{max} of 65 and 78 GHz, respectively. Cryogenic DC measurements were performed to study the injection and recombination mechanisms at the base -emitter junction. At low temperatures, tunneling injection and bulk base recombination dominate while at room temperature themionic emission and other recombination processes are activated. Microwave measurements at various temperature revealed that both f_{t} and f_{max} improve as the temperature is lowered. The measured RF parameters of the MBE InAlAs/InGaAs HBT were used to design oscillators, amplifiers and photoreceivers. The oscillators operated at 7 and 14 GHz with output powers of 4 and 2 mW. The transimpedance amplifiers demonstrated a bandwidth of 17 GHz with a transimpedance of 40 dB Omega. The photoreceivers showed an optical bandwidth of 7 GHz and clearly open eye diagrams at 3 Gbits/s.

Cowles, John Charles, Jr.

311

A low noise preamplifier using a tetrode field effect transistor in a novel feedback arrangement  

Microsoft Academic Search

This paper describes a low noise n-channel tetrode field effect transistor circuit in which the d.c. input and output voltages of a current integrator are held close to zero. This is achieved by a feedback network to the substrate gate of the tetrode FET. An analysis is made of the circuit arrangement. The application for the circuit configuration is for

J. H. Howes; M. D. Deighton; A. J. Smith

1984-01-01

312

Si\\/SiGe HBT technology for low-cost monolithic microwave integrated circuits  

Microsoft Academic Search

This silicon-based microwave integrated-circuit technology is suitable for implementation of high-performance low-cost active circuits from 5-25 GHz. This technology promises to dramatically reduce the cost of microwave integrated circuit technology by utilizing manufacturable, high-yield, silicon IC processing, and at the same time enable more highly integrated implementations of microwave transceiver components. A variety of microwave integrated circuits implemented in this

Lawrence Larson; Michael Case; Steven Rosenbaum; David Rensch; Perry MacDonald; Mehran Matloubian; Mary Chen; David Harame; John Malinowski; Bernard Meyerson; Monica Gilbert; Stephen Maas

1996-01-01

313

Broadband opto-mechanical phase shifter for photonic integrated circuits  

NASA Astrophysics Data System (ADS)

A broadband opto-mechanical phase shifter for photonic integrated circuits is proposed and numerically investigated. The structure consists of a mode-carrying waveguide and a deformable non-mode-carrying nanostring, which are parallel with each other. Since the nanostring can be deflected by the optical gradient force between the waveguide and the nanostring, the effective refractive indices of the waveguide will be changed and a phase shift will be generated. The phase shift under different geometry sizes, launched powers and boundary conditions are calculated and the dynamical properties as well as the thermal noise's effect are also discussed. It is demonstrated that a ? phase shift can be realized with only about 0.64 mW launched power and 50 ?m long nanostring. The proposed phase shifter may find potential usage in future investigation of photonic integrated circuits.

Guo, Xiang; Zou, Chang-Ling; Ren, Xi-Feng; Sun, Fang-Wen; Guo, Guang-Can

2012-08-01

314

Test diagnostics of RF effects in integrated circuits  

NASA Astrophysics Data System (ADS)

The results are presented for an effort to measure the RF upset susceptibilities of CMOS and low power Schottky integrated circuits and to demonstrate a test probe methodology for measuring RF noise coupling, generation, and propagation into and upon these integrated circuits chips. RF interference used was continuous wave CW from 1MHz to 200MHz. This was combined with the digital signal using an op-amp combiner and directly coupled into the device ports. Upset threshold voltage levels were measured, complex input impedances were measured, and upset power levels were calculated and plotted. A scanning electron microscope (SEM), quantitative voltage contrast (QVC) system was used to measure internal waveforms along the intended signal path, on adjacent metals runs, and an internal power and ground connections.

Wilson, David D.; Epshtein, Stan; Rossi, Mark G.; Proffitt, Christine L.

1990-02-01

315

TRANSISTORIZED RADIATION MONITORS  

Microsoft Academic Search

Paper presented at I.R.E. Professional Group on Nuclear Science ; Meeting, New York, Oct. 3l, l957. The advantages of transistors over vacuum ; tubes in radiation instruments have long been realized but a somewhat different ; approach to circuit design must be followed in developing transistor instruments, ; as compared with that used in vacuum tube circuits, and this seems

Goulding

1957-01-01

316

PETRIC. A positron emission tomography readout integrated circuit  

Microsoft Academic Search

We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel

M. Pedrali-Noyt; Gregory Gruber; Bradley Krieger; Emmanuele Mandelli; Gerrit Meddeler; William Moses; Valeria Rosso

2000-01-01

317

PETRIC-a positron emission tomography readout integrated circuit  

Microsoft Academic Search

We present the architecture, critical design issues, and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit for reading out a photodiode array coupled with Lu 2SiO5[Ce] scintillator crystals for a medical imaging application: positron emission topography. Each channel consists of a low-noise charge-sensitive preamplifier, an RC-CR pulse shaper and a winner-take-all multiplexer that selects the channel with

M. Pedrali-Noy; G. Gruber; B. Krieger; E. Mandelli; G. Meddeler; W. Moses; V. Rosso

2001-01-01

318

A CMOS integrated timing discriminator circuit for fast scintillation counters  

Microsoft Academic Search

Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (tr⩾2 ns) scintillation counters at the cooler synchrotron COSY-Julich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide

Michael W. Jochmann

1997-01-01

319

Mixed Signal Custom Integrated Circuit Development for Physics Instrumentation  

Microsoft Academic Search

Further author information- C. L. B. for the collaboration (correspondence) Email: brittoncl@ornl.gov, Telephone: 423 574-1878; Fax: 423-576-2813. The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the

C. L. Britton; W. L. Bryan; M. S. Emery; S. S. Frank; M. N. Ericson; U. Jagadish; J. A. Moore; M. L. Simpson; M. C. Smith; A. L. Wintenberg; G. R. Young; R. A. Kroeger; W. N. Johnson; J. D. Kurfess; W. G. Schwarz

320

A CMOS integrated timing discriminator circuit for fast scintillation counters  

Microsoft Academic Search

Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (tr⩾2 ns) scintillation counters at the cooler synchrotron COSY-Julich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide

M. W. Jochmann

1998-01-01

321

Automation of pre-cap visual inspection for integrated circuits  

NASA Astrophysics Data System (ADS)

The feasibility of an automatic inspection system which can perform a 100% internal visual inspection of integrated circuits (ICs) during production was investigated. Columbia Research Corporation (CRC) reviewed technical approaches and the feasibility of applying them to production. They also surveyed the companies currently developing automated IC inspection systems and found that no commercial contractor has installed equipment for routine inspection on a production basis. This project was terminated because the necessary equipment is still undergoing design and evaluation.

Flake, D.; Fisher, G.; Watson, P.; Niemiec, G.

1982-12-01

322

Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits  

Microsoft Academic Search

\\u000a A tool to model interconnect parasitics in radio-frequency (RF) integrated circuits (RFICs) is presented. Accurate modeling\\u000a is achieved by combining a detailed RLC wire model together with a distributed RC substrate model. Wire geometry is fractured\\u000a to ensure accurate modeling of wave propagation as well as displacement current due to substrate losses. The wire model includes\\u000a resistance and coupled capacitance

Jérôme Lescot; François J. R. Clément

2003-01-01

323

Aperture efficiency of integrated-circuit horn antennas  

Microsoft Academic Search

The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent

Yong Guo; Karen Lee; Philip Stimson; Kent Potter; David Rutledge

1991-01-01

324

Advanced polymer systems for optoelectronic integrated circuit applications  

Microsoft Academic Search

An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness,

Louay A. Eldada; Kelly M. Stengel; Lawrence W. Shacklette; Robert A. Norwood; Chengzeng Xu; Chengjiu Wu; James T. Yardley

1997-01-01

325

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer  

Microsoft Academic Search

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full

Michael John Sebastian Smith

1985-01-01

326

A Smart Sensor Integrated Circuit for NASA's New Millennium Spacecraft  

Microsoft Academic Search

The modern space era can greatly benefit from the rapidly growingmicroelectronics technologies in order to enable the ambitious exploratoryand commercial space endeavors of the new millennium. A smart sensor, analog\\/digital, integrated circuit, suitable for spacecraft avionics dataacquisition and control is presented. The Remote Input\\/Output (RIO) device isdeveloped by The Johns Hopkins University\\/Applied Physics Laboratory, for NASA's Jet Propulsion Laboratory, to

Nikolaos P. Paschalidis

2001-01-01

327

A smart sensor integrated circuit for NASA's new millennium spacecraft  

Microsoft Academic Search

The modern space era can greatly benefit from the rapidly growing microelectronics technologies in order to enable the ambitious exploratory and commercial space endeavors of the new millennium. A smart sensor, analog\\/digital, integrated circuit, suitable for spacecraft avionics data acquisition and control is presented. The Remote Input\\/Output (RIO) device is developed by The Johns Hopkins University\\/Applied Physics Laboratory, for NASA's

Nikolaos P. Paschalidis

1999-01-01

328

Mechanical Computing Redux: Relays for Integrated Circuit Applications  

Microsoft Academic Search

Power density has grown to be the dominant challenge for continued complementary metal-oxide-semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applications. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical

Vincent Pott; Hei Kam; Rhesa Nathanael; Jaeseok Jeon; Elad Alon; Tsu-Jae King Liu

2010-01-01

329

Observation and Circuit Application of Negative Differential Conductance in Silicon Single-Electron Transistors  

NASA Astrophysics Data System (ADS)

A conductance anomaly displaying large negative differential conductance (NDC) has been observed in a drain current vs. drain voltage curve of Si single-electron transistors (SETs) at 27 K. The NDC appears, mainly in the single-electron-tunneling regime, in such a way that it aligns parallel to the edges of Coulomb diamonds, strongly suggesting that it reflects the discrete nature of the dot states. We show that high-gain SETs, i.e., SETs with gate capacitance that is well larger than the junction capacitances, enable us to regulate the appearance of NDC and to accentuate the tunneling conditions only at the drain side because of the asymmetric sharing of the source-drain voltage between the two junctions. We also show, using high-gain SETs, that the NDC results in a hysteresis loop of drain output voltage as a function of gate voltage for a constant drain-current bias. This enables us to use the SET as a Schmitt-trigger with excellent noise immunity.

Ono, Yukinori; Takahashi, Yasuo

2002-04-01

330

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...  

Federal Register 2010, 2011, 2012, 2013

...Semiconductor Integrated Circuits and Products Containing...Determination To Review in Part a Final Initial Determination...determined to review in part the final initial...semiconductor integrated circuits and products containing...accused LSI integrated circuits. The ALJ conducted...review the final ID in part....

2010-02-04

331

A CMOS integrated circuit for pulse-shaped discrimination  

SciTech Connect

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the zero crossing of the shaped signal. The circuit is designed to interface with two photomultiplier tubes -- one for pulse processing and one for coincidence detection. Two Outputs from the IC, a start and stop, can be used with a high speed timing system for pulse characterization with minimal external control. The circuit was fabricated in Orbit 1.2{mu}m CMOS and operates from a 5-V supply. Specifics of the design including overall topology, charge sensitive preamplifier and CFD characteristics, shaping method and time constant selections, system timing, and implementation are discussed. Circuit performance is presented including dynamic range, timing walk, system dead time, and power consumption.

Frank, S.S.; Ericson, M.N.; Simpson, M.L.; Todd, R.A.; Hutchinson, D.P.

1995-06-01

332

High density vertical interconnects for 3-D integration of silicon integrated circuits  

Microsoft Academic Search

This paper describes a technology platform being developed for three-dimensional (3-D) integration of thin stacked silicon integrated circuits (ICs). 3-D integration technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator array devices hybridized with silicon read-out electronics. Currently, advanced 3-D integrated infrared focal plane array detectors are being developed within the DARPA vertically

C. A. Bower; D. Malta; D. Temple; J. E. Robinson; P. R. Coffinan; M. R. Skokan; T. B. Welch

2006-01-01

333

Long-term stability of Gallium Nitride High Electron Mobility Transistors: a reliability physics approach  

Microsoft Academic Search

Several groups have demonstrated nitride-based High Electron Mobility Transistors with excellent rf output power, with a constant increase in performances. However, despite the large efforts spent in the last few years, and the progress in MTTF (Mean Time To Failure) values, reliability of GaN HEMTs (High Electron Mobility Transistors) and MMICs (Millimeter Microwave Integrated Circuits) still has to be fully

E. Zanoni; G. Meneghesso; M. Meneghini; A. Tazzoli; N. Ronchi; A. Stocco; F. Zanon; A. Chini; G. Verzellesi; A. Cetronio; C. Lanzieri; M. Peroni

2009-01-01

334

Integrating anatomy and function for zebrafish circuit analysis.  

PubMed

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

Arrenberg, Aristides B; Driever, Wolfgang

2013-04-23

335

Integrated diode circuits for greater than 1 THz  

NASA Astrophysics Data System (ADS)

The terahertz frequency band, spanning from roughly 100 GHz to 10 THz, forms the transition from electronics to photonics. This band is often referred to as the "terahertz technology gap" because it lacks typical microwave and optical components. The deficit of terahertz devices makes it difficult to conduct important scientific measurements that are exclusive to this band in fields such as radio astronomy and chemical spectroscopy. In addition, a number of scientific, military and commercial applications will become more practical when a suitable terahertz technology is developed. UVa's Applied Electrophysics Laboratory has extended non-linear microwave diode technology into the terahertz region. Initial success was achieved with whisker-contacted diodes and then discrete planar Schottky diodes soldered onto quartz circuits. Work at UVa and the Jet Propulsion Laboratory succeeded in integrating this diode technology onto low dielectric substrates, thereby producing more practical components with greater yield and improved performance. However, the development of circuit integration technologies for greater than 1 THz and the development of broadly tunable sources of terahertz power remain as major research goals. Meeting these critical needs is the primary motivation for this research. To achieve this goal and demonstrate a useful prototype for one of our sponsors, this research project has focused on the development of a Sideband Generator at 1.6 THz. This component allows use of a fixed narrow band source as a tunable power source for terahertz spectroscopy and compact range radar. To prove the new fabrication and circuit technologies, initial devices were fabricated and tested at 200 and 600 GHz. These circuits included non-ohmic cathodes, air-bridged fingers, oxideless anode formation, and improved quartz integration processes. The excellent performance of these components validated these new concepts. The prototype process was then further optimized to produce a substantially increased yield and to maintain excellent performance at 1.6 THz. The successful fabrication of integrated 1.6 THz SBG circuits establishes the viability of the new processes for terahertz applications. Additionally, this new technology can also be applied to other components, such as mixers, multipliers, and direct detectors thereby helping to close the terahertz technology gap.

Schoenthal, Gerhard Siegbert

336

Design of self-checking N-MOS (H-MOS) integrated circuits  

NASA Astrophysics Data System (ADS)

The design of self-checking N metal oxide semiconductor circuits is discussed. Two types of test are planned for the use of these circuits: on-line testing to detect failures during the function run of software; and off-line testing, with an emphasis on detection and localization for maintainability. The design of these circuits is based on transistor level fault hypotheses. The design of a functional part, the design of a checker, and procedures/design rules for a design for maintainability are addressed.

Nicolaidis, M.; Courtois, B.

1984-10-01

337

Monolithically integrated, flexible display of polymer-dispersed liquid crystal driven by rubber-stamped organic thin-film transistors  

SciTech Connect

This letter describes the monolithic integration of rubber-stamped thin-film organic transistors with polymer-dispersed liquid crystals (PDLCs) to create a multipixel, flexible display with plastic substrates. We report the electro-optic switching behavior of the PDLCs as driven by the organic transistors, and we show that our displays operate robustly under flexing and have a contrast comparable to that of newsprint. {copyright} 2001 American Institute of Physics.

Mach, P.; Rodriguez, S. J.; Nortrup, R.; Wiltzius, P.; Rogers, J. A.

2001-06-04

338

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits  

Microsoft Academic Search

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication

Ahmet Bindal; Sotoudeh Hamedi-Hagh

2006-01-01

339

Electrostatic Discharge Protection for RF Integrated Circuits: New ESD Design Challenges  

Microsoft Academic Search

Electrostatic discharge (ESD) protection circuit design for radio-frequency (RF) integrated circuits emerges as a new design challenge. Yet currently, RF ESD protection is still a problem in definition. This paper proposes a new and comprehensive ESD-circuit interaction theory to address the complex mutual influences between the ESD protection networks and the circuits being protected in both directions. Design examples demonstrating

H. G. Feng; R. Y. Zhan; G. Chen; Q. Wu; Albert Z. Wang

2004-01-01

340

Large-scale DWDM photonic integrated circuits: a manufacturable and scalable integration platform  

Microsoft Academic Search

Commercial scaling of electronic integrated circuits has proceeded at a fast pace once the initial hurdle to integration was overcome. Recently, it has been shown that record active and passive optical device counts, exceeding 50 discrete components, can be incorporated onto a single monolithic 100 Gbps DWDM transmitter PIC InP chip. We will investigate key production metrics for this large-scale

C. H. Joyner; J. L. Pleumeekers; A. Mathur; P. W. Evans; D. J. H. Lambert; S. Murthy; S. K. Mathis; F. H. Peters; J. Baeck; M. J. Missey; A. G. Dentai; R. A. Salvatore; R. P. Schneider; M. Ziari; M. Kato; R. Nagarajan; J. S. Bostak; T. Butrie; V. G. Dominic; M. Kauffman; R. H. Miles; M. L. Mitchell; A. C. Nilsson; S. C. Pennypacker; R. Schlenker; R. B. Taylor; Huan-Shang Tsai; M. F. Van Leeuwen; J. Webjorn; D. Perkins; J. Singh; S. G. Grubb; M. Reffle; D. G. Mehuys; F. A. Kish; D. F. Welch

2005-01-01

341

Millimeter wave planar integrated circuit developments for communication applications  

NASA Astrophysics Data System (ADS)

Millimeter wave communication systems offer certain advantages over lower frequency systems. These advantages are related to wider bandwidth, larger data handling capacity, covert operation, and better immunity to jamming. Newer developments in the area of component technology for systems operating at millimeter wavelengths have utilized planar integrated circuits. Such circuits provide benefits of light weight, small size, and inherent low cost due to ease of high volume manufacturing. The present paper is concerned with a number of key IC components which have been developed. These components are ideally suited for direct application in advanced tactical, radar, and satellite communication systems. Attention is given to a rat-race microstrip balanced mixer, a crossbar stripline balanced mixer, and various subsystems developments.

Chang, K.; Sun, C.

342

Thermionic integrated circuit technology for high power space applications  

SciTech Connect

Thermionic triode and integrated circuit technology is in its infancy and it is emerging. The Thermionic triode can operate at relatively high voltages (up to 2000V) and at least tens of amperes. These devices, including their use in integrated circuitry, operate at high temperatures (800/sup 0/C) and are very tolerant to nuclear and other radiations. These properties can be very useful in large space power applications such as that represented by the SP-100 system which uses a nuclear reactor. This paper presents an assessment of the application of thermionic integrated circuitry with space nuclear power system technology. A comparison is made with conventional semiconductor circuitry considering a dissipative shunt regulator for SP-100 type nuclear power system rated at 100 kW. The particular advantages of thermionic circuitry are significant reductions in size and mass of heat dissipation and radiation shield subsystems.

Yadavalli, S.R.

1984-08-01

343

Equivalent circuit modeling of losses and dispersion in single and coupled lines for microwave and millimeter-wave integrated circuits  

Microsoft Academic Search

Losses and dispersion in open inhomogeneous guided-wave structures such as microstrips and other planar structures at microwave and millimeter-wave frequencies and in MMICs (monolithic microwave integrated circuits) have been modeled with circuits consisting of ideal lumped elements and lossless TEM (transverse electromagnetic) lines. It is shown that, given a propagation structure for which numerical techniques to compute the propagation characteristics

Vijai K. Tripathi; Achim Hill

1988-01-01

344

On teaching circuit reliability  

Microsoft Academic Search

Integrated circuits in the coming years are expected to be based on nano-scaled devices, such as single electron transistors, self-assembled DNA, carbon nano-tubes, and resonant tunnel diodes. Future designs based on such nano-devices will exhibit high integration densities, and might be either low power or fast switching but not both. Unfortunately, nano-devices suffer heavily from fabrication inconsistencies, and transient and

Azam Beg; Walid Ibrahim

2008-01-01

345

Extraction of the InP/InGaAs metallic collector-up heterojunction bipolar transistor small-signal equivalent circuit  

NASA Astrophysics Data System (ADS)

An efficient technique for determining the small-signal equivalent-circuit model of a Metal collector-up Heterojunction Bipolar Transistor (C-up MHBT) is presented. The technique employs analytically derived expressions for direct calculation of HBT T-Model equivalent circuit element values in terms of the measured S-parameters. This approach avoids errors due to uncertainty in fitting to large, over determined equivalent circuits and does not require the use of test structures and extra measurement steps to evaluate parasitics. Physically realistic results are demonstrated under various biasing conditions for the n-p-n InP/InGaAs HBT with metallic collector up structure. The agreement between the measured and model-produced data is excellent over the large frequency range and for several polarizations conditions for devices.

Bourguiga, R.; Oudir, A.; Mahdouani, M.; Pardo, F.; Pelouard, J. L.

2008-06-01

346

A 1 bit binary-decision-diagram adder circuit using single-electron transistors made by selective-area metalorganic vapor-phase epitaxy  

NASA Astrophysics Data System (ADS)

We demonstrate single-electron operation of a 1 bit adder circuit using GaAs single-electron tunneling transistors (SETs). GaAs dot and wire coupled structures for the fabrication of SETs were grown by a selective-area metalorganic vapor-phase epitaxy technique. The logic circuit was realized based on a binary decision diagram architecture using Coulomb blockade (CB) in GaAs dots and switching operations were achieved in a single-electron mode because of the CB effects. Through this architecture, a 1 bit adder circuit was realized with three SETs, two of which were for AND logic and one with two input gates for exclusive OR (XOR). Both AND and XOR operations were demonstrated at 1.9 K, which indicated successful fabrication of the 1 bit adder.

Miyoshi, Yoshihito; Nakajima, Fumito; Motohisa, Junichi; Fukui, Takashi

2005-07-01

347

A Direct Power Injection Model for Immunity Prediction in Integrated Circuits  

Microsoft Academic Search

This paper introduces a complete simulation model of a direct power injection (DPI) setup, used to measure the immunity of integrated circuits to conducted continuous-wave interference. This model encompasses the whole measurement setup itself as well as the integrated circuit under test and its environment (printed circuit board, power supply). Furthermore, power losses are theoretically computed, and the most significant

Ali Alaeldine; Richard Perdriau; Mohamed Ramdani; Jean-Luc Levant; M'hamed Drissi

2008-01-01

348

A Direct Power Injection Model for Immunity Prediction in Integrated Circuits  

Microsoft Academic Search

This paper introduces a complete simulation model of a Direct Power Injection (DPI) setup, used to measure the immunity of integrated circuits to conducted continuous-wave interference. This model encompasses the whole measurement setup itself as well as the integrated circuit under test and its environment (printed circuit board, power supply). Furthermore, power losses are theoretically computed, and the most significant

Ali Alaeldine; Richard Perdriau; Mohamed Ramdani; Jean-Luc Levant

2006-01-01

349

Charge-domain integrated circuits for signal processing  

NASA Astrophysics Data System (ADS)

A new class of integrated circuits called charge-domain devices has been developed for performing enhanced monolithic signal processing. All signal-processing operations are accomplished by splitting, routing, and combining charge packets, thus overcoming many of the limitations of alternative devices such as charge-coupled device (CCD) split-electrode transversal filters and switched capacitor filters. Charge manipulation techniques are described, which allow poles as well as zeroes of a transfer function to be implemented efficiently, leading to infinite impulse response monolithic filters suitable for high-frequency applications. Several test filters, including a narrow-band bandpass filter, have been demonstrated. The 8-pole bandpass filter exhibits a passband width of 1 percent of the clock frequency and over 70-dB stopband attenuation on a chip only 2.0 x 2.7 mm in size. Since only charge-coupled device delay-line-type operations are used, the device clock rate is only limited by the inherent charge transfer inefficiency. Clocking speeds of up to 15 MHz have been demonstrated using surface channel devices. These charge-domain devices are useful in applications ranging from radio IF to radar to video signal processing with a high level of integration achievable on a single charge-domain integrated circuit.

Vogelsong, T. L.; Tiemann, J. J.; Steckl, A. J.

1985-04-01

350

Integrated detectors for embedded optical interconnections on electrical boards, modules, and integrated circuits  

Microsoft Academic Search

Significant opportunities exist for optical interconnections at the board, module, and chip level if compact, low-loss, high-data-rate optical interconnections can be integrated into these electrical interconnection systems. To create such an integrated optoelectronic\\/electronic microsystem, mask-based alignment of the optical interconnection waveguide, optoelectronic active devices, and interface circuits is attractive from a packaging alignment standpoint. This paper describes an integration process

Sang-Yeon Cho; Sang-Woo Seo; Martin A. Brooke; Nan M. Jokerst

2002-01-01

351

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

Cole, E.I. Jr.; Soden, J.M.

1995-07-04

352

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Creighton, J. Randall (Albuquerque, NM); Dominguez, Frank (Albuquerque, NM); Johnson, A. Wayne (Albuquerque, NM); Omstead, Thomas R. (Albuquerque, NM)

1997-01-01

353

Wireless multichannel biopotential recording using an integrated FM telemetry circuit  

Microsoft Academic Search

This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of ?0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-?m double-poly double-metal n-well standard

Pedram Mohseni; Khalil Najafi; Steven J. Eliades; Xiaoqin Wang

2005-01-01

354

Thermal resistance of VCSEL's bonded to integrated circuits  

SciTech Connect

The thermal resistance of vertical-cavity surface-emitting lasers (VCSEL's) flip chip bonded to GaAs substrates and CMOS integrated circuits has been measured. The measurements on GaAs show that if the bonding is done properly, the bonding does not add significantly to the thermal resistance. However, the SiO{sub 2} under the CMOS bonding pad can double the thermal resistance unless measures are taken to improve the thermal conductance of these layers. Finite element simulations indicate that the thermal resistance of bonded VCSEL's increases rapidly as the solder bond size and the aperture size decrease below {approximately}10 {micro}m.

Pu, R.; Wilmsen, C.W.; Geib, K.M.; Choquette, K.D.

1999-12-01

355

Method for deposition of a conductor in integrated circuits  

DOEpatents

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

356

New prototype assembly methods for biosensor integrated circuits.  

PubMed

Two new prototype assembly methods have been evaluated for biosensors that combine an integrated circuit (IC) sensor with a culture chamber. The first method uses a poly-ethylene glycol (PEG) mould to mask the IC sensor during application of a room temperature vulcanising (RTV) silicone elastomer used to insulate the bondpads and bondwires. The second method utilises the 'partial encapsulation' service offered by Quik-Pak, USA. Both methods were shown to provide good electrical insulation and demonstrated biocompatibility with the NG108-15 cell line. These methods are particularly useful for the assembly of low-cost ICs with a small (< 4 mm²) sensor area. PMID:21478042

Graham, Anthony H D; Bowen, Chris R; Surguy, Susan M; Robbins, Jon; Taylor, John

2011-04-07

357

Nanowire-organic thin film transistor integration and scale up towards developing sensor array for biomedical sensing applications  

NASA Astrophysics Data System (ADS)

Exploratory research works have demonstrated the capability of conducting nanowire arrays in enhancing the sensitivity and selectivity of bio-electrodes in sensing applications. With the help of different surface manipulation techniques, a wide range of biomolecules have been successfully immobilized on these nanowires. Flexible organic electronics, thin film transistor (TFT) fabricated on flexible substrate, was a breakthrough that enabled development of logic circuits on flexible substrate. In many health monitoring scenarios, a series of biomarkers, physical properties and vital signals need to be observed. Since the nano-bio-electrodes are capable of measuring all or most of them, it has been aptly suggested that a series of electrode (array) on single substrate shall be an excellent point of care tool. This requires an efficient control system for signal acquisition and telemetry. An array of flexible TFTs has been designed that acts as active matrix for controlled switching of or scanning by the sensor array. This array is a scale up of the flexible organic TFT that has been fabricated and rigorously tested in previous studies. The integration of nanowire electrodes to the organic electronics was approached by growing nanowires on the same substrate as TFTs and fl ip chip packaging, where the nanowires and TFTs are made on separate substrates. As a proof of concept, its application has been explored in various multi-focal biomedical sensing applications, such as neural probes for monitoring neurite growth, dopamine, and neuron activity; myocardial ischemia for spatial monitoring of myocardium.

Kumar, Prashanth S.; Hankins, Phillip T.; Rai, Pratyush; Varadan, Vijay K.

2010-03-01

358

Laser-beam writing system for optical integrated circuits.  

PubMed

A computer-controlled laser-beam writing system has been developed for optical integrated circuits (optical ICs). This system allows us to make waveguide patterns 3-4 microm wide, such as directional couplers, and Yjunction, crossed, and S-shaped waveguides, automatically within an edge roughness of 0.2 microm on a photoresist-coated LiNbO(3) substrate. By combining these waveguide patterns, optical ICs can be delineated over more than 50-mm length. This paper presents the system description and the laser-beam writing characteristics of key waveguide patterns. The integrated-optic fiber laser Doppler velocimeter is also demonstrated as an example of large-area optical ICs. PMID:20523409

Haruna, M; Yoshida, S; Toda, H; Nishihara, H

1987-11-01

359

Mixed signal custom integrated circuit development for physics instrumentation  

SciTech Connect

The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

1998-10-01

360

Influence of Low Dielectric SiOF Film on Metal Oxide Semiconductor Field Effect Transistor Characteristics and Its Impact on Circuit Performance  

NASA Astrophysics Data System (ADS)

A low dielectric fluorine-doped silicon oxide (SiOF) film, which was produced by adding C2F6 to the conventional chemical vapor deposited oxide, was applied to a 0.35 µm complementary metal oxide semiconductor (CMOS) and its influence on metal oxide semiconductor field effect transistor characteristics was analyzed. A shift of the transconductance was observed when the SiOF film was used as an intermediate dielectric and the Si3N4 film as the dielectric on the metal. An improvement in speed of 13% due to the SiOF film was experimentally confirmed under the condition where the transconductance does not show a shift. Using circuit simulations, the necessity for such low dielectric films as the SiOF film, on the scaling trend in the improvement of circuit performance, was clearly shown and was also emphasized from the point of view of power reduction. It was revealed that circuit speed and power consumption of 0.35 µm CMOS were degraded if the SiOF film was not used, because the improvement of the transistor performance did not overcome the increase in interconnect capacitance due to the increase in the adjacent interconnect capacitance component.

Ida, Jiro; Ohtomo, Atsushi; Yoshimaru, Masashi

1998-11-01

361

TUTORIAL: Integrated circuit amplifiers for multi-electrode intracortical recording  

NASA Astrophysics Data System (ADS)

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

Jochum, Thomas; Denison, Timothy; Wolf, Patrick

2009-02-01

362

Fully-integrated LDO voltage regulator for digital circuits  

NASA Astrophysics Data System (ADS)

Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a fully-integrated LDO without any external capacitance is preferred in order to achieve a fast and energy-efficient wake-up. Commonly, an LDO is specified, designed and verified for DC load currents. In contrast, a digital load creates large current spikes. As an LDO designed for low quiescent current is too slow to react on fast current spikes, a minimum on-chip capacitance is required to keep the supply voltage within a certain error window. Different fully-integrated LDO topologies are investigated regarding their suitability to supply low-voltage digital circuits. The any-load stable LDO topology is selected and implemented on a 0.13 ?m test-chip. The LDO is able to provide a maximum load current of 2.5 mA while consuming a quiescent current of 17 ?A.

Lüders, M.; Eversmann, B.; Schmitt-Landsiedel, D.; Brederlow, R.

2011-08-01

363

Development of optical packet and circuit integrated ring network testbed.  

PubMed

We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. PMID:22274025

Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

2011-12-12

364

Tuning the threshold voltage in electrolyte-gated organic field-effect transistors  

PubMed Central

Low-voltage organic field-effect transistors (OFETs) promise for low power consumption logic circuits. To enhance the efficiency of the logic circuits, the control of the threshold voltage of the transistors are based on is crucial. We report the systematic control of the threshold voltage of electrolyte-gated OFETs by using various gate metals. The influence of the work function of the metal is investigated in metal-electrolyte-organic semiconductor diodes and electrolyte-gated OFETs. A good correlation is found between the flat-band potential and the threshold voltage. The possibility to tune the threshold voltage over half the potential range applied and to obtain depletion-like (positive threshold voltage) and enhancement (negative threshold voltage) transistors is of great interest when integrating these transistors in logic circuits. The combination of a depletion-like and enhancement transistor leads to a clear improvement of the noise margins in depleted-load unipolar inverters.

Kergoat, Loig; Herlogsson, Lars; Piro, Benoit; Pham, Minh Chau; Horowitz, Gilles; Crispin, Xavier; Berggren, Magnus

2012-01-01

365

Micropower Integrated Circuits Study Program Extension to Scope of Work.  

National Technical Information Service (NTIS)

The Extension to Scope of Work provides further study of items not investigated completely by the original basic contract. These are the items dealing with computerized models of the field effect transistor. The primary computer model is the SCEPTRE progr...

B. O. Jordan D. E. Mullins J. L. Farley P. Pringle

1971-01-01

366

Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida  

NASA Astrophysics Data System (ADS)

A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

1984-07-01

367

Manufacturing issues for 3D integrated active circuits into organic laminate substrates  

Microsoft Academic Search

The three dimensional integration of active circuits, thinned or in standard thickness, into polymeric substrates challenges current substrate manufacturing processes in an unprecedented way. In order to overcome the risks associated with this 3D integration technology, the issues must be carefully studied and assessed. For the direct integration of ultrathin chips into dielectric build up layers of multi-layer printed circuit

Erik Jung; Dirk Wojakowski; Alexander Neumann; Andreas Ostmann; Rolf Aschenbrenner; Herbert Reichl

2003-01-01

368

ROBUST GENERALIZED PEEC METHODOLOGY FOR FULL-WAVE ANALYSIS OF INTEGRATED CIRCUITS  

Microsoft Academic Search

A numerically stable extension of the Partial Element Equivalent Circuit interpretation of the electric field integral equation for the modeling of arbitrarily shaped interconnections and integrated passives in high-speed\\/high- frequency integrated circuits is presented in this paper. The proposed methodology utilizes triangular cells for the discretization of conductor surfaces and triangular prisms for the modeling of finite dielectrics. Its numerical

Aosheng Rong; Andreas C. Cangellaris

369

Integration of a 4Stage 4 K Pulse Tube Cryocooler Prototype With a Superconducting Integrated Circuit  

Microsoft Academic Search

A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power,

Vladimir V. Dotsenko; Jean Delmas; Robert J. Webber; Timur V. Filippov; Dmitry E. Kirichenko; Saad Sarwana; Deepnarayan Gupta; Alan M. Kadin; Elie K. Track

2009-01-01

370

A schematic-based design model for microphone and circuit integration  

Microsoft Academic Search

The transistor-level elements for condenser microphone design have been implemented in an IC design environment. Arbitrary diaphragm shapes can be composed and simulated by using our basic elements. The sensitivity and frequency response are obtained by co-simulation with the microphone and the readout circuit using Cadence\\/Spectrereg simulator. The new model is capable of dealing with the multi-field coupling effects including

Jen-Yi Chen; Shu-Sheng Lee; Peter Chang; Chun-Hsun Chu; Tamal Mukherjee; G. K. Fedder

2007-01-01

371

Two-Transistor Active Pixel Sensor Readout Circuits in Amorphous Silicon Technology for High-Resolution Digital Imaging Applications  

Microsoft Academic Search

Active pixel sensor (APS) architectures using two transistors per pixel are reported in this paper for high-resolution low-noise digital imaging applications. The fewer number of on-pixel elements and reduced pixel complexity result in a smaller pixel pitch and increased pixel gain, which makes the two-transistor (2T) APS architectures promising for high-resolution, low-noise, and high-speed digital imaging including emerging medical imaging

Farhad Taghibakhsh; Karim S. Karim

2008-01-01

372

Integrated circuit for processing a low-frequency signal from a seismic detector  

SciTech Connect

Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex 'Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

2011-12-15

373

Planarization techniques for vertically integrated metallic MEMS on silicon foundry circuits  

Microsoft Academic Search

Various micromachining techniques exist to realize integrated microelectromechanical systems (MEMS), which include sensors, signal processing and\\/or driving circuits, and\\/or actuators in one small die. Post-processing techniques performed on foundry-fabricated circuits (e.g., MOSIS) are attractive since such an approach eliminates the need for an in-house integrated circuit fabrication line to produce integrated MEMS. A method based on the combination of metallic

J-B Leey; Joseph Mayo

1997-01-01

374

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer  

DOEpatents

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Lodi, Robert J. (Tewksbury, MA)

1976-01-01

375

The large-scale integration of high-performance silicon nanowire field effect transistors.  

PubMed

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale. PMID:19755723

Li, Qiliang; Zhu, Xiaoxiao; Yang, Yang; Ioannou, Dimitris E; Xiong, Hao D; Kwon, Doo-Won; Suehle, John S; Richter, Curt A

2009-09-16

376

Germanium on silicon to enable integrated photonic circuits  

NASA Astrophysics Data System (ADS)

Electronic circuits alone cannot fully meet future requirements for speed, size, and weight of many sensor systems, such as digital radar technology and as a result, interest in integrated photonic circuits (IPCs) and the hybridization of electronics with photonics is growing. However, many IPC components such as photodetectors are not presently ideal, but germanium has many advantages to enable higher performance designs that can be better incorporated into an IPC. For example, Ge photodetectors offer an enormous responsivity to laser wavelengths near 1.55?m at high frequencies to 40GHz, and they can be easily fabricated as part of a planar silicon processing schedule. At the same time, germanium has enormous potential for enabling 1.55 micron lasers on silicon and for enhancing the performance of silicon modulators. Our new effort has begun by studying the deposition of germanium on silicon and beginning to develop methods for processing these films. In initial experiments comparing several common chemical solutions for selective etching under patterned positive photoresist, it was found that hydrogen peroxide (H2O2) at or below room temperature (20 C) produced the sharpest patterns in the Ge films; H2O2 at a higher temperature (50 C) resulted in the greatest lateral etching.

Hopkins, F. Kenneth; Walsh, Kevin M.; Benken, Alexander; Jones, John; Averett, Kent; Diggs, Darnell E.; Tan, Loon-Seng; Mou, Shin; Grote, James G.

2013-09-01

377

Wireless multichannel biopotential recording using an integrated FM telemetry circuit.  

PubMed

This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB. PMID:16200750

Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

2005-09-01

378

Evaluation of AlGaN/GaN Heterostructure Field-Effect Transistors on Si Substrate in Power Factor Correction Circuit  

NASA Astrophysics Data System (ADS)

A new device of high-power AlGaN/GaN heterostructure field-effect transistors (HFETs) fabricated on a Si substrate is proposed. Its application of the power factor correction (PFC) circuit is presented for the first time. The AlGaN/GaN HFETs fabricated on the Si substrate with a gate width of 152 mm exhibited a breakdown voltage of more than 800 V, an on-resistance of 65 m?, and a maximum drain current of more than 50 A. As for the results of the experiment on the PFC at 200 W and f = 109 kHz, a power conversion efficiency of 95.2% was obtained. This value was about 1% higher than that of the PFC-circuit-using Si devices.

Iwakami, Shinichi; Machida, Osamu; Izawa, Yoshimichi; Baba, Ryohei; Yanagihara, Masataka; Ehara, Toshihiro; Kaneko, Nobuo; Goto, Hirokazu; Iwabuchi, Akio

2007-08-01

379

Room-temperature-operating data processing circuit based on single-electron transfer and detection with metal-oxide-semiconductor field-effect transistor technology  

NASA Astrophysics Data System (ADS)

A single-electron-based circuit, in which electrons are transferred one by one with a turnstile and subsequently detected with a high-charge-sensitivity electrometer, was fabricated on a silicon-on-insulator substrate. The turnstile, which is operated by opening and closing two metal-oxide-semiconductor field-effect transistors alternately, allows single-electron transfer at room temperature owing to electric-field-assisted shrinkage of the single-electron box. It also achieves fast single-electron transfer (less than 10 ns) and extremely long retention (more than 104 s). We have applied these features to a multilevel memory and a time-division weighted sum circuit for a digital-to-analog converter.

Nishiguchi, Katsuhiko; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Takahashi, Yasuo

2006-05-01

380

Unfolding an electronic integrate-and-fire circuit.  

PubMed

Many physical and biological phenomena involve accumulation and discharge processes that can occur on significantly different time scales. Models of these processes have contributed to understand excitability self-sustained oscillations and synchronization in arrays of oscillators. Integrate-and-fire (I+F) models are popular minimal fill-and-flush mathematical models. They are used in neuroscience to study spiking and phase locking in single neuron membranes, large scale neural networks, and in a variety of applications in physics and electrical engineering. We show here how the classical first-order I+F model fits into the theory of nonlinear oscillators of van der Pol type by demonstrating that a particular second-order oscillator having small parameters converges in a singular perturbation limit to the I+F model. In this sense, our study provides a novel unfolding of such models and it identifies a constructible electronic circuit that is closely related to I+F. PMID:20039058

Carrillo, Humberto; Hoppensteadt, Frank

2009-12-29

381

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.  

PubMed

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices. PMID:19722537

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

382

Wireless Neural Recording With Single Low-Power Integrated Circuit  

PubMed Central

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-?m 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

383

Proton isolation for GaAs integrated circuits  

NASA Astrophysics Data System (ADS)

Significant improvement in the electrical isolation of closely spaced GaAs integrated circuit (IC) devices has been achieved with proton implantation. Isolation voltages have been increased by a factor of four in comparison to a selective implant process. In addition, the tendency of negatively biased ohmic contacts to reduce the current flow in neighboring MESFET's (backgating) has been reduced by at least a factor of three. The GaAs IC compatible process includes implantation of protons through the SiO2 field oxide and a three-layered dielectric-Au mask which is definable to 3-micron linewidths and is easily removed. High temperature storage tests have demonstrated that proton isolation, with lifetimes on the order of 100,000 h at 290 C, is not a lifetime limiting component in a GaAs IC process.

Davanzo, D. C.

1982-07-01

384

Universal application-specific integrated circuit for bioelectric data acquisition.  

PubMed

Use of highly integrated application specific circuits (ASICs) in bioelectric data acquisition systems promise important new insights into the origin of a large variety of health problems by providing light-weight, low-power, low-cost medical measurement devices that allow long-term studies. They also promise significant cost reduction in medical care, as patients in principle become mobile and do not have to be hospitalized for observation. We report on the development and successful implementation of a universal ASIC, designed to meet key characteristics of a broad variety of bioelectric signals in terms of their dynamic range, sampling rate and input referred noise; e.g. electrocardiogram (ECG), electroencephalogram (EEG) and, most constringently, evoked potentials (EPs). Our approach for the first time makes cost-effective use of state-of-the-art microelectronics in medical measurement equipment, thus offering to replace discrete, single application devices used at present. PMID:12460729

Fuchs, Bernhard; Vogel, Sven; Schroeder, Dietmar

2002-12-01

385

Apparatus and method for defect testing of integrated circuits  

SciTech Connect

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Cole, E.I. Jr.; Soden, J.M.

2000-02-29

386

Control of CVD precursor purity for integrated circuit manufacture  

NASA Astrophysics Data System (ADS)

Chemical vapor deposition, CVD, has assumed an increasing share of the processes utilized in the manufacture of submicron integrated circuits. In addition to the conventional CVD materials such as silicon oxide, nitride and polysilicon, an array of new materials for both dielectric and conductive material applications are in development. For films like BPSG or tungsten, convenient volatile precursor sources exist, however, in other cases temperature sensitive, lower volatility liquids and solids are utilized. The quality and consistency of these molecular precursors can have a marked impact on the film forming process. The application of SPC methodology to precursor manufacture provides an effective metric for controlling both the quality and the consistency of the precursors.

Roberts, David A.; Graf, Hans J.; Halberstadt, Michael J.

1995-09-01

387

Design and testing of integrated circuits for reactor protection channels  

SciTech Connect

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built.

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K. [Oak Ridge National Lab., TN (United States); Naser, J. [Electric Power Research Inst., Palo Alto, CA (United States)

1995-06-01

388

Design and testing of integrated circuits for reactor protection channels  

SciTech Connect

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K. [Oak Ridge National Lab., TN (United States); Naser, J. [Electric Power Research Inst., Palo Alto, CA (United States); Rana, I. [Southern Company Services, Birmingham, AL (United States)

1995-06-01

389

Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays  

Microsoft Academic Search

This paper presents a novel CMOS charge transfer readout circuit for X-ray time delay and integration (TDI) arrays with a depth of 64. The proposed circuit uses a charge transfer readout similar to CCD; thus, the summing of the signal charges can be implemented easily compared with other typical CMOS readout circuits for TDI arrays. The weakness of TDI arrays

Chul Bum Kim; Byung-Hyuk Kim; Yong Soo Lee; Han Jung; Hee Chul Lee

2006-01-01

390

Planar resonant multi-output transformer for printed circuit board integration  

Microsoft Academic Search

A converter with printed circuit board integrated transformer to supply 16 similar isolated loads is designed and manufactured. The transformer of the power converter is constructed as planar device consisting of printed circuit board spiral windings and ferrite polymer compound plates as magnetic core, which can be laminated to the printed circuit board. The design consists of one large primary

Eberhard Waffenschmidt; Joep Jacobs

2008-01-01

391

CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600°C  

Microsoft Academic Search

CMOS shift registers, buffers, and gray-scale representation circuits for integrated peripheral drive circuits of poly-Si TFT LCDs were fabricated at temperatures below 600°C on a glass substrate. The maximum operation frequency of the CMOS shift register was 1.25 MHz. The total power consumption of the 10 stage CMOS shift registers at a clock frequency of 46.8 kHz and a power

M. Takabatake; J. Ohwada; Y. A. Ono; K. Ono; A. Mimura; N. Konishi

1991-01-01

392

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit.  

PubMed

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal processing is accomplished with a current-to-frequency converter circuit that forms the causal portion of the matched filter for dc luminescence in wide-band white noise. Measurements show that luminescence can be detected from as few as 4 x 10(5) cells/ml. PMID:12192685

Simpson, M L; Sayler, G S; Patterson, G; Nivens, D E; Bolton, E K; Rochelle, J M; Arnott, J C; Applegate, B M; Ripp, S; Guillorn, M A

2001-01-25

393

Volatile general anesthetic sensing with organic field-effect transistors integrating phospholipid membranes.  

PubMed

The detailed action mechanism of volatile general anesthetics is still unknown despite their effect has been clinically exploited for more than a century. Long ago it was also assessed that the potency of an anesthetic molecule well correlates with its lipophilicity and phospholipids were eventually identified as mediators. As yet, the direct effect of volatile anesthetics at physiological relevant concentrations on membranes is still under scrutiny. Organic field-effect transistors (OFETs) integrating a phospholipid (PL) functional bio inter-layer (FBI) are here proposed for the electronic detection of archetypal volatile anesthetic molecules such as diethyl ether and halothane. This technology allows to directly interface a PL layer to an electronic transistor channel, and directly probe subtle changes occurring in the bio-layer. Repeatable responses of PL FBI-OFET to anesthetics are produced in a concentration range that reaches few percent, namely the clinically relevant regime. The PL FBI-OFET is also shown to deliver a comparably weaker response to a non-anesthetic volatile molecule such as acetone. PMID:22921091

Daniela Angione, Maria; Magliulo, Maria; Cotrone, Serafina; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Gobeljic, Danka; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2012-08-10

394

Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology  

Microsoft Academic Search

On-chip electrostatic discharge (ESD) protection circuits are built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with scaled-down CMOS devices are very susceptible to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in nano-scale CMOS technology. The whole-chip ESD protection

Ming-Dou Ker; Hsin-Chin Jiang

2001-01-01

395

A precision CMOS sample-and-hold circuit with low temperature drift for integrated transducers  

Microsoft Academic Search

A new precision CMOS sample-and-hold (S\\/H) circuit for integrated transducers is proposed. The circuit utilizes auto-zero technique for circuit error sampling, parallel bootstrap switch for reducing switch sampling error due to dominant switch charge injection and chopper-stabilized differential difference amplifier for accurate canceling common-mode error components. Not only does the S\\/H circuit exhibit low temperature drift, it eliminates 1\\/f noise

P. K. Chan; J. Cui

2004-01-01

396

Photonic integrated circuits based on novel glass waveguides and devices  

NASA Astrophysics Data System (ADS)

Novel materials, micro-, nano-scale photonic devices, and 'photonic systems on a chip' have become important focuses for global photonics research and development. This interest is driven by the rapidly growing demand for broader bandwidth in optical communication networks, and higher connection density in the interconnection area, as well as a wider range of application areas in, for example, health care, environment monitoring and security. Taken together, chalcogenide, heavy metal fluoride and fluorotellurite glasses offer transmission from ultraviolet to mid-infrared, high optical non-linearity and the ability to include active dopants, offering the potential for developing optical components with a wide range of functionality. Moreover, using single-mode large cross-section glass-based waveguides as an optical integration platform is an elegant solution for the monolithic integration of optical components, in which the glass-based structures act both as waveguides and as an optical bench for integration. We have previously developed a array of techniques for making photonic integrated circuits and devices based on novel glasses. One is fibre-on-glass (FOG), in which the fibres can be doped with different active dopants and pressed onto a glass substrate with a different composition using low-temperature thermal bonding under mechanical compression. Another is hot-embossing, in which a silicon mould is placed on top of a glass sample, and hot-embossing is carried out by applying heat and pressure. In this paper the development of a fabrication technique that combines the FOG and hot-embossing procedures to good advantage is described. Simulation and experimental results are presented.

Zhang, Yaping; Zhang, Deng; Pan, Weijian; Rowe, Helen; Benson, Trevor; Loni, Armando; Sewell, Phillip; Furniss, David; Seddon, Angela B.

2006-04-01

397

Digital integrated circuit design for system-on-glass  

Microsoft Academic Search

In this paper, we have developed a design environment for a stripe-shaped PMELA process and have designed digital circuits such as a serial-to-parallel converter and a PRBS generator as examples of digital VLSI circuits. The designed circuits and standard cells are fabricated in bulk CMOS process and are verified their operations. The whole circuits are fabricated in PMELA 0.5 mum

Keita Ikai; Jinmyoung Kim; Makoto Ikeda; Kunihiro Asada

2008-01-01

398

Intelligent switches of integrated lightwave circuits with core telecommunication functions  

NASA Astrophysics Data System (ADS)

We present a brief overview of a promising switching technology based on Silica on Silicon thermo-optic integrated circuits. This is basically a 2D solid-state optical device capable of non-blocking switching operation. Except of its excellent performance (insertion loss<5dB, switching time<2ms...), the switch enables additional important build-in functionalities. It enables single-to- single channel switching and single-to-multiple channel multicasting/broadcasting. In addition, it has the capability of channel weighting and variable output power control (attenuation), for instance, to equalize signal levels and compensate for unbalanced different optical input powers, or to equalize unbalanced EDFA gain curve. We examine the market segments appropriate for the switch size and technology, followed by a discussion of the basic features of the technology. The discussion is focused on important requirements from the switch and the technology (e.g., insertion loss, power consumption, channel isolation, extinction ratio, switching time, and heat dissipation). The mechanical design is also considered. It must take into account integration of optical fiber, optical planar wafer, analog electronics and digital microprocessor controls, embedded software, and heating power dissipation. The Lynx Photon.8x8 switch is compared to competing technologies, in terms of typical market performance requirements.

Izhaky, Nahum; Duer, Reuven; Berns, Neil; Tal, Eran; Vinikman, Shirly; Schoenwald, Jeffrey S.; Shani, Yosi

2001-05-01

399

Self-aligned coupled nanowire transistor.  

PubMed

The integration of multiple functionalities into individual nanoelectronic components is increasingly explored as a means to step up computational power, or for advanced signal processing. Here, we report the fabrication of a coupled nanowire transistor, a device where two superimposed high-performance nanowire field-effect transistors capable of mutual interaction form a thyristor-like circuit. The structure embeds an internal level of signal processing, showing promise for applications in analogue computation. The device is naturally derived from a single NW via a self-aligned fabrication process. PMID:21815650

Kulmala, Tero S; Colli, Alan; Fasoli, Andrea; Lombardo, Antonio; Haque, Samiul; Ferrari, Andrea C

2011-08-10

400

A complete monolithically-integrated circuit for all-optical generation of millimeter-wave frequencies  

SciTech Connect

An optoelectronic integrated circuit for generating mm-wave frequencies is demonstrated and design issues detailed. A monolithically integrated ring laser, optical amplifier, and photodiode generate electrical signals up to 85.2 GHz.

Vawter, G.A.; Mar, A.; Hietala, V.; Zolper, J.

1997-02-01

401

Cryogenic operation of a SiGe integrated circuit for control time domain SQUID multiplexing  

NASA Astrophysics Data System (ADS)

This paper presents an ultra low noise instrumentation based on cryogenic electronic integrated circuit. We have designed an ASIC (Application Specific Integrated Circuit) in standard BiCMOS SiGe 0.35 ?m AMS technology. The main functions of this circuit, the readout and the control of a 24 to 1 SQUID multiplexer, is presented. We also report the cryogenic operation of each part of this ASIC.

Prêle, D.; Voisin, F.; Bréelle, E.; Piat, M.

402

Cryogenic operation of a SiGe integrated circuit for control time domain SQUID multiplexing  

Microsoft Academic Search

This paper presents an ultra low noise instrumentation based on cryogenic electronic integrated circuit. We have designed an ASIC (Application Specific Integrated Circuit) in standard BiCMOS SiGe 0.35 mum AMS technology. The main functions of this circuit, the readout and the control of a 24 to 1 SQUID multiplexer, is presented. We also report the cryogenic operation of each part

D. Prêle; F. Voisin; E. Bréelle; M. Piat

2009-01-01

403

Equivalent Circuit Analysis of RF-Integrated Inductors with\\/without Ferromagnetic Material  

Microsoft Academic Search

In this paper, the detailed procedure to extract pi-type equivalent circuit parameters of RF-integrated spiral inductors with\\/without ferromagnetic material is presented. RF-integrated spiral inductors have been fabricated and the Tohoku University group (TU) and The Tokyo Institute of Technology group (TIT) separately acquired equivalent circuit parameters of an air-core spiral. The S-parameters were measured to extract the equivalent circuit parameters.

Masahiro Yamaguchi; Yoshisato Yokoyama; Shinji Ikeda; Takashi Kuribara; Kazuya Masu; Ken-Ichi Arai

2003-01-01

404

A NLTL-Based Integrated Circuit for a 70-200 GHz VNA System  

Microsoft Academic Search

We present an integrated circuit, based on nonlinear transmission lines (NLTL), for network analysis within 70-200 GHz. This is the first integrated circuit containing all elements of a S-Parameter test set: A multiplier to generate the RF signal, couplers to separate the incident and reflected waves, and a pair of high speed sampling circuits for down-converting the signals to lower

O. Wohigemuth; B. Agarwal; R. Pullela; D. Mensa; Q. Lee; J. Guthrie; M. J. W. Rodwell; R. Reuter; J. Braunstein; M. Schlechtweg; T. Krems; K. Kohler

1998-01-01

405

A statistical model for determining the minimum size in integrated circuits  

Microsoft Academic Search

A physical-statistical model for determining the minimum linewidth in integrated circuits of any kind is described. The minimum linewidth in integrated circuits is determined on the basis of a physical-statistical model for layout of the circuit pattern. First, the minimum spot size, 2.5 nm, of photon, electron, or ion beams, is determined, based on the Heisenberg uncertainty principle, minimum molecule

J. T. Wallmark

1979-01-01

406

Focused ion beam damage to MOS integrated circuits  

SciTech Connect

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

FLEETWOOD,D.M.; CAMPBELL,ANN N.; HEMBREE,CHARLES E.; TANGYUNYONG,PAIBOON; JESSING,JEFFREY R.; SODEN,JERRY M.

2000-05-10

407

SEMICONDUCTOR INTEGRATED CIRCUITS: Design of a DTCTGAL circuit and its application  

NASA Astrophysics Data System (ADS)

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 ?m CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

Pengjun, Wang; Kunpeng, Li; Fengna, Mei

2009-11-01

408

Selection of test signals and parametric estimation of susceptibility of integrated circuits to electromagnetic conducted disturbances  

Microsoft Academic Search

Some questions related to susceptibility (immunity) of integrated circuits to conducted electromagnetic disturbances are discussed. This includes the selection of test signals, determination of monitoring EMC parameters and proposals of quantitative estimation of integrated circuits susceptibility on the base of measured values of the established parameters and they relative changes under the influence of test signals. Introduction Some measurement methods

Jerzy F. Ko?odziejski

409

SOI-based monolithic integration of SiON and Si planar optical circuits  

Microsoft Academic Search

In recent years there has been a growing interest in using Silicon on Insulator (SOI) as a platform for integrated planar optical circuits, this is mainly due to the high quality yield volume processes demonstrated by the CMOS manufacturing industry and recent MEMS technology progress. In this work we present monolithic integration of Silicon and SiON planar lightwave circuits on

Oded Cohen; Richard Jones; Omri Raday; Alexander Fang; Nahum Izhaky; Doron Rubin; Mario Paniccia

2006-01-01

410

A Model for the Failure of Bipolar Silicon Integrated Circuits Subjected to Electrostatic Discharge  

Microsoft Academic Search

The results are presented of a study into the mechanism by which failure occurs in an integrated circuit when it is subjected to a discharge of static electricity. The current that flows through an integrated circuit during a static discharge is shown to be an exponentially decaying current pulse. The peak value and rate of decay of the pulse can

Thomas S. Speakman

1974-01-01

411

Genetically-engineered whole-cell bioreporters on integrated circuits for environmental monitoring  

Microsoft Academic Search

A bioluminescent bioreporter integrated circuit (BBIC) biosensor for environmental monitoring is presented. The bioluminescent bioreporters are bacteria that can be genetically altered to achieve bioluminescence when in contact with a targeted substance. The bioreporters are placed on a microluminometer. The microluminometer includes integrated photodiodes and signal processing circuits and is realized in a standard CMOS process. The BBIC can detect

Nora D. Bull; Syed K. Islam; Benjamin J. Blalock; S. Ripp; S. Moser; G. S. Sayler

2008-01-01

412

Application independent evaluation of electromagnetic emissions for integrated circuits by the measurement of conducted signals  

Microsoft Academic Search

This paper gives measurement methods to evaluate the electromagnetic emission (EME) of integrated circuits (IC). The effect of disturbances of any ICs depend on design and layout of the application the specific integrated circuit is built in. To evaluate the EME behavior independent from the final application the proposed methods apply conducted signals, the RF-voltage at any pin and the

W. R. Pfaff

1998-01-01

413

Manufacturing semiconductor integrated circuits with built-in hermetic equivalent reliability  

Microsoft Academic Search

A new, thin film process for use in manufacturing high reliability integrated circuits is presented. Known as ChipSealTM inorganic coating technology, the approach produces the smallest realization of a completely packaged integrated circuit. Standard thin film processing and new silicon materials science has been combined to produce a hermetic equivalent, chip level package. This paper reviews the development of the

M. J. Loboda; R. C. Camilletti; L. A. Goodman; L. K. White; H. L. Pinch; C. P. Wu

1996-01-01

414

Modeling and Design Considerations for Substrate Integrated Waveguide Circuits and Components  

Microsoft Academic Search

This paper presents an overview of the recent achievements in the held of substrate integrated waveguides (SIW) technology, with particular emphasis on the modeling strategy and design considerations of millimeter-wave integrated circuits as well as the physical interpretation of the operation principles and loss mechanisms of these structures. The most common numerical methods for modeling both SIW interconnects and circuits

Maurizio Bozzi; Feng Xu; Dominic Deslandes; Ke Wu

2007-01-01

415

Thermal management for high performance integrated circuits with non-uniform chip power considerations  

Microsoft Academic Search

Thermal management for nonuniform chip power integrated circuits is studied. Circuit chip power analysis was used to generate nonuniform chip power and computational fluid dynamics (CFD) techniques are used to calculate the chip temperature. This paper also presents an integrated thermomechanical analysis of a ceramic ball grid array (CBGA) single chip module (SCM) system under chip power loads. A three-dimensional

Tsorng-Dih Yuan; Bor Zen Hong; Howard H. Chen; Li-Kong Wang

2001-01-01

416

High electric stress and insulation challenges in integrated microelectronic circuits  

Microsoft Academic Search

The insulating layer in the transistor has decreased from 100 nm in the early 1970s to only a few nanometers today. This thin insulating layer gives rise to very high electric fields approaching 1000 kV\\/mm for an operating voltage of 1 V. Degradation of the insulation during ageing takes place due to the high field and may eventually lead to

Frøydis Oldervoll

2002-01-01

417

Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors, Non-volatile Memory and Circuits for Transparent Electronics  

Microsoft Academic Search

The ability to make electronic devices, that are transparent to visible and near infrared wavelength, is a relatively new field of research in the development of the next generation of optoelectronic devices. A new class of inorganic thin-film transistor (TFT) channel material based on amorphous oxide semiconductors, that show high carrier mobility and high visual transparency, is being researched actively.

Arun Suresh

2009-01-01

418

An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED  

NASA Astrophysics Data System (ADS)

Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is proposed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the parameters of LTPS TFTs were extracted from the LTPS TFTs made in our lab. The simulation results indicate that the circuit can fulfill the driving function.

Zhao, Li-Qing; Wu, Chun-Ya; Hao, Da-Shou; Yao, Ying; Meng, Zhi-Guo; Xiong, Shao-Zhen

2009-03-01

419

A Compact Circuit Model of Five-Port Transformer Balun for CMOS RF Integrated Circuits  

NASA Astrophysics Data System (ADS)

A compact circuit model for five-port on-chip transformer balun is presented. Compared to the conventional model, the proposed model is simpler without any accuracy degradation and ensures faster convergence time, which in turn enables flexible RF circuit design optimization. The validity of the proposed model is confirmed through extensive EM simulations and measurements.

Chang, Shinil; Shin, Hyunchol

420

A Compact Circuit Model of Five-Port Transformer Balun for CMOS RF Integrated Circuits  

Microsoft Academic Search

A compact circuit model for five-port on-chip transformer balun is presented. Compared to the conventional model, the proposed model is simpler without any accuracy degradation and ensures faster convergence time, which in turn enables flexible RF circuit design optimization. The validity of the proposed model is confirmed through extensive EM simulations and measurements.

Shinil Chang; Hyunchol Shin

2008-01-01

421

A low-power RF integrated circuit for implantable sensors  

Microsoft Academic Search

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable\\u000a of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional\\u000a to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external\\u000a RF power source. The circuit

Mohammad A. Adeeb; Hung Nguyen; Syed K. Islam; Mo Zhang

2006-01-01

422

Unipolar characteristics of Carbon Nanotube Field Effect Transistor  

Microsoft Academic Search

Carbon Nano Tube (CNT) is one of the several cutting edge emerging technologies within Nano technology, that is showing high efficiency and very wide range of applications in many different streams of science and technology. The Carbon Nano Tube Field Effect Transistors (CNTFETs) have been explored and proposed to be the promising candidate for the next generation of integrated circuit

V. Sridevi; T. Jayanthy

2010-01-01

423

Wireless amperometric neurochemical monitoring using an integrated telemetry circuit.  

PubMed

An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order Delta Sigma modulator (Delta Sigma M) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 microm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of approximately 250 fA, approximately 1.5 pA, approximately 4.5 pA, and approximately 17 pA were achieved for input currents in the range of +/-5, +/-37, +/-150, and +/-600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 microM wirelessly over a transmission distance of approximately 0.5 m in flow injection analysis experiments. PMID:18990633

Roham, Masoud; Halpern, Jeffrey M; Martin, Heidi B; Chiel, Hillel J; Mohseni, Pedram

2008-11-01

424

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.  

PubMed

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 ?m(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

425

Comprehensive methodology for integrated circuit in-line defect classification  

NASA Astrophysics Data System (ADS)

The earliest attempts by human inspectors to classify defects found during in-line inspection of integrated circuits were fraught with difficulties in clarifying defect definitions and in training a diverse and changing inspector staff. These deficiencies were exacerbated by the challenges of expanding classification categories as new defects were discovered. Our diversified product mix had accumulated a knowledge base of approximately seventy defect types, posing a formidable learning challenge for even the most knowledgeable inspector. Not surprisingly, the average accuracy of the group in classifying defects was approximately 55 percent, and even the best inspector scored around 70 percent. To address these issues, we developed a comprehensive methodology for classifying defects. This methodology includes both word descriptions of the physical appearance of defects and a hierarchical questionnaire leading to precise defect classification. After adopting this methodology and implementing strong training programs, our team significantly improved its defect review process, ultimately reaching approximately 80 percent classification accuracy. With this degree of accuracy, we were able to implement defect specific statistical process control charts, together with formalized 'decision tree' procedures for correcting defect excursions. These formalisms then became an effective part of the fab's yield improvement program. Today, as technology advances into the realm of automatic defect classification (ADC), the lessons learned from human defect inspection form a strong foundation by establishing a comprehensive set of defect categories uniquely related to causality and supporting defect identification standards that can be used by the entire community of ADC training engineers.

Guldi, Richard L.; Paradis, Douglas E.; Sridhar, Nagarajan; Hightower, Jesse B.

2000-10-01

426

PETRIC - A positron emission tomography readout integrated circuit  

SciTech Connect

We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

2000-11-05

427

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip  

PubMed Central

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 ?m2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

428

Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)  

NASA Astrophysics Data System (ADS)

Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

2000-03-01

429

Reactor protection system design using application specific integrated circuits  

SciTech Connect

Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed.

Battle, R.E.; Bryan, W.L.; Kisner, R.A.; Wilson, T.L. Jr.

1992-01-01

430

Reactor protection system design using application specific integrated circuits  

SciTech Connect

Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed.

Battle, R.E.; Bryan, W.L.; Kisner, R.A.; Wilson, T.L. Jr.

1992-08-01

431

The short circuit analysis of integrated three phase superconducting fault current limiter with two phase superconducting circuits  

Microsoft Academic Search

The integrated three-phase superconducting fault current limiter (SFCL) using two superconducting circuits was conceptually designed and analyzed. The integrated three-phase SFCL system is an upgrade version of inductive single-phase SFCL systems. It uses one magnetic core having three legs, like a three phase transformer. Each leg has a copper winding as a primary winding but, as a secondary winding, only

Seungje Lee; Eung Ro Lee; Chanjoo Lee; Suk-jin Choi; Tae Kuk Ko

2002-01-01

432

High-temperature stable W/GaAs interface and application to metal--semiconductor field-effect transistors and digital circuits  

SciTech Connect

The thermal stability of the physical, chemical, and electrical properties of W thin films sputter deposited on GaAs were investigated. A variety of characterization methods, including thin film stress analysis, Auger analysis, Rutherford backscattering spectrometry (RBS) analysis, and Schottky barrier measurements showed that the W/GaAs interface remains stable after high-temperature furnace annealing at 900 /sup 0/C for 15 min or rapid-lamp annealing at 1000 /sup 0/C for 11 s. Some refractory metal compounds were also investigated, including, WSi, WN/sub x/, and TaSi/sub x/. Pure W films produced the best Schottky diode characteristics. The average Schottky barrier height was 0.70 +- 0.009 V across a 2-in wafer after furnace annealing at 800 /sup 0/C/15 min. Pure W self-aligned gate (SAG) metal-semiconductor field-effect transistors (MESFET) and digital circuits were also fabricated. Transconductances as high as 300 mS/mm (L/sub g/ = 1.0 ..mu..m) were measured for enhancement mode SAG MESFET's. Circuits were fabricated with SAG MESFET enhancement-resistor mode logic using pure W gates, including ring oscillators, with gate delay as low as 25 ps and divide-by-eight circuits that functioned at a frequency >1 GHz.

Josefowicz, J.Y.; Rensch, D.B.

1987-11-01

433

Full Wave Simulation of Integrated Circuits Using Hybrid Numerical Methods  

NASA Astrophysics Data System (ADS)

Transmission lines play an important role in digital electronics, and in microwave and millimeter-wave circuits. Analysis, modeling, and design of transmission lines are critical to the development of the circuitry in the chip, subsystem, and system levels. In the past several decays, at the EM modeling level, the quasi-static approximation has been widely used due to its great simplicity. As the clock rates increase, the inter-connect effects such as signal delay, distortion, dispersion, reflection, and crosstalk, limit the performance of microwave systems. Meanwhile, the quasi-static approach loses its validity for some complex system structures. Since the successful system design of the PCB, MCM, and the chip packaging, rely very much on the computer aided EM level modeling and simulation, many new methods have been developed, such as the full wave approach, to guarantee the successful design. Many difficulties exist in the rigorous EM level analysis. Some of these include the difficulties in describing the behavior of the conductors with finite thickness and finite conductivity, the field singularity, and the arbitrary multilayered multi-transmission lines structures. This dissertation concentrates on the full wave study of the multi-conductor transmission lines with finite conductivity and finite thickness buried in an arbitrary lossy multilayered environment. Two general approaches have been developed. The first one is the integral equation method in which the dyadic Green's function for arbitrary layered media has been correctly formulated and has been tested both analytically and numerically. By applying this method, the double layered high dielectric permitivitty problem and the heavy dielectrical lossy problem in multilayered media in the CMOS circuit design have been solved. The second approach is the edge element method. In this study, the correct functional for the two dimensional propagation problem has been successfully constructed in a rigorous way from the vector wave equation at the first time. Applying this functional, the 2D1over2 propagation structures, including the dielectric loss, conductor loss, finite thickness of the conductors, and anisotropic dielectric material, are all solved in a consistent manner. Furthermore, the stripline-like open structures are solved by a newly proposed third kind of boundary conditions in the edge element implementation. By applying the new boundary condition to the open sides of the structures, the geometry mesh size is dramatically reduced and the CPU time is also saved greatly. The 2D1over2 structure study provides the basis for solving general 3D problems, including the transmission line discontinuities. This dissertation also studies many important issues including resonance problems and radiation effects. A design rule to avoid the spurious radiation is also suggested.

Tan, Jilin

434

Basic EMC (electromagnetic compatibility) technology advancement for c3 systems. Volume 1: A nonlinear macromodel of the bipolar integrated circuit operational amplifier for electromagnetic interference analysis  

NASA Astrophysics Data System (ADS)

A macromodel containing two transistors can accurately predict how amplitude modulated RF signals with RF carrier frequencies in the 0.05 to 100.0 MHz range are demodulated in bipolar operational amplifiers (micro A741 and LM10 op amps) to cause undesired low frequency responses related to the modulation envelope of the RF signals. The original op amp macromodel which was developed by Boyle at al was modified by adding four capacitors C(sub) to account for parasitic capacitance effects in integrated circuit op amps. A procedure for assigning C(sub) values is given. The macromodel can be used when the RFI signals are incident upon the op amp input terminals. The use of the macromodel leads to a substantial reduction in computer time and expense. The ability of the nonlinear macromodel to represent the overall integrated circuit nonlinear response with only two transistors at the input stage is explained using the feedback theory of cascaded nonlinear transfer functions. In an operational amplifier with a linear feedback in its second stage, the nonlinear response of the second stage is suppressed. The overall nonlinear response is dominated by the nonlinearities of the input stage.

Chen, G. K. C.; Whalen, J. J.

1983-12-01

435

Bridge fault simulation strategies for CMOS integrated circuits  

Microsoft Academic Search

Abstract Unfaulted Circuit Faulted Circuit X X After introducing the Primitive Bridge Function , a char - acteristic function describing the behavior of bridged com - ponents, we present a theorem for detecting feedback bridge faults We discuss two di erent methods of bridge fault simu - lation, one of which is new, and present experimental results relating the relative

Brian Chess; Tracy Larrabee

1993-01-01

436

Electrical integrity of state-of-the-art 0.13 ?m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication  

Microsoft Academic Search

We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

K. W. Guarini; A. W. Topol; M. Ieong; R. Yu; L. Shi; M. R. Newport; D. J. Frank; D. V. Singh; G. M. Cohen; S. V. Nitta; D. C. Boyd; P. A. O'Neil; S. L. Tempest; H. B. Pogge; S. Purushothaman; W. E. Haensch

2002-01-01

437

Double heterojunction GaAs-GaAlAs bipolar transistors grown by MOCVD for emitter coupled logic circuits  

Microsoft Academic Search

Double heterojonction N-p-N GaAlAs-GaAs-GaAlAs bipolar transistors (DHBT's) have been developed using MOCVD growth. We have investigated the influence of growth conditions on the d.c. characteristics of DHBT's. Devices with 0.2 µm base thichness and p = 2.1018cm-3exihibited common emitter current gain, ?, of up to 5500. The recombination current has been reduced such asbeta simeq 1for current densites as low

C. Dubon; R. Azoulay; P. Desrousseaux; J. Dangla; A. M. Duchenois; M. Hountondji; D. Ankri

1983-01-01

438

Interfacial electronic effects in functional biolayers integrated into organic field-effect transistors  

PubMed Central

Biosystems integration into an organic field-effect transistor (OFET) structure is achieved by spin coating phospholipid or protein layers between the gate dielectric and the organic semiconductor. An architecture directly interfacing supported biological layers to the OFET channel is proposed and, strikingly, both the electronic properties and the biointerlayer functionality are fully retained. The platform bench tests involved OFETs integrating phospholipids and bacteriorhodopsin exposed to 1–5% anesthetic doses that reveal drug-induced changes in the lipid membrane. This result challenges the current anesthetic action model relying on the so far provided evidence that doses much higher than clinically relevant ones (2.4%) do not alter lipid bilayers’ structure significantly. Furthermore, a streptavidin embedding OFET shows label-free biotin electronic detection at 10 parts-per-trillion concentration level, reaching state-of-the-art fluorescent assay performances. These examples show how the proposed bioelectronic platform, besides resulting in extremely performing biosensors, can open insights into biologically relevant phenomena involving membrane weak interfacial modifications.

Angione, Maria Daniela; Cotrone, Serafina; Magliulo, Maria; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Fratini, Emiliano; Baglioni, Piero; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2012-01-01

439

Diode-HBT-logic circuits monolithically integrable with ECl\\/CML circuits  

Microsoft Academic Search

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs\\/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic\\/current-mode-logic (ECL\\/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160

K.-C. Wang; S. M. Beccue; M.-C. F. Chang; R. B. Nubling; A. M. Cappon; T. C.-T. Tsen; D. M. Chen; P. M. Asbeck; C. Y. Kwok

1992-01-01

440

Triple-mode single-transistor graphene amplifier and its applications.  

PubMed

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications. PMID:20939515

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

441

Optimized (2nd Pass) Gallium Arsenide (GaAs) Integrated Circuit Radio Frequency (RF) Booster Designs for 425 MHz and Dual Band (425 and 900 MHz).  

National Technical Information Service (NTIS)

High-performance microwave and radio frequency integrated circuits are of interest to the Army. Several monolithic microwave integrated circuits (MMICs) were designed to enhance the performance of commercial-off-the-shelf (COTS) RF integrated circuits (RF...

J. Penn

2010-01-01

442

Gallium Arsenide (GaAs) Microwave Integrated Circuit Designs Submitted to TriQuint Semiconductor for Fabrication (ARL Tile No. 2).  

National Technical Information Service (NTIS)

High-performance microwave and radio frequency integrated circuits are of interest to the Army. Several monolithic microwave integrated circuits (MMICs) were designed to enhance the performance of commercial-off-the-shelf (COTS) RF integrated circuits (RF...

J. Penn

2010-01-01

443

An Exponential-Decay Synapse Integrated Circuit for Bio-inspired Neural Networks  

Microsoft Academic Search

Biologically-realistic artificial neurons and synapses are implemented on analog specific integrated circuits, to offer real-time\\u000a computation. We present here specific circuits where synaptic interactions are modeled using exponential-decay synapses, which\\u000a are digitally controlled. The design method is detailed, and experimental measurements on fabricated circuits are presented\\u000a to illustrate the synaptic mechanisms. We finally propose to exploit the synapses to build

Ludovic Alvado; Sylvain Saïghi; Jean Tomas; Sylvie Renaud-le Masson

2003-01-01

444

All-optical polariton transistor  

NASA Astrophysics Data System (ADS)

Although optical technology provides the best solution for the transmission of information, all-optical devices must satisfy several qualitative criteria to be used as logic elements. In particular, cascadability is difficult to obtain in optical systems, and it is assured only if the output of one stage is in the correct form to drive the input of the next stage. Exciton-polaritons, which are composite particles resulting from the strong coupling between excitons and photons, have recently demonstrated huge non-linearities and unique propagation properties. Here we show that polariton fluids moving in the plane of the microcavity can operate as input and output of an all-optical transistor, obtaining up to 19 times amplification and demonstrating the cascadability of the system. Moreover, the operation as an AND/OR gate is shown, validating the connectivity of multiple transistors in the microcavity plane and opening the way to the implementation of polariton integrated circuits.

Ballarini, D.; de Giorgi, M.; Cancellieri, E.; Houdré, R.; Giacobino, E.; Cingolani, R.; Bramati, A.; Gigli, G.; Sanvitto, D.

2013-04-01

445

All-optical polariton transistor.  

PubMed

Although optical technology provides the best solution for the transmission of information, all-optical devices must satisfy several qualitative criteria to be used as logic elements. In particular, cascadability is difficult to obtain in optical systems, and it is assured only if the output of one stage is in the correct form to drive the input of the next stage. Exciton-polaritons, which are composite particles resulting from the strong coupling between excitons and photons, have recently demonstrated huge non-linearities and unique propagation properties. Here we show that polariton fluids moving in the plane of the microcavity can operate as input and output of an all-optical transistor, obtaining up to 19 times amplification and demonstrating the cascadability of the system. Moreover, the operation as an AND/OR gate is shown, validating the connectivity of multiple transistors in the microcavity plane and opening the way to the implementation of polariton integrated circuits. PMID:23653190

Ballarini, D; De Giorgi, M; Cancellieri, E; Houdré, R; Giacobino, E; Cingolani, R; Bramati, A; Gigli, G; Sanvitto, D

2013-01-01

446

Toward Printed Integrated Circuits based on Unipolar or Ambipolar Polymer Semiconductors.  

PubMed

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (?) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of ? ? 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. PMID:23761043

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-06-12

447

Integration of Tunnel-Coupled Double Nanocrystalline Silicon Quantum Dots with a Multiple-Gate Single-Electron Transistor  

Microsoft Academic Search

We report on integration of double nanocrystalline silicon quantum dots (nc-Si QDs) of approximately 10 nm in diameter onto the multiple-gate single-electron transistor (SET) used as a highly-sensitive charge polarization detector. The SET with a single charging island is first patterned lithographically on silicon-on-insulator, and the multiple-gate bias dependence of the Coulomb current oscillation is characterized at 4.2 K. The

Yoshiyuki Kawata; Mohammed A. H. Khalafalla; Kouichi Usami; Yoshishige Tsuchiya; Hiroshi Mizuta; Shunri Oda

2007-01-01

448

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement  

ERIC Educational Resources Information Center

|This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

449

Heterodyne electrostatic force microscopy used as a new non-contact test technique for integrated circuits  

Microsoft Academic Search

In this paper a new high-resolution non-contact scanned probe voltage measurement technique for integrated circuits is presented. Voltages are extracted by sensing the localized electrostatic force between an energized probe and a point on the circuit being tested. Using a nulling method, the technique is capable of accurate magnitude measurements of high frequency signals without complex calibration requirements. An instrument

R. Said; G. Bridges

1995-01-01

450

Low power integrated circuits for an implantable pulsed Doppler ultrasonic blood flowmeter  

Microsoft Academic Search

Describes two custom integrated circuits which were developed for an implantable pulsed Doppler ultrasonic blood flowmeter. Prime design goals were a minimum circuit volume, minimum power consumption, and operation at low supply voltages. The first of the two IC's performs system timing functions and produces the ultrasonic transmit burst. It can deliver up to 40 mW of peak output power

ROBERT W. GILL; J. D. Meindl

1975-01-01

451

Quasi-Static Derived Physically Expressive Circuit Model for Lossy Integrated RF Passives  

Microsoft Academic Search

This paper presents a novel approach for deriving a physically meaningful circuit model for integrated RF lossy passives such as spiral inductors on a silicon substrate. The approach starts from a quasi-static partial element equivalent circuit (PEEC) model. The concept of complex inductance and capacitance is introduced to uniformly deal with the conductor and dielectric losses. Basic Y- Delta network

Hai Hu; Kai Yang; Ke-Li Wu; Wen-Yan Yin

2008-01-01

452

Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection  

Microsoft Academic Search

Radiation detectors based on the deposition of a 10 to 30 mum thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies.

M. Despeisse; G. Anelli; P. Jarron; J. Kaplon; D. Moraes; A. Nardulli; F. Powolny; N. Wyrsch

2008-01-01

453

Design and Fabrication of Audio Amplifier Utilizing Master-Slice Integrated Circuit.  

National Technical Information Service (NTIS)

This report describes the design and fabrication of an audio output amplifier built with a Master-Slice integrated circuit. The purpose of this program was the development of a general-purpose communication circuit that would demonstrate the utility of th...

R. A. Mammano

1968-01-01

454

A circuit extraction system and graphical display for VLSI (Very Large Scale Integrated) design  

NASA Astrophysics Data System (ADS)

A system is proposed for higher order logic extraction of components from a net-list of transistors and the graphical display of the extracted components. Critical sections were implemented to demonstrate the feasibility of the system. These sections include a prototype expert system written in CLIPS and a graphical display capable of displaying extracted components on a Sun workstation. Extraction techniques which were developed use pattern matching and multiple passes. Graphical techniques used in the display include simple line drawing and translation of images. This research has the potential to provide savings of time and effort to engineers designing new circuits or reverse-engineering older circuits for which no adequate specifications exist. This system will also help to close the design cycle and allow the designer to assure that what he has physically designed is what he has logically designed.

Yarost, Stuart A.

1989-12-01

455

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.  

ERIC Educational Resources Information Center

|Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)|

Muyskens, Mark A.

1997-01-01

456

Integrated Circuit/Message Switch Feasibility Model Development, Test, and Evaluation. Volume III. Time Division Module.  

National Technical Information Service (NTIS)

This report covers an investigation of known digital switching techniques to determine the most suitable technique for future switching applications. In addition, a digital switching matrix was designed, installed in the existing Integrated Circuit and Me...

B. Patrusky A. Mack N. Van Delft

1972-01-01

457

Investigation of Factors Involved in Reliability Assurance of Plastic-Encapsulated Integrated Circuits.  

National Technical Information Service (NTIS)

Upper temperature limits to accelerated stress testing of plastic-encapsulated integrated circuits were determined and evidence of chip-encapsulant interaction was obtained. Possible yield-reliability correlations were considered and alternatives to MIL-M...

J. L. Prince

1978-01-01

458

DirAc: An Integrated Circuit for Direct Acquisition of the M-Code Signal.  

National Technical Information Service (NTIS)

This paper describes the first integrated circuit (IC) designed, fabricated, and tested to perform direct acquisition of the M code signal. This DirAc IC prototype provides direct acquisition capability for test receivers and also demonstrates the feasibi...

J. D. Fite J. W. Betz P. T. Capozza

2004-01-01

459

The development of an uncommitted integrated circuit for combined digital and analogue applications  

NASA Astrophysics Data System (ADS)

An uncommmited integrated circuit is a standardized integrated circuit needing only a fraction of the normal processing steps to program it for a required application. The result is a reduction in the time, money and knowledge required to develop an integrated circuit. The development and industrialization of an uncommitted circuit for combined digital and analog applications are described. Integrated Injection Logic (I2L) is used to realize digital functions, and standard analog techniques, based on a bipolar process, are used to realize analog functions. A novel architecture, as well as the use of three masks to realize a required interconnection pattern, results in a very high efficiency in terms of the number of components that was used.

Kemp, A. J.

1982-06-01

460

Issues of verification and validation of application-specific integrated circuits in reactor trip systems.  

National Technical Information Service (NTIS)

Concepts of using application-specific integrated circuits (ASICs) in nuclear reactor safety systems are evaluated. The motivation for this evaluation stems from the difficulty of proving that software-based protection systems are adequately reliable. Imp...

R. E. Battle G. T. Alley

1993-01-01

461

An efficient method for computing transient response of integrated circuits with lossy transmission lines  

Microsoft Academic Search

Computing the transient signals in circuits with lossy transmission lines involves evaluation of convolution integrals at each time step. Each convolution integral requires signals from the initial time up to the current time. The paper presents a technique called the polynomial convolution algorithm that allows evaluation of a convolution integral at the current time step by using the result of

S. Chowdhury; J. S. Barkatullah

1992-01-01

462

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth  

NASA Astrophysics Data System (ADS)

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 ?m CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

463

Micromachined microwave actuator (MIMAC) technology-a new tuning approach for microwave integrated circuits  

Microsoft Academic Search

The authors describe a novel approach to the realization of tunable\\/variable III-V planar microwave integrated circuits, which uses micromachined electrostatically controlled actuator technology. This technology is potentially compatible with conventional MMIC (monolithic microwave integrated circuit) fabrication techniques, and allows precise positioning and re-positioning of metal conductors on an insulating substrate after fabrication is complete. A variety of structures has been

Lawrence E. Larson; Roy H. Hackett; Melissa A. Melendes; Ross F. Lohr

1991-01-01

464

Full software analysis and impedance matching of radio frequency CMOS integrated circuits  

Microsoft Academic Search

We present a systematic analysis technique of complementary metal-oxide-semiconductor (CMOS) radio-frequency (RF) integrated circuits (ICs). A full simulation program with integrated circuit emphasis (SPICE) simulation of the whole chip including the package and the die, with the parameters extracted from purely software analysis, has been performed. It is shown that the RF impedance matching without S-parameter based techniques is possible

Ki Hyuk Kim; Hoi Ju Chung; Sung Ho Yoon; Sung Woo Hwang; Jinwoo Park; Soo-Won Kim; Joongho Choi; D. Ahn

2000-01-01

465

Design of a semi-custom integrated circuit for the SLAC SLC timing control system  

SciTech Connect

A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given.

Linstadt, E.

1984-10-01

466

Monolithic Integration of UHF-MOSFET-Structures and Bipolar UHF Transistors.  

National Technical Information Service (NTIS)

Compatible UHF MOSFET and bipolar monolithic technology for application to FM and television electronic tuners was studied. A UHF MOS tetrode which features very low noise and high transductance, and MOS triodes and UHF bipolar transistors feasible for in...

W. Mueller

1982-01-01

467

Monolithic Integration of UHF-Mosfet-Structures and Bipolar UHF Transistors.  

National Technical Information Service (NTIS)

Compatible UHF MOSFET and bipolar monolithic technology for application to FM and television electronic tuners was studied. A UHF MOS tetrode which features very low noise and high transductance, and MOS triodes and UHF bipolar transistors feasible for in...

W. Mueller

1980-01-01

468

A Standard Digital Control Module for Two-Transistor Pulsewidth Modulated Converters  

Microsoft Academic Search

Two-transistor pulsewidth modulated converters do not find widespread application since they are usually expensive, bulky, and difficult to design. To resolve these difficulties, a circuit is presented in which the pulsewidth control mechanism is separate from the power-handling stages. This permits the use of a standard integrated digital control module, which simplifies the overall design of two-transistor pulsewidth modulated converters.

R. W. Michelet; M. Parente

1970-01-01

469

InP-based monolithic integration of 1.55-um MQW laser diode and HBT driver circuit  

NASA Astrophysics Data System (ADS)

An improved fabrication process and related experiment results of an InP-based monolithic integrated transmitter OEIC with a 1.55 micrometers MQW laser diode (LD) and an InP/InGaAs heterojunction bipolar transistors (HBT) driver circuit are presented. The epitaxial structure of the laser and driver circuits were continuously grown on semi- insulating Fe-doped InP substrate by a metal-organic chemical vapor deposition system using a vertically integration. HCL, H3PO4/H2O2 and HBr/HNO3 solution system were involved as selective or nonelective wet chemical etching respectively for the epitaxies of InP, InGaAs and InGaPAs. Both a nearly-standard contact photolithography depending on a two-step exposure technique and an electrical connection related to smoothly wet chemical etching profile of InP and InGaP in the crystal direction of (01-1) were developed in the process. The laser diode with a 3-um-wide ridge waveguide forming by a double- groove process self-aligned to the metal contact of P-type region showed an average threshold current as low as about 10mA. The HBT with a 120-nm-thick base layer performed a DC current gain of about 60-70 and an emitter-collector breakdown voltage of up to 4-5V. A clear eye diagram of the monolithic transmitter under a pulsed operation with 622Mbit/s bitrate nonreturn-to-zero pseudorandom code was obtained.

Li, Xian-Jie; Zhao, Fang-Hai; Zeng, Qing-Ming; Dong, Yi; Li, Xu-hui; Yang, Shu-Ren; Cai, Ke-Li; Wang, Benzhong; Ao, Jin-Ping; Liang, Chun-Guang; Liu, ShiYong

2000-04-01

470

Full Wave Simulation of Integrated Circuits Using Hybrid Numerical Methods  

Microsoft Academic Search

Transmission lines play an important role in digital electronics, and in microwave and millimeter-wave circuits. Analysis, modeling, and design of transmission lines are critical to the development of the circuitry in the chip, subsystem, and system levels. In the past several decays, at the EM modeling level, the quasi-static approximation has been widely used due to its great simplicity. As

Jilin Tan

1994-01-01

471

Low power RF integrated circuits: principles and practice  

Microsoft Academic Search

Ultralow power wireless communicators, such as paging receivers operating from a single cell, have prompted the development and discovery of circuit techniques and architectures which lower power consumption of RF IC's ten-fold or more compared to today's norms. This paper illustrates many of these design principles, mainly in a CMOS context. It argues for seeking strategic combinations of high quality

A. A. Abidi; H. Darabi

1999-01-01

472

Integration of high frequency current shunts in power electronic circuits  

Microsoft Academic Search

The majority of power electronic converters employ some kind of current measurement. Current transformers and current sensors employing Hall elements are convenient to use since they are galvanically isolated, and have therefore very good noise characteristics. Shunts on the other hand are very cost effective since it only involves placing a low value resistance in the circuit and amplifying the

J. A. Ferreira; W. A. Cronje; W. A. Relihan

1995-01-01

473

NOTE: Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies  

NASA Astrophysics Data System (ADS)

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process.

Yu, Xiaomei; Tang, Yaquan; Zhang, Haitao

2008-03-01

474

All-silicon nonlinear transmission line integrated into a Si\\/SiGe heterostructure bipolar transistor process  

Microsoft Academic Search

Summary form only given. Nonlinear Transmission Lines (NLTL) have been fabricated so far on GaAs substrates only. Recently, we were able to demonstrate a working nonlinear transmission line for the first time on high resistivity silicon proving the applicability of the NLTL concept to silicon millimeter wave integrated circuits (SIMMWICs). We have significantly improved our previous results by integrating the

M. Birk; D. Behammer; H. Schumacher

2000-01-01

475

Novel integrated readout circuit of variable integration time with background suppression for quantum dot infrared photo-detectors  

NASA Astrophysics Data System (ADS)

This paper discussed about a readout circuit for Quantum Dot Infrared Photodetector (QDIP) Focal-Plane-Array (FPA) imaging system. The readout circuit employed a modified regulated cascode circuit to stabilize the bias of QDIP. The readout circuit consisted of in-pixel dark current cancellation circuit, sensed current integration and in-pixel switch integration capacitor. The chip worked at 5V power supply and operated at 1MHz clock rate. Output voltage ranging from 2 volt to 4 volt was generated when the sensing current from 10nA to 100nA, the dark current was set up to 100nA. The total power consumption was less than 3.3 mW. The dimension of unit pixel was 30×30?m and the integration capacitance was about 0.24pF. The 8×8 pixels array readout circuit of in-pixel variable integration capacitors was implemented by using TSMC 0.35?m Mixed Signal 2P4M CMOS process.

Lu, Yi-Chuan; Shieh, Hsiu-Li; Hung, Sen-Chuan; Sun, Tai-Ping; Sheu, Meng-Lieh; Tang, Shiang-Feng; Chiang, Cheng-Der

2009-07-01

476

Current regulating circuit  

SciTech Connect

A battery charger which includes terminals for connection to an electric power source, an electrical charging circuit and an operative arrangement for connecting at least one rechargeable battery cell, in series with the charging circuit across the terminals. The battery charger has a charging circuit which includes a first resistor, a second resistor, a third resistor and a rectifier, constituted by at least one diode, in series. A first transistor, which has a collector-emitter path and a base-emitter path, is operatively connected so that the base-emitter path is connected in parallel with the first resistor. A fourth resistor is provided, the fourth resistor being connected in series with the collector-emitter path of the transistor and the third resistor. A plurality of additional transistors, connected in Darlington configuration, includes a second transistor and a final transistor, each of the additional transistors having its collector connected to a circuit point between the third resistor and an electrode of the diode. The first transistor and the last transistor have their emitters connected via a current-limiting PTC fifth resistor which may act as a fuse. The first transistor and the second transistor have their respective collector and base conductively connected. The connection of the third resistor provides internal feedback. The fifth resistor, when in series with the first resistor in the base-emitter circuit, provides external feedback.

Hoffman, Ph. A.

1985-03-12

477

Buffer direct injection readout integrated circuit design for dual band infrared focal plane array detector  

NASA Astrophysics Data System (ADS)

This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 ?m. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.

Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Tang, Shiang-Feng; Lin, Wen-Jen

2013-05-01

478

A new sustainer with primary sided integrated of DC\\/DC converter and energy recovery circuit for AC-PDP  

Microsoft Academic Search

A new Sustainer with Primary sided Integration of DC\\/DC converter and Energy Recovery circuit (SPIDER) is proposed. The proposed circuit operates as a DC\\/DC converter during address period and energy recovery circuit during sustain period. Therefore, the conventional three electronic circuits composed of the power supply, X-driver, and Y-driver can be reduced to one circuit. As a result, it has

Jae-Sung Park; Yong-Saeng Shin; Sung-Soo Hong; Sang-Kyoo Han; Dong-Sung Oh; Chung-Wook Roh

2011-01-01

479

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings  

Microsoft Academic Search

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs\\/GaAlAs, the design and fabrication of AlGaAs\\/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for

D. B. Ostrowsky; S. Sriram

1985-01-01

480

Heterogeneous GaSb/SOI mid-infrared photonic integrated circuits for spectroscopic applications  

NASA Astrophysics Data System (ADS)

Mid-infrared spectroscopy has gained significant importance in recent years as a detection technique for substances that absorb in this spectral region. Traditionally, a spectroscopic system consists of bulky equipment which is difficult to handle and incurs high cost. An integrated spectroscopic system would eliminate these disadvantages. GaSb-based active opto-electronic devices allow realizing mid-infrared light sources and detectors in the 2-3?m wavelength range for such integrated systems. Silicon photonics, based on Silicon-on-Insulator (SOI) waveguide circuits, on the other hand, is a well established technology based on high refractive index contrast waveguides, enabling ultra-compact passive integrated photonic circuits. Moreover, SOI waveguide circuit processing is compatible with CMOS processes. Hence, the integration of GaSb-based active devices onto SOI passive waveguide circuits potentially allows highly compact spectroscopic systems with a large degree of freedom in passive device design to improve the system performance. This approach has a high potential for several applications, e.g. an implantable glucose level monitor and gas sensing devices. In this paper, we report our work on the integration of GaSb-based epitaxy onto SOI waveguide circuits. The heterogeneous integration is based on an epitaxial layer transfer process using the polymer divinylsiloxanebenzocyclobutene (DVS-BCB) as a bonding agent. The process is performed by transferring the epitaxial layer to an SOI waveguide circuit wafer through a die-to-wafer bonding process. With this approach, a bonding layer of 150 nm thickness is easily achievable. We also report our results on the integration of waveguide-based GaSb p-i-n photodetectors coupled to SOI waveguide circuits using evanescent coupling, which show a responsivity higher than 0.4A/W. The design of active and passive structures and the overall fabrication process will also be discussed.

Hattasan, N.; Cerutti, L.; Rodriguez, J. B.; Tournié, E.; van Thourhout, D.; Roelkens, G.

2011-01-01

481

Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits  

Microsoft Academic Search

This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic

Pankaj Pant; Vivek K. De; Abhijit Chatterjee

1998-01-01

482

Efficient evaluation of spectral integrals in the moment method solution of microstrip antennas and circuits  

Microsoft Academic Search

A numerical algorithm for the moment method solution of printed circuit antenna problems is developed. The formulation uses a spectral domain approach. However, the integration variables are in the Cartesian instead of the polar coordinate system. This numerical scheme separates the integration involving the longitudinal and the transverse dependence of the basis functions. This aspect may reduce the computation effort

Hung-Yu Yang; Akifumi Nakatani; J. A. Castaneda

1990-01-01

483

Failures induced on analog integrated circuits by conveyed electromagnetic interferences: A review  

Microsoft Academic Search

Failures induced on analog integrated circuits by electromagnetic interference (EMI) will be analyzed with particular emphasis on integrated operational amplifiers built with different technologies. Additionally, the correlation found between EMI susceptibility and large-signal opamp behavior will be discussed. Some criteria for the design of low EMI susceptibility opamps will be derived. Finally, as an application example, the design of a

G. Masetti; S. Graffi; D. Golzio; Zs. M. Kovács-V

1996-01-01

484

Birefringent photonic integrated circuit for beam forming network of independently steerable multibeam antenna  

Microsoft Academic Search

We report on the development of a beam forming network (BFN) for three independently steerable beams by a five-element array antenna integrated on a birefringent photonic integrated circuit (PIC) chip and measured phase shift characteristics of the BFN by optical wavelength tuning. In a coherent optical signal processing system transmitting an RF signal as the frequency difference of two lightwaves,

Keizo Inagaki; W. Weiwei Hu; Yoshihiko Mizuguchi; Takashi Ohira

2000-01-01

485

APPLICATIONS OF RFID TECHNOLOGY TO IMPROVE PRODUCTION EFFICIENCY FOR INTEGRATED-CIRCUIT ASSEMBLY HOUSES  

Microsoft Academic Search

Efficiency and accuracy are the main factors to develop the competence for the integrated-circuit (IC) assembly industry. An IC assembly house needs to deal with problems of integrating production flows of wafer in, assembly, test, and shipping to provide clients instant and accurate products and services information.