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1

CMOS-based carbon nanotube pass-transistor logic integrated circuits  

PubMed Central

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

2

Large-scale complementary integrated circuits based on organic transistors  

Microsoft Academic Search

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of

B. Crone; A. Dodabalapur; Y.-Y. Lin; R. W. Filas; Z. Bao; A. Laduca; R. Sarpeshkar; H. E. Katz; W. Li

2000-01-01

3

Organic field-effect transistors and all-polymer integrated circuits  

Microsoft Academic Search

Electrical properties of field-effect transistors made of different solution processable organic semiconductors are described. The temperature and gate-voltage dependence of the mobility is shown and theoretically described using a model based on the variable-range hopping of charge carriers in an exponential density of states. Furthermore, a technology has been developed to make all-polymer integrated circuits. It involves reproducible fabrication of

M. Matters; D. M. de Leeuw; M. J. C. M. Vissenberg; C. M. Hart; P. T. Herwig; T. Geuns; C. M. J. Mutsaers; C. J. Drury

1999-01-01

4

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates  

NASA Astrophysics Data System (ADS)

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports pentacene organic thin film transistors fabricated on flexible polymeric substrates with record performance, the fastest photolithographically patterned organic TFT integrated circuits on polymeric substrates reported to date, and the fabrication of the organic TFT backplanes used to build the first organic TFT-driven active matrix liquid crystal display (AMLCD), also the first AMLCD on a flexible substrate, ever reported. In addition, the first investigation of functionalized pentacene derivatives used as the active layer in organic thin film transistors is reported. A low temperature (<110°C) process technology was developed allowing the fabrication of high performance organic TFTs, integrated circuits, and large TFT arrays on flexible polymeric substrates. This process includes the development of a novel water-based photolithographic active layer patterning process using polyvinyl alcohol that allows the patterning of organic semiconductor materials for elimination of active layer leakage current without causing device degradation. The small molecule aromatic hydrocarbon pentacene was used as the active layer material to fabricate organic TFTs on the polymeric material polyethylene naphthalate with field-effect mobility as large as 2.1 cm2/V-s and on/off current ratio of 108. These are the best values reported for organic TFTs on polymeric substrates and comparable to organic TFTs on rigid substrates. Analog and digital integrated circuits were also fabricated on polymeric substrates using pentacene TFTs with propagation delay as low as 38 musec and clocked digital circuits that operated at 1.1 kHz. These are the fastest photolithographically patterned organic TFT circuits on polymeric substrates reported to date. Finally, 16 x 16 pentacene TFT pixel arrays were fabricated on polymeric substrates and integrated with polymer dispersed liquid crystal to build an AMLCD. The pixel arrays showed good optical response to changing data signals when standard quarter-VGA display waveforms were applied. This result marks the first organic TFT-driven active matrix liquid crystal display ever reported as well as the first active matrix liquid crystal display on a flexible polymeric substrate. Lastly, functionalized pentacene derivatives were used as the active layer in organic thin film transistor materials. Functional groups were added to the pentacene molecule to influence the molecular ordering so that the amount of pi-orbital overlap would be increased allowing the potential for improved field-effect mobility. The functionalization of these materials also improves solubility allowing for the possibility of solution-processed devices and increased oxidative stability. Organic thin film transistors were fabricated using five different functionalized pentacene active layers. Devices based on the pentacene derivative triisopropylsilyl pentacene were found to have the best performance with field-effect mobility as large as 0.4 cm 2/V-s.

Sheraw, Christopher Duncan

2003-10-01

5

Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies  

SciTech Connect

Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q. [Sandia National Labs., Albuquerque, NM (United States); Enquist, P.M. [Research Triangle Inst., Research Triangle Park, NC (United States)

1995-12-31

6

Circuit Design with Independent Double Gate Transistors  

Microsoft Academic Search

Circuits with transistors using independently controlled gates have been designed to reduce the number of transistors and to increase the logic density per area. This paper proposed a full adder and substractor circuit with novel Vertical Slit Field Effect Transistor and unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. With the help of

Viranjay M. Srivastava; Nitant Saubagya; G. Singh

2010-01-01

7

Large-area stretchable organic transistor integrated circuits for sensor and display applications  

NASA Astrophysics Data System (ADS)

Stretchability significantly expands the scope of electronic applications-particularly large-area electronics such as displays, sensors, and actuators-because stretchable electronics can cover arbitrary surfaces and movable parts, which is impossible with conventional electronics. However, the realization of stretchable electronics for the manufacturing of electrical wiring with high conductivity, high stretchability, and large-area compatibility is a major hurdle. We manufactured printable elastic conductors comprising single-walled carbon nanotubes (SWNTs) uniformly dispersed in fluorinated rubber. Using ionic liquid and jet milling, we produced longer and finer SWNT bundles that formed well-developed conducting networks in rubber. A conductivity and stretchability greater than 100 S/cm and 100%, respectively, were obtained. In order to demonstrate the feasibility of the elastic conductors for electrical wiring, we manufactured a rubber-like large-area organic transistor active matrix comprising printed organic transistors and elastic conductors. The effective area of the matrix was 20 × 20 cm2. The active matrix sheet was uniaxially and biaxially stretched to 70% without incurring mechanical or electrical damage. Furthermore, we constructed a rubber-like stretchable active matrix display comprising integrated printed elastic conductors, organic transistors, and organic light-emitting diodes. The display could stretch by 30-50% and spread over a hemisphere without being mechanically or electrically damaged.

Sekitani, Tsuyoshi; Someya, Takao

2009-08-01

8

431 531 Class Notes 5 5 Transistors and Transistor Circuits  

E-print Network

431 531 Class Notes 5 5 Transistors and Transistor Circuits Although I will not follow the text in detail for the discussion of transistors, I will follow the text's philosophy. Unless one gets into device fabrication, it is generally not important to understand the inner workings of transistors

Frey, Raymond E.

9

A spiking neuron circuit based on a carbon nanotube transistor  

NASA Astrophysics Data System (ADS)

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions.

Chen, C.-L.; Kim, K.; Truong, Q.; Shen, A.; Li, Z.; Chen, Y.

2012-07-01

10

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates  

Microsoft Academic Search

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports

Christopher Duncan Sheraw

2003-01-01

11

A Bonded-Micro-Platform Technology for Modular Merging of RF MEMS and Transistor Circuits  

E-print Network

A Bonded-Micro-Platform Technology for Modular Merging of RF MEMS and Transistor Circuits Ark µmechanical filters with integrated BiCMOS transistor circuits while attempting to preserve the Q of mounted are then released (together with devices) and compression bonded onto a transistor circuit wafer, making electrical

Nguyen, Clark T.-C.

12

Transistor operation and circuit performance in organic electronics  

Microsoft Academic Search

Electronics based on organic transistors is steadily progressing towards higher levels of integration and better performance. In this work we discussed the operation of organic field-effect transistors and the charge transport properties of organic conjugated semiconductors. We also presented a simple analysis of some basic building blocks used in organic digital electronics, focusing on the relation between device and circuit

E. Cantatore; E. J. Meijer

2003-01-01

13

THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development,  

E-print Network

THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit-gain cutoff frequencies of 1-3 THz. High bandwidths are obtained by scaling; the critical limits for the 64 nm scaling geneation (1 THz f, 2 THz fmax) have been developed. We here examine the high

Rodwell, Mark J. W.

14

Modeling Advanced Avalanche Effects for Bipolar Transistor Circuit Design  

E-print Network

Modeling Advanced Avalanche Effects for Bipolar Transistor Circuit Design Vladimir Milovanovi operating frequency and high output power of modern bipolar transistor circuits increase, designers are trying to exploit transistor operating regions where they would be able satisfy both conditions, namely

Technische Universiteit Delft

15

Field-Effect Transistor Reactance Circuits.  

National Technical Information Service (NTIS)

Efforts to miniaturize the reactance circuits of vacuum-tube technology by using junction transistors have been only partially successful. Large equivalent inductances and capacitances are obtainable, but the effective Q is limited to low values by the lo...

G. D. Clark

1968-01-01

16

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.  

SciTech Connect

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

2008-08-01

17

High Performance Crystalline Organic Transistors and Circuit.  

National Technical Information Service (NTIS)

We have examined the best available small molecule crystalline organic semiconductors as active layers in thin-film transistors. We have optimized the field-induced conductance, a figure of merit that will relate directly to circuit speeds. A simple figur...

A. Dodabalapur

2011-01-01

18

RF SMALL SIGNAL AVALANCHE CHARACTERIZATION AND REPERCUSSIONS ON BIPOLAR TRANSISTOR CIRCUIT DESIGN  

E-print Network

RF SMALL SIGNAL AVALANCHE CHARACTERIZATION AND REPERCUSSIONS ON BIPOLAR TRANSISTOR CIRCUIT DESIGN transistor circuits, electronic circuit designers are exploring regimes of transistor operation that meet on some important transistor properties like unilateral and maximum available power gain, as well

Technische Universiteit Delft

19

Adder circuits with transistors using independently controlled gates  

Microsoft Academic Search

Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. So far only small building blocks have been presented. This paper investigates for the first time the use of independent double gate transistors in 16 bit ripple carry and parallel prefix adders. New adder circuits and

Marcus Weis; Andrzej Pfitzner; Dominik Kasprowicz; Rainer Emling; Wojciech Maly; Doris Schmitt-Landsiedel

2009-01-01

20

High-performance top-gated monolayer SnS2 field-effect transistors and their integrated logic circuits.  

PubMed

Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm(2) V(-1) s(-1), much higher than that of the back-gated counterparts (~1 cm(2) V(-1) s(-1)). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics. PMID:23989804

Song, H S; Li, S L; Gao, L; Xu, Y; Ueno, K; Tang, J; Cheng, Y B; Tsukagoshi, K

2013-10-21

21

Modeling and simulation of insulated-gate field-effect transistor switching circuits  

Microsoft Academic Search

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET

HAROLD SHICHMAN; DAVID A. HODGES

1968-01-01

22

Testing tri-state and pass transistor circuit structures  

E-print Network

effort for tristate and pass transistor structures. We do circuit level modeling to help develop and validate gate level models, which can be used in production ATPG. We study the two primary effects of interest, capacitive coupling and leakage...

Parikh, Shaishav Shailesh

2005-11-01

23

Co-integrated resonant tunneling and heterojunction bipolar transistor full adder  

Microsoft Academic Search

We present the first resonant tunneling bipolar transistor integrated circuits operating at room temperature. The circuits are comprised of co-integrated resonant tunneling and double heterojunction bipolar transistors based on III-V heteroepitaxy on InP substrates. The resonant tunneling bipolar transistors exhibit a peak-to-valley collector current ratio exceeding 70 which is higher than previous room temperature reports. Using this technology we demonstrate

A. C. Seabaugh; A. H. Taddiken; J. N. Randall; Y.-C. Kao; B. Newell

1993-01-01

24

CMOS magnetic sensor integrated circuit with sectorial MAGFET  

Microsoft Academic Search

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6?m digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling

Guo Qing; Zhu Dazhong; Yao Yunruo

2006-01-01

25

Heterogeneous photonic integrated circuits  

NASA Astrophysics Data System (ADS)

Photonic Integrated Circuits (PICs) have been dichotomized into circuits with high passive content (silica and silicon PLCs) and high active content (InP tunable lasers and transceivers) due to the trade-off in material characteristics used within these two classes. This has led to restrictions in the adoption of PICs to systems in which only one of the two classes of circuits are required to be made on a singular chip. Much work has been done to create convergence in these two classes by either engineering the materials to achieve the functionality of both device types on a single platform, or in epitaxial growth techniques to transfer one material to the next, but have yet to demonstrate performance equal to that of components fabricated in their native substrates. Advances in waferbonding techniques have led to a new class of heterogeneously integrated photonic circuits that allow for the concurrent use of active and passive materials within a photonic circuit, realizing components on a transferred substrate that have equivalent performance as their native substrate. In this talk, we review and compare advances made in heterogeneous integration along with demonstrations of components and circuits enabled by this technology.

Fang, Alexander W.; Fish, Gregory; Hall, Eric

2012-01-01

26

Direct extraction of equivalent circuit parameters for heterojunction bipolar transistors  

Microsoft Academic Search

A new method is presented for the direct extraction of hybrid-T equivalent circuits for heterojunction bipolar transistors. The method differs from previous ones by extracting the equivalent circuit without using test structures or numerical optimization techniques. Instead, all equivalent circuit parameters are calculated analytically from small-signal S-parameters measured under different bias conditions. The analysis includes the distributed nature of the

Ce-Jun Wei; James C. M. Hwang

1995-01-01

27

Integration of Cell Membranes and Nanotube Transistors  

E-print Network

Integration of Cell Membranes and Nanotube Transistors Keith Bradley, Alona Davis, Jean. As the nanoelectronic device, we use a nanotube network transistor, which incorporates many individual nanotubes as transistors, and that the two systems interact. Further, we use the interaction to study the charge

Gruner, George

28

Bioluminescent bioreporter integrated circuit  

DOEpatents

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

2000-01-01

29

A "Single-Photon" Transistor in Circuit Quantum Electrodynamics  

E-print Network

We introduce a circuit quantum electrodynamical setup for a "single-photon" transistor. In our approach photons propagate in two open transmission lines that are coupled via two interacting transmon qubits. The interaction is such that no photons are exchanged between the two transmission lines but a single photon in one line can completely block respectively enable the propagation of photons in the other line. High on-off ratios can be achieved for feasible experimental parameters. Our approach is inherently scalable as all photon pulses can have the same pulse shape and carrier frequency such that output signals of one transistor can be input signals for a consecutive transistor.

Lukas Neumeier; Martin Leib; Michael J. Hartmann

2012-11-30

30

Lab 3: Transistor Circuits and JFETs This Lab is Too Long by 50  

E-print Network

Lab 3: Transistor Circuits and JFETs This Lab is Too Long by 50 3.1 Goals of this Lab Following our introduction to transistors in Lab 2, this time we will study some common transistor circuits. Finally, there is a short introduction to one type of transistor of the FET technology family, the JFET. For convenience

Frey, Raymond E.

31

Reactance Controlled Transistor Oscillator Circuit Arrangement.  

National Technical Information Service (NTIS)

An accurate and precise reactance control circuit is provided which functions equally well over an extended frequency spectrum. A frequency control circuit is shown for use with a variable frequency oscillator. It introduces a constant change in frequency...

R. Krausz, J. M. Shapiro

1965-01-01

32

The Integrated Circuit Game  

NSDL National Science Digital Library

Integrated circuits can be found in almost every modern electrical device; such as computers, cars, television sets, CD players, cell phones, and so on. But what is an integrated circuit and what is the history behind it? Learn about Nobel Laureate Jack Kilby and his part in the invention that is the basis of all modern technology. In the beginning of this game you have to take the quiz consisting of four questions, otherwise you will not be able to move on in this game. The answers to the questions are found in the museum. As "Maria" you walk around in the fantasy town "Techville" in Texas. At some points you have to give the right answers or figure out something before you can move on. You will pass a portal that takes you back in time to Nobel Laureate Jack Kilby's lab in 1958, among other things. The challenge in this game is to make it to the end.

2013-06-20

33

6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design  

E-print Network

6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design Prof. Joel L;6.301 Solid State Circuits Recitation 1: Transistor Biasing and Thoughts on Design Prof. Joel L. Dawson Page 2's move on to the matter of biasing a transistor circuit. What does this mean, and what constitutes a good

Goldwasser, Shafi

34

An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization  

E-print Network

An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization topology, the delay can be controlled by varying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit

Sapatnekar, Sachin

35

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 693 Buffer Minimization in Pass Transistor Logic  

E-print Network

2001 693 Buffer Minimization in Pass Transistor Logic Hai Zhou and Adnan Aziz Abstract--With shrinking feature sizes and increasing transistor counts on chips, demands for higher speed and lower power make metal­oxide­semiconductors. Among them, pass transistor logic (PTL) is of great promise. Since delay

Zhou, Hai

36

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits  

Microsoft Academic Search

Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related nonidealities and imperfections, and parasitic resistances and capacitances extracted from the CNFET circuit layout. We use

Nishant Patil; Jie Deng; Subhasish Mitra; H.-S. Philip Wong

2009-01-01

37

Flexible organic transistors and circuits with extreme bending stability  

NASA Astrophysics Data System (ADS)

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100?m. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5?m), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2010-12-01

38

Integration of pentacene-based thin film transistors via photolithography for low and high voltage applications  

E-print Network

An organic thin film transistor (OTFT) technology platform has been developed for flexible integrated circuits applications. OTFT performance is tuned by engineering the dielectric constant of the gate insulator and the ...

Smith, Melissa Alyson

2012-01-01

39

Heat Generation and Transport in Nanometer-Scale Transistors Heat problems in ever-smaller integrated circuits include hot-spots at transistor drain areas, reduced heat conduction in new devices and higher thermal resistance at material boundaries  

Microsoft Academic Search

As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin

Eric Pop; Sanjiv Sinha; Kenneth E. Goodson

40

Run-Time Programming of Analog Circuits Using Floating-Gate Transistors  

E-print Network

Run-Time Programming of Analog Circuits Using Floating-Gate Transistors David W. Graham Lane of floating-gate (FG) transistors provides programmability to analog circuitry and, hence, the ability to recalibrate an analog system. If the FG transistors are programmed indirectly by using a second transistor

Graham, David W.

41

Integrated High Voltage Wsitching Circuit for Ultrasound Transducer Array.  

National Technical Information Service (NTIS)

An integrated high-voltage switching circuit includes a switch having ON and OFF states and having a parasitic gate capacitance. The switch consists of a pair of DMOS transistors integrated back to back and having a shared gate terminal, the drains of the...

R. G. Wodnicki

2004-01-01

42

Chapter II MOS Transistor Modelling for MMW Circuits ChapterChapterChapterChapter IIIIIIII  

E-print Network

Chapter II MOS Transistor Modelling for MMW Circuits 15 ChapterChapterChapterChapter IIIIIIII MOS transistor model and layout issues One of the most important design issues in millimeter wave circuit design in modern MOS technologies is active devices and related parasitic elements modeling. The MOS transistor

Paris-Sud XI, Université de

43

Extraction of Gate Level Models from Transistor Circuits by FourValued Symbolic Analysis  

E-print Network

Extraction of Gate Level Models from Transistor Circuits by Four­Valued Symbolic Analysis Randal E­level representation of an MOS transistor circuit. The resulting model contains only four­valued unit and zero delay transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones

Bryant, Randal E.

44

Thermionic integrated circuits: electronics for hostile environments  

SciTech Connect

Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

1985-01-01

45

Confinement-modulated junctionless nanowire transistors for logic circuits.  

PubMed

We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices. PMID:25297836

Vaurette, François; Leturcq, Renaud; Lepilliet, Sylvie; Grandidier, Bruno; Stiévenard, Didier

2014-10-24

46

Integrated coherent matter wave circuits  

E-print Network

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then propagate freely in waveguides where they can be switched, divided, recombined, and detected. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. Here we report experiments demonstrating integrated matter wave circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly-moving, tightly-focused laser beam exerts forces on atoms through their electrical polarizability. The source of coherent matter waves is a Bose-Einstein condensate (BEC). We launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These developments open the door to creating arbitrary and dynamic coherent mat...

Ryu, C

2014-01-01

47

Thermoelectricity from wasted heat of integrated circuits  

NASA Astrophysics Data System (ADS)

We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systems-on-chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

Fahad, Hossain; Hasan, Md.; Li, Guodong; Hussain, Muhammad

2013-06-01

48

Photonic integrated circuits for optical logic applications  

E-print Network

The optical logic unit cell is the photonic analog to transistor-transistor logic in electronic devices. Active devices such as InP-based semiconductor optical amplifiers (SOA) emitting at 1550 nm are vertically integrated ...

Williams, Ryan Daniel

2007-01-01

49

Logic and transistor circuit verification using regression testing and hierarchical recursive learning.  

E-print Network

??We describe a new approach for formal verification of combinational logic circuits, and their switch-level transistor implementation. Our approach CODibines regression testing, hierarchical recursive learning,… (more)

Shao, Li

2012-01-01

50

Silicon integrated circuit technology from past to future  

Microsoft Academic Search

Tremendous progress of the silicon integrated circuits (ICs) has been driven by the downsizing of their components such as MOS field effect transistors (MOSFETs) over 30 years. In order to maintain the progress for future, every dimension of the MOSFETs has to be shrunk continuously with almost the same ratio. However, the dimensions are now close to their limit of

Hiroshi Iwai; Shun'ichiro Ohmi

2002-01-01

51

Synthetic Biology: Integrated Gene Circuits  

PubMed Central

A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits “from scratch” that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches are providing fundamental insights into the regulatory architecture, dynamics, and evolution of genetic circuits and enabling new levels of control across diverse biological systems. PMID:21885772

Nandagopal, Nagarajan; Elowitz, Michael B.

2014-01-01

52

CIRCUIT CELLAR MARCH 2014 #28480TECHTHEFUTURE People want transistors--lots of them. It  

E-print Network

CIRCUIT CELLAR · MARCH 2014 #28480TECHTHEFUTURE People want transistors--lots of them. It pretty, the more the merrier. Diversity is also good. The more different the transistors, the more useful and interesting the product. And without any question, the cheaper the transistors, the better. So the issue is

Friedman, Eby G.

53

54 IRE TRANSACTIONS-CIRCUIT THEORY March Solution of a Transistor Transient Response Problem*  

E-print Network

54 IRE TRANSACTIONS-CIRCUIT THEORY March Solution of a Transistor Transient Response Problem-frequency and switching applications of transistors. A single transient response measure- ment can, in principle, yield of the device allows its response to any other driving curve-shape to be calculated.' Calculation of transistor

Macdonald, James Ross

54

431 531 Class Notes 8 5.8 More on Transistor Circuits  

E-print Network

431 531 Class Notes 8 5.8 More on Transistor Circuits 5.8.1 Intrinsic Emitter Resistance One consequenceof the Ebers-Moll equation, which wewill discuss later, is that the transistor emitter has an e ective resistance is just the usual parallel resistance of R1, R2, and the transistor input impedance RE

Frey, Raymond E.

55

Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint  

E-print Network

Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint Manjit University Park, PA 16802 Mary Jane Irwin Abstract We consider the problem of transistor sizing in a static that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption

He, Lei

56

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits  

E-print Network

that sequential printing of NWs, nanoribbons, and/or CNTs is a viable approach for constructing 3D integrated) Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS

Xiong, Qihua

57

A superconductive integrated circuit foundry  

NASA Astrophysics Data System (ADS)

A foundry has been established for production of superconductive integrated circuits, modeled after semiconductor application-specific integrated circuit (IC) production. The foundry supports and improves standardized Nb-based IC processing, and develops advanced processes such as a novel NbN-based process. The authors discuss the operation of the foundry, standardized process technologies, design rules, process flows, in-line product tracking, statistical process control, and automated parametric testing. The advantages of fine-line lithography and a class 10/100 environment are presented. Internal and external customer support with standard layout and circuit design tools enables reliable, quick turnaround production of a wide range of circuits. Finally, the authors present examples of concurrent device and process development towards improved, denser circuits, while maintaining a disciplined foundry environment.

Abelson, L. A.; Thomasson, S. L.; Murduck, J. M.; Elmadjian, R.; Akerling, G.; Kono, R.; Chan, H. W.

1993-03-01

58

Radio Frequency Integrated Circuits  

E-print Network

DEPARTMENT OF ENGINEERING SCIENCES UPPSALA UNIVERSITY UPPSALA, SWEDEN Submitted to the Faculty of Science of Technology. #12;© Peter Lindberg, 2005 Printed in Sweden by Eklundshofs Grafiska AB, Uppsala, 2005 #12;To developed during the Euro- pean Commission funded project ARTEMIS. The circuits have been manufactured using

59

Weaving integrated circuits into textiles  

Microsoft Academic Search

In this paper, we present and demonstrate a technology for integrating electronic functionality at the yarn level of woven textiles. The technology principles are compliant with commercial weaving processes and suitable for large scale manufacturing. Thin-film devices, interconnect lines and contact pads are patterned and silicon-based integrated circuits are attached to flexible plastic substrates. The substrates are cut into electronic

Christoph Zysset; Kunigunde Cherenack; Thomas Kinkeldei; G. Troster

2010-01-01

60

Circuit yield of organic integrated electronics  

Microsoft Academic Search

Research on organic electronics is focussed on materials and on the performance of discrete devices. Reliability and circuit yield is largely unexplored. Yield, based on measurements on digital organic circuits up to 1000 transistors, is described. The causes of yield loss are analyzed and design solutions to improve the yield are discussed.

E. Cantatore; C. M. Hart; M. Digioia; G. H. Gelinck; T. C. T. Geuns; H. E. A. Huitema; L. R. R. Schrijnemakers; E. van Veenendaal; D. M. de Leeuw

2003-01-01

61

Superconductor integrated circuit fabrication technology  

Microsoft Academic Search

Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates\\/cm2. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex

LYNN A. ABELSON; GEORGE L. KERBER

2004-01-01

62

e bipolar junction transistor (BJT) is historically the first solid-state analog amplifier and digital switch, and formed the basis of integrated circuits (IC) in the 1970s. Starting in the early 1980s, the  

E-print Network

, the invention of silicon­germanium base heterojunction bipolar transistor (SiGe HBT) brought the bipolar line communications applications. Today, SiGe HBTs are used to design radio-frequency integrated radar, wireless distribution of cable television, millimeter wave radios, and many more applications

Wilamowski, Bogdan Maciej

63

Vertically Integrated Circuits at Fermilab  

SciTech Connect

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

2009-01-01

64

Gallium arsenide for devices and integrated circuits  

SciTech Connect

Gallium Arsenide has long been hailed as the material of the future and it is only in recent years that the technology associated with its growth and processing has matured to the point where IC production can be contemplated at the industrial level. This point has now been reached and the electronics industries in Europe, the USA and Japan are actively moving from research activities into product development using this and related material. The text is divided into 15 chapters: Gallium Arsenide: Physical and Transport Properties; Liquid phase and Vapour Phase Epitaxy of GaAs and Related Compounds; Expitaxial Growth and GaAs: MBE and MOCVD; Characterization of GaAs I: Electrical Techniques; Characterization of GaAsII: Ion Beam Analysis; Ion Implantation; Wet and Dry Processing GaAs; Microwave and Millimetre - Wave Diodes; GaAs Mesfet's and High Electron Mobility Transistors (HEMT); Optoelectronic Devices and Components; Gallium Arsenide Monolithic Microwave Integrated Circuits; GaAs Digital Integrated Circuits; III-V Semiconductors for Solar Cells.

Morgan, D.V.; Thomas, H.

1986-01-01

65

Graphene-Dielectric Integration for Graphene Transistors  

PubMed Central

Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-? dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities. PMID:21278913

Liao, Lei; Duan, Xiangfeng

2010-01-01

66

Automatic generation of signal processing integrated circuits  

Microsoft Academic Search

A system for the automated design of signal processing integrated circuits is described in this thesis. The system is based on a library of circuit cells, and a software package that can configure the cells into complete integrated circuits. The architecture of the cell library is optimized for low and medium bandwidth digital signal processing applications. Circuits designed with the

Pope

1985-01-01

67

Logic and transistor circuit verification using regression testing and hierarchical recursive learning  

E-print Network

We describe a new approach for formal verification of combinational logic circuits, and their switch-level transistor implementation. Our approach CODibines regression testing, hierarchical recursive learning, and test generation techniques. A...

Shao, Li

2012-06-07

68

Vertically integrated circuit development at Fermilab for detectors  

NASA Astrophysics Data System (ADS)

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

Yarema, R.; Deptuch, G.; Hoff, J.; Khalid, F.; Lipton, R.; Shenai, A.; Trimpl, M.; Zimmerman, T.

2013-01-01

69

Modeling of single-event upset in bipolar integrated circuits  

NASA Technical Reports Server (NTRS)

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.

1983-01-01

70

Low-power integrated-circuit driver for ferrite-memory word lines  

NASA Technical Reports Server (NTRS)

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Katz, S.

1970-01-01

71

Self-integration of nanowires into circuits via guided growth  

PubMed Central

The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom–up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel “self-integration” of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

2013-01-01

72

Simulation of radiation induced circuit failure modes in SOS integrated circuits  

NASA Astrophysics Data System (ADS)

The design of radiation hard integrated circuits is discussed. The complex interaction between the several distinct effects of radiation on an individual transistor's characteristic is considered. Existing simulations often examine only one effect at any one time, and then in a crude global manner. The task of predicting the combined effects of these phenomena on a circuit as a whole is difficult, and as a result critical circuit failure mechanisms can often be overlooked. The major radiation effects with which the designer is concerned and some techniques used to predict their combined effect using the SPICE circuit simulator are described. An example of some of the results of this kind of analysis are presented, together with some conclusions drawn from them. Suggestions for future improvements in modeling and simulation techniques are made.

Townsend, G. C.; Bird, S. A.

1991-03-01

73

Bipolar junction transistor models for circuit simulation of cosmic-ray-induced soft errors  

NASA Technical Reports Server (NTRS)

This paper examines bipolar junction transistor models suitable for calculating the effects of large excursions of some of the variables determining the operation of a transistor. Both the Ebers-Moll and Gummel-Poon models are studied, and the junction and diffusion capacitances are evaluated on the basis of the latter model. The most interesting result of this analysis is that a bipolar junction transistor when struck by a cosmic particle may cause a single event upset in an electronic circuit if the transistor is operated at a low forward base-emitter bias.

Benumof, R.; Zoutendyk, J.

1984-01-01

74

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress  

NASA Technical Reports Server (NTRS)

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Mclyman, W. T. (inventor)

1981-01-01

75

A new parameter extraction technique for small-signal equivalent circuit of polysilicon emitter bipolar transistors  

Microsoft Academic Search

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection

Seonghearn Lee; Byung R. Ryum; Sang Won Kang

1994-01-01

76

New platforms for electronic devices: N-channel organic field-effect transistors, complementary circuits, and nanowire transistors  

Microsoft Academic Search

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized alpha,o-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N'-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric\\/electrode surface treatment on the response of bottom-contact devices was also examined

Byungwook Yoo

2007-01-01

77

Plasma processing for integrated circuits  

SciTech Connect

The steady advance of integrated circuit technology is one of the most remarkable technology trends in this era of technological revolution. For example, the 64-k memory chips of the early 1980s are now being replaced by 4-M and even 16-M chips. This trend is expected to continue with chips at the giga-bit level being available in a decade. The needs for ultraviolet and then X-ray lithography to define the submicron features needed for these larger, denser chips have been widely discussed. However, in parallel, the equipment (referred to as tools in the industry) and related processes to carry out the deposition and etching steps needed to actually produce devices in the tenth-micron range also require significant development. This paper summarizes present and anticipated contributions of magnetic fusion plasma theory and diagnostics and plasma production technology at Oak Ridge National Laboratory (ORNL) for the development of integrated circuit production technology. The discussion is introduced with a review of past technology evolution and of the present economic context for manufacturing.

Berry, L.A.

1994-10-01

78

Organic thin-film transistors: Characterization and integration on low temperature substrates for flexible electronics  

NASA Astrophysics Data System (ADS)

In this work pentacene thin-film transistors (TFTs) are fabricated and characterized on low temperature substrates for flexible electronic applications. Maximum processing temperature is <120°C. Pentacene transistors are optimized by varying the deposition conditions, thickness ratio of source-drain metal contact to pentacene film. By using parylene as the gate dielectric film, pentacene TFTs with low threshold voltage (VT) and low V T variation are fabricated. Gate-last integration technique is presented enabling integration of pentacene p-type TFTs with a:Si:H n-type TFTs to form hybrid complementary metal-oxide-semiconductor (CMOS) circuits on polyethylene naphthalate (PEN). Circuits evaluated are inverters, 2-input NAND and NOR logic gates. Parylene gate dielectric reliability and gate bias stress analysis of TFTs and hybrid CMOS circuit is also presented.

Gowrisanker, Srinivas

79

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)  

Microsoft Academic Search

The drive circuit requirements of the insulated gate bipolar transistor (IGBT) are explained with the aid of an analytical model. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of anode voltage. Model results are compared with measured turn-on and turn-off waveforms for different drive, load, and feedback circuits, and for different

1991-01-01

80

Fabrication process design for complementary metal-cytop-organic-semiconductor integrated circuits  

Microsoft Academic Search

We report on design flows for the fabrication process of n and p type organic transistors onto a single substrate that allows for the integration of integrated circuits. Our fabrication process employs Cytop as the gate dielectric and four different combinations of organic semiconductors. Two p type organic semiconductors were used, Pentacene and alpha-sexithiophene and two n type semiconductors were

Edward Choi; Recep Ozgun; Bal Mukund Dhar; Howard Katz; Andreas G. Andreou

2008-01-01

81

A circuit-compatible model of ballistic carbon nanotube field-effect transistors  

Microsoft Academic Search

Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V

Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy

2004-01-01

82

Transistor-level test generation for physical failures in CMOS circuits  

Microsoft Academic Search

A new methodology is proposed for generating tests at the transistor level for realistic failures including bridging faults, and transistor gate-to-source short and gate-to-drain short faults in CMOS combinational circuits. A new tree model for a fault-free CMOS complex gate is used to propagate errors due to faults with much less computation time. The technique adapts the tree structure representation

Hsi-Ching Shih; Jacob A. Abraham

1986-01-01

83

Lithography for enabling advances in integrated circuits and devices.  

PubMed

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing. PMID:22802500

Garner, C Michael

2012-08-28

84

Integrated Circuit Electromagnetic Immunity Handbook  

NASA Astrophysics Data System (ADS)

This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

Sketoe, J. G.

2000-08-01

85

InP HBTs for THz Frequency Integrated Circuits M. Urteaga1  

E-print Network

InP HBTs for THz Frequency Integrated Circuits M. Urteaga1 , M.Seo1 , J. Hacker1 , Z. Griffith1 , A process has been developed for THz frequency integrated circuits. A 0.25x4m2 HBT exhibits an extrapolated ft/fmax of 430GHz/1.03THz at IC =11mA, VCE= 1.8V. The transistors achieve this performance while main

Rodwell, Mark J. W.

86

Automatic generation of signal processing integrated circuits  

SciTech Connect

A system for the automated design of signal processing integrated circuits is described in this thesis. The system is based on a library of circuit cells, and a software package that can configure the cells into complete integrated circuits. The architecture of the cell library is optimized for low and medium bandwidth digital signal processing applications. Circuits designed with the system use a multiprocessor architecture. Input to the system is a design file written in a specialized programming language. Software emulation from the design file is used to verify performance. A two-pass silicon compiler is used to translate the design file into a mask-level description of an integrated circuit. A major goal of the project is to make the system useable by those with little or no formal training in integrated circuits. A second goal is to reduce the time and cost associated with performing an integrated circuit design, while still producing designs which are reasonably efficient in their use of the technology. Development of the system was guided by basic research on appropriate architectures and circuit constructs for signal processors. As part of this research an integrated circuit was designed which performs speech analysis and synthesis. This vocoder circuit is intended for use in low-bit-rate digital speech transmission systems.

Pope, S.P.

1985-01-01

87

The design of a regulated variable power supply for transistor circuits  

E-print Network

LI BRARg A & M COLLEGE OF TE)gS THE DESIGN OF A REGULATED VARIARLE POMER SUPPLY FOR TRANSISTOR CIRCUITS A THESIS Oscar David Graham Submitted to the Graduate School of the Agricultural snd Mechanical College of Texas in partial fulfillment... of the recpirements for the degree of MASTER OF SCIENCE May 1959 Major Sub/cot: Electrical ~ineering THE DESIGN OF A REGULATED VARIA33LE POWER SUPPLY FOR TRANSISTOR CIRCUITS A Thesis Oscar David Graham Approved as to style and content, by: Cha rman...

Graham, Oscar David

2012-06-07

88

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits  

Microsoft Academic Search

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at

Jian Gu

2003-01-01

89

A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors  

Microsoft Academic Search

This paper presents a circuit-compatible compact model for short channel length (5 nm~100 nm), quasi-ballistic single wall carbon nanotube field-effect transistors (CNFETs). For the first time, a universal circuit-compatible CNFET model was implemented with HSPICE. This model includes practical device non-idealities, e.g. the quantum confinement effects in both circumferential and channel length direction, the acoustical\\/optical phonon scattering in channel region

J. Deng; H.-S. P. Wong

2006-01-01

90

Transistor Sizing of Energy-DelayEfficient Circuits Paul I. Penzes, Mika Nystrom, Alain J. Martin  

E-print Network

Transistor Sizing of Energy-Delay­Efficient Circuits Paul I. P´enzes, Mika Nystr¨om, Alain J optimized for energy-delay efficiency, i.e., for optimal ¢¤£¦¥ where ¢ is the energy consumption-off between energy and delay. We propose a set of analytical formulas that closely ap- proximate the optimal

91

Sleep Transistor Sizing According to Circuit Speed, Silicon Area and Leakage Current in High-Performance Digital Circuit Modules  

NASA Astrophysics Data System (ADS)

It is proposed that the power supply of key circuit modules could be gated to achieve significant reductions of leakage current, with minimal costs to circuit speed and die area in 0.25, 0.18 and 0.07 µm technologies. This study describes an extension to power supply gating using body overdrive and gate underdrive, analysis techniques to predict leakage current and performance parameters, a procedure for optimization of the sleep transistor size and simulation results that demonstrate the accuracy of the analysis and advantages of the approach. A leakage current estimation technique has been studied using the Berkeley Predictive Technology Model Parameters. An estimation technique has been verified using ISCAS85 combinational Benchmark test circuits. Finally the optimization algorithm has been verified using these same benchmark test circuits.

Kucukkomurler, Ahmet; Garverick, Steven L.

92

Reusable vibration resistant integrated circuit mounting socket  

DOEpatents

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Evans, Craig N. (Irwin, PA)

1995-01-01

93

Carbon nanotube synthesis for integrated circuit interconnects  

E-print Network

Based on their properties, carbon nanotubes (CNTs) have been identified as ideal replacements for copper interconnects in integrated circuits given their higher current density, inertness, and higher resistance to ...

Nessim, Gilbert Daniel

2009-01-01

94

Printed inorganic transistors  

E-print Network

Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

Ridley, Brent (Brent Alan), 1974-

2003-01-01

95

The resonant gate transistor  

Microsoft Academic Search

A device is described which permits high-Qfrequency selection to be incorporated into silicon integrated circuits. It is essentially an electrostatically excited tuning fork employing field-effect transistor \\

HARVEY C. NATHANSON; WILLIAM E. NEWELL; ROBERT A. WICKSTROM

1967-01-01

96

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-28, NO. 5, MAY 1981390 C. Y. Wu and K. N. Lai, "A new integrated voltage-controlled  

E-print Network

. Takagi, and I. Teramoto, "Theory of negative resistance of junction field-effect transistors," IEEE J Organization (ERSO), ITRI. Rep. of China. His research activities have been in integrated-circuit technologies

Van Dooren, Paul

97

Integrated Circuit Stellar Magnitude Simulator  

ERIC Educational Resources Information Center

Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

Blackburn, James A.

1978-01-01

98

A History of the Continuously Innovative Analog Integrated Circuit  

Microsoft Academic Search

This article chronicles the invention and development of basic analog integrated circuits --Basic Analog Sub-Circuits, Analog Circuit Building Blocks, and Analog Circuit Functional Blocks -- that have become standard techniques for analog IC design. Ian Young

Ian Young

2007-01-01

99

Double Pass Transistor Logic for High Performance Wave Pipeline Circuits  

Microsoft Academic Search

Wave pipelining is a digital design technique that can be applied to combinational logic circuits to increase the throughput of the system without increasing the demand for storage space and power. The internal capacitances of the gates are used for storage. The gate library for wave pipelining should have input independent, functionality independent and load capacitance independent delays. Conventional static

Rajesh S. Parthasarathy; Ramalingam Sridhar

1998-01-01

100

\\\\Proc. IEEE 2004 Int. Conference on MicroelectronicTest Structures, Vol 17, March 2004. 127 A New Test Circuit for the Matching Characterization of npn Bipolar Transistors  

E-print Network

.3 A New Test Circuit for the Matching Characterization of npn Bipolar Transistors Jan Einfeld", Ulrich is presented for the mismatch characterization of npn bipolar transistors. The macro contains a CMOS circuit a force/sense method is employed to assure the high voltage accuracy requested for bipolar transistors

McNeill, John A.

101

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors  

NASA Astrophysics Data System (ADS)

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-01

102

A new family of very low-voltage analog circuits based on quasi-floating-gate transistors  

Microsoft Academic Search

A new family of very low-voltage analog circuits is introduced. These circuits do not show the GB degradation that characterizes other low-voltage approaches based on floating-gate transistors. The proposed approach is validated with experimental results of a CMOS mixer in 0.5-?m CMOS technology with 0.7-V input signal swing that operates on a single 0.8-V supply with transistor threshold voltages of

Jaime Ramírez-Angulo; Carlos A. Urquidi; Ramon González-Carvajal; Antonio Torralba; Antonio López-Martín

2003-01-01

103

Self-checking CMOS circuits using pass-transistor logic  

Microsoft Academic Search

This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0\\/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free.

Kanji Hirabayashi; Komukai Toshiba-cho

1991-01-01

104

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1989-01-01

105

Polysilicon photoconductor for integrated circuits  

DOEpatents

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

1990-01-01

106

Design methodologies for silicon photonic integrated circuits  

NASA Astrophysics Data System (ADS)

This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.

Chrostowski, Lukas; Flueckiger, Jonas; Lin, Charlie; Hochberg, Michael; Pond, James; Klein, Jackson; Ferguson, John; Cone, Chris

2014-03-01

107

Solution methods for very highly integrated circuits.  

SciTech Connect

While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator, both prominent world-class software tools.

Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

2010-12-01

108

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits  

NASA Technical Reports Server (NTRS)

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

1975-01-01

109

External electro-optic probing of millimeter-wave integrated circuits  

NASA Technical Reports Server (NTRS)

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.; Valdmanis, J. A.; Jackson, T. A.; Bhasin, K. B.; Romanofsky, Robert R.; Mourou, G. A.

1989-01-01

110

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits  

NASA Astrophysics Data System (ADS)

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

111

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits.  

PubMed

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Sporea, R A; Trainor, M J; Young, N D; Shannon, J M; Silva, S R P

2014-01-01

112

Package for integrated optic circuit and method  

DOEpatents

A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

1998-01-01

113

Package for integrated optic circuit and method  

DOEpatents

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

114

Test Structures For Bumpy Integrated Circuits  

NASA Technical Reports Server (NTRS)

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Buehler, Martin G.; Sayah, Hoshyar R.

1989-01-01

115

Photonics For Integrated Circuits And Communications  

NASA Astrophysics Data System (ADS)

This paper reviews recent progress in the development of integrated optical circuits involving the GaAs/AfGaAs double heterostructure system. Devices utilizing periodic corrugations or gratings are considered briefly, whereas alternative attempts to fabricate optical circuits by chemical etching are discussed in detail. The InGaAsP/InP system is also considered. Recent advances in processing techniques for optical integration, including reactive ion etching, are described, along with recent measurements that correlate waveguide loss with epitaxial layer uniformity.

Merz, J. L.; Yuan, Y. R.; Vawter, G. A.

1985-04-01

116

Transistor size optimization in the tailor layout system  

Microsoft Academic Search

This paper describes a combination transistor sizing\\/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound

David Marple

1989-01-01

117

Transistor Size Optimization in the Tailor Layout System  

Microsoft Academic Search

This paper describes a combination transistor sizing\\/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound

David Marple

1989-01-01

118

Imaging and evaluation of latch-up sites in CMOS Integrated Circuits  

E-print Network

Figure 1. CMOS inverter with parasitic bipolars. 2. SCR I-V characteristic. 3. The MOS transistor (n-type). 4. Enhancement MOSFET (a) and Depletion MOSFET (b). 5. N-tub formation. 6. Self aligned p-type source/drain formation (a), Self aligned n... Integrated circuits (VLSI) have become dominant in the iield of memory devices. One such type, the Complementary Metal Oxide Semiconductor (CMOS), uses both p-channel and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) on the same...

Antoniou, Nicholas

2012-06-07

119

Microwave integrated circuit for Josephson voltage standards  

NASA Technical Reports Server (NTRS)

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

Holdeman, L. B.; Toots, J.; Chang, C. C. (inventors)

1980-01-01

120

A CCD integrated circuit for transient recorders  

NASA Technical Reports Server (NTRS)

A 50 MHz CCD integrated circuit is described that was developed for use in transient analog signal recorders to sample and time expand transient signals. The integrated circuit achieves an effective 200 MHz sample rate by using four 32 stage peristaltic CCDs to sample the transient signal four times each clock period. Dual frequency, 4 phi clocking is used to sample and time expand the sampled data. The output signals of the four CCDs are multiplexed on chip into a single low frequency output data line. When operated with 50 MHz/165 KHz 4 phi clocks, this circuit has a 200 MHz sample rate, a record length of 640 nanoseconds, a time expansion factor of 303, and overall signal to noise ratio of 40:1. The signal to noise ratio is limited by fixed pattern noise of the four CCDs.

Balch, J. W.; Mcconaghy, C. F.

1976-01-01

121

Integrated Microphone with CMOS Circuits on a Single Chip  

NASA Astrophysics Data System (ADS)

A miniature diaphragm microphone having sensitivity to acoustic signals at the level of conversational speech has successfully been integrated with CMOS circuits on a single chip. The microphone is built on 1.4 ?m thick LPCVD silicon nitride diaphragm (2 x 2 mm^2 in size) with electrodes and ZnO piezoelectric film to transduce mechanical deformation into electrical charge. The CMOS amplifier put next to the microphone on a single chip has a gain of 491, flat in audio frequency range with 3-dB frequency being 18 kHz. The total number of transistors integrated in an amplifier is more than 300. The amplified sensitivity of the integrated microphone with a gain of 491 is 1.5 mV/mu bar when excited by sound waves at 1 kHz with the sensitivity variation from 100 Hz to 20 kHz being approximately 9 dB. The integrated microphone has been fabricated through an interactive joint process between a commercial CMOS foundry and a university lab. It is the first to demonstrate an integration of a microphone with CMOS circuits on a single chip. Theory of the integrated microphone has been developed through combining mechanics, piezoelectricity and circuit theory. Also developed are theoretical optimizations for sensitivity-bandwidth product and signal-to-noise ratio. A new processing technique to align features on the front side of a wafer to those on its backside has been developed for bulk micromachining. A tiny (30 mum-square and 1.6 ?m -thick) diaphragm serves as an alignment pattern. At the same time that the alignment diaphragm is made, much thicker, large-area diaphragms can be partially etched using "mesh" masking patterns in these area. The mesh-masking technique exploits the etch-rate differences between (100) and (111) planes to control the depths reached by etch pits in selected areas. The large, partially etched diaphragms (2 to 3 mm squares roughly 100 ?m thick) are sufficiently robust to survive subsequent IC-processing steps in a silicon-foundry environment. The thin alignment diaphragm can be processed through these steps because of its very small area. The partially etched diaphragms can be reduced to useful thicknesses in a final etch step after the circuits have been fabricated. This technique was successfully employed to fabricate microphones and on-chip CMOS circuits.

Kim, Eun Sok

1990-01-01

122

Annual report 2009 Integrated Devices & Circuits  

E-print Network

and related materials for bio-sensors. Fabricated in the KTH Electrum Laboratory in Kista (MyFab). VCSELs detection. Fabricated in the KTH Electrum Laboratory in Kista (MyFab). Silicon Device Technology PhotonicV or high temperatures > 300 °C Integrated circuits for harsh environments. Fabricated in the KTH Electrum

Lagergren, Jens

123

Towards an EMC roadmap for Integrated Circuits  

Microsoft Academic Search

The following document gathers a collection of information and trends about integrated circuit (IC) technology to build a tentative roadmap for ElectroMagnetic Compatibility (EMC) of ICs until year 2020, with focus on embedded system-on-chip (SoC) for automotive and consumer electronics applications.

M. Ramdani; E. Sicard; S. Ben Dhia; J. Catrysse

2008-01-01

124

Optoelectronic Integrated Circuits For Neural Networks  

NASA Technical Reports Server (NTRS)

Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

1990-01-01

125

Integrated Circuits in the Introductory Electronics Laboratory  

ERIC Educational Resources Information Center

Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

English, Thomas C.; Lind, David A.

1973-01-01

126

Modeling "Soft" Errors in Bipolar Integrated Circuits  

NASA Technical Reports Server (NTRS)

Mathematical models represent single-event upset in bipolar memory chips. Physics of single-event upset in integrated circuits discussed in theoretical paper. Pair of companion reports present mathematical models to predict critical charges for producing single-event upset in bipolar randomaccess memory (RAM) chips.

Zoutendyk, J.; Benumof, R.; Vonroos, O.

1985-01-01

127

Large-scale photonic integrated circuits  

Microsoft Academic Search

100-Gb\\/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb\\/s on a DWDM wavelength grid. Optical system performance results across a

R. Nagarajan; C. H. Joyner; J. S. Bostak; T. Butrie; A. G. Dentai; V. G. Dominic; P. W. Evans; M. Kato; M. Kauffman; D. J. H. Lambert; S. K. Mathis; A. Mathur; R. H. Miles; M. L. Mitchell; M. J. Missey; S. Murthy; A. C. Nilsson; F. H. Peters; S. C. Pennypacker; J. L. Pleumeekers; R. A. Salvatore; R. K. Schlenker; R. B. Taylor; Huan-Shang Tsai; M. F. Van Leeuwen; J. Webjorn; M. Ziari; D. Perkins; J. Singh; S. G. Grubb; M. S. Reffle; D. G. Mehuys; F. A. Kish; D. F. Welch

2005-01-01

128

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.  

PubMed

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42?GHz and a maximum oscillation frequency fMAX up to 50?GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9?GHz, fMAX~1?GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

129

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics  

NASA Astrophysics Data System (ADS)

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42?GHz and a maximum oscillation frequency fMAX up to 50?GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9?GHz, fMAX~1?GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-01

130

Data readout system utilizing photonic integrated circuit  

NASA Astrophysics Data System (ADS)

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Stopi?ski, S.; Malinowski, M.; Piramidowicz, R.; Smit, M. K.; Leijtens, X. J. M.

2013-10-01

131

Optimization of Integrated Transistors for Very High Frequency DC-DC Converters  

E-print Network

This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is ...

Sagneri, Anthony D.

132

Development of 3D integrated circuits for HEP  

Microsoft Academic Search

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

R. Yarema

2006-01-01

133

Development of 3D integrated circuits for HEP  

SciTech Connect

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

Yarema, R.; /Fermilab

2006-09-01

134

Implementation of a Statistical Model as Integrated Circuits.  

National Technical Information Service (NTIS)

This report discusses the implementation of a statistical model as an integrated analog circuit. Compared to a PC solution, an integrated circuit has the advantage of a potential for increased clock speed and increased parallel computation capability, les...

J. M. Oestby

1996-01-01

135

Viewing Integrated-Circuit Interconnections By SEM  

NASA Technical Reports Server (NTRS)

Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

1990-01-01

136

Progress in radiation immune thermionic integrated circuits  

SciTech Connect

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

Lynn, D.K.; McCormick, J.B. (comps.)

1985-08-01

137

Vacuum die attach for integrated circuits  

DOEpatents

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

Schmitt, Edward H. (Livermore, CA); Tuckerman, David B. (Livermore, CA)

1991-01-01

138

Vacuum die attach for integrated circuits  

DOEpatents

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

139

An integrator circuit in cerebellar cortex.  

PubMed

The brain builds dynamic models of the body and the outside world to predict the consequences of actions and stimuli. A well-known example is the oculomotor integrator, which anticipates the position-dependent elasticity forces acting on the eye ball by mathematically integrating over time oculomotor velocity commands. Many models of neural integration have been proposed, based on feedback excitation, lateral inhibition or intrinsic neuronal nonlinearities. We report here that a computational model of the cerebellar cortex, a structure thought to implement dynamic models, reveals a hitherto unrecognized integrator circuit. In this model, comprising Purkinje cells, molecular layer interneurons and parallel fibres, Purkinje cells were able to generate responses lasting more than 10 s, to which both neuronal and network mechanisms contributed. Activation of the somatic fast sodium current by subthreshold voltage fluctuations was able to maintain pulse-evoked graded persistent activity, whereas lateral inhibition among Purkinje cells via recurrent axon collaterals further prolonged the responses to step and sine wave stimulation. The responses of Purkinje cells decayed with a time-constant whose value depended on their baseline spike rate, with integration vanishing at low (< 1 per s) and high rates (> 30 per s). The model predicts that the apparently fast circuit of the cerebellar cortex may control the timing of slow processes without having to rely on sensory feedback. Thus, the cerebellar cortex may contain an adaptive temporal integrator, with the sensitivity of integration to the baseline spike rate offering a potential mechanism of plasticity of the response time-constant. PMID:23731348

Maex, Reinoud; Steuber, Volker

2013-09-01

140

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

141

General electromagnetic compatibility analysis for nonlinear microwave integrated circuits  

Microsoft Academic Search

The paper proposes a new solution to the standard electromagnetic compatibility problem for nonlinear RF\\/microwave integrated circuits. Radiation from the given circuit is first numerically analysed by means of electromagnetic simulation. Under the assumption of a uniform plane wave incident on the circuit, the reciprocity theorem is then used to characterize the linear subnetwork by a Norton equivalent circuit. Finally,

Vittorio Rizzoli; Alessandra Costanzo; Giuseppina Monti

2004-01-01

142

3D packaging for integrated circuit systems  

SciTech Connect

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

Chu, D.; Palmer, D.W. [eds.

1996-11-01

143

Tool For Tinning Integrated-Circuit Leads  

NASA Technical Reports Server (NTRS)

As many as eight flatpacks held. Tool made of fiberglass boards. Clamps row of flatpacks by their leads so leads on opposite side of packages dipped. After dipping, nuts on boards loosened, flatpacks turned around, nuts retightened, and untinned leads dipped. Strips of magnetic material grip leads of flatpacks (made of Kovar, magnetic iron/nickel/cobalt alloy) while boards repositioned. Micrometerlike screw used to adjust exposed width of magnetic strip to suit dimensions of flatpacks. Holds flatpack integrated circuits so leads tinned. Accommodates several flatpacks for simultaneous dipping of leads in molten solder. Adjusts to accept flatpacks in range of sizes.

Prosser, Gregory N.

1988-01-01

144

Novel Current-Scaling Current-Mirror Hydrogenated Amorphous Silicon Thin-Film Transistor Pixel Electrode Circuit with Cascade Capacitor  

E-print Network

Novel Current-Scaling Current-Mirror Hydrogenated Amorphous Silicon Thin-Film Transistor Pixel Electrode Circuit with Cascade Capacitor for Active-Matrix Organic Light-Emitting Devices Hojin LEE, Juhn S; accepted October 31, 2006; published online March 16, 2007) We proposed the hydrogenated amorphous silicon

Kanicki, Jerzy

145

Transistors: aerosol jet printed, sub-2 v complementary circuits constructed from p- and N-type electrolyte gated transistors (adv. Mater. 41/2014).  

PubMed

Printed low-voltage complementary inverters based on electrolyte gated transistors are demonstrated by C. D. Frisbie and co-workers on page 7032. The printed complementary inverters exhibit a gain of 18 and a power dissipation below 10 nW. Five-stage ring oscillators are achieved operating at 2 V with an oscillation frequency of 2.2 kHz. These printed circuits are promising for realizing low-voltage, printed electronics. PMID:25363882

Hong, Kihyon; Kim, Yong Hyun; Kim, Se Hyun; Xie, Wei; Xu, Weichao David; Kim, Chris H; Frisbie, C Daniel

2014-11-01

146

A test structure for the measurement and characterization of layout-induced transistor variation  

E-print Network

Transistor scaling has enabled us to design circuits with higher performance, lower cost, and higher density; billions of transistors can now be integrated onto a single die. However, this trend also magnifies the significance ...

Chang, Albert Hsu Ting

2009-01-01

147

A 1.5-V bootstrapped pass-transistor-based Manchester carry chain circuit suitable for implementing low-voltage carry look-ahead adders  

Microsoft Academic Search

This paper reports a 1.5-V bootstrapped pass-transistor-based Manchester carry chain circuit suitable for implementing low-voltage carry look-ahead adders. As verified by the experimentally measured data from a test chip fabricated using a 0.8-?m single-poly double-metal CMOS technology, with the bootstrapped pass-transistor-based Manchester carry chain circuit technique, the speed performance of a 16-bit carry look-ahead adder circuit is enhanced by 56%

J. H. Lou; J. B. Kuo

1998-01-01

148

Radiation effects on JFETs (Junction Field-Effect Transistors), MOSFETs, and dipolar transistors, as related to SSC circuit design  

NASA Astrophysics Data System (ADS)

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents less or equal to 1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier.

Kennedy, E. J.; Alley, G. T.; Britton, C. L., Jr.; Skubic, P. L.; Gray, B.; Wu, A.

1990-10-01

149

Fluidic microchemomechanical integrated circuits processing chemical information.  

PubMed

Lab-on-a-chip (LOC) technology has blossomed into a major new technology fundamentally influencing the sciences of life and nature. From a systemic point of view however, microfluidics is still in its infancy. Here, we present the concept of a microfluidic central processing unit (CPU) which shows remarkable similarities to early electronic Von Neumann microprocessors. It combines both control and execution units and, moreover, the complete power supply on a single chip and introduces the decision-making ability regarding chemical information into fluidic integrated circuits (ICs). As a consequence of this system concept, the ICs process chemical information completely in a self-controlled manner and energetically self-sustaining. The ICs are fabricated by layer-by-layer deposition of several overlapping layers based on different intrinsically active polymers. As examples we present two microchips carrying out long-term monitoring of critical parameters by around-the-clock sampling. PMID:23038405

Greiner, Rinaldo; Allerdissen, Merle; Voigt, Andreas; Richter, Andreas

2012-12-01

150

Amorphous InGaZnO Thin Film Transistor Current-Scaling Pixel Electrode Circuit for Active-Matrix Organic Light-Emitting Displays  

E-print Network

and operational voltages can be reduced when compare to the same circuit using hydrogenated amorphous silicon (a) thin film transistors (TFTs) or hydrogenated amorphous silicon (a-Si:H) TFTs. Both backplane and one capacitor voltage-programmed pixel circuit. The usage of such circuit requires the a-InGaZnO TFTs

Kanicki, Jerzy

151

Design for manufacturability with regular fabrics in digital integrated circuits  

E-print Network

Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the ...

Gazor, Mehdi (Seyed Mehdi)

2005-01-01

152

Current Mode Control Integrated Circuit with High Accuracy Current Sensing Circuit for Buck Converter  

Microsoft Academic Search

A current mode control integrated circuit with accuracy current sensing circuit ( CSC ) for buck converter is presented in this the proposed accurate integrated current sensed inductor with the internal ramp be used for DC-DC converter feedback proposed CSC doesn't need an op amp to implement, and has been fabricated with a standard 0.35 mum CMOS process. Simulation result

Chih-Jen HsuandY; Y. S. Lee

2007-01-01

153

Characterization of Schottky barrier carbon nanotube transistors and their applications to digital circuit design  

E-print Network

The difficulty in shrinking silicon transistors past a certain feature size has been acknowledged for years. Carbon nanotubes (CNTs) offer a technology with an exciting solution to the scaling issues of transistors and ...

Cline, Julia Van Meter, 1979-

2004-01-01

154

The Photon Transport Transistor: a Novel Device for Optoelectronic Integration.  

NASA Astrophysics Data System (ADS)

A theoretical model for a photon transport transistor was developed, based on a set of rate equations. At low bias conditions, the differential current gain is dominated by spontaneous emission of photons from the active region of the laser diode. It then decreases once stimulated emission becomes dominant and finally collapses to a small value at and above lasing threshold of the laser diode. The residual current gain above lasing is due to the absorption of scattered photons from the laser cavity. The photon transport transistors fabricated using both the AlGaAs/GaAs and the InP/InGaAs material systems were studied. In AlGaAs/GaAs material system, a maximum current gain of 0.84 was measured below lasing threshold. Above lasing, the current gain is only 0.13. Two methods were proposed to improve the current gain when biasing the device above lasing threshold. The first method was to coat the facets of the laser diode with highly reflectivity mirrors. After coating, the current gain was improved 2.7 times. In addition, the same technique can be used to extract the waveguide losses of a laser diode without requiring any optical calibration. The second method was to increase the optical coupling between the laser diode and the photodiode by merging the two devices. A measured maximum current gain of 1.35 and a calculated transit frequency of 1.9 GHz were obtained above lasing threshold when the photodiode was forward biased by 1 V. In addition, the output characteristics of the laser diode can be improved through photon recycling. This is the first device which is able to function as a laser diode and an electronic transistor under the same bias conditions. The first lattice-matched InP/InGaAs photon transport transistor was fabricated and characterized. This device consists of a multi-quantum well LED integrated on top of a photodiode. The center wavelength of the emission spectra of the LED is at 1.55 mm. The device fabricated has a voltage gain of 258, a current gain of 0.07 resulting a power gain of 18.1. In addition, it was demonstrated that the concept of this device is extendible to material systems other than AlGaAs/GaAs. (Abstract shortened by UMI.).

Chu, Ann-Kuo

155

Material selection and nanofabrication techniques for electronic photonic integrated circuits  

E-print Network

Electronic-photonic integrated circuits have the potential to circumvent many of the performance bottlenecks of electronics. To achieve the full benefits of integrating photonics with electronics it is generally believed ...

Holzwarth, Charles W., III (Charles Willett)

2009-01-01

156

Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section  

E-print Network

Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section Anthony E. Parker are collaborating to establish a local GaAs digital integrated design and fabrication capability. Gallium Arsenide Laboratory for Communication Science and Engineering, Sydney University Electrical Engineering Gallium

157

Characterization and Modeling of TSV Based 3-D Integrated Circuits  

E-print Network

Characterization and Modeling of TSV Based 3-D Integrated Circuits Speaker: Prof. Ioannis Savidis's research interests include emerging integrated circuit technologies, as well as analysis, modeling) based 3-D technologies. My work on the electrical modeling of TSVs culminated in the development

158

Aerosol jet printed, sub-2 v complementary circuits constructed from p- and N-type electrolyte gated transistors.  

PubMed

Printed low-voltage complementary inverters based on electrolyte gated transistors are demonstrated. The printed complementary inverters showed gain of 18 and power dissipation below 10 nW. 5-stage ring oscillators operate at 2 V with an oscillation frequency of 2.2 kHz, corresponding to stage delays of less than 50 ?s. The printed circuits exhibit good stability under continuous dynamic operation. PMID:24975133

Hong, Kihyon; Kim, Yong Hyun; Kim, Se Hyun; Xie, Wei; Xu, Weichao David; Kim, Chris H; Frisbie, C Daniel

2014-11-01

159

Pentacene integrated thin-film transistors and circuits  

E-print Network

Organic semiconductors offer the potential of large-area, mechanically flexible electronics due to their low processing temperatures. We have developed a near-room-temperature (< 95°C) process flow to fabricate pentacene ...

Nausieda, Ivan Alexander

2009-01-01

160

Optimization of transistor design including large signal device/circuit interactions at extremely high frequencies (20-100+GHz)  

NASA Technical Reports Server (NTRS)

Transistor design for extremely high frequency applications requires consideration of the interaction between the device and the circuit to which it is connected. Traditional analytical transistor models are to approximate at some of these frequencies and may not account for variations of dopants and semiconductor materials (especially some of the newer materials) within the device. Physically based models of device performance are required. These are based on coupled systems of partial differential equations and typically require 20 minutes of Cray computer time for a single AC operating point. A technique is presented to extract parameters from a few partial differential equation solutions for the device to create a nonlinear equivalent circuit model which runs in approximately 1 second of personal computer time. This nonlinear equivalent circuit model accurately replicates the contact current properties of the device as computed by the partial differential solver on which it is based. Using the nonlinear equivalent circuit model of the device, optimization of systems design can be performed based on device/circuit interactions.

Levy, Ralph; Grubin, H. L.

1991-01-01

161

Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion  

Microsoft Academic Search

A pixel array readout integrated circuit (ROIC) containing per-pixel analog-to-digital conversion (ADC) and digital-to- analog conversion (DAC) for infrared detectors is presented with design and test result details. Fabricated in a standard 0.35 micron, 3.3 volt CMOS technology. the prototype consists of a linear array of 64 pixels, containing over 100 transistors per 30 by 30 micron pixel. The 8-bit

Stuart Kleinfelder; Alison Hottes; R. Fabian W. Pease

2000-01-01

162

Fluoropolymer coatings for improved carbon nanotube transistor device and circuit performance  

NASA Astrophysics Data System (ADS)

We report on the marked improvements in key device characteristics of single walled carbon nanotube (SWCNT) field-effect transistors (FETs) by coating the active semiconductor with a fluoropolymer layer such as poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE). The observed improvements include: (i) A reduction in off-current by about an order of magnitude, (ii) a significant reduction in the variation of threshold voltage, and (iii) a reduction in bias stress-related instability and hysteresis present in device characteristics. These favorable changes in device characteristics also enhance circuit performance and the oscillation amplitude, oscillation frequency, and increase the yield of printed complementary 5-stage ring oscillators. The origins of these improvements are explored by exposing SWCNT FETs to a number of vapor phase polar molecules which produce similar effects on the FET characteristics as the PVDF-TrFE. Coating of the active SWCNT semiconductor layer with a fluoropolymer will be advantageous for the adoption of SWCNT FETs in a variety of printed electronics applications.

Jang, Seonpil; Kim, Bongjun; Geier, Michael L.; Prabhumirashi, Pradyumna L.; Hersam, Mark C.; Dodabalapur, Ananth

2014-09-01

163

Optoelectronic integration of a GaAs/AlGaAs Bistable Field Effect Transistor (BISFET) and LED  

NASA Astrophysics Data System (ADS)

The bistable field effect transistor (BISFET) is a novel inversion-channel switching device exhibiting abrupt current transitions and hysteresis in its output characteristics. The semiconductor structure of the BISFET is compatible with a range of electronic and optoelectronic devices. Integration of a BISFET with a LED is reported. Both devices have been implemented on a single semiconductor substrate using a single fabrication sequence. The BISFET is used to current-drive the LED. Abrupt transitions and hysteresis are seen in the optical output from the circuit in the range of gate voltage from 1.75 V to 1.9 V.

Ojha, J. J.; Simmons, J. G.; Mand, R. S.; Spring Thorpe, A. J.

1994-02-01

164

Basic Study on the Radio Frequency Characteristics of the Transmission Lines Employing Periodically Perforated Ground Metal on GaAs Monolithic Microwave Integrated Circuit and Their Equivalent Ciruits  

NASA Astrophysics Data System (ADS)

In this work, basic characteristics of transmission line employing periodically perforated ground metal (PPGM) were investigated using theoretical and experimental analysis. Concretely, bandwidth and impedance were investigated using theoretical analysis, and wavelength and effective permittivity were extracted from experimental results. In addition, insertion loss and isolation characteristics were investigated using equivalent circuit analysis. For simplification of design process, equivalent circuits for the PPGM cell were extracted, and all circuit parameters were expressed by closed-form equation. Above results indicate that the transmission line employing PPGM is a promising candidate for a development of matching and passive elements on monolithic microwave integrated circuit (MMIC) including wireless communication circuit and compound semiconducting devices such as high electron mobility transistor (HEMT), diamond field effect transistor (FET) and light emitting diode (LED).

Yun, Young; Ju, Jeong-Gab; Kim, Hong Seung

2011-01-01

165

Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration  

E-print Network

Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring ...

Sredojevi?, Ranko Radovin.

2008-01-01

166

Organic electronics integration technology and logic circuits  

NASA Astrophysics Data System (ADS)

Organic transistor technology has been the subject of intense research in the last decade paving the way for industrialization of organic electronics applications characterized by low fabrication costs, additive manufacturing processes at low-energy, high flexibility and application versatility. A dedicated technology platform has been developed at ST and fully characterized, which is devoted to the manufacturing of all-organic transistor devices with sub-micron feature size as multilayered structures, obtained through a sequential combination of deposition from solution and patterning steps through stamps. The design and manufacturing platform is actually being assessed through the development of the first all-organic 'reduced complexity' microprocessor. An outline of the architecture and major building blocks will be presented.

Occhipinti, L.; La Rosa, M.; Rizzotto, G.

2008-08-01

167

The model and optimisation of structure of power integrated pulse transistor (in Ukrainian)  

NASA Astrophysics Data System (ADS)

A model describing the mode of transition to the ohm quasi--saturation in the collector of power integrated bipolar transistors the special features of which is the irregularity of distributed resistance of the collector part, is proposed. The questions of optimisation of topology of power integrated pulse transistors that work in the mode of great relative pulse duration of short pulses with insignificant heat release are considered. The optimisation allows to make a choice of the construction and determine the geometrical dimensions of integrated transistor structure which is characterized by the minimum values of output capacity and resistance of the collector.

Smerklo, L. M.

168

A Lithographic Process for Integrated Organic Field-Effect Transistors  

Microsoft Academic Search

This paper reports a photolithographic process for fabricating organic field-effect transistors which provides two layers of metal with arbitrary via placement, and optionally allows for subtractive lithographic patterning of the transistor active layer. The demonstrated pentacene transistors have a field-effect mobility of 0.1±0.05 cm2\\/(V·s). Parylene-C is used both as the gate dielectric and an encapsulation layer which allows for subtractive

Ioannis Kymissis; Akintunde Ibitayo Akinwande; Vladimir Bulovic

2005-01-01

169

Nanophotonic integrated circuits from nanoresonators grown on silicon  

NASA Astrophysics Data System (ADS)

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore’s law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D.; Li, Kun; Chang-Hasnain, Connie

2014-07-01

170

Experimental determination of single-event upset (SEU) as a function of collected charge in bipolar integrated circuits  

NASA Technical Reports Server (NTRS)

Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.

Zoutendyk, J. A.; Malone, C. J.; Smith, L. S.

1984-01-01

171

Photonic Interconnections Integrated circuits (ICs) are tradi  

E-print Network

tronics may be able to operate at liquid nitrogen temperatures, includ ing circuits based on new "high if connections are made via poor ther mal conductors such as glass, rather than excellent conductors

Fossum, Eric R.

172

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits  

PubMed Central

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal?oxide?semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

173

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits.  

PubMed

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at V(DD) = 80 V (70% of 1/2V(DD)) and a gain of 85. Additionally, robust SWNT complementary metal-oxide-semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C-K; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-04-01

174

Reduced 30% scanning time 3D multiplexer integrated circuit applied to large array format 20KHZ frequency inkjet print heads  

E-print Network

Enhancement of the number and array density of nozzles within an inkjet head chip is one of the keys to raise the printing speed and printing resolutions. However, traditional 2D architecture of driving circuits can not meet the requirement for high scanning speed and low data accessing points when nozzle numbers greater than 1000. This paper proposes a novel architecture of high-selection-speed three-dimensional data registration for inkjet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array inkjet printheads with nozzles numbering more than 1000. This IC (Integrated Circuit) architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection (S), address (A), and power supply (P), are employed toge...

Liou, J -C

2008-01-01

175

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess  

E-print Network

circuit. The bridge fault transforms the two gates for which the bridged wires are outputs into a singleBridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault

Larrabee, Tracy

176

35 GHz integrated circuit rectifying antenna with 33 percent efficiency  

NASA Technical Reports Server (NTRS)

A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

Yoo, T.-W.; Chang, K.

1991-01-01

177

LEC GaAs for integrated circuit applications  

NASA Technical Reports Server (NTRS)

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

178

Design automation and analysis of three-dimensional integrated circuits  

E-print Network

This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical ...

Das, Shamik, 1977-

2004-01-01

179

Performance Trend in Three-Dimensional Integrated Circuits Author list  

E-print Network

Performance Trend in Three-Dimensional Integrated Circuits Author list Affiliation xxx@xxx ABSTRACT performance, 3D clock skew, power 1. INTRODUCTION Interconnect dominants the system performance in deep sub

Davis, Rhett

180

Research Centers Center for Integrated Circuits and Systems ......................................................................................... RC.1  

E-print Network

Research Centers Center for Integrated Circuits and Systems ......................................................................................... RC.1 Intelligent Transporation Research Center@MIT ....................................................................................................................................... RC.4 #12;RC.1 MICROSYSTEMS TECHNOLOGY LABORATORIES ANNUAL RESEARCH REPORT 2009 ReseaRCh Cente

Reif, Rafael

181

Advanced modeling of planarization processes for integrated circuit fabrication  

E-print Network

Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing ...

Fan, Wei, Ph. D. Massachusetts Institute of Technology

2012-01-01

182

Fast, automated thermal simulation of three-dimensional integrated circuits  

Microsoft Academic Search

Three-dimensional (3D) stacked integrated circuits (ICs) can significantly improve circuit performance and offer the promise of integrating various technologies (memory, logic, RF, mixed-signal, optoelectronics) within a single block. Lack of 3D design tools and heat dissipation from vertically stacked multiple layers are the crucial problems in their development. To address these issues, CFD Research Corporation (CFDRC) is developing methodologies and

Patrick Wilkerson; Ashok Raman; Marek Turowski

2004-01-01

183

Advanced tools for integrated circuit design  

E-print Network

of the mathematical approaches used are described in the following. On- Target Design This approach was used by Taguchi for circuit quality improvement. The main idea behind his approach is the use of the "expected loss" function. This would give a measure... of the mathematical approaches used are described in the following. On- Target Design This approach was used by Taguchi for circuit quality improvement. The main idea behind his approach is the use of the "expected loss" function. This would give a measure...

Dubagunta, Sai Kumar

2012-06-07

184

A new aSi:H thin-film transistor pixel circuit for active-matrix organic light-emitting diodes  

Microsoft Academic Search

We propose a new pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), composed of three switching and one driving TFT, for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage source method. The circuit simulation results based on the measured threshold voltage shift of a-Si:H TFTs by gate-bias stress indicate that this circuit compensates for the threshold voltage shifts

Joon-Chul Goh; Jin Jang; Kyu-Sik Cho; Choong-Ki Kim

2003-01-01

185

Circuit-level input integration in bacterial gene regulation.  

PubMed

Gene regulatory circuits can receive multiple simultaneous inputs, which can enter the system through different locations. It is thus necessary to establish how these genetic circuits integrate multiple inputs as a function of their relative entry points. Here, we use the dynamic circuit regulating competence for DNA uptake in Bacillus subtilis as a model system to investigate this issue. Specifically, we map the response of single cells in vivo to a combination of (i) a chemical signal controlling the constitutive expression of key competence genes, and (ii) a genetic perturbation in the form of copy number variation of one of these genes, which mimics the level of stress signals sensed by the bacteria. Quantitative time-lapse fluorescence microscopy shows that a variety of dynamical behaviors can be reached by the combination of the two inputs. Additionally, the integration depends strongly on the relative locations where the two perturbations enter the circuit. Specifically, when the two inputs act upon different circuit elements, their integration generates novel dynamical behavior, whereas inputs affecting the same element do not. An in silico bidimensional bifurcation analysis of a mathematical model of the circuit offers good quantitative agreement with the experimental observations, and sheds light on the dynamical mechanisms leading to the different integrated responses exhibited by the gene regulatory circuit. PMID:23572583

Espinar, Lorena; Dies, Marta; Cagatay, Tolga; Süel, Gürol M; Garcia-Ojalvo, Jordi

2013-04-23

186

0.5 V ANALOG INTEGRATED CIRCUITS  

Microsoft Academic Search

Semiconductor technology scaling has enabled function density increases and cost reductions by orders of magnitudes, but for shrinking device sizes the operating voltages have to be reduced. As we move into the nanoscale semiconductor technologies, power supply voltages well below 1 V are projected. The design of MOS analog circuits operating from a power supply voltage of 0.5 V is

Peter Kinget; Shouri Chatterjee; Yannis Tsividis

187

Adaptive filtering using neural network integrated circuits  

Microsoft Academic Search

How analog neural network techniques can be used to implement efficient adaptive filtering as a replacement to current digital implementations is discussed. Several experimental circuits and systems for analog adaptive signal processing are presented. An approach to vector quantization using these systems is discussed. The fabrication of a decision-directed filter using neural network techniques to improve the frequencies at which

Richard Kaul; Steven Bibyk; Mohammed Ismail; Monty Andro

1990-01-01

188

Inverted process for graphene integrated circuits fabrication  

NASA Astrophysics Data System (ADS)

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB.CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB. Electronic supplementary information (ESI) available: Optical images and Raman spectrum of graphene, AFM image of the buried gate stack. See DOI: 10.1039/c3nr06904d

Lv, Hongming; Wu, Huaqiang; Liu, Jinbiao; Huang, Can; Li, Junfeng; Yu, Jiahan; Niu, Jiebin; Xu, Qiuxia; Yu, Zhiping; Qian, He

2014-05-01

189

Integration of room temperature single electron transistor with CMOS subsystem  

NASA Astrophysics Data System (ADS)

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10--18 J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash-Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt. These two parameters lead to the tunneling rate of an electron in the SET device, Gamma. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Cheam, Daw Don

190

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model  

NASA Astrophysics Data System (ADS)

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

191

Current gain in bipolar transistors with a field plate over the base surface  

E-print Network

Current gain in bipolar transistors with a field plate over the base surface V. Anantharam and K.N. Bhat Indexing terms: Bipolar transistors, Analogue simulation, Carrier lifetime, Minority carriers. Abstract: Vertical n-p-n and lateral p-n-p transistor structures of an integrated circuit are studied using

Anantharam, Venkat

192

Inkjet-printing-based soft-etching technique for high-speed polymer ambipolar integrated circuits.  

PubMed

Here, we report the so-called soft-etching process based on an inkjet-printing technique for realizing high-performance printed and flexible organic electronic circuits with conjugated polymer semiconductors. The soft-etching process consists of selective etching of the gate made of a dielectric polymer and deposition of another gate dielectric layer. The method enables the use of a more desirable polymer dielectric layer for the p-channel and n-channel organic field-effect transistors (OFETs) in complementary integrated circuits. We fabricated high-performance ambipolar complementary inverters and ring oscillators (ROs) using poly([N,N'-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5'-(2,2'-bithiophene)) (P(NDI2OD-T2)) as the active layer as well as poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and polystyrene ((PS)/P(VDF-TrFE)) as dielectric materials for the p-channel (pull-up transistor) and n-channel (pull-down transistor) OFETs, respectively. The PS dielectric polymer was selectively etched by inkjetting of n-butyl acetate as an orthogonal solvent for P(NDI2OD-T2). Employing this methodology, the five-stage ambipolar ROs with P(NDI2OD-T2) exhibited an oscillation frequency of ?16.7 kHz, which was much higher than that of non-soft-etched ROs with a single dielectric layer (P(VDF-TrFE); ?3 kHz). PMID:24219097

Khim, Dongyoon; Baeg, Kang-Jun; Kang, Minji; Lee, Seung-Hoon; Kim, Nam-Koo; Kim, Jihong; Lee, Geon-Woong; Liu, Chuan; Kim, Dong-Yu; Noh, Yong-Young

2013-12-11

193

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses  

NASA Astrophysics Data System (ADS)

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

194

Subsurface microscopy of interconnect layers of an integrated circuit  

E-print Network

of a polished silicon substrate effectively transforms the NAIL and the planar sample into an integrated SIL angles [1]. NA- increasing lens (NAIL) microscopy has been developed as an application of the SIL technique to subsurface imaging of integrated circuits (ICs) [2]. A Si NAIL placed on the backside

195

Simulation of proton-induced energy deposition in integrated circuits  

NASA Technical Reports Server (NTRS)

A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

Fernald, Kenneth W.; Kerns, Sherra E.

1988-01-01

196

Pixel-Level Digital-to-Analog Conversion Scheme with Compensation of Thin-Film-Transistor Variations for Compact Integrated Data Drivers of Active Matrix Organic Light Emitting Diodes  

Microsoft Academic Search

The previous pixel-level digital-to-analog-conversion (DAC) scheme that implements a part of a DAC in a pixel circuit turned out to be very efficient for reducing the peripheral area of an integrated data driver fabricated with low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). However, how the pixel-level DAC can be compatible with the existing pixel circuits including compensation schemes of TFT

Tae-Wook Kim; Sang-Gyu Park; Byong-Deok Choi

2011-01-01

197

Dual threshold voltage organic thin-film transistor technology  

E-print Network

A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The nearroom-temperature (<; 95 °C) process produces ...

Nausieda, Ivan A.

198

technologie transistor.  

E-print Network

�léments de technologie Les circuits intégrées c-MOS. L'élément de base est le transistor. Deux types de transistors complémentaires n-MOS et p-MOS. Avantages des c-MOS : #21; très grande intégration des impuretés. - plus récement : bombardement ionique. 2 #12; Transistor n-MOS (Metal

Hivert, Florent

199

Development of integrated thermionic circuits for high-temperature applications  

NASA Technical Reports Server (NTRS)

Integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 C are studied. A set of practical design and performance equations is demonstrated. Experimental results are discussed in which both devices and simple circuits were successfully operated in 5000 C environments for extended periods. It is suggested that ITC's may become an important technology for high temperature instrumentation and control systems in geothermal and other high temperature environments.

Mccormick, J. B.; Wilde, D.; Depp, S.; Hamilton, D. J.; Kerwin, W.; Derouin, C.; Roybal, L.; Wooley, R.

1981-01-01

200

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

2012-06-07

201

Development of integrated thermionic circuits for high-temperature applications  

SciTech Connect

This report describes a class of microminiature, thin film devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500/sup 0/C. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time (greater than 11,000 hours).

McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.

1981-01-01

202

An MOS transistor model for RF IC design valid in all regions of operation  

Microsoft Academic Search

This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic

Christian Enz

2002-01-01

203

Photonic integrated circuits based on silica and polymer PLC  

NASA Astrophysics Data System (ADS)

Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

Izuhara, T.; Fujita, J.; Gerhardt, R.; Sui, B.; Lin, W.; Grek, B.

2013-03-01

204

Publish date: 06/27/2011 ECE 4310: Introduction to Very Large Scale Integrated Circuit Design  

E-print Network

Circuits - 3 hours Circuit Layout - 3 hours Device Modeling - 6 hours Circuit Simulation - 6 hours BasicPublish date: 06/27/2011 ECE 4310: Introduction to Very Large Scale Integrated Circuit Design: B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001. Catalog description: ECE

Gelfond, Michael

205

Design and operation of microelectrochemical gates and integrated circuits.  

PubMed

Here we report a simple design philosophy, based on the principles of bipolar electrochemistry, for the operation of microelectrochemical integrated circuits. The inputs for these systems are simple voltage sources, but because they do not require much power they could be activated by chemical or biological reactions. Device output is an optical signal arising from electrogenerated chemiluminescence. Individual microelectrochemical logic gates are described first, and then multiple logic circuits are integrated into a single microfluidic channel to yield an integrated circuit that can perform parallel logic functions. AND, OR, NOR, and NAND gates are described. Eventually, systems such as those described here could provide on-chip data processing functions for lab-on-a-chip devices. PMID:20942419

Chang, Byoung-Yong; Crooks, John A; Chow, Kwok-Fan; Mavré, François; Crooks, Richard M

2010-11-01

206

Polariton Condensate Transistor Switch  

E-print Network

A polariton condensate transistor switch is realized through optical excitation of a microcavity ridge with two beams. The ballistically ejected polaritons from a condensate formed at the source are gated using the 20 times weaker second beam to switch on and off the flux of polaritons. In the absence of the gate beam the small built-in detuning creates potential landscape in which ejected polaritons are channelled toward the end of the ridge where they condense. The low loss photon-like propagation combined with strong nonlinearities associated with their excitonic component makes polariton based transistors particularly attractive for the implementation of all-optical integrated circuits.

Gao, T; Liew, T C H; Tsintzos, S I; Stavrinidis, G; Deligeorgis, G; Hatzopoulos, Z; Savvidis, P G

2012-01-01

207

Majority carrier type conversion in solution-processed organic transistors and flexible complementary logic circuits  

NASA Astrophysics Data System (ADS)

We report on the realization of high performance solution-processed ambipolar organic transistors based on a quinoidal oligothiophene derivative. The devices show hole and electron field-effect mobilities in air as high as 0.1 and 0.006 cm2 V-1 s-1, respectively, and can be converted from ambipolar p-type dominant to n-type transistors by thermal annealing. The conversion of the majority carrier type is assigned to strong variations in molecular packing. The demonstration of complementary flexible inverters suggests an effective strategy for patterning lateral pn-bipolar structures in solution-processed thin films made from a monolithic ambipolar organic semiconductor.

Ribierre, J. C.; Watanabe, S.; Matsumoto, M.; Muto, T.; Aoyama, T.

2010-02-01

208

3D circuit integration for Vertex and other detectors  

SciTech Connect

High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

Yarema, Ray; /Fermilab

2007-09-01

209

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks  

Microsoft Academic Search

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The

Zhanping Chen; Mark Johnson; Liqiong Wei; Kaushik Roy

1998-01-01

210

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.  

PubMed

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits. PMID:19086836

Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

2009-01-01

211

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.  

PubMed

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries. PMID:24567478

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

212

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design and Application Considerations for  

E-print Network

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design, and Seshadri Subbanna, Member, IEEE Invited Paper Abstract--SiGe HBT transistors achieving over 200 GHz and MAX--BiCMOS integrated circuits, bipolar transistors, heterojunctions, semiconductor devices. I. INTRODUCTION BIPOLAR

Rieh, Jae-Sung

213

Theory and Practice of "Striping" for Improved ON/OFF Ratio in Carbon Nanonet Thin Film Transistors  

E-print Network

Theory and Practice of "Striping" for Improved ON/OFF Ratio in Carbon Nanonet Thin Film Transistors nanotubes (CNTs) relevant for large-scale integrated circuits based on CNT-nanonet transistors is proposed the ON/OFF ratio of CNT-nanonet transistors; however, the corresponding degradation in ON-current has

Rogers, John A.

214

MICROX-an all-silicon technology for monolithic microwave integrated circuits  

Microsoft Academic Search

An improved silicon-on-insulator (SOI) approach offers devices and circuits operating to 10 GHz by providing formerly unattainable capabilities in bulk silicon: reduced junction-to-substrate capacitances in FETs and bipolar transistors, inherent electrical isolation between devices, and low-loss microstrip lines. The concept, called MICROX (patent pending), is based on the SIMOX process, but uses very-high-resistivity (typically>10000 ?-cm) silicon substrates, MICROX NMOS transistors

Maurice H. Hanes; Anant K. Agarwal; T. W. O'Keeffe; H. M. Hobgood; John R. Szedon; T. J. Smith; R. R. Siergiej; Paul G. McMullin; H. C. Nathanson; Michael C. Driver; R. Noel Thomas

1993-01-01

215

Modeling of opto-electronics in complex photonic integrated circuits  

NASA Astrophysics Data System (ADS)

This work addresses a versatile modeling of complex photonic integrated circuits (PICs) including optical and electrical sub-elements. We introduce a new family of electrical elements, together with a novel electronic-photonic co-design, that complements current capabilities of photonic circuit simulators. This is illustrated with the modeling of complex electric circuits contained in photonic devices. Simulations of the interaction between electrical and optical parts allow the analysis of unwanted effects such as reflections due to impedance mismatching, as well as the optimization of the PIC as a whole. We illustrate the functionalities of our approach through application examples. As a use case, we present a model of the electrical driver for a monolithically-integrated InP transmitter developed in frame of the European research project MIRTHE and the analysis of the driver and the EA-Modulator interplay.

Arellano, C.; Mingaleev, S.; Koltchanov, I.; Richter, A.

2014-03-01

216

Thin film transistors for displays on plastic substrates  

Microsoft Academic Search

We have successfully made thin film transistors on transparent, flexible polymer substrates. These transistors have electrical properties suitable for driving the pixels in active matrix liquid crystal displays and also for building integrated row driver circuits. The devices are fabricated on polyethylene naphthalate using a low temperature CdSe process at a maximum temperature of 150°C, by evaporation and radio frequency

M. J Lee; C. P Judge; S. W Wright

2000-01-01

217

Method for double-sided processing of thin film transistors  

DOEpatents

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Yuan, Hao-Chih (Madison, WI); Wang, Guogong (Madison, WI); Eriksson, Mark A. (Madison, WI); Evans, Paul G. (Madison, WI); Lagally, Max G. (Madison, WI); Ma, Zhenqiang (Middleton, WI)

2008-04-08

218

Integrated Circuit Security Techniques Using Variable Supply Voltage  

E-print Network

voltage based gate-level characterization (GLC). Our GLC scheme is capable of characterizing both and Protection--Physical Security General Terms Security Keywords Gate-level characterization, integrated circuit without fee provided that copies are not made or distributed for profit or commercial advantage

Potkonjak, Miodrag

219

1998 technology roadmap for integrated circuits used in critical applications  

SciTech Connect

Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

Dellin, T.A.

1998-09-01

220

Integrated circuits: Resistless processing simplifies production and cuts costs  

Microsoft Academic Search

Reducing the complexity and cost of producing deep-submicrometer integrated circuits (IC's) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the

K. Weiner

1993-01-01

221

Innovative packaging concepts for ultra thin integrated circuits  

Microsoft Academic Search

The increasing demand on miniaturized and flat packaging technologies is driven by the trend towards small and portable electronic systems. Due to the requirements of modern Ball Grid Arrays, Smart Cards or Chip Size Packages thickness of integrated circuits has been reduced considerably compared with original wafer thickness. Driven by this evolution, the Fraunhofer Institute for Reliability and Microintegration has

Gerhard Klink; Michael Feil; Frank Ansorge; Rolf Aschenbrenner; Herbert Reichl

2001-01-01

222

An integrated circuit/packet switched videoconferencing system  

SciTech Connect

The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible videoconferencing system for use by high energy physics collaborations and others wishing to use videoconferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of videoconferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEP`s needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Videoconferencing Using PAckets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched videoconferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet videoconferencing interface. Augmentation is centered in another subsystem called MSB (Multiport multisession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system.

Kippenhan, H.A. Jr.; Lidinsky, W.P.; Roediger, G.A. [Fermi National Accelerator Lab., Batavia, IL (United States); Watts, T.A. [Rutgers Univ., Piscataway, NJ (United States). Busch Campus

1995-11-01

223

DNA chips --Integrated Chemical Circuits for DNADiagnosis and DNA computers  

E-print Network

DNA chips -- Integrated Chemical Circuits for DNADiagnosis and DNA computers Akira Suyama, Associate Professor Institute of Physics, Graduate School of Arts and Sciences, The University of Tokyo DNA chips are si l i con­ or glass­based smal l surfaces on which many DNA ol i gonuc l eotides are i

Hagiya, Masami

224

Automated failure population creation for validating integrated circuit diagnosis methods  

Microsoft Academic Search

Integrated circuit (IC) diagnosis typically analyzes failed chips by reasoning about their responses to test patterns to deduce what has gone wrong. Current trends use diagnosis as the first step in extracting valuable information from a large population of failing ICs that include, for example, design-feature failure rates and defect-occurrence statistics. However, it is difficult to examine the accuracy of

Wing Chiu Tam; Osei Poku

2009-01-01

225

Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits  

E-print Network

Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits Aris Christou Materials of the failure rate of each component due to interaction effects of the failed components. The Monte Carlo failure rates become nonconstant. The Monte Carlo technique is an appropriate methodology used to treat

Rubloff, Gary W.

226

Macroelectronic Integrated Circuits Using High-Performance Separated  

E-print Network

and ring-oscillators.9 13 Thin-films of single-walled carbon nano- tubes which possess extraordinary conduc-film tran- sistors (TFTs), such as amorphous silicon22 24 or organic materials,25 28 nano- tube thinMacroelectronic Integrated Circuits Using High-Performance Separated Carbon Nanotube Thin

Zhou, Chongwu

227

Integrated Circuit White Space Redistribution for Temperature Optimization  

E-print Network

Integrated Circuit White Space Redistribution for Temperature Optimization Yuankai Chen , Hai Zhou thermal problems. One remedy is to redistribute white space during floorplanning. In this paper, we propose a two-phase algorithm to redistribute white space. In the first phase, the lateral heat flow white

Zhou, Hai

228

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits  

NASA Astrophysics Data System (ADS)

In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60×180nm2 achieves a large change in resistance of 3.52k? (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

Iga, Fumitaka; Kamiyanagi, Masashi; Ikeda, Shoji; Miura, Katsuya; Hayakawa, Jun; Hasegawa, Haruhiro; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

229

Radiation damage in MOS integrated circuits, Part 1  

NASA Technical Reports Server (NTRS)

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Danchenko, V.

1971-01-01

230

Automated Cell Synthesis of Analog Integrated Circuit Layout Anasyn.  

NASA Astrophysics Data System (ADS)

This thesis describes a novel model to automate cell generation for the design of analog integrated circuits and the conclusions about important features that such automation should include. This research represents the first attempt to address this problem by analyzing relevant issues of what constitutes an analog cell and how a technique can be implemented to generate these cells automatically. Our motivation for doing this is the critical limitations to circuit performance which arise from cell design. This thesis defines unique construction properties for the layout of some commonly used analog circuit topologies or cells. This thesis defines the physical layout of analog circuit cells beyond simple geometrical description. Each cell is an independent object that can be interfaced and communicated with. This thesis has extended the concept of an analog cell even further by incorporating synthesis rules into the cell definition. These rules are used to dynamically construct the optimized layout that will satisfy many of the options encountered in actual analog circuit design such as area, matching, tolerance, element rationing and parasitic components. This model can construct complex geometric shapes such as common-centroids, waffles, interdigitated, cascode etc. that are optimized at device level with the precise models for parasitic components. Furthermore, Object-Oriented implementation used in this thesis allow for easy integration of this work into other CAD tools. To demonstrate the feasibility and correctness of the ideas described in this thesis, a CAD tool ANASYN has been written. To test and demonstrate the utility and the performance developed, a variety of test cells have been generated. Data presented clearly demonstrate the uniqueness, flexibility, and precision of the analog circuit layout cells implemented in this research thesis. In addition, one test chip and one design chip have been laid out using cells generated by ANASYN and fabricated at the Defense Advanced Research Project Agency (DARPA) silicon foundry referred to as MOSIS. Data are presented which show good agreement between developed cell models and the circuits actually produced.

Stanojevich, Bob Srbislav

231

Current sensing circuit  

NASA Technical Reports Server (NTRS)

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Franke, Ralph J. (Inventor)

1996-01-01

232

Application of AlGaAs\\/GaAs ballistic collection transistors to multiplexer and preamplifier circuits  

Microsoft Academic Search

Ballistic collection transistors with a 'launcher' (L-BCTs) are applied to the fabrication of high-speed\\/broadband ICs. The L-BCTs, in which base widening is suppressed and the ballistic transport of electrons is utilized to reduce transit time without an increase in base collector capacitance, are combined with a novel self-alignment process technology that makes it possible to enlarge the cutoff frequency f

Y. Matsuoka; S. Yamahata; H. Ichino; E. Sano; T. Ishibashi

1991-01-01

233

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes.  

PubMed

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ?46.2 cm(2) V(-1) s(-1), 10(5) and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates. PMID:25363072

Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng

2014-12-21

234

Conductus makes high-T sub c integrated circuit  

SciTech Connect

This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step.

Not Available

1991-01-01

235

Millimeter-wave and terahertz integrated circuit antennas  

NASA Technical Reports Server (NTRS)

This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

Rebeiz, Gabriel M.

1992-01-01

236

Organic thin-film transistors for circuits in a foundry: process, charge transport phenomena and device library  

NASA Astrophysics Data System (ADS)

For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.

Pankalla, Sebastian; Ganz, Simone; Spiehl, Dieter; Dörsam, Edgar; Glesner, Manfred

2013-09-01

237

Switching Transistor  

NASA Technical Reports Server (NTRS)

Westinghouse Electric Corporation's D60T transistors are used primarily as switching devices for controlling high power in electrical circuits. It enables reduction in the number and size of circuit components and promotes more efficient use of energy. Wide range of application from a popcorn popper to a radio frequency generator for solar cell production.

1981-01-01

238

Integrated circuit electrometer and sweep circuitry for an atmospheric probe  

NASA Technical Reports Server (NTRS)

The design of electrometer circuitry using an integrated circuit operational amplifier with a MOSFET input is described. Input protection against static voltages is provided by a dual ultra low leakage diode or a neon lamp. Factors affecting frequency response leakage resistance, and current stability are discussed, and methods are suggested for increasing response speed and for eliminating leakage resistance and current instabilities. Based on the above, two practical circuits, one having a linear response and the other a logarithmic response, were designed and evaluated experimentally. The design of a sweep circuit to implement mobility measurements using atmospheric probes is presented. A triangular voltage waveform is generated and shaped to contain a step in voltage from zero volts in both positive and negative directions.

Zimmerman, L. E.

1971-01-01

239

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors  

E-print Network

industry. Circuit simulation time has been substantially reduced through algorithm improvement and hardware enhancement through high performance computing (HPC) platforms. Given its ‘industry standard’ status for computer aided design and analysis... to Prof. Razali Ismail for the advice and supports. I could not complete my study without the help and discussions with Chin Shin Liang, Desmond Chek, David Chuah and Caston Urayai. Their contributions in quantum physics and circuit simulation...

Tan, Michael Loong Peng

2011-06-07

240

Attachment method for stacked integrated circuit (IC) chips  

SciTech Connect

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Bernhardt, Anthony F. (Berkeley, CA); Malba, Vincent (Livermore, CA)

1999-01-01

241

Attachment method for stacked integrated circuit (IC) chips  

DOEpatents

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Bernhardt, A.F.; Malba, V.

1999-08-03

242

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers  

NASA Astrophysics Data System (ADS)

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized

Hsu, Yu-Jen

243

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor  

SciTech Connect

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M., E-mail: muhammadmustafa.hussain@kaust.edu.sa [Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical Mathematical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia)

2013-11-25

244

Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits  

Microsoft Academic Search

As the number of transistors integrated on a circuit continues to increase, roughly doubling every 18 months, the impact of transistor variations on circuit performance becomes more significant. Even in the absence of systematic variations (implant nonuniformities, Leff and Weff variations), there exists a fundamental variability in the threshold voltage VT due to the finite number of dopant atoms in

D. Burnett; K. Eringtron; C. Subramanian; K. Baker

1994-01-01

245

Thermal modeling of power gallium arsenide microwave integrated circuits  

SciTech Connect

Low-power Gallium Arsenide-based microwave circuits have been used for many years for frequencies higher than those possible with silicon technology. At the present time manufacturers are developing power devices for ever higher frequencies using GaAs MESFET's and heterojunction bipolar devices constructed with III-V compounds on GaAs substrates. There is also interest in integrating power devices on Monolithic Microwave Integrated Circuits (MMIC's). A problem with the technology is the low thermal conductivity of Gallium Arsenide and this gives rise to thermal design problems which must be solved if good reliability is to be achieved. The paper uses a three-dimensional numerical simulator to study this problem and in particular examines the approximations which are possible in performing realistic assessments of the thermal resistance of typical GaAs power device structures under steady-state conditions.

Webb, P.W. (Univ. of Birmingham, Edgbaston (United Kingdom))

1993-05-01

246

Mechanical Computing Redux: Relays for Integrated Circuit Applications  

Microsoft Academic Search

Power density has grown to be the dominant challenge for continued complementary metal-oxide-semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applications. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical

Vincent Pott; Hei Kam; Rhesa Nathanael; Jaeseok Jeon; Elad Alon; Tsu-Jae King Liu

2010-01-01

247

Extended life testing evaluation of complementary MOS integrated circuits  

NASA Technical Reports Server (NTRS)

The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

Brosnan, T. E.

1972-01-01

248

A novel voltage output integrated circuit temperature sensor  

Microsoft Academic Search

The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two-terminal Zener, has\\u000a breakdown voltage directly proportional to Kelvin temperature at 10 mV\\/°C, with typical error of less than±1.0°C over a temperature\\u000a range from ?50°C to +125°C. In addition to all the features that conventional IC temperature sensors have, the new device\\u000a also has very

Wu Xiao-bo; Zhao Meng-lian; Fang Zhi-gang; Yan Xiao-lang

2002-01-01

249

Dielectric interface effects in subsurface microscopy of integrated circuits  

NASA Astrophysics Data System (ADS)

We investigate the defocus and image quality affected by a dielectric interface on high numerical aperture focusing of linearly polarized illumination in aplanatic mode. Theoretical and experimental demonstration is performed on subsurface backside microscopy of silicon integrated circuits, showing that the high longitudinal magnification provided by solid immersion lens microscopy allows the observation of significant astigmatism. It is shown that a 50 micron longitudinal displacement of the objective lens with respect to the sample is necessary to achieve maximum resolutions in two directions.

Hakan Köklü, F.; Goldberg, Bennett B.; Selim Ünlü, M.

2012-04-01

250

High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel  

NASA Astrophysics Data System (ADS)

Polycrystalline silicon thin-film transistors (TFTs) integrating sputtered Al2O3 gate dielectric with bridged-grain active channel are demonstrated. The proposed TFTs exhibit excellent device performance in terms of smaller threshold voltage, steeper subthreshold swing and higher on-current/off-current ratio. More importantly, the mobility of the proposed TFT is 5.5 times that of conventional TFTs with SiO2 gate dielectric. All of these results suggest that the proposed TFT is a good choice for low-power and high-speed driving circuits in display application.

Zhang, Meng; Zhou, Wei; Chen, Rongsheng; Wong, Man; Kwok, Hoi-Sing

2013-11-01

251

Optical Packet & Circuit Integrated Network for Future Networks  

NASA Astrophysics Data System (ADS)

This paper presents recent progress made in the development of an optical packet and circuit integrated network. From the viewpoint of end users, this is a single network that provides both high-speed, inexpensive services and deterministic-delay, low-data-loss services according to the users' usage scenario. From the viewpoint of network service providers, this network provides large switching capacity with low energy requirements, high flexibility, and efficient resource utilization with a simple control mechanism. The network we describe here will contribute to diversification of services, enhanced functional flexibility, and efficient energy consumption, which are included in the twelve design goals of Future Networks announced by ITU-T (International Telecommunication Union - Telecommunication Standardization Sector). We examine the waveband-based network architecture of the optical packet and circuit integrated network. Use of multi-wavelength optical packet increases the switch throughput while minimizing energy consumption. A rank accounting method provides a solution to the problem of inter-domain signaling for end-to-end lightpath establishment. Moving boundary control for packet and circuit services makes for efficient resource utilization. We also describe related advanced technologies such as waveband switching, elastic lightpaths, automatic locator numbering assignment, and biologically-inspired control of optical integrated network.

Harai, Hiroaki

252

The transition to Cu, damascene and low-K dielectrics for integrated circuit interconnects, impacts on the industry.  

NASA Astrophysics Data System (ADS)

This paper will briefly describe impacts of the transition to Cu and low-K dielectrics: why we want them, how close we are to fulfilling the want, and how they will impact the microelectronics industry. The improvements of microelectronic performance that fostered these innovations where in the past paced by our ability to build smaller, and therefore faster, transistors. Today the pace of innovation is being governed by our ability to build interconnections between these ever smaller and exponentially more numerous transistors. As a result the entire industry is embarking on the first major revision of integrated circuit interconnect technology since the original Robert Noyce invention of over 30 years ago. This transition calls for a change in all of the materials used to fabricate integrated circuit interconnects as well as the tools and methods by which we build them. In short, we plan to change everything. The short history and the current status of the technology transition will be reviewed. The core technology will be discussed, but this paper will also discuss other impacts of the transition, such as the equipment business¯ and of course, metrology. Changing everything in the technology is not simply going to impact the end products; it will also impact the entire industry and infrastructure of semiconductor manufacturing.

Monnig, Kenneth A.

2001-01-01

253

Neuromorphic opto-electronic integrated circuits for optical signal processing  

NASA Astrophysics Data System (ADS)

The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

2014-08-01

254

An alternative approach to model the Internal Activity of integrated circuits.  

E-print Network

An alternative approach to model the Internal Activity of integrated circuits. N. Berbel, R Toulouse Toulouse, France Abstract--This paper deals with the EMC modeling of integrated circuits and the standardized model IEC 62433-2 (Integrated Circuit Emission Model ­ Conducted Emission [1]). This standardized

Paris-Sud XI, Université de

255

Focal plane infrared readout circuit  

NASA Technical Reports Server (NTRS)

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

Pain, Bedabrata (Inventor)

2002-01-01

256

Pneumatic oscillator circuits for timing and control of integrated microfluidics  

PubMed Central

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

2013-01-01

257

Integrating anatomy and function for zebrafish circuit analysis  

PubMed Central

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties—e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

Arrenberg, Aristides B.; Driever, Wolfgang

2013-01-01

258

Fully integrated circuit chip of microelectronic neural bridge  

NASA Astrophysics Data System (ADS)

Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-?m CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

Xiaoyan, Shen; Zhigong, Wang

2014-09-01

259

Integrating anatomy and function for zebrafish circuit analysis.  

PubMed

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

Arrenberg, Aristides B; Driever, Wolfgang

2013-01-01

260

How to Build Electronic Circuits  

NSDL National Science Digital Library

This site offers a series of 41 videos about building electronic circuits. The videos include: -How Electron Flow Occurs in Electronic Circuits -Why Schematics are Used to Build Electronic Circuits -How Current is Determined by the Electronic Circuit -How Resistors Work in Electronic Circuits -Color Codes for Resistors in Electronic Circuits -How Capacitors Work in Electronic Circuits -How to Store a Charge in a Capacitor Inductors & Their Function -How to Measure Components in an Electronic Circuit -How Printed Circuit Boards Work -What Tools are Needed to Work with Electronics -Differences in Wire Gauges -How to Strip Wires Using Wire Strippers -How to Safely Work with Electronics -How to Power an Electronic Circuit -How to Measure Voltage in an Electronic Circuit -How to Measure Current in a Circuit -How to Measure Resistance in an Electronic Circuit -How Soldering Irons Work -How to Tin a Soldering Iron -How to Solder Electronic Leads Together -How to Use Perfboard to Make an Electronic Circuit -How to De-solder Electronic Connections -How to Diagnose Cold Solder Connections -How to Reflow a Connection in an Electronic Circuit -How to Use a Breadboard to Prototype a Circuit Board -How a Light Emitting Diode Works Uses & Operation of a Fuse -How to Use Integrated Circuits -How Transistors Work in an Electronic Circuit -How a Variable Resistor Works in an Electronic Circuit -How Does a Series Circuit Work -How to Compute Resistor Resistance in an Electronic Circuit -How Resistors Work in Parallel Circuits -How Schematics are Used in Electronics -How Switches Open & Close Circuits Electronic Circuits in Garage Door Openers -How to Make a Schematic for Your Electronic Circuit Project -How to Test a Prototype of Your Electronic Circuit -How to Use Perfboard to Build an Electronic Circuit and -Practical Operation of Electronic Circuit Indicators

Safronoff, Ross

2009-08-17

261

Advances in integrated photonic circuits for packet-switched interconnection  

NASA Astrophysics Data System (ADS)

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8? space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

262

Equivalent circuit modeling of losses and dispersion in single and coupled lines for microwave and millimeter-wave integrated circuits  

Microsoft Academic Search

Losses and dispersion in open inhomogeneous guided-wave structures such as microstrips and other planar structures at microwave and millimeter-wave frequencies and in MMICs (monolithic microwave integrated circuits) have been modeled with circuits consisting of ideal lumped elements and lossless TEM (transverse electromagnetic) lines. It is shown that, given a propagation structure for which numerical techniques to compute the propagation characteristics

Vijai K. Tripathi; Achim Hill

1988-01-01

263

Integrated circuits: Resistless processing simplifies production and cuts costs  

NASA Astrophysics Data System (ADS)

Reducing the complexity and cost of producing deep-submicrometer integrated circuits (IC's) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today's industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, 'cluster' processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

Weiner, K.

1993-03-01

264

Integrated circuits: Resistless processing simplifies production and cuts costs  

SciTech Connect

Reducing the complexity and cost of producing deep-submicrometer integrated circuits (ICs) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today`s industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, ``cluster`` processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

Weiner, K.

1993-03-25

265

An integrated workstation environment for modelling of high-frequency transistors  

E-print Network

AN INTEGRATED WORKSTATION ENVIRONMENT FOR MODELLING OF HIGH-FREQUENCY TRANSISTORS A Thesis by SRIRAM NARAYAN Submitted to the Office of Graduate Studies of Texas A@M University in partial fulfillment of the requirements 1' or the degree... for Modelling of High-frequency Transsstors. (August 1990) Sriram Narayan, B. Tech. . Indian Institute of Technology Bombay Co ? Chairs ot' Advisory Committee: Dr. R. L. Geiger Dr. J. R. Ranurez The objective of this research is to study the technique...

Narayan, Sriram

2012-06-07

266

Light-induced voltage alteration for integrated circuit analysis  

DOEpatents

An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

Cole, E.I. Jr.; Soden, J.M.

1995-07-04

267

SiGe/Si Monolithically Integrated Amplifier Circuits  

NASA Technical Reports Server (NTRS)

With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

Katehi, Linda P. B.; Bhattacharya, Pallab

1998-01-01

268

Wireless multichannel biopotential recording using an integrated FM telemetry circuit  

Microsoft Academic Search

This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of ?0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-?m double-poly double-metal n-well standard

Pedram Mohseni; Khalil Najafi; Steven J. Eliades; Xiaoqin Wang

2005-01-01

269

High-fidelity quantum photonics on a programmable integrated circuit  

E-print Network

We introduce a programmable photonic integrated circuit for implementing arbitrary linear optics transformations in the spatial mode basis with high fidelity. Under a realistic fabrication model, we analyze programmed implementations of the CNOT gate, CPHASE gate, iterative phase estimation algorithm, state preparation, and quantum random walks. We find that programmability dramatically improves device tolerance to fabrication imperfections and enables a single device to implement a broad range of both quantum and classical linear optics experiments. Our results suggest that existing fabrication processes are sufficient to build such a device in the silicon photonics platform.

Jacob Mower; Nicholas C. Harris; Gregory R. Steinbrecher; Yoav Lahini; Dirk Englund

2014-06-12

270

HEATRING -SMART INVESTIGATION OF TEMPERATURE IMPACT ON INTEGRATED CIRCUIT DEVICES  

E-print Network

at different temperatures usually the transistor area on the wafer is heated by external heat sources which directly controls the temperature of the investigated transistor area on the wafer, guaranteeing is to use an external heat source such as a thermo-chuck. A smart option is to use a heatring structure

Paris-Sud XI, Université de

271

Continuum based modeling of silicon integrated circuit processing: An object oriented approach  

E-print Network

Continuum based modeling of silicon integrated circuit processing: An object oriented approach Mark based integrated circuit process modeling is the dominant tool used to investigate and understand in- tegrated circuit (IC) development. This paper describes the commonly used models for implantation, diusion

Florida, University of

272

Stainless Steel NaK Circuit Integration and Fill Submission  

NASA Technical Reports Server (NTRS)

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Garber, Anne E.

2006-01-01

273

Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits  

E-print Network

Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power ...

Nagarajan, Raghavan

2008-01-01

274

Post-irradiation effects in CMOS integrated circuits  

SciTech Connect

The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80/sup 0/C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105/sup 0/C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80/sup 0/C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal.

Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

1988-12-01

275

Electronic-photonic integrated circuits on the CMOS platform  

NASA Astrophysics Data System (ADS)

The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

2006-02-01

276

The 11th International Symposium on Wireless Personal Multimedia Communications (WPMC 2008) DEVELOPMENT OF THZ TRANSISTORS  

E-print Network

) DEVELOPMENT OF THZ TRANSISTORS AND (300-3000 GHZ) SUB-MM-WAVE INTEGRATED CIRCUITS Mark Rodwell, E. Lobisser, M of 1-3 THz. High bandwidths are obtained by scaling; the critical limits to such scaling maxf and 324 GHz amplifiers have been demonstrated. Transistors with target maxf over 1 THz

Rodwell, Mark J. W.

277

Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors.  

PubMed

Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. PMID:24965261

Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; Li, Liang; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I; Alshareef, H N; Zhang, Yafei; Zhang, X X

2014-08-01

278

Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits  

SciTech Connect

Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

Keast, Craig (M.I.T. Lincoln Laboratory) [M.I.T. Lincoln Laboratory

2007-02-28

279

Local and nonlocal optically induced transparency effects in graphene-silicon hybrid nanophotonic integrated circuits.  

PubMed

Graphene is well-known as a two-dimensional sheet of carbon atoms arrayed in a honeycomb structure. It has some unique and fascinating properties, which are useful for realizing many optoelectronic devices and applications, including transistors, photodetectors, solar cells, and modulators. To enhance light-graphene interactions and take advantage of its properties, a promising approach is to combine a graphene sheet with optical waveguides, such as silicon nanophotonic wires considered in this paper. Here we report local and nonlocal optically induced transparency (OIT) effects in graphene-silicon hybrid nanophotonic integrated circuits. A low-power, continuous-wave laser is used as the pump light, and the power required for producing the OIT effect is as low as ?0.1 mW. The corresponding power density is several orders lower than that needed for the previously reported saturated absorption effect in graphene, which implies a mechanism involving light absorption by the silicon and photocarrier transport through the silicon-graphene junction. The present OIT effect enables low power, all-optical, broadband control and sensing, modulation and switching locally and nonlocally. PMID:25372937

Yu, Longhai; Zheng, Jiajiu; Xu, Yang; Dai, Daoxin; He, Sailing

2014-11-25

280

Developing design rules to avert cracking and debonding in integrated circuit structures  

E-print Network

Developing design rules to avert cracking and debonding in integrated circuit structures X.H. Liua,2]. . Dissimilar materials are integrated on a chip. When the structure is cooled from the processing temperature 26 January 2000 Abstract In an integrated circuit, stresses come from many sources (e.g., dierential

Suo, Zhigang

281

Manufacturing issues for 3D integrated active circuits into organic laminate substrates  

Microsoft Academic Search

The three dimensional integration of active circuits, thinned or in standard thickness, into polymeric substrates challenges current substrate manufacturing processes in an unprecedented way. In order to overcome the risks associated with this 3D integration technology, the issues must be carefully studied and assessed. For the direct integration of ultrathin chips into dielectric build up layers of multi-layer printed circuit

Erik Jung; Dirk Wojakowski; Alexander Neumann; Andreas Ostmann; Rolf Aschenbrenner; Herbert Reichl

2003-01-01

282

Investigation of failure mechanisms in integrated vacuum circuits  

NASA Technical Reports Server (NTRS)

The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

Rosengreen, A.

1972-01-01

283

Development of a plan for automating integrated circuit processing  

NASA Technical Reports Server (NTRS)

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

1971-01-01

284

Plasmonic nanopatch array for optical integrated circuit applications.  

PubMed

Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

Qu, Shi-Wei; Nie, Zai-Ping

2013-01-01

285

Design and testing of integrated circuits for reactor protection channels  

SciTech Connect

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K. [Oak Ridge National Lab., TN (United States); Naser, J. [Electric Power Research Inst., Palo Alto, CA (United States); Rana, I. [Southern Company Services, Birmingham, AL (United States)

1995-06-01

286

Design and testing of integrated circuits for reactor protection channels  

SciTech Connect

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built.

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K. [Oak Ridge National Lab., TN (United States); Naser, J. [Electric Power Research Inst., Palo Alto, CA (United States)

1995-06-01

287

Gallium Arsenide pilot line for high performance components. SARGIC HFET (Self Aligned Refractory Gate Integrated Circuit/Hetro-junction FET) design manual  

NASA Astrophysics Data System (ADS)

This manual describes and layout of GaAs integrated circuits using SARGIC/HFET (Self Aligned Refractory Gate Integrated Circuit/Hetro-junction Field effect Transistor) process. It is divided into three sections, layout design rules, device terminal characteristics, and process control monitor (PCM). The first section outlines the layout of digital GaAs circuits in the SARGIC/HFET, 2 micrometers design rules. It describes the circuit layout procedure level by level, and includes the process's layout design rules. The second section contains the terminal characteristics of Enhancement (EHFET), Depletion (DHFET), and diode devices. This includes drain and gate I/V and capacitance curves modeled by AT and T's ADVICE circuit simulator at 25 and 125 C. The last section includes the design and layout of the Process Control Monitor (PCM). The PCM contains test structures for process control and the extraction of circuit simulator models and device S parameters. This allows the foundry to test for process biases, extract process/device parameters, ADVICE models, and gate propagation delays and noise margins.

1988-06-01

288

Related News "Flexible" Circuit Boards in  

E-print Network

Stretchy circuit The Engineer - Mar 31, 2008 Full coverage » Stretchy circuit possibilities 3 days ago in different directions. The researchers incorporated the stretchy circuits into transistors, oscillators

Rogers, John A.

289

Novel Current-Scaling Current-Mirror Hydrogenated Amorphous Silicon Thin-Film Transistor Pixel Electrode Circuit with Cascade Capacitor for Active-Matrix Organic Light-Emitting Devices  

Microsoft Academic Search

We proposed the hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with current-scaling function which is suitable for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current-mirror circuit, this circuit with the cascaded storage capacitors can provide a high data-to-organic light-emitting device (OLED) current ratio without increasing the a-Si:H TFT size. Moreover, since the number of

Hojin Lee; Juhn S. Yoo; Chang-Dong Kim; In-Jae Chung; Jerzy Kanicki

2007-01-01

290

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit.  

PubMed

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal processing is accomplished with a current-to-frequency converter circuit that forms the causal portion of the matched filter for dc luminescence in wide-band white noise. Measurements show that luminescence can be detected from as few as 4 x 10(5) cells/ml. PMID:12192685

Simpson, M L; Sayler, G S; Patterson, G; Nivens, D E; Bolton, E K; Rochelle, J M; Arnott, J C; Applegate, B M; Ripp, S; Guillorn, M A

2001-01-25

291

Nanowire-organic thin film transistor integration and scale up towards developing sensor array for biomedical sensing applications  

NASA Astrophysics Data System (ADS)

Exploratory research works have demonstrated the capability of conducting nanowire arrays in enhancing the sensitivity and selectivity of bio-electrodes in sensing applications. With the help of different surface manipulation techniques, a wide range of biomolecules have been successfully immobilized on these nanowires. Flexible organic electronics, thin film transistor (TFT) fabricated on flexible substrate, was a breakthrough that enabled development of logic circuits on flexible substrate. In many health monitoring scenarios, a series of biomarkers, physical properties and vital signals need to be observed. Since the nano-bio-electrodes are capable of measuring all or most of them, it has been aptly suggested that a series of electrode (array) on single substrate shall be an excellent point of care tool. This requires an efficient control system for signal acquisition and telemetry. An array of flexible TFTs has been designed that acts as active matrix for controlled switching of or scanning by the sensor array. This array is a scale up of the flexible organic TFT that has been fabricated and rigorously tested in previous studies. The integration of nanowire electrodes to the organic electronics was approached by growing nanowires on the same substrate as TFTs and fl ip chip packaging, where the nanowires and TFTs are made on separate substrates. As a proof of concept, its application has been explored in various multi-focal biomedical sensing applications, such as neural probes for monitoring neurite growth, dopamine, and neuron activity; myocardial ischemia for spatial monitoring of myocardium.

Kumar, Prashanth S.; Hankins, Phillip T.; Rai, Pratyush; Varadan, Vijay K.

2010-04-01

292

Thermal coupling in integrated circuits: application to thermal testing  

Microsoft Academic Search

The power dissipated by the devices of a circuit can be construed as a signature of the circuit's performance and state. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements of the silicon die surface via built-in differential temperature sensors. In this paper, dynamic and spatial thermal behavioral characterization of VLSI MOS devices is presented

Josep Altet; Antonio Rubio; Emmanuel Schaub; Stefan Dilhaire; Wilfrid Claeys

2001-01-01

293

Planar fluxgate current sensor integrated in printed circuit board  

Microsoft Academic Search

This paper describes the design and testing of a planar fluxgate current sensor, which is totally embedded in printed circuit board (PCB) and which is suitable for sensing currents in the printed circuit board traces. Fluxgate excitation and pickup coils are implemented as racetrack shaped copper winding in the printed circuit board internal layers. These are surrounded by an electroplated

Terence O’Donnell; A. Tipek; A. Connell; P. McCloskey; S. C. O’Mathuna

2006-01-01

294

A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor  

E-print Network

We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

2010-08-28

295

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20 um SiGe heterojunction bipolar transistors and circuits.  

SciTech Connect

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallele-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

Fritz, Karl (Mayo Foundation, Rochester, MN); Irwin, Timothy J. (Jackson & Tull Chartered Engineers, Washington, DC); Niu, Guofu (Auburn University, Auburn, AL); Fodness, Bryan (SGT, Inc., Greenbelt, MD); Carts, Martin A. (Raytheon ITSS, Greenbelt, MD); Marshall, Paul W. (Brookneal, VA); Reed, Robert A. (NASA/GSFC, Greenbelt, MD); Gilbert, Barry (Mayo Foundation, Rochester, MN); Randall, Barbara (Mayo Foundation, Rochester, MN); Prairie, Jason (Mayo Foundation, Rochester, MN); Riggs, Pam (Mayo Foundation, Rochester, MN); Pickel, James C. (PR& T, Inc., Fallbrook, CA); LaBel, Kenneth (NASA/GSFC, Greenbelt, MD); Cressler, John D. (Georgia Institute of Technology, Atlanta, GA); Krithivasan, Ramkumar (Georgia Institute of Technology, Atlanta, GA); Dodd, Paul Emerson; Vizkelethy, Gyorgy

2003-09-01

296

Intelligent switches of integrated lightwave circuits with core telecommunication functions  

NASA Astrophysics Data System (ADS)

We present a brief overview of a promising switching technology based on Silica on Silicon thermo-optic integrated circuits. This is basically a 2D solid-state optical device capable of non-blocking switching operation. Except of its excellent performance (insertion loss<5dB, switching time<2ms...), the switch enables additional important build-in functionalities. It enables single-to- single channel switching and single-to-multiple channel multicasting/broadcasting. In addition, it has the capability of channel weighting and variable output power control (attenuation), for instance, to equalize signal levels and compensate for unbalanced different optical input powers, or to equalize unbalanced EDFA gain curve. We examine the market segments appropriate for the switch size and technology, followed by a discussion of the basic features of the technology. The discussion is focused on important requirements from the switch and the technology (e.g., insertion loss, power consumption, channel isolation, extinction ratio, switching time, and heat dissipation). The mechanical design is also considered. It must take into account integration of optical fiber, optical planar wafer, analog electronics and digital microprocessor controls, embedded software, and heating power dissipation. The Lynx Photon.8x8 switch is compared to competing technologies, in terms of typical market performance requirements.

Izhaky, Nahum; Duer, Reuven; Berns, Neil; Tal, Eran; Vinikman, Shirly; Schoenwald, Jeffrey S.; Shani, Yosi

2001-05-01

297

Focused ion beam damage to MOS integrated circuits  

SciTech Connect

Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga{sup +} ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed.

FLEETWOOD,D.M.; CAMPBELL,ANN N.; HEMBREE,CHARLES E.; TANGYUNYONG,PAIBOON; JESSING,JEFFREY R.; SODEN,JERRY M.

2000-05-10

298

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET  

E-print Network

AbstractThe performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well...

Tan, Michael Loong P; Lentaris, Georgios; Amaratunga AJ, Gehan

2012-08-19

299

Tuning the threshold voltage in electrolyte-gated organic field-effect transistors  

PubMed Central

Low-voltage organic field-effect transistors (OFETs) promise for low power consumption logic circuits. To enhance the efficiency of the logic circuits, the control of the threshold voltage of the transistors are based on is crucial. We report the systematic control of the threshold voltage of electrolyte-gated OFETs by using various gate metals. The influence of the work function of the metal is investigated in metal-electrolyte-organic semiconductor diodes and electrolyte-gated OFETs. A good correlation is found between the flat-band potential and the threshold voltage. The possibility to tune the threshold voltage over half the potential range applied and to obtain depletion-like (positive threshold voltage) and enhancement (negative threshold voltage) transistors is of great interest when integrating these transistors in logic circuits. The combination of a depletion-like and enhancement transistor leads to a clear improvement of the noise margins in depleted-load unipolar inverters. PMID:22586088

Kergoat, Loig; Herlogsson, Lars; Piro, Benoit; Pham, Minh Chau; Horowitz, Gilles; Crispin, Xavier; Berggren, Magnus

2012-01-01

300

An investigation of defect detection using random defect excitation and deterministic defect observation in complex integrated logic circuits  

E-print Network

aWhenever integrated circuits are manufactured, a certain percentage of those circuits will be defective. Defective circuits present problems for both the manufacturers who wish to maintain a good reputation with their customers and the consumers...

Dworak, Jennifer

2013-02-22

301

Characterization and requirements for Cu-Cu bonds for three-dimensional integrated circuits  

E-print Network

Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and reduces global RC delay by increasing the device density per unit chip area. ...

Tadepalli, Rajappa, 1979-

2007-01-01

302

Materials and devices for optical switching and modulation of photonic integrated circuits  

E-print Network

The drive towards photonic integrated circuits (PIC) necessitates the development of new devices and materials capable of achieving miniaturization and integration on a CMOS compatible platform. Optical switching: fast ...

Seneviratne, Dilan Anuradha

2007-01-01

303

CMOS transistor processing compatible with monolithic 3-D Integration B. Rajendran, R. S. Shenoy1  

E-print Network

affecting the reliability of devices below. I. INTRODUCTION The main concern in the sequential fabrication heating material deeper within the work piece. In an earlier work, we demonstrated that laser annealing) integrated circuit structure without affecting the reliability of the devices below. Here, we demonstrate

Pease, R. Fabian W.

304

FAILURE ANALYSIS OF INTEGRATED CIRCUITS USING OPTICAL THERMOGRAPHY AND SPECTROREFLECTANCE MICROSCOPY  

Microsoft Academic Search

We demonstrate failure analysis of integrated circuits (IC) at optical resolution (~ 1 µm) using an optical feedback laser diode confocal microscope. By acquiring the reflectance and the optical-beam-induced current (OBIC) images at each point on the sample, it is possible to discriminate the semiconductor from the metallic sites in integrated circuits(1). Such spatial classification reveals the nature of defect

Carlo Mar Blanca; Vernon Cemine; Vera Sastine; Berns Buenaobra; Caesar Saloma

305

Program Counter as an Integrated Circuit Metrics for Secured Program Identification  

E-print Network

Program Counter as an Integrated Circuit Metrics for Secured Program Identification Kofi Appiah of Computer Science & Electronic Engineering University of Essex, Colchester, UK {xzhai.G.J.Howells@kent.ac.uk Abstract--Integrated Circuit Metrics is mainly concerned with the extraction of measurable properties

Hu, Huosheng

306

Performance and applications of gallium-nitride monolithic microwave integrated circuits (GaN MMICs)  

NASA Astrophysics Data System (ADS)

The evolution of wide-bandgap semiconductor transistor technology is placed in historical context with other active device technologies. The relative rapidity of GaN transistor development is noted and is attributed to the great parallel activity in the lighting sector and the historical experience and business model from the III-V compound semiconductor sector. The physical performance expectations for wide-bandgap technologies such as Gallium-Nitride Field-Effect Transistors (GaN FETs) are reviewed. We present some device characteristics. Challenges met in characterising, and prospects for modeling GaN FETs are described. Reliability is identified as the final remaining hurdle facing would-be foundries. Evolutionary and unsurprising applications as well as novel and revolutionary applications are suggested. Novel applications include wholly monolithic switchmode power supplies, simplified tools for ablation and diathermy in tissue, and very wide dynamic range circuits for audio or low phase noise signal generation. We conclude that now is the time to embark on circuit design of MMICs in wide-bandgap technology. The potential for fabless design groups to capitalise upon design IP without strong geopraphic advantage is noted.

Scott, Jonathan B.; Parker, Anthony E.

2007-12-01

307

A parameterized functional cell design methodology for analog integrated circuits  

E-print Network

linear and nonlinear analog circuits, including filters, summing amplifiers, piecewise- linear functions, modulators, bistables, waveform generators, and A/D and D/A converters. The GPFC utilizes switched-capacitor (SC) techniques, and consists... bistable circuit A generalized bistable circuit Block diagram of an algorithmic A/D converter First tivo stages of the GPFC implementation of the algorithmic A/D converter in Figure 2. 25 . Organization of the AIDE CAD system Application of the AIDE...

Bily, Stephen Frank

2012-06-07

308

Laser Micromachining of Active and Passive Photonic Integrated Circuits  

E-print Network

This thesis describes the development of advanced laser resonators and applications of laserinduced micromachining for photonic circuit fabrication. Two major advantages of laserinduced micromachining are direct patterning ...

Cho, Seong-Ho

2006-06-28

309

Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS  

NASA Technical Reports Server (NTRS)

Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful performance of experimental, proof-of-concept MMIC K/Ka-band arrays developed with U.S. industry in field demonstrations with ACTS indicates that high density MMIC integration at 20 and 30 GHz is indeed feasible. The successful development and demonstration of the MMIC array systems was possible only because of significant intergovernmental and Government/industry cooperation and the high level of teamwork within Lewis. The results provide a strong incentive for continuing the focused development of MMIC-array technology for satellite communications applications, with emphasis on packaging and cost issues, and for continuing the planning and conducting of other appropriate demonstrations or experiments of phased-array technology with ACTS. Given the present pressures on reducing funding for research and development in Government and industry, the extent to which this can be continued in a cooperative manner will determine whether MMIC array technology will make the transition from the proof-of-concept level to the operational system level.

1996-01-01

310

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip  

PubMed Central

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 ?m2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

311

PETRIC - A positron emission tomography readout integrated circuit  

SciTech Connect

We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

2000-11-05

312

Scheduling revisited workstations in integrated-circuit fabrication  

NASA Technical Reports Server (NTRS)

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

Kline, Paul J.

1992-01-01

313

Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology  

NASA Astrophysics Data System (ADS)

A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9 dB. A 50 mV 10 MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

Guo, Wei-Feng; Zhao, Yong; Wang, Wan-Jun; Shao, Hai-Feng; Yang, Jian-Yi; Jiang, Xiao-Qing

2012-04-01

314

Soft-error generation due to heavy-ion tracks in bipolar integrated circuits  

NASA Technical Reports Server (NTRS)

Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

Zoutendyk, J. A.

1984-01-01

315

Volatile general anesthetic sensing with organic field-effect transistors integrating phospholipid membranes.  

PubMed

The detailed action mechanism of volatile general anesthetics is still unknown despite their effect has been clinically exploited for more than a century. Long ago it was also assessed that the potency of an anesthetic molecule well correlates with its lipophilicity and phospholipids were eventually identified as mediators. As yet, the direct effect of volatile anesthetics at physiological relevant concentrations on membranes is still under scrutiny. Organic field-effect transistors (OFETs) integrating a phospholipid (PL) functional bio inter-layer (FBI) are here proposed for the electronic detection of archetypal volatile anesthetic molecules such as diethyl ether and halothane. This technology allows to directly interface a PL layer to an electronic transistor channel, and directly probe subtle changes occurring in the bio-layer. Repeatable responses of PL FBI-OFET to anesthetics are produced in a concentration range that reaches few percent, namely the clinically relevant regime. The PL FBI-OFET is also shown to deliver a comparably weaker response to a non-anesthetic volatile molecule such as acetone. PMID:22921091

Daniela Angione, Maria; Magliulo, Maria; Cotrone, Serafina; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Gobeljic, Danka; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

2013-02-15

316

Developing design rules to avert cracking and debonding in integrated circuit structures  

Microsoft Academic Search

In an integrated circuit, stresses come from many sources (e.g., differential thermal expansion and electromigration). The circuit structures are never perfect, possibly containing crack-like flaws. The stresses may drive the pre-existing cracks to grow and cause circuit failure. We explore a fracture mechanics approach to formulate design rules to avert crack growth. We adopt a strategy based on two attributes

X. H. Liu; Z. Suo; Q. Ma; H. Fujimoto

2000-01-01

317

Laser micromachining of active and passive photonic integrated circuits  

E-print Network

This thesis describes the development of advanced laser resonators and applications of laser-induced micromachining for photonic circuit fabrication. Two major advantages of laser-induced micromachining are direct patterning ...

Cho, Seong-Ho, 1966-

2004-01-01

318

Organic nanofibers integrated by transfer technique in field-effect transistor devices  

PubMed Central

The electrical properties of self-assembled organic crystalline nanofibers are studied by integrating these on field-effect transistor platforms using both top and bottom contact configurations. In the staggered geometries, where the nanofibers are sandwiched between the gate and the source-drain electrodes, a better electrical conduction is observed when compared to the coplanar geometry where the nanofibers are placed over the gate and the source-drain electrodes. Qualitatively different output characteristics were observed for top and bottom contact devices reflecting the significantly different contact resistances. Bottom contact devices are dominated by contact effects, while the top contact device characteristics are determined by the nanofiber bulk properties. It is found that the contact resistance is lower for crystalline nanofibers when compared to amorphous thin films. These results shed light on the charge injection and transport properties for such organic nanostructures and thus constitute a significant step forward toward a nanofiber-based light-emitting device. PMID:21711821

2011-01-01

319

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation  

Microsoft Academic Search

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be

Ming-Dou Ker; Cheng-Cheng Yen; Pi-Chia Shih

2008-01-01

320

Estimation of On-Chip Simultaneous Switching Noise on Signal Delay in Synchronous CMOS Integrated Circuits  

Microsoft Academic Search

On-chip parasitic inductance inherent to the power distribution network has becoming significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution network, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits.

Kevin T. Tang; Eby G. Friedman

321

Delay uncertainty due to on-chip simultaneous switching noise in high performance CMOS integrated circuits  

Microsoft Academic Search

On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits. Analytical expressions characterizing

Kevin T. Tang; Eby G. Friedman

2000-01-01

322

Abstract--With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate  

E-print Network

Abstract--With the growing concerns about electromagnetic compatibility of integrated circuits-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level be extended towards online diagnosis and self-healing. Index Terms-- Electromagnetic compatibility, signal

Boyer, Edmond

323

Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview  

Microsoft Academic Search

This paper is an overview of the concepts and methodologies used to predict soft-error rates (SER) due to cosmic and high-energy particle radiation in integrated circuit chips. The paper emphasizes the need for the SER simulation using the actual chip circuit model which includes device, process, and technology parameters as opposed to using either the discrete device simulation or generic

G. R. Srinivasan

1996-01-01

324

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement  

Microsoft Academic Search

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within one semester, and the grading cycle in the most recent

Wei-Liang Lin; Wang-Chuan Cheng; Chen-Hao Wu; Hai-Ming Wu; Chang-Yu Wu; Kuan-Hsuan Ho; Chueh-An Chan

2010-01-01

325

The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions  

SciTech Connect

A method for modeling the variations in defect levels in circuits produced on modern integrated circuit manufacturing lines is described in this paper. The effects on defect and fault distributions are derived. A deficiency in some previous yield models is eliminated.

Stapper, C.H.

1985-01-01

326

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1 On-Chip Noise Sensor for Integrated Circuit  

E-print Network

of interferences within the circuit and a diagnosis of failure origins. Index Terms--Electromagnetic compatibility. INTRODUCTION THESE LAST years, the concerns about electromagnetic compatibility (EMC) of integrated circuits Vrignon, Mikaël Deobarro, and Thanh Vinh Dinh Abstract--With the growing concerns about electromagnetic

Boyer, Edmond

327

A New Monolothic Integrated Circuit for Multiwire Proportional Chamber (MWPC) Read-Out System  

Microsoft Academic Search

A new monolithic 8-channel PMOS integrated circuit has been developed for an experiment to be carried out on the CERN 300 GeV accelerator. The circuit, read-out electronics and tests performed on 12 large MWPC (total of 48 000 channels) are described and the results are presented.

P. Bareyre; P. Borgeaud; J. C. Brisson; B. Ollivier; J. Poinsignon; J. Borel; G. Merckel; P. Meunier; B. Billion; J. Prunier

1976-01-01

328

Development of a switched capacitor based multi-channel transient waveform recording integrated circuit  

Microsoft Academic Search

The paper describes a new full custom integrated circuit addressing the problem of transient analog signal recording. The chip includes 2048 sample and hold cells, fast clock generation logic and readout amplifiers. The 2048 sample and hold circuits are divided into 16 channels of 128 samples per channel. One read amplifier is used per channel. Clock signals are generated via

S. A. Kleinfelder

1988-01-01

329

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.  

ERIC Educational Resources Information Center

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

Muyskens, Mark A.

1997-01-01

330

GeSi photodetectors and electro-absorption modulators for Si electronic-photonic integrated circuits  

E-print Network

The silicon electronic-photonic integrated circuit (EPIC) has emerged as a promising technology to break through the interconnect bottlenecks in telecommunications and on-chip interconnects. High performance photonic ...

Liu, Jifeng, Ph. D. Massachusetts Institute of Technology

2007-01-01

331

Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications  

E-print Network

Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade ...

Fariborzi, Hossein

2013-01-01

332

High-speed silicon electro-optic modulator for electronic photonic integrated circuits  

E-print Network

The development of future electronic-photonic integrated circuits (EPIC) based on silicon technology critically depends on the availability of CMOS-compatible high-speed modulators that enable the interaction of electronic ...

Gan, Fuwan

2007-01-01

333

Characterization and modeling of plasma etch pattern dependencies in integrated circuits  

E-print Network

A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent ...

Abrokwah, Kwaku O

2006-01-01

334

Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits  

E-print Network

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures ...

Leong, Hoi Liong

335

Reducing hot spots and junction temperatures of integrated circuits using carbon composite in a printed circuit board and substrate  

Microsoft Academic Search

Carbon composite laminate is used in the integral structure of printed circuit boards (PCB) today to spread the heat from the heat source mounted on the surface. The thermal conductivity of carbon fiber used in the composite is lateral and ranging from 10W\\/m.K to 600W\\/m.K. This lateral property results in high thermal conductivity in-plane, opposed to the through-plane of composite.

K. Vasoya

2006-01-01

336

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications  

NASA Astrophysics Data System (ADS)

In this work we explore several doping schemes for aggressively scaled multi-gate field-effect transistor devices with the conduction channels wrapped around silicon fins (FinFETs) (HFin?37 nm, WFin?10 nm, Lg?30 nm), using conventional ion implantation (I/I), and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, single-sided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher six transistors-static random access memory (6T-SRAM) static noise margin (SNM) values. Key advantages of the extension-less approach are: reduced cost and cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Si-epitaxial raised source/drain (SEG), and up to 20× lower IOFF. It, however, requires a tight spacer critical dimension (CD) control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins.

Veloso, Anabela; De Keersgieter, An; Brus, Stephan; Horiguchi, Naoto; Absil, Philippe P.; Hoffmann, Thomas

2011-04-01

337

Astrocyte-encoded positional cues maintain sensorimotor circuit integrity  

PubMed Central

SUMMARY Astrocytes, the most abundant cells in the central nervous system, promote synapse formation and help refine neural connectivity. Although they are allocated to spatially distinct regional domains during development, it is unknown whether region-restricted astrocytes are functionally heterogeneous. Here we show that postnatal spinal cord astrocytes express several region-specific genes, and that ventral astrocyte-encoded Semaphorin3a (Sema3a) is required for proper motor neuron and sensory neuron circuit organization. Loss of astrocyte-encoded Sema3a led to dysregulated ?–motor neuron axon initial segment orientation, markedly abnormal synaptic inputs, and selective death of ?–but not of adjacent ?–motor neurons. Additionally, a subset of TrkA+ sensory afferents projected to ectopic ventral positions. These findings demonstrate that stable maintenance of a positional cue by developing astrocytes influences multiple aspects of sensorimotor circuit formation. More generally, they suggest that regional astrocyte heterogeneity may help to coordinate postnatal neural circuit refinement. PMID:24776795

Molofsky, Anna V.; Kelley, Kevin W.; Tsai, Hui-Hsin; Redmond, Stephanie A.; Chang, Sandra M.; Madireddy, Lohith; Chan, Jonah R.; Baranzini, Sergio E.; Ullian, Erik M.; Rowitch, David H.

2014-01-01

338

Pulsed laser-induced SEU in integrated circuits; A practical method for hardness assurance testing  

SciTech Connect

The authors have used a pulsed picosecond laser to measure the threshold for single event upset (SEU) and single event latchup (SEL) for two different kinds of integrated circuits. The relative thresholds show good agreement with published ion upset data. The consistency of the results together with the advantages of using a laser system suggest that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits.

Buchner, S.; Kang, K. (Martin Marietta Labs., Baltimore, MD (USA)); Stapor, W.J.; Campbell, A.B.; Knudson, A.R.; McDonald, P. (Naval Research Lab., Washington, DC (USA)); Rivet, S. (Harris Corp., Melbourne, FL (USA). Semiconductor Sector)

1990-12-01

339

A control and signal Processing integrated circuit for the JPL-boeing micromachined gyroscopes  

Microsoft Academic Search

A special-purpose integrated circuit that accomplishes the real-time control and filtering tasks for the JPL-Boeing micromachined gyroscopes using a flexible, low-power implementation is presented. Our exposition focuses on the integration of the circuit and a prototype sensor, the synthesis and implementation of the control filters, and the subsequent performance of the closed-loop system. Identified sensor models are also presented because

Yen-Cheng Chen; Robert T. M'Closkey; Tuan A. Tran; Brent Blaes

2005-01-01

340

Design of a semi-custom integrated circuit for the SLAC SLC timing control system  

SciTech Connect

A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given.

Linstadt, E.

1984-10-01

341

Laser removal of Aluminum links for applications in wafer scale integrated circuits  

E-print Network

LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis by HARSHAVADAN B. PARIKH Submitted to the Graduate College of Texas A&M University in partial fulfillment of the requirement for the degree... of MASTER OF SCIENCE May 1987 Major Subject: Electrical Engineering LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis HARSHAVADAN B. PARIKH Approved ss to style snd content by: M. H, Weichold (Chairman...

Parikh, Harshavadan B.

2012-06-07

342

Thermal Characteristics of Plastic Small Outline Transistor (SOT) Packages  

Microsoft Academic Search

Surface mount plastic packages, including small outline transistor (SOT), small outline integrated circuit (SOIC), and plastic leaded chip carrier (PLCC), are projected to be the next generation replacement for plastic dual in-line packages (DIP's). Relative to DIP's, surface mount packages are small in size and allow higher package density on a hoard, leading to higher electrical speed for system applications.

MOHAMED MUNAF ALLI; MALI MAHALINGAM; JAMES A. ANDREWS

1986-01-01

343

The temperature characteristics of bipolar transistors fabricated in CMOS technology  

Microsoft Academic Search

This paper presents the results of an experimental investigation of the temperature characteristics of bipolar transistors fabricated in CMOS technology. These results have to be known and understood to enable the design of high-performance temperature sensors and bandgap references in CMOS integrated circuits. The non-idealities of proportional to the absolute temperature voltage (VPTAT) have been studied, and the results show

Guijie Wang; Gerard C. M Meijer

2000-01-01

344

Broad Beam and Ion Microprobe Studies of Single-Event Upsets in High Speed 0.18micron Silicon Germanium Heterojunction Bipolar Transistors and Circuits  

NASA Technical Reports Server (NTRS)

SiGe based technology is widely recognized for its tremendous potential to impact the high speed microelectronic industry, and therefore the space industry, by monolithic incorporation of low power complementary logic with extremely high speed SiGe Heterojunction Bipolar Transistor (HBT) logic. A variety of studies have examined the ionizing dose, displacement damage and single event characteristics, and are reported. Accessibility to SiGe through an increasing number of manufacturers adds to the importance of understanding its intrinsic radiation characteristics, and in particular the single event effect (SEE) characteristics of the high bandwidth HBT based circuits. IBM is now manufacturing in its 3rd generation of their commercial SiGe processes, and access is currently available to the first two generations (known as and 6HP) through the MOSIS shared mask services with anticipated future release of the latest (7HP) process. The 5 HP process is described and is characterized by a emitter spacing of 0.5 micron and a cutoff frequency ff of 50 GHz, whereas the fully scaled 7HP HBT employs a 0.18 micron emitter and has an fT of 120 GHz. Previous investigations have the examined SEE response of 5 HP HBT circuits through both circuit testing and modeling. Charge collection modeling studies in the 5 H P process have also been conducted, but to date no measurements have been reported of charge collection in any SiGe HBT structures. Nor have circuit models for charge collection been developed in any version other than the 5 HP HBT structure. Our investigation reports the first indications of both charge collection and circuit response in IBM s 7HP-based SiGe process. We compare broad beam heavy ion SEU test results in a fully function Pseudo-Random Number (PRN) sequence generator up to frequencies of 12 Gbps versus effective LET, and also report proton test results in the same circuit. In addition, we examine the charge collection characteristics of individual 7HP HBT structures and map out the spatial sensitivities using the Sandia Focused Heavy Ion Microprobe Facility s Ion Beam Induced Charge Collection (IBICC) technique. Combining the two data sets offers insights into the charge collection mechanisms responsible for circuit level response and provides the first insights into the SEE characteristics of this latest version of IBM s commercial SiGe process.

Reed, Robert A.; Marshall, Paul W.; Pickel, Jim; Carts, Martin A.; Irwin, TIm; Niu, Guofu; Cressler, John; Krithivasan, Ramkumar; Fritz, Karl; Riggs, Pam

2003-01-01

345

Invited Paper An Integrated-Circuit Switched-Capacitor Model  

E-print Network

, and left ventricle. The contractions in each of the four chambers lead to pressure differences that cause delays between the various signals may be useful in monitoring parameters related to blood pressure via circuit model of the heart. The chip may be useful in low-power body sensor networks that use analysis

Sarpeshkar, Rahul

346

Electromagnetic Interference (EMI) Resisting Analog Integrated Circuit Design Tutorial  

E-print Network

are analyzed and compared to each other in terms of EMI-Induced input offset voltage and other important specifications such as current consumption. In this work, EMI-robust analog circuits are proposed, of which the architecture is based on source...

Yu, Jingjing

2012-10-19

347

Design of micro-ring optical sensors and circuits for integration on optical printed circuit boards (O-PCBs)  

NASA Astrophysics Data System (ADS)

We report on the design of micro-ring resonator optical sensors for integration on what we call optical printed circuit boards (O-PCBs). The objective is to realize application-specific O-PCBs, either on hard board or on flexible board, by integrating micro/nano-scale optical sensors for compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly processing of information. The O-PCBs consist of two-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing and then storing, transporting, processing, switching, routing and distributing optical signals that have been collected by means of sensors. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate sensors and other micro/ nano-scale photonic devices. Here, in our study, we focus on the sensors based on the micro-ring structures. We designed bio-sensors using silicon based micro-ring resonator. We investigate the characteristics such as sensitivity and selectivity (or quality factor) of micro-ring resonator for their use in bio-sensing application. We performed simulation studies on the quality factor of micro-ring resonators by varying the radius of the ring resonators and the separation between adjacent waveguides. We introduce the effective coupling coefficient as a realistic value to describe the strength of the coupling in micro-ring resonators.

Lee, El-Hang; Lee, Hyun S.; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

2007-05-01

348

Integrated circuit substrate coupling models based on Voronoi tessellation  

Microsoft Academic Search

We present a modeling technique for assessing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Since the magnitude of the noise problem is a function of the relative proximity of noisy and sensitive devices, design aids are required which can incorporate the switching noise effects at the post-layout phase of design verification. In our approach, SPICE-compatible lumped element

Ivan L. Wemple; Andrew T. Yang

1995-01-01

349

A disinhibitory circuit mediates motor integration in the somatosensory cortex  

PubMed Central

The influence of motor activity on sensory processing is crucial for perception and motor execution. However, the underlying circuits are not known. To unravel the circuit by which activity in the primary vibrissal motor cortex (vM1) modulates sensory processing in the primary somatosensory barrel cortex (S1), we used optogenetics to examine the long-range inputs from vM1 to the various neuronal elements in S1. We found that S1-projecting vM1 pyramidal neurons strongly recruited vasointestinal peptide (VIP)-expressing GABAergic interneurons, a subset of serotonin receptor–expressing interneurons. These VIP interneurons preferentially inhibited somatostatin-expressing interneurons, neurons that target the distal dendrites of pyramidal cells. Consistent with this vM1-mediated disinhibitory circuit, the activity of VIP interneurons in vivo increased and that of somatostatin interneurons decreased during whisking. These changes in firing rates during whisking depended on vM1 activity. Our results suggest previously unknown circuitry by which inputs from motor cortex influence sensory processing in sensory cortex. PMID:24097044

Lee, Soohyun; Kruglikov, Illya; Huang, Z Josh; Fishell, Gord; Rudy, Bernardo

2014-01-01

350

Extreme ultraviolet lithography and three dimensional integrated circuit-A review  

NASA Astrophysics Data System (ADS)

Extreme ultraviolet lithography (EUVL) and three dimensional integrated circuit (3D IC) were thoroughly reviewed. Since proposed in 1988, EUVL obtained intensive studies globally and, after 2000, became the most promising next generation lithography method even though challenges were present in almost all aspects of EUVL technology. Commercial step-and-scan tools for preproduction are installed now with full field capability; however, EUV source power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 200 W in-band power at IF, current tools can supply only approximately 40-55 W. EUVL resist has improved significantly in the last few years, with 13 nm line/space half-pitch resolution being produced with approximately 3-4 nm line width roughness (LWR), but LWR needs 2× improvement. Creating a defect-free EUVL mask is currently an obstacle. Actual adoption of EUVL for 22 nm and beyond technology nodes will depend on the extension of current optical lithography (193 nm immersion lithography, combined with multiple patterning techniques), as well as other methods such as 3D IC. Lithography has been the enabler for IC performance improvement by increasing device density, clock rate, and transistor rate. However, after the turn of the century, IC scaling resulted in short-channel effect, which decreases power efficiency dramatically, so clock frequency almost stopped increasing. Although further IC scaling by lithography reduces gate delay, interconnect delay and memory wall are dominant in determining the IC performance. 3D IC technology is a critical technology today because it offers a reasonable route to further improve IC performance. It increases device density, reduces the interconnect delay, and breaks memory wall with the application of 3D stacking using through silicon via. 3D IC also makes one chip package have more functional diversification than those enhanced only by shrinking the size of the features. The main advantages of 3D IC are the smaller form factor, low energy consumption, high speed, and functional diversification. EUVL, if adopted, will continue to enable IC performance improvement at a slower rate, but 3D IC provides an alternative way to improve the system performance. The best scenario is the adoption of both EUVL and 3D IC. However, the possible further delay of EUVL could enhance the realization of 3D IC for IC system improvement.

Wu, Banqiu; Kumar, Ajay

2014-03-01

351

Heterogeneous GaSb/SOI mid-infrared photonic integrated circuits for spectroscopic applications  

NASA Astrophysics Data System (ADS)

Mid-infrared spectroscopy has gained significant importance in recent years as a detection technique for substances that absorb in this spectral region. Traditionally, a spectroscopic system consists of bulky equipment which is difficult to handle and incurs high cost. An integrated spectroscopic system would eliminate these disadvantages. GaSb-based active opto-electronic devices allow realizing mid-infrared light sources and detectors in the 2-3?m wavelength range for such integrated systems. Silicon photonics, based on Silicon-on-Insulator (SOI) waveguide circuits, on the other hand, is a well established technology based on high refractive index contrast waveguides, enabling ultra-compact passive integrated photonic circuits. Moreover, SOI waveguide circuit processing is compatible with CMOS processes. Hence, the integration of GaSb-based active devices onto SOI passive waveguide circuits potentially allows highly compact spectroscopic systems with a large degree of freedom in passive device design to improve the system performance. This approach has a high potential for several applications, e.g. an implantable glucose level monitor and gas sensing devices. In this paper, we report our work on the integration of GaSb-based epitaxy onto SOI waveguide circuits. The heterogeneous integration is based on an epitaxial layer transfer process using the polymer divinylsiloxanebenzocyclobutene (DVS-BCB) as a bonding agent. The process is performed by transferring the epitaxial layer to an SOI waveguide circuit wafer through a die-to-wafer bonding process. With this approach, a bonding layer of 150 nm thickness is easily achievable. We also report our results on the integration of waveguide-based GaSb p-i-n photodetectors coupled to SOI waveguide circuits using evanescent coupling, which show a responsivity higher than 0.4A/W. The design of active and passive structures and the overall fabrication process will also be discussed.

Hattasan, N.; Cerutti, L.; Rodriguez, J. B.; Tournié, E.; Van Thourhout, D.; Roelkens, G.

2011-01-01

352

Local CRH Signaling Promotes Synaptogenesis and Circuit Integration of Adult-Born Neurons.  

PubMed

Neural activity either enhances or impairs de novo synaptogenesis and circuit integration of neurons, but how this activity is mechanistically relayed in the adult brain is largely unknown. Neuropeptide-expressing interneurons are widespread throughout the brain and are key candidates for conveying neural activity downstream via neuromodulatory pathways that are distinct from classical neurotransmission. With the goal of identifying signaling mechanisms that underlie neuronal circuit integration in the adult brain, we have virally traced local corticotropin-releasing hormone (CRH)-expressing inhibitory interneurons with extensive presynaptic inputs onto new neurons that are continuously integrated into the adult rodent olfactory bulb. Local CRH signaling onto adult-born neurons promotes and/or stabilizes chemical synapses in the olfactory bulb, revealing a neuromodulatory mechanism for continued circuit plasticity, synapse formation, and integration of new neurons in the adult brain. PMID:25199688

Garcia, Isabella; Quast, Kathleen B; Huang, Longwen; Herman, Alexander M; Selever, Jennifer; Deussing, Jan M; Justice, Nicholas J; Arenkiel, Benjamin R

2014-09-29

353

6-1 Research Centers MTL Annual Research Report 2008 Center for Integrated Circuits and Systems  

E-print Network

, Intel, IBM, Linear Technology, Marvell Technology Group, Maxim Integrated Products, Media Tek, National may invite students to give on-site presentations, or they may offer students summer employment believe that it will have a lasting impact on the field of integrated circuits and systems. Research

Reif, Rafael

354

Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends  

Microsoft Academic Search

Integrated circuit (IC) testing for quality assurance is approaching 50% of the manufacturing costs for some complex mixed-signal ICs. For many years the market growth and technology advancements in digital ICs were driving the developments in testing. The increasing trend to integrate information acquisition and digital processing on the same chip has spawned increasing attention to the test needs of

Andrew Grochowski; Debashis Bhattacharya; T. R. Viswanathan; Ken Laker

1997-01-01

355

40 Gb\\/s integrated clock and data recovery circuit in a silicon bipolar technology  

Microsoft Academic Search

An integrated clock and data recovery circuit (CDR) applying the PLL technique has been developed for future optical transmission systems. It is fabricated in a 0.5 ?m\\/50 GHz fT double-polysilicon bipolar technology using only production-like process steps. The circuit operates up to 40 Gb\\/s, which is the highest operating speed to date for this type of IC in a silicon

M. Wurzer; J. Bock; W. Zirwasx; H. Knapp; F. Schumann; A. Felder; L. Treitinger

1998-01-01

356

20 Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency  

Microsoft Academic Search

Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA\\/cm2 Nb\\/AlOx\\/Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoNx resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 mum; total

Sergey K. Tolpygo; D. Yohannes; R. T. Hunt; J. A. Vivalda; D. Donnelly; D. Amparo; A. F. Kirichenko

2007-01-01

357

Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.  

PubMed

We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data. PMID:24921554

LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

2014-06-01

358

A circuit method to integrate metamaterial and graphene in absorber design  

NASA Astrophysics Data System (ADS)

We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

2014-10-01

359

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation  

NASA Technical Reports Server (NTRS)

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.

1980-01-01

360

"Double exposure method": a novel photolithographic process to fabricate flexible organic field-effect transistors and circuits.  

PubMed

A novel process called "double exposure method" has for the first time been developed to utilize common organic materials as insulating layers at low annealing temperature in the process of photolithography. In this method, organic dielectric layer will not dissolve in the final lift-off step by using developer to replace traditional acetone. Bottom-gate bottom-contact (BGBC) OFETs are fabricated on the flexible PET substrates with polystyrene (PS) and pentacene as dielectric layer and semiconductor layer, respectively. Transistors with mobility of 0.36 cm2 V(-1) s(-1) and logic inverter with gain of 9 on the plastic substrates have been fabricated, demonstrating the potential appliction of "double exposure method" in flexible organic electronics. PMID:23270576

Ji, Deyang; Jiang, Lang; Dong, Huanli; Meng, Qing; Wang, Zongrui; Zhang, Hantang; Hu, Wenping

2013-04-10

361

Method and apparatus for in-system redundant array repair on integrated circuits  

DOEpatents

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

2007-12-18

362

Substrate Integrated Circuits (SICs) for Terahertz Electronics and Photonics: Current Status and Future Outlook  

NASA Astrophysics Data System (ADS)

This paper attempts to provide a panoramic picture of research and development of substrate integrated circuits (SICs), presumably the next generation of integrated circuits for GHz and THz electronics and photonics. Current status and future outlook of SICs-related research and development are briefly discussed with focus on THz. WITH interest in low-cost and matured cmos and si-related technologies, we examine the possibility of developing innovative SICs within such platforms. This may be enabled by rapid deployment of through-silicon via (TSV) processes and related 3-D silicon stacking techniques as well as material research progress such as nanostructured techniques in this way, SICs may allow us to anticipate and extrapolate the trends of their applications towards the THz frequency range where no tangible integrated circuits technology is available yet to date. Challenging issues and future directions are considered, pointing to a potentially cost-effective and performance-promising ICs solution for mass commercial applications.

Wu, Ke

2011-09-01

363

Electron and optical beam testing of integrated circuits using CIVA, LIVA, and LECIVA  

SciTech Connect

Charge-Induced Voltage Alteration (CIVA), Light-Induced Voltage Alteration, (LIVA), and Low Energy CIVA (LECIVA) are three new failure analysis imaging techniques developed to quickly localize defects on ICs. All three techniques utilize the voltage fluctuations of a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA yield rapid localization of open interconnections on ICs. LIVA allows quick localization of open-circuited and damaged semiconductor junctions. LIVA can also be used to image transistor logic states and can be performed from the backside of ICs with an infrared laser source. The physics of signal generation for each technique and examples of their use in failure analysis are described.

Cole, E.I. Jr.

1995-09-01

364

Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics  

E-print Network

In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. ...

Chung, Jinwook W. (Jinwook Will)

2011-01-01

365

Organic thin-film transistors: Characterization and integration on low temperature substrates for flexible electronics  

Microsoft Academic Search

In this work pentacene thin-film transistors (TFTs) are fabricated and characterized on low temperature substrates for flexible electronic applications. Maximum processing temperature is <120°C. Pentacene transistors are optimized by varying the deposition conditions, thickness ratio of source-drain metal contact to pentacene film. By using parylene as the gate dielectric film, pentacene TFTs with low threshold voltage (VT) and low V

Srinivas Gowrisanker

2009-01-01

366

Diagnostics of doping integrity in n+/p/n+ transistor-channel structure by scanning nonlinear dielectric microscopy  

NASA Astrophysics Data System (ADS)

Scanning nonlinear dielectric microscopy was used to diagnose doping integrity in a transistor channel. The carrier state at various points in a pn junction was defined as n-type, p-type, or depletion through nonlinear capacitance (dC/dV) profiling and pinpoint capacitance-voltage analysis. Carrier state analysis was applied to the n+/p/n+ transistor channel of structures with different process parameters. An increase in the n+ activation temperature from 800 to 950 °C caused shrinkage in channel length of the p-type region. Decreasing the substrate acceptor concentration from 1018 to 1017 cm-3 caused depletion of the entire channel when the gate length was less than 200 nm.

Matsukawa, Takashi; Yasumuro, Chiaki; Masahara, Meishoku; Tanoue, Hisao; Kanemaru, Seigo

2004-04-01

367

Pixelwise readout integrated circuits with pixel-level ADC for microbolometers  

NASA Astrophysics Data System (ADS)

Pixelwise integrated circuits involving a pixel-level analog-to-digital converter (ADC) are studied for 320 × 240 microbolometer focal plane arrays (FPAs). It is necessary to use the pixelwise readout architecture for decreasing the thermal noise. However, it is hard to locate a sufficiently large integration capacitor in a unit pixel of FPAs because of the area limitation. To effectively overcome this problem, a two step integration method is proposed. First, after integrating the current of the microbolometer for 32?s, upper 5bits of the 13bit digital signal are output through a pixel-level ADC. Then, the current of the microbolometer is integrated during 1ms after the skimming current correction using upper 5bits in a field-programmable gate array (FPGA), and then lower 8bits are obtained through a pixel-level ADC. Finally, upper 5bits and lower 8bits are combined into the digital image signal after the gain and offset correction in digital signal processor (DSP) Each 2×2 pixel shares an readout circuit, including a current-mode background skimming circuit, an operational amplifier(op-Amp), an integration capacitor and a single slope ADC. When the current of a microbolometer is integrated, the integration capacitor is connected between a negative input and an output of the op-Amp. Therefore a capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. When the output of a microbolometer is converted to digital signal, the Op-Amp is used as a comparator of the single slope ADC. This readout circuit is designed to achieve 35×35?m2 pixel size in 0.35?m 2-poly 3-metal CMOS technology.

Hwang, C. H.; Kim, C. B.; Lee, Y. S.; Yu, B. G.; Lee, H. C.

2007-04-01

368

Molten-Caustic-Leaching (MCL or Gravimelt) System Integration Project. Topical report for test circuit operation  

SciTech Connect

This is a report of the results obtained from the operation of an integrated test circuit for the Molten-Caustic-Leaching (MCL or Gravimelt) process for the desulfurization and demineralization of coal. The objectives of operational testing of the 20 pounds of coal per hour integrated MCL test circuit are: (1) to demonstrate the technical capability of the process for producing a demineralized and desulfurized coal that meets New Source Performance Standards (NSPS); (2) to determine the range of effective process operation; (3) to test process conditions aimed at significantly lower costs; and (4) to deliver product coal.

Not Available

1990-11-01

369

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits  

SciTech Connect

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F. [CEA, Bruyeres-le-Chatel (France)] [CEA, Bruyeres-le-Chatel (France)

1998-06-01

370

Automated extraction of the passive distribution network of an integrated circuit for the assessment of conducted electromagnetic emission  

Microsoft Academic Search

This paper introduces an automated extraction flow for the passive distribution network (PDN) of a complex integrated circuit. This extraction makes it possible to predict the propagation of external and internal electromagnetic disturbances on power supply networks inside the circuit and, consequently, to have a better knowledge of the conducted emission and immunity of this circuit. This method can be

J. Cordi; A. Alaeldine; J.-L. Levant; R. Perdriau; M. Ramdani; P. Pinel

2008-01-01

371

Integrated circuit failure analysis by low-energy charge-induced voltage alteration  

DOEpatents

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

Cole, Jr., Edward I. (2116 White Cloud St., NE., Albuquerque, NM 87112)

1996-01-01

372

Built-In Test from the chip up - Self-testing integrated circuit design methodologies  

NASA Astrophysics Data System (ADS)

Design techniques for implementing BIT on the integrated circuit level are described, along with the voting circuitry and BIT functions. It is pointed out that the application of BITE on a chip level offers the potential of significantly reducing repair time, increasing maintainability, and increasing system reliability. BIT on IC substrates can be easily implemented using component redundant circuits and an appropriate voting circuit. A simple binary comparator can be used to compare outputs from digital logic circuits, and a window comparator can be used to compare analog paths. It is suggested that the application of nonvolatile memory and system status communication circuitry can extend the usefulness of the reconfigurable analog fault-tolerant IC architecture.

Ferrell, John

1988-09-01

373

CMOS RF Integrated Circuits: Past, Present and Future (Invited)  

Microsoft Academic Search

CMOS RF ICs continue their transition from academic curiosities to practical devices. Recent milestones at the device- and building block-level include: Noise figures for single-ended LNAs of ~ldB in the low-GHz range; fully integrated oscillators with phase noise compliant with GSM specifications at under lOmW power consumption; 5GHz injection-locked frequency dividers with sub-mW power consumption and large (~30%) tuning range;

Thomas H. Lee

1999-01-01

374

A functional validation methodology based on error models for measuring the quality of digital integrated circuits  

NASA Astrophysics Data System (ADS)

Functional validation plays an important role in the design cycle of digital integrated circuits. The generation of good test benches is required for checking the complete circuit behaviour. Early location of design errors could highly reduce the development time and cost for these circuits. There are several initiatives for the development of methods that enhance the functional validation of a design. Traditionally, logic abstraction level has been most employed for this purpose, but recent years have shown a strong trend to treat the problem at higher abstraction levels, where design teams normally work. High abstraction levels and automatic synthesis tools are currently being used in top-down methodology. These aspects make difficult to find out design errors when the circuit is described in lower levels of abstraction. It is crucial to obtain a complete functional validation system applicable in the first design stages, where circuits are currently being designed, and also usable along the whole design process for further test plans. In this paper we propose a complete methodology for performing high quality functional validation. The proposed method checks the capability of a given test bench to detect design errors in a circuit description. This checking employs functional simulation of the circuit description at RT level together with the application of error models. An automatic and formal protocol has been developed so that design teams could apply it with no extra effort. The method provides a measurement of the quality of functional validation as well as the location of non-enough validated areas in the circuit. Therefore, the proposed method helps designers in the process of performing the functional validation of their circuits, which could be applied automatically from RT descriptions to lower abstraction levels. Finally, experimental results have proved the correctness of the proposed method as well as the error models applied.

Lopez-Ongil, Celia; Entrena-Arrontes, Luis; Riesgo-Alcaide, Teresa; Uceda-Antolin, Javier

2005-06-01

375

Recent progress in integration of III-V nanowire transistors on Si substrate by selective-area growth  

NASA Astrophysics Data System (ADS)

We report on the recent progress in electronic applications using III-V nanowires (NWs) on Si substrates using the selective-area growth method. This method could align vertical III-V NWs on Si under specific growth conditions. Detailed studies of the III-V NW/Si heterointerface showed the possibility of achieving coherent growth regardless of misfit dislocations in the III-V/Si heterojunction. The vertical III-V NWs grown using selective-area growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III-V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III-V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

Tomioka, Katsuhiro; Fukui, Takashi

2014-10-01

376

The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits  

Microsoft Academic Search

The Waveform Relaxation (WR) method is an iterative method for analyzing nonlinear dynamical systems in the time domain. The method, at each iteration, decomposes the system into several dynamical subsystems each of which is analyzed for the entire given time interval. Sufficient conditions for convergence of the WR method are proposed and examples in MOS digital integrated circuits are given

Ekachai Lelarasmee; Albert E. Ruehli; Alberto L. Sangiovanni-vincentelli

1982-01-01

377

Internet vs. Circuit Switched Telephony: Cost and QoS of Large Scale Integrated Services  

E-print Network

Internet vs. Circuit Switched Telephony: Cost and QoS of Large Scale Integrated Services Networks December 28, 1998 Abstract Telephony is an Internet application that has the potential to radically alter, business models, etc. Today, users can transmit telephone-like voice trac over the Internet at zero

378

Parasitic modes on printed circuit boards and their effects on EMC and signal integrity  

Microsoft Academic Search

In this paper, parasitic modes, such as slotline, parallel plane, and surface wave (SW) modes, commonly found on printed circuit boards (PCBs) are analyzed and their effects on electromagnetic compatibility (EMC) and signal integrity are discussed. The analysis is based on numerical simulations using the finite difference time domain (FDTD) method which is shown to be very well suited for

Christian Schuster; Wolfgang Fichtner

2001-01-01

379

Hot-Spot Detection in Integrated Circuits by Substrate Heat-Flux Sensing  

Microsoft Academic Search

This letter presents a novel approach to detect hot spots (HSs) in active integrated circuits (ICs) and devices. It is based on sensing the HS heat flux within the chip substrate with a probe-laser beam. As the beam passes through the die, it experiences a deflection directly proportional to the heat flux found along its trajectory (internal infrared laser deflection

X. Perpina; J. Altet; X. Jorda; M. Vellvehi; J. Millan; N. Mestres

2008-01-01

380

Organic film and contaminant removal from surfaces in the manufacture of integrated circuits  

Microsoft Academic Search

This work focuses on the development of novel approaches to organic film removal, surface cleaning, and conditioning that ensures compatibility of this critical fabrication step with vacuum sequences in integrated circuit (IC) manufacturing. The general approach investigated for organic film and contaminant removal is the use of a fluid under elevated temperature and pressure conditions. A fluid in the vicinity

2000-01-01

381

User-oriented development and production of integrated circuits in small and medium quantities  

NASA Astrophysics Data System (ADS)

User-orientated integrated circuit (IC) computer assisted design systems, standard cells, and high resolution analog to digital converters were developed. Interfaces for development and layout of custom IC by the user were verified. Linearity tests show a variance of 3 digits for a resolution of 2,000,000 digits. The unit replaces a full component plate of 6 by 10 cm.

Flocke, H.; Schneidewind, K. E.; Beck, G.

1984-08-01

382

Hybrid Integrated Circuit Manufacturing Process as Controlled by Shop Information Systems  

Microsoft Academic Search

Hybrid integrated circuits (HIC's) used in Bell System transmission equipment are rapidly increasing in numbers, type, and complexity. An efficient and effective system of controlling and monitoring the HIC manufacturing process is therefore of prime importance if scheduling, inventory, product yield, and operator performance are to be accurately determined. The major sequence of operations is described of both thin- and

D. Krause; D. Locy

1980-01-01

383

Modeling, analysis and design of integrated magnetics for modern power electronics circuits  

Microsoft Academic Search

Summary form only as given. In modern power electronic circuits, such as power-factor-corrected regulators and cascaded converters, multiple numbers of electronic switches and magnetic components are often used. A lot of research work has been carried out to integrate the electronic switches so as to reduce the number of switches required and the cost. However, not much systematic work on

D. K. W. Cheng; L. P. Wong; Y. S. Lee

1999-01-01

384

May 20, 2014 Page 1 of 26 Sahu and Rincn-Mora Analog Integrated Circuits Laboratory  

E-print Network

May 20, 2014 Page 1 of 26 Sahu and Rincón-Mora Analog Integrated Circuits Laboratory Georgia Tech, GA 30332 USA E-mail: {bsahu, rincon-mora}@ece.gatech.edu Address for Correspondence Biranchinath Sahu-inverting, Synchronous Buck­Boost Converter for Portable Applications Biranchinath Sahu, Student Member, IEEE

Rincon-Mora, Gabriel A.

385

An investigation on the plasma treatment of integrated circuit bond pads  

Microsoft Academic Search

Integrated circuit (IC) bond pads play an important role in the wire bond reliability of the microelectronic devices. Being the device’s only electrical connection to the package and electronic systems, it is mandatory that the bond pads are free of contaminants and possess excellent bonding characteristics. Contaminants such as oxides and organic residues impair the bondability to a considerable extent

Y. F Chong; R Gopalakrishnan; C. F Tsang; G Sarkar; S Lim; S Tatti

2000-01-01

386

Stresa, Italy, 25-27 April 2007 REDUCED 30% SCANNING TIME 3D MULTIPLEXER INTEGRATED CIRCUIT  

E-print Network

Stresa, Italy, 25-27 April 2007 - - REDUCED 30% SCANNING TIME 3D MULTIPLEXER INTEGRATED CIRCUIT,2,3 1 MEMS Inst., 2 Engineering and System Science Dept. National Tsing Hua University, Taiwan, ROC. 3 Division of Mechanics, Research Center for Applied Sciences, Academia Sinica, Taiwan, ROC ABSTRACT

Paris-Sud XI, Université de

387

Using Bzier Curve to Improve the Accuracy in Integrated Circuit Design Analysis  

E-print Network

provide smoother curves than piecewise linear functions. Among polynomial nonlinear curves, B-splines to the knots using CAD tools is sometime necessary to obtain an ideal spline curve. B-spline curves have bUsing Bézier Curve to Improve the Accuracy in Integrated Circuit Design Analysis Eric Y. Chen

Tomkins, Andrew

388

Classification of the Marking on Integrated Circuit Chips Based on Moments and Projection Profile - A Comparison  

Microsoft Academic Search

In this paper, an Industrial machine vision system incorporating Optical Character Recognition (OCR) is employed to inspect the marking on the Integrated Circuit (IC) Chips. This inspection is carried out while the ICs are coming out from the manufacturing line. A TSSOP-DGG type of IC package from Texas Instrument is used in the investigation. The IC chips are laser printed.

M. Karthigayan; R. Nagarajan; Sazali Yaacob; Paulraj Pandian; Mohammed Rizon; Shamsudin Hj Amin; Marzuki Khalid

389

Stress-induced voiding study in integrated circuit interconnects  

NASA Astrophysics Data System (ADS)

An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

Hou, Yuejin; Tan, Cher Ming

2008-07-01

390

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications  

DOEpatents

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Schwank, James R. (Albuquerque, NM); Shaneyfelt, Marty R. (Albuquerque, NM); Draper, Bruce L. (Albuquerque, NM); Dodd, Paul E. (Tijeras, NM)

2001-01-01

391

Computer-aided design of analog and mixed-signal integrated circuits  

Microsoft Academic Search

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing

GEORGES G. E. GIELEN; ROB A. RUTENBAR

2000-01-01

392

High-performance low-noise 128-channel readout-integrated circuit for flat-panel x-ray detector systems  

NASA Astrophysics Data System (ADS)

A silicon mixed-signal integrated circuit is needed to extract and process x-ray induced signals from a coated flat panel thin film transistor array (TFT) in order to generate a digital x-ray image. Indigo Systems Corporation has designed, fabricated, and tested such a readout integrated circuit (ROIC), the ISC9717. This off-the-shelf, high performance, low-noise, 128-channel device is fully programmable with a multistage pipelined architecture and a 9 to 14-bit programmable A/D converter per channel, making it suitable for numerous X-ray medical imaging applications. These include high-resolution radiography in single frame mode and fluoroscopy where high frame rates are required. The ISC9717 can be used with various flat panel arrays and solid-state detectors materials: Selenium (Se), Cesium Iodide (CsI), Silicon (Si), Amorphous Silicon, Gallium Arsenide (GaAs), and Cadmium Zinc Telluride (CdZnTe). The 80-micron pitch ROIC is designed to interface (wire bonding or flip-chip) along one or two sides of the x-ray panel, where ROICs are abutted vertically, each reading out charge from pixels multiplexed onto 128 horizontal read lines. The paper will present the design and test results of the ROIC, including the mechanical and electrical interface to a TFT array, system performance requirements, output multiplexing of the digital signals to an off-board processor, and characterization test results from fabricated arrays.

Beuville, Eric J.; Belding, Mark; Costello, Adrienne N.; Hansen, Randy; Petronio, Susan M.

2004-05-01

393

Characterization of temperature sensor using VT extractor circuit  

Microsoft Academic Search

The semiconductor (or IC for integrated circuit) temperature sensor is an electronic device fabricated in a similar way to other modern electronic semiconductor components such as microprocessors, diode, transistors, capacitors and etc. There are few temperature sensors being used in nowadays i.e diode type and threshold voltage (VT) extractor type. Normally hundreds or thousands of devices are formed on single

Hazian Mamat; Y. Yusoff; I. M. Yusof; W. Suradi; Tan Kong Yew

2009-01-01

394

Escherichia coli Flagellar Genes as Target Sites for Integration and Expression of Genetic Circuits  

PubMed Central

E. coli is a model platform for engineering microbes, so genetic circuit design and analysis will be greatly facilitated by simple and effective approaches to introduce genetic constructs into the E. coli chromosome at well-characterised loci. We combined the Red recombinase system of bacteriophage ? and Isothermal Gibson Assembly for rapid integration of novel DNA constructs into the E. coli chromosome. We identified the flagellar region as a promising region for integration and expression of genetic circuits. We characterised integration and expression at four candidate loci, fliD, fliS, fliT, and fliY, of the E. coli flagellar region 3a. The integration efficiency and expression from the four integrations varied considerably. Integration into fliD and fliS significantly decreased motility, while integration into fliT and fliY had only a minor effect on the motility. None of the integrations had negative effects on the growth of the bacteria. Overall, we found that fliT was the most suitable integration site. PMID:25350000

Juhas, Mario; Evans, Lewis D. B.; Frost, Joe; Davenport, Peter W.; Yarkoni, Orr; Fraser, Gillian M.; Ajioka, James W.

2014-01-01

395

A SQUID gradiometer module with wire-wound pickup antenna and integrated voltage feedback circuit  

NASA Astrophysics Data System (ADS)

The performance of the direct readout schemes for dc SQUID, Additional Positive Feedback (APF), noise cancellation (NC) and SQUID bootstrap circuit (SBC), have been studied in conjunction with planar SQUID magnetometers. In this paper, we examine the NC technique applied to a niobium SQUID gradiometer module with an Nb wire-wound antenna connecting to a dual-loop SQUID chip with an integrated voltage feedback circuit for suppression of the preamplifier noise contribution. The sensitivity of the SQUID gradiometer module is measured to be about 1 fT/(cm ?Hz) in the white noise range in a magnetically shielded room. Using such gradiometer, both MCG and MEG signals are recorded.

Zhang, Guofeng; Zhang, Yi; Zhang, Shulin; Krause, Hans-Joachim; Wang, Yongliang; Liu, Chao; Zeng, Jia; Qiu, Yang; Kong, Xiangyan; Dong, Hui; Xie, Xiaoming; Offenhäusser, Andreas; Jiang, Mianheng

2012-10-01

396

The simulation of a readout integrated circuit with high dynamic range for long wave infrared FPA  

NASA Astrophysics Data System (ADS)

This paper describes the simulation results of a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors, which has high dynamic range (HDR). A special architecture is used to the input unit cell to accommodate the wide scene dynamic range requirement, thus providing over a factor of 70dB dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents and a folded cascade amplifier with a gain of 73dB is designed. A 6.4pF integration capacitor is used for supporting a wide scene dynamic range, which can store 80Me. Because of the restriction of the layout area, four unit cells will share an integration capacitor. A sample and hold capacitor is also part of the input unit cell architecture, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled by an external clock pulse. The simulation results show that the circuit works well under 5V power supply and the nonlinearity is calculated less than 0.1%. The total power dissipation is less than 150mW.

Zhai, Yongcheng; Ding, Rui-jun; Chen, Guo-qiang; Wang, Pan; Hao, Li-chao

2013-12-01

397

Page 1 of 5 Using transistors as switches  

E-print Network

Page 1 of 5 Using transistors as switches by Dan Morris Intro A key aspect of proper hacking is the use of transistors for switching things on and off. A typical example is using a computer's parallel at the silicon level in a transistor. So every time I used a transistor circuit in a project, I would promptly

Salisbury, Kenneth

398

Sleep Transistor Sizing and Control for Resonant Supply  

E-print Network

1 Sleep Transistor Sizing and Control for Resonant Supply Noise Damping Jie Gu, Hanyong Eom@ece.umn.edu www.umn.edu/~chriskim/ #12;2 Outline · Introduction · Conventional Sizing of Sleep Transistors · Sleep Transistor Sizing Considering Resonant Supply Damping · Adaptive Sleep Transistor Circuit · Conclusions #12

Kim, Chris H.

399

Moving the boundary between wavelength resources in optical packet and circuit integrated ring network.  

PubMed

Optical packet and circuit integrated (OPCI) networks provide both optical packet switching (OPS) and optical circuit switching (OCS) links on the same physical infrastructure using a wavelength multiplexing technique in order to deal with best-effort services and quality-guaranteed services. To immediately respond to changes in user demand for OPS and OCS links, OPCI networks should dynamically adjust the amount of wavelength resources for each link. We propose a resource-adjustable hybrid optical packet/circuit switch and transponder. We also verify that distributed control of resource adjustments can be applied to the OPCI ring network testbed we developed. In cooperation with the resource adjustment mechanism and the hybrid switch and transponder, we demonstrate that automatically allocating a shared resource and moving the wavelength resource boundary between OPS and OCS links can be successfully executed, depending on the number of optical paths in use. PMID:24514964

Furukawa, Hideaki; Miyazawa, Takaya; Wada, Naoya; Harai, Hiroaki

2014-01-13

400

SOI single-electron transistor with low RC delay for logic cells and SET\\/FET hybrid ICs  

Microsoft Academic Search

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET\\/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the

Kyu-Sul Park; Sang-Jin Kim; In-Bok Baek; Won-Hee Lee; Jong-Seuk Kang; Yong-Bum Jo; Sang Don Lee; Chang-Keun Lee; Jung-Bum Choi; Jang-Han Kim; Keun-Hyung Park; Won-Ju Cho; Moon-Gyu Jang; Seong-Jae Lee

2005-01-01

401

Photonic integrated circuit on InP for millimeter wave generation  

NASA Astrophysics Data System (ADS)

Indium phosphide and associated epitaxially grown alloys is a material system of choice to make photonic integrated circuits for microwave to terahertz signal generation, processing and detection. Fabrication of laser emitters, high speed electro-optical modulators, passive waveguides and couplers, optical filters and high speed photodetectors is well mastered for discrete devices. But monolithic integration of them while maintaining good performances is a big challenge. We have demonstrated a fully integrated tunable heterodyne source designed for the generation and modulation of sub-Terahertz signals. This device is to be used for high data-rate wireless transmissions. DFB lasers, SOA amplifiers, passive waveguides, beam combiners, electro-optic modulators and high speed photodetectors have been integrated on the same InP-based platform. Millimeter wave generation at up to 120 GHz based on heterodyning the optical tones from two integrated lasers in an also integrated high bandwidth photodetector has been obtained.

van Dijk, Frederic; Lamponi, Marco; Chtioui, Mourad; Lelarge, François; Kervella, Gaël.; Rouvalis, Efthymios; Renaud, Cyril; Fice, Martyn; Carpintero, Guillermo

2014-03-01

402

Advances in Linear Modeling of Microwave Transistors  

Microsoft Academic Search

Heterojunction field effect transistors (HFET) based on gallium nitride (AlGaN\\/GaN) and metal semiconductor field effect transistors (MESFETs) based on silicon carbide (SiC) are the preferred transistors for high-power amplifier circuit designs rather than MESFETs, high electron mobility transistors (HEMTs) and pseudomorphic HEMTs based on gallium arsenide (GaAs) or indium phosphide (InP) semiconductor technology. While AlGaN\\/GaN and SiC are good candidates

Andres Zarate-de Landa; José Eleazar Zúñiga-Juárez; José Raúl Loo-Yau; J. Reynoso-Hernandez; Maria Maya-Sanchez; Juan Luis del Valle-Padilla

2009-01-01

403

A new circuit model of HgCdTe photodiode for SPICE simulation of integrated IRFPA  

NASA Astrophysics Data System (ADS)

We propose a novel sub circuit model to simulate HgCdTe infrared photodiodes in a circuit simulator, like PSPICE. We have used two diodes of opposite polarity in parallel to represent the forward biased and the reverse biased behavior of an HgCdTe photodiode separately. We also connected a resistor in parallel with them to represent the ohmic shunt and a constant current source to represent photocurrent. We show that by adjusting the parameters in standard diode models and the resistor and current values, we could actually fit the measured data of our various HgCdTe photodiodes having different characteristics. This is a very efficient model that can be used for simulation of readout integrated circuit (ROIC) for HgCdTe IR photodiode arrays. This model also allows circuit level Monte Carlo simulation on a complete IRFPA at a single circuit simulator platform to estimate the non-uniformity for given processes of HgCdTe device fabrication and Si ROIC fabrication.

Saxena, Raghvendra Sahai; Saini, Navneet Kaur; Bhan, R. K.; Sharma, R. K.

2014-11-01

404

Analog Integrated Circuit for Motion Detection with Simple-Shape Recognition Based on Frog Vision System  

NASA Astrophysics Data System (ADS)

We proposed in this research a novel two-dimensional network based on the frog visual system, with a motion detection function and a newly developed simple-shape recognition function, for use in object discrimination by integrated circuits. Specifically, the network mimics the signal processing of the small-field cell in a frog brain, consisting of the tectum and thalamus, which generates signals of the motion and simple shape of an object. The proposed network is constructed from simple analog complementary metal oxide semiconductor (CMOS) circuits; a test chip of the proposed network was fabricated with a 1.2 ?m CMOS process. Measurements on the chip clarified that the proposed network can generate signals of the moving direction, velocity, and simple shape, as well as perform information processing of the small-field cell. Results with the simulation program with integrated circuit emphasis (SPICE) showed that the analog circuits used in the network have low power consumption. Applications of the proposed network are expected to realize advanced vision chips with functions such as object discrimination and target tracking.

Nishio, Kimihiro; Yonezu, Hiroo; Furukawa, Yuzo

2007-09-01

405

Organic Transistors on Fiber: A first step towards electronic textiles Josephine B. Lee and Vivek Subramanian  

E-print Network

, actuation, and displays into clothing and surface coverings. With the performance and interconnection from a viable e-textile technology; fiber transistors will enable cloth-based large-area circuits-textile interconnection/integration. 250 µm and 500 µm diameter Al wires were used as gate lines. These may be directly

California at Irvine, University of

406

High-Performance Contacts in Plastic Transistors and Logic Gates That Use Printed Electrodes of  

E-print Network

with micrometer (~ 5 lm) resolution over large areas (well over 3 m2 ) and with multilevel registration (maximum are simple enough that registration errors and multilevel stack integrity are not limiting. In addition (DNNSA-PANI/SWNT) electrodes to pro- duce n- and p-type transistors and complementary inverter circuits

Rogers, John A.

407

Magnetically-coupled current sensors using CMOS split-drain transistors  

Microsoft Academic Search

Integrated current sensing circuits intended for Smart-Power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using the CMOS compatible split-drain transistor (MAGFET) that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field. The Coil approach and the Strip approach. In the first one the current

F. C. Castaldo; V. R. Mognon; C. A. dos Reis Filho

2008-01-01

408

XI Conference on Design of Integrated Circuits and Systems (DCIS'96), Sitges (Barcelona), November 19-22, 1996, pp. 411-416. A Co-Synthesis Environment for  

E-print Network

XI Conference on Design of Integrated Circuits and Systems (DCIS'96), Sitges (Barcelona), November to guide the #12;XI Conference on Design of Integrated Circuits and Systems (DCIS'96), Sitges (Barcelona

Cardoso, João Manuel Paiva

409

Advances in gallium arsenide monolithic microwave integrated-circuit technology for space communications systems  

NASA Technical Reports Server (NTRS)

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. In this paper, current developments in GaAs MMIC technology are described, and the status and prospects of the technology are assessed.

Bhasin, K. B.; Connolly, D. J.

1986-01-01

410

Heavy-ion induced single-event upset in integrated circuits  

NASA Technical Reports Server (NTRS)

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Zoutendyk, J. A.

1991-01-01

411

Physics 326 Spring 2014 1/15/14 Lab 4: DIODES AND TRANSISTORS  

E-print Network

Physics 326 Spring 2014 1/15/14 1 Lab 4: DIODES AND TRANSISTORS Please read Faissler Chapters 4045. Goals: Study two rectifier circuits and 2 simple transistor circuits. This will be a one week and describe what happens. Fig. 2 the Full wave rectifier. B. Transistors. The transistor is one

Glashausser, Charles

412

High-sensitivity cytometric detection using fluidic-photonic integrated circuits with array waveguides  

Microsoft Academic Search

We demonstrate a new detection scheme for a microfabricated flow cytometer. The fluidic-photonic integrated circuits (FPICs) that perform flow cytometric detection possess new functionality, such as on-chip excitation, time-of-flight measurement, and above all, greatly enhanced fluorescence detection sensitivity. Using the architecture of space-division waveguide demultiplexer and the technique of cross-correlation analysis, we obtained high detection sensitivity with a simple light

Victor Lien; Kai Zhao; Yevgeny Berdichevsky; Yu-Hwa Lo

2005-01-01

413

A combination of FDTD and Prony's methods for analyzing microwave integrated circuits  

Microsoft Academic Search

It is demonstrated that in applying the FD-TD technique to analyze microwave integrated circuits, the long FD-TD time record required for generating accurate frequency domain scattering parameters can be extrapolated from a relatively short FD-TD time record by using Prony's method. As shown by comparison with the direct FD-TD generated results, the approach using the combination of FD-TD and Prony's

Wai Lee KO; Raj Mittra

1991-01-01

414

Basic structures for photonic integrated circuits in Silicon-on-insulator  

Microsoft Academic Search

For the compact integration of photonic circuits, wavelength-scale structures with a high index contrast are a key requirement. We developed a fabrication process for these nanophotonic structures in Silicon-on-insulator using CMOS processing techniques based on deep UV lithography. We have fabricated both photonic wires and photonic crystal waveguides and show that, with the same fabrication technique, photonic wires have much

W. Bogaerts; D. Taillaert; B. Luyssaert; P. Dumon; J. van Campenhout; P. Bienstman; D. van Thourhout; R. Baets; V. Wiaux; S. Beckx

2004-01-01

415

Reliability-yield allocation for semiconductor integrated circuits: modeling and optimization  

E-print Network

: : : : : : : : : : : : : : : 17 III.1. Manufacturing Yield . . . . . . . . . . . . . . . . . . . 18 III.2. Reliability of Semiconductor Integrated Circuits . . . 19 III.3. Defect Size, Defect Density, and Critical Area . . . . . 22 III.4. Poisson and Negative Binomial Yield... : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 36 IV.1. System Architecture of a Typical Memory IC . . . . . 36 IV.2. Yield Model with Redundancy . . . . . . . . . . . . . 39 IV.3. Yield Model with Various Types of Failures . . . . . . 40 IV.4. Yield Model with ECC...

Ha, Chunghun

2005-11-01

416

Hot spot detection in integrated circuits laterally accessing to their substrate using a laser beam  

Microsoft Academic Search

This work presents an approach to detect hot spots in active Integrated Circuits (IC) and devices. It is based on sensing the hot spot heat-flux within the chip substrate with a probe-laser beam. As the beam passes through the die, it experiences a deflection directly proportional to the heat-flux found along its trajectory (Internal InfraRed-Laser Deflection technique, IIR-LD). The proposed

X. Perpiña?; J. Altet; X. Jorda?; M. Vellvehi

2010-01-01

417

A SC rectification and bin-integration circuit for nerve signal processing: experimental results  

Microsoft Academic Search

In this paper, we describe a low-voltage CMOS switched-capacitor rectification and bin-integration (RBI) circuit dedicated to sensor electronic interfaces. The applications of these interfaces are among others, biomedical and more particularly the implantable devices. RBI is the most common signal processing function applied to the nerve signals. Since the frequency of these signals is below 10 kHz, a switched-capacitor architecture

A. Harb; M. Sawan

2003-01-01

418

Integrated circuit mask generation using a raster scanned laser trimming system  

E-print Network

OF SCIENCE May 1982 Major Subject: Electrical Engineering INTEGRATED CIRCUIT MASK GENERATION USING A RASTER SCANNED LASER TRIMMING SYSTEM A Thesis by KEVIN DWAYNE GOURLEY Approved as to style and content by: hair ma ommittee Dr . Dou as M. Green 4... is that of IC mask generation. The topics of mask generation and laser applications wer e explored and are discussed in this section. A general discussion of computer aided design concepts will then be presented. Mask Gener ation Mask generation...

Gourley, Kevin Dwayne

2012-06-07

419

Multi-Energy, Fast Counting Hybrid CZT Pixel Detector with Dedicated Readout Integrated Circuit  

Microsoft Academic Search

A new mixed signal front-end readout electronics integrated circuit (IC) called HILDA (Hyperspectral Imaging with Large Detector Arrays) has been developed for two-dimensional CdZnTe (CZT) pixel detector arrays. The CZT array is directly bonded on top of the IC. The CZT array and the HILDA-IC have matching geometric pixel\\/channel structure and dimensions, a 16times16 array of 0.5 mm times 0.5

Martin Clajus; Victoria B. Cajipe; Satoshi Hayakawa; T. O. Turner; Paul D. Willson

2006-01-01

420

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications  

Microsoft Academic Search

High-temperature power converters (dc–dc, dc–ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor

Mohammad A. Huque; Syed K. Islam; Leon M. Tolbert; Benjamin J. Blalock

2012-01-01

421

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement  

Microsoft Academic Search

Our application of an integrated-circuit (IC) temperature sensor which is easy-to-use, inexpensive, rugged, easily computer-interfacable and has good precision is described. The design, based on the National Semiconductor LM35 IC chip, avoids some of the difficulties associated with conventional sensors (thermocouples, thermistors, and platinum resistance thermometers) and a previously described IC sensor. The sensor can be used with a variety

Mark Muyskens

1997-01-01

422

A multilink active catheter with polyimide-based integrated CMOS interface circuits  

Microsoft Academic Search

This paper describes an active catheter with flexible polyimide-based integrated CMOS interface circuits for communication and control (C&C IC) to be used for applications in biomedicine. The active catheter has a multilink structure. Distributed micro shape memory alloy (SMA) coils are utilized as actuators for multidegree of freedom movement. The C&C IC's, which are incorporated on the links, require three

Ki-Tae Park; Masayoshi Esashi

1999-01-01

423

High-resolution differential thermography of integrated circuits with optical feedback laser scanning microscopy  

Microsoft Academic Search

We demonstrate a noninvasive technique for generating differential thermal maps of semiconductor edifices in integrated circuits (IC) at diffraction-limited resolution. An inexpensive optical feedback laser-scanning microscope detects changes in the optical beam-induced currents (OBIC) that are produced in the active layer in response to variations in the IC package temperature. The OBIC yield of a semiconductor normally increases with temperature.

Carlo Mar Blanca; Vernon Julius Cemine; Vera Marie Sastine; Caesar Saloma

2005-01-01

424

An integrated active-quenching circuit for single-photon avalanche diodes  

Microsoft Academic Search

We introduce the first integrated active quenching circuit (I-AQC) that drives an avalanche photodiode (APD) above its breakdown voltage, in order to detect single photons. Based on the I-AQC, we developed a compact and versatile photon-counting module suitable for applications in which very weak optical signals have to be detected, as for instance, photon correlation spectroscopy, luminescence measurements, and laser

Franco Zappa; Massimo Ghioni; Sergio Cova; Carlo Samori; Andrea Carlo Giudice

2000-01-01

425

A 2.7-4.5 V single chip GSM transceiver RF integrated circuit  

Microsoft Academic Search

This paper describes the design and implementation of a single-chip GSM (Global System for Mobile communications) transceiver RF integrated circuit. The chip includes the RF-to-baseband and baseband-to-RF (receive and transmit) functions, two fixed frequency PLL's, and a programmable frequency agile UHF synthesizer. It is implemented In a 1.5 ?m silicon bipolar process with 12 GHz NPN's and 110 MHz lateral

Trudy D. Stetzler; Irving G. Post; Joseph H. Havens; Mikio Koyama

1995-01-01

426

Molten-Caustic-Leaching (Gravimelt) System Integration Project, Phase 2. Topical report for test circuit operation  

SciTech Connect

The objective of the task (Task 6) covered in this document was to operate the refurbished/modified test circuit of the Gravimeh Process in a continuous integrated manner to obtain the engineering and operational data necessary to assess the technical performance and reliability of the circuit. This data is critical to the development of this technology as a feasible means of producing premium clean burning fuels that meet New Source Performance Standards (NSPS). Significant refurbishments and design modifications had been made to the facility (in particular to the vacuum filtration and evaporation units) during Tasks 1 and 2, followed by off-line testing (Task 3). Two weeks of continuous around-the-clock operation of the refurbished/modified MCL test circuit were performed. During the second week of testing, all sections of the plant were operated in an integrated fashion for an extended period of time, including a substantial number of hours of on-stream time for the vacuum filters and the caustic evaporation unit. A new process configuration was tested in which centrate from the acid wash train (without acid addition) was used as the water makeup for the water wash train, thus-eliminating the one remaining process waste water stream. A 9-inch centrifuge was tested at various solids loadings and at flow rates up to 400 lbs/hr of coal feed to obtain a twenty-fold scaleup factor over the MCL integrated test facility centrifuge performance data.

Not Available

1993-02-01

427

Integrated Low Power and High Bandwidth Optical Isolator for Monolithic Power MOSFETs Driver  

E-print Network

the remote control circuit and the power transistor. The most advanced and attractive solution so far isolation between power transistors and their control unit is presented in this paper. This solution solutions have been presented to date for the integration of the required isolation between the power switch

Paris-Sud XI, Université de

428

170 GHz Uni-Traveling Carrier Photodiodes for InP-based photonic integrated circuits.  

PubMed

We demonstrate the capability of fabricating extremely high-bandwidth Uni-Traveling Carrier Photodiodes (UTC-PDs) using techniques that are suitable for active-passive monolithic integration with Multiple Quantum Well (MQW)-based photonic devices. The devices achieved a responsivity of 0.27 A/W, a 3-dB bandwidth of 170 GHz, and an output power of -9 dBm at 200 GHz. We anticipate that this work will deliver Photonic Integrated Circuits with extremely high bandwidth for optical communications and millimetre-wave applications. PMID:23037061

Rouvalis, E; Chtioui, M; van Dijk, F; Lelarge, F; Fice, M J; Renaud, C C; Carpintero, G; Seeds, A J

2012-08-27

429

Threshold logic circuit design of parallel adders using resonant tunneling devices  

Microsoft Academic Search

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a

Christian Pacha; Uwe Auer; Christian Burwick; Peter Glösekötter; Andreas Brennemann; Werner Prost; F.-J. Tegude; K. F. Goser

2000-01-01

430

Magnetically Coupled Current Sensors Using CMOS Split-Drain Transistors  

Microsoft Academic Search

Integrated current-sensing circuits intended for smart-power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using a CMOS-compatible split-drain transistor that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field: the coil approach and the strip approach. In the first, the current to be sensed flows

Fernando C. Castaldo; Vilson R. Mognon; Carlos A. dos Reis Filho

2009-01-01

431

Superconducting flux flow digital circuits  

DOEpatents

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

Hietala, Vincent M. (Placitas, NM); Martens, Jon S. (Sunnyvale, CA); Zipperian, Thomas E. (Albuquerque, NM)

1995-01-01

432

Monolithic integrated enhancement/depletion-mode AlGaN/GaN high electron mobility transistors with cap layer engineering  

NASA Astrophysics Data System (ADS)

Monolithic integrated enhancement/depletion (E/D)-mode AlGaN/GaN high electron mobility transistors (HEMTs) are fabricated on an AlGaN/GaN heterostructure with an engineered triple-cap-layer. The energy band of the cap layer is greatly tailored by the polarizations within it, which improves the controllability of D-to-E mode conversion with gate recess. The uniformity of the threshold voltage (Vth) across a 3? wafer is assessed and the standard deviations of Vth are 0.1 V and 0.14 V for E-mode and D-mode devices, respectively. Direct-coupled field-effect transistor logic E/D HEMT inverter and 17-stage ring oscillator are demonstrated, and the latter shows a oscillation frequency of 201 MHz at a supply voltage of 1 V, corresponding to a propagation delay of 146 ps/stage and a power-delay product of 1.96 pJ/stage.

Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Zhang, Youtao; Lu, Haiyan; Chen, Tangsheng

2013-01-01

433

Design, Fabrication and Integration of a NaK-Cooled Circuit  

NASA Technical Reports Server (NTRS)

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned to for use with lithium. Due to a shi$ in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a fill design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped liquid metal NaK flow circuit.

Garber, Anne; Godfroy, Thomas

2006-01-01

434

Photonic integrated circuit for all-optical millimeter-wave signal generation  

SciTech Connect

Generation of millimeter-wave electronic signals and power is required for high-frequency communication links, RADAR, remote sensing and other applications. However, in the 30 to 300 GHz mm-wave regime, signal sources are bulky and inefficient. All-optical generation of mm-wave signals promises to improve efficiency to as much as 30 to 50 percent with output power as high as 100 mW. All of this may be achieved while taking advantage of the benefits of monolithic integration to reduce the overall size to that of a single semiconductor chip only a fraction of a square centimeter in size. This report summarizes the development of the first monolithically integrated all-optical mm-wave signal generator ever built. The design integrates a mode-locked semiconductor ring diode laser with an optical amplifier and high-speed photodetector into a single optical integrated circuit. Frequency generation is demonstrated at 30, 60 and 90 Ghz.

Vawter, G.A.; Mar, A.; Zolper, J.; Hietala, V.

1997-03-01

435

Ultra-stable oscillator with complementary transistors  

NASA Technical Reports Server (NTRS)

A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bi-polar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form with the piezoelectric crystal being common to both circuits. By this configuration small changes in quiescent current are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.

Kleinberg, L. L. (inventor)

1974-01-01

436

Heterogeneous Integration of Epitaxial Ge on Si using AlAs/GaAs Buffer Architecture: Suitability for Low-power Fin Field-Effect Transistors  

PubMed Central

Germanium-based materials and device architectures have recently appeared as exciting material systems for future low-power nanoscale transistors and photonic devices. Heterogeneous integration of germanium (Ge)-based materials on silicon (Si) using large bandgap buffer architectures could enable the monolithic integration of electronics and photonics. In this paper, we report on the heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization. The superior structural quality of the integrated Ge on Si using AlAs/GaAs was demonstrated using high-resolution x-ray diffraction analysis. High-resolution transmission electron microscopy confirmed relaxed Ge with high crystalline quality and a sharp Ge/AlAs heterointerface. X-ray photoelectron spectroscopy demonstrated a large valence band offset at the Ge/AlAs interface, as compared to Ge/GaAs heterostructure, which is a prerequisite for superior carrier confinement. The temperature-dependent electrical transport properties of the n-type Ge layer demonstrated a Hall mobility of 370?cm2/Vs at 290?K and 457?cm2/Vs at 90?K, which suggests epitaxial Ge grown on Si using an AlAs/GaAs buffer architecture would be a promising candidate for next-generation high-performance and energy-efficient fin field-effect transistor applications. PMID:25376723

Hudait, Mantu K.; Clavel, Michael; Goley, Patrick; Jain, Nikhil; Zhu, Yan

2014-01-01

437

Heterogeneous Integration of Epitaxial Ge on Si using AlAs/GaAs Buffer Architecture: Suitability for Low-power Fin Field-Effect Transistors.  

PubMed

Germanium-based materials and device architectures have recently appeared as exciting material systems for future low-power nanoscale transistors and photonic devices. Heterogeneous integration of germanium (Ge)-based materials on silicon (Si) using large bandgap buffer architectures could enable the monolithic integration of electronics and photonics. In this paper, we report on the heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization. The superior structural quality of the integrated Ge on Si using AlAs/GaAs was demonstrated using high-resolution x-ray diffraction analysis. High-resolution transmission electron microscopy confirmed relaxed Ge with high crystalline quality and a sharp Ge/AlAs heterointerface. X-ray photoelectron spectroscopy demonstrated a large valence band offset at the Ge/AlAs interface, as compared to Ge/GaAs heterostructure, which is a prerequisite for superior carrier confinement. The temperature-dependent electrical transport properties of the n-type Ge layer demonstrated a Hall mobility of 370?cm(2)/Vs at 290?K and 457?cm(2)/Vs at 90?K, which suggests epitaxial Ge grown on Si using an AlAs/GaAs buffer architecture would be a promising candidate for next-generation high-performance and energy-efficient fin field-effect transistor applications. PMID:25376723

Hudait, Mantu K; Clavel, Michael; Goley, Patrick; Jain, Nikhil; Zhu, Yan

2014-01-01

438

Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices.  

PubMed

We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs. PMID:25328156

Logoteta, Demetrio; Fiori, Gianluca; Iannaccone, Giuseppe

2014-01-01

439

Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices  

PubMed Central

We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs. PMID:25328156

Logoteta, Demetrio; Fiori, Gianluca; Iannaccone, Giuseppe

2014-01-01

440

Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices  

NASA Astrophysics Data System (ADS)

We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

Logoteta, Demetrio; Fiori, Gianluca; Iannaccone, Giuseppe

2014-10-01

441

Structure of the EGF receptor transactivation circuit integrates multiple signals with cell context  

SciTech Connect

Transactivation of the epidermal growth factor receptor (EGFR) has been proposed to be a mechanism by which a variety of cellular inputs can be integrated into a single signaling pathway, but the regulatory topology of this important system is unclear. To understand the transactivation circuit, we first created a “non-binding” reporter for ligand shedding. We then quantitatively defined how signals from multiple agonists were integrated both upstream and downstream of the EGFR into the extracellular signal regulated kinase (ERK) cascade in human mammary epithelial cells. We found that transactivation is mediated by a recursive autocrine circuit where ligand shedding drives EGFR-stimulated ERK that in turn drives further ligand shedding. The time from shedding to ERK activation is fast (<5 min) whereas the recursive feedback is slow (>15 min). Simulations showed that this delay in positive feedback greatly enhanced system stability and robustness. Our results indicate that the transactivation circuit is constructed so that the magnitude of ERK signaling is governed by the sum of multiple direct inputs, while recursive, autocrine ligand shedding controls signal duration.

Joslin, Elizabeth J.; Shankaran, Harish; Opresko, Lee K.; Bollinger, Nikki; Lauffenburger, Douglas A.; Wiley, H. S.

2010-05-10

442

The functional significance of newly born neurons integrated into olfactory bulb circuits  

PubMed Central

The olfactory bulb (OB) is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ) of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons. PMID:24904263

Sakamoto, Masayuki; Kageyama, Ryoichiro; Imayoshi, Itaru

2014-01-01

443

Silicon nanowire circuits fabricated by AFM oxidation nanolithography.  

PubMed

We report a top-down process for the fabrication of single-crystalline silicon nanowire circuits and devices. Local oxidation nanolithography is applied to define very narrow oxide masks on top of a silicon-on-insulator substrate. In a plasma etching, the nano-oxide mask generates a nanowire with a rectangular section. The nanowire width coincides with the lateral size of the mask. In this way, uniform and well-defined transistors with channel widths in the 10-20 nm range have been fabricated. The nanowires can be positioned with sub-100 nm lateral accuracy. The transistors exhibit an on/off current ratio of 10(5). The atomic force microscope nanolithography offers full control of the nanowire's shape from straight to circular or a combination of them. It also enables the integration of several nanowires within the same circuit. The nanowire transistors have been applied to detect immunological processes. PMID:20484797

Martínez, Ramses V; Martínez, Javier; Garcia, Ricardo

2010-06-18

444

Neural CMOS-integrated circuit and its application to data classification.  

PubMed

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-?m technology. PMID:24806121

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

445

60-GHz integrated-circuit high data rate quadriphase shift keying exciter and modulator  

NASA Technical Reports Server (NTRS)

An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modlator packaged into a small volume of 1.8 x 2.5 x 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.

Grote, A.; Chang, K.

1984-01-01

446

Basic dynamics from a pulse-coupled network of autonomous integrate-and-fire chaotic circuits.  

PubMed

This paper studies basic dynamics from a novel pulse-coupled network (PCN). The unit element of the PCN is an integrate-and-fire circuit (IFC) that exhibits chaos. We an give an iff condition for the chaos generation. Using two IFC, we construct a master-slave PCN. It exhibits interesting chaos synchronous phenomena and their breakdown phenomena. We give basic classification of the phenomena and their existence regions can be elucidated in the parameter space. We then construct a ring-type PCN and elucidate that the PCN exhibits interesting grouping phenomena based on the chaos synchronization patterns. Using a simple test circuit, some of typical phenomena can be verified in the laboratory. PMID:18244412

Nakano, H; Saito, T

2002-01-01

447

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging  

NASA Astrophysics Data System (ADS)

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5?m standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150?m pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

448

A Matterwave Transistor Oscillator  

E-print Network

A triple-well atomtronic transistor combined with forced RF evaporation is used to realize a driven matterwave oscillator circuit. The transistor is implemented using a metalized compound glass and silicon substrate. On-chip and external currents produce a cigar-shaped magnetic trap, which is divided into transistor source, gate, and drain regions by a pair of blue-detuned optical barriers projected onto the magnetic trap through a chip window. A resonant laser beam illuminating the drain portion of the atomtronic transistor couples atoms emitted by the gate to the vacuum. The circuit operates by loading the source with cold atoms and utilizing forced evaporation as a power supply that produces a positive chemical potential in the source, which subsequently drives oscillation. High-resolution in-trap absorption imagery reveals gate atoms that have tunneled from the source and establishes that the circuit emits a nominally mono-energetic matterwave with a frequency of 23.5(1.0) kHz by tunneling from the gate, ...

Caliga, Seth C; Zozulya, Alex A; Anderson, Dana Z

2012-01-01

449

Heterogeneous integration of III–V on Silicon based microlaser sources for photonic integrated circuit applications  

Microsoft Academic Search

Large scale integration of optical functions on Silicon has become of a great interest in the last years. Through heterogeneous integration of III-V materials on Silicon, new building blocks are currently studied. An important issue is the development of efficient laser sources, for both guided and free space emission. Low threshold combined to small footprints are required for silicon photonics

Pedro Rojo Romeo; Lydie Ferrier; Fabien Mandorlo; Xavier Letartre; Pierre Viktorovitch; Jean-Marc Fedeli

2009-01-01

450

Potential for integrated optical circuits in advanced aircraft with fiber optic control and monitoring systems  

NASA Astrophysics Data System (ADS)

Fiber optic technology is expected to be used in future advanced weapons platforms as well as commercial aerospace applications. Fiber optic waveguides will be used to transmit noise free high speed data between a multitude of computers as well as audio and video information to the flight crew. Passive optical sensors connected to control computers with optical fiber interconnects will serve both control and monitoring functions. Implementation of fiber optic technology has already begun. Both the military and NASA have several programs in place. A cooperative program called FOCSI (Fiber Optic Control System Integration) between NASA Lewis and the NAVY to build environmentally test and flight demonstrate sensor systems for propul sion and flight control systems is currently underway. Integrated Optical Circuits (IOC''s) are also being given serious consideration for use in advanced aircraft sys tems. IOC''s will result in miniaturization and localization of components to gener ate detect optical signals and process them for use by the control computers. In some complex systems IOC''s may be required to perform calculations optically if the technology is ready replacing some of the electronic systems used today. IOC''s are attractive because they will result in rugged components capable of withstanding severe environments in advanced aerospace vehicles. Manufacturing technology devel oped for microelectronic integrated circuits applied to IOC''s will result in cost effective manufacturing. This paper reviews the current FOCSI program and describes the role of IOC''s in FOCSI applications.

Baumbick, Robert J.

1991-02-01

451

SEM analysis of ionizing radiation effects in linear integrated circuits. [Scanning Electron Microscope  

NASA Technical Reports Server (NTRS)

A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.

Stanley, A. G.; Gauthier, M. K.

1977-01-01

452

A combination of FD-TD and Prony's methods for analyzing microwave integrated circuits  

NASA Astrophysics Data System (ADS)

It is demonstrated that in applying the FD-TD technique to analyze microwave integrated circuits, the long FD-TD time record required for generating accurate frequency domain scattering parameters can be extrapolated from a relatively short FD-TD time record by using Prony's method. As shown by comparison with the direct FD-TD generated results, the approach using the combination of FD-TD and Prony's methods achieves the same type of accuracy with a time record computed over a much shorter time.

Ko, Wai L.; Mittra, Raj

1991-12-01

453

Optically controlled phased array antenna concepts using GaAs monolithic microwave integrated circuits  

NASA Technical Reports Server (NTRS)

The desire for rapid beam reconfigurability and steering has led to the exploration of new techniques. Optical techniques have been suggested as potential candidates for implementing these needs. Candidates generally fall into one of two areas: those using fiber optic Beam Forming Networks (BFNs) and those using optically processed BFNs. Both techniques utilize GaAs Monolithic Microwave Integrated Circuits (MMICs) in the BFN, but the role of the MMIC for providing phase and amplitude variations is largely eliminated by some new optical processing techniques. This paper discusses these two types of optical BFN designs and provides conceptual designs of both systems.

Kunath, R. R.; Bhasin, K. B.

1986-01-01

454

Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems.  

PubMed

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

Rhee, Minsoung; Burns, Mark A

2009-11-01

455

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems  

PubMed Central

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

Rhee, Minsoung

2010-01-01

456

A Bistable Circuit Involving SCARECROW-RETINOBLASTOMA Integrates Cues to Inform Asymmetric Stem Cell Division  

PubMed Central

SUMMARY In plants, where cells cannot migrate, asymmetric cell divisions (ACDs) must be confined to the appropriate spatial context. We investigate tissue-generating asymmetric divisions in a stem cell daughter within the Arabidopsis root. Spatial restriction of these divisions requires physical binding of the stem cell regulator SCARECROW (SCR) by the RETINOBLASTOMA-RELATED (RBR) protein. In the stem cell niche, SCR activity is counteracted by phosphorylation of RBR through a cyclinD6;1-CDK complex. This cyclin is itself under transcriptional control of SCR and its partner SHORT ROOT (SHR), creating a robust bistable circuit with either high or low SHR-SCR complex activity. Auxin biases this circuit by promoting CYCD6;1 transcription. Mathematical modeling shows that ACDs are only switched on after integration of radial and longitudinal information, determined by SHR and auxin distribution, respectively. Coupling of cell-cycle progression to protein degradation resets the circuit, resulting in a “flip flop” that constrains asymmetric cell division to the stem cell region. PMID:22921914

Cruz-Ramirez, Alfredo; Diaz-Trivino, Sara; Blilou, Ikram; Grieneisen, Veronica A.; Sozzani, Rosangela; Zamioudis, Christos; Miskolczi, Pal; Nieuwland, Jeroen; Benjamins, Rene; Dhonukshe, Pankaj; Caballero-Perez, Juan; Horvath, Beatrix; Long, Yuchen; Mahonen, Ari Pekka; Zhang, Hongtao; Xu, Jian; Murray, James A.H.; Benfey, Philip N.; Bako, Laszlo; Maree, Athanasius F.M.; Scheres, Ben

2012-01-01

457

Digital Circuit Design Trends  

Microsoft Academic Search

This paper has described the different trends in the digital circuit design and changes over the past two decades moving from chips that contained tens of thousands of devices to today' s chips that may contain over a billion transistors. The job of the digital circuit designer has grown with the chips, moving from optimizing and validating gates, to working

Mark Horowitz; Donald Stark; Elad Alon

2008-01-01

458

Characterization of the Effect of thermal Cycling on the Signal Integrity of Interconnect Structures used in 3D Integrated Circuits  

NASA Astrophysics Data System (ADS)

The performance and reliability of the microelectronic devices are significantly influenced by the condition of interconnects in Integrated Circuits (IC). These interconnects serve primarily as signal transmission pathways in IC. Good interconnects enable free flow of electrical signals with low impedance. However, microelectronic devices are continuously subjected to fluctuating temperature conditions during their lifetime, which affect the signal integrity of interconnects. Therefore, this project takes a look at the effect of repeated temperature cycling on the reliability and performance of interconnects. Two types of interconnects: Back-End-of-Line (BEOL) and Through-Si-Via (TSV) were studied. We simulate the real world conditions by applying repeated temperature cycling, and use an RF network analyzer to extract the reflection and transmission signal characteristics of the interconnects. The mean-time-to-failure is determined upon their breakdown which is followed by the failure analysis to determine the root cause of failure.

Kandel, Binayak

2012-03-01

459

Characterization, modeling and optimization of fills and stress in semiconductor integrated circuits  

E-print Network

builds upon this modeling to improve circuit performance atmodeling of temperature dependences of SOI CMOS devices and circuitsModeling and analysis of self-heating in FinFET devices for improved circuit and

Topaloglu, Rasit Onur

2008-01-01

460

Fourth optical inspection of integrated circuits using image processing and mathematical morphology: a report  

E-print Network

that are then sliced to form wafers. The circuits are formed on the wafer using a photographic process in conjunction with chemical processes. After the circuits are finished, the dies (circuits) are separated then soldered to a metal plate (lead frame... that are then sliced to form wafers. The circuits are formed on the wafer using a photographic process in conjunction with chemical processes. After the circuits are finished, the dies (circuits) are separated then soldered to a metal plate (lead frame...

Chemaly, Ephrem A.

2013-03-13

461

VO II-based microbolometer uncooled infrared focal plane arrays with CMOS readout integrated circuit  

NASA Astrophysics Data System (ADS)

Thin films of vanadium dioxide (VO II) were selected for microbolometers. The thin films were fabricated with a novel method mainly including ion-sputtering and annealing. It is found that the electrical properties of these thin films can be controlled by adjusting the time of ion-sputtering and annealing. A standard microbolometer pixel structure of micro-bridge has been applied. Two-dimensional arrays of microbolometers have been fabricated on silicon integrated circuit wafers using a surface micromachining technique. A new type of on-chip readout integrated circuit (ROIC) for 32×32 pixel bolometric detector arrays has been designed and fabricated using a 1.5?m double metal poly complementary metal oxide semiconductor (CMOS) processing. The readout circuit consists of three stages, which provides low noise, a highly stable detector bias, high photon current injection efficiency, high gain, and high speed. Several prototypes of 32×32 pixel bolometric detector arrays have been designed and fabricated. These arrays consist of detectors with lateral dimensions of 50?m 50?m, and each bolometric detector is on a 100?m pitch. The results of measurement show that the fabricated uncooled infrared focal plane arrays (UIRFPAs) have excellent performance. The frame rate is 50Hz, the pixel operability is above 96%, the responsivity (R) @ f/1 value is up to 15000V/W, the noise equivalent temperature difference (NETD) @ f/1 and 30Hz is about 50mK, and the average power dissipation is only 24.7mW. The results indicate that the technology of fabricating these 32×32 UIRFPAs has potential to be utilized for fabricating low cost and large-scale UIRFPAs.

Chen, Xiqu; Yi, Xinjian

2005-11-01

462

Hybrid integration of synthesized dielectric image waveguides in substrate integrated circuit technology and its millimeter wave applications  

NASA Astrophysics Data System (ADS)

This thesis deals with a novel type of integrated dielectric waveguide which is synthesized on a planar grounded substrate by perforation of the zones adjacent to a guiding channel in the center. The resulting Substrate Integrated Image Guide (SIIG) not only allows for low-loss guidance of electromagnetic waves in a similar way as the standard image guide, but also meets the requirements of low cost and ease of integration. A first objective was the detailed analysis of the propagation properties of fundamental and higher order modes in this waveguide structure, regarding attenuation, dispersion behavior, bandwidth, leakage effects, and the impact of fabrication tolerances. For this purpose, specifically adapted techniques of analysis are presented, since established methods for the conventional image guide can not be applied to the more complex periodic SIIG. Commercial electromagnetic full-wave software is used along with a dual-line approach involving a subsequent extraction of the propagation constant from simulated S-parameters. Alternatively, the solution of the eigenmode problem of a single SIIG unit cell also performs the task. Both techniques are in good agreement and provide accurate results, which is supported by measurements on laser-fabricated prototypes. It is shown that the achievable attenuation is much lower than in the standard integrated technologies and that losses mainly depend on the chosen dielectric material. As a consequence, the SIIG also is an attractive technology for applications beyond the mmW band, i. e. in the terahertz range. Design recommendations for the geometric parameters of the SIIG are discussed and a simplified equivalent model with homogeneous dielectric regions is introduced to speed up the design of passive components. Low-loss transitions between dissimilar waveguide structures are indispensable key components for a hybrid integrated platform. In order to enable the connection of standard measurement equipment in the W-band (75 GHz to 110 GHz), a transition from rectangular waveguide to SIIG was developed. Another transition to either microstrip or CPW is essential to enable coplanar probe measurements and to achieve compatibility with monolithic millimeter wave integrated circuits (MMICs). Microstrip and image guide have very different requirements for the substrate thickness, for which reason efforts were concentrated on a wideband transition between the SIIG and CPW. The designed transition shows good broadband performance and minimal radiation loss. Other transitions from the SIIG to the Substrate Integrated Waveguide (SIW) are also presented in the context of substrate integrated circuits (SICs). The latter technology combines planar transmission lines and originally non-planar waveguide structures that are synthesized in planar form on a common substrate. High alignment precision is a direct consequence, which eliminates the necessity for additional tuning. As an open dielectric waveguide technology with very small transmission loss, the SIIG is particularly suitable for antennas and corresponding feed lines. The similarity of the SIIG with other dielectric waveguides and especially with the image guide suggests a knowledge transfer from known dielectric antennas. A planar SIIG rod antenna was designed and fabricated, as a derivative of the established polyrod antenna. The structural shape is simple and compact, and it provides a medium gain in the range of 10 dBi to 15 dBi. A second developed type, an SIIG traveling-wave linear array antenna, is frequency-steerable through broadside due to special radiation elements. The novel design of a slab-mode antenna forms an endfire beam by a planar lens configuration. In addition, all of those dielectric-based antennas are highly efficient. Being synthesized on a planar substrate, the SIIG can be combined in a hybrid way with other waveguide structures on the same substrate in so-called substrate integrated circuits (SICs). It joins the SIW and the Substrate Integrated Non-Radiative Dielectric guide (SINRD) and adds unique featu

Patrovsky, Andreas

463

Multisensory integration for odor tracking by flying Drosophila: Behavior, circuits and speculation.  

PubMed

Many see fruit flies as an annoyance, invading our homes with a nagging persistence and efficiency. Yet from a scientific perspective, these tiny animals are a wonder of multisensory integration, capable of tracking fragmented odor plumes amidst turbulent winds and constantly varying visual conditions. The peripheral olfactory, mechanosensory, and visual systems of the fruit fly, Drosophila melanogaster, have been studied in great detail;1-4 however, the mechanisms by which fly brains integrate information from multiple sensory modalities to facilitate robust odor tracking remain elusive. Our studies on olfactory orientation by flying flies reveal that these animals do not simply follow their "nose"; rather, fruit flies require mechanosensory and visual input to track odors in flight.5,6 Collectively, these results shed light on the neural circuits involved in odor localization by fruit flies in the wild and illuminate the elegant complexity underlying a behavior to which the annoyed and amazed are familiar. PMID:20539786

Duistermars, Brian J; Frye, Mark A

2010-01-01

464

Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices  

PubMed Central

Summary Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths. PMID:23365801

Iovan, Adrian; Fischer, Marco; Lo Conte, Roberto

2012-01-01

465

Ion-beam apparatus and method for analyzing and controlling integrated circuits  

DOEpatents

An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

Campbell, Ann N. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

1998-01-01

466

Ion-beam apparatus and method for analyzing and controlling integrated circuits  

DOEpatents

An ion-beam apparatus and method for analyzing and controlling integrated circuits are disclosed. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal. 4 figs.

Campbell, A.N.; Soden, J.M.

1998-12-01

467

Ge Photodetectors Integrated with Waveguides for Electronic-Photonic Integrated Circuits on CMOS Platform  

Microsoft Academic Search

Ge p-i-n photodetectors monolithically integrated with silicon oxynitride and silicon nitride waveguides on Si CMOS platform are presented. The devices demonstrated high efficiency (~1.08 A\\/W) and high-speed (>14 Gbit\\/s) performances at low bias.

Donghwan Ahn; Ching-yin Hong; Jifeng Liu; Mark Beals; Jian Chen; Franz X Kaertner; L. C. Kimerling; J. Michel

2007-01-01

468

Electronics is the branch of physics, engineering and technology dealing with electrical circuits that involve active  

E-print Network

28/04/14 1 Electronics is the branch of physics, engineering and technology dealing with electrical circuits that involve active electrical components such as vacuum tubes, transistors, diodes and integrated computers, tablets, internet... · Mobile devices: iPhones, mp3 players... · Solar cells, led displays

Ã?nay, Devrim

469

A 40Gb\\/s integrated clock and data recovery circuit in a 50GHz f T silicon bipolar technology  

Microsoft Academic Search

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb\\/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f T self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon

Martin Wurzer; J. Bock; Herbert Knapp; W. Zirwas; F. Schumann; A. Felder

1999-01-01

470

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications  

NASA Technical Reports Server (NTRS)

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

471

Minimizing spikes in switching-regulator circuits  

NASA Technical Reports Server (NTRS)

Circuit, employing tapped inductor to back-bias rectifying diodes and extra diode to cummutate current, minimizes current spikes that cause premature transistor failure in switching-regulator circuits.

Mclyman, W. T.

1980-01-01

472

High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor  

E-print Network

In this letter, we present a new AlGaN/GaN enhancement-mode (E-mode) transistor based on a dual-gate structure. The dual gate allows the transistor to combine an E-mode behavior with low on-resistance and very high breakdown ...

Lu, Bin

473

Sparse gallium arsenide to silicon metal waferbonding for heterogeneous monolithic microwave integrated circuits  

NASA Astrophysics Data System (ADS)

Waferbonding is a technique that integrates different semiconductors together, in order to obtain hybrid structures that exploit the strengths of each material. Work was done at the University of California at San Diego to investigate the waferbonding of III/V compound semiconductors to silicon using a metal interface. GaAs and other III/V compound semiconductors surpass silicon in their ability to create high performance microwave devices, while silicon offers an inexpensive platform with a proven digital architecture that can interface with microwave devices and support passive components and driver circuitry. Intimate integration of the two will be required, as mixed RF/digital and optical/digital systems for communications devices such as cell phones, wi-fi, and optical communications systems are pushed smaller, faster, and to higher power. The metalbonding implementation of a proposed heterogeneous monolithic microwave integrated circuit (HMMIC) system was investigated, and was shown to extend the capabilities of existing homogeneous monolithic microwave integrated circuit (MMIC) systems. The main goals of this work were two-fold; first to implement a robust heterogeneous integration technique, and second, to show that this approach uniquely improves upon existing microwave integration technology. The metalbonding technique investigated sparsely integrated GaAs structures onto silicon, in pursuit of this HMMIC scheme. Both bottom-up and top-down fabrication methods were implemented. These approaches required the development of a myriad of meticulously designed fabrication procedures capable of avoiding the many incompatibilities between the compound semiconductor, bondmetal, and silicon materials. The bondmetal interface, provided by these techniques, broadens the scope of existing monolithic microwave integrated circuit technology design possibilities. Essential bond interface properties were measured to establish the performance of this heterogeneous integration method. Passive bond test structures were designed, fabricated, and measured to extract the bond interface electrical behavior, electrical contact resistivity, and thermal conductivity. The In-Pd alloy, employed as the bondmetal interface between these GaAs/silicon test structures, provided a universal ohmic contact between all doping combinations. The bond interface contact resistivity between n-type GaAs and p-type Si was found to be 1.03x10-5 ohm-cm2 and a bondmetal thermal conductivity of 2.51 W/m-K was also determined. In addition, passive un-bonded and bonded microwave waveguides were constructed to test the microwave propagation properties of the bondmetal. The characteristics of these test structures qualified the metalbonding technique for use in heterogeneous microwave systems. The successful fabrication of these structures demonstrated that this metalbonding method could be extended to active devices as well, which would be of similar size, form factor, and utilize the same fabrication methods. An un-bonded active microwave waveguide, similar to one which could become common in heterogeneous microwave systems, was investigated to illustrate its unique microwave properties. This un-bonded traveling wave PIN semiconductor waveguide propagated microwaves in a 'slow-wave' manner, as a consequence of its diode structure.

Bickford, Justin Robert

474

Intelligent, compact and robust semiconductor circuit breaker based on silicon carbide devices  

Microsoft Academic Search

A novel semiconductor circuit breaker based on SiC (silicon carbide) is introduced in this paper. It integrates an electronic power circuit breaker consisting of two anti-serial cascodes, a control unit with current, voltage and temperature measurement as well as a power supply, making the switch fully self-sufficient. Each cascode is composed of a high-voltage SiC-JFET (junction field effect transistor) or

K. Handt; G. Griepentrog; R. Maier

2008-01-01

475

Magnetophoretic circuits for digital control of single particles and cells.  

PubMed

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells