Sample records for transistor integrated circuit

  1. High Current Analog Bipolar Junction Transistor Amplifier Integrated Circuit Development

    E-print Network

    Texas at Arlington, University of

    (considering push-pull, class AB, common emitter and emitter follower designs) A. Comparison of circuit, common emitter and emitter follower designs C. Circuits - procedures for and determination of practicalHigh Current Analog Bipolar Junction Transistor Amplifier Integrated Circuit Development Statement

  2. MOS transistor modeling for RF integrated circuit design

    Microsoft Academic Search

    Christian Enz

    2000-01-01

    The design of radio-frequency (RF) integrated circuits in deep-submicron CMOS processes requires accurate and scalable compact models of the MOS transistor that are valid in the GHz frequency range and even beyond. Unfortunately, the currently available compact models give inaccurate results if they are not modified adequately. This paper presents the basis of the modeling of the MOS transistor for

  3. Integrated logic circuits using single-atom transistors

    PubMed Central

    Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

    2011-01-01

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

  4. Integrated circuits based on bilayer MoS? transistors.

    PubMed

    Wang, Han; Yu, Lili; Lee, Yi-Hsien; Shi, Yumeng; Hsu, Allen; Chin, Matthew L; Li, Lain-Jong; Dubey, Madan; Kong, Jing; Palacios, Tomas

    2012-09-12

    Two-dimensional (2D) materials, such as molybdenum disulfide (MoS(2)), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS(2) allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene's advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS(2) show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS(2) to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between 2 to 12 transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS(2). Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions. PMID:22862813

  5. Gigahertz flexible graphene transistors for microwave integrated circuits.

    PubMed

    Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

    2014-08-26

    Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations. PMID:25062282

  6. Printed organic thin-film transistor-based integrated circuits

    NASA Astrophysics Data System (ADS)

    Mandal, Saumen; Noh, Yong-Young

    2015-06-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted.

  7. Organic thin-film transistors, integrated circuits, and light-emitting diodes

    Microsoft Academic Search

    Hagen Klauk

    1999-01-01

    This thesis reports high-performance organic thin film transistors on glass substrates and the fastest all-organic integrated circuits reported to date. In addition, a novel fully integrated all-organic light emitting diode\\/thin film transistor active pixel is reported. The process technology necessary to fabricate organic thin film transistors on arbitrary substrates was developed. Using the small-molecule hydrocarbon pentacene as the active material,

  8. High Electron Mobility Transistors Yield Improvement with Ultrasonically Assisted Recess for High-Speed Integrated Circuits

    E-print Network

    Seo, Kwang Seok

    High Electron Mobility Transistors Yield Improvement with Ultrasonically Assisted Recess for High) InAlAs/InGaAs high electron mobility transistors (HEMTs) have been a great contribution to the research and development of high-speed integrated circuits, owing to their high electron mobilities, high

  9. CMOS-based carbon nanotube pass-transistor logic integrated circuits.

    PubMed

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  10. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    PubMed Central

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4?V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  11. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 °C

    Microsoft Academic Search

    Philip G. Neudeck; David J. Spry; Liang-Yu Chen; NASA GRC; Glenn M. Beheim; Robert S. Okojie; Laura J. Evans; Roger Meredith; Terry Ferrier; Michael J. Krasowski; Norman F. Prokop

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the ~ 300 °C effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation

  12. Large-scale complementary integrated circuits based on organic transistors

    Microsoft Academic Search

    B. Crone; A. Dodabalapur; Y.-Y. Lin; R. W. Filas; Z. Bao; A. Laduca; R. Sarpeshkar; H. E. Katz; W. Li

    2000-01-01

    Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of

  13. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    PubMed

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics. PMID:18269256

  14. Hardness Assurance Guidelines for Moderate Neutron Environment Effects in Bipolar Transistors and Integrated Circuits

    Microsoft Academic Search

    Robert A. Berger; Joseph L. Azarewicz; Harvey Eisen

    1978-01-01

    This paper sets forth procedures which provide effective means of obtaining semiconductor devices whose neutron-induced response is within known, acceptable limits. These Hardness Assurance (HA) procedures can be applied to bipolar transistors, TTL (54\\/74 series) digital integrated circuits, and operational amplifiers (such as the 741). HA is implemented by imposing two control levels on the supplier and\\/or two quality levels

  15. Advances in the modeling of single electron transistors for the design of integrated circuit.

    PubMed

    Chi, Yaqing; Sui, Bingcai; Yi, Xun; Fang, Liang; Zhou, Hailiang

    2010-09-01

    Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy. PMID:21133161

  16. Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching

    Microsoft Academic Search

    M. Saitoh; H. Harata; T. Hiramoto

    2004-01-01

    This paper reports the first room-temperature (RT) operation of integrated single-electron transistor (SET) circuits. We fabricate silicon single-hole transistors (SHTs) with high controllability and obtain large Coulomb blockade (CB) oscillation with the peak-to-valley current ratio (PVCR) of over 103 at RT. A current switch using two SHTs integrated under a single gate is demonstrated at RT. We propose a novel

  17. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 °C

    Microsoft Academic Search

    Philip G. Neudeck; David J. Spry; Liang-Yu Chen; Carl W. Chang; Glenn M. Beheim; Robert S. Okojie; Laura J. Evans; Roger D. Meredith; Terry L. Ferrier; Michael J. Krasowski; Norman F. Prokop

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long- term 500 °C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H- SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous

  18. Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

    SciTech Connect

    Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q. [Sandia National Labs., Albuquerque, NM (United States); Enquist, P.M. [Research Triangle Inst., Research Triangle Park, NC (United States)

    1995-12-31

    Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

  19. SEMICONDUCTOR INTEGRATED CIRCUITS: A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

    NASA Astrophysics Data System (ADS)

    Wei, Wang; Beiju, Huang; Zan, Dong; Weilian, Guo; Hongda, Chen

    2010-05-01

    A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 ?m CMOS technology. This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics. At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor, a flexible logic circuit is realized in this work, which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor. It turns out that MOS-NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.

  20. Emitter bypassing in transistor circuits

    Microsoft Academic Search

    R. Murray

    1957-01-01

    The emitter bypass capacitor has probably become as commonplace in transistor circuitry as its vacuum tube counterpart, the cathode bypass capacitor. An equivalent circuit analysis of the common-emitter amplifier yields a simple relation that may be used for the determination of the approximate value of the capacitor in terms of the required low-frequency response and the circuit and transistor parameters.

  1. THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development,

    E-print Network

    Rodwell, Mark J. W.

    THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit Scientific Abstract--We examine the feasibility of developing bipolar transistors with current-gain and power-frequency performance limits of InP-based bipolar transistors, and their potential for operation at low THz frequencies

  2. On the optimum design of the front-end PIN-heterojunction bipolar transistor optoelectronic integrated circuit photoreceiver

    Microsoft Academic Search

    N. R. Das; M. J. Deen

    2002-01-01

    In this article, a detailed analysis of the performance of an integrated front-end PIN-heterojunction bipolar transistor photoreceiver has been given and optimum designs are suggested for maximum gain-bandwidth product (GB) and gain-bandwidth-sensitivity measure (GBS) of the device. The present SPICE-based analysis requires the equivalent circuit model of the receiver components. An expression for the impulse response of a PIN photodiode

  3. Development of high-performance printed organic field-effect transistors and integrated circuits.

    PubMed

    Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

    2014-07-24

    Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications. PMID:25057765

  4. Transistor sizing in CMOS circuits

    Microsoft Academic Search

    Mehmet A. Cirit

    1987-01-01

    The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

  5. Fast organic thin-film transistor circuits

    Microsoft Academic Search

    Hagen Klauk; David J. Gundlach; Thomas N. Jackson

    1999-01-01

    We have fabricated organic thin-film transistors and integrated circuits using pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam sputtered silicon dioxide as the gate dielectric and a double-layer photoresist process to isolate devices. These transistors have carrier mobility near 0.5 cm2\\/V-s and on\\/off current ratio larger than 107. Using a level-shifting design that allows

  6. Improved chopper circuit uses parallel transistors

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage.

  7. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    NASA Astrophysics Data System (ADS)

    Liang, Shibo; Zhang, Zhiyong; Si, Jia; Zhong, Donglai; Peng, Lian-Mao

    2014-08-01

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  8. Monolithic integrated resonant tunneling diode and heterostructure junction field effect transistor circuits

    Microsoft Academic Search

    J. C. Yen; Q. Zhang; M. J. Mondry; P. M. Chavarkar; E. L. Hu; S. I. Long; U. K. Mishra

    1996-01-01

    We have developed a simple technology for monolithic integration of resonant tunneling diodes (RTDs) and heterostructure junction-modulated field effect transistors (HJFETs). We have achieved good device performance with this technology: HJFETs had transconductances of 290 mS\\/mm and current densities of 310 mA\\/mm for a 1.5 ?m gate length; RTDs had room temperature peak to valley ratios greater than 20:1 with

  9. High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

    E-print Network

    Seo, Kwang Seok

    resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an In of resonant tunnelling diode (RTD) and conventional transis- tors has attracted much attention for highHigh-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling

  10. Transistor device techniques aid circuit designers, too

    Microsoft Academic Search

    C. S. Sujan

    1984-01-01

    The present investigation is concerned with some practical examples which demonstrate an approach to the design of a microwave packaged transistor, giving particular attention to aspects of the microwave design. A similar design procedure can be used for a hybrid or integrated circuit configuration on alumina, epsilam-10, RT\\/Duroid 6010, or any other suitable substrate. Both the Smith chart and computer-aided

  11. Monolithic Integration of Heterojunction Bipolar Transistor and Grating-Outcoupled Surface Emitting Laser Electronic-Photonic Integrated Circuit

    Microsoft Academic Search

    W. A. Jones; S. McWilliams; C. Boehme; Haijun Zhu; P. Pinsukanjana; T. Masood; Linglin Jiang; V. Amarasinghe; M. Achtenhagen; G. A. Evans

    2007-01-01

    This paper reports on the design, growth, fabrication, and processing of an integrated Grating-Outcoupled Surface Emitting (GSE) semiconductor laser and a Double Heterojunction Bipolar Transistor (DHBT) driver. The GSE laser has a 380 mum long gain section, 15 mum long out-coupler, and 200 mum long distributed Bragg reflectors (DBRs). The design of the DHBT includes an InP emitter and collector

  12. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

    Microsoft Academic Search

    Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

    2008-01-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

  13. Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors

    SciTech Connect

    Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Blalock, Benjamin J [ORNL; Islam, Syed K [ORNL

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  14. Transistor device techniques aid circuit designers, too

    NASA Astrophysics Data System (ADS)

    Sujan, C. S.

    1984-10-01

    The present investigation is concerned with some practical examples which demonstrate an approach to the design of a microwave packaged transistor, giving particular attention to aspects of the microwave design. A similar design procedure can be used for a hybrid or integrated circuit configuration on alumina, epsilam-10, RT/Duroid 6010, or any other suitable substrate. Both the Smith chart and computer-aided design (CAD) facilitate design realization, taking into account the treatment of matching sections as either transmission lines or reactive elements. The first step in the considered design process involves the determination of the chip impedance and the plotting of impedance on a Smith chart. A considered example is concerned with an analysis of a typical transistor package metallization.

  15. An MOS transistor model for analog circuit design

    Microsoft Academic Search

    A. I. A. Cunha; M. C. Schneider; C. Galup-Montoro

    1998-01-01

    This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in

  16. Worst Case Design of Digital Integrated Circuits

    Microsoft Academic Search

    J. C. Zhang

    1994-01-01

    This paper describes ±? transistor modeling and its application in worst case design of digital integrated circuits. We explore the implicit assumptions made when using the ±? transistor model, establish the relationship between worst-case design and variability minimization, and extend the variability minimization principles to the worst-case measure reduction. A CMOS delay circuit is used to clarify the discussion

  17. Transistor and interconnect modeling for design of carbon nanotube integrated circuits

    Microsoft Academic Search

    Ashok Srivastava

    2012-01-01

    The one-dimensional carbon nanotube (CNT) has excellent electrical, mechanical and thermal properties which have made the CNT one of the promising materials for applications in nanoelectronics and micro\\/nano-systems. Nanometer CMOS technology, especially in 22 nm and below, is plagued due to performance degradation of conventional Cu\\/low-k dielectric as an interconnect material for gigascale integration. In search for novel technologies, no

  18. Monolithically-integrated optoelectronic circuit for ultrafast sampling of a dual-gate field-effect transistor

    Microsoft Academic Search

    J. Allam; N. de B. Baynes; J. R. A. Cleaver; K. Ogawa; T. Mishima; I. Ohbu

    1996-01-01

    An integrated optoelectronic circuit for ultrafast sampling of multi-terminal devices is described. This is achieved using optimized photoconductive switches fabricated from low-temperature-grown GaAs, monolithic integration of the device with the sampling circuit, control of the electromagnetic modes propagating on the coplanar waveguide using microfabricated airbridges, and discrimination of guided and freely-propagating modes using a novel electrooptic sampling method. As an

  19. Programmable resistive-switch nanowire transistor logic circuits.

    PubMed

    Shim, Wooyoung; Yao, Jun; Lieber, Charles M

    2014-09-10

    Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks. PMID:25133781

  20. Field-effect transistor self-electrooptic effect device: integrated photodiode, quantum well modulator and transistor

    Microsoft Academic Search

    D. A. B. Miller; M. D. Feuer; T. Y. Chang; S. C. Shunk; J. E. Henry; D. J. Burrows; D. S. Chemla

    1989-01-01

    The authors propose and demonstrate the integration of a photodiode, a quantum-confined Stark-effect quantum-well optical modulator, and a metal-semiconductor field-effect transistor (MESFET) to make a field-effect transistor self-electrooptic effect device. This integration allows optical inputs and outputs on the surface of a GaAs-integrated circuit chip, compatible with standard MESFET processing. To provide an illustration of feasibility, the authors demonstrate signal

  1. Coulomb blockade, single-electron transistors and circuits in silicon

    Microsoft Academic Search

    Zahid A. K Durrani

    2003-01-01

    Single-electron devices in silicon provide a means to control the electrons in nanoscale electronic systems precisely while retaining compatibility with large-scale integrated (LSI) circuit technology. Single-electron transistors operating at room temperature have now been fabricated in silicon-on-insulator, polycrystalline silicon, and nanocrystalline silicon material. Memory cells where the stored states are defined by single electrons, and few-electron memory cell arrays with

  2. Simulating Hybrid Circuits of Single-Electron Transistors and Field-Effect Transistors

    Microsoft Academic Search

    Günther Lientschnig; Irek Weymann; Peter Hadley

    2003-01-01

    An exact model for a single-electron transistor was developed within the circuit simulation package SPICE. This model uses the orthodox theory of single-electron tunneling and determines the average current through the transistor as a function of the bias voltage, the gate voltage, and the temperature. Circuits including single-electron transistors, field-effect transistors (FETs), and operational amplifiers were then simulated. In these

  3. Modeling and simulation of insulated-gate field-effect transistor switching circuits

    Microsoft Academic Search

    HAROLD SHICHMAN; DAVID A. HODGES

    1968-01-01

    A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET

  4. 'Soft' amplifier circuits based on field-effect ionic transistors.

    PubMed

    Boon, Niels; Olvera de la Cruz, Monica

    2015-06-28

    Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor. PMID:25990873

  5. Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign

    E-print Network

    EE134 1 Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and Design of text. EE134 6 Last LectureLast Lecture ! Last lecture " Moore's Law " Challenges in digital IC design in complexity of ICsSummarizes progress in complexity of ICs 1971 P4 2000 2,300 transistors 108 KHz operation 42

  6. Semiconductor photonic integrated circuits

    Microsoft Academic Search

    Thomas L. Koch; Uziel Koren

    1991-01-01

    Semiconductor photonic integrated circuits (PICs) refer to that subset of optoelectronic integrated circuits (OEICs) which focus primarily on the monolithic integration of optically interconnected guided-wave optoelectronic devices. The principal motivation for PIC research is the expected cost reduction and packaging robustness associated with replacing individually aligned, single-mode optical connections between discrete optoelectronic devices with lithographically produced integrated waveguides. This field

  7. 2734 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 12, DECEMBER 2007 Integrated Heterojunction Bipolar Transistor

    E-print Network

    Choi, Woo-Young

    P heterojunction bipolar transistor (HBT), monolithic microwave integrated circuit (MMIC), optical injection integrated circuit (MMIC) oscillator and demonstrate 30-GHz bi-directional data trans- mission. The HBT MMIC

  8. Thin-Film Transistors and Circuits Based on Carbon Nanotubes

    Microsoft Academic Search

    Didier Pribat; P. Bondavalli

    2012-01-01

    Carbon nanotubes are actively studied for thin-film transistor and electronics applications. Although these nanomaterials were first considered as potential candidates for the replacement of Si MOS type transistors in VLSI circuits, their main field of application is shifting towards large area electronics on flexible, plastic-type substrates, a domain which is at present, less demanding in terms of device dimensions and

  9. Programmable Resistive-Switch Nanowire Transistor Logic Circuits Wooyoung Shim,,,

    E-print Network

    Lieber, Charles M.

    Programmable Resistive-Switch Nanowire Transistor Logic Circuits Wooyoung Shim,,, Jun Yao that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive

  10. Macromodeling of single-electron transistors for efficient circuit simulation

    Microsoft Academic Search

    Yun Seop Yu; Sung Woo Hwang; D. Ahn

    1999-01-01

    In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors

  11. Fabrication of InP-based Optoelectronic Integrated Circuit (OEIC) Photoreceivers Using Shared Layer Integration of Heterojunction Bipolar Transistors and Refracting-Facet Photodiodes

    NASA Astrophysics Data System (ADS)

    Lee, Bangkeun; Yang, Kyounghoon

    2004-04-01

    InP-based monolithic photoreceivers have been fabricated using a shared layer integration scheme of refracting-facet photodiodes (RFPDs) and heterojunction bipolar transistors (HBTs). An HBT was fabricated using a self-aligned emitter-base process and nonalloyed metallization of the emitter, base and collector ohmic contacts. The fabricated 2× 10 ?m2 emitter HBT exhibited a maximum current gain of 40. The maximum cutoff frequencies of this HBT were measured to be fT=79 GHz and fmax=143 GHz at IC=19 mA and VCE=1.5 V, respectively. An RFPD was fabricated using the base-collector junction layers of the HBT based on the selective wet chemical etching characteristics of InP and InGaAs layers. The fabricated RFPD showed a 37% increased optical responsivity of 0.48 A/W compared to the fabricated surface-illuminated photodiode using the same photoreceiver epitaxial layer. The full width at half maximum (FWHM) of the fabricated RFPD was determined to be 24 ps using the standard 50 ? system load. The fabricated three-stage transimpedance amplifier (TIA) showed a transimpedance gain of 46 dB? and a -3 dB bandwidth of 12 GHz. The fabricated monolithic RFPD/HBT photoreceiver has demonstrated a -3 dB optical bandwidth of 6.9 GHz.

  12. Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

    NASA Technical Reports Server (NTRS)

    1973-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

  13. A Study of Transistor Circuits for Television

    Microsoft Academic Search

    G. C. Sziklai; R. D. Lohman; G. B. Herzog

    1953-01-01

    This paper describes a general study of transistors in television receivers. For this purpose the development of a completely transistorized television receiver was undertaken. An experimental model using 37 developmental transistors and a five-inch kinescope housed in a cabinet 13??12??7 inches was constructed. This portable receiver operates on a single channel using a self-contained loop, and has a total battery-power

  14. Parallel transistor level circuit simulation using domain decomposition methods

    Microsoft Academic Search

    He Peng; Chung-kuan Cheng

    2009-01-01

    This paper presents an efficient parallel transistor level full-chip circuit simulation tool with SPICE-accuracy. The new approach partitions the circuit into a linear domain and several non-linear domains based on circuit non-linearity and connectivity. The linear domain is solved by parallel fast linear solver while nonlinear domains are parallelly distributed into different processors and solved by direct solver. Parallel domain

  15. Integrated circuits incorporating thin-film active and passive elements

    Microsoft Academic Search

    P. K. Weimer; H. Borkan; G. Sadasiv; L. Meray-Horvath; F. V. Shallcross

    1964-01-01

    The thin-film field-effect transistor (TFT) provides the active element for complex integrated circuits deposited upon an insulating substrate. N-type transistors are obtained with evaporated layers of cadmium sulfide or selenide and p-type transistors with evaporated tellurium. Switching speeds of less than 4 nsec and gain-bandwidth products of greater than 30 Mc are observed with polycrystalline films of cadmium sulfide. Oscillations

  16. Challenges for dielectric materials in future integrated circuit technologies

    Microsoft Academic Search

    C. M. Garner; G. Kloster; G. Atwood; L. Mosley; A. C. Palanduz

    2005-01-01

    Dielectrics provide crucial functions in integrated circuits as gate dielectrics, transistor isolation structures, memory elements, interlevel dielectrics, and also provide charge storage in fast capacitors for power isolation. As the feature sizes of integrated circuits continues to decrease and speed increases, the performance requirements for these dielectrics increases significantly. Conventional materials such as thermal and CVD SiO2 are being replaced

  17. Integration of pentacene-based thin film transistors via photolithography for low and high voltage applications

    E-print Network

    Smith, Melissa Alyson

    2012-01-01

    An organic thin film transistor (OTFT) technology platform has been developed for flexible integrated circuits applications. OTFT performance is tuned by engineering the dielectric constant of the gate insulator and the ...

  18. Silicon Vertically Integrated Nanowire Field Effect Transistors

    E-print Network

    Yang, Peidong

    Silicon Vertically Integrated Nanowire Field Effect Transistors Josh Goldberger, Allon I. Hochbaum Manuscript Received February 24, 2006 ABSTRACT Silicon nanowires have received considerable attention, alternative transistor geometries need to be considered.1 Silicon nanowire based devices2,3 and horizontal

  19. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    NASA Technical Reports Server (NTRS)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  20. Translinear circuits using subthreshold floating-gate MOS transistors

    Microsoft Academic Search

    Bradley A. Minch; Chris Diorio; Paul Hasler; Carver A. Mead

    1996-01-01

    We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and\\/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family

  1. Bipolar transistor modeling of avalanche generation for computer circuit simulation

    Microsoft Academic Search

    R. W. Dutton

    1975-01-01

    An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.

  2. Analysis of magnetic proportional drive circuits for bipolar junction transistors

    Microsoft Academic Search

    R. L. Avant; W. T. Michael; D. J. Shortt; R. E. Palma

    1985-01-01

    A comparison is presented of some advantages and disadvantages of three popular magnetic proportional drive circuits for bipolar junction transistors (BJT) used in spacecraft switched mode power supplies (SMPS). A generic classification of these drives is introduced. A novel adaptation of one of these drives, the multiple mode proportional drive (MMPD), is developed to provide a total proportional drive for

  3. Bioluminescent bioreporter integrated circuit

    DOEpatents

    Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  4. Flexible organic transistors and circuits with extreme bending stability

    NASA Astrophysics Data System (ADS)

    Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

    2010-12-01

    Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100?m. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5?m), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

  5. Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits

    E-print Network

    Wang, Yu

    Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits Yu Wang method in circuit standby mode. Reducing leakage current through fine- grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improves circuit noise margins

  6. Rapid evolution of analog circuits configured on a field programmable transistor array

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

    2002-01-01

    The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

  7. Run-Time Programming of Analog Circuits Using Floating-Gate Transistors

    E-print Network

    Graham, David W.

    Run-Time Programming of Analog Circuits Using Floating-Gate Transistors David W. Graham Lane of floating-gate (FG) transistors provides programmability to analog circuitry and, hence, the ability to recalibrate an analog system. If the FG transistors are programmed indirectly by using a second transistor

  8. Amorphous silicon thin-film transistor gate driver circuit design optimization using a simulation-based evolutionary technique

    Microsoft Academic Search

    Ying-Ju Chiu; Kuo-Fu Lee; Ying-Chieh Chen; Hui-Wen Cheng; Yiming Li; Tony Chiang; Kuen-Yu Huang; Tsau-Hua Hsieh

    2010-01-01

    In this work, we for the first time optimize dynamic characteristic of amorphous silicon thin-film transistor (TFT) gate (ASG) driver circuits for TFT-LCD panel. The rise time, fall time, power dissipation, and ripple voltage of the ASG driver circuit are optimized using simulation-based evolutionary method which integrates genetic algorithm and circuit simulation on the unified optimization framework. Two different a-Si:H

  9. Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

    2008-01-01

    There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

  10. Microwave Enginering Microwave Integrated Circuits

    E-print Network

    Iqbal, Sheikh Sharif

    's but are larger than MMIC's; therefore miniature hybrid circuit technology can be also called quasi;· Monolithic Microwave Integrated Circuits (MMICs): is a type of circuit in which all active and passive deposition scheme as epitaxy, ion implantation, sputtering, evaporation, diffusion. · RF/MW MMIC circuits

  11. Transistors and tunnel diodes for analog\\/mixed-signal circuits and embedded memory

    Microsoft Academic Search

    A. Seabaugh; X. Deng; T. Blaket; B. Brar; T. Broekaert; R. Lake; F. Morris; G. Frazier

    1998-01-01

    An integrated tunnel diode\\/transistor process can be used to increase the speed of signal processing circuitry or reduce power at the same speed; in memory applications, tunnel diodes can be used to reduce static power dissipation (>20X in Si, >1000X in III-V materials) relative to conventional approaches. This paper summarizes recent progress in InP and Si-based tunnel diodes and circuits

  12. Confinement-modulated junctionless nanowire transistors for logic circuits.

    PubMed

    Vaurette, François; Leturcq, Renaud; Lepilliet, Sylvie; Grandidier, Bruno; Stiévenard, Didier

    2014-11-21

    We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices. PMID:25297836

  13. Transistorized power switch and base drive circuit therefore

    SciTech Connect

    Lee, F.C.; Carter, R.A.

    1981-03-24

    A high power switching circuit is disclosed which utilizes a four-terminal Darlington transistor block to improve switching speed, particularly in rapid turn-off. Two independent reverse drive currents are utilized during turn-off in order to expel the minority carriers of the Darlington pair at their own charge sweep-out rate. The reverse drive current may be provided by a current transformer, the secondary of which is tapped to the base terminal of the power stage of the Darlington block. In one application, the switching circuit is used in each power switching element in a chopper-inverter drive of an electric vehicle propulsion system.

  14. Carbon Nanotubes, Semiconductor Nanowires and Graphene for Thin Film Transistor and Circuit Applications

    NASA Astrophysics Data System (ADS)

    Pribat, Didier; Cojocaru, Costel-Sorin

    2011-03-01

    In this paper, we briefly review the use of carbon nanotubes and semiconductor nanowires, which represent a new class of nanomaterials actively studied for thin film transistors and electronics applications. Although these nanomaterials are usually synthesised at moderate to high temperatures, they can be transferred to any kind of substrate after growth, paving the way for the fabrication of flexible displays and large area electronics systems on plastic. Over the past few years, the field has progressed well beyond the realisation of elementary devices, since active matrix displays driven by nanowire thin film transistors have been demonstrated, as well as the fabrication of medium scale integrated circuits based on random arrays of carbon nanotubes. Also, graphene, a new nanomaterial has appeared in the landscape; although it is a zero gap semiconductor, it can still be used to make transistors, provided narrow ribbons or bilayers are used. Graphene is also a serious contender for the replacement of oxide-based transparent conducting films.

  15. Organic Transistor Circuits for Application to Organic Light-Emitting-Diode Displays

    Microsoft Academic Search

    Masatoshi Kitamura; Tadahiro Imada; Yasuhiko Arakawa

    2003-01-01

    Organic thin-film transistor circuits based on the small molecule, copper phthalocyanine, have been demonstrated for application to an active-matrix display with organic light-emitting diodes. The circuit consists of two organic thin-film transistors and one storage capacitor which provide continuous current under pulsed operation. The transistors for the circuit have been designed on the basis of the current characteristics of the

  16. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  17. Telesensor integrated circuits.

    PubMed

    Ferrell, T L; Britton, C L; Bryan, W L; Clonts, L G; Emery, M S; Ericson, M N; Merraudeau, F; Morrison, G W; Passian, A; Smith, S F; Threatt, T D; Turner, G W; Wintenberg, A L

    2001-11-01

    Progress in personal computing has recently permitted small research programs to design and simulate application-specific integrated circuits (ASICs). Inexpensive fabrication of silicon chips can then be obtained using chip foundries, and quite complex circuits can be greatly reduced in size with an accompanying increase in certain performance characteristics. Within the past 5 years it has also become possible to design ASICs which can transmit and receive radio signals and which thus may be employed in applications in which wired connections for input and output of signals are not practicable. We are currently developing research-grade prototype ASICs for the monitoring of human vital signs. In this case one or more sensors placed on an ASIC provides a signal to be transmitted a distance of 2-3 meters to a receiver/display unit. The use of ASIC telesensors provides the possibility of wireless monitoring, including long-term monitoring, with inexpensive and unencumbering devices. Their self-contained nature permits a number of potential uses in future biomedical applications as new sensors are devised which are amenable to deployment on silicon. PMID:11760745

  18. CMOS ASIC (application specific integrated circuit)

    SciTech Connect

    Nuckolls, L.R.

    1989-07-01

    This paper discusses the following topics: semicustom integrated circuits; radiation effects and hardness; circuit design considerations; the design cycle; fault analysis and design for test; and circuit layout.

  19. A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

    Microsoft Academic Search

    Shigeyoshi Watanabe; Kenji Tsuchida; Daisaburo Takashima; Yukihito Oowaki; Akihiro Nitayama; Katsuhiko Hieda; Hirishi Takato; Kazumasa Sunouchi; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka; Hisashi Hara

    1995-01-01

    This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by

  20. Methodologies for statistical behavioral modeling and simulation of complex analog integrated circuits 

    E-print Network

    Swidzinski, Jan

    1997-01-01

    transistors, statistical i-nodeling techniques for integrated circuits, statistical behavioral modeling of analog functional blocks, and finally statistical behavioral system level modeling and simulation. A full statistical model for the behavioral parameters...

  1. Some properties and circuit applications of super–alpha composite transistors

    Microsoft Academic Search

    A. R. Pearlman

    1955-01-01

    A three-terminal amplifying device having the characteristics of a super-alpha Junction transistor can be constructed by making suitable interconnections between ordinary medium-alpha Junction transistors. It is shown that the circuit properties of such a device are very similar to those of a vacuum tube for many applications. Voltage-follower and voltage-amplifier circuits using composite transistors are described. Characteristics of two-stage and

  2. Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

    SciTech Connect

    Takano, H.; Hosogi, K.; Kato, T. [Mitsubishi Electric Corp., Itami (Japan)] [and others] [Mitsubishi Electric Corp., Itami (Japan); and others

    1995-05-01

    A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.

  3. Graphene-Dielectric Integration for Graphene Transistors

    PubMed Central

    Liao, Lei; Duan, Xiangfeng

    2010-01-01

    Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-? dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities. PMID:21278913

  4. A hybrid nanomemristor/transistor logic circuit capable of self-programming.

    PubMed

    Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

    2009-02-10

    Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

  5. CADAT integrated circuit mask analysis

    NASA Technical Reports Server (NTRS)

    1981-01-01

    CADAT System Mask Analysis Program (MAPS2) is automated software tool for analyzing integrated-circuit mask design. Included in MAPS2 functions are artwork verification, device identification, nodal analysis, capacitance calculation, and logic equation generation.

  6. Analysis of a novel drive circuit for bipolar transistor switches in dc-dc converters

    Microsoft Academic Search

    R. Osabe; H. Matsuo

    2003-01-01

    When employing a bipolar transistor as a main switch in the dc-dc converter, the driving circuit with the current transformer is widely used to improve the power efficiency. However, it is also known that there exists low limit of the turn on time of the main switch in this conventional driving circuit. In this paper, a novel driving circuit for

  7. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  8. Radio Frequency Integrated Circuits

    E-print Network

    and complete transmitters. Measured results of individual circuit blocks, subsystems (e.g. VCO together Temperature Co-fired Ceramic (LTCC) packaging has been manufactured and evaluated, including a balun structure and transmitter presented in this thesis. Fifthly, thanks to my former diploma supervisor and fellow Ph.D student

  9. Supporting Information for: Programmable Resistive-Switch Nanowire Transistor Logic Circuits

    E-print Network

    Lieber, Charles M.

    Supporting Information for: Programmable Resistive-Switch Nanowire Transistor Logic Circuits of a resistive-switch nanowire transistor at different programmed states. (a) (Left panel) For a programmed active state (the resistive switch is at ON state), the Ge/Si nanowire channel is depleted for a Vg

  10. Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits

    E-print Network

    Yener, Aylin

    Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior by the Editor #12;Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior -- In this paper, we characterize the Energy-Delay performance of logic circuits realized using Single Electron

  11. RELIABILITY ANALYSIS OF DYNAMIC LOGIC CIRCUITS UNDER TRANSISTOR AGING EFFECTS IN NANOTECHNOLOGY

    E-print Network

    Mahmoodi, Hamid

    As the CMOS technology scales down towards nanoscale dimensions, there are increasing transistor reliability on performance metrics of a dynamic logic circuit, namely, delay, power, and Unity Noise Gain (UNG). It is observed that the aging of the PMOS keeper transistor and the PMOS in the output inverter of a dynamic

  12. Logic and transistor circuit verification using regression testing and hierarchical recursive learning 

    E-print Network

    Shao, Li

    1996-01-01

    We describe a new approach for formal verification of combinational logic circuits, and their switch-level transistor implementation. Our approach CODibines regression testing, hierarchical recursive learning, and test generation techniques. A...

  13. Superconductor integrated circuit fabrication technology

    Microsoft Academic Search

    LYNN A. ABELSON; GEORGE L. KERBER

    2004-01-01

    Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates\\/cm2. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex

  14. Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

    Microsoft Academic Search

    Alexandre Schmid; Yusuf Leblebici

    2003-01-01

    This paper addresses the functional robustness and fault-tolerance capability of very-deep submicron CMOS and single-electron transistor (SET) circuits. A set of guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. Empirical results based on SPICE simulations show that the proposed design method improves fault immunity at transistor level. Graceful degradation of circuit

  15. Circuit-level simulation of transistor lasers and its application to modelling of microwave photonic links

    NASA Astrophysics Data System (ADS)

    Iezekiel, Stavros; Christou, Andreas

    2015-03-01

    Equivalent circuit models of a transistor laser are used to investigate the suitability of this relatively new device for analog microwave photonic links. The three-terminal nature of the device enables transistor-based circuit design techniques to be applied to optoelectronic transmitter design. To this end, we investigate the application of balanced microwave amplifier topologies in order to enable low-noise links to be realized with reduced intermodulation distortion and improved RF impedance matching compared to conventional microwave photonic links.

  16. Organic thin-film transistors: Characterization and integration on low temperature substrates for flexible electronics

    NASA Astrophysics Data System (ADS)

    Gowrisanker, Srinivas

    In this work pentacene thin-film transistors (TFTs) are fabricated and characterized on low temperature substrates for flexible electronic applications. Maximum processing temperature is <120°C. Pentacene transistors are optimized by varying the deposition conditions, thickness ratio of source-drain metal contact to pentacene film. By using parylene as the gate dielectric film, pentacene TFTs with low threshold voltage (VT) and low V T variation are fabricated. Gate-last integration technique is presented enabling integration of pentacene p-type TFTs with a:Si:H n-type TFTs to form hybrid complementary metal-oxide-semiconductor (CMOS) circuits on polyethylene naphthalate (PEN). Circuits evaluated are inverters, 2-input NAND and NOR logic gates. Parylene gate dielectric reliability and gate bias stress analysis of TFTs and hybrid CMOS circuit is also presented.

  17. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    NASA Technical Reports Server (NTRS)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  18. Bipolar junction transistor models for circuit simulation of cosmic-ray-induced soft errors

    NASA Technical Reports Server (NTRS)

    Benumof, R.; Zoutendyk, J.

    1984-01-01

    This paper examines bipolar junction transistor models suitable for calculating the effects of large excursions of some of the variables determining the operation of a transistor. Both the Ebers-Moll and Gummel-Poon models are studied, and the junction and diffusion capacitances are evaluated on the basis of the latter model. The most interesting result of this analysis is that a bipolar junction transistor when struck by a cosmic particle may cause a single event upset in an electronic circuit if the transistor is operated at a low forward base-emitter bias.

  19. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  20. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2010-01-01

    The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

  1. Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

    NASA Technical Reports Server (NTRS)

    Mclyman, W. T. (inventor)

    1981-01-01

    In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

  2. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  3. Optoelectronic and Photonic Integrated Circuits

    Microsoft Academic Search

    Kiyohide Wakao

    \\u000a Optical technology has come to be used in optical communication, light information, and optical measurement. Optical semiconductor\\u000a devices offer high performance and reliability, and studies on optical semiconductor integrated circuits (ICs) have focused\\u000a on improving their performance, functionality, usefulness and reliability.

  4. EMP Susceptibility of Integrated Circuits

    Microsoft Academic Search

    C. R. Jenkins; D. L. Durgin

    1975-01-01

    This paper summarizes the results of a major test program which involved the measurement of the pulse power failure thresholds of 41 integrated circuit types, representing seven logic families. The pulse widths used in these tests range from 0.1 microsecond to 10 microseconds. The failure threshold data have been grouped by logic family and test terminal to form failure categories.

  5. Micromechanical photonic integrated circuits

    Microsoft Academic Search

    Ming C. Wu

    2000-01-01

    The ability to integrate micro-optical elements with movable structures and microactuators has opened up many new opportunities for optical and optoelectronic systems. It allows us to manipulate optical beams more effectively than conventional methods, and is scalable to large optical systems. Optical MEMS (microelectromechanical systems) have applications in display, sensing, and optical data storage. Recently, telecommunications have become the market

  6. Circuit engineering and technological optimization of very high speed LSI logic elements and transistor structures

    Microsoft Academic Search

    A. N. Bubennikov

    1984-01-01

    The prospects of adapting the structural and technological parameters of logic elements and concurrent current circuit engineering and technological optimization of logic elements and transistor structures are examined. It is found that concurrent optimization makes it possible to achieve better VLSI circuit use from the viewpoint of the level of circuitry and base technological implementation achieved. Adaptation of the structural

  7. Stability of amorphous silicon thin film transistors and circuits

    NASA Astrophysics Data System (ADS)

    Liu, Ting

    Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used for the active-matrix addressing of flat panel displays, optical scanners and sensors. Extending the application of the a-Si TFTs from switches to current sources, which requires continuous operation such as for active-matrix organic light-emitting-diode (AMOLED) pixels, makes stability a critical issue. This thesis first presents a two-stage model for the stability characterization and reliable lifetime prediction for highly stable a-Si TFTs under low gate-field stress. Two stages of the threshold voltage shift are identified from the decrease of the drain saturation current under low-gate field. The first initial stage dominates up to hours or days near room temperature. It can be characterized with a stretched-exponential model, with the underlying physical mechanism of charge trapping in the gate dielectric. The second stage dominates in the long term and then saturates. It corresponds to the breaking of weak bonds in the amorphous silicon. It can be modeled with a "unified stretched exponential fit," in which a thermalization energy is used to unify experimental measurements of drain current decay at different temperatures into a single curve. Two groups of experiments were conducted to reduce the drain current instability of a-Si TFTs under prolonged gate bias. Deposition conditions for the silicon nitride (SiNx) gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive ion etching steps, or with all wet etching steps, the latter in a new process. The two-stage model that unites charge trapping in the SiNx gate dielectric and defect generation in the a-Si channel was used to interpret the experimental results. We identified the optimal substrate temperature, gas flow ratios, and RF deposition power densities. The stability of the a-Si channel depends also on the deposition conditions for the underlying SiNx gate insulator. TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% decay time of the drain current of back channel passivated dry-etched TFTs under continuous operation at 20°C from 3.3 x 104 sec (9.2 hours) to 4.4 x 107 sec (1.4 years). The 50% lifetime can be further improved by ˜2 times through wet etching process. Two assumptions in the two-stage model were revisited. First, the distribution of the gap state density in a-Si was obtained with the field-effect technique. The redistribution of the gap state density after low-gate field stress supports the idea that defect creation in a-Si dominates in the long term. Second, the drain-bias dependence of drain current degradation was measured and modeled. The unified stretched exponential was validated for a-Si TFTs operating in saturation. Finally, a new 3-TFT voltage-programmed pixel circuit with an in-pixel current source is presented. This circuit is largely insensitive to the TFT threshold voltage shift. The fabricated pixel circuit provides organic light-emitting diode (OLED) currents ranging from 25 nA to 2.9 microA, an on/off ratio of 116 at typical quarter graphics display resolution (QVGA) display timing. The overall conclusion of this thesis research is that the operating life of a-Si TFTs can be quite long, and that these transistors can expect to find yet more applications in large area electronics.

  8. Microfluidic photonic integrated circuits

    Microsoft Academic Search

    Sung Hwan Cho; Jessica Godin; Chun Hao Chen; Frank S. Tsai; Yu-Hwa Lo

    2008-01-01

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled twodimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are

  9. Yield learning model for integrated circuit package 

    E-print Network

    Balasubramaniam, Gaurishankar

    1996-01-01

    In a semiconductor industry, packaging of integrated circuit chips, product quality control and rapid problem diagnosis are very critical to economic success. The integrated circuit package makes up a large fraction of the total production cost...

  10. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  11. The Impact of On-Chip Interconnections on CMOS RF Integrated Circuits

    Microsoft Academic Search

    Munir M. El-Desouki; Samar M. Abdelsayed; M. Jamal Deen; Natalia K. Nikolova; Yaser M. Haddara

    2009-01-01

    Achieving power- and area-efficient fully integrated transceivers is one of the major challenges faced when designing high-frequency electronic circuits suitable for biomedical applications or wireless sensor networks. The power losses associated with the parasitics of on-chip inductors, transistors, and interconnections have posed design challenges in the full integration of power-efficient CMOS radio-frequency integrated circuits (RF ICs). In addition, the parasitics

  12. Microfluidic Photonic Integrated Circuits

    PubMed Central

    Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S.; Lo, Yu-Hwa

    2010-01-01

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled two-dimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1–10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments. PMID:20428483

  13. Microfluidic Photonic Integrated Circuits.

    PubMed

    Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S; Lo, Yu-Hwa

    2008-11-18

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled two-dimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1-10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments. PMID:20428483

  14. A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

    NASA Astrophysics Data System (ADS)

    Gutiérrez-Heredia, G.; González, L. A.; Alshareef, H. N.; Gnade, B. E.; Quevedo-López, M.

    2010-11-01

    We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 µA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 µA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented.

  15. A circuit-compatible model of ballistic carbon nanotube field-effect transistors

    Microsoft Academic Search

    Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy

    2004-01-01

    Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V

  16. A miniature microcontroller curve tracing circuit for space flight testing transistors

    NASA Astrophysics Data System (ADS)

    Prokop, N.; Greer, L.; Krasowski, M.; Flatico, J.; Spina, D.

    2015-02-01

    This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

  17. Ultra-low power microwave CHFET integrated circuit development

    SciTech Connect

    Baca, A.G.; Hietala, V.M.; Greenway, D.; Sloan, L.R.; Shul, R.J.; Muyshondt, G.P.; Dubbert, D.F.

    1998-04-01

    This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

  18. Simulation of Circuits Composed of HTSC-Single Hole Transistors by Using Superconducting SET-SPICE

    NASA Astrophysics Data System (ADS)

    Shen, B.; Jiang, J. F.; Cai, Q. Y.

    2000-11-01

    We have adapted the single electron transistor SPICE (SET-SPICE) in order to introduce the device model of HTSC-single hole transistor (HTSC-SHT) into the general-purpose circuit simulator SPICE. Some results of the simulation from the SuSET-SPICE are compared with those from the Monte-Carlo reference simulator. This work is based on the semiclassical theory of the single electron tunneling effects, and provides an approach to the simulation of the large scale and hybrid circuits containing superconducting single electron devices.

  19. Printed inorganic transistors

    E-print Network

    Ridley, Brent (Brent Alan), 1974-

    2003-01-01

    Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

  20. The resonant gate transistor

    Microsoft Academic Search

    HARVEY C. NATHANSON; WILLIAM E. NEWELL; ROBERT A. WICKSTROM

    1967-01-01

    A device is described which permits high-Qfrequency selection to be incorporated into silicon integrated circuits. It is essentially an electrostatically excited tuning fork employing field-effect transistor \\

  1. Metal problems in plastic encapsulated integrated circuits

    Microsoft Academic Search

    E. D. Metz

    1969-01-01

    The long-term reliability of plastic encapsulated integrated circuits in humid environments is ultimately limited by the effects of entering moisture. Degradation of device characteristics may be acceptable in some types of circuits, but catastrophic failures (\\

  2. Process oriented design aids for very large scale integrated circuits

    Microsoft Academic Search

    M. Kamiya

    1979-01-01

    Process oriented circuit design aids to simulate the more complex circuits, and still accurately reflect the smaller size MOS transistor characteristics are developed. Precise device modeling for small size MOSFET's, process characterization in connection with device model parameters, and development of the presently available high level LSI logic circuit simulator (MOTIS), compatible with a general purpose circuit analysis program such

  3. A New Bipolar Type Transistor Created Based on Interface Effects of Integrated All Perovskite Oxides

    NASA Astrophysics Data System (ADS)

    Xia, Feng-Jin; Wu, Hao; Fu, Yue-Ju; Xu, Bo; Yuan, Jie; Zhu, Bei-Yi; Qiu, Xiang-Gang; Cao, Li-Xin; Li, Jun-Jie; Jin, Ai-Zi; Wang, Yu-Mei; Li, Fang-Hua; Liu, Bao-Ting; Xie, Zhong; Zhao, Bai-Ru

    2012-10-01

    Oxide transistor is the basic device to construct the oxide electronic circuit that is the backing to develop integrated oxide electronics with high efficiency and low power consumption. By growing the perovskite oxide integrated layers and tailoring them to lead semiconducting functions at their interfaces, the development of oxide transistors may be able to perform. We realize a kind of p-i-n type integrated layers consisting of an n-type cuprate superconductor, p-type colossal magnetoresistance manganite, and a ferroelectric barrier (i). From this, bipolar transistors were fabricated at the back-to-back p-i-n junctions, for which the Schottky emission and p-n junction barriers, as well as the ferroelectric polarization, were integrated into the interfaces to control the transport properties; a preliminary but distinct current gain greater than 1.6 at input current of microampers order was observed. These results present a real possibility to date for developing bipolar all perovskite oxide transistors.

  4. Novel Asymmetric Tunnel Source Transistors for Energy Efficient Circuits and Mixed Signal Applications

    NASA Astrophysics Data System (ADS)

    Jhaveri, Ritesh Atul

    Over the history of integrated circuits, a gargantuan increase in speed and performance has been achieved due to the trend of scaling. In recent years, however, many daunting challenges arise as we scale into sub-32nm regime. The building block of the MOSFET device, Silicon, is being pushed to its performance limitation. New materials and design methodologies are being investigated to extract better performance. In this study, we concentrate on two flavors of Novel Source Tunneling Transistors: the Schottky Tunnel Source FET and the Source Pocket band-to-band tunneling FET. Schottky barrier FETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-32nm technology nodes. In this study, an asymmetric Schottky Tunnel Source SOI FET (STS-FET) has been proposed. The STS-FET has the source/drain regions replaced with metal/silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the injection of carriers through gate controlled Schottky barrier tunneling at the source. The optimized device structure shows improved performance as compared to conventional Schottky FETs. The analog performance of the STS-FET was studied and the device was found to be a superior alternative to conventional CMOS transistors. Various process modules were designed and developed. The STS-FET was then fabricated with NiSi technology and successfully demonstrated for 0.11mum gate lengths. The high immunity to short channel effects and the excellent analog performance of the device makes it an attractive candidate for continued scaling into sub 32nm node as well as mixed signal applications. Energy Efficiency is also an important concern for sub-32nm CMOS integrated circuits. Scaling of devices to below 32nm leads to an increase in active power dissipation (CVDD2.f) and off-state power (IOFF·VDD). Hence, new device innovations are being explored to address these problems. In this study, a novel source-pocket tunnel field effect transistor (SP-TFET), based on the principle of band to band tunneling is proposed. TFETs have the potential to overcome the 60mV/dec limit set on the subthreshold swing of conventional CMOS transistors thus making them very attractive for continued power supply scaling. p-i-n TFETs and source-pocket TFETs were studied, optimized and successfully demonstrated on both bulk and SOI substrates. The source-pocket TFET shows better performance when compared to a p-i-n TFET. The source pocket TFET was also compared to various other TFETs in literature. The comparison suggests that if multiple strategies are used to improve the device performance, the source pocket TFET along with other TFETs can be very attractive alternatives to conventional MOSFET devices especially for low power applications.

  5. Transistors

    NSDL National Science Digital Library

    Mr. Blackburn

    2004-07-05

    How does a transistor work ? History of semi-conductors Visit the museum of how the transistor was developed. Transistor history The Transistor Museum How stuff works Visit this site and follow through a short course on how a semi-conductor works. How stuff works PBS site Visit the PBS site of transistors and semi-conductors. Watch shorth videos on the development of the transistor. Timeline pbs ...

  6. V.DMOS transistor modeling for simulation of power electronic circuits

    Microsoft Academic Search

    Malgorzata Napieralska

    1991-01-01

    A nonlinear, short channel model of a power V.DMOS transistor, the elements of which depend only on physical and technological data, is presented. By an analysis of the active regions of the V.DMOS structure, in order to study switching modes, this model is simplified to a topology compatible with the SPICE circuit simulator. Parameter extraction methods and validation programs are

  7. Modeling and characterization of organic thin film transistors for circuit design

    Microsoft Academic Search

    M. Fadlallah; W. Benzarti; G. Billiot; W. Eccleston; D. Barclay

    2006-01-01

    In this paper, we develop a device model of an organic thin film transistor for a circuit design, more specifically, for organic radio frequency identification applications. This model is based on variable range hopping theory, i.e., a carrier may either hop over a small distance with a high activation energy or hop over a long distance with a low activation

  8. Integrated circuit generating 3- and 5-scroll attractors

    NASA Astrophysics Data System (ADS)

    Trejo-Guerra, R.; Tlelo-Cuautle, E.; Jiménez-Fuentes, J. M.; Sánchez-López, C.; Muñoz-Pacheco, J. M.; Espinosa-Flores-Verdad, G.; Rocha-Pérez, J. M.

    2012-11-01

    This paper introduces the experimental realization of the first integrated circuit of a multi-scroll continuous chaotic oscillator showing 3- and 5-scroll attractors. It is based on a variant of the Chua's system. The most relevant issue is the implementation of a saw-tooth-like nonlinear function, which is designed by using floating gate MOS (FGMOS) transistors. Therefore, the realization of a voltage-to-current nonlinear cell by a piecewise-linear approach allows us to have only two external control inputs instead of numerous external voltage references, as usually done in current circuit realizations. Experimental results of the proposed integrated multi-scroll oscillator along with its corner analysis are provided.

  9. Computer aided design of MOS integrated circuits

    Microsoft Academic Search

    C. W. Gwyn

    1974-01-01

    Computer aided design (CAD) techniques provide the circuit designer with a complete set of computer programs to aid in a step by step design of an integrated circuit (IC). A list of computer software based on circuit design using a standard cell library and a typical design sequence are presented for complete custom MOS digital IC design from logic description

  10. Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign

    E-print Network

    EE134 1 Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignIntroduction ! Why is designing digital ICs different today than it was before? ! Will it change in future? #12;EE134

  11. Asynchronous sequential circuit design using pass transistor iterative logic arrays

    NASA Technical Reports Server (NTRS)

    Liu, M. N.; Maki, G. K.; Whitaker, S. R.

    1991-01-01

    The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

  12. Integrated circuits and logic operations based on single-layer MoS2.

    PubMed

    Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

    2011-12-27

    Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced. PMID:22073905

  13. Diamond-integrated optomechanical circuits.

    PubMed

    Rath, Patrik; Khasminskaya, Svetlana; Nebel, Christoph; Wild, Christoph; Pernice, Wolfram H P

    2013-01-01

    Diamond offers unique material advantages for the realization of micro- and nanomechanical resonators because of its high Young's modulus, compatibility with harsh environments and superior thermal properties. At the same time, the wide electronic bandgap of 5.45 eV makes diamond a suitable material for integrated optics because of broadband transparency and the absence of free-carrier absorption commonly encountered in silicon photonics. Here we take advantage of both to engineer full-scale optomechanical circuits in diamond thin films. We show that polycrystalline diamond films fabricated by chemical vapour deposition provide a convenient wafer-scale substrate for the realization of high-quality nanophotonic devices. Using free-standing nanomechanical resonators embedded in on-chip Mach-Zehnder interferometers, we demonstrate efficient optomechanical transduction via gradient optical forces. Fabricated diamond resonators reproducibly show high mechanical quality factors up to 11,200. Our low cost, wideband, carrier-free photonic circuits hold promise for all-optical sensing and optomechanical signal processing at ultra-high frequencies. PMID:23575694

  14. EEE 6328 Microwave IC Design 1. Catalog Description (3 credits) Fundamentals of microwave integrated circuit

    E-print Network

    Fang, Yuguang "Michael"

    of fundamentals of design and testing of RF integrated, circuits operating at microwave frequencies 4 - Microwave Transistor Amplifiers Analysis and Design b. Author - G. Gonzalez c. Publication date and edition(2hours) Week 9 (3/12) (22~24) amplifier power gain (Lec. 22-23), stability (Lec. 24) Week 10 (3/19) (25

  15. Aerosol-Jet-Printed, 1 Volt HBridge Drive Circuit on Plastic with Integrated Electrochromic Pixel

    E-print Network

    Kim, Chris H.

    Aerosol-Jet-Printed, 1 Volt HBridge Drive Circuit on Plastic with Integrated Electrochromic Pixel electrochromic (EC) pixel as large as 4 mm2 that is printed on the same substrate. All of the key components, flexible electronics, electrochromic pixel, transistor, capacitor, ion gel 1. INTRODUCTION Printing

  16. Computer-Aided Analysis of RFI Effects in Digital Integrated Circuits

    Microsoft Academic Search

    James Whalen; Joseoh Tront; Curtis Larson; James Roe

    1979-01-01

    A computer-aided analysis procedure based upon a modified Ebers-Moli transistor model is used to predict RFI effects in bipolar integrated circuits (IC's). The procedure is applied to a digital IC to determine the RF power levels that cause several EM susceptibility thresholds to be exceeded.

  17. Field Effect Transistor /FET/ circuit for variable gin amplifiers

    NASA Technical Reports Server (NTRS)

    Spaid, G. H.

    1969-01-01

    Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

  18. InP photonic integrated circuits

    Microsoft Academic Search

    M. K. Smit

    2002-01-01

    Photonic integrated circuits have the potential to reduce the volume and packaging costs of complex photonic devices. In this presentation an overview of InP-based photonic integration technology and examples of advanced photonic ICs are given.

  19. Photonic crystal devices for photonic integrated circuits

    Microsoft Academic Search

    Min-Hsiung Shih

    2006-01-01

    Photonic crystal devices are potential candidates for chip-scale, dense photonic integrated circuits because photonic crystal devices have versatile optical characteristics and compact size. This thesis presents works to understand the properties of isolated photonic crystal elements before implement photonic integrated circuits with these individual elements as components. In this thesis, a brief introduction for photonic crystals will be followed by

  20. Susceptibility of Integrated Circuits to RFI

    Microsoft Academic Search

    V. Pozzolo; P. Tenti; F. Fiori; G. Spiazzi; S. Buso

    This paper surveys the results of an extended research activity concerning the effects of radio frequency interference (RFI) on integrated circuits (IC's). Initially, the possible injection methods for conducted and radiated interference are presented, discussing their applicability and limitations. Then, the basic results of the susceptibility analysis of operational amplifiers and smart power integrated circuits are briefly discussed. Finally, experimental

  1. e bipolar junction transistor (BJT) is historically the first solid-state analog amplifier and digital switch, and formed the basis of integrated circuits (IC) in the 1970s. Starting in the early 1980s, the

    E-print Network

    Wilamowski, Bogdan Maciej

    transistor back into high-volume commercial production, mainly for the now widespread wire- less and wire spaced PN junctions connected back to back sharing the same p-type region, as shown in Figure 9.1a. e...........................................................................9-12 Thermal Sensitivity · Second Order Effects · SPICE Model of the Bipolar Transistor 9.8 Si

  2. Floating-Gates Transistors For Precision Analog Circuit Design: An Overview Venkatesh Srinivasan, David W. Grahamand Paul Hasler

    E-print Network

    Graham, David W.

    Floating-Gates Transistors For Precision Analog Circuit Design: An Overview Venkatesh Srinivasan@ece.gatech.edu Abstract-- This paper presents an overview of floating-gate transistors with an emphasis on using them is such that floating-gate MOSFETs play the role of programmable elements while forming an inherent part

  3. Abstract--The parametric shifts or circuit failures caused by transistor aging have become more severe with shrinking device

    E-print Network

    Kim, Chris H.

    severe with shrinking device sizes and voltage margins. Designing circuits that can withstand these aging), and Time Dependent Dielectric Breakdown (TDDB) have become more severe with shrinking transistor sizes

  4. All-Printed Low Voltage Operation Polymer Transistors and Circuits Based on Ion Gel Gate Dielectrics

    NASA Astrophysics Data System (ADS)

    Xia, Yu; Cho, Jeong Ho; Ha, Mingjing; Renn, Michael; Frisbie, C.

    2009-03-01

    A key challenge in the development of organic electronics lies in the realization of high quality devices with low cost. In this presentation, we demonstrate high performance polymer transistors and circuits with all components fabricated by a commercial aerosol jet printing technique. Printing saves the device manufacturing cost through its simple procedure, fast speed, high throughput and low waste of materials. Furthermore, by employing a specially designed ion gel as the gate dielectric material, ultra-high density carrier accumulation (> 10^14 cm-2) can be achieved in the transistor channel, which results in an exceptionally large transconductance of 10 ?S/?m. Our typical transistors have mobility higher than 1cm^2/Vs and frequency response up to 10 kHz. Inverters, NAND and NOR logic circuits and ring oscillators have been realized as well, with low operation voltage, fast speed and high gain. In addition, the high polarizability of the gate dielectric allows us to print the gate electrode of each single transistor along with its source and drain electrodes at the same time in a coplanar architecture, which significantly simplifies the fabrication procedure.

  5. Modularized construction of general integrated circuits on individual carbon nanotubes.

    PubMed

    Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

    2014-06-11

    While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future. PMID:24796796

  6. SC filters and design centering of integrated circuits. Part 2: Design centering of integrated circuits

    NASA Astrophysics Data System (ADS)

    Lueder, E.; Kreutzer, H.; Opelt, M.

    1984-12-01

    A statistical program for design centering for cheap production of integrated circuits was developed. Design centering provides mathematical means to shift the parameters of a circuit to a location (design center), where they can fluctuate in a wider range without impairing the function of the circuit. The method can be used to enhance the performance of an integrated circuit. With a modification of the program the design center can also be found starting with circuit parameters which do not meet the tolerance specifications. The program is successfully applied to the design of VLSI circuits.

  7. Realistic single-electron transistor modeling and novel CMOS\\/SET hybrid circuits

    Microsoft Academic Search

    Ki-Whan Song; Gwanghyeon Baek; Sang-Hoon Lee; Dae Hwan Kim; Kyung Rok Kim; Dong-Soo Woo; Jae Sung Sim; Jong Duk Lee; Byung-Gook Park

    2003-01-01

    A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of

  8. An Electronic Tongue System Design Using Ion Sensitive Field Effect Transistors and Their Interfacing Circuit Techniques

    Microsoft Academic Search

    Wen-Yaw Chung; Kuo-Chung Chang; Da-You Hong; Cheanyeh Cheng; F. Cruza; Tai Sung Liu; D. G. Pijanowska; M. Dawgul; W. Torbicz; Chung Huang Yang; Pitor B. Grabiec; Bohdan Jarosewicz; Jung-Lung Chiang

    2008-01-01

    This paper proposes an electronic tongue system design using ion sensitive field effect transistors (ISFETs), extended-gate FET (EGFET) and their interfacing circuit techniques. Bridge-type constant voltage, constant current, and temperature compensation circuitries have all been developed for ISFET to sense hydrogen and chloride ions for water quality monitoring applications. This design offers a sensitivity of over 54 mV\\/pH and an

  9. Testing tri-state and pass transistor circuit structures

    E-print Network

    Parikh, Shaishav Shailesh

    2005-11-01

    will cause some lines in the circuit to float and take unknown values. A stuck-on control line can cause fighting when the two drivers connected to the same node drive different values. This thesis develops new gate level fault models and dynamic test...

  10. Gerentology of Silicon Integrated Circuits

    Microsoft Academic Search

    M. I. Gorlov; A. V. Strogonov

    2001-01-01

    The lifetime of silicon ICs in relation to material and component aging is discussed. The service time of the circuits was predicted from accelerated tests. The lifetime of circuits of series 106, 134, 1804, 582, and 136 was evaluated from parameter failures with the Box–Jenkins model.

  11. Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits.

    PubMed

    Sporea, R A; Trainor, M J; Young, N D; Shannon, J M; Silva, S R P

    2014-01-01

    Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

  12. Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

    PubMed Central

    Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

    2014-01-01

    Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

  13. Photonic Interconnections Integrated circuits (ICs) are tradi

    E-print Network

    Fossum, Eric R.

    Photonic Interconnections Integrated circuits (ICs) are tradi tionally connected internally The taxonomy of photonically in terconnected circuits consists. of three primary components: an opti cal source of photonic fre quencies enable waveguides to be made much smaller. Thus, the alter native of connecting ICs

  14. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits

    PubMed Central

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M.

    2009-01-01

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (Vout) versus input (Vin) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of ?45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits. PMID:19940239

  15. Robotic workcell for wire wrapping integrated circuits

    Microsoft Academic Search

    D. O. Law

    1992-01-01

    A robotic workcell was developed that electrically shorts the leads of integrated circuits by weaving a 0.005-in. copper wire around individual leads. This workcell has the capability to manipulate 13 different integrated circuit body styles including 14- to 64-lead flatpacks, 14- to 40-pin dual inline packages, and 3- to 10-pin cans. Features of the system include automatic program selection based

  16. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

    PubMed

    Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

    2008-07-24

    The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics. PMID:18650920

  17. Multiple-input, multiple-output pass transistor logic

    Microsoft Academic Search

    M. SHAMANNA; K. CAMERON; S. R. WHITAKER

    1995-01-01

    Techniques are presented for the design of multiple-input, multiple-output pass transistor circuits. By using shared functions as map-entered variables, dramatic reductions in transistor count can be achieved. Applied to a Viterbi decoder design for NASA, the transistor count of a CMOS integrated circuit was reduced by nearly 100000 transistors over the best previously known techniques. A proof is presented which

  18. Control of threshold voltage in organic thin-film transistors by modifying gate electrode surface with MoOX aqueous solution and inverter circuit applications

    NASA Astrophysics Data System (ADS)

    Shiwaku, Rei; Yoshimura, Yudai; Takeda, Yasunori; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

    2015-02-01

    We controlled the threshold voltage of organic thin-film transistors (TFTs) by treating only the gate electrode surface with a MoOX aqueous solution and used them to build inverter circuits. The threshold voltage was changed by varying the concentration of the MoOX aqueous solution. A strong correlation between the work function of the gate electrode and the threshold voltage was observed. The threshold voltage of one of the two organic TFT devices in the inverter circuit was selectively changed by +2.3 V by reducing the concentration of the MoOx solution. We controlled the switching voltage of p-type organic inverter circuits and obtained excellent inverter characteristics. These results indicate that using a MoOx aqueous solution to control the threshold voltage is very useful for integrated circuits applications.

  19. Nano-technology-device prospects: quantum dots and transistors for ultracompact integration and terahertz analogue applications

    Microsoft Academic Search

    H. L. Hartnagel

    1998-01-01

    Nanometric-sized transistors can be employed to control the charge transfer from one quantum dot (QD) to another one. The charge in a QD can also be used to control the transistor current. In principle here then electronics is not related to currents but due to charges. It is of interest, not only to apply this to ultracompact digital circuits, but

  20. Integrated Circuit Stellar Magnitude Simulator

    ERIC Educational Resources Information Center

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  1. ECE 423 CMOS Integrated Circuits II Catalog Description: Analysis and design of analog integrated circuits in CMOS technology;

    E-print Network

    ECE 423 ­ CMOS Integrated Circuits II Catalog Description: Analysis and design of analog integrated Integrated Circuits, Gray and Meyer, John Wiley & Sons, 2001 (required) Microelectronic Circuits, A. Sedra Integrated Circuits, B. Razavi, McGraw-Hill, 1999 (optional) Students with Disabilities: #12;Accommodations

  2. Four-Thin Film Transistor Pixel Electrode Circuits for Active-Matrix Organic Light-Emitting Displays

    Microsoft Academic Search

    Yi He; Reiji Hattori; Jerzy Kanicki

    2001-01-01

    Constant-current, four-thin-film-transistor (TFT) pixel electrode circuits, based on hydrogenated amorphous silicon (a-Si:H) TFT technology for active-matrix organic light-emitting displays (AM-OLEDs), have been designed, fabricated, and characterized. Experimental results indicate that continuous pixel electrode excitation can be achieved with these circuits. The pixel electrode circuits use a current driver to automatically adjust their current level for threshold voltage shifts of both

  3. Organic materials in future integrated optoelectronic circuits

    Microsoft Academic Search

    L. M. Walpita

    1990-01-01

    During the last two decades, lithium niobate has been extensively studied for applications in integrated optical circuits. However, it is difficult to integrate lithium niobate optical devices with semiconductor electronic devices because the materials are incompatible. In recent years, semiconductor materials have been emerging as the main contenders in applications; these materials have the advantage of allowing both optical and

  4. Millimeter wave integrated circuit techniques and technology

    Microsoft Academic Search

    Shiban Kishen Koul; Hauz Khas

    2010-01-01

    This paper presents techniques and technology for the design and development of low cost microwave and millimeter wave integrated circuits. Starting from the conventional microstrip, other key technologies including suspended stripline, dielectric integrated guides and micromachining are described. Design methodology leading to the development of several high performance components\\/subsystems at 35 GHz and 140 GHz is presented. The components reported

  5. Photonic integrated circuits: A technology update

    Microsoft Academic Search

    Serge Melle

    2008-01-01

    A photonic integrated circuit (PIC) monolithically integrates many optical components, such as lasers, modulators, detectors, attenuators, multiplexers, demultiplexers, and amplifiers, into a single photonic substrate and device. PICs thus provide important benefits for optical transmission systems, including packaging consolidation, increased system density, reduced power consumption, reduction in fiber couplings, and improved reliability.

  6. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

    PubMed

    Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

    2014-01-01

    Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42?GHz and a maximum oscillation frequency fMAX up to 50?GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9?GHz, fMAX~1?GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

  7. Integrated circuit tester evaluation study

    NASA Astrophysics Data System (ADS)

    Stevens, P.

    1980-03-01

    The primary AIMD test requirements for a small, inexpensive, commercially available, digital IC tester could be met by only one tester. This was the Automatic Fault Isolation Tester (AFIT) model 2050 manufactured by Testline Co. Many other testers were available that had the basic testing capability but were outside the price constraints or that were edge board testers. Bed-of-nails testers were not considered for AIMD use. The AFIT was submitted for technical and User Evaluations and demonstrated that it could detect faulty IC's on PC boards not coated with a conformal moisture-proofing compound. This fault detection ability was demonstrated for both the in-circuit and out-of-circuit modes of operation.

  8. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    NASA Technical Reports Server (NTRS)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  9. Integrating Circuit Analyses for Assertion-based Verification

    E-print Network

    Sen, Alper

    Integrating Circuit Analyses for Assertion-based Verification of Programmable AMS Circuits Dogan-signal (AMS) verification environment. Therefore, we integrate common analog circuit analyses into mixed-signal time-domain verification still remains a challenge. In this paper, we integrate circuit

  10. A novel interpretation of transistor S-parameters by poles and zeros for RF IC circuit design

    Microsoft Academic Search

    Shey-Shi Lu; T.-W. Chen; H.-C. Chen; C.-C. Meng

    2001-01-01

    In this paper, we have developed an interpretation of transistor S-parameters by poles and zeros. The results from our proposed method agreed well with experimental data from GaAs FETs and Si MOSFETs. The concept of source-series feedback was employed to analyze a transistor circuit set up for the measurement of the S-parameters. Our method can describe the frequency responses of

  11. Heterojunction field effect transistors (HJFETs) for a readout circuit of a cryogenically cooled far-infrared detector

    Microsoft Academic Search

    Iwao Hosako; Kenichi Okumura; Yukari Yamashita-Yui; Makoto Akiba; Norihisa Hiromoto

    1998-01-01

    Deep cryogenic field effect transistors (FETs) which are able to operate under liquid helium temperatures have significant advantages over conventional cryogenic Silicon- Junction-FETs or Si-metal-oxide-semiconductor-FETs as readout circuits of a far-IR focal plane array detector: simple operation, simple system structures, and large transconductance. We report the testing of an InGaAs-channel heterojunction field effect transistor (HJFET) operating at 4.2 K designed

  12. Advanced photonic integration and high-index-contrast circuit

    Microsoft Academic Search

    Sai Chu; B. Little; Wei Chen; J. Hryniewicz; F. Johnson; Wenlu Chen; O. King; R. Davidson; K. Donovan; D. Gill; J. Monk; F. Kish

    2009-01-01

    We highlight recent advances in advanced photonic integration of reliable densely integrated photonic integrated circuits (PIC) and high-index-contrast photonic lightwave circuits (PLC). The applications and benefits of these devices will be presented.

  13. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  14. Ambipolar MoTe2 transistors and their applications in logic circuits.

    PubMed

    Lin, Yen-Fu; Xu, Yong; Wang, Sheng-Tsung; Li, Song-Lin; Yamamoto, Mahito; Aparecido-Ferreira, Alex; Li, Wenwu; Sun, Huabin; Nakaharai, Shu; Jian, Wen-Bin; Ueno, Keiji; Tsukagoshi, Kazuhito

    2014-05-28

    We report ambipolar charge transport in ?-molybdenum ditelluride (MoTe2 ) flakes, whereby the temperature dependence of the electrical characteristics was systematically analyzed. The ambipolarity of the charge transport originated from the formation of Schottky barriers at the metal/MoTe2 contacts. The Schottky barrier heights as well as the current on/off ratio could be modified by modulating the electrostatic fields of the back-gate voltage (Vbg) and drain-source voltage (Vds). Using these ambipolar MoTe2 transistors we fabricated complementary inverters and amplifiers, demonstrating their feasibility for future digital and analog circuit applications. PMID:24692079

  15. Total dose and dose rate models for bipolar transistors in circuit simulation.

    SciTech Connect

    Campbell, Phillip Montgomery; Wix, Steven D.

    2013-05-01

    The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

  16. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

    1990-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  17. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, Robert B. (Los Alamos, NM); Bowman, Douglas R. (Eatontown, NJ)

    1989-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  18. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  19. Phase-controlled integrated photonic quantum circuits

    E-print Network

    Brian J. Smith; Dmytro Kundys; Nicholas Thomas-Peter; P. G. R. Smith; I. A. Walmsley

    2009-09-23

    Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externally-controlled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms.

  20. Advanced tools for integrated circuit design 

    E-print Network

    Dubagunta, Sai Kumar

    1992-01-01

    ADVANCED TOOLS FOR INTEGRATED CIRCUIT DESIGN A Thesis SAI KUMAR DUBAGUNTA Submitted to the OfFice of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE August 1992 Major... Subject: Computer Science TEXAS AkM UNIVERSITY LIB%4& Y ADVANCED TOOLS FOR INTEGRATED CIRCUIT DESIGN A Thesis by SAI KUMAR DUBAGUNTA Approved as to style and content by: Friesen, Donald K, (Co-Chai of mmittee) Sty nski, M. A (Co-Chair of Committee...

  1. Phase-controlled integrated photonic quantum circuits.

    PubMed

    Smith, Brian J; Kundys, Dmytro; Thomas-Peter, Nicholas; Smith, P G R; Walmsley, I A

    2009-08-01

    Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externallycontrolled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms. PMID:19654759

  2. Integrated Over-Temperature Protection Circuit for GaN Smart Power ICs

    NASA Astrophysics Data System (ADS)

    Kwan, Alex Man Ho; Guan, Yue; Liu, Xiaosen; Chen, Kevin J.

    2013-08-01

    As a thermal sensing and protection module on a GaN smart power IC platform, the first GaN over-temperature protection (OTP) circuit is demonstrated to deliver a desirable triggering signal at the critical temperature. The integrated OTP circuit is realized based on monolithic integration of enhancement-/depletion-mode high electron mobility transistors (HEMT) and HEMT-compatible lateral field effect rectifiers on a baseline AlGaN/GaN-on-Si wafer. The circuit effectively indicates the over-temperature up to 250 °C, and has a power supply rejection radio well above 35 dB. This sensing/protection circuit is expected to provide enhanced reliability to the high-voltage GaN power devices.

  3. Terminal modeling of hardened integrated circuits

    NASA Astrophysics Data System (ADS)

    Kleiner, C. T.; Haas, R.; Peacock, M.; Mandel, G.; Messenger, G. C.; Weakley, D.; Demartino, V.

    1981-12-01

    Kleiner et al. (1979) have reported modeling and test verification techniques used to develop medium-scale, dielectrically isolated integrated circuits (DIIC). The current investigation is concerned with the approaches employed in modeling the new circuits for applications studied by design and radiation hardening engineers. The described technique improves significantly the cost-effective application of computer programs such as SYSCAP II. The terminal model offers the designer of radiation-hardened electronic circuits a method for evaluating the effects of radiation transients on single or multiple piece-part response at the circuit board level. Although the models presented were intended for TREE design and analysis, it is possible to extend the technique to EMP and SGEMP evaluations.

  4. Microwave integrated circuit for Josephson voltage standards

    NASA Technical Reports Server (NTRS)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (inventors)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  5. Automatic test pattern generation for asynchronous circuits 

    E-print Network

    Vasudevan, Dilip Prasad

    2012-11-29

    The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the ...

  6. Integrated Circuit / Microfluidic Chips for Dielectric Manipulation

    E-print Network

    Heller, Eric

    Integrated Circuit / Microfluidic Chips for Dielectric Manipulation A THESIS PRESENTED BY THOMAS Manipulation Thomas Peter Hunt Advisor: Robert M. Westervelt This thesis describes the development the surrounding medium can be manipulated with DEP. #12;iv We initially fabricated an array of microscale post

  7. Integrated circuit test sensors using semiconducting nanotubes

    Microsoft Academic Search

    R. Glenn Wright; Larry V. Kirkland; M. Zgol; S. Keeton; D. Adebimbe

    2001-01-01

    This paper describes unique research efforts relating, to the development of semiconducting nanotubes for use within integrated circuits as an aid in determining IC functionality and operational status. This is accomplished by assessing both the electrical and chemical properties of the device through the use of unique carbon nanotube-based sensors specially designed for this purpose. Theoretical issues associated with the

  8. Integrated circuit failure detection using IR laser

    Microsoft Academic Search

    Ernest Keenan; Larry V. Kirkland; R. G. Wright; M. Zgol; D. Adebimpe

    2002-01-01

    This paper presents unique research efforts related to the use of infrared (IR) laser beams for detecting failures in integrated circuits. The transparency of the silicon substrate of ICs to radiation in the near infrared (NIR) spectrum permits a noninvasive method for imaging the component circuitry of the IC. A laser test fixture consisting of a 1064 nm continuous wave

  9. Large-Scale Photonic Integrated Circuits

    Microsoft Academic Search

    R. Nagarajan; M. Kato; J. Pleumeekers; P. Evans; S. Hurtt; A. Dentai; M. Missey; A. Chen; A. Mathur; D. Lambert; P. Chavarkar; J. Back; R. Muthiah; S. Murthy; R. Salvatore; C. Joyner; J. Rossi; R. Schneider; M. Ziari; F. Kish; D. Welch

    2007-01-01

    We review our work in the area of large scale InP photonic integrated circuits (PIC). We will review dense wavelength division multiplexed (DWDM) transmitter and receiver PICs with up to 40 channels, and operating at data rates up to 40 Gbit\\/s.

  10. Optoelectronic Integrated Circuits For Neural Networks

    NASA Technical Reports Server (NTRS)

    Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

    1990-01-01

    Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

  11. Harnessing optical forces in integrated photonic circuits

    Microsoft Academic Search

    Mo Li; W. H. P. Pernice; C. Xiong; T. Baehr-Jones; M. Hochberg; H. X. Tang

    2008-01-01

    The force exerted by photons is of fundamental importance in light-matter interactions. For example, in free space, optical tweezers have been widely used to manipulate atoms and microscale dielectric particles. This optical force is expected to be greatly enhanced in integrated photonic circuits in which light is highly concentrated at the nanoscale. Harnessing the optical force on a semiconductor chip

  12. A Smart Power Integrated Circuit Educational Tool

    Microsoft Academic Search

    Saulo Finco; Wellington Melo; Fernando Castaldo; José Pomilio; Beatriz Vieira Borges; Pedro Santos

    2007-01-01

    This paper describes a course in Smart Power based on the introduction of an innovative educational tool-a preprocessed Smart Power integrated circuit. The methodology used to introduce students to the issue of Smart Power design, resorting to low cost standard CMOS technology is presented. The theoretical support is envisaged to provide the required knowledge to specify characteristics and performance of

  13. Healing Voids In Interconnections In Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

    1989-01-01

    Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

  14. Annual report 2009 Integrated Devices & Circuits

    E-print Network

    Lagergren, Jens

    together Silicon Device Tehnology Silicon carbide (SiC) Devices and Circuits Phtononic Devices in III-projects (Semiconductor Research Corporation) · Collaborative projects in silicon carbide (SiC) with Acreo and TranSiC AB/V-materials based on quantum wells (VCSEL, detectors, sensors) Radio and Mixed Signal Integrated Systems Professors

  15. Development of 3D integrated circuits for HEP

    SciTech Connect

    Yarema, R.; /Fermilab

    2006-09-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

  16. SYSTEMATIC SYNTHESIS METHOD FOR ANALOGUE CIRCUITS PART III ALL-TRANSISTOR CIRCUIT SYNTHESIS

    E-print Network

    Papavassiliou, Christos

    and admittance matrix representations for all types of controlled sources and the impedance converter using laid down [1], including a new admittance matrix notation for the ideal nullor using unbounded elements the notation for admittance matrix description of nullor circuits in [1], the admittance matrix expansions

  17. A new pixel circuit for driving organic light-emitting diode with low temperature polycrystalline silicon thin-film transistors

    Microsoft Academic Search

    Ya-Hsiang Tai; Bo-Ting Chen; Yu-Ju Kuo; Chun-Chien Tsai; Ko-Yu Chiang; Ying-Jyun Wei; Huang-Chung Cheng

    2005-01-01

    A new pixel circuit design for active matrix organic light-emitting diode (AMOLED), based on the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. Threshold voltage compensation pixel circuit consisting of four n-type TFTs, one p-type TFT, one additional control signal, and one storage capacitor is used to enhance display image quality. The simulation results show

  18. Four-Thin-Film-Transistor Pixel Circuit for Amorphous-Silicon Active-Matrix Organic Light-Emitting Diode Displays

    Microsoft Academic Search

    Shinya Ono; Yoshinao Kobayashi

    2004-01-01

    Voltage-controlled pixel circuit with four thin-film-transistor (TFT) for amorphous-silicon (a-Si) active-matrix organic light-emitting diode (AM-OLED) displays has been designed, simulated and evaluated. Deviation and aging of the properties of the driver-TFT cause image sticking or degradation of image quality. These problems require compensation for high-quality display applications, and a pixel-level compensation circuit is one of the solutions. In this paper,

  19. Packaging concept for LSI beam lead integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1972-01-01

    Development of packaging system for mounting beam lead integrated chip circuit on lead frame is discussed. Process for fabricating large scale integration circuits is described. Diagrams illustrating method of construction are included.

  20. Stretchable and Foldable Silicon Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Kim, Dae-Hyeong; Ahn, Jong-Hyun; Choi, Won Mook; Kim, Hoon-Sik; Kim, Tae-Ho; Song, Jizhou; Huang, Yonggang Y.; Liu, Zhuangjian; Lu, Chun; Rogers, John A.

    2008-04-01

    We have developed a simple approach to high-performance, stretchable, and foldable integrated circuits. The systems integrate inorganic electronic materials, including aligned arrays of nanoribbons of single crystalline silicon, with ultrathin plastic and elastomeric substrates. The designs combine multilayer neutral mechanical plane layouts and “wavy” structural configurations in silicon complementary logic gates, ring oscillators, and differential amplifiers. We performed three-dimensional analytical and computational modeling of the mechanics and the electronic behaviors of these integrated circuits. Collectively, the results represent routes to devices, such as personal health monitors and other biomedical devices, that require extreme mechanical deformations during installation/use and electronic properties approaching those of conventional systems built on brittle semiconductor wafers.

  1. Selective remanent ambipolar charge transport in polymeric field-effect transistors for high-performance logic circuits fabricated in ambient.

    PubMed

    Fabiano, Simone; Usta, Hakan; Forchheimer, Robert; Crispin, Xavier; Facchetti, Antonio; Berggren, Magnus

    2014-11-26

    Ambipolar polymeric field-effect transistors can be programmed into a p- or n-type mode by using the remanent polarization of a ferroelectric gate insulator. Due to the remanent polarity, the device architecture is suited as a building block in complementary logic circuits and in CMOS-compatible memory cells for non-destructive read-out operations. PMID:25284119

  2. Microelectronic Devices and Circuits

    NSDL National Science Digital Library

    del Alamo, Jesus

    The topics of this course include: modeling of microelectronic devices, basic microelectronic circuit analysis and design, physical electronics of semiconductor junction and MOS devices, relation of electrical behavior to internal physical processes, development of circuit models, and understanding the uses and limitations of various models. The course uses incremental and large-signal techniques to analyze and design bipolar and field effect transistor circuits, with examples chosen from digital circuits, single-ended and differential linear amplifiers, and other integrated circuits.

  3. Wireless Integrated Circuit for 100-Channel Neural Stimulation

    E-print Network

    Harrison, Reid R.

    USA Abstract--We present the design of an integrated circuit for wireless neural stimulation, along and implement a low-power, implantable, wireless neural stimulator. Recent advances in circuit integration haveWireless Integrated Circuit for 100-Channel Neural Stimulation Brandon K. Thurgood, Noah M

  4. Laser-Controlled Rapid Prototyping of Photonic Integrated Circuits

    Microsoft Academic Search

    Louay A. Eldada

    1994-01-01

    Photonic integrated circuits offer important cost and environmental advantages over circuits composed of discrete components. However, the design and fabrication of complex, large-area photonic integrated circuits (PICs) is severely limited by the lack of prototyping tools as well as the appropriate device structures. This thesis describes the use of a novel laser fabrication process for the rapid prototyping of integrated

  5. DISTROY: Detecting Integrated Circuit Trojans with Compressive Measurements

    E-print Network

    Kung, H. T.

    DISTROY: Detecting Integrated Circuit Trojans with Compressive Measurements Youngjune L. Gwon, H. T in an integrated circuit (IC) is an important but hard problem. A Trojan is malicious hardware--it can be extremely. They outsource the manufacturing of their integrated circuit (IC) products to cheaper or more advanced

  6. 7.5 Gb\\/s monolithically integrated clock recovery circuit using PLL and 0.3-micron gate length quantum well HEMT's

    Microsoft Academic Search

    Zhi-Gong Wang; Manfred Berroth; Ulrich Nowotny; Peter Hofmann; Axel Huelsmann; Klaus Koehler; Brian Raynor; Joachim Schneider

    1994-01-01

    A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement\\/depletion AlGaAs\\/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 micron has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz

  7. 7.5 Gb\\/s monolithically integrated clock recovery circuit using PLL and 0.3-?m gate length quantum well HEMT's

    Microsoft Academic Search

    Zhi-Gong Wang; Manfred Berroth; Ulrich Nowotny; Peter Hofmann; A. Hulsmann; K. Kohler; B. Raynor; J. Schneider

    1994-01-01

    A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement\\/depletion AlGaAs\\/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 ?m has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz

  8. An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

    NASA Astrophysics Data System (ADS)

    Han, Sang-Kug; Choi, Hoon; Moon, Kyo-Ho; Choi, Young-Seok; Jeong, Kyung-Deuk; Park, Kwang-Mook; Choi, Sie-Young

    2012-04-01

    We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

  9. Robotic workcell for wire wrapping integrated circuits

    NASA Astrophysics Data System (ADS)

    Law, D. O.

    1992-05-01

    A robotic workcell was developed that electrically shorts the leads of integrated circuits by weaving a 0.005-in. copper wire around individual leads. This workcell has the capability to manipulate 13 different integrated circuit body styles including 14- to 64-lead flatpacks, 14- to 40-pin dual inline packages, and 3- to 10-pin cans. Features of the system include automatic program selection based on the particular body style provided, combined with automatic modification of the program to compensate for subtle differences between components supplied by various manufacturers of a given body style. Additionally, the workcell prepared and packages devices for storage by placing conductive foam on the leads of the device, inserting the device/foam into a plastic bag, and heat sealing the bag.

  10. Ultrafast characterization of an in-plane gate transistor integrated with photoconductive switches

    Microsoft Academic Search

    K. Ogawa; J. Allam; N. De B. Baynes; J. R. A. Cleaver; T. Mishima; I. Ohbu

    1995-01-01

    An in-plane gate field-effect transistor is characterized by ultrafast electro-optic sampling. The transistor is monolithically integrated with photoconductive switches in coplanar waveguide and <0.5 ps measurement time resolution is achieved. The gate-drain capacitance of the transistor is obtained as 1.8 fF at zero drain voltage from displacement current transients. The gate-drain capacitance is dominated by parasitic capacitance and the intrinsic

  11. An Analog Integrated-Circuit Vocal Tract

    Microsoft Academic Search

    Keng Hoong Wee; Lorenzo Turicchia; Rahul Sarpeshkar

    2008-01-01

    We present the first experimental integrated-circuit vocal tract by mapping fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The 275 muW analog vocal tract chip includes a 16-stage cascade of two-port pi-elements that forms a tunable transmission line, electronically variable impedances, and a current source as the

  12. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  13. Photonic circuits integrated with CMOS compatible photodetectors

    Microsoft Academic Search

    Dana Cristea; F. Craciunoiu; M. Modreanu; M. Caldararu; I. Cernica

    2001-01-01

    This paper presents the integration of photodetectors and photonic circuits (waveguides and interferometers, coupling elements and chemo-optical transducing layer) on one silicon chip. Different materials: silicon, doped or undoped silica, SiOxNy, polymers, and different technologies: LPCVD, APCVD, sol–gel, spinning, micromachining have been used to realize the photonic and micromechanical components and the transducers. Also, MOS compatible processes have been used

  14. Niobium-based integrated circuit technologies

    Microsoft Academic Search

    Yoshinobu Tarutani; Mikio Hirano; Ushio Kawabe

    1989-01-01

    Metallurgical and electrical properties of Nb and NbN films for use as Josephson junction electrodes and wiring layers are investigated. The crystallographic and superconducting properties necessary for Nb-based integrated circuit processes are clarified. Tunnel barrier structures of NbN-Nb oxide-NbN (Pb alloy) and Nb-Al oxide-Nb Josephson junctions have been analyzed and correlated with junction characteristics and critical current unformity. It was

  15. Understanding the Impact of Transistor-Level BTI Variability

    E-print Network

    Sapatnekar, Sachin

    in a circuit simulator [4] and demonstrated on an inverter circuit, predicting large delay variations (with. Keywords-Bias-Temperature Instability (BTI); Variability; Digital Circuit Delay; Degradation Analysis I scale integrated (VLSI) circuits. The BTI effect causes the threshold voltage, , of CMOS transistors

  16. Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

    SciTech Connect

    Kennedy, E.J. (Tennessee Univ., Knoxville, TN (USA) Oak Ridge National Lab., TN (USA)); Alley, G.T.; Britton, C.L. Jr. (Oak Ridge National Lab., TN (USA)); Skubic, P.L. (Oklahoma Univ., Norman, OK (USA)); Gray, B.; Wu, A. (Tennessee Univ., Knoxville, TN (USA))

    1990-01-01

    Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents {le}1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier.

  17. Power system with an integrated lubrication circuit

    DOEpatents

    Hoff, Brian D. (East Peoria, IL); Akasam, Sivaprasad (Peoria, IL); Algrain, Marcelo C. (Peoria, IL); Johnson, Kris W. (Washington, IL); Lane, William H. (Chillicothe, IL)

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  18. Silicon photonic devices for optoelectronic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tien, Ming-Chun

    Electronic and photonic integrated circuits use optics to overcome bottlenecks of microelectronics in bandwidth and power consumption. Silicon photonic devices such as optical modulators, filters, switches, and photodetectors have being developed for integration with electronics based on existing complementary metal-oxide-semiconductor (CMOS) circuits. An important building block of photonic devices is the optical microresonator. On-chip whispering-gallery-mode optical resonators such as microdisks, microtoroids, and microrings have very small footprint, and thus are suitable for large scale integration. Micro-electro-mechanical system (MEMS) technology enables dynamic control and tuning of optical functions. In this dissertation, microring resonators with tunable power coupling ratio using MEMS electrostatic actuators are demonstrated. The fabrication is compatible with CMOS. By changing the physical gap spacing between the waveguide coupler and the microring, the quality factor of the microring can be tuned from 16,300 to 88,400. Moreover, we have demonstrated optical switches and tunable optical add-drop filters with an optical bandwidth of 10 GHz and an extinction ratio of 20 dB. Potentially, electronic control circuits can also be integrated. To realize photonic integrated circuits on silicon, electrically-pumped silicon lasers are desirable. However, because of the indirect bandgap, silicon is a poor material for light emission compared with direct-bandgap III-V compound semiconductors. Heterogeneous integration of III-V semiconductor lasers on silicon is an alternative to provide on-chip light sources. Using a room-temperature, post-CMOS optofluidic assembly technique, we have experimentally demonstrated an InGaAsP microdisk laser integrated with silicon waveguides. Pre-fabricated InGaAsP microdisk lasers were fluidically assembled and aligned to the silicon waveguides on silicon-on-insulator (SOI) with lithographic alignment accuracy. The assembled microdisk lasers exhibited a threshold pump of 0.6 mW and a maximum output power of 90 muW at room temperature under pulsed condition. The light was evanescently coupled to the waveguides on SOI for on-chip optical routing.

  19. Highly sensitive tactile sensors integrated with organic transistors

    NASA Astrophysics Data System (ADS)

    Kim, Jiseok; Nga Ng, Tse; Soo Kim, Woo

    2012-09-01

    This paper presents a highly sensitive capacitive pressure sensor composed of a polymer dielectric film with a nano-needle structure. The nano-needle polymer films were prepared by facile fabrication methods including breath figures formation followed by stamping. The pressure sensitivity of the sensor reached 1.76 kPa-1 in the low pressure range (<1 kPa), which is comparable to the sensitivity of human skin. Analysis of the geometries and densities effect was shown, and the nano-needle film showed better sensitivity in comparison to films with hemispherical or conical structures. The pressure sensors were integrated with printed organic thin film transistors to enable flexible, large-area tactile sensing applications.

  20. Fully integrated nonlinear modeling and characterization system of microwave transistors with on-wafer pulsed measurements

    Microsoft Academic Search

    J. P. Teyssier; J. P. Viaud; J. J. Raoux; R. Quere

    1995-01-01

    A novel approach for nonlinear characterization and modeling of microwave transistors has been developed. The whole process is organized as a set of methods contained in the transistor database. This implies that characterization and modeling are performed in an integrated manner. I(V) and S-parameters are measured on wafer under pulsed conditions, suitable for MESFETs, HEMTs or HBTs as illustrated by

  1. Coaxial inverted geometry transistor having buried emitter

    NASA Technical Reports Server (NTRS)

    Hruby, R. J.; Cress, S. B.; Dunn, W. R. (inventors)

    1973-01-01

    The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

  2. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  3. Shielding and Securing Integrated Circuits with Sensors Davood Shahrjerdi

    E-print Network

    into the Integrated Circuit (IC) supply chain of Design Manufacturing Test- ing Integration Packaging Distribution [1]. SHIELD is envisioned to be the hardware root-of-trust which when packaged into any IC equips@rice.edu, rkarri@nyu.edu Abstract--An integrated circuit (IC) Supply Chain Hardware Integrity for Electronics

  4. Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

    NASA Astrophysics Data System (ADS)

    Es-Sakhi, Azzedin D.

    Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

  5. SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs

    SciTech Connect

    Huque, Mohammad A [ORNL; Tolbert, Leon M [ORNL; Blalock, Benjamin [University of Tennessee, Knoxville (UTK); Islam, Syed K [University of Tennessee, Knoxville (UTK)

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  6. A wafer-scale 3-D circuit integration technology

    Microsoft Academic Search

    James A. Burns; Brian F. Aull; Chenson K. Chen; Chang-Lee Chen; Craig L. Keast; Jeffrey M. Knecht; V. Suntharalingam; K. Warner; P. W. Wyatt; D.-R. W. Yost

    2006-01-01

    The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

  7. Integrated testing and algorithms for visual inspection of integrated circuits.

    PubMed

    Pau, L F

    1983-06-01

    This paper deals with the integrated pre-cap testing of integrated circuits (IC's), defined as a simultaneous combination of electrical testing and of visual inspection using image analysis techniques. The emphasis is on image analysis models and algorithms for integrated testing of small and large defects. Two algorithms are presented for the analysis of visible and infrared imagery during electrical testing. Algorithm 1 matches bridges or subgraphs derived from the topological layout. Algorithm 2 computes a figure of merit for the IC from a fuzzy language description. PMID:21869146

  8. 3D packaging for integrated circuit systems

    SciTech Connect

    Chu, D.; Palmer, D.W. [eds.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  9. Automatic Parametric Testing Of Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Jennings, Glenn A.; Pina, Cesar A.

    1989-01-01

    Computer program for parametric testing saves time and effort in research and development of integrated circuits. Software system automatically assembles various types of test structures and lays them out on silicon chip, generates sequency of test instructions, and interprets test data. Employs self-programming software; needs minimum of human intervention. Adapted to needs of different laboratories and readily accommodates new test structures. Program codes designed to be adaptable to most computers and test equipment now in use. Written in high-level languages to enhance transportability.

  10. Analysis of millimeter and microwave integrated circuits

    SciTech Connect

    Compton, R.C.

    1987-01-01

    The design and measurement of millimeter and microwave integrated circuits encompasses a diverse spectrum of interesting disciplines. A number of contrasting approaches used for theoretically and experimentally characterizing circuits in this frequency range are presented. Rigorous methods for calculating antenna patterns and impedances of the planar bow-tie antenna used in millimeter-wave receiver systems were developed. A 94-GHz antenna measurement system and microwave-scale models were constructed to confirm these theoretical predictions. Pattern measurements were also made on a linear array of bow-tie antennas, a long-strip antenna, and a log-periodic antenna. In modified form, these techniques were applied to the investigation of planar-array structures. An equivalent-circuit model for an array of squares joined at the corners by discrete devices was formulated. This model was verified with impedance and pattern measurements. Finally, a set of analysis tools that have been assembled into an interactive computer-aided design program, called Puff, is discussed. Puff has been used in microwave laboratory classes at the California Institute of Technology, Cornell University and the University of California, Los Angeles.

  11. Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration

    E-print Network

    Sredojevi?, Ranko Radovin.

    2008-01-01

    Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring ...

  12. Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits

    NASA Astrophysics Data System (ADS)

    Sutton, Akil K.

    Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

  13. Coulomb blockade memory using integrated single-electron transistor\\/metal-oxide-semiconductor transistor gain cells

    Microsoft Academic Search

    Zahid Ali Khan Durrani; A. C. Lnine; Haroon Ahmed

    2000-01-01

    A 3×3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 ?m×1 ?m or 1 ?m×70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write\\/read

  14. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    DOEpatents

    Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  15. Microcontact-printed self-assembled monolayers as ultrathin gate dielectrics in organic thin-film transistors and complementary circuits.

    PubMed

    Zschieschang, Ute; Halik, Marcus; Klauk, Hagen

    2008-03-01

    We have developed a manufacturing process for organic thin-film transistors and organic complementary circuits in which a microcontact-printed phosphonic acid self-assembled monolayer is employed first as an etch resist to pattern aluminum gate electrodes by wet etching and then as the gate dielectric of the same device. To our knowledge, this is the first report of a printing process for electronic devices that combines the concepts of direct and indirect printing in the same printing step and for the same material by employing a transferred pattern both as an etch resist (indirect printing) and as a functional material as part of the final device (direct printing). Owing to the small thickness and the high quality of the monolayer gate dielectric, the transistors and circuits operate at a low voltage of 3 V. PMID:18198917

  16. GaAs-based heterojunction bipolar transistors for very high performance electronic circuits

    Microsoft Academic Search

    PETER M. ASBECK; FRANK MAU-CHUNG CHANG; KEH-CHUNG WANG; GERARD J. SULLIVAN; DEREK T. CHEUNG

    1993-01-01

    This paper reviews the principles and status of AlGaAs\\/GaAs heterojunction bipolar transistor technology. Comparisons of this technology with Si bipolar transistor and GaAs field-effect transistor technologies are made. Epitaxial materials, fabrication processes, transistor DC and RF characteristics, and modeling of AlGaAs\\/GaAs HBT's are described. Key areas of HBT application are also highlighted

  17. High mobility flexible graphene field-effect transistors and ambipolar radio-frequency circuits

    NASA Astrophysics Data System (ADS)

    Liang, Yiran; Liang, Xuelei; Zhang, Zhiyong; Li, Wei; Huo, Xiaoye; Peng, Lianmao

    2015-06-01

    Field-effect transistors (GFETs) were fabricated on mechanically flexible substrates using chemical vapor deposition grown graphene. High current density (nearly 200 ?A ?m-1) with saturation, almost perfect ambipolar electron-hole behavior, high transconductance (120 ?S ?m-1) and good stability over 381 days were obtained. The average carrier mobility for holes (electrons) is 13 540 cm2 V-1 s-1 (12 300 cm2 V-1 s-1) with the highest value over 24 000 cm2 V-1 s-1 (20 000 cm2 V-1 s-1) obtained in flexible GFETs. Ambipolar radio-frequency circuits, frequency doubler, were constructed based on the high performed flexible GFET, which show record high output power spectra purity (~97%) and high conversion gain of -13.6 dB. Bending measurements show the flexible GFETs are able to work under modest strain. These results show that flexible GFETs are a very promising option for future flexible radio-frequency electronics.Field-effect transistors (GFETs) were fabricated on mechanically flexible substrates using chemical vapor deposition grown graphene. High current density (nearly 200 ?A ?m-1) with saturation, almost perfect ambipolar electron-hole behavior, high transconductance (120 ?S ?m-1) and good stability over 381 days were obtained. The average carrier mobility for holes (electrons) is 13 540 cm2 V-1 s-1 (12 300 cm2 V-1 s-1) with the highest value over 24 000 cm2 V-1 s-1 (20 000 cm2 V-1 s-1) obtained in flexible GFETs. Ambipolar radio-frequency circuits, frequency doubler, were constructed based on the high performed flexible GFET, which show record high output power spectra purity (~97%) and high conversion gain of -13.6 dB. Bending measurements show the flexible GFETs are able to work under modest strain. These results show that flexible GFETs are a very promising option for future flexible radio-frequency electronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr02292d

  18. Design for manufacturability with regular fabrics in digital integrated circuits

    E-print Network

    Gazor, Mehdi (Seyed Mehdi)

    2005-01-01

    Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the ...

  19. Heterojunction bipolar transistor technology for data acquisition and communication

    NASA Technical Reports Server (NTRS)

    Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

    1992-01-01

    Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

  20. Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess

    E-print Network

    Larrabee, Tracy

    Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda shown that the vast majority of all local defects in MOS technologies cause changes in the circuit. We use the Carafe fault extractor to extract realistic bridge faults in CMOS circuits [10

  1. The design of a regulated variable power supply for transistor circuits 

    E-print Network

    Graham, Oscar David

    1959-01-01

    Instruments 2N251 p-n-p germanium power transistor was used for the series regulator with a Tl 2N291 p-n-p germanium tran- sistor used in compound-connection with it. It would. be desirable to use a transistor with a higher breakdown voltage instead... assumed that its magnitude was quite low. The transistor used for the d-c amplifier was a Motorola 2N652 p-n-p germanium transistor. The main criterisn for selecting this par- ticular transistor was its breakdown voltage, The breakdown voltage wss...

  2. Basic Study on the Radio Frequency Characteristics of the Transmission Lines Employing Periodically Perforated Ground Metal on GaAs Monolithic Microwave Integrated Circuit and Their Equivalent Ciruits

    NASA Astrophysics Data System (ADS)

    Yun, Young; Ju, Jeong-Gab; Kim, Hong Seung

    2011-01-01

    In this work, basic characteristics of transmission line employing periodically perforated ground metal (PPGM) were investigated using theoretical and experimental analysis. Concretely, bandwidth and impedance were investigated using theoretical analysis, and wavelength and effective permittivity were extracted from experimental results. In addition, insertion loss and isolation characteristics were investigated using equivalent circuit analysis. For simplification of design process, equivalent circuits for the PPGM cell were extracted, and all circuit parameters were expressed by closed-form equation. Above results indicate that the transmission line employing PPGM is a promising candidate for a development of matching and passive elements on monolithic microwave integrated circuit (MMIC) including wireless communication circuit and compound semiconducting devices such as high electron mobility transistor (HEMT), diamond field effect transistor (FET) and light emitting diode (LED).

  3. High mobility flexible graphene field-effect transistors and ambipolar radio-frequency circuits.

    PubMed

    Liang, Yiran; Liang, Xuelei; Zhang, Zhiyong; Li, Wei; Huo, Xiaoye; Peng, Lianmao

    2015-07-01

    Field-effect transistors (GFETs) were fabricated on mechanically flexible substrates using chemical vapor deposition grown graphene. High current density (nearly 200 ?A ?m(-1)) with saturation, almost perfect ambipolar electron-hole behavior, high transconductance (120 ?S ?m(-1)) and good stability over 381 days were obtained. The average carrier mobility for holes (electrons) is 13?540 cm(2) V(-1) s(-1) (12?300 cm(2) V(-1) s(-1)) with the highest value over 24?000 cm(2) V(-1) s(-1) (20?000 cm(2) V(-1) s(-1)) obtained in flexible GFETs. Ambipolar radio-frequency circuits, frequency doubler, were constructed based on the high performed flexible GFET, which show record high output power spectra purity (?97%) and high conversion gain of -13.6 dB. Bending measurements show the flexible GFETs are able to work under modest strain. These results show that flexible GFETs are a very promising option for future flexible radio-frequency electronics. PMID:26061485

  4. Dewlopment of bB/i-Si/hSb and 6B/i-Si/hSb/i-Si/&B Resonant Interband Tunnel Diodes For Integrated Circuit Applications

    E-print Network

    Rommel, Sean

    Dewlopment of bB/i-Si/hSb and 6B/i-Si/hSb/i-Si/&B Resonant Interband Tunnel Diodes For Integrated developments in Si based tunnel diode technologies have made the realization of circuits incorporating both t,unnel resonant tunneling diodes (DBRTDs) [3] have been demonstrated with fewer transistors and lower power

  5. Circuit design for embedded memory in low-power integrated circuits

    E-print Network

    Qazi, Masood

    2012-01-01

    This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the ...

  6. Hinged Polysilicon Structures with Integrated CMOS Thin Film Transistors

    NASA Astrophysics Data System (ADS)

    Pister, Kristofer Stefan Josef

    Micro electromechanical systems (MEMS) have the potential to have a profound impact on both scientific research and commercial products. MEMS have proven to be a commercial success, finding application in such diverse environments as hospital operating rooms and automobile engines. One of the open research problems in MEMS is the fabrication of three dimensional structures using what is essentially a planar process. Several methods exist for making large vertical steps in silicon, but they offer only specific geometries and have limited resolution. The process described here is based on polysilicon surface micromachining, with the addition that micro hinges are built along with other structures. In this approach, polycrystalline silicon structural elements are fabricated in the plane of the wafer, and then rotated out of the plane of the wafer using hinged joints. Individual elements are then assembled together to form more complicated three dimensional structures with high detail in all dimensions. The assembly process has been automated to some degree by the inclusion of spring loaded locks which snap into place once a hinge has reached a critical angle. With these hinged structures and spring locks, thousands of structures can be rotated and locked into place simultaneously in the final step of fabrication. Several examples of hinged three dimensional structures are presented, including a hot wire anemometer, a frog-embryo dynamometer, and a parallel jaw gripper, all of which fit inside a 1 millimeter cube. In addition to the structural elements provided in the process, several electronic elements have been integrated as well. These elements include CMOS thin film transistors integrated directly in the polysilicon structural thin film, piezoresistive strain sensors for measuring force and deflection, and flexible micro ribbon cable which allows electrical wiring to be run between the substrate and the rotated structures.

  7. Radiation effects on power integrated circuits

    SciTech Connect

    Darwish, M.N.; Dolly, M.C.; Goodwin, C.A.; Titus, J.L

    1988-12-01

    A study was initiated to investigate the effects of gamma (total ionizing dose), prompt gamma (gamma dot), and neutron radiation on commercially available power integrated circuits (PIC's). A Dielectric Isolated (DI) Bipolar-CMOS-DMOS (BCDMOS) technology developed at AT and T Bell Laboratories was selected for this characterization. Total ionizing dose testing resulted in device failure at 30 krads (Si). Gamma dot testing (30 ns pulsewidth) resulted in device failure due to transient upset of the CMOS logic at 1.0 E+09 rads(Si)/s. Neutron testing resulted in severe degradation in performance, but devices remained functional after receiving a fluence of 2.0 E+14 n/cm/sup 2/. Also, an attempt was made to harden the BCDMOS technology to gamma radiation. Devices from eight processing splits were characterized to determine if specific process changes would improve their performance.

  8. Post irradiation effects (PIE) in integrated circuits

    NASA Technical Reports Server (NTRS)

    Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

    1991-01-01

    Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

  9. Assembly and packaging technology for integrated circuits

    NASA Astrophysics Data System (ADS)

    Rose, A. S.

    1982-08-01

    The electrical interconnections of semiconductor integrated circuit devices are manufactured by bonding fine-diameter wires to peripherally located thin film pads of aluminum, which make ohmic contact with the functional structures of the semiconductor. The aluminum or gold bonded wires are attached to their bond pads by ultrasonic, thermocompression or thermosonic techniques, and their outer ends are similarly bonded to a metal lead frame or to metallized substrates which achieve the circuitry's expansion from micro to macro dimensions. The metallurgical considerations affecting bond quality and reliability are related to the potential formation of intermetallic compounds and grain boundary deterioration in the wires and interfaces. The packaging used after the assembly operations described is primarily conducted in plastic or ceramic formats.

  10. Integrated optical interconnections on printed circuit boards

    NASA Astrophysics Data System (ADS)

    Riester, Markus; Langer, Gregor; Leising, Günther

    2007-02-01

    The development of integrated optical interconnections (IOIs) represents a quantum leap for the functionality of printed circuit boards (PCBs). This new technology will allow highly complex product features and hence, higher product added value. PCBs with optical interconnections will be used where applications call either for very high data streams between components, modules or functional units (e.g. backplanes or multiprocessor boards) or for a space-saving design for interconnection paths (e.g. mobile applications). We discuss the different approaches towards integrating optical waveguides into PCBs and analyze the prerequisites for a transfer to a product. Application scenarios for different markets are presented and steps proposed for required action to deliver solutions that can be driven into a market. In a second section a new and innovative concept for the integration of an optical interconnection system in PCBs is presented. This revolutionary concept is highly supporting the worldwide trend towards miniaturization of not only electronic but also optoelectronic systems in PCBs. The alignment of the optoelectronic components to the waveguides has been addressed by this concept. It is shown that the process will allow the tolerances incurred in the manufacturing processes to be dealt with in a separate process step, allowing existing standard methods for the production of electronic interconnection systems to be used.

  11. Investigation of using the organic thin film transistors in the pixel circuit of the active matrix organic light emitting diode flat panel display

    Microsoft Academic Search

    Mohamed M. Montasser; Darek Korzec

    2008-01-01

    Organic technology is having some limitations like threshold voltage variation and mobility degradation of the organic thin film transistors and the organic light emitting diode luminance degradation. In this paper, a voltage programming pixel circuit for active-matrix OLED display is investigated. The circuit is compensating for the OTFT threshold voltage variation and mobility degradation. Compensation for the OLED luminance degradation

  12. Monolithic vertical integration of metal-oxide-semiconductor transistor with subterranean photonics in silicon

    Microsoft Academic Search

    Tejaswi Indukuri; Prakash Koonath; Bahram Jalali

    2006-01-01

    Monolithic integration of photonics and electronics has been achieved in silicon by vertically integrating metal-oxide-semiconductor field-effect transistors and waveguide-coupled microdisk resonators in a double-layer silicon-on-insulator wafer, thus paving the way towards dense three-dimensional optoelectronic integration

  13. High-performance Organic Thin-film Transistor 

    E-print Network

    Jung, Yunbum

    2014-03-19

    application in integrated circuits (ICs) that are essential for high-tech electronics. In order to be competitive in market, the performance improvement of organic thin film transistors (OTFTs) has become an indispensable prerequisite. Although the low...

  14. Dual threshold voltage organic thin-film transistor technology

    E-print Network

    Nausieda, Ivan A.

    A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The nearroom-temperature (<; 95 °C) process produces ...

  15. An ultra low noise readout integrated circuit for uncooled microbolometers

    Microsoft Academic Search

    Jian Lv; YaDong Jiang; DongLu Zhang; Yun Zhou

    2010-01-01

    A low noise readout architecture for uncooled microbolometer focal plane arrays is described. The on-chip readout circuit\\u000a contains an integration circuit in which the bolometer current is directed injected into a capacitor, and exhibits extremely\\u000a low noise with no decrease in signal by using an ultra low noise capacitive transimpedance amplifier (CTIA). The simple configuration\\u000a of the integration circuit makes

  16. A TDC integrated circuit for drift chamber readout

    Microsoft Academic Search

    M. Passaseo; E. Petrolo; S. Veneziano

    1995-01-01

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start\\/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 ?m CMOS technology, with 1 ns LSB realized using a

  17. Photonic Integrated Circuits with SOAs in WDM Optical Networks

    Microsoft Academic Search

    Steve Grubb; Radha Nagarajan; Masaki Kato; Fred Kish; Dave Welch

    2008-01-01

    Photonic integrated circuits (PICs) have had a significant impact on WDM transmission systems and are scalable, reliable, economic, and have performance comparable to discrete optoelectronic components. Integration of SOAs to the PIC platform extend the performance and benefits of PICs.

  18. Low power integrated circuits for wireless neural recording applications

    Microsoft Academic Search

    Xu Zhang; Weihua Pei; Qiang Gui; Hongda Chen

    2008-01-01

    A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit,

  19. OYSTER: A Study of Integrated Circuits as Three Dimensional Structures

    Microsoft Academic Search

    George M. Koppelman; Michael A. Wesley

    1983-01-01

    This paper presents a design for a software system (OYSTER) for the parametric simulation and analysis of the fabrication steps of very large scale integrated circuit devices. The system is based on a solid geometric modeling approach in which the component parts of an integrated circuit are represented at any step as three-dimensional solid objects in a geometric data base.

  20. Characterization and Modeling of TSV Based 3-D Integrated Circuits

    E-print Network

    community are discussed, and guidelines are provided for designing these evolving through silicon via (TSV. Finally, generation and spreading of heat in 3-D integrated circuits are discussed as part design, and DC and high frequency electrical measurements for TSV based 3-D integrated circuits. Ioannis

  1. Computer aided engineering of semi-conductor integrated circuits

    Microsoft Academic Search

    D. P. Kennedy

    1977-01-01

    The objectives of this program are to remove the empiricism associated with the design and manufacturing of custom integrated circuits for military applications and to reduce the cost of these circuits by devising improved computer-aided engineering techniques. Efforts of research covered by this report are Part I, Semiconductor Device Modeling conducted by the University of Florida and, Part II, Integrated

  2. Substrate Integrated Artificial Dielectric (SIAD) Structure for Miniaturized Microstrip Circuits

    Microsoft Academic Search

    Martin Coulombe; Hoang V. Nguyen; Christophe Caloz

    2007-01-01

    A substrate integrated artificial dielectric (SIAD) structure for planar microstrip circuits miniaturization is presented. This structure is paraelectric and paramagnetic, i.e., provides enhancement of both the permittivity and the permeability from a given host substrate, and therefore achieves guided wavelength compression, leading to circuit size miniaturization. The SIAD is fully integrated and may be engineered by repeatable laser drilling and

  3. Equivalency-processing parallel photonic integrated circuit EP3

    E-print Network

    Louri, Ahmed

    Equivalency-processing parallel photonic integrated circuit EP3 IC : equivalence search module present an optoelectronic module called the equivalency-processing parallel photonic integrated circuit EP.e., database word searches . The module combines a parallel-computation model with multiwavelength photonic

  4. Product specification File under Integrated Circuits, IC06

    E-print Network

    Berns, Hans-Gerd

    /HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HCDATA SHEET Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT04 Hex inverter For a complete data sheet, please also download: · The IC06 74HC

  5. Product specification File under Integrated Circuits, IC06

    E-print Network

    Berns, Hans-Gerd

    /HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HCDATA SHEET Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HCU04 Hex inverter For a complete data sheet, please also download: · The IC06 74HC

  6. Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits.

    PubMed

    Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C-K; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

    2014-04-01

    Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at V(DD) = 80 V (70% of 1/2V(DD)) and a gain of 85. Additionally, robust SWNT complementary metal-oxide-semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

  7. Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

    PubMed Central

    Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

    2014-01-01

    Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal?oxide?semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

  8. E-Learning System for Design and Construction of Amplifier Using Transistors

    ERIC Educational Resources Information Center

    Takemura, Atsushi

    2014-01-01

    This paper proposes a novel e-Learning system for the comprehensive understanding of electronic circuits with transistors. The proposed e-Learning system allows users to learn a wide range of topics, encompassing circuit theories, design, construction, and measurement. Given the fact that the amplifiers with transistors are an integral part of…

  9. An MOS transistor model for RF IC design valid in all regions of operation

    Microsoft Academic Search

    Christian Enz

    2002-01-01

    This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic

  10. The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

    Microsoft Academic Search

    Ahmet Bindal; Adithya Naresh; Pearl Yuan; Kim K. Nguyen; Sotoudeh Hamedi-Hagh

    2007-01-01

    This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective

  11. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit

    PubMed Central

    Nakazato, Kazuo

    2014-01-01

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10?MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  12. Fast Comparisons of Circuit Implementations Shrirang K. Karandikar and Sachin S. Sapatnekar, Fellow, IEEE

    E-print Network

    Sapatnekar, Sachin

    -- Estimation, Very-large-scale integration, CMOS digital integrated circuits, Digital integrated circuits I1 Fast Comparisons of Circuit Implementations Shrirang K. Karandikar and Sachin S. Sapatnekar, such as transistor sizing can signifi- cantly improve circuit performance, by optimizing critical paths to meet

  13. Automated Visual Integrated Circuit Mounting Operations Inspections

    NASA Astrophysics Data System (ADS)

    Chapron, Michel

    1987-05-01

    The paper deals with visual inspections which take place on integrated-circuit assembly lines after the following operations : die-bonding, wire bonding, lid sealing, package marking. Ceramic package inspection is also described. An X-ray camera enables us to inspect eutectic die bondings or epoxy die bondings. Different defect types are detected by using mainly 2 methods : the former is based on classical processings, the latter is based on unusual projections. Photographs, obtained by an ultra-sonic microscope, show the power of this new means of die-bonding inspection. The microscope permits sufficient magnification in order to inspect the wire-bonding. The method presented is primarily based on mathematical morphology. The inspection of lid sealing consists of two inspections : lid centering inspection and joint inspection. The method proposed for solving the first inspection is based on mathematical morphology, projections, Hough transform, and is available for different types and sizes of packages. It is also invariant in translation and rotation. The second inspection is mainly based on mathematical morphology. Two methods are proposed for solving package marking inspection : the first one is based on mathematical morphology, the other one on a Bayesian method. The final inspection, ceramic package integrity inspection, which is made with a horizontal lighting, is based on classical processings and mathematical morphology.

  14. Reduced 30% scanning time 3D multiplexer integrated circuit applied to large array format 20KHZ frequency inkjet print heads

    E-print Network

    Liou, J -C

    2008-01-01

    Enhancement of the number and array density of nozzles within an inkjet head chip is one of the keys to raise the printing speed and printing resolutions. However, traditional 2D architecture of driving circuits can not meet the requirement for high scanning speed and low data accessing points when nozzle numbers greater than 1000. This paper proposes a novel architecture of high-selection-speed three-dimensional data registration for inkjet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array inkjet printheads with nozzles numbering more than 1000. This IC (Integrated Circuit) architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection (S), address (A), and power supply (P), are employed toge...

  15. Nanophotonic integrated circuits from nanoresonators grown on silicon

    NASA Astrophysics Data System (ADS)

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D.; Li, Kun; Chang-Hasnain, Connie

    2014-07-01

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore’s law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  16. Nanophotonic integrated circuits from nanoresonators grown on silicon.

    PubMed

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

    2014-01-01

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits. PMID:24999601

  17. An analog integrated-circuit vocal tract.

    PubMed

    Keng Hoong Wee; Turicchia, L; Sarpeshkar, R

    2008-12-01

    We present the first experimental integrated-circuit vocal tract by mapping fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The 275 muW analog vocal tract chip includes a 16-stage cascade of two-port pi-elements that forms a tunable transmission line, electronically variable impedances, and a current source as the glottal source. A nonlinear resistor models laminar and turbulent flow in the vocal tract. The measured SNR at the output of the analog vocal tract is 64, 66, and 63 dB for the first three formant resonances of a vocal tract with uniform cross-sectional area. The analog vocal tract can be used with auditory processors in a feedback speech locked loop-analogous to a phase locked loop-to implement speech recognition that is potentially robust in noise. Our use of a physiological model of the human vocal tract enables the analog vocal tract chip to synthesize speech signals of interest, using articulatory parameters that are intrinsically compact and linearly interpolatable. PMID:23853134

  18. Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

    NASA Astrophysics Data System (ADS)

    Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

    2014-12-01

    The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

  19. Picosecond Optoelectronics In High-Speed Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Jain, R. K.; Stenersen, K.; Snyder, D. E.

    1983-11-01

    The direct addressing of ultrafast integrated circuits by picosecond optical pulses has numerous applications in electronics and data processing. These include new and unambiguous ways of characterizing the speeds of Gigahertz logic circuits, contact-free diagnosis of problems or failures in complex circuits, and the presentation of novel possibilities for data input and interconnections in future high-speed data processors and super-computers.

  20. Two-photon laser-assisted device alteration in silicon integrated-circuits.

    PubMed

    Serrels, Keith A; Erington, Kent; Bodoh, Dan; Farrell, Carl; Leslie, Neel; Lundquist, Theodore R; Vedagarbha, Praveen; Reid, Derryck T

    2013-12-01

    Optoelectronic imaging of integrated-circuits has revolutionized device design debug, failure analysis and electrical fault isolation; however modern probing techniques like laser-assisted device alteration (LADA) have failed to keep pace with the semiconductor industry's aggressive device scaling, meaning that previously satisfactory techniques no longer exhibit a sufficient ability to localize electrical faults, instead casting suspicion upon dozens of potential root-cause transistors. Here, we introduce a new high-resolution probing technique, two-photon laser-assisted device alteration (2pLADA), which exploits two-photon absorption (TPA) to provide precise three-dimensional localization of the photo-carriers injected by the TPA process, enabling us to implicate individual transistors separated by 100 nm. Furthermore, we illustrate the technique's capability to reveal speed-limiting transistor switching evolution with an unprecedented timing resolution approaching <10 ps. Together, the exceptional spatial and temporal resolutions demonstrated here now make it possible to extend optical fault localization to sub-14 nm technology nodes. PMID:24514459

  1. A survey of optimization techniques for integrated-circuit design

    NASA Astrophysics Data System (ADS)

    Brayton, R. K.; Hachtel, G. D.; Sangiovanni-Vincentelli, A. L.

    1981-10-01

    Contemporary optimization techniques are surveyed and related to optimization problems which arise in the design of integrated circuits. Theory, algorithms, and programs are reviewed, and an assessment is made of the impact optimization has had and will have on integrated-circuit design. Integrated circuits are characterized by complex tradeoffs between multiple nonlinear objectives with multiple nonlinear and sometimes nonconvex constraints. Function and gradient evaluations require the solution of very large sets of nonlinear differential equations; consequently they are inaccurate and extremely expensive. Futhermore, the parameters to be optimized are subject to inherent statistical fluctuations. Particular emphasis is given to those multiobjective constrained optimization techniques which are appropriate to this environment.

  2. A statistical MOSFET modeling method for CMOS integrated circuit simulation 

    E-print Network

    Chen, Jian

    1992-01-01

    riw = cir. /(sisr), or X:, ", (z. , ? 22)(x, s ? rs) r1k- (n ? 1)s, ss (2 4) It is clear from equations (2. 3) and (2. 4) that crt = cir, r po = r, s and res = 1. The correlation coefficient approaches 1. 0 (or -1. 0) when a, strong positive (or... PARAMETER VARIATIONS IN CMOS CIR- CIJITS A. IC Simulation and Statistical Model . B. Basic Characterizations of Multivariate Populations C, Parameter Standardization and Scaling D. Transistor Parameter Variations in CMOS Circuits 3 4 6 8 8 8 11...

  3. Electrothermal Analysis and Optimization Techniques for Nanoscale Integrated Circuits

    E-print Network

    Sapatnekar, Sachin

    , Brent Goplen, and Sachin S. Sapatnekar Department of Electrical and Computer Engineering University in the design of electrical circuits. This paper overviews several methods for the analysis and optimization Æ Fig. 1. Schematic of a VLSI chip with packaging (a) integrated circuit and the packaging structure

  4. Autoclave testing of plastic encapsulated 4001 CMOS integrated circuits

    Microsoft Academic Search

    R. Holecinski

    1980-01-01

    Samples from 10 vendors of CMOS 4001 plastic encapsulated integrated circuits were tested in an autoclave at 121 C, 100% RH and 15 psig with and without electrical bias. Twenty-nine test groups of 16 circuits each accumulated over 200,000 device hours. Failure analyses were performed to verify moisture related electrochemical aluminum metal corrosion on the die. Weibull failure distributions showed

  5. A Low Noise Readout Circuit for Integrated Electrochemical Biosensor Arrays

    E-print Network

    Mason, Andrew

    A Low Noise Readout Circuit for Integrated Electrochemical Biosensor Arrays Jichun Zhang, Nicholas electrochemical interface circuit that is tuned to the needs of protein-based biosensor arrays and compatible biosensor output currents from 10pA to 10 A to suit a wide range of sensitivities and electrode areas

  6. Integrated MQW optical amplifier\\/noise-filter\\/photodetector photonic circuit

    Microsoft Academic Search

    R. C. Alferness; L. L. Buhl; U. Koren; T. L. Koch; I. Kim; B. I. Miller; M. A. Newkirk; M. G. Young; R. P. Gnall; F. Hernandez-Gil; H. M. Presby; G. Raybon; C. A. Burrus

    1993-01-01

    A monolithically integrated photonic circuit with an InGaAs\\/InGaAsP multiple-quantum-well (MQW) traveling-wave optical amplifier, a Bragg reflection grating-folded noise filter, and an MQW photodetector has been demonstrated. This photonic circuit offers potential as a preamplified lightwave receiver in high-data-rate applications because of its compactness and potentially low cost

  7. AMGIE-A synthesis environment for CMOS analog integrated circuits

    Microsoft Academic Search

    Geert Van Der Plas; Geert Debyser; Francky Leyn; Koen Lampaert; Jan Vandenbussche; Georges G. E. Gielen; Willy M. C. Sansen; Petar Veselinovic; Domine Leenaerts

    2001-01-01

    A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent.

  8. An organic thin-film transistor circuit for large-area temperature-sensing

    E-print Network

    He, David Da

    2008-01-01

    This thesis explores the application of organic thin-film transistors (OTFTs) for temperature-sensing. The goal of this work is twofold: the understanding of the OTFT's electrical characteristics' temperature dependence, ...

  9. Superconducting single photon detectors integrated with diamond nanophotonic circuits

    E-print Network

    Patrik Rath; Oliver Kahl; Simone Ferrari; Fabian Sproll; Georgia Lewes-Malandrakis; Dietmar Brink; Konstantin Ilin; Michael Siegel; Christoph Nebel; Wolfram Pernice

    2015-05-16

    Photonic quantum technologies promise to repeat the success of integrated nanophotonic circuits in non-classical applications. Using linear optical elements, quantum optical computations can be performed with integrated optical circuits and thus allow for overcoming existing limitations in terms of scalability. Besides passive optical devices for realizing photonic quantum gates, active elements such as single photon sources and single photon detectors are essential ingredients for future optical quantum circuits. Material systems which allow for the monolithic integration of all components are particularly attractive, including III-V semiconductors, silicon and also diamond. Here we demonstrate nanophotonic integrated circuits made from high quality polycrystalline diamond thin films in combination with on-chip single photon detectors. Using superconducting nanowires coupled evanescently to travelling waves we achieve high detection efficiencies up to 66 % combined with low dark count rates and timing resolution of 190 ps. Our devices are fully scalable and hold promise for functional diamond photonic quantum devices.

  10. Superconducting single photon detectors integrated with diamond nanophotonic circuits

    E-print Network

    Rath, Patrik; Ferrari, Simone; Sproll, Fabian; Lewes-Malandrakis, Georgia; Brink, Dietmar; Ilin, Konstantin; Siegel, Michael; Nebel, Christoph; Pernice, Wolfram

    2015-01-01

    Photonic quantum technologies promise to repeat the success of integrated nanophotonic circuits in non-classical applications. Using linear optical elements, quantum optical computations can be performed with integrated optical circuits and thus allow for overcoming existing limitations in terms of scalability. Besides passive optical devices for realizing photonic quantum gates, active elements such as single photon sources and single photon detectors are essential ingredients for future optical quantum circuits. Material systems which allow for the monolithic integration of all components are particularly attractive, including III-V semiconductors, silicon and also diamond. Here we demonstrate nanophotonic integrated circuits made from high quality polycrystalline diamond thin films in combination with on-chip single photon detectors. Using superconducting nanowires coupled evanescently to travelling waves we achieve high detection efficiencies up to 66 % combined with low dark count rates and timing resolu...

  11. Design automation and analysis of three-dimensional integrated circuits

    E-print Network

    Das, Shamik, 1977-

    2004-01-01

    This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical ...

  12. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  13. IMPROVED FUNCTIONALITY AND PERFORMANCE IN PHOTONIC INTEGRATED CIRCUITS

    E-print Network

    Coldren, Larry A.

    IMPROVED FUNCTIONALITY AND PERFORMANCE IN PHOTONIC INTEGRATED CIRCUITS Larry A. Coldren, JamesP-based photonic ICs, improvements in their functionality, performance, and reliability are evolving. High reliability and reduced power dissipation. Increased reliability results from the elimination of possible

  14. Advanced modeling of planarization processes for integrated circuit fabrication

    E-print Network

    Fan, Wei, Ph. D. Massachusetts Institute of Technology

    2012-01-01

    Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing ...

  15. Integrated prepulse circuits for efficient excitation of gas lasers

    NASA Technical Reports Server (NTRS)

    Rothe, Dietmar E. (Inventor)

    1990-01-01

    Efficient impedance-matched gas laser excitation circuits integrally employ prepulse power generators. Magnetic switches are employed to both generate the prepulse and switch the prepulse onto the laser electrodes.

  16. Switching Transistor

    NASA Technical Reports Server (NTRS)

    1981-01-01

    Westinghouse Electric Corporation's D60T transistors are used primarily as switching devices for controlling high power in electrical circuits. It enables reduction in the number and size of circuit components and promotes more efficient use of energy. Wide range of application from a popcorn popper to a radio frequency generator for solar cell production.

  17. Fast, automated thermal simulation of three-dimensional integrated circuits

    Microsoft Academic Search

    Patrick Wilkerson; Ashok Raman; Marek Turowski

    2004-01-01

    Three-dimensional (3D) stacked integrated circuits (ICs) can significantly improve circuit performance and offer the promise of integrating various technologies (memory, logic, RF, mixed-signal, optoelectronics) within a single block. Lack of 3D design tools and heat dissipation from vertically stacked multiple layers are the crucial problems in their development. To address these issues, CFD Research Corporation (CFDRC) is developing methodologies and

  18. Protection of Sensitive Security Parameters in Integrated Circuits

    Microsoft Academic Search

    Dejan E. Lazich; Micaela Wuensche

    2008-01-01

    To protect sensitive security parameters in the non-volatile memory of integrated circuits, a device is designed that generates\\u000a a special secret key (called IC-Eigenkey) to symmetrically encrypt this data. The IC-Eigenkey is generated by the integrated\\u000a circuit itself and therefore unknown to anybody else. The desired properties of such an IC-Eigenkey are postulated and a theoretical\\u000a limit on the distribution

  19. Laser rapid prototyping of photonic integrated circuits

    Microsoft Academic Search

    Louay Eldada; Miguel Levy; Robert Scarmozzino; Richard M. Osgood

    1994-01-01

    In this paper, we will describe our work at Columbia in developing a laser prototyping system, in conjunction with computer simulation, to design, fabricate, and test novel waveguide circuits. The system is also useful for manufacturing small-run circuit designs. The fundamental technique uses a laser-induced photoelectrochemical process for etching GaAs and other III-V compounds. The technique is maskless and discretionary.

  20. V-band low-noise integrated circuit receiver

    NASA Astrophysics Data System (ADS)

    Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

    1983-02-01

    A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

  1. Spatial gradients and multidimensional dynamics in a neural integrator circuit

    PubMed Central

    Miri, Andrew; Daie, Kayvon; Arrenberg, Aristides B.; Baier, Herwig; Aksay, Emre; Tank, David W.

    2011-01-01

    In a neural integrator, the variability and topographical organization of neuronal firing rate persistence can provide information about the circuit’s functional architecture. Here we use optical recording to measure the time constant of decay of persistent firing (“persistence time”) across a population of neurons comprising the larval zebrafish oculomotor velocity-to-position neural integrator. We find extensive persistence time variation (10-fold; coefficients of variation 0.58–1.20) across cells within individual larvae. We also find that the similarity in firing between two neurons decreased as the distance between them increased and that a gradient in persistence time was mapped along the rostrocaudal and dorsoventral axes. This topography is consistent with the emergence of persistence time heterogeneity from a circuit architecture in which nearby neurons are more strongly interconnected than distant ones. Collectively, our results can be accounted for by integrator circuit models characterized by multiple dimensions of slow firing rate dynamics. PMID:21857656

  2. A graphene quantum dot with a single electron transistor as an integrated charge sensor

    Microsoft Academic Search

    Lin-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Hong-Wen Jiang; Guo-Ping Guo

    2010-01-01

    A quantum dot (QD) with an integrated charge sensor is becoming a common architecture for a spin or charge based solid state qubit. To implement such a structure in graphene, we have fabricated a twin-dot structure in which the larger dot serves as a single electron transistor (SET) to read out the charge state of the nearby gate controlled small

  3. Integrated digital inverters based on two-dimensional anisotropic ReS2 field-effect transistors

    PubMed Central

    Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching-Hwa; Huang, Ying-Sheng; Cao, Zhengyi; Wang, Laiguo; Li, Aidong; Zeng, Junwen; Song, Fengqi; Wang, Xinran; Shi, Yi; Yuan, Hongtao; Hwang, Harold Y.; Cui, Yi; Miao, Feng; Xing, Dingyu

    2015-01-01

    Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS2) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS2 field-effect transistors, which exhibit competitive performance with large current on/off ratios (?107) and low subthreshold swings (100?mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconducting materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS2 anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications. PMID:25947630

  4. Current-source aSi:H thin-film transistor circuit for active-matrix organic light-emitting displays

    Microsoft Academic Search

    Yi He; Reiji Hattori; Jerzy Kanicki

    2000-01-01

    In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as ?3 V, the output current variations can be less than 1

  5. Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

    SciTech Connect

    Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M., E-mail: muhammadmustafa.hussain@kaust.edu.sa [Integrated Nanotechnology Lab, Electrical Engineering, Computer Electrical Mathematical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia)

    2013-11-25

    We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

  6. Three-dimensional integration of metal-oxide-semiconductor transistor with subterranean photonics in silicon

    Microsoft Academic Search

    Tejaswi Indukuri; Prakash Koonath; Bahram Jalali

    2006-01-01

    Monolithic integration of photonics and electronics has been achieved in silicon by three-dimensionally integrating metal-oxide-semiconductor field-effect transistors and waveguide-coupled microdisk resonators. Implantation of oxygen ions into a silicon-on-insulator substrate with a patterned thermal oxide mask followed by a high temperature anneal was utilized to realize the buried photonic structures. This results in the formation of vertically stacked silicon layers separated

  7. Preliminary specification File under Integrated Circuits, IC11

    E-print Network

    Ida, Nathan

    DATA SHEET Preliminary specification File under Integrated Circuits, IC11 1997 Jul 09 INTEGRATED chip TDA5147CH QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT Supply voltage VCC5 analog5 VCC5 disable disable brake DRIVER DRIVER from PORN block VCCS12 disable disable b

  8. Integrating Through-Wafer Interconnects With Active Devices and Circuits

    Microsoft Academic Search

    Jim Jozwiak; Richard G. Southwick; III; Vaughn N. Johnson; William B. Knowlton; Amy J. Moll

    2008-01-01

    Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside

  9. Product specification File under Integrated Circuits, IC06

    E-print Network

    Martin, Tom

    Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines #12;December 1990 2 PhilipsDATA SHEET Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED download: · The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic

  10. Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

    2006-09-01

    A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

  11. Carbon Nanotubes, Semiconductor Nanowires and Graphene for Thin Film Transistor and Circuit Applications

    Microsoft Academic Search

    Didier Pribat

    2011-01-01

    In this paper, we briefly review the use of carbon nanotubes and semiconductor nanowires, which represent a new class of nanomaterials actively studied for thin film transistors and electronics applications. Although these nanomaterials are usually synthesised at moderate to high temperatures, they can be transferred to any kind of substrate after growth, paving the way for the fabrication of flexible

  12. 6.301 Solid State Circuits Recitation 3: AC Coupling, and Single-Transistor Amplifiers

    E-print Network

    Goldwasser, Shafi

    -amps: As a warm-up, the familiar Common Emitter Stage: RI vi R0 avvi RI RIvi vi R0 R0 avvi avvi "Interstage from the emitter: RIN = r + rb +1 Summary of common base stage: High gain, low input impedance, high-Transistor Amplifiers Prof. Joel L. Dawson Page 7 Emitter Follower Sta

  13. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

    Microsoft Academic Search

    Zhanping Chen; Mark Johnson; Liqiong Wei; Kaushik Roy

    1998-01-01

    Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The

  14. Simulation of proton-induced energy deposition in integrated circuits

    NASA Technical Reports Server (NTRS)

    Fernald, Kenneth W.; Kerns, Sherra E.

    1988-01-01

    A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

  15. Computer models of hearing aid transducers for integrated circuit design.

    PubMed

    Agnew, J

    1992-03-01

    Electronic circuit modeling using computer-based simulation tools is well established and device models are available for common electronic components. However, acoustic models of audio transducers for use during integrated circuit design are not readily available. This causes difficulty for designers of audio amplifiers, and increases the uncertainties of a successful silicon integration of a circuit design. This paper reports on a technique for the creation of electroacoustic models of hearing aid microphones and receivers that can be connected to an amplifier under design, and incorporated into PSPICE simulations. Verification of the technique and models was performed by comparing measured frequency response data with graphs created by PSPICE modeling. The conclusions were that the method developed for creating these models, and the models themselves, were accurate enough to be used for acoustic simulations of frequency response performance during amplifier design, and gave results comparable to data obtained from breadboard measurements of the same circuits. PMID:1564209

  16. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    PubMed

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits. PMID:19086836

  17. Thermal analysis and verification of a mounted monolithic integrated circuit

    Microsoft Academic Search

    T. Robert Harris; Samson Melamed; Sonali Luniya; W. R. Davis; Michael B. Steer; Lawrence E. Doxsee; Kurt Obermiller; Chad Hawkinson

    2010-01-01

    As circuit density increases and high-power applications are facilitated, thermal considerations become paramount a design concern. In this paper, a high power monolithic microwave integrated circuit (MMIC) is modeled by the fREEDA multi-physics simulator and measured for validation. While validation is the crux of any simulation model, it is known that thermal measurements accurate to a high resolution are problematic.

  18. Feasibility of BCB as an interlevel dielectric in integrated circuits

    Microsoft Academic Search

    S. Bothra; M. Kellam; P. Garrou

    1994-01-01

    This paper investigates the feasibility of using an organic polymer based on benzocyclobutene as an interlevel dielectric\\u000a material in very large scale integrated (VLSI) circuits. The material is a thermoset resin with attractive electrical and\\u000a mechanical properties for application as an interlevel dielectric in VLSI circuits. It has a low relative dielectric constant\\u000a of 2.7. The single coating planarization achieved

  19. A statistical MOSFET modeling method for CMOS integrated circuit simulation

    E-print Network

    Chen, Jian

    1992-01-01

    A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

  20. Large-Scale Photonic Integrated Circuit Transmitters with Monolithically Integrated Semiconductor Optical Amplifiers

    Microsoft Academic Search

    Sanjeev Murthy; Masaki Kato; Radhakrishnan Nagarajan; Mark Missey; Vince Dominic; V. Lai; Brian Taylor; Jacco Pleumeekers; Jianping Zhang; Peter Evans; Mehrdad Ziari; Ranjani Muthiah; Randal Salvatore; Huan-Shang Tsai; Alan Nilson; Don Pavinski; P. Studenkov; S. Agashe; A. Dentai; D. Lambert; J. Bostak; J. Stewart; C. Joyner; J. Rossi; R. Schneider; M. Reffle; F. Kish; D. Welch

    2008-01-01

    We have successfully demonstrated large-scale photonic integrated circuit (LS-PIC) transmitters with monolithically integrated semiconductor optical amplifiers. Data is presented for for 10 channel devices operating at 10 and 40 Gb\\/sec.

  1. Integrated reactive components in power electronic circuits

    Microsoft Academic Search

    M. Ehsani; O. H. Stielau; J. D. van Wyk; I. J. Pitel

    1993-01-01

    Methods of integrating capacitive and inductive components into new compact devices are presented. Configurations for integrating various combinations of L-C networks are shown. A example of the construction of an integrated L-C for a series-resonant converter is evaluated both practically and experimentally

  2. ON PLACEMENT AND SIZING OF SLEEP TRANSISTORS IN LEAKAGE CRITICAL CIRCUITS

    Microsoft Academic Search

    Vishal Khandelwal; Ankur Srivastava

    Leakage power is increasingly gaining importance with tech nology scaling. Multi-Threshold CMOS (MTCMOS) technology has bec ome a popular technique for standby power reduction. Sleep tran sistor in- sertion in circuits is an effective application of MTCMOS te chnology for reducing leakage power. In this paper we present a fine gra ined approach where each gate in the circuit is

  3. A PWM transistor inverter for an ac electric vehicle drive

    NASA Technical Reports Server (NTRS)

    Slicker, J. M.

    1981-01-01

    A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

  4. A PWM transistor inverter for an ac electric vehicle drive

    NASA Astrophysics Data System (ADS)

    Slicker, J. M.

    1981-10-01

    A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

  5. The functional test of complex integrated circuits

    NASA Astrophysics Data System (ADS)

    Bellon, C.

    1984-06-01

    A multilevel automatic generation of test sequences is proposed. The procedure starts by considering the set of functional parameters and the fine structure of the electronic modules composing the circuit. The method may be considered related to automatic software testing or automata identification methods. A functional microprocessor test procedure is described. The method takes into account the synchronous input signals and allows the automatic generation of test programs. A specific high level computer language was developed for that purpose and is described. The 68000 microprocessor was described in that language and its test programs generated. The elements implementing the system are detailed.

  6. Enhanced heterostructure field effect transistor CAD model suitable for simulation of mixed mode circuits

    Microsoft Academic Search

    Trond Ytterdal; Tor A. Fjeldly; Michael S. Shur; Steven M. Baier; R. Lucero

    1999-01-01

    We describe a new enhanced model for deep submicron heterostructure field effect transistors (HFET's) suitable for implementation in computer aided design (CAD) software packages such as SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of both n- and p-channel deep submicron HFET's over the temperature range 250-450 K. The current-voltage (I-V) characteristics are described by a single, continuous,

  7. Pentacene organic thin-film transistors for circuit and display applications

    Microsoft Academic Search

    Hagen Klauk; David J. Gundlach; Jonathan A. Nichols; Thomas N. Jackson

    1999-01-01

    We have fabricated organic thin-film transistors (TFT's) using the small-molecule polycyclic aromatic hydrocarbon pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam deposited silicon dioxide as the gate dielectric, ion-beam deposited palladium for the source and drain contacts, and vacuum-evaporated pentacene to form the active layer. Excellent electrical characteristics were obtained, including carrier mobility as

  8. Application of AlGaAs\\/GaAs ballistic collection transistors to multiplexer and preamplifier circuits

    Microsoft Academic Search

    Y. Matsuoka; S. Yamahata; H. Ichino; E. Sano; T. Ishibashi

    1991-01-01

    Ballistic collection transistors with a 'launcher' (L-BCTs) are applied to the fabrication of high-speed\\/broadband ICs. The L-BCTs, in which base widening is suppressed and the ballistic transport of electrons is utilized to reduce transit time without an increase in base collector capacitance, are combined with a novel self-alignment process technology that makes it possible to enlarge the cutoff frequency f

  9. 3D circuit integration for Vertex and other detectors

    SciTech Connect

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  10. Integration of resonant-tunneling transistors and hot-electron transistors

    Microsoft Academic Search

    Theodore S. Moise; Yung-Chung Kao; Alan C. Seabaugh; Albert H. Taddiken

    1994-01-01

    We have integrated a tunneling hot-electron transfer amplifier (THETA) and a novel resonant-tunneling hot-electron transfer amplifier (RTHETA) within a single epitaxial growth. At room temperature, the THETA exhibits a common-emitter current gain of greater than six and a voltage swing of 800 mV when measured in an inverter configuration. The RTHETA exhibits similar common-emitter current gain and a four-state voltage

  11. InP-based photonic integrated circuits

    Microsoft Academic Search

    L. A. Coldren

    2008-01-01

    The monolithic integration of a number of photonic components on a single InP chip for increased functionality and reliability as well as decreased power dissipation and cost is becoming an accepted goal for most component vendors. This tutorial will review current integration approaches and results, emphasizing our UCSB work.

  12. Smart Power: New power integrated circuit technologies and their applications

    NASA Astrophysics Data System (ADS)

    Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

    1992-05-01

    Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

  13. Single Event Transients in Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed to transients. In some cases, such events produced resets by falsely triggering circuits designed to protect against over- voltage or over-current. On at least three occasions, transients caused satellites to switch into "safe mode" in which most of the systems on board the satellites were powered down for an extended period. By the time the satellites were reconfigured and returned to full operational state, much scientific data had been lost. Fortunately, no permanent damage occurred in any of the systems and they were all successfully re-activated.

  14. Photonic integrated circuits for phase modulation formats

    Microsoft Academic Search

    S. Corzine; P. Evans; M. Kato; M. Fisher; M. Raburn; A. Dentai; I. Lyubomirsky; A. Nilsson; J. Rahn; R. Nagarajan; B. Behnia; J. Bostak; J. Stewart; D. Christini; M. Missey; V. Lal; H. Dinh; A. Chen; J. Thomson; W. Williams; P. Chavarkar; S. Nguyen; D. Lambert; S. Agashe; A. Spannagel; J. Rossi; P. Liu; J. Webjorn; T. Butrie; M. Reffle; R. Schneider; M. Ziari; C. Joyner; F. Kish; D. Welch

    2008-01-01

    We will review the latest performance metrics for components enabling communication networks based on phase modulation formats. For spectral efficiency, reduced complexity, reliability, and power consumption; monolithic integration on InP is clearly the superior path.

  15. Organic nanofibers integrated by transfer technique in field-effect transistor devices

    Microsoft Academic Search

    Luciana Tavares; Jakob Kjelstrup-Hansen; Kasper Thilsing-Hansen; Horst-Günter Rubahn

    2011-01-01

    The electrical properties of self-assembled organic crystalline nanofibers are studied by integrating these on field-effect\\u000a transistor platforms using both top and bottom contact configurations. In the staggered geometries, where the nanofibers are\\u000a sandwiched between the gate and the source-drain electrodes, a better electrical conduction is observed when compared to the\\u000a coplanar geometry where the nanofibers are placed over the gate

  16. Direct integration of metal oxide nanowire in vertical field-effect transistor

    Microsoft Academic Search

    Pho Nguyen; Hou T. Ng; Toshishige Yamada; Michael K. Smith; Jun Li; Jie Han; M. Meyyappan

    2004-01-01

    We demonstrate seamless direct integration of a semiconductor nanowire grown using a bottom-up approach to obtain a vertical field-effect transistor (VFET). We first synthesize single crystalline semiconductor indium oxide (In2O3) nanowires projecting vertically and uniformly on a nonconducting optical sapphire substrate. Direct electrical contact to the nanowires is uniquely provided by a self-assembled underlying In2O3 buffer layer formed in-situ during

  17. Analytic Circuit Model of Ballistic Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor for Transient Analysis

    NASA Astrophysics Data System (ADS)

    Numata, Tatsuhiro; Uno, Shigeyasu; Kamakura, Yoshinari; Mori, Nobuya; Nakazato, Kazuo

    2013-04-01

    A fully analytic and explicit model of device properties in the ballistic transport in gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed, which enables circuit simulations. The electrostatic potential distribution in the wire cross section is approximated by a parabolic function. Using the applied potential, the energy levels of electrons are analytically obtained in terms of a single unknown parameter by perturbation theory. Ballistic current is obtained in terms of an unknown parameter using the analytic expression of the electron energy level and the current equation for ballistic transport. We analytically derive the parameter with a one-of-a-kind approximate methodology. With the obtained parameter, the fully analytic and explicit model of device properties such as energy levels, ballistic current, and effective capacitance is derived with satisfactory accuracy compared with the numerical simulation results. Finally, we perform a transient simulation using a circuit simulator, introducing our model to it as a Verilog-A script.

  18. Analog Integrated Circuits Design for Processing Physiological Signals

    Microsoft Academic Search

    Yan Li; Carmen C. Y. Poon; Yuan-Ting Zhang

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this

  19. Radio-frequency integrated circuits for portable communications

    Microsoft Academic Search

    Asad A. Abidi

    1994-01-01

    A new market has emerged in the form of portable wireless communications devices, operating in the 900 MHz to 2 GHz range, where miniaturization and low-energy operation is sought through the aggressive large-scale integration typical of silicon ICs, yet the circuit design style at times resembles MMICs. Early indications suggest that silicon will be the technology of choice in this

  20. CMOS RF integrated circuits at 5 GHz and beyond

    Microsoft Academic Search

    THOMAS H. LEE; S. SIMON WONG

    2000-01-01

    A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RFIC) technology in unprecedented ways. These pressures are stimulating novel solutions that allow RFICs to enjoy more of the benefits of

  1. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  2. HMIC the ultimate SOI microwave integrated circuit technology

    Microsoft Academic Search

    Timothy Boles

    2011-01-01

    HMIC is a microwave and mmW integrated circuit topology that can create three dimensional structures based upon a inimitable marriage of silicon and glass at a waferscale level which enable high performance, low loss, lower cost realizations of many of the classic hybrid MMIC's. In addition, the unique nature of the bonding together of these two dissimilar materials into common

  3. NEWS FOR ECE ILLINOIS ALUMNI AND FRIENDS Integrated Circuit

    E-print Network

    Liu, Gang "Logan"

    NEWS FOR ECE ILLINOIS ALUMNI AND FRIENDS FALL 2008 Integrated Circuit turns50 Also in this issue: Illinois home to new Microsoft- and Intel-funded parallel computing center Copper nanowires grown by new process create long-lasting displays Control, Thy Passion: The story of an eminent Illinois lab Department

  4. Electronic-photonic integrated circuits on the CMOS platform

    Microsoft Academic Search

    L. C. Kimerling; D. Ahn; A. B. Apsel; M. Beals; D. Carothers; Y.-K. Chen; T. Conway; D. M. Gill; M. Grove; C.-Y. Hong; M. Lipson; J. Liu; J. Michel; D. Pan; S. S. Patel; A. T. Pomerene; M. Rasras; D. K. Sparacin; K.-Y. Tu; A. E. White; C. W. Wong

    2006-01-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and

  5. EM Effects on Semiconductor Devices, Gates and Integrated Circuit

    E-print Network

    Anlage, Steven

    EM Effects on Semiconductor Devices, Gates and Integrated Circuit Interconnects Dept. of Electrical Xi Shao, Parvez N. Guzdar Akin Akturk, Zeynep Dilli, Bo Yang, Todd Firestone #12;EM Effects Verify with experiments: Chips fabricated through MOSIS #12;Outline EM Coupling: Levels Investigated Task

  6. EM Effects on Semiconductor Devices Gates and Integrated Circuit

    E-print Network

    Anlage, Steven

    EM Effects on Semiconductor Devices Gates and Integrated Circuit Interconnects Dept. of Electrical Xi Shao, Parvez N. Guzdar4 Akin Akturk, Zeynep Dilli, Yun Bai, Todd Firestone #12;EM Effects. Verify with experiments: Chips fabricated through MOSIS #12;Outline EM Coupling: Levels Investigated Task

  7. An integrated circuit/packet switched videoconferencing system

    SciTech Connect

    Kippenhan, H.A. Jr.; Lidinsky, W.P.; Roediger, G.A. [Fermi National Accelerator Lab., Batavia, IL (United States); Watts, T.A. [Rutgers Univ., Piscataway, NJ (United States). Busch Campus

    1995-11-01

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible videoconferencing system for use by high energy physics collaborations and others wishing to use videoconferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of videoconferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEP`s needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Videoconferencing Using PAckets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched videoconferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet videoconferencing interface. Augmentation is centered in another subsystem called MSB (Multiport multisession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system.

  8. EMI Modeling of Integrated Circuits using pattern simulation

    E-print Network

    Paris-Sud XI, Université de

    EMI Modeling of Integrated Circuits using pattern simulation COURAU Lionel, GERBERT-GAILLARD Brice finishing, a new noise simulation has been developped in order to be fast and accurate. Then some comparisons have been made with standard spice simulations showing the efficiency of this flow. 1

  9. Alcohol Modified RTV Silicone Encapsulation for Integrated Circuit Device Packaging

    Microsoft Academic Search

    Ching-Ping Wong; DENI M. ROSE

    1983-01-01

    Room temperature vulcanized (RTV) silicone elastomer has been proven to be one of the most effective encapsulants for mechanical, moisture, electrical, and alpha particle protection of bipolar, metal--oxide semiconductor (MOS), and hybrid integrated circuit (IC) devices. This RTV material is also one of the few commercial polymer materials that meets Bell System encapsulant specifications. The chemistry of the silicone elastomer

  10. Reliability of plastic-encapsulated integrated circuits in moisture environments

    Microsoft Academic Search

    L. Gallace; M. Rosenfield

    1984-01-01

    Some of the factors affecting the reliability of plastic-encapsulated integrated circuits (ICs) in moist environments are discussed. Particular attention is given to the moisture related failure mechanism EMA (electrolytic metal attack). Three types of EMA were identified in a series of experiments: galvanic cell corrosion; concentration cell corrosion; and ionic cell corrosion. In addition to EMA, the interaction of moisture

  11. Reliability Evaluation of Hermetic Integrated Circuit Chips in Plastic Packages

    Microsoft Academic Search

    H. Khajezadeh; A. S. Rose

    1975-01-01

    Previous studies of the basic failure mechanisms of conventional plastic-encapsulated integrated circuits have led to improvements in materials and processes which have yielded two orders of magnitude improvement in reliability. Additionally, it has been demonstrated that, where severe environmental conditions are encountered, enhanced reliability is provided by device surfaces passivated with a silicon nitride dielectric and metallized with a titanium,

  12. Gas Cooling Enhancement Technology for Integrated Circuit Chips

    Microsoft Academic Search

    TOHRU KISHIMOTO; ETSURO SASAKI; KUNIO MORIYA

    1984-01-01

    New approaches are described for increasing the capability of forced gas convection cooling for integrated circuit chips, using an enhanced heat transfer technique and a higher gas flow velocity in a closed-cycle flow. A turbulence promoting fin with low pressure loss has been developed and enhancement of the heat transfer coefficient using gas flow velocities up to 50 m\\/s is

  13. Accelerated reliability evaluation for high density packaging integrated circuits

    Microsoft Academic Search

    Bin Yao; Ping Lai

    2011-01-01

    The demand for miniaturization, increased functionality, better performance and lower cost has forced the electronics industry to shift from traditional packaging techniques to advanced high density packaging technologies. As the packaging density increases, the packaging reliability becomes more essential. In this paper, an accelerated reliability test method to evaluate the packaging reliability of high density packaging integrated circuits (ICs) is

  14. An Integrated Automated Layout Generation System for DSP Circuits

    Microsoft Academic Search

    Jan M. Rabaey; Stephen P. Pope; Robert W. Brodersen

    1985-01-01

    An integrated CAD system for the automated design of digital signal-processing (DSP) circuits for audio and telecommunication applications is described. The system uses as unique input a symbolic description of algorithm. This representation is translated into an actual layout using a two-step process. First, the symbolic input is mapped into the target architecture, which consists basically of a set of

  15. Novel technique for reliability testing of silicon integrated circuits

    Microsoft Academic Search

    Phuong LeMinh; H. Wallinga; P. H. Woerlee; Albert van den Berg; J. Holleman

    2001-01-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer2 in sizes. Both

  16. Laser applications in integrated circuits and photonics packaging

    Microsoft Academic Search

    Yong Feng Lu; L. P. Li; K. Mendu; J. Shi

    2004-01-01

    Laser processing has large potential in the packaging of integrated circuits (IC). It can be used in many applications such as laser cleaning of IC mold tools, laser deflash to remove mold flash from heat sinks and lead wires of IC packages, laser singulation of BGA (ball grid array) and CSP (chip scale packages), laser reflow of solder ball on

  17. Cooling of Integrated Circuits Using Droplet-Based Microfluidics

    E-print Network

    Chakrabarty, Krishnendu

    and microfluidics-based solutions were proposed in the past. We present a cooling method based on highCooling of Integrated Circuits Using Droplet-Based Microfluidics Vamsee K. Pamula Duke University General Terms Measurement, Design, Experimentation. Keywords Microfluidics, Droplet, Electrowetting, Hot

  18. DNA chips --Integrated Chemical Circuits for DNADiagnosis and DNA computers

    E-print Network

    Hagiya, Masami

    DNA chips -- Integrated Chemical Circuits for DNADiagnosis and DNA computers Akira Suyama, Associate Professor Institute of Physics, Graduate School of Arts and Sciences, The University of Tokyo DNA chips are si l i con­ or glass­based smal l surfaces on which many DNA ol i gonuc l eotides are i

  19. Automated failure population creation for validating integrated circuit diagnosis methods

    Microsoft Academic Search

    Wing Chiu Tam; Osei Poku

    2009-01-01

    Integrated circuit (IC) diagnosis typically analyzes failed chips by reasoning about their responses to test patterns to deduce what has gone wrong. Current trends use diagnosis as the first step in extracting valuable information from a large population of failing ICs that include, for example, design-feature failure rates and defect-occurrence statistics. However, it is difficult to examine the accuracy of

  20. Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits

    E-print Network

    Rubloff, Gary W.

    Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits Aris Christou Materials of the failure rate of each component due to interaction effects of the failed components. The Monte Carlo failure rates become nonconstant. The Monte Carlo technique is an appropriate methodology used to treat

  1. ESD protection and biomedical integrated circuit co-design techniques

    Microsoft Academic Search

    Jian Liu; Xin Wang; Hui Zhao; Qiang Fang; Zitao Shi; Li Wang; Chen Zhang; Albert Wang; Yuhua Cheng; Bin Zhao; Gary Zhang

    2011-01-01

    This paper reviews new design techniques for electrostatic discharge (ESD) and biomedical integrated circuit (IC) co-designs (ESD-Biomed co-design) for whole-chip design optimization. Challenges for ESD protection design for biomedical electronics are discussed. Promising ESD protection structures for biomedical ICs are described. Example of ESD-protected ultrasound medical imaging system is presented.

  2. Radiation Response of High Speed CMOS Integrated Circuits

    Microsoft Academic Search

    H. Yue; D. Davison; R. F. Jennings; P. Lothongkam; D. Rinerson; D. Wyland

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis.

  3. A Microcomputer-Controlled Testing System for Digital Integrated Circuits

    Microsoft Academic Search

    Gary L. West; Victor P. Nelson

    1980-01-01

    This paper describes a low-cost digital integrated circuit (IC) tester designed and implemented using the Intel 8080 microcomputer family. Test patterns are applied to each IC to be tested from a lookup table stored in memory, along with appropriate clock signals if needed. The resulting chip outputs are then examined for errors resulting from stuck-at conditions or other functional errors.

  4. Performance of digital integrated circuit technologies at very high temperatures

    SciTech Connect

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  5. Chemical vapor deposition for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1980-01-01

    Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

  6. Novel technology for hybrid integration of photonic and electronic circuits

    Microsoft Academic Search

    Shinji Matsuo; Tatsushi Nakahara; Kouta Tateno; Takaslii Kurokawa

    1996-01-01

    We have developed a new three-dimensional integration technology which involves hybrid integration of photonic and electronic circuits by means of polyimide bonding. To demonstrate this technology, we fabricated a GaAs metal-semiconductor-metal photodetector on a silicon substrate. Each photodetector on a polyimide layer is electrically connected to the electrode on the silicon substrate. The electrical interconnection between the photodetector and electrode

  7. Photonic integrated circuits: research curiosity or packaging common sense?

    Microsoft Academic Search

    Thomas L. Koch; Uziel Koren

    1990-01-01

    The potential of photonic integrated circuits (PICs) for meeting the requirements of high-connectivity optical communication architectures (where there is a variety of cascaded, interconnected optical devices at each station) at a reasonable cost is discussed. PICs refer to the monolithic (single-substrate) integration of optically interconnected guided-wave devices. PIC technology replaces the separate, sequential alignment of single-mode fiber interconnections between the

  8. Fully-Integrated, Power-Efficient Regulator and Bandgap Circuits for Wireless-Powered Biomedical

    E-print Network

    Gulak, P. Glenn

    of such sensors are bacteria identification circuits or neural implants. In such systems the circuits containedFully-Integrated, Power-Efficient Regulator and Bandgap Circuits for Wireless-Powered Biomedical to the system. It is also highly desirable to fully integrate the power receiver circuits and the coil

  9. The 11th International Symposium on Wireless Personal Multimedia Communications (WPMC 2008) DEVELOPMENT OF THZ TRANSISTORS

    E-print Network

    Rodwell, Mark J. W.

    ) DEVELOPMENT OF THZ TRANSISTORS AND (300-3000 GHZ) SUB-MM-WAVE INTEGRATED CIRCUITS Mark Rodwell, E. Lobisser, M of 1-3 THz. High bandwidths are obtained by scaling; the critical limits to such scaling maxf and 324 GHz amplifiers have been demonstrated. Transistors with target maxf over 1 THz

  10. InP Photonic Integrated Circuits

    Microsoft Academic Search

    Radhakrishnan Nagarajan; Masaki Kato; Jacco Pleumeekers; Peter Evans; Scott Corzine; Sheila Hurtt; Andrew Dentai; Sanjeev Murthy; Mark Missey; Ranjani Muthiah; Randal A. Salvatore; Charles Joyner; Mehrdad Ziari; Fred Kish; David Welch

    2010-01-01

    InP is an ideal integration platform for optical generation, switching, and detection components operating in the range of 1.3-1.6 m wavelength, which is preferred for data transmission in the most prevalent silica-based optical fiber. We review the current state of the art in advanced InP photonic ICs.

  11. 3-D integration of MQW modulators over active submicron CMOS circuits: 375 Mb\\/s transimpedance receiver-transmitter circuit

    Microsoft Academic Search

    A. V. Krishnamoorthy; A. L. Lentine; K. W. Goossen; J. A. Walker; T. K. Woodward; J. E. Ford; G. F. Aplin; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. Dahringer; M. F. Chirovsky; D. A. B. Miller

    1995-01-01

    We accomplish the integration of GaAs-AlGaAs multiple quantum well modulators directly on top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved and also allows the design and optimization of the CMOS circuits to proceed independently of the placement and the bonding of surface-normal optical modulators to the circuit. Using this technique, we demonstrate operation of

  12. Nanoengineered polymers for photonic integrated circuits

    Microsoft Academic Search

    Louay Eldada

    2005-01-01

    We describe nanoengineered polymeric materials, their properties, and their use to produce state-of-the-art integrated optical components with optimal optical, electrical, mechanical, and thermal properties. These components met all performance and reliability requirements in the telecommunication industry, including Telcordia GR-1209\\/GR-1221 qualification, as well as accelerated aging tests that significantly exceed Telcordia requirements, such as aging at extreme temperature (5000 hours at

  13. Waveguide single-photon detectors for integrated quantum photonic circuits

    E-print Network

    J. P. Sprengers; A. Gaggero; D. Sahin; S. Jahanmiri Nejad; F. Mattioli; R. Leoni; J. Beetz; M. Lermer; M. Kamp; S. Höfling; R. Sanjines; A. Fiore

    2011-08-25

    The generation, manipulation and detection of quantum bits (qubits) encoded on single photons is at the heart of quantum communication and optical quantum information processing. The combination of single-photon sources, passive optical circuits and single-photon detectors enables quantum repeaters and qubit amplifiers, and also forms the basis of all-optical quantum gates and of linear-optics quantum computing. However, the monolithic integration of sources, waveguides and detectors on the same chip, as needed for scaling to meaningful number of qubits, is very challenging, and previous work on quantum photonic circuits has used external sources and detectors. Here we propose an approach to a fully-integrated quantum photonic circuit on a semiconductor chip, and demonstrate a key component of such circuit, a waveguide single-photon detector. Our detectors, based on superconducting nanowires on GaAs ridge waveguides, provide high efficiency (20%) at telecom wavelengths, high timing accuracy (60 ps), response time in the ns range, and are fully compatible with the integration of single-photon sources, passive networks and modulators.

  14. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to

    E-print Network

    Rogers, John A.

    Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses complementary metal-oxide-semi- conductor (CMOS) integrated circuits approaching that of conven- tional devices of single crystalline silicon nanomaterials for the semiconductor pro- vides performance in stretchable

  15. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-12

    ...Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products Containing Same; Commission...of certain integrated circuit packages provided with multiple heat-conducting paths and products containing same by reason...

  16. Large scale integration of graphene transistors for potential applications in the back end of the line

    NASA Astrophysics Data System (ADS)

    Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

    2015-06-01

    A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

  17. Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

    SciTech Connect

    Dell'Erba, Giorgio; Natali, Dario [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano (Italy); Luzio, Alessandro; Caironi, Mario, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu [Heeger Center for Advanced Materials, School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwagiro, Buk-gu, Gwangju 500-712 (Korea, Republic of); Noh, Yong-Young, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Department of Energy and Materials Engineering, Dongguk University, 26 Pil-dong, 3-ga, Jung-gu, Seoul 100-715 (Korea, Republic of)

    2014-04-14

    Ambipolar semiconducting polymers, characterized by both high electron (?{sub e}) and hole (?{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with ?{sub h}?=?0.29 cm{sup 2}/V s and ?{sub e}?=?0.001 cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with ?{sub e}?=?0.12 cm{sup 2}/V s and ?{sub h}?=?8 ×?10{sup ?4}?cm{sup 2}/V?s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

  18. Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

    Microsoft Academic Search

    Ming Wu; Xiang-Zheng Bo; James C. Sturm; Sigurd Wagner

    2002-01-01

    We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950°C. The substrates were 0.2-mm thick steel foil coated with 0.5-?m thick SiO2. We employed silicon crystallization times ranging from 6 h (600°C) to 20 s (950°C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO2

  19. Evaluation of AlGaN\\/GaN Heterostructure Field-Effect Transistors on Si Substrate in Power Factor Correction Circuit

    Microsoft Academic Search

    Shinichi Iwakami; Osamu Machida; Yoshimichi Izawa; Ryohei Baba; Masataka Yanagihara; Toshihiro Ehara; Nobuo Kaneko; Hirokazu Goto; Akio Iwabuchi

    2007-01-01

    A new device of high-power AlGaN\\/GaN heterostructure field-effect transistors (HFETs) fabricated on a Si substrate is proposed. Its application of the power factor correction (PFC) circuit is presented for the first time. The AlGaN\\/GaN HFETs fabricated on the Si substrate with a gate width of 152 mm exhibited a breakdown voltage of more than 800 V, an on-resistance of 65

  20. Hybrid integration of light emitting diodes with photonic integrated circuits on silicon

    Microsoft Academic Search

    D. Cristea; M. Modreanu; M. Caldararu; H. Cernica; V. Avramescu

    1998-01-01

    This paper presents the experiments we performed for hybrid integration of LEDs with silicon photonic integration circuits. LEDs were face down mounted in a silicon cavity. The edge-emitted light is coupled in SiON waveguides. The silicon cavity was obtained by anisotropic etching of the silicon substrate. The integration of all the components on one chip increases the sensor reliability and

  1. RTD\\/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

    Microsoft Academic Search

    J. I. Bergman; J. Chang; Y. Joo; B. Matinpour; J. Laskar; N. M. Jokerst; M. A. Brooke; B. Brar

    1999-01-01

    The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed

  2. An analogue test technique for massively parallel integrated circuits and systems: An approach to neural networks circuits testing

    Microsoft Academic Search

    Kurosh Madani

    1993-01-01

    \\u000a Abstract  The increase in integration density and in complexity of moderns integrated circuits and systems revealed the necessity to\\u000a consider the testability problem at the design level of circuits. One of the most active research areas in circuits design,\\u000a over the past decade, has been the implementation of neural networks as electronic VLSI chips. Especially, the implementation\\u000a of artificial neural networks

  3. How to Build Electronic Circuits

    NSDL National Science Digital Library

    Safronoff, Ross

    This site offers a series of 41 videos about building electronic circuits. The videos include: -How Electron Flow Occurs in Electronic Circuits -Why Schematics are Used to Build Electronic Circuits -How Current is Determined by the Electronic Circuit -How Resistors Work in Electronic Circuits -Color Codes for Resistors in Electronic Circuits -How Capacitors Work in Electronic Circuits -How to Store a Charge in a Capacitor Inductors & Their Function -How to Measure Components in an Electronic Circuit -How Printed Circuit Boards Work -What Tools are Needed to Work with Electronics -Differences in Wire Gauges -How to Strip Wires Using Wire Strippers -How to Safely Work with Electronics -How to Power an Electronic Circuit -How to Measure Voltage in an Electronic Circuit -How to Measure Current in a Circuit -How to Measure Resistance in an Electronic Circuit -How Soldering Irons Work -How to Tin a Soldering Iron -How to Solder Electronic Leads Together -How to Use Perfboard to Make an Electronic Circuit -How to De-solder Electronic Connections -How to Diagnose Cold Solder Connections -How to Reflow a Connection in an Electronic Circuit -How to Use a Breadboard to Prototype a Circuit Board -How a Light Emitting Diode Works Uses & Operation of a Fuse -How to Use Integrated Circuits -How Transistors Work in an Electronic Circuit -How a Variable Resistor Works in an Electronic Circuit -How Does a Series Circuit Work -How to Compute Resistor Resistance in an Electronic Circuit -How Resistors Work in Parallel Circuits -How Schematics are Used in Electronics -How Switches Open & Close Circuits Electronic Circuits in Garage Door Openers -How to Make a Schematic for Your Electronic Circuit Project -How to Test a Prototype of Your Electronic Circuit -How to Use Perfboard to Build an Electronic Circuit and -Practical Operation of Electronic Circuit Indicators

  4. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

    PubMed

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

    2008-12-01

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

  5. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

    PubMed Central

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

    2008-01-01

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ?1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ?140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

  6. Integrated circuit electrometer and sweep circuitry for an atmospheric probe

    NASA Technical Reports Server (NTRS)

    Zimmerman, L. E.

    1971-01-01

    The design of electrometer circuitry using an integrated circuit operational amplifier with a MOSFET input is described. Input protection against static voltages is provided by a dual ultra low leakage diode or a neon lamp. Factors affecting frequency response leakage resistance, and current stability are discussed, and methods are suggested for increasing response speed and for eliminating leakage resistance and current instabilities. Based on the above, two practical circuits, one having a linear response and the other a logarithmic response, were designed and evaluated experimentally. The design of a sweep circuit to implement mobility measurements using atmospheric probes is presented. A triangular voltage waveform is generated and shaped to contain a step in voltage from zero volts in both positive and negative directions.

  7. Optimized structural designs for stretchable silicon integrated circuits.

    PubMed

    Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

    2009-12-01

    Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies. PMID:19824002

  8. Six-channel neural signal regeneration integrated circuit.

    PubMed

    Li, Wenyuan; Wang, Fei; Wang, Zhigong; Lu, Xiaoying; Shen, Xiaoyan

    2009-01-01

    A six-channel neural signal regeneration integrated circuit (IC) was designed and fabricated in CSMC's 0.5-microm CMOS technology. The circuit consists of a low-noise and high common mode rejection ratio (CMRR) instrument amplifier, an inverted operational amplifier (OPA) and a buffer. The six-channel IC occupies a die area of 1.9mmx1.6mm. The testing result shows that the consumption of a single channel is less than 5 mW, and the output voltage swing reaches 5 V under +/-2.5V power supply, the gain can be adjusted from 60dB to 110dB. The circuit has been used for in-vivo experiments on toad's nerve with electrodes to regenerate neural signals. Different neural signals have been successfully regenerated on toad's nerve and corresponding actions have been observed. PMID:19964761

  9. A new patterning process concept for large-area transistor circuit fabrication without using an optical mask aligner

    Microsoft Academic Search

    Yoshiro Mikami; Yoshiharu Nagae; Yuji Mori; Kazuhiro Kuwabara; Takeshi Saito; H. Hayama; H. Asada; Y. Akimoto; M. Kobayashi; S. Okazaki; K. Asaka; H. Matsui; K. Nakamura; E. Kaneko

    1994-01-01

    A new concept to produce large thin film transistor liquid crystal displays (TFT-LCD's) without using an optical mask aligner is proposed which emphasizes patterning technology. Some experimental thin film transistors (TFT's) are fabricated according to the concept and operated like conventional transistors fabricated by using an optical mask aligner. The concept includes improvement of printing technology and development of a

  10. Publish date: 06/27/2011 ECE 4321: Applications of Analog Integrated Circuits

    E-print Network

    Gelfond, Michael

    Publish date: 06/27/2011 ECE 4321: Applications of Analog Integrated Circuits Credit / Contact, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000. Catalog description: Principles involved in designing analog integrated circuits. Device physics, small-signal and large-signal models. Biasing

  11. Publish date: 06/27/2011 ECE 4310: Introduction to Very Large Scale Integrated Circuit Design

    E-print Network

    Gelfond, Michael

    Publish date: 06/27/2011 ECE 4310: Introduction to Very Large Scale Integrated Circuit Design: B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001. Catalog description: ECE introduction to very large-scale integrated design of circuits and devices. Geometrical patterns

  12. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, Anthony F. (Berkeley, CA); Malba, Vincent (Livermore, CA)

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  13. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  14. Detectability of dynamic photon emission in static Si CCD for signal path determination in integrated circuits

    Microsoft Academic Search

    Piotr Laskowski; Arkadiusz Glowacki; Christian Boit

    2008-01-01

    The detection of dynamic photon emission by static cameras is an inexpensive approach to track circuit signal paths, but successful application depends on the signal pattern and frequency the devices are operating at. For improvement of predictability, a model has been developed, built upon the composition of operating modes and targeted to calculate the static emission signal. On single transistor

  15. Investigation of SFQ integrated circuits using Nb fabrication technology

    NASA Astrophysics Data System (ADS)

    Numata, H.; Tanaka, M.; Kitagawa, Y.; Tahara, S.

    1999-11-01

    In NEC's standard process, the minimum junction size is 2 µm and the critical current density (JC) is 2.5 kA cm-2. In the process, i-line stepper lithography and reactive ion etching with SF6 gas are used and the standard deviation (icons/Journals/Common/sigma" ALT="sigma" ALIGN="TOP"/>) of the critical current (IC) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an IC variation of +/-10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.

  16. Refractory resistors with etch stop for superconductor integrated circuits

    SciTech Connect

    Przybysz, J.X.; Buttan, J.

    1990-02-27

    This patent describes a method for preparing molybdenum resistors in a superconductor integrated circuit. It comprises: depositing superconductor film on a support; patterning the superconductor film to provide a patterned superconductor and exposed support; applying an aluminum film on the superconductor film and the exposed support; applying a molybdenum film on the aluminum film to provide an aluminum-molybdenum, etch-stop interface; applying a patterned resist film on the molybdenum film to provide exposed molybdenum film and unexposed molybdenum film; etching the exposed molybdenum film to define the molybdenum resistor and expose a portion of the aluminum-molybdenum, etch-stop interface; and oxidizing the exposed aluminum-molybdenum, etch-stop interface. The aluminum-molybdenum, etch-stop interface protects the patterned superconductor film and the support and increases processing margins for the etch time. Also described is a molybdenum resistor configuration for a superconductor integrated circuit.

  17. Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits

    Microsoft Academic Search

    Zyad Hassan; Nicholas Allec; Li Shang; Robert P. Dick; Vishak Venkatraman; Ronggui Yang

    2009-01-01

    Thermal analysis has long been essential for designing reliable high-performance cost-effective integrated circuits (ICs). Increasing power densities are making this problem more important. Characterizing the thermal profile of an IC quickly enough to allow feedback on the thermal effects of tentative design changes is a daunting problem, and its complexity is increasing. The move to nanometer-scale fabrication processes is increasing

  18. Wireless integrated circuit for 100-channel neural stimulation

    Microsoft Academic Search

    Brandon K. Thurgood; Noah M. Ledbetter; David J. Warren; Gregory A. Clark; Reid R. Harrison

    2008-01-01

    We present the design of an integrated circuit for wireless neural stimulation, along with bench-top and in-vivo experimental results. The chip has the ability to drive 100 individual stimulation electrodes with constant-current pulses of varying amplitude, duration, interphasic delay, and repetition rate. The stimulation is done using a biphasic (cathodic and anodic) current source, injecting and retracting charge from the

  19. Wireless Neural Recording With Single Low-Power Integrated Circuit

    Microsoft Academic Search

    Reid R. Harrison; Ryan J. Kier; Cynthia A. Chestek; Vikash Gilja; Paul Nuyujukian; Stephen Ryu; Bradley Greger; Florian Solzbacher; Krishna V. Shenoy

    2009-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled

  20. Silicon compiler design of combinational and pipeline adder integrated circuits

    Microsoft Academic Search

    A. O. Froede III

    1985-01-01

    The architecture and structures used by the MacPitts silicon compiler to design integrated circuits are described, and the capabilities and limitations of the compiler are discussed. The performance of several combinational and pipeline adders designed by MacPitts and a hand-crafted pipeline adder are compared. Several different MacPitts design errors are documented. Tutorial material is presented to aid in using the

  1. Electromagnetic Interference (EMI) Resisting Analog Integrated Circuit Design Tutorial

    E-print Network

    Yu, Jingjing

    2012-10-19

    .............................................................................................. 7 2.2 EMI Transmission .......................................................................................... 10 2.3 Integrated Circuit Susceptibility to Conducted EMI/RFI ................................. 13 2.3.1 EMI/RFI Effects... Page Fig. 1. 1. Sources of EMI/RFI in a System on a Chip (SoC) typical architecture ........... 2 Fig. 1. 2. Effect of EMI/RFI conveyed to the input pin ................................................. 4 Fig. 2. 1. Commonly-used terms...

  2. Optical Packet & Circuit Integrated Network for Future Networks

    NASA Astrophysics Data System (ADS)

    Harai, Hiroaki

    This paper presents recent progress made in the development of an optical packet and circuit integrated network. From the viewpoint of end users, this is a single network that provides both high-speed, inexpensive services and deterministic-delay, low-data-loss services according to the users' usage scenario. From the viewpoint of network service providers, this network provides large switching capacity with low energy requirements, high flexibility, and efficient resource utilization with a simple control mechanism. The network we describe here will contribute to diversification of services, enhanced functional flexibility, and efficient energy consumption, which are included in the twelve design goals of Future Networks announced by ITU-T (International Telecommunication Union - Telecommunication Standardization Sector). We examine the waveband-based network architecture of the optical packet and circuit integrated network. Use of multi-wavelength optical packet increases the switch throughput while minimizing energy consumption. A rank accounting method provides a solution to the problem of inter-domain signaling for end-to-end lightpath establishment. Moving boundary control for packet and circuit services makes for efficient resource utilization. We also describe related advanced technologies such as waveband switching, elastic lightpaths, automatic locator numbering assignment, and biologically-inspired control of optical integrated network.

  3. Nanowire-organic thin film transistor integration and scale up towards developing sensor array for biomedical sensing applications

    NASA Astrophysics Data System (ADS)

    Kumar, Prashanth S.; Hankins, Phillip T.; Rai, Pratyush; Varadan, Vijay K.

    2010-04-01

    Exploratory research works have demonstrated the capability of conducting nanowire arrays in enhancing the sensitivity and selectivity of bio-electrodes in sensing applications. With the help of different surface manipulation techniques, a wide range of biomolecules have been successfully immobilized on these nanowires. Flexible organic electronics, thin film transistor (TFT) fabricated on flexible substrate, was a breakthrough that enabled development of logic circuits on flexible substrate. In many health monitoring scenarios, a series of biomarkers, physical properties and vital signals need to be observed. Since the nano-bio-electrodes are capable of measuring all or most of them, it has been aptly suggested that a series of electrode (array) on single substrate shall be an excellent point of care tool. This requires an efficient control system for signal acquisition and telemetry. An array of flexible TFTs has been designed that acts as active matrix for controlled switching of or scanning by the sensor array. This array is a scale up of the flexible organic TFT that has been fabricated and rigorously tested in previous studies. The integration of nanowire electrodes to the organic electronics was approached by growing nanowires on the same substrate as TFTs and fl ip chip packaging, where the nanowires and TFTs are made on separate substrates. As a proof of concept, its application has been explored in various multi-focal biomedical sensing applications, such as neural probes for monitoring neurite growth, dopamine, and neuron activity; myocardial ischemia for spatial monitoring of myocardium.

  4. Neuromorphic opto-electronic integrated circuits for optical signal processing

    NASA Astrophysics Data System (ADS)

    Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

    2014-08-01

    The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

  5. Photonic-integrated circuit for continuous-wave THz generation.

    PubMed

    Theurer, Michael; Göbel, Thorsten; Stanze, Dennis; Troppenz, Ute; Soares, Francisco; Grote, Norbert; Schell, Martin

    2013-10-01

    We demonstrate a photonic-integrated circuit for continuous-wave (cw) terahertz (THz) generation. By comprising two lasers and an optical phase modulator on a single chip, the full control of the THz signal is enabled via a unique bidirectional operation technique. Integrated heaters allow for continuous tuning of the THz frequency over 570 GHz. Applied to a coherent cw THz photomixing system operated at 1.5 ?m optical wavelength, we reach a signal-to-noise ratio of 44 dB at 1.25 THz, which is identical to the performance of a standard system based on discrete components. PMID:24081036

  6. A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor

    E-print Network

    Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

    2010-08-28

    We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

  7. A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor

    E-print Network

    Wang, Ling-Jun; Tu, Tao; Li, Hai-Ou; Zhou, Cheng; Hao, Xiao-Jie; Su, Zhan; Guo, Guang-Can; Guo, Guo-Ping; Jiang, Hong-Wen

    2010-01-01

    We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

  8. Large-scale DWDM photonic integrated circuits: a manufacturable and scalable integration platform

    Microsoft Academic Search

    C. H. Joyner; J. L. Pleumeekers; A. Mathur; P. W. Evans; D. J. H. Lambert; S. Murthy; S. K. Mathis; F. H. Peters; J. Baeck; M. J. Missey; A. G. Dentai; R. A. Salvatore; R. P. Schneider; M. Ziari; M. Kato; R. Nagarajan; J. S. Bostak; T. Butrie; V. G. Dominic; M. Kauffman; R. H. Miles; M. L. Mitchell; A. C. Nilsson; S. C. Pennypacker; R. Schlenker; R. B. Taylor; Huan-Shang Tsai; M. F. Van Leeuwen; J. Webjorn; D. Perkins; J. Singh; S. G. Grubb; M. Reffle; D. G. Mehuys; F. A. Kish; D. F. Welch

    2005-01-01

    Commercial scaling of electronic integrated circuits has proceeded at a fast pace once the initial hurdle to integration was overcome. Recently, it has been shown that record active and passive optical device counts, exceeding 50 discrete components, can be incorporated onto a single monolithic 100 Gbps DWDM transmitter PIC InP chip. We will investigate key production metrics for this large-scale

  9. The Planar Circuit--An Approach to Microwave Integrated Circuitry

    Microsoft Academic Search

    TAKANORI OKOSHI; TANROKU MIYOSHI

    1972-01-01

    Three principal categories have been known in electrical circuitry so far. They are the lumped-constant (0-dimensional) circuit, distributed-constant (1-dimensional) circuit, and waveguide (3-dimensional) circuit. The planar circuit to be discussed in general in this paper is a circuit category that should be positioned as a 2-dimensional circuit. It is defined as an \\

  10. A bipolar analog front-end integrated circuit for the SDC silicon tracker

    SciTech Connect

    Kipnis, I.; Spieler, H.; Collins, T.

    1993-11-01

    A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT&T`s CBIC-U2, 4 GHz f{sub T} complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 {mu}m pitch double-sided silicon strip detector. The chip measures 6.8 mm {times} 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a {Phi}=10{sup 14} protons/cm{sup 2} have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

  11. The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

    Microsoft Academic Search

    Ahmet Bindal; Sotoudeh Hamedi-Hagh

    2006-01-01

    This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication

  12. Fully integrated circuit chip of microelectronic neural bridge

    NASA Astrophysics Data System (ADS)

    Xiaoyan, Shen; Zhigong, Wang

    2014-09-01

    Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-?m CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

  13. Integrating anatomy and function for zebrafish circuit analysis.

    PubMed

    Arrenberg, Aristides B; Driever, Wolfgang

    2013-01-01

    Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

  14. ASAP: a portable program for the symbolic analysis of analog integrated circuits

    Microsoft Academic Search

    F. V. Fernandez; A. Rodriguez-Vazquez; J. L. Huertas

    1990-01-01

    A new and efficient symbolic analyzer for analog integrated circuits, ASAP (Analog Symbolic Analysis Program), is presented. ASAP provides symbolic expressions for all types of AC transfer and driving-point characteristics of analog integrated circuits. The resulting expressions can be automatically simplified, which makes them useful for circuit synthesis. The main features of the program are described as well as some

  15. Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference

    Microsoft Academic Search

    Lawrence T. Clark; Ranjit Gharpurey; Payam Heydari

    2008-01-01

    This special issue of the IEEE Journal of Solid-State Circuits is a selection of papers published in the IEEE 2007 Custom Integrated Circuits Conference (CICC). The issue consists of 14 papers that cover a wide range of technical areas, including wireless and RF circuit design, mixed-signal and analog design, digital IC design, integrated power regulation, memory design and biological applications

  16. Design of Integrated Fiber-Optic Receivers Using Heterojunction Bipolar Transistors.

    NASA Astrophysics Data System (ADS)

    Buchwald, Aaron Wayne

    Recent demands for increased information transfer through communication networks are stretching channel capacities to the limit. Telecommunication trunking, local-area data networks, video on demand, integrated multi-media applications, etc. require ever increasing bandwidths. Optical fibers are the best known medium for point-to-point communication because of their high bandwidth (1400 GHz-km) and low losses (0.15 dB/km). Electronic circuits are not fast enough to fully exploit the broadhand fiber-optic channel, and cause a bottleneck in the throughput of optical communication systems. This dissertation focuses on the theory and practice of the design of integrated circuits for multi-gigabit -per-second fiber-optic receivers. Realizing a 10 Gb/s system consistent with the SONET hierarchy is the ultimate goal of the research, and test circuits were developed to this end. Difficulty in implementing clock recovery circuits at rates greater than 3 Gb/s have limited the capacity of integrated receivers. Therefore, considerable attention is paid to clock extraction techniques. Architectures applicable to high-speed systems and insensitive to parasitic effects are presented. Among the test circuits developed was a 12 GHz InP-based HBT preamplifier. The circuit contains a PIN photodetector and can achieve an rms input noise of approximately 1.25muA at a data rate of 10 Gb/s. Two VCOs were designed in an AIGaAs/GaAs HBT process. A ring oscillator and emitter-coupled multivibrator, both operating at 2.75 GHz were fabricated. A patented 7 GHz ring VCO with frequency doubling was also designed. The new VCO was used to implement a 6 GHz phase-lock loop. The test circuits demonstrate functionality of key building blocks of a high-speed clock recovery circuit. Simulations based on models extracted from the test circuit predict that the architectures presented are applicable for clock recovery at a data rate of 10 Gb/s. Further research is needed to implement a complete integrated receiver.

  17. Synthetic circuits integrating logic and memory in living cells.

    PubMed

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications. PMID:23396014

  18. Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign --Week 3, Lecture 5Week 3, Lecture 5

    E-print Network

    EE134 1 EE134 1 Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) LayoutAgenda " Last Lecture ! Design rules ! Layout and Design ! Ties to VDD and GND ! Padframes ! Pin Packages of CMOS digital ICs " Application Specific IC (ASIC) ! Full Custom (What we are doing) ­ Most flexible

  19. Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits

    E-print Network

    Nagarajan, Raghavan

    2008-01-01

    Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power ...

  20. Analog integrated circuit design techniques for high-speed signal processing in communications systems

    E-print Network

    Hernandez Garduno, David

    2009-05-15

    This work presents design techniques for the implementation of high-speed analog integrated circuits for wireless and wireline communications systems. Limitations commonly found in high-speed switched-capacitor (SC) circuits used for intermediate...

  1. The charge-flow transistor - A new MOS device. [for integrated sensor applications

    NASA Technical Reports Server (NTRS)

    Senturia, S. D.; Sechen, C. M.; Wishneusky, J. A.

    1977-01-01

    A new device, the charge-flow transistor (CFT), has been developed to achieve integrated MOS compatibility in sensor applications, such as gas, humidity, and fire detection, where one is interested in monitoring the transverse resistance of a thin film. The resistive material is incorporated into the gate structure of the CFT in such a way that there is a time delay between the application of the gate-to-source voltage and the appearance of a complete channel. This time delay depends on the resistivity of the thin film. A theory of device operation is presented, together with experimental results on the first CFT's. These results confirm the principles of operation, and demonstrate the utility of the CFT for making fully integrated sensing devices.

  2. Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits*

    E-print Network

    Thornton, Mitchell

    in that higher density per integrated circuit area can be achieved as compared to binary logic implementationsQuaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits* Satyendra R of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels

  3. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  4. Stainless Steel NaK Circuit Integration and Fill Submission

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

  5. Aesop: a tool for automated transistor sizing

    Microsoft Academic Search

    Kye S. Hedlund

    1987-01-01

    This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area

  6. Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits

    SciTech Connect

    Keast, Craig (M.I.T. Lincoln Laboratory) [M.I.T. Lincoln Laboratory

    2007-02-28

    Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

  7. Printing microchips Lithography is used in the manufacture of integrated circuits (ICs) to transfer circuit patterns from a mask to the silicon wafer.

    E-print Network

    circuit patterns from a mask to the silicon wafer. The number of transistors that can be put on a computer; - less than 70% reflectivity; - produces a 4 or 5 reduction of the mask's image on the wafer ­ 120 mm to illuminate the reflective reticle (mask); Wafer - thin slice of silicon or other

  8. Mixed signal custom integrated circuit development for physics instrumentation

    SciTech Connect

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  9. Development of optical packet and circuit integrated ring network testbed.

    PubMed

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. PMID:22274025

  10. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  11. An analytical approach to model manufacturing a drift heterobipolar transistors: On approach to optimize technological process to increase integration rate

    NASA Astrophysics Data System (ADS)

    Pankratov, E. L.; Bulaeva, E. A.

    2015-03-01

    In this paper, we introduce an approach to increase integration rate of drift heterobipolar transistors. The approach is based on manufacturing of heterostructure with spatial configuration, doping of required areas of the heterostructure by diffusion or ion implantation and optimization of annealing of dopant and/or radiation defects.

  12. A large-area, flexible, and lightweight sheet image scanner integrated with organic field-effect transistors and organic photodiodes

    Microsoft Academic Search

    T. Someya; S. Iba; Y. Kato; T. Sekitani; Y. Noguchi; Y. Murase; H. Kawaguchi; T. Sakurai

    2004-01-01

    A large-area, flexible, and lightweight sheet image scanner has been successfully manufactured on a plastic film, for the first time, integrating high-quality organic transistors and organic photodetectors. Since this area-type image-capturing device does not require any optics or any mechanical scanning devices, it is innovatively light to carry, shock-resistant and potentially inexpensive to manufacture.

  13. Design and application of thin, planar magnetic components for embedded passives integrated circuits

    Microsoft Academic Search

    Etierhard Waffenschmidt

    2004-01-01

    The integration of passive components into the printed circuit board (PCB) as embedded passives integrated circuits (emPIC) results in a higher power density of power converters. To achieve a highly automated, low cost, integral manufacturing, the devices are constructed layerwise. Especially for magnetic components like inductors and transformers the design of such thin components is challenge. Because of the high

  14. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits

    E-print Network

    Xiong, Qihua

    materials and suggest substantial promise for 3D inte- grated circuits. 3D integrated circuits multilayer reports (9, 10) have investigated 3D integration of nanoscale materials. This work has shown that sequential printing of NWs, nanoribbons, and/or CNTs is a viable approach for constructing 3D integrated

  15. A current mirroring integration based readout circuit for high performance infrared FPA applications

    Microsoft Academic Search

    Haluk Kulah; Tayfun Akin

    2003-01-01

    Reports a current mirroring integration (CMI) CMOS readout circuit for high-resolution infrared focal plane array (FPA) applications. The circuit uses a feedback structure with current mirrors to provide stable bias voltage across the photodetector diode, while mirroring the diode current to an integration capacitor. The integration capacitor can be placed outside of the unit pixel, reducing the pixel area and

  16. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  17. Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

    PubMed

    Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

    2015-04-01

    Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology. PMID:25968767

  18. Integrated circuit for processing a low-frequency signal from a seismic detector

    SciTech Connect

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex 'Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  19. Integration of a 4Stage 4 K Pulse Tube Cryocooler Prototype With a Superconducting Integrated Circuit

    Microsoft Academic Search

    Vladimir V. Dotsenko; Jean Delmas; Robert J. Webber; Timur V. Filippov; Dmitry E. Kirichenko; Saad Sarwana; Deepnarayan Gupta; Alan M. Kadin; Elie K. Track

    2009-01-01

    A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power,

  20. Multi-parameter extraction from SOI photonic integrated circuits using circuit simulation and evolutionary algorithms

    NASA Astrophysics Data System (ADS)

    Ruocco, A.; Fiers, M.; Vanslembrouck, M.; Van Vaerenbergh, T.; Bogaerts, W.

    2015-02-01

    We propose a procedure to extract multiple parameters from the spectral characteristic of a single photonic integrated circuit. We applied the method on high order silicon Mach-Zehnder lattice filters:1 these filters are realized by cascading delay stages and directional couplers of different length. Because of their cascaded nature and steep roll-off properties, these devices can be used to accurately extract properties of the waveguides and the directional couplers. The spectral transmission is measured between the inputs and the outputs. This result is compared to a full CAPHE optical circuit simulation with parametric behavioral models for the waveguide and the directional couplers. An evolutionary fitting algorithm based on the covariance matrix adaptation method is used to match the circuit simulation with the measurement. This black box approach gives us fast and accurate parameter extraction with a reduced number of iteration steps. The quadratic error between measurement and simulation of each iteration is used as feedback for the evolutionary algorithm that adapts the test values for the following step. The objective of our analysis is an accurate, wavelength-dependent model for the waveguide group index and the directional couplers. The proposed method has been used for wafer scale parameter extraction. Our fast method makes it possible to extract the parameters in real time, and correlate the functional parameters of the waveguides with process statistics collected during fabrication. The obtained parameters are in substantial agreement with the results of the simulations used in the design, and can be used to further improve behavioral models that correlate the manufacturing process data with the optical performance.

  1. Planar resonant multi-output transformer for printed circuit board integration

    Microsoft Academic Search

    Eberhard Waffenschmidt; Joep Jacobs

    2008-01-01

    A converter with printed circuit board integrated transformer to supply 16 similar isolated loads is designed and manufactured. The transformer of the power converter is constructed as planar device consisting of printed circuit board spiral windings and ferrite polymer compound plates as magnetic core, which can be laminated to the printed circuit board. The design consists of one large primary

  2. Two-Transistor Active Pixel Sensor Readout Circuits in Amorphous Silicon Technology for High-Resolution Digital Imaging Applications

    Microsoft Academic Search

    Farhad Taghibakhsh; Karim S. Karim

    2008-01-01

    Active pixel sensor (APS) architectures using two transistors per pixel are reported in this paper for high-resolution low-noise digital imaging applications. The fewer number of on-pixel elements and reduced pixel complexity result in a smaller pixel pitch and increased pixel gain, which makes the two-transistor (2T) APS architectures promising for high-resolution, low-noise, and high-speed digital imaging including emerging medical imaging

  3. High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel

    E-print Network

    High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum (5pp) doi:10.1088/0268-1242/28/11/115003 High-performance polycrystalline silicon thin September 2013 Online at stacks.iop.org/SST/28/115003 Abstract Polycrystalline silicon thin-film transistors

  4. Testing of analog integrated circuits based on power-supply current monitoring and discrimination analysis

    Microsoft Academic Search

    Zhihua Wang; Georges Gielen; Willy Sansen

    1994-01-01

    A new method for the testing and fault detection of analog integrated circuits is presented. The power-supply current is monitored to detect possible faults in an analog circuit. The spectrum of the power-supply current is used to construct the statistical signature of the fault-free and faulty circuits. The decision of a circuit being fault-free or faulty is taken based on

  5. Investigation of failure mechanisms in integrated vacuum circuits

    NASA Technical Reports Server (NTRS)

    Rosengreen, A.

    1972-01-01

    The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

  6. Feasibility of BCB as an interlevel dielectric in integrated circuits

    NASA Astrophysics Data System (ADS)

    Bothra, S.; Kellam, M.; Garrou, P.

    1994-08-01

    This paper investigates the feasibility of using an organic polymer based on benzocyclobutene as an interlevel dielectric material in very large scale integrated (VLSI) circuits. The material is a thermoset resin with attractive electrical and mechanical properties for application as an interlevel dielectric in VLSI circuits. It has a low relative dielectric constant of 2.7. The single coating planarization achieved by spin coating the material is superior to currently used materials and makes it a very attractive material for the fabrication of multilevel metal systems. The planarization properties of this material are presented and compared with those of polyimide. The patterning and dry etching of BCB to define 1 µm vias is described. As the material has limited thermal stability at temperatures greater than 350°C, compatible materials for low via resistivity have been investigated using a double level metal structure. The effect of post metal anneals on via resistivity of various via structures is presented. It is found that a low via resistivity of 3 × 10-9 gW-cm2 without any post metal anneal is obtained by using an AlCu/Pd-AlCu metallurgy.

  7. Basic structures of integrated photonic circuits for smart biosensor applications

    NASA Astrophysics Data System (ADS)

    Germer, S.; Cherkouk, C.; Rebohle, L.; Helm, M.; Skorupa, W.

    2013-05-01

    The breadth of opportunities for applied technologies for optical sensors ranges from environmental and biochemical control, medical diagnostics to process regulation. Thus the specified usage of the optical sensor system requires a particular design and functionalization. Especially biochemical sensors incorporate electronic and photonic devices for the detection of harmful substances e.g. in drinking water. Here we present recent developments in the integration of a Si-based light emitting device (LED) [1-3, 8] into a photonic circuit for an optical waveguide-based biodetection system. This concept includes the design, fabrication and characterization of the dielectric high contrast waveguide as an important component, beside the LED, in the photonic system circuit. First approaches involve simulations of Si3N4/SiO2-waveguides with the finite element method (FEM) and their fabrication by plasma enhanced chemical vapour deposition (PECVD), optical lithography and reactive ion etching (RIE). In addition, we characterized the deposited layers via ellipsometry and the etched structures by scanning electron microscopy (SEM). The obtained results establish a basis for optimized Si-based LED waveguide butt-coupling with adequate coupling efficiency, low attenuation loss and a high optical power throughput.

  8. CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600°C

    Microsoft Academic Search

    M. Takabatake; J. Ohwada; Y. A. Ono; K. Ono; A. Mimura; N. Konishi

    1991-01-01

    CMOS shift registers, buffers, and gray-scale representation circuits for integrated peripheral drive circuits of poly-Si TFT LCDs were fabricated at temperatures below 600°C on a glass substrate. The maximum operation frequency of the CMOS shift register was 1.25 MHz. The total power consumption of the 10 stage CMOS shift registers at a clock frequency of 46.8 kHz and a power

  9. Advanced lift-off planarization process for Josephson integrated circuits

    SciTech Connect

    Ishida, I.; Tahara, S.; Wada, Y.

    1988-07-25

    An advanced lift-off planarization process utilizing an undercut technique of a photoresist etching mask has been developed to achieve planarization of thin-sputtered and fine-patterned films that are necessary for high-performance Josephson integrated circuits (IC's). A stack of the same kind of photoresist layers, including the modified layer between them, has been utilized as an etching mask providing fine-patterned film profiles with minimized resist degradation by the top photoresist protection layer. This advanced planarization process brings about smooth surfaces having no residues and no grooves along pattern edges. 30 nm deviation from planarity has been demonstrated on a 200-nm-thick planarized Nb superconducting layer. A four-level interconnection of Josephson IC's was successfully fabricated by this process.

  10. Apparatus and method for defect testing of integrated circuits

    DOEpatents

    Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  11. Apparatus and method for defect testing of integrated circuits

    SciTech Connect

    Cole, E.I. Jr.; Soden, J.M.

    2000-02-29

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  12. Plasmonic nanopatch array for optical integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  13. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  14. Unfolding an electronic integrate-and-fire circuit.

    PubMed

    Carrillo, Humberto; Hoppensteadt, Frank

    2010-01-01

    Many physical and biological phenomena involve accumulation and discharge processes that can occur on significantly different time scales. Models of these processes have contributed to understand excitability self-sustained oscillations and synchronization in arrays of oscillators. Integrate-and-fire (I+F) models are popular minimal fill-and-flush mathematical models. They are used in neuroscience to study spiking and phase locking in single neuron membranes, large scale neural networks, and in a variety of applications in physics and electrical engineering. We show here how the classical first-order I+F model fits into the theory of nonlinear oscillators of van der Pol type by demonstrating that a particular second-order oscillator having small parameters converges in a singular perturbation limit to the I+F model. In this sense, our study provides a novel unfolding of such models and it identifies a constructible electronic circuit that is closely related to I+F. PMID:20039058

  15. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K. [Oak Ridge National Lab., TN (United States); Naser, J. [Electric Power Research Inst., Palo Alto, CA (United States); Rana, I. [Southern Company Services, Birmingham, AL (United States)

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

  16. Integrated Conditional Teleportation and Readout Circuit Based on a Photonic Crystal Single Chip

    E-print Network

    Durdu Ö. Güney; David A. Meyer

    2006-05-06

    We demonstrate the design of an integrated conditional quantum teleportation circuit and a readout circuit using a two-dimensional photonic crystal single chip. Fabrication and testing of the proposed quantum circuit can be accomplished with current or near future semiconductor process technology and experimental techniques. The readout part of our device, which has potential for independent use as an atomic interferometer, can also be used on its own or integrated with other compatible optical circuits to achieve atomic state detection. Further improvement of the device in terms of compactness and robustness could be achieved by integrating it with sources and detectors in the optical regime.

  17. Characterization and requirements for Cu-Cu bonds for three-dimensional integrated circuits

    E-print Network

    Tadepalli, Rajappa, 1979-

    2007-01-01

    Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and reduces global RC delay by increasing the device density per unit chip area. ...

  18. Heterogeneous photonic integrated circuits and their applications in computing, networking, and imaging

    E-print Network

    Yoo, S. J. Ben

    consumption, while enhancing performance, stability, reliability, and scalability. In some cases, photonicHeterogeneous photonic integrated circuits and their applications in computing, networking, networking, and imaging applications. We will review photonic integration technologies including silicon, In

  19. A complete monolithically-integrated circuit for all-optical generation of millimeter-wave frequencies

    Microsoft Academic Search

    G. A. Vawter; A. Mar; V. Hietala; J. Zolper

    1997-01-01

    An optoelectronic integrated circuit for generating mm-wave frequencies is demonstrated and design issues detailed. A monolithically integrated ring laser, optical amplifier, and photodiode generate electrical signals up to 85.2 GHz.

  20. A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation

    Microsoft Academic Search

    KLAAS BULT; ANDHANS WALLINGA

    1987-01-01

    ,4Mruct—A class of accurateanafog CMOS circuits is presented which relieson the square-law characteristic of MOStransistorsoperating in the saturated region. 'fIds class of circuits includes voltage multipliers, current multipliers, linear V-Z convertors (LVIC'S), linearZ- V convertors (LfVC's),current squaring circuits (CSC'S), and current divider circuits (DfVC's). Typicalfor thesecircuitsis an independent control of the sum as well as the difference between two gate-source

  1. Noise analysis for infrared focal plane arrays CMOS readout integrated circuit

    Microsoft Academic Search

    Jiamu Lin; Ruijun Ding; Honglei Chen; Xiao Shen; Fei Liu

    2008-01-01

    With the development of the infrared focal plane detectors, the internal noises in the infrared focal plane arrays (IRFPAs) CMOS readout integrated circuit gradually became an important factor of the development of the IRFPAs. The internal noises in IRFPAs CMOS readout integrated circuit are researched in this work. Part of the motivation for this work is to analyze the mechanism

  2. A Systems Approach to a Compatible Family of Linear Integrated Circuits

    Microsoft Academic Search

    G. Strull; M. N. Giuliano; R. C. Gallagher

    1966-01-01

    An efficient and rapid technique for developing a compatible family of custom integrated circuits for systems applications is described. The approach makes use of a general purpose functional block which can be readily wired into a number of integrated circuit configurations. Wire bonded interconnections are used in place of the usual metallized interconnections. This permits a convenient form factor for

  3. Exploitation of parallelism and ultraspeed integrated circuits in the next generation of distributed super signal processors

    SciTech Connect

    Gilbert, B.K.; Naused, B.A.; Hartley, S.M.; Vannurden, W.K.; Deming, R.

    1983-10-01

    The emerging application of gallium arsenide digital integrated circuits to signal processing problems will require the development of architectures tuned to its special characteristics. Chip design methods may be similar to those used for silicon very high-speed integrated circuit (VHSIC) components, but system design constraints will be unique to GAAS. 8 references.

  4. Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits

    Microsoft Academic Search

    Marios Iliopoulos; Theodore Antonakopoulos

    2000-01-01

    The increasing demand of networking applications has imposed a new category of electronic circuits that integrate powerful CPU processing, networking and system support functions in a single, low cost chip. These integrated circuits, called Network Processors, are optimized for tasks such as access protocol implementation, data queuing and forwarding, traffic shaping and Quality of Service (QoS) support. This paper presents

  5. EPIC: Ending Piracy of Integrated Circuits Jarrod A. Roy, Farinaz Koushanfar and Igor L. Markov

    E-print Network

    Markov, Igor

    EPIC: Ending Piracy of Integrated Circuits Jarrod A. Roy, Farinaz Koushanfar and Igor L. Markov technique to end piracy of integrated circuits (EPIC). It requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be dupli- cated. EPIC

  6. EPIC: Ending Piracy of Integrated Circuits Jarrod A. Royt, Farinaz Koushanfart and Igor L. Markovt

    E-print Network

    EPIC: Ending Piracy of Integrated Circuits Jarrod A. Royt, Farinaz Koushanfart and Igor L. Markovt a novel comprehensive technique to end piracy of integrated circuits (EPIC). It requires that every chip- cated. EPIC is based on (i) automatically-generated chip IDs, (ii) a novel combinational locking

  7. Design of integrated readout circuit with enhanced capacitance mechanism for dual-band infrared detector

    Microsoft Academic Search

    Tai-Ping Sun; Yi-Chuan Lu; Hsiu-Li Shieh; Shiuan-Shuo Shiu; Yi-Ting Liu; Shiang-Feng Tang; Wen-Jen Lin

    2011-01-01

    This study proposes a solution for an excessive dark current by a sharing capacitor, which avoids output signal distortion due to integration voltage saturation. Integration capacitance can be changed by adding a switch in the pixel circuit, which will increase the capacitance by two times the original. This circuit also provides output functions of either single-band or dual-band by switching

  8. Digital Integrated Circuit Layout and Design Prof: Roger Lake Hours/week: 3 lecture, 3 lab

    E-print Network

    EE134 Digital Integrated Circuit Layout and Design Prof: Roger Lake Hours/week: 3 lecture, 3 lab introduces the student to Complimentary Metal Oxide Semiconductor (CMOS) digital integrated circuit layout and design using industry standard CADENCE CAD tools. For undergraduate students: CMOS,layout, Bsim3 model

  9. A Complementary Metal-Oxide-Semiconductor Image Sensor with 2.0 e- Random Noise and 110 ke- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits

    NASA Astrophysics Data System (ADS)

    Kohara, Takahiro; Lee, Woonghee; Mizobuchi, Koichi; Sugawa, Shigetoshi

    2010-04-01

    A low noise complementary metal-oxide-semiconductor (CMOS) image sensor without degradation of saturation performance has been developed by using column amplifiers of the gains of about 1.0 in a lateral overflow integration capacitor technology. The 1/4-in., 4.5-µm pitch, 800H×600V pixels CMOS image sensor fabricated by a 0.18-µm 2-poly 3-metal CMOS technology including a buried pinned photo-diode structure has achieved fully linear response, 0.98 column readout gain, 104-µV/e- conversion gain, 2.0-e- total random noise, 110,000-e- full well capacity and 95-dB dynamic range in one exposure. Moreover, the random noise of the developed readout circuits has been reduced to 0.5-e- without degradation of saturation performance. As a result, the behaviors of pixel noises have been accurately measured. Operating condition dependency of the random noise generated by pixel transistors has been measured by using the developed readout circuits. In addition, considering the result of the measurements, we optimize pixel operating condition.

  10. A Complementary Metal-Oxide-Semiconductor Image Sensor with 2.0 e- Random Noise and 110 ke- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits

    NASA Astrophysics Data System (ADS)

    Takahiro Kohara,; Woonghee Lee,; Koichi Mizobuchi,; Shigetoshi Sugawa,

    2010-04-01

    A low noise complementary metal-oxide-semiconductor (CMOS) image sensor without degradation of saturation performance has been developed by using column amplifiers of the gains of about 1.0 in a lateral overflow integration capacitor technology. The 1/4-in., 4.5-?m pitch, 800H× 600V pixels CMOS image sensor fabricated by a 0.18-?m 2-poly 3-metal CMOS technology including a buried pinned photo-diode structure has achieved fully linear response, 0.98 column readout gain, 104-?V/e- conversion gain, 2.0-e- total random noise, 110,000-e- full well capacity and 95-dB dynamic range in one exposure. Moreover, the random noise of the developed readout circuits has been reduced to 0.5-e- without degradation of saturation performance. As a result, the behaviors of pixel noises have been accurately measured. Operating condition dependency of the random noise generated by pixel transistors has been measured by using the developed readout circuits. In addition, considering the result of the measurements, we optimize pixel operating condition.

  11. Design structure for in-system redundant array repair in integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  12. AbstractAn indium-phosphide (InP) double-heterojunction bipolar transistor (DHBT) based suite of terahertz monolithic

    E-print Network

    Rodwell, Mark J. W.

    demonstrate the capability of 256nm InP DHBT technology to enable sophisticated single-chip heterodyne their use in many applications. During the 1970's, the development of the microwave monolithic integrated circuit (MMIC) enabled the implementation of complex transistor-based microwave circuits monolithically

  13. Built-In Testing of Integrated Circuit Wafers

    Microsoft Academic Search

    Sampath Rangarajan; Donald S. Fussell; Miroslaw Malek

    1990-01-01

    Production testing of a digital circuit requires the generation of a sequence of tests and their application to the circuit being tested. Currently, in test application, the output of the circuit under test is compared to a known correct output for each test. The method has some drawbacks likely to become more critical in the near future. In homogeneous systems

  14. Automatic visual inspection of integrated circuits using an SEM

    SciTech Connect

    Kayaalp, A.E.

    1988-01-01

    The author investigates the complex problem of designing an integrated-circuit inspection system that will be used in controlling an automated semiconductor manufacturing facility. To satisfy the accuracy requirements, he proposes a system that integrates information supplied by multiple intelligent (virtual) sensors. Most of his work concentrated on the design of two scanning-electron-microscope (SEM)-based, intelligent sensors. One of them extracts 3D IC surface-topography information using computer stereo-vision techniques, and the other identifies shape defects in IC patterns using the IC design file as the reference. Both of these problems are viewed as constrained contour-matching problems. In stereo matching, feature contours extracted from the left and right stereo images are matched, where in pattern-shape inspection, pattern boundary contours extracted from the image and the IC design file are matched. An optimization technique is presented for solving the matching problem that results in both cases. This general approach simplifies the task of transforming the specifications of a physical problem into a computational form and results in a modular system.

  15. Development of microwave and millimeter-wave integrated-circuit stepped-frequency radar sensors for surface and subsurface profiling 

    E-print Network

    Park, Joongsuk

    2005-02-17

    Two new stepped-frequency continuous wave (SFCW) radar sensor prototypes, based on a coherent super-heterodyne scheme, have been developed using Microwave Integrated Circuits (MICs) and Monolithic Millimeter-Wave Integrated Circuits (MMICs...

  16. Development of microwave and millimeter-wave integrated-circuit stepped-frequency radar sensors for surface and subsurface profiling

    E-print Network

    Park, Joongsuk

    2005-02-17

    Two new stepped-frequency continuous wave (SFCW) radar sensor prototypes, based on a coherent super-heterodyne scheme, have been developed using Microwave Integrated Circuits (MICs) and Monolithic Millimeter-Wave Integrated Circuits (MMICs...

  17. Ambipolar operation of hybrid SiC-carbon nanotube based thin film transistors for logic circuits applications

    E-print Network

    on the ambipolar operation of back-gated thin film field-effect transistors based on hybrid n switching units suggested to date as TFT, single-walled carbon nanotubes (SWNT) are an exem- plary case due-oxide-semiconductor (CMOS) architecture is preferred because it has lower power consumption compared with other logic

  18. Reliability issues in power and ground on submicron circuits

    SciTech Connect

    Tuan, J.F.; Young, T.K. [EPIC Design Technology, Inc., Santa Clara, CA (United States)

    1995-12-31

    The reliability of the power supply network is becoming an important issue for IC designers as circuit sizes increase. The reliability problems in power networks are electromigration, voltage drop, and ground bounce. RailMill is an integrated environment that addresses the power network reliability problems. RailMill covers four important aspects in power network analysis: accurate extraction of power networks, accurate simulation of transistor circuits, accurate simulation of power networks and layout display of circuit and simulation results.

  19. High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.

    2002-01-01

    Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

  20. Abstract--In this paper we present an integrated circuit designed for PMT pulse processing. This circuit was developed

    E-print Network

    Paris-Sud XI, Université de

    . For power consumption consideration we used a CMOS technology. This technology is known to have a large. This circuit was developed for the RICH detector of the AMS experiment. It integrates 16 identical channels and has to deal with space environment constraints (low power consumption, radiation hardness

  1. PAMM Proc. Appl. Math. Mech. 11, 783 784 (2011) / DOI 10.1002/pamm.201110380 Variational integrators for electric circuits

    E-print Network

    Ober-Blöbaum, Sina

    2011-01-01

    integrators for electric circuits Sina Ober-Blöbaum1, , Molei Tao2, , and Houman Owhadi2, 1 Computational of mechanical systems. In this work, we develop a variational integrator for the simulation of electric circuits for the simulation of the electric circuit. In this way, a variational integrator is constructed that gains several

  2. Design of micro-ring optical sensors and circuits for integration on optical printed circuit boards (O-PCBs)

    Microsoft Academic Search

    El-Hang Lee; Hyun S. Lee; S. G. Lee; B. H. O; S. G. Park; K. H. Kim

    2007-01-01

    We report on the design of micro-ring resonator optical sensors for integration on what we call optical printed circuit boards (O-PCBs). The objective is to realize application-specific O-PCBs, either on hard board or on flexible board, by integrating micro\\/nano-scale optical sensors for compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly processing of information. The O-PCBs consist of two-dimensional planar arrays

  3. Laser Micromachining of Active and Passive Photonic Integrated Circuits

    E-print Network

    Cho, Seong-Ho

    2006-06-28

    This thesis describes the development of advanced laser resonators and applications of laserinduced micromachining for photonic circuit fabrication. Two major advantages of laserinduced micromachining are direct patterning ...

  4. Review and Analysis of the Radiation-Induced Degradation Observed for the Input Bias Current of Linear Integrated Circuits

    Microsoft Academic Search

    Laurent Dusseau; Muriel Bernard; Jérôme Boch; Yago Gonzalez Velo; Nicolas Roche; Eric Lorfevre; Françoise Bezerra; Philippe Calvel; Ronan Marec; Frédéric Saigne

    2008-01-01

    It is shown that the variety of shapes of the input current versus dose curve observed in several ICs is due to circuit effects, depending on the architecture, the value of the currents and the bias conditions. When stages are cascaded, the degradation of the second stage may add or subtract current to the collector current of the input transistor.

  5. PETRIC - A positron emission tomography readout integrated circuit

    SciTech Connect

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  6. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  7. Physics and technology development of single-crystal thin-film silicon-on-insulator (TFSOI) CMOS integrated circuits

    SciTech Connect

    Velo, L.A.

    1991-01-01

    Design and fabrication of very-large-scale-integration (VLSI) devices and circuits has seen an enormous improvement in the last decade. The major contributing factors have been the advances in fabrication processes, the reduction in device dimensions, and the increasing support from computer-aided-design (CAD) tools. As one embarks on ultra-large-scale-integration (ULSI), size-reduction techniques fail to provide the increased packing density required, and the performance limitations of conventional VLSI planar technology become salient. Thin-film (TF) MOS silicon-on-insulator (SOI) technology offers the possibility of integrating devices of superior performance to conventional bulk MOS transistors. Analysis leads to the design and optimization of TF SOI devices. This work presents the physics and development of an SOI technology based on Epitaxial-Lateral-Overgrowth (ELO) of silicon. Contrary to previous approaches, this technology provides a tool to fabricate devices in high-quality monocrystalline silicon with process parameters that can be modified to attain an optimal device architecture.

  8. Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)

    NASA Astrophysics Data System (ADS)

    Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

    2000-03-01

    Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this technique are a reduction in reagents, higher sensitivity, minimal preparation of complex samples such as blood, real-time calibration, and extremely rapid analysis.

  9. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 1, JANUARY 2007 123 A Low-Power Integrated Circuit for a Wireless

    E-print Network

    Harrison, Reid R.

    Circuit for a Wireless 100-Electrode Neural Recording System Reid R. Harrison, Member, IEEE, Paul T a prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array. The design of both the system-level architecture and the individual circuits were driven by severe power

  10. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 1775 Transforming Cyclic Circuits Into

    E-print Network

    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 1775 Transforming Cyclic Circuits Into Acyclic Equivalents Osama Neiroukh, Stephen A. Edwards tools can intro- duce unwanted cycles in digital circuits, and for certain com- binational functions

  11. 436 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 3, MARCH 2008 Quantum Circuit Simplification and

    E-print Network

    Miller, D. Michael

    436 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 3, MARCH 2008 Quantum Circuit Simplification and Level Compaction Dmitri Maslov, Gerhard W. Dueck, Member, IEEE, D. Michael Miller, Member, IEEE, and Camille Negrevergne Abstract--Quantum circuits are time

  12. Low-voltage polymer/small-molecule blend organic thin-film transistors and circuits fabricated via spray deposition

    NASA Astrophysics Data System (ADS)

    Hunter, By Simon; Ward, Jeremy W.; Payne, Marcia M.; Anthony, John E.; Jurchescu, Oana D.; Anthopoulos, Thomas D.

    2015-06-01

    Organic thin-film electronics have long been considered an enticing candidate in achieving high-throughput manufacturing of low-power ubiquitous electronics. However, to achieve this goal, more work is required to reduce operating voltages and develop suitable mass-manufacture techniques. Here, we demonstrate low-voltage spray-cast organic thin-film transistors based on a semiconductor blend of 2,8-difluoro- 5,11-bis (triethylsilylethynyl) anthradithiophene and poly(triarylamine). Both semiconductor and dielectric films are deposited via successive spray deposition in ambient conditions (air with 40%-60% relative humidity) without any special precautions. Despite the simplicity of the deposition method, p-channel transistors with hole mobilities of >1 cm2/Vs are realized at -4 V operation, and unipolar inverters operating at -6 V are demonstrated.

  13. Integrated Regulation for Energy-Efficient Digital Circuits

    Microsoft Academic Search

    Elad Alon; Mark Horowitz

    2008-01-01

    Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective supply impedance of digital circuits without increasing their total power dissipation. Achieving this

  14. Low voltage pentacene OTFT integration for smart sensor control circuits

    Microsoft Academic Search

    Prashanth S. Kumar; Pratyush Rai; Gyanesh N. Mathur; Vijay K. Varadan

    2010-01-01

    The past decade has witnessed remarkable progress in Organic electronics and Organic sensor technology on flexible substrates. Temperature and strain sensors for wireless active health monitoring systems have been tested and demonstrated. These sensors need control circuits to condition and transmit the measurand to the data acquisition system. The control circuits have to be incorporated on to the same substrate

  15. Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics

    E-print Network

    Chung, Jinwook W. (Jinwook Will)

    2011-01-01

    In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. ...

  16. Evolutionary Technique for Automated Synthesis of Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

    2007-01-01

    An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

  17. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1 On-Chip Noise Sensor for Integrated Circuit

    E-print Network

    Boyer, Edmond

    induced by circuit activity is limited by the bandwidth of CMOS analog buffer and electrical parasitic to characterize accurately and solve power integrity, simultaneous switching noise, ground bounce, crosstalk be classified into two families: the on-chip waveform capturing circuits and the noise detectors. Most on- chip

  18. The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions

    Microsoft Academic Search

    C. H. Stapper

    1985-01-01

    A method for modeling the variations in defect levels in circuits produced on modern integrated circuit manufacturing lines is described in this paper. The effects on defect and fault distributions are derived. A deficiency in some previous yield models is eliminated.

  19. Few-electron quantum dot circuit with integrated charge read out J. M. Elzerman,1

    E-print Network

    Few-electron quantum dot circuit with integrated charge read out J. M. Elzerman,1 R. Hanson,1 J. S circuit containing just a single conduction electron. Few-electron quantum dots have been realized in self-0033, Japan Received 6 February 2003; published 30 April 2003 We report on the realization of a few-electron

  20. A New CMOS Integrable Oscillating Circuit for High-Value Wide-Range Resistive Sensors

    Microsoft Academic Search

    A. Depari; A. Flamminil; D. Mariolil; A. Taronil; A. De Marcellis; G. Ferri; V. Stornelli

    2007-01-01

    A new oscillating circuit is proposed to estimate resistance and parallel parasitic capacitance of chemical sensors. The circuit is able to reveal resistance in a wide range, from tens of k Omega to over than 100 G Omega. Experimental results of a discrete board prototype confirm the very good performance of post-layout simulation tests concerning the CMOS integrated implementation.