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Sample records for transistor integrated circuit

  1. Radiation-hardened transistor and integrated circuit

    DOEpatents

    Ma, Kwok K. (Albuquerque, NM)

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  2. From The Lab to The Fab: Transistors to Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.

    2003-09-01

    Transistor action was experimentally observed by John Bardeen and Walter Brattain in n-type polycrystalline germanium on December 16, 1947 (and subsequently polycrystalline silicon) as a result of the judicious placement of gold-plated probe tips in nearby single crystal grains of the polycrystalline material (i.e., the point-contact semiconductor amplifier, often referred to as the point-contact transistor).The device configuration exploited the inversion layer as the channel through which most of the emitted (minority) carriers were transported from the emitter to the collector. The point-contact transistor was manufactured for ten years starting in 1951 by the Western Electric Division of AT&T. The a priori tuning of the point-contact transistor parameters, however, was not simple inasmuch as the device was dependent on the detailed surface structure and, therefore, very sensitive to humidity and temperature as well as exhibiting high noise levels. Accordingly, the devices differed significantly in their characteristics and electrical instabilities leading to "burnout" were not uncommon. With the implementation of crystalline semiconductor materials in the early 1950s, however, p-n junction (bulk) transistors began replacing the point-contact transistor, silicon began replacing germanium and the transfer of transistor technology from the lab to the lab accelerated. We shall review the historical route by which single crystalline materials were developed and the accompanying methodologies of transistor fabrication, leading to the onset of the Integrated Circuit (IC) era. Finally, highlights of the early years of the IC era will be reviewed from the 256 bit through the 4M DRAM. Elements of IC scaling and the role of Moore's Law in setting the parameters by which the IC industry's growth was monitored will be discussed.

  3. Printed organic thin-film transistor-based integrated circuits

    NASA Astrophysics Data System (ADS)

    Mandal, Saumen; Noh, Yong-Young

    2015-06-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted.

  4. Technology for LSI circuits combining integrated injection logic and bipolar transistors

    NASA Astrophysics Data System (ADS)

    Clauss, H.

    1983-10-01

    Large scale integrated circuits combining integrated injection logic (I2L) and bipolar circuits are described. By shrinking the lateral dimensions of the I2L-gates the packing density is increased from 230 to 640 gates/sqmm. Some I2L-Logic and bipolar transistors with breakdown voltage 30 V were combined. For compact integrated circuits a gate array with 700 I2L-gates and bipolar periphery circuits was developed and tested. For short time realization of special mask designs a computer assisted design system was prepared. A high speed I2L allows 6 nsec delay time. The speed power product is 0,1 pJ at low currents and 0,5 pJ at 10 nsec delay. The packing density is 900 gates/sqmm.

  5. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

  6. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

  7. Development of high-performance printed organic field-effect transistors and integrated circuits.

    PubMed

    Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

    2015-10-01

    Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications. PMID:25057765

  8. High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

    E-print Network

    Seo, Kwang Seok

    ) integration technology on an InP substrate. The number of devices of the proposed D-F/F circuit is reducedHigh-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology Hyungtae KIM Ã , Seongjin YEON

  9. Improved chopper circuit uses parallel transistors

    NASA Technical Reports Server (NTRS)

    1966-01-01

    Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage.

  10. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    SciTech Connect

    Liang, Shibo; Zhang, Zhiyong Si, Jia; Zhong, Donglai; Peng, Lian-Mao

    2014-08-11

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2?V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  11. Nanofluidic Transistor Circuits

    NASA Astrophysics Data System (ADS)

    Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti

    2012-02-01

    Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.

  12. Evolvable circuit with transistor-level reconfigurability

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

    2004-01-01

    An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

  13. Study and fabrication of AlGaAs/GaAs double heterojunction bipolar transistors for integrated injection logic circuits

    NASA Astrophysics Data System (ADS)

    Jamai, Jamal

    The operating conditions of integrated injection logic are recalled and the advantages resulting from the use of AlGaAs/GaAs double heterojunction bipolar transistors are summarized. The realization of samples by molecular beam epitaxy and ionic implantation is described, emphasizing the realization conditions used to meet the structure requirements. Electric characterization identified the physical mechanisms accounting for operation limitations. The correlation observed between the behavior of the direct and reverse operations confirms the importance of conduction and that of parasitic charge storage in the collector-base diode. The best performances obtained, highlighting maximum current gains of 500 in forward operation and 100 in reverse operation and an offset voltage as low as 3 mW, show that the properties of the realized epitaxial structures should match the operation of the projected test integrated circuits.

  14. A spiking neuron circuit based on a carbon nanotube transistor.

    PubMed

    Chen, C-L; Kim, K; Truong, Q; Shen, A; Li, Z; Chen, Y

    2012-07-11

    A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a 'soma' circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions. PMID:22710137

  15. Complementary GaAs junction-gated heterostructure field effect transistor fabrication for integrated circuits

    SciTech Connect

    Baca, A.G.; Zolper, J.C.; Sherwin, M.E.; Robertson, P.J.; Shul, R.J.; Howard, A.J.; Rieger, D.J.; Klem, J.F.

    1994-10-01

    A new GaAs junction-gated complementary logic technology that integrates a modulation doped p-channel heterostructure field effect transistor (pHFET) and a fully ion implanted n-channel JFET has recently been fabricated. High-speed, low-power operation has been demonstrated with loaded ring oscillators that show gate delays of 179 ps/stage for a power-delay product of 28 fJ at 1.2 V operation and 320 ps/stage and 8.9 fJ at 0.8 V operation. The principal advantages of this technology include the ability to independently set the threshold voltage of n- and p-channel devices and to independently design the pHFET for high performance. A self-aligned refractory gate process based on tungsten and tungsten silicide gate metal has been used to fabricate the FETs. Novel aspects of the fabrication include the simultaneous formation of non-alloyed, refractory ohmic contacts for the junction gates and the formation of shallow p-n junctions by ion implantation.

  16. Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Blalock, Benjamin J; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  17. Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits

    E-print Network

    Rubloff, Gary W.

    Monte Carlo Reliability Model for Microwave Monolithic Integrated Circuits Aris Christou Materials Carlo simulation is reported for analog integrated circuits and is based on the modification behavior of MMICs (Monolithic Microwave Integrated Circuits) from individual FET (Field Effect Transistor

  18. Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

    NASA Astrophysics Data System (ADS)

    Petti, Luisa; Faber, Hendrik; Münzenrieder, Niko; Cantarella, Giuseppe; Patsalas, Panos A.; Tröster, Gerhard; Anthopoulos, Thomas D.

    2015-03-01

    Indium oxide (In2O3) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm2V-1s-1 and 16 cm2V-1s-1 for coplanar and staggered architectures, respectively. Integration of In2O3 transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (?250 °C) of In2O3 also allowed transistor fabrication on free-standing 50 ?m-thick polyimide foils. The resulting flexible In2O3 transistors exhibit good characteristics and remain fully functional even when bent to tensile radii of 4 mm.

  19. A comparative study of plasma-enhanced chemical vapor gate dielectrics for solution-processed polymer thin-film transistor circuit integration

    NASA Astrophysics Data System (ADS)

    Li, Flora M.; Nathan, Arokia; Wu, Yiliang; Ong, Beng S.

    2008-12-01

    This paper considers plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) and silicon oxide (SiOx) as gate dielectrics for organic thin-film transistors (OTFTs), with solution-processed poly[5,5'-bis(3-dodecyl-2-thienyl)-2,2'-bithiophene] (PQT-12) as the active semiconductor layer. We examine transistors with SiNx films of varying composition deposited at 300 °C as well as 150 °C for plastic compatibility. The transistors show over 100% (two times) improvement in field-effect mobility as the silicon content in SiNx increases, with mobility (?FE) up to 0.14 cm2/V s and on/off current ratio (ION/IOFF) of 108. With PECVD SiOx gate dielectric, preliminary devices exhibit a ?FE of 0.4 cm2/V s and ION/IOFF of 108. PQT-12 OTFTs with PECVD SiNx and SiOx gate dielectrics on flexible plastic substrates are also presented. These results demonstrate the viability of using PECVD SiNx and SiOx as gate dielectrics for OTFT circuit integration, where the low temperature and large area deposition capabilities of PECVD films are highly amenable to integration of OTFT circuits targeted for flexible and lightweight applications.

  20. Integrated circuit with multiple collector current source

    NASA Technical Reports Server (NTRS)

    Hellstrom, M. J.; Lin, H. C.

    1969-01-01

    Integrated circuit with multiple collector current source achieves the equivalent of a large number of resistors in a small area. Functional equivalents of a transistor reduce the size requirement for low power integrated circuits, providing an efficient alternative to the conventional diffused resistor process in integrated circuit fabrication.

  1. Pass-transistor very large scale integration

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Bhatia, Prakash R. (Inventor)

    2004-01-01

    Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements.

  2. Growth of a single-wall carbon nanotube film and its patterning as an n-type field effect transistor device using an integrated circuit compatible process.

    PubMed

    Shiau, S H; Liu, C W; Gau, C; Dai, B T

    2008-03-12

    This study presents the synthesis of a dense single-wall carbon nanotube (SWNT) network on a silicon substrate using alcohol as the source gas. The nanosize catalysts required are made by the reduction of metal compounds in ethanol. The key point in spreading the nanoparticles on the substrate, so that the SWNT network can be grown over the entire wafer, is making the substrate surface hydrophilic. This SWNT network is so dense that it can be treated like a thin film. Methods of patterning this SWNT film with integrated circuit compatible processes are presented and discussed for the first time in the literature. Finally, fabrication and characteristic measurements of a field effect transistor (FET) using this SWNT film are also demonstrated. This FET is shown to have better electronic properties than any other kind of thin film transistor. This thin film with good electronic properties can be readily applied in the processing of many other SWNT electronic devices. PMID:21817696

  3. Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

    SciTech Connect

    Petti, Luisa; Faber, Hendrik; Anthopoulos, Thomas D.; Münzenrieder, Niko; Cantarella, Giuseppe; Tröster, Gerhard; Patsalas, Panos A.

    2015-03-02

    Indium oxide (In{sub 2}O{sub 3}) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1?cm{sup 2}V{sup ?1}s{sup ?1} and 16?cm{sup 2}V{sup ?1}s{sup ?1} for coplanar and staggered architectures, respectively. Integration of In{sub 2}O{sub 3} transistors enabled realization of unipolar inverters with high gain (5.3?V/V) and low-voltage operation. The low temperature deposition (?250?°C) of In{sub 2}O{sub 3} also allowed transistor fabrication on free-standing 50??m-thick polyimide foils. The resulting flexible In{sub 2}O{sub 3} transistors exhibit good characteristics and remain fully functional even when bent to tensile radii of 4?mm.

  4. Thermionic integrated circuits

    SciTech Connect

    MacRoberts, M.; Brown, D.R.; Dooley, R.; Lemons, R.; Lynn, D.; McCormick, B.; Mombourquette, C.; Sinah, D.

    1986-01-01

    Thermionic integrated circuits combine vacuum-tube technology with integrated-circuit techniques to form integrated vacuum circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

  5. MOS integrated circuit fault modeling

    NASA Technical Reports Server (NTRS)

    Sievers, M.

    1985-01-01

    Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.

  6. Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and DesignDesign --Lecture 4Lecture 4

    E-print Network

    Lake, Roger

    EE134 1 Digital Integrated Circuit (IC) Layout andDigital Integrated Circuit (IC) Layout and Design's Lecture ! MOS manufacturing process ! Design rules ! Layout and Design ! Ties to VDD and GND ! Padframes--Isolated CMOS ProcessIsolated CMOS Process silicide layer on poly #12;EE134 7 Transistor LayoutTransistor Layout

  7. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. XX, XX 2013 1 Stochastic Testing Method for Transistor-Level

    E-print Network

    Reif, Rafael

    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. XX, XX--Uncertainties have become a major concern in integrated circuit design. In order to avoid the huge number of repeated concern in today's nanometer integrated circuit design [1]. It is well known that the uncertainties

  8. Displacement Damage in Bipolar Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  9. Macroelectronic Integrated Circuits Using High-Performance Separated

    E-print Network

    Zhou, Chongwu

    Macroelectronic Integrated Circuits Using High-Performance Separated Carbon Nanotube Thin- strate ballistic and high mobility transistors6 8 and integrated logic circuits such as inverters devices and integrated circuits.16,19,21 Nevertheless, the mainstream nanotube TFT approach men- tioned

  10. Transistor Level Circuit Experiments using Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

    2005-01-01

    The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

  11. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

    E-print Network

    Rogers, John A.

    LETTERS Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates , Kaushik Roy7 , Muhammad A. Alam7 & John A. Rogers1­6 The ability to form integrated circuits on flexible-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors

  12. Sizing and Placement of Charge Recycling Transistors in MTCMOS Circuits

    E-print Network

    Pedram, Massoud

    Sizing and Placement of Charge Recycling Transistors in MTCMOS Circuits Ehsan Pakbaznia Dep transitions between sleep and active modes. Previously, a charge recycling (CR) MTCMOS architecture and placement of charge- recycling transistors is key to achieving the maximum power saving. In this paper, we

  13. 378 INTEGRATED CIRCUIT SIGNAL DELAY INTEGRATED CIRCUIT SIGNAL DELAY

    E-print Network

    Friedman, Eby G.

    378 INTEGRATED CIRCUIT SIGNAL DELAY INTEGRATED CIRCUIT SIGNAL DELAY Technologies for designing commercial discrete circuits (ICs) were in- troduced in the late 1950s (1) (monolithic integrated circuits were introduced in the 1960s). As predicted by Moore's law in the 1960s (2), integrated-circuit density

  14. Problem Set: Transistors and transistor circuits 1. In terms of Boolean logic, what is ground (Vss) equivalent to?

    E-print Network

    Estrada, Francisco

    Problem Set: Transistors and transistor circuits 1. In terms of Boolean logic, what is ground (Vss) equivalent to? 2. Is the control terminal in the transistor electrically connected to either of the two remaining terminals? 3. If the control terminal is connected to Vdd, is the transistor considered open

  15. A general method in synthesis of pass-transistor circuits D. Markovica,*, B. Nikolicb

    E-print Network

    Zakhor, Avideh

    A general method in synthesis of pass-transistor circuits D. Markovic´a,*, B. Nikolic´b , V in different pass-transistor network topologies is analyzed. Several pass-transistor logic families have been be used to efficiently synthesize pass- transistor logic circuits, which have balanced loads on true

  16. A "Single-Photon" Transistor in Circuit Quantum Electrodynamics

    E-print Network

    Lukas Neumeier; Martin Leib; Michael J. Hartmann

    2013-07-26

    We introduce a circuit quantum electrodynamical setup for a "single-photon" transistor. In our approach photons propagate in two open transmission lines that are coupled via two interacting transmon qubits. The interaction is such that no photons are exchanged between the two transmission lines but a single photon in one line can completely block respectively enable the propagation of photons in the other line. High on-off ratios can be achieved for feasible experimental parameters. Our approach is inherently scalable as all photon pulses can have the same pulse shape and carrier frequency such that output signals of one transistor can be input signals for a consecutive transistor.

  17. Integration of pentacene-based thin film transistors via photolithography for low and high voltage applications

    E-print Network

    Smith, Melissa Alyson

    2012-01-01

    An organic thin film transistor (OTFT) technology platform has been developed for flexible integrated circuits applications. OTFT performance is tuned by engineering the dielectric constant of the gate insulator and the ...

  18. An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization

    E-print Network

    Sapatnekar, Sachin

    An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization topology, the delay can be controlled by varying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit

  19. Microwave Enginering Microwave Integrated Circuits

    E-print Network

    Iqbal, Sheikh Sharif

    EE 407 Microwave Enginering Microwave Integrated Circuits Dr. Sheikh Sharif Iqbal Lecture 27-28 #12;Microwave Integrated Circuits (MIC's): ·There are three types of circuit elements that either are used: · Hybrid Microwave Integrated Circuits (HMICs): where solid state devices and passive elements (both lumped

  20. GaAs Optoelectronic Integrated-Circuit Neurons

    NASA Technical Reports Server (NTRS)

    Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

    1992-01-01

    Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

  1. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 5, MAY 2001 693 Buffer Minimization in Pass Transistor Logic

    E-print Network

    Zhou, Hai

    2001 693 Buffer Minimization in Pass Transistor Logic Hai Zhou and Adnan Aziz Abstract--With shrinking feature sizes and increasing transistor counts on chips, demands for higher speed and lower power make metal­oxide­semiconductors. Among them, pass transistor logic (PTL) is of great promise. Since delay

  2. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (inventor); Sayah, Hoshyar R. (inventor)

    1988-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  3. Bioluminescent bioreporter integrated circuit

    DOEpatents

    Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  4. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1990-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  5. Rapid evolution of analog circuits configured on a field programmable transistor array

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

    2002-01-01

    The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

  6. Unipolar sequential circuits based on individual-carbon-nanotube transistors and thin-film carbon resistors.

    PubMed

    Ryu, Hyeyeon; Kälblein, Daniel; Schmidt, Oliver G; Klauk, Hagen

    2011-09-27

    A fabrication process for the monolithic integration of field-effect transistors based on individual carbon nanotubes and load resistors based on vacuum-evaporated carbon films into fast unipolar logic circuits on glass substrates is reported for the first time. The individual-carbon-nanotube transistors operate with relatively small gate-source and drain-source voltages of 1 V and combine large transconductance (up to 6 ?S), large ON/OFF ratio (>10(4)), and short switching delay time constants (12 ns). The thin-film carbon load resistors provide linear current-voltage characteristics and resistances between 300 k? and 100 M?, depending on the layout of the resistors and the thickness of the vacuum-evaporated carbon films. Various combinational circuits (NAND, NOR, AND, OR gates) as well as a sequential circuit ( ?S ?R NAND latch) have been fabricated and characterized. Although these unipolar circuits cannot compete with optimized complementary circuits in terms of integration density and static power consumption, they offer the possibility of realizing air-stable, low-voltage integrated circuits with promising static and dynamic performance on unconventional substrates for large-area electronics applications, such as displays or sensors. PMID:21870841

  7. Transistor Sizing of Energy-DelayEfficient Circuits Paul I. Penzes, Mika Nystrom, Alain J. Martin

    E-print Network

    Transistor Sizing of Energy-Delay­Efficient Circuits Paul I. P´enzes, Mika Nystr¨om, Alain J,mika,alain¡ @async.caltech.edu Abstract This paper studies the problem of transistor sizing of CMOS circuits transistor sizes. We then study an efficient iteration procedure that can further improve the original

  8. Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis

    E-print Network

    Bryant, Randal E.

    Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis Randal E-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones

  9. Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

    2008-01-01

    There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

  10. Monolithic Optoelectronic Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Walters, Wayne; Gustafsen, Jerry; Bendett, Mark

    1990-01-01

    Monolithic optoelectronic integrated circuit (OEIC) receives single digitally modulated input light signal via optical fiber and converts it into 16-channel electrical output signal. Potentially useful in any system in which digital data must be transmitted serially at high rates, then decoded into and used in parallel format at destination. Applications include transmission and decoding of control signals to phase shifters in phased-array antennas and also communication of data between computers and peripheral equipment in local-area networks.

  11. Integrated Circuit Immunity

    NASA Technical Reports Server (NTRS)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  12. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  13. Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

    PubMed

    Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

    2015-03-11

    High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles. PMID:25715122

  14. Four-gate transistor analog multiplier circuit

    NASA Technical Reports Server (NTRS)

    Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

    2011-01-01

    A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

  15. SiC JFET Transistor Circuit Model for Extreme Temperature Range

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.

    2008-01-01

    A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

  16. Integration of Cell Membranes and Nanotube Transistors

    E-print Network

    Gruner, George

    as transistors, and that the two systems interact. Further, we use the interaction to study the charge, while biological systems ranging from lipids7 to living cells2 have been assembled on nanotube Manuscript Received March 23, 2005 ABSTRACT We report the integration of a complex biological system

  17. Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint

    E-print Network

    He, Lei

    Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint Manjit University Park, PA 16802 Mary Jane Irwin Abstract We consider the problem of transistor sizing in a static that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption

  18. Nanowire transistor arrays for mapping neural circuits in acute brain slices

    E-print Network

    Xie, Xiaoliang Sunney

    Nanowire transistor arrays for mapping neural circuits in acute brain slices Quan Qinga,1 , Sumon K, we show that silicon nanowire field-effect transistor (Si NWFET) arrays fabricated on transparent-density passive multielectrode arrays (MEAs) (2) and active transistor arrays on silicon substrates (3) enable

  19. Photonic integrated circuits for optical logic applications

    E-print Network

    Williams, Ryan Daniel

    2007-01-01

    The optical logic unit cell is the photonic analog to transistor-transistor logic in electronic devices. Active devices such as InP-based semiconductor optical amplifiers (SOA) emitting at 1550 nm are vertically integrated ...

  20. Integrated coherent matter wave circuits

    E-print Network

    C. Ryu; M. G. Boshier

    2015-10-20

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. Here we report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly-moving, tightly-focused laser beam exerts forces on atoms through their electric polarizability. The source of coherent matter waves is a Bose-Einstein condensate (BEC). We launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.

  1. Integrated coherent matter wave circuits

    NASA Astrophysics Data System (ADS)

    Ryu, C.; Boshier, M. G.

    2015-09-01

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. Here we report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. The source of coherent matter waves is a Bose-Einstein condensate (BEC). We launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.

  2. Transistor Sizing of EnergyDelay--Efficient Circuits Paul I. P

    E-print Network

    Martin, Alain

    consumption, and today, there are still no alternatives that approach it in energy e#ciency. NeverthelessTransistor Sizing of Energy­Delay--Efficient Circuits Paul I. P â?? enzes, Mika Nystr Ë? om, Alain J,mika,alain}@async.caltech.edu ABSTRACT This paper studies the problem of transistor sizing of CMOS circuits optimized for energy­delay e

  3. Recent progress on ZnO-based metal-semiconductor field-effect transistors and their application in transparent integrated circuits.

    PubMed

    Frenzel, Heiko; Lajn, Alexander; von Wenckstern, Holger; Lorenz, Michael; Schein, Friedrich; Zhang, Zhipeng; Grundmann, Marius

    2010-12-14

    Metal-semiconductor field-effect transistors (MESFETs) are widely known from opaque high-speed GaAs or high-power SiC and GaN technology. For the emerging field of transparent electronics, only metal-insulator-semiconductor field-effect transistors (MISFETs) were considered so far. This article reviews the progress of high-performance MESFETs in oxide electronics and reflects the recent advances of this technique towards transparent MESFET circuitry. We discuss design prospects as well as limitations regarding device performance, reliability and stability. The presented ZnO-based MESFETs and inverters have superior properties compared to MISFETs, i.e., high channel mobilities and on/off-ratios, high gain, and low uncertainty level at comparatively low operating voltages. This makes them a promising approach for future low-cost transparent electronics. PMID:20878625

  4. Vertically Integrated Multiple Nanowire Field Effect Transistor.

    PubMed

    Lee, Byung-Hyun; Kang, Min-Ho; Ahn, Dae-Chul; Park, Jun-Young; Bang, Tewook; Jeon, Seung-Bae; Hur, Jae; Lee, Dongil; Choi, Yang-Kyu

    2015-12-01

    A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling. PMID:26544156

  5. A hybrid nanomemristor/transistor logic circuit capable of self-programming

    PubMed Central

    Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

    2009-01-01

    Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

  6. Analog Integrated Circuits and Signal Processing, 21, 7990 (1999) # 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

    E-print Network

    Serdijn, Wouter A.

    1999-01-01

    Analog Integrated Circuits and Signal Processing, 21, 79±90 (1999) # 1999 Kluwer Academic circuit uses only bipolar transistors and one capacitor and is, therefore, very well suited for integrated circuit. The translinear integrator operates from a single supply voltage down to 0.95 V. The current

  7. Circuit Theory for Analysis and Design of Spintronic Integrated Circuits

    E-print Network

    Manipatruni, Sasikanth; Young, Ian A

    2011-01-01

    We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The proposed formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We derive the circuit models for vector spin conduction in non-magnetic and magnetic components. We then propose an extension to the modified nodal analysis for the analysis of spin circuits. We demonstrate the applicability of the proposed theory using an example spin logic circuit.

  8. Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits

    NASA Astrophysics Data System (ADS)

    Gu, Jian

    This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of ?hin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

  9. Variational integrators for electric circuits

    SciTech Connect

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.; Applied and Computational Mathematics, California Institute of Technology

    2013-06-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

  10. Transistorized Marx bank pulse circuit provides voltage multiplication with nanosecond rise-time

    NASA Technical Reports Server (NTRS)

    Jung, E. A.; Lewis, R. N.

    1968-01-01

    Base-triggered avalanche transistor circuit used in a Marx bank pulser configuration provides voltage multiplication with nanosecond rise-time. The avalanche-mode transistors replace conventional spark gaps in the Marx bank. The delay time from an input signal to the output signal to the output is typically 6 nanoseconds.

  11. Water-Soluble Thin Film Transistors and Circuits Based on Amorphous Indium-Gallium-Zinc Oxide

    E-print Network

    Rogers, John A.

    Water-Soluble Thin Film Transistors and Circuits Based on Amorphous Indium-Gallium-Zinc Oxide Sung for amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) comprised completely of water. INTRODUCTION Research in recent years has established amorphous indium- gallium-zinc oxide (a

  12. Logic and transistor circuit verification using regression testing and hierarchical recursive learning 

    E-print Network

    Shao, Li

    1996-01-01

    We describe a new approach for formal verification of combinational logic circuits, and their switch-level transistor implementation. Our approach CODibines regression testing, hierarchical recursive learning, and test generation techniques. A...

  13. Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

    NASA Technical Reports Server (NTRS)

    Johnston, Allan H.; Rax, Bernard G.

    2006-01-01

    This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

  14. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    NASA Technical Reports Server (NTRS)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  15. Low-power integrated-circuit driver for ferrite-memory word lines

    NASA Technical Reports Server (NTRS)

    Katz, S.

    1970-01-01

    Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

  16. Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

    NASA Technical Reports Server (NTRS)

    Mclyman, W. T. (inventor)

    1981-01-01

    In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

  17. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  18. Modeling of single-event upset in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1983-01-01

    The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

  19. Self-integration of nanowires into circuits via guided growth

    PubMed Central

    Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

    2013-01-01

    The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom–up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel “self-integration” of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

  20. Yield learning model for integrated circuit package 

    E-print Network

    Balasubramaniam, Gaurishankar

    1996-01-01

    In a semiconductor industry, packaging of integrated circuit chips, product quality control and rapid problem diagnosis are very critical to economic success. The integrated circuit package makes up a large fraction of the total production cost...

  1. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  2. Cramming More Components onto Integrated Circuits

    E-print Network

    Mignotte, Max

    Cramming More Components onto Integrated Circuits GORDON E. MOORE, LIFE FELLOW, IEEE With unit cost this science into many new areas. Integrated circuits will lead to such wonders as home computers--or at least potential lies in the production of large systems. In telephone communications, integrated circuits

  3. Integrated Circuit / Microfluidic Chips for Dielectric Manipulation

    E-print Network

    Integrated Circuit / Microfluidic Chips for Dielectric Manipulation A THESIS PRESENTED BY THOMAS by Thomas Hunt All rights reserved. #12;iii Abstract Integrated Circuit / Microfluidic Chips for Dielectric of integrated circuit / microfluidic chips to move individual living cells and chemical droplets along

  4. Integrated circuits, and design and manufacture thereof

    SciTech Connect

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  5. Microfluidic Photonic Integrated Circuits

    PubMed Central

    Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S.; Lo, Yu-Hwa

    2010-01-01

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled two-dimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1–10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments. PMID:20428483

  6. Microfluidic Photonic Integrated Circuits.

    PubMed

    Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S; Lo, Yu-Hwa

    2008-11-18

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled two-dimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1-10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments. PMID:20428483

  7. High-performance organic transistors for printed circuits

    NASA Astrophysics Data System (ADS)

    Takeya, J.

    2014-10-01

    This presentation focuses on recent development of key technologies for printed LSIs which can provide future low-cost platforms for RFID tags, AD converters, data processors, and sensing circuitries. Such prospect bears increasing reality because of recent research innovations in the field of material chemistry, charge transport physics, and solution processes of printable organic semiconductors. Achieving band transport in state-of-the-art printable organic semiconductors, carrier mobility is elevated above 15 cm2/Vs, so that reasonable speed in moderately integrated logic circuits can be available. With excellent chemical and thermal stability for such compounds, we are developing simple integrated devices based on CMOS using p-type and n-type printed organic FETs. Particularly important are new processing technologies for continuous growth of inch-size organic single-crystalline semiconductor "wafers" from solution and for lithographical patterning of semiconductors and metal electrodes. Successful rectification and identification are demonstrated at 13.56 MHz with printed organic CMOS circuits for the first time.

  8. A miniature microcontroller curve tracing circuit for space flight testing transistors

    NASA Astrophysics Data System (ADS)

    Prokop, N.; Greer, L.; Krasowski, M.; Flatico, J.; Spina, D.

    2015-02-01

    This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

  9. Insulated Gate Bipolar Transistors (IGBT) modelization for circuit simulation and utilization in pulse modulated inverters

    NASA Astrophysics Data System (ADS)

    Behr, Ernst-Karl

    A model is developed for the IGBT, which can be used on components for the simulation of power electronics circuits. The use of IGBT in a typical utilization case is examined, e.g., a quick switching pulse inverter for the control of asynchronous machines. The starting point of IGBT model production is an equivalent circuit from a bipolar transistor and from a controlling field effect transistor. The stationary behavior of the bipolar transistor is described by analytically produced nonlinear equations. Available model equations are collected in a dynamic IGBT model. New and modified processes are developed, with which all relevant IGBT parameters can be obtained by electrical measurements in simple test circuits. The validity of the developed IGBT model is demonstrated, using typical load conditions, by comparison with simulation and measurement results.

  10. Removing Bonded Integrated Circuits From Boards

    NASA Technical Reports Server (NTRS)

    Rice, John T.

    1989-01-01

    Small resistance heater makes it easier, faster, and cheaper to remove integrated circuit from hybrid-circuit board, package, or other substrate for rework. Heater, located directly in polymeric bond interface or on substrate under integrated-circuit chip, energized when necessary to remove chip. Heat generated softens adhesive or solder that bonds chip to substrate. Chip then lifted easily from substrate.

  11. Printed inorganic transistors

    E-print Network

    Ridley, Brent (Brent Alan), 1974-

    2003-01-01

    Forty years of exponential growth of semiconductor technology have been predicated on the miniaturization of the transistors that comprise integrated circuits. While complexity has greatly increased within a given area of ...

  12. VHSIC /very high speed integrated circuits/ - Technologies and tradeoffs

    NASA Astrophysics Data System (ADS)

    Barna, A.

    Very high speed integrated circuits (VHSIC) are large-scale digital integrated circuits with typical logic-gate propagation delays below 1 nanosecond. Bipolar technology was first to enter into this speed range. However, MOS and GaAs technologies are now also available. Attention is given to emitter-coupled logic, integrated injection logic, n-channel MOS logic, complementary MOS logic, depletion-mode GaAs logic, and enhancement-mode GaAs logic. Gate arrays are considered, taking into account the basic structure, capacitances, propagation delays, transistor sizes, and a comparison of propagation delays. Advantages and limitations of custom logic and functional cells are examined, and questions of power dissipation and chip complexity are investigated.

  13. Lithography for enabling advances in integrated circuits and devices.

    PubMed

    Garner, C Michael

    2012-08-28

    Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing. PMID:22802500

  14. SYSTEMATIC SYNTHESIS METHOD FOR ANALOGUE CIRCUITS PART III ALL-TRANSISTOR CIRCUIT SYNTHESIS

    E-print Network

    Papavassiliou, Christos

    by introducing nullors which are equivalent to open- and short-circuits into the initial circuit. Nullors by synthesising the open-circuit and the short-circuit using nullors. We then show how nullor open-circuits and short-circuits may be introduced into a circuit without affecting matrix equivalence. We then apply

  15. Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors

    NASA Astrophysics Data System (ADS)

    Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

    2014-06-01

    Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

  16. Asynchronous sequential circuit design using pass transistor iterative logic arrays

    NASA Technical Reports Server (NTRS)

    Liu, M. N.; Maki, G. K.; Whitaker, S. R.

    1991-01-01

    The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

  17. Effects of Silicides and Device Structure on the Characteristics and Circuit Performance of Poly-Silicon Thin Film Transistors for Active-Matrix Liquid-Crystal Displays.

    NASA Astrophysics Data System (ADS)

    Sarcona, Greg Thomas

    The leading technology in flat panel displays is active matrix addressed displays, with either amorphous or polycrystalline silicon thin film transistors as the pixel switching element. For cost and performance reasons, integration of display driver circuitry onto the display substrate is desirable. This thesis focuses on devices for driver circuitry necessary for AMLCD operation. Circuits to control the data transferred to the pixels are discussed, and their timing constraints determined. The ability of amorphous and polysilicon Thin Film Transistors (TFTs) to meet the needs of the circuits is considered. The characteristics of the devices are examined to determine their utility in driver circuit design. One of the major limitations of thin film transistors is their series resistance, which decreases the output current and slows the circuit response. In this work, self-aligned silicidation has been developed for thin film transistors to reduce the extrinsic resistance. The principles of silicidation are reviewed, and applied towards the development of cobalt and nickel silicide processes on thin polycrystalline and amorphous silicon and silicon-germanium films. The effect of the film on the electrical properties of silicide is studied. Cobalt and nickel silicides are used on the source and drain of polysilicon TFTs, and their effects on the device characteristics are analyzed. Their impact is greatest on ultra-thin film polysilicon devices, where the high series resistance limits the current to about 1 muA. With silicides, the output current is increased one-hundredfold. The improvement in AMLCD driver circuit performance by the incorporation of silicides is shown by circuit simulation. The objective of this dissertation is to develop a silicidation process for polysilicon thin film transistors and determine the effects of this process on device performance, and project the improvements to AMLCD driver circuitry this process may provide.

  18. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Scalable Methods for Analyzing the Circuit Failure

    E-print Network

    Sapatnekar, Sachin

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown Jianxin Fang, and Sachin S. Sapatnekar, Fellow at the individual transistor level, but has seen very little work at the circuit level. We first develop an analytic

  19. Sleep Transistor Sizing According to Circuit Speed, Silicon Area and Leakage Current in High-Performance Digital Circuit Modules

    NASA Astrophysics Data System (ADS)

    Kucukkomurler, Ahmet; Garverick, Steven L.

    It is proposed that the power supply of key circuit modules could be gated to achieve significant reductions of leakage current, with minimal costs to circuit speed and die area in 0.25, 0.18 and 0.07 µm technologies. This study describes an extension to power supply gating using body overdrive and gate underdrive, analysis techniques to predict leakage current and performance parameters, a procedure for optimization of the sleep transistor size and simulation results that demonstrate the accuracy of the analysis and advantages of the approach. A leakage current estimation technique has been studied using the Berkeley Predictive Technology Model Parameters. An estimation technique has been verified using ISCAS85 combinational Benchmark test circuits. Finally the optimization algorithm has been verified using these same benchmark test circuits.

  20. Field Effect Transistor /FET/ circuit for variable gin amplifiers

    NASA Technical Reports Server (NTRS)

    Spaid, G. H.

    1969-01-01

    Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

  1. Diamond-integrated optomechanical circuits.

    PubMed

    Rath, Patrik; Khasminskaya, Svetlana; Nebel, Christoph; Wild, Christoph; Pernice, Wolfram H P

    2013-01-01

    Diamond offers unique material advantages for the realization of micro- and nanomechanical resonators because of its high Young's modulus, compatibility with harsh environments and superior thermal properties. At the same time, the wide electronic bandgap of 5.45 eV makes diamond a suitable material for integrated optics because of broadband transparency and the absence of free-carrier absorption commonly encountered in silicon photonics. Here we take advantage of both to engineer full-scale optomechanical circuits in diamond thin films. We show that polycrystalline diamond films fabricated by chemical vapour deposition provide a convenient wafer-scale substrate for the realization of high-quality nanophotonic devices. Using free-standing nanomechanical resonators embedded in on-chip Mach-Zehnder interferometers, we demonstrate efficient optomechanical transduction via gradient optical forces. Fabricated diamond resonators reproducibly show high mechanical quality factors up to 11,200. Our low cost, wideband, carrier-free photonic circuits hold promise for all-optical sensing and optomechanical signal processing at ultra-high frequencies. PMID:23575694

  2. Circuits F 2015 For the following questions assume that all NMOS transistors are identical with gate capacitances

    E-print Network

    Anlage, Steven

    Circuits F 2015 For the following questions assume that all NMOS transistors are identical (across nodes a-b) and show that there is a value of G such that the circuit becomes an oscillator and give the oscillation frequency. #2. (6 points) The following BJT circuits (called Darlington

  3. Integrated Circuit Electromagnetic Immunity Handbook

    NASA Astrophysics Data System (ADS)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  4. Gyrator employing field effect transistors

    NASA Technical Reports Server (NTRS)

    Hochmair, E. S. (inventor)

    1973-01-01

    A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

  5. Evaluation and fabrication of GaAs integrated logic circuits

    NASA Astrophysics Data System (ADS)

    Vannel, Jean-Paul

    The working principles and the state of art of integrated injection logic circuits are reviewed. A fine modeling allows to evaluate the potential performances and the optimization criteria for this family, based on GaAlAs/GaAs double heterojunction bipolar transistors. The fabrication sequences for the integrated injection logic circuits are described. Emphasis is given to the molecular beam epitaxy and the ion implantation. The high maximum current gains, measured for the elementary transistors in forward and reverse operations (250 and 400 respectively) and the effective gains measured in the four collector gates (between 16 and 4 according to the collector rank), simultaneously testify to the possibilities brought by the double heterojunction structure concerning the fan out and the noise immunity. The performances of this technology enhanced from the seven stage ring oscillator response, give a minimum propagation delay time about one nanosecond and a 1 pJ power delay product for a 20 micrometer design rule. Both agree with theoretical previsions.

  6. High-performance and stable organic transistors and circuits with patterned polypyrrole electrodes.

    PubMed

    Li, Liqiang; Jiang, Lin; Wang, Wenchong; Du, Chuan; Fuchs, Harald; Hu, Wenping; Chi, Lifeng

    2012-04-24

    High performance p-/n-type transistors and complementary inverter circuits are demonstrated using patterned polypyrrole (PPY) as pure electrodes. Strikingly, these devices show good stability under continuous operation and long-term storage conditions. Furthermore, PPY electrodes also exhibit good applicability in solution-processed and flexible devices. All these results indicate the great potential of PPY electrodes in solution-processed, all-organic, flexible, transparent, and low-power electronics. PMID:22431264

  7. A Simple 2-Transistor Touch or Lick Detector Circuit

    ERIC Educational Resources Information Center

    Slotnick, Burton

    2009-01-01

    Contact or touch detectors in which a subject acts as a switch between two metal surfaces have proven more popular and arguably more useful for recording responses than capacitance switches, photocell detectors, and force detectors. Components for touch detectors circuits are inexpensive and, except for some special purpose designs, can be easily…

  8. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  9. Integrated-Circuit Pseudorandom-Number Generator

    NASA Technical Reports Server (NTRS)

    Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

    1992-01-01

    Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

  10. A miniature microcontroller curve tracing circuit for space flight testing transistors.

    PubMed

    Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

    2015-02-01

    This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results. PMID:25725870

  11. Widefield subsurface microscopy of integrated circuits.

    PubMed

    Köklü, Fatih Hakan; Quesnel, Justin I; Vamivakas, Anthony N; Ippolito, Stephen B; Goldberg, Bennett B; Unlü, M Selim

    2008-06-23

    We apply the numerical aperture increasing lens technique to widefield subsurface imaging of silicon integrated circuits. We demonstrate lateral and longitudinal resolutions well beyond the limits of conventional backside imaging. With a simple infrared widefield microscope (lambda(0) = 1.2 microm), we demonstrate a lateral spatial resolution of 0.26 microm (0.22 lambda(0)) and a longitudinal resolution of 1.24 microm (1.03 lambda(0)) for backside imaging through the silicon substrate of an integrated circuit. We present a spatial resolution comparison between widefield and confocal microscopy, which are essential in integrated circuit analysis for emission and excitation microscopy, respectively. PMID:18575515

  12. Reusable vibration resistant integrated circuit mounting socket

    DOEpatents

    Evans, Craig N. (Irwin, PA)

    1995-01-01

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  13. Carbon nanotube synthesis for integrated circuit interconnects

    E-print Network

    Nessim, Gilbert Daniel

    2009-01-01

    Based on their properties, carbon nanotubes (CNTs) have been identified as ideal replacements for copper interconnects in integrated circuits given their higher current density, inertness, and higher resistance to ...

  14. Chain Of Test Contacts For Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo

    1989-01-01

    Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

  15. External electro-optic probing of millimeter-wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Whitaker, J. F.; Valdmanis, J. A.; Jackson, T. A.; Bhasin, K. B.; Romanofsky, Robert R.; Mourou, G. A.

    1989-01-01

    An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

  16. Reverse engineering of integrated circuits

    DOEpatents

    Chisholm, Gregory H. (Shorewood, IL); Eckmann, Steven T. (Colorado Springs, CO); Lain, Christopher M. (Pittsburgh, PA); Veroff, Robert L. (Albuquerque, NM)

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  17. Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator

    E-print Network

    Lee, Jong Duk

    dealing with bending effects and com- plementary organic circuits have been performed.4,5) Al- though(vinyl alcohol) (PVA) is a promising organic gate dielectric because of its high dielectric constant6) and easyElectrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double

  18. Thin-film transistor circuits on large-area spherical surfaces

    NASA Astrophysics Data System (ADS)

    Hsu, P. I.; Bhattacharya, R.; Gleskova, H.; Huang, M.; Xi, Z.; Suo, Z.; Wagner, S.; Sturm, J. C.

    2002-08-01

    We report amorphous silicon (a-Si:H) thin-film transistors (TFTs) fabricated on a planar foil substrate, which is then permanently deformed to a spherical dome, where they are interconnected to inverter circuits. This dome subtends as much as 66° (˜1 sr) with the tensile strain reaching a maximum value of ˜6% on its top. Functional TFTs are obtained if design rules are followed to make stiff TFT islands of limited size on compliant substrates. Photoresist patterns for island interconnects are made on the flat structure, are plastically deformed during the shaping of the dome, and then serve to delineate interconnects deposited after deformation by lift-off. We describe the effect of deformation on the TFTs before and after deformation and the performance of TFT inverter circuits. Our results demonstrate that the concept of stiff circuit islands fabricated on deformable foil substrates is a promising approach to electronics on surfaces with arbitrary shapes.

  19. Réalisation de circuits intégrés I^2L à base de transistors bipolaires a double hétérojonction GaAlAs/GaAs

    NASA Astrophysics Data System (ADS)

    Vannel, J. P.; Camps, T.; Ferreira, A. S.; Tasselh, J.; Cazarré, A.; Marty, A.; Bailbé, J. P.

    1991-04-01

    GaAlAs/GaAs double heterojunction bipolar transistors (DHBT's) have a number of advantages for I^2L (integrated injection logic) high speed integrated circuits concerning the interchangeability between the emitter and the collector and a high design flexibility due to the use of two heterojunctions. We present the fabrication process of an I^2L integrated circuit including a frequency divider-by-two and a ring oscillator which presents a propagation delay time of 1.2 ns for a power consumption of 8 mW. Les transistors bipolaires à double hétérojonction GaAlAs/GaAs (TBDH) présentent de nombreux avantages pour leur application dans des circuits intégrés de logique I^2L (logique à injection intégrée), dont en particulier l'interchangeabilité entre émetteur et collecteur, et la liberté de conception résultant de l'utilisation de deux hétérojonctions. Dans ce cadre nous décrivons les principales étapes technologiques de fabrication d'un circuit intégré I^2L comportant un diviseur de fréquence par 2 et un oscillateur en anneau. Ce demier présente un temps de propagation de 1,2 ns pour une puissance dissipée de 8 mW.

  20. IEEE Communications Magazine February 20022 Distributed Integrated Circuits

    E-print Network

    Hajimiri, Ali

    IEEE Communications Magazine · February 20022 Distributed Integrated Circuits: An Alternative Approach to High-Frequency Design 0163-6804/02/$17.00 © 2002 IEEE ABSTRACT Distributed integrated circuits be implemented as integrated circuits. The integrated circuit design process is then divided further by defining

  1. Area "Integrated Circuits and Systems" ICS Specialization in Bachelor Program

    E-print Network

    Grabner, Helmut

    Area "Integrated Circuits and Systems" 1 / 2 ICS Specialization in Bachelor Program Core Recommendations: "Integrated Circuits and Systems" (ICS) describe a small but coherent subset of core courses Integrated Circuits" lays the foundations for understanding how integrated circuits intended for low

  2. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

    PubMed Central

    Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

    2014-01-01

    Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

  3. Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

    PubMed

    Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

    2011-08-01

    Ambipolar ?-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (?4.1 eV) compared to that of a pristine Au electrode (?4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ?0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ?0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ?12 kHz) based on a solution-processed ambipolar polymer are demonstrated. PMID:21805991

  4. Integrated Circuit Stellar Magnitude Simulator

    ERIC Educational Resources Information Center

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  5. Complementary metal oxide silicon integrated circuits incorporating monolithically integrated stretchable wavy interconnects

    E-print Network

    Rogers, John A.

    Complementary metal oxide silicon integrated circuits incorporating monolithically integrated--yields strain independent electrical performance and realistic paths to circuit integration. A typical circuit systems.2 A disadvantage of the former is that large scale integration can be difficult, due

  6. ECE 423 CMOS Integrated Circuits II Catalog Description: Analysis and design of analog integrated circuits in CMOS technology;

    E-print Network

    ECE 423 ­ CMOS Integrated Circuits II Catalog Description: Analysis and design of analog integrated Integrated Circuits, Gray and Meyer, John Wiley & Sons, 2001 (required) Microelectronic Circuits, A. Sedra Integrated Circuits, B. Razavi, McGraw-Hill, 1999 (optional) Students with Disabilities: #12;Accommodations

  7. Integrated circuit components for 94 GHz applications

    NASA Astrophysics Data System (ADS)

    Ngan, Y. C.; Yen, Y. E.; English, D.; Grote, A.; Pham, T.

    1987-01-01

    The development, design and performance of 94 GHz Microstrip Integrated Circuit (MIC) Gunn VCOs, down-converters, IMPATT injection-locked amplifiers, and low loss circulators are described in this paper. These components have subsequently been integrated into an all integrated circuit short pulse transceiver. Test results of the transceiver verify their superior performance working as a subsystem. This work clearly establishes MIC technology as a viable approach toward achieving compact and lightweight 94 GHz transceiver design in planar construction, which is a necessary precursor to full monolithic implementation.

  8. Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

    NASA Technical Reports Server (NTRS)

    Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

    1995-01-01

    Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

  9. Solution methods for very highly integrated circuits.

    SciTech Connect

    Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

    2010-12-01

    While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator, both prominent world-class software tools.

  10. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    NASA Technical Reports Server (NTRS)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  11. A test structure for the measurement and characterization of layout-induced transistor variation

    E-print Network

    Chang, Albert Hsu Ting

    2009-01-01

    Transistor scaling has enabled us to design circuits with higher performance, lower cost, and higher density; billions of transistors can now be integrated onto a single die. However, this trend also magnifies the significance ...

  12. Total dose and dose rate models for bipolar transistors in circuit simulation.

    SciTech Connect

    Campbell, Phillip Montgomery; Wix, Steven D.

    2013-05-01

    The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

  13. Integrating Circuit Analyses for Assertion-based Verification

    E-print Network

    Sen, Alper

    Integrating Circuit Analyses for Assertion-based Verification of Programmable AMS Circuits Dogan-signal (AMS) verification environment. Therefore, we integrate common analog circuit analyses into mixed-signal time-domain verification still remains a challenge. In this paper, we integrate circuit

  14. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, Stanley H. (26 Aspen Rd., Placitas, NM 87043); Hadley, G. Ronald (6012 Annapolis NE., Albuquerque, NM 87111); Warren, Mial E. (3825 Mary Ellen NE., Albuquerque, NM 87111); Carson, Richard F. (1036 Jewel Pl. NE., Albuquerque, NM 87123); Armendariz, Marcelino G. (1023 Oro Real NE., Albuquerque, NM 87123)

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  15. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

    1998-08-04

    A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

  16. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  17. III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

    PubMed

    Svensson, Johannes; Dey, Anil W; Jacobsson, Daniel; Wernersson, Lars-Erik

    2015-12-01

    III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high Ion/Ioff ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si. PMID:26595174

  18. Phase-controlled integrated photonic quantum circuits

    E-print Network

    Brian J. Smith; Dmytro Kundys; Nicholas Thomas-Peter; P. G. R. Smith; I. A. Walmsley

    2009-09-23

    Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externally-controlled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms.

  19. Test Structures For Bumpy Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  20. Laboratory experiments in integrated circuit fabrication

    NASA Technical Reports Server (NTRS)

    Jenkins, Thomas J.; Kolesar, Edward S.

    1993-01-01

    The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

  1. Microwave integrated circuits for space applications

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  2. Microwave integrated circuit for Josephson voltage standards

    NASA Technical Reports Server (NTRS)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (inventors)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  3. Automatic test pattern generation for asynchronous circuits 

    E-print Network

    Vasudevan, Dilip Prasad

    2012-11-29

    The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the ...

  4. Research Centers Center for Integrated Circuits and Systems ......................................................................................... RC.1

    E-print Network

    Reif, Rafael

    Research Centers Center for Integrated Circuits and SystemsRs Center for Integrated Circuits and systems Professor Hae-Seung Lee, Director The Center for Integrated. The result is truly synergistic, and it will have a lasting impact on the field of integrated circuits

  5. Integrated Circuit Failure Analysis Hypertext Help System

    Energy Science and Technology Software Center (ESTSC)

    1995-02-23

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  6. Integrated Circuits in the Introductory Electronics Laboratory

    ERIC Educational Resources Information Center

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  7. Package Holds Five Monolithic Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  8. Bioluminescent bioreporter integrated circuit detection methods

    DOEpatents

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  9. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    NASA Technical Reports Server (NTRS)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  10. Development of 3D integrated circuits for HEP

    SciTech Connect

    Yarema, R.; /Fermilab

    2006-09-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

  11. Single-Event Upset and Snapback in Silicon-on-Insulator Devices and Integrated Circuits

    SciTech Connect

    DODD,PAUL E.; SHANEYFELT,MARTY R.; WALSH,DAVID S.; SCHWANK,JAMES R.; HASH,GERALD L.; LOEMKER,RHONDA ANN; DRAPER,BRUCE L.; WINOKUR,PETER S.

    2000-08-15

    The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

  12. Integrated-Circuit Active Digital Filter

    NASA Technical Reports Server (NTRS)

    Nathan, R.

    1986-01-01

    Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

  13. SEU In An Advanced Bipolar Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A.; Secrest, Elaine C.; Berndt, Dale F.

    1989-01-01

    Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

  14. AbstractAn indium-phosphide (InP) double-heterojunction bipolar transistor (DHBT) based suite of terahertz monolithic

    E-print Network

    Rodwell, Mark J. W.

    of terahertz monolithic integrated circuits (TMICs) fabricated using 256nm InP DHBT transistors their use in many applications. During the 1970's, the development of the microwave monolithic integrated circuit (MMIC) enabled the implementation of complex transistor-based microwave circuits monolithically

  15. Minimizing the area required for time constants in integrated circuits

    NASA Technical Reports Server (NTRS)

    Lyons, J. C.

    1972-01-01

    When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.

  16. technologie transistor.

    E-print Network

    Hivert, Florent

    Éléments de technologie Les circuits intégrées c-MOS. L'élément de base est le transistor. Deux types de transistors complémentaires n-MOS et p-MOS. Avantages des c-MOS : #21; très grande intégration des impuretés. - plus récement : bombardement ionique. 2 #12; Transistor n-MOS (Metal

  17. DISTROY: Detecting Integrated Circuit Trojans with Compressive Measurements

    E-print Network

    Kung, H. T.

    DISTROY: Detecting Integrated Circuit Trojans with Compressive Measurements Youngjune L. Gwon, H. T in an integrated circuit (IC) is an important but hard problem. A Trojan is malicious hardware--it can be extremely. They outsource the manufacturing of their integrated circuit (IC) products to cheaper or more advanced

  18. Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section

    E-print Network

    Gallium Arsenide Integrated Circuits 1988 ANZAAS Congress, VLSI Section Anthony E. Parker. As a result, GaAs integrated circuits are found increasingly in very high performance systems in communications, computers and instrumentation. High performance digital integrated circuits will be especially

  19. Title of dissertation: CHAOTIC OSCILLATIONS IN CMOS INTEGRATED CIRCUITS

    E-print Network

    Anlage, Steven

    ABSTRACT Title of dissertation: CHAOTIC OSCILLATIONS IN CMOS INTEGRATED CIRCUITS Myunghwan Park and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic OSCILLATIONS IN CMOS INTEGRATED CIRCUITS by Myunghwan Park Dissertation submitted to the Faculty

  20. Integrating suspended quantum dot circuits for applications in nanomechanics

    E-print Network

    Ludwig-Maximilians-Universität, München

    Integrating suspended quantum dot circuits for applications in nanomechanics J. Kirschbaum, E. M 15 May 2002 We present an integrated nanoelectromechanical circuit designed for achieving and integrated a nanomechanical resonator with a freely sus- pended quantum dot circuit which allows us to probe

  1. Integrated-Circuit Controller For Brushless dc Motor

    NASA Technical Reports Server (NTRS)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  2. Applying analog integrated circuits for HERO protection

    NASA Technical Reports Server (NTRS)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  3. Relationships among classes of self-oscillating transistor parallel inverters. [dc to square wave converter circuits for power conditioning

    NASA Technical Reports Server (NTRS)

    Wilson, T. G.; Lee, F. C. Y.; Burns, W. W., III; Owen, H. A., Jr.

    1974-01-01

    A procedure is developed for classifying dc-to-square-wave two-transistor parallel inverters used in power conditioning applications. The inverters are reduced to equivalent RLC networks and are then grouped with other inverters with the same basic equivalent circuit. Distinction between inverter classes is based on the topology characteristics of the equivalent circuits. Information about one class can then be extended to another class using the basic oscillation theory and the concept of duality. Oscillograms from test circuits confirm the validity of the procedure adopted.

  4. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  5. Progress in radiation immune thermionic integrated circuits

    SciTech Connect

    Lynn, D.K.; McCormick, J.B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  6. Integrated digital inverters based on two-dimensional anisotropic ReS? field-effect transistors

    DOE PAGESBeta

    Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching -Hwa; et al

    2015-05-07

    Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS?) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS? field-effect transistors, which exhibit competitive performance with large current on/off ratios (~10?) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconductingmore »materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS? anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications.« less

  7. Integrated digital inverters based on two-dimensional anisotropic ReS? field-effect transistors

    SciTech Connect

    Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching -Hwa; Huang, Ying -Sheng; Cao, Zhengyi; Wang, Laiguo; Li, Aidong; Zeng, Junwen; Song, Fengqi; Wang, Xinran; Shi, Yi; Yuan, Hongtao; Hwang, Harold Y.; Cui, Yi; Miao, Feng; Xing, Dingyu

    2015-05-07

    Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS?) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS? field-effect transistors, which exhibit competitive performance with large current on/off ratios (~10?) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconducting materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS? anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications.

  8. Power system with an integrated lubrication circuit

    DOEpatents

    Hoff, Brian D. (East Peoria, IL); Akasam, Sivaprasad (Peoria, IL); Algrain, Marcelo C. (Peoria, IL); Johnson, Kris W. (Washington, IL); Lane, William H. (Chillicothe, IL)

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  9. Coaxial inverted geometry transistor having buried emitter

    NASA Technical Reports Server (NTRS)

    Hruby, R. J.; Cress, S. B.; Dunn, W. R. (inventors)

    1973-01-01

    The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

  10. Radio Frequency Transistors and Circuits Based on CVD MoS2.

    PubMed

    Sanne, Atresh; Ghosh, Rudresh; Rai, Amritesh; Yogeesh, Maruthi Nagavalli; Shin, Seung Heon; Sharma, Ankit; Jarvis, Karalee; Mathew, Leo; Rao, Rajesh; Akinwande, Deji; Banerjee, Sanjay

    2015-08-12

    We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 ?A/?m and maximum transconductance of 38 ?S/?m. A contact resistance corrected low-field mobility of 55 cm(2)/(V s) was achieved. Radio frequency FETs were fabricated in the ground-signal-ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications. PMID:26134588

  11. Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

    NASA Astrophysics Data System (ADS)

    Es-Sakhi, Azzedin D.

    Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

  12. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  13. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, Edward H. (Livermore, CA); Tuckerman, David B. (Livermore, CA)

    1991-01-01

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

  14. SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs

    SciTech Connect

    Huque, Mohammad A; Tolbert, Leon M; Blalock, Benjamin; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  15. Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A. (inventor)

    1991-01-01

    Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

  16. Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration

    E-print Network

    Sredojevi?, Ranko Radovin.

    2008-01-01

    Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring ...

  17. Integrated-Circuit Broadband Infrared Sources

    NASA Technical Reports Server (NTRS)

    Lamb, G.; Jhabvala, M.; Burgess, A.

    1989-01-01

    Microscopic devices consume less power, run hotter, and are more reliable. Simple, compact, lightweight, rapidly-responding reference sources of broadband infrared radiation made available by integrated-circuit technology. Intended primarily for use in calibration of remote-sensing infrared instruments, devices eventually replace conventional infrared sources. New devices also replace present generation of miniature infrared sources. Self-passivating nature of poly-crystalline silicon adds to reliability of devices. Maximum operating temperature is 1,000 K, and power dissipation is only one-fourth that of prior devices.

  18. Accelerating functional verification of an integrated circuit

    SciTech Connect

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G

    2015-11-05

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  19. Accelerating functional verification of an integrated circuit

    SciTech Connect

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  20. Tool For Tinning Integrated-Circuit Leads

    NASA Technical Reports Server (NTRS)

    Prosser, Gregory N.

    1988-01-01

    As many as eight flatpacks held. Tool made of fiberglass boards. Clamps row of flatpacks by their leads so leads on opposite side of packages dipped. After dipping, nuts on boards loosened, flatpacks turned around, nuts retightened, and untinned leads dipped. Strips of magnetic material grip leads of flatpacks (made of Kovar, magnetic iron/nickel/cobalt alloy) while boards repositioned. Micrometerlike screw used to adjust exposed width of magnetic strip to suit dimensions of flatpacks. Holds flatpack integrated circuits so leads tinned. Accommodates several flatpacks for simultaneous dipping of leads in molten solder. Adjusts to accept flatpacks in range of sizes.

  1. 3D packaging for integrated circuit systems

    SciTech Connect

    Chu, D.; Palmer, D.W.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  2. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    DOEpatents

    Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  3. A Bonded-Micro-Platform Technology for Modular Merging of RF MEMS and Transistor Circuits

    E-print Network

    Nguyen, Clark T.-C.

    /transistor process technol- ogy [4]-[6], single-chip RF MEMS front-ends using high-performance super with active transistor electronics. This bonded platform technology allows low-capacitance, "single-chip

  4. Systems/Circuits Nonlinear Spatial Integration in the Receptive Field

    E-print Network

    Gollisch, Tim

    Systems/Circuits Nonlinear Spatial Integration in the Receptive Field Surround of Retinal Ganglion Go¨ttingen, Germany Throughout different sensory systems, individual neurons integrate incoming signals over their receptive fields. The characteristics of this signal integration are crucial

  5. Optimization of transistor design including large signal device/circuit interactions at extremely high frequencies (20-100+GHz)

    NASA Technical Reports Server (NTRS)

    Levy, Ralph; Grubin, H. L.

    1991-01-01

    Transistor design for extremely high frequency applications requires consideration of the interaction between the device and the circuit to which it is connected. Traditional analytical transistor models are to approximate at some of these frequencies and may not account for variations of dopants and semiconductor materials (especially some of the newer materials) within the device. Physically based models of device performance are required. These are based on coupled systems of partial differential equations and typically require 20 minutes of Cray computer time for a single AC operating point. A technique is presented to extract parameters from a few partial differential equation solutions for the device to create a nonlinear equivalent circuit model which runs in approximately 1 second of personal computer time. This nonlinear equivalent circuit model accurately replicates the contact current properties of the device as computed by the partial differential solver on which it is based. Using the nonlinear equivalent circuit model of the device, optimization of systems design can be performed based on device/circuit interactions.

  6. Challenges and advances of photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Debrégeas-Sillard, Hélène; Kazmierski, Christophe

    2008-11-01

    The idea of Photonic Integrated Circuits (PICs) appeared in the 1970s, had first achievements in the 1980s with, for example, a laser-modulator. However, recently, due to the demand for increasing bandwidth (100 Gb/s) at lower cost and consumption, and due to semiconductor optoelectronics processing maturity, extremely complex PICs have been developed and industrially produced. This dense integration is an important technological breakthrough, and has a strong impact on optical communication systems with for example cost-effective O/E/O nodes, or transmissions with new modulation formats. This article presents the technological challenges related to PICs, and the major realizations made, up to today. To cite this article: H. Debrégeas-Sillard, C. Kazmierski, C. R. Physique 9 (2008).

  7. Packaging challenges for integrated silicon photonic circuits

    NASA Astrophysics Data System (ADS)

    Pavarelli, Nicola; Lee, Jun Su; O'Brien, Peter A.

    2014-05-01

    Cost-effective packaging of silicon photonic devices presents a significant bottleneck to commercialization of the technology. One way of addressing this packaging challenge is to use techniques that have been developed by the electronics industry and which also benefit from the use of advanced electronics assembly equipment. Even packaging processes such as fiber coupling can benefit from this approach, along with the hybrid integration of devices such as electronic components (e.g. modulator driver integrated circuits). In this paper, we will present developments made by our group towards achieving scalable fiber and electronic packaging processes that rely on electronic assembly techniques such as flip-chip assembly. We will also provide an overview of packaged prototypes being developed within our group for telecom and sensing applications and how these packaging technologies are now being made available to users through the ePIXfab foundry service.

  8. Technologies for highly parallel optoelectronic integrated circuits

    SciTech Connect

    Lear, K.L.

    1994-10-01

    While summarily reviewing the range of optoelectronic integrated circuits (OEICs), this paper emphasizes technology for highly parallel optical interconnections. Market volume and integration suitability considerations highlight board-to-board interconnects within systems as an initial insertion point for large OEIC production. The large channel count of these intrasystem interconnects necessitates two-dimensional laser transmitter and photoreceiver arrays. Surface normal optoelectronic components are promoted as a basis for OEICs in this application. An example system is discussed that uses vertical cavity surface emitting lasers for optical buses between layers of stacked multichip modules. Another potentially important application for highly parallel OEICs is optical routing or packet switching, and examples of such systems based on smart pixels are presented.

  9. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

    PubMed

    Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

    2015-08-12

    Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (?38) and small static power (picowatts), paving the way for low power electronic system in 2D materials. PMID:26192468

  10. Self-integration of nanowires into circuits via guided growth

    E-print Network

    Joselevich, Ernesto

    Self-integration of nanowires into circuits via guided growth Mark Schvartzmana , David Tsiviona applied this approach for the integration of 14 discrete NWs into an electronic circuit operat- ing discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration

  11. Heterojunction bipolar transistor technology for data acquisition and communication

    NASA Technical Reports Server (NTRS)

    Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

    1992-01-01

    Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

  12. Design for manufacturability with regular fabrics in digital integrated circuits

    E-print Network

    Gazor, Mehdi (Seyed Mehdi)

    2005-01-01

    Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the ...

  13. Integrated photo-responsive metal oxide semiconductor circuit

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzban D. (inventor); Dargo, David R. (inventor); Lyons, John C. (inventor)

    1987-01-01

    An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

  14. High mobility flexible graphene field-effect transistors and ambipolar radio-frequency circuits.

    PubMed

    Liang, Yiran; Liang, Xuelei; Zhang, Zhiyong; Li, Wei; Huo, Xiaoye; Peng, Lianmao

    2015-07-01

    Field-effect transistors (GFETs) were fabricated on mechanically flexible substrates using chemical vapor deposition grown graphene. High current density (nearly 200 ?A ?m(-1)) with saturation, almost perfect ambipolar electron-hole behavior, high transconductance (120 ?S ?m(-1)) and good stability over 381 days were obtained. The average carrier mobility for holes (electrons) is 13,540 cm(2) V(-1) s(-1) (12,300 cm(2) V(-1) s(-1)) with the highest value over 24,000 cm(2) V(-1) s(-1) (20,000 cm(2) V(-1) s(-1)) obtained in flexible GFETs. Ambipolar radio-frequency circuits, frequency doubler, were constructed based on the high performed flexible GFET, which show record high output power spectra purity (?97%) and high conversion gain of -13.6 dB. Bending measurements show the flexible GFETs are able to work under modest strain. These results show that flexible GFETs are a very promising option for future flexible radio-frequency electronics. PMID:26061485

  15. Pentacene integrated thin-film transistors and circuits

    E-print Network

    Nausieda, Ivan Alexander

    2009-01-01

    Organic semiconductors offer the potential of large-area, mechanically flexible electronics due to their low processing temperatures. We have developed a near-room-temperature (< 95°C) process flow to fabricate pentacene ...

  16. Ge/Si Integrated Circuit For Infrared Imaging

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.

    1990-01-01

    Proposed integrated circuit consists of focal-plane array of metal/germanium Schottky-barrier photodetectors on same chip with silicon-based circuits that processes signals from photodetectors. Made compatible with underlying silicon-based circuitry by growing germanium epitaxially on silicon circuit wafers. Metal deposited in ultrahigh vacuum immediately after growth of germanium. Combination of described techniques results in high-resolution infrared-imaging circuits of superior performance.

  17. Heterogeneous photonic integrated circuits and their applications in computing, networking, and imaging

    E-print Network

    Yoo, S. J. Ben

    Heterogeneous photonic integrated circuits and their applications in computing, networking integration, photonic integrated circuits, optical interconnects. 1. INTRODUCTION The continuing exponential on integrated circuits to offer scalability, high performance, and cost-effectiveness. Such demands have been

  18. Preventing Simultaneous Conduction In Switching Transistors

    NASA Technical Reports Server (NTRS)

    Mclyman, William T.

    1990-01-01

    High voltage spikes and electromagnetic interference suppressed. Power-supply circuit including two switching transistors easily modified to prevent simultaneous conduction by both transistors during switching intervals. Diode connected between collector of each transistor and driving circuit for opposite transistor suppresses driving signal to transistor being turned on until transistor being turned off ceases to carry current.

  19. Circuit design for embedded memory in low-power integrated circuits

    E-print Network

    Qazi, Masood

    2012-01-01

    This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the ...

  20. Monolithic microwave integrated circuit water vapor radiometer

    NASA Technical Reports Server (NTRS)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  1. Dual threshold voltage organic thin-film transistor technology

    E-print Network

    Nausieda, Ivan A.

    A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The nearroom-temperature (<; 95 °C) process produces ...

  2. Condensed-matter Physics: Flat transistor defies the limit

    NASA Astrophysics Data System (ADS)

    Tomioka, Katsuhiro

    2015-10-01

    A transistor has been demonstrated that operates at low supply voltages by exceeding a theoretical limit. The finding opens up avenues to the development of integrated circuits that have extremely low power consumption. See Letter p.91

  3. W88 integrated circuit shelf life program

    SciTech Connect

    Soden, J.M.; Anderson, R.E.

    1998-01-01

    The W88 Integrated Circuit Shelf Life Program was created to monitor the long term performance, reliability characteristics, and technological status of representative WR ICs manufactured by the Allied Signal Albuquerque Microelectronics Operation (AMO) and by Harris Semiconductor Custom Integrated Circuits Division. Six types of ICs were used. A total of 272 ICs entered two storage temperature environments. Electrical testing and destructive physical analysis were completed in 1995. During each year of the program, the ICs were electrically tested and samples were selected for destructive physical analysis (DPA). ICs that failed electrical tests or DPA criteria were analyzed. Fifteen electrical failures occurred, with two dominant failure modes: electrical overstress (EOS) damage involving the production test programs and electrostatic discharge (ESD) damage during analysis. Because of the extensive handling required during multi-year programs like this, it is not unusual for EOS and ESD failures to occur even though handling and testing precautions are taken. The clustering of the electrical test failures in a small subset of the test operations supports the conclusion that the test operation itself was responsible for many of the failures and is suspected to be responsible for the others. Analysis of the electrical data for the good ICs found no significant degradation trends caused by the storage environments. Forty-six ICs were selected for DPA with findings primarily in two areas: wire bonding and die processing. The wire bonding and die processing findings are not surprising since these technology conditions had been documented during manufacturing and were determined to present acceptable risk. The current reliability assessment of the W88 stockpile assemblies employing these and related ICs is reinforced by the results of this shelf life program. Data from this program will aid future investigation of 4/3 micron or MNOS IC technology failure modes.

  4. Development of a stereo-symmetrical nanosecond pulsed power generator composed of modularized avalanche transistor Marx circuits.

    PubMed

    Li, Jiang-Tao; Zhong, Xu; Cao, Hui; Zhao, Zheng; Xue, Jing; Li, Tao; Li, Zheng; Wang, Ya-Nan

    2015-09-01

    Avalanche transistors have been widely studied and used in nanosecond high voltage pulse generations. However, output power improvement is always limited by the low thermal capacities of avalanche transistors, especially under high repetitive working frequency. Parallel stacked transistors can effectively improve the output current but the controlling of trigger and output synchronism has always been a hard and complex work. In this paper, a novel stereo-symmetrical nanosecond pulsed power generator with high reliability was developed. By analyzing and testing the special performances of the combined Marx circuits, numbers of meaningful conclusions on the pulse amplitude, pulse back edge, and output impedance were drawn. The combining synchronism of the generator was confirmed excellent and lower conducting current through the transistors was realized. Experimental results showed that, on a 50 ? resistive load, pulses with 1.5-5.2 kV amplitude and 5.3-14.0 ns width could be flexibly generated by adjusting the number of combined modules, the supply voltage, and the module type. PMID:26429438

  5. Development of a stereo-symmetrical nanosecond pulsed power generator composed of modularized avalanche transistor Marx circuits

    NASA Astrophysics Data System (ADS)

    Li, Jiang-Tao; Zhong, Xu; Cao, Hui; Zhao, Zheng; Xue, Jing; Li, Tao; Li, Zheng; Wang, Ya-Nan

    2015-09-01

    Avalanche transistors have been widely studied and used in nanosecond high voltage pulse generations. However, output power improvement is always limited by the low thermal capacities of avalanche transistors, especially under high repetitive working frequency. Parallel stacked transistors can effectively improve the output current but the controlling of trigger and output synchronism has always been a hard and complex work. In this paper, a novel stereo-symmetrical nanosecond pulsed power generator with high reliability was developed. By analyzing and testing the special performances of the combined Marx circuits, numbers of meaningful conclusions on the pulse amplitude, pulse back edge, and output impedance were drawn. The combining synchronism of the generator was confirmed excellent and lower conducting current through the transistors was realized. Experimental results showed that, on a 50 ? resistive load, pulses with 1.5-5.2 kV amplitude and 5.3-14.0 ns width could be flexibly generated by adjusting the number of combined modules, the supply voltage, and the module type.

  6. Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

    PubMed Central

    Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

    2014-01-01

    Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal?oxide?semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

  7. Material selection and nanofabrication techniques for electronic photonic integrated circuits

    E-print Network

    Holzwarth, Charles W., III (Charles Willett)

    2009-01-01

    Electronic-photonic integrated circuits have the potential to circumvent many of the performance bottlenecks of electronics. To achieve the full benefits of integrating photonics with electronics it is generally believed ...

  8. Complementary junction heterostructure field-effect transistor

    DOEpatents

    Baca, Albert G. (Albuquerque, NM); Drummond, Timothy J. (Albuquerque, NM); Robertson, Perry J. (Albuquerque, NM); Zipperian, Thomas E. (Albuquerque, NM)

    1995-01-01

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

  9. Complementary junction heterostructure field-effect transistor

    DOEpatents

    Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

    1995-12-26

    A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

  10. E-Learning System for Design and Construction of Amplifier Using Transistors

    ERIC Educational Resources Information Center

    Takemura, Atsushi

    2014-01-01

    This paper proposes a novel e-Learning system for the comprehensive understanding of electronic circuits with transistors. The proposed e-Learning system allows users to learn a wide range of topics, encompassing circuit theories, design, construction, and measurement. Given the fact that the amplifiers with transistors are an integral part of…

  11. Plug-in integrated/hybrid circuit

    NASA Technical Reports Server (NTRS)

    Stringer, E. J.

    1974-01-01

    Hybrid circuitry can be installed into standard round bayonet connectors, to eliminate wiring from connector to circuit. Circuits can be connected directly into either section of connector pair, eliminating need for hard wiring to that section.

  12. Timing Verification of Adaptive Integrated Circuits 

    E-print Network

    Kumar, Rohit

    2014-08-01

    An adaptive circuit can perform built-in self-detection of timing variations and accordingly adjust itself to avoid timing violations. Compared with conventional over-design approach, adaptive circuit design is conceptually advantageous in terms...

  13. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit

    PubMed Central

    Nakazato, Kazuo

    2014-01-01

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10?MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  14. Programmable Logic Circuits for Functional Integrated Smart Plastic Systems

    E-print Network

    Sou, Antony; Jung, Sungjune; Gili, Enrico; Pecuni, Vincenzo; Joimel, Jerome; Fichet, Guillaume; Sirringhaus, Henning

    2014-09-12

    In this paper, we present a functional integrated plastic system. We have fabricated arrays of organic thin-film transistors (OTFTs) and printed electronic components driving an electrophoretic ink display up to 70mm by 70mm on a single flexible...

  15. How will photonic integrated circuits develop?

    NASA Astrophysics Data System (ADS)

    Haney, Michael W.

    2013-02-01

    This paper explores issues associated with Photonic Integrated Circuit (PIC) research and development - with an overall goal of initiating a discussion of how PIC technology should develop and eventually be deployed with high impact. Significant research and development programs have focused on PICs for routing and switching, and computer interconnects. Most recently, the application domain of PICs has diversified greatly, and now includes analog signal processing, remote sensing, biological and chemical sensing, neural interfacing, and solar cells. A key feature of PIC technology growth has been the exploitation of high-density fabrication and packaging technology originally developed for the Silicon IC industry. PIC foundry services are emerging - and there has been a natural attempt to ascribe a "Moore's Law" to PIC scaling. Analogies to Silicon electronic scaling, however, should be used with caution. PIC complexity scaling may be driven more by the ability to access the degrees-of-freedom offered by PIC-based optical domain signal processing, rather than increasing device count. Specific examples of PIC research in chip-scale computer interconnects and integrated micro-concentrators for solar cells are highlighted.

  16. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  17. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90?nm node

    SciTech Connect

    Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90?nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  18. 77 FR 39735 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-05

    ...337-TA-851] Certain Integrated Circuit Packages Provided With Multiple...after importation of certain integrated circuit packages provided with multiple...after importation of certain integrated circuit packages provided with...

  19. 77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-23

    ...337-TA-859] Certain Integrated Circuit Chips and Products Containing...after importation of certain integrated circuit chips and products containing...after importation of certain integrated circuit chips and products...

  20. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ...Docket No. 2899] Certain Integrated Circuit Packages Provided With Multiple...complaint entitled Certain Integrated Circuit Packages Provided With Multiple...after importation of certain integrated circuit packages provided with...

  1. 78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-02-14

    ...Docket No. 2938] Certain Integrated Circuit Devices and Products Containing...complaint entitled Certain Integrated Circuit Devices and Products Containing...after importation of certain integrated circuit devices and products...

  2. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-02-04

    ...of: Certain Semiconductor Integrated Circuits and Products Containing Same...importation of certain semiconductor integrated circuits and products containing same...of infringement certain LSI integrated circuits, as well as certain...

  3. 78 FR 16533 - Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-15

    ...337-TA-873] Certain Integrated Circuit Devices and Products Containing...after importation of certain integrated circuit devices and products containing...after importation of certain integrated circuit devices and products...

  4. 75 FR 16837 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-02

    ...In the Matter of Certain Integrated Circuits, Chipsets, and Products...after importation of certain integrated circuits, chipsets, and products...after importation of certain integrated circuits, chipsets, or products...

  5. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-05-05

    ...Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...importation of certain large scale integrated circuit semiconductor chips and products...importation of certain large scale integrated circuit semiconductor chips or...

  6. 75 FR 43553 - In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-26

    ...Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing...importation of certain encapsulated integrated circuit devices and products containing...importation of certain encapsulated integrated circuit devices and products...

  7. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-29

    ...2888] Certain Semiconductor Integrated Circuit Devices and Products Containing...entitled Certain Semiconductor Integrated Circuit Devices and Products Containing...importation of certain semiconductor integrated circuit devices and products...

  8. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-01

    ...337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing...importation of certain semiconductor integrated circuit devices and products containing...importation of certain semiconductor integrated circuit devices and products...

  9. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-07

    ...COMMISSION [DN 2860] Certain Integrated Circuits, Chipsets, and Products...complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products...after importation of certain integrated circuits, chipsets, and...

  10. 77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-09-18

    ...337-TA-786] Certain Integrated Circuits, Chipsets, and Products...products that were adjudicated in Integrated Circuits I are precluded under the...and MediaTek's infringing integrated circuits, chipsets, and...

  11. 77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-13

    ...Certain Radio Frequency Integrated Circuits and Devices Containing Same...of certain radio frequency integrated circuits and devices containing same...of certain radio frequency integrated circuits and devices containing...

  12. 76 FR 41521 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-07-14

    ...In the Matter of Certain Integrated Circuits, Chipsets, and Products...after importation of certain integrated circuits, chipsets, and products...after importation of certain integrated circuits, chipsets, and...

  13. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products.... International Trade Commission has received a complaint entitled Certain Integrated Circuit Packages Provided... sale within the United States after importation of certain integrated circuit packages provided...

  14. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design and Application Considerations for

    E-print Network

    Rieh, Jae-Sung

    IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 645 Transistor Design, and Seshadri Subbanna, Member, IEEE Invited Paper Abstract--SiGe HBT transistors achieving over 200 GHz and MAX--BiCMOS integrated circuits, bipolar transistors, heterojunctions, semiconductor devices. I. INTRODUCTION BIPOLAR

  15. FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

    NASA Astrophysics Data System (ADS)

    Fenouillet-Beranger, C.; Previtali, B.; Batude, P.; Nemouchi, F.; Cassé, M.; Garros, X.; Tosti, L.; Rambal, N.; Lafond, D.; Dansas, H.; Pasini, L.; Brunet, L.; Deprat, F.; Grégoire, M.; Mellier, M.; Vinet, M.

    2015-11-01

    To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

  16. Method for double-sided processing of thin film transistors

    DOEpatents

    Yuan, Hao-Chih (Madison, WI); Wang, Guogong (Madison, WI); Eriksson, Mark A. (Madison, WI); Evans, Paul G. (Madison, WI); Lagally, Max G. (Madison, WI); Ma, Zhenqiang (Middleton, WI)

    2008-04-08

    This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

  17. Ultra High Density Logic Designs Using Transistor-Level Monolithic 3D Integration

    E-print Network

    Lim, Sung Kyu

    Ultra High Density Logic Designs Using Transistor-Level Monolithic 3D Integration Young-Joon Lee1@ece.gatech.edu Abstract-- Recent innovations in monolithic 3D technology enable much higher-density vertical connections and challenges of monolithic 3D integration technology for ultra high-density logic designs. Based on our layout

  18. Nanophotonic integrated circuits from nanoresonators grown on silicon

    NASA Astrophysics Data System (ADS)

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D.; Li, Kun; Chang-Hasnain, Connie

    2014-07-01

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore’s law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  19. Nanophotonic integrated circuits from nanoresonators grown on silicon.

    PubMed

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

    2014-01-01

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits. PMID:24999601

  20. Securing Health Sensing Using Integrated Circuit Metric.

    PubMed

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-01-01

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware "fingerprints". The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner. PMID:26492250

  1. Securing Health Sensing Using Integrated Circuit Metric

    PubMed Central

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-01-01

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner. PMID:26492250

  2. Two-photon laser-assisted device alteration in silicon integrated-circuits.

    PubMed

    Serrels, Keith A; Erington, Kent; Bodoh, Dan; Farrell, Carl; Leslie, Neel; Lundquist, Theodore R; Vedagarbha, Praveen; Reid, Derryck T

    2013-12-01

    Optoelectronic imaging of integrated-circuits has revolutionized device design debug, failure analysis and electrical fault isolation; however modern probing techniques like laser-assisted device alteration (LADA) have failed to keep pace with the semiconductor industry's aggressive device scaling, meaning that previously satisfactory techniques no longer exhibit a sufficient ability to localize electrical faults, instead casting suspicion upon dozens of potential root-cause transistors. Here, we introduce a new high-resolution probing technique, two-photon laser-assisted device alteration (2pLADA), which exploits two-photon absorption (TPA) to provide precise three-dimensional localization of the photo-carriers injected by the TPA process, enabling us to implicate individual transistors separated by 100 nm. Furthermore, we illustrate the technique's capability to reveal speed-limiting transistor switching evolution with an unprecedented timing resolution approaching <10 ps. Together, the exceptional spatial and temporal resolutions demonstrated here now make it possible to extend optical fault localization to sub-14 nm technology nodes. PMID:24514459

  3. PHY327 Lab 4 --Diodes and Transistors Transistor

    E-print Network

    Gustafsson, Torgny

    PHY327 Lab 4 -- Diodes and Transistors Diode: Transistor: #12;Silicon: the most important material exponential decay of a RC circuit. #12;Transistor ­ one of the greatest inventions A transistor (3-terminal. The transistor is the fundamental building block of modern electronic devices, and is ubiquitous in modern

  4. (In)AlGaN Heterojunction Field Effect Transistors and Circuits for High-Power Applications at Microwave and Millimeter-Wave Frequencies

    NASA Astrophysics Data System (ADS)

    Maroldt, Stephan; Quay, Rüdiger; Dennler, Philippe; Schwantuschke, Dirk; Musser, Markus; Dammann, Michael; Aidam, Rolf; Waltereit, Patrick; Tessmann, Axel; Ambacher, Oliver

    2013-08-01

    The suitability of the AlGaN/GaN heterostructure for applications up to 20 GHz is demonstrated based on a technically mature process. A broadband power amplifier integrated circuit is designed and fabricated in order to monitor the technology performance. Further, a 100 W power transistor for mobile communications is realized with an efficiency of 70% and an operation frequency of up to 3 GHz. We also demonstrate the performance of a 60 W switch-mode power amplifier module with 75% efficiency for industrial, scientific and medical applications at 2.4 GHz. To push the technology towards higher millimeter-wave frequencies an InAlGaN-based heterostructure was developed. This structure yields high sheet carrier concentration and mobility of 1.9×1013 cm-2 and 1590 cm2 V-1 s-1, respectively. An excellent fT of 110 GHz and fmax of 190 GHz were achieved with HFETs with a gate length of 100 nm. This allowed the realization of InAlGaN-based power amplifier monolithic microwave integrated circuits (MMICs) operating at millimeter-wave frequencies of 60 and 94 GHz.

  5. Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

    NASA Astrophysics Data System (ADS)

    Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

    2015-10-01

    Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 ?m) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

  6. A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

    PubMed

    Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

    2014-03-28

    Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries. PMID:24567478

  7. Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

    E-print Network

    Tan, Michael Loong Peng

    2011-06-07

    of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs...

  8. An organic thin-film transistor circuit for large-area temperature-sensing

    E-print Network

    He, David Da

    2008-01-01

    This thesis explores the application of organic thin-film transistors (OTFTs) for temperature-sensing. The goal of this work is twofold: the understanding of the OTFT's electrical characteristics' temperature dependence, ...

  9. A Low Noise Readout Circuit for Integrated Electrochemical Biosensor Arrays

    E-print Network

    Mason, Andrew

    A Low Noise Readout Circuit for Integrated Electrochemical Biosensor Arrays Jichun Zhang, Nicholas electrochemical interface circuit that is tuned to the needs of protein-based biosensor arrays and compatible biosensor output currents from 10pA to 10 A to suit a wide range of sensitivities and electrode areas

  10. The Effects of Space Radiation on Linear Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Johnston, A.

    2000-01-01

    Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

  11. 35 GHz integrated circuit rectifying antenna with 33 percent efficiency

    NASA Technical Reports Server (NTRS)

    Yoo, T.-W.; Chang, K.

    1991-01-01

    A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

  12. A Multi-Gigahertz Analog Transient Recorder Integrated Circuit

    E-print Network

    Kleinfelder, Stuart A

    2015-01-01

    A monolithic multi-channel analog transient recorder, implemented using switched capacitor sample-and-hold circuits and a high-speed analogically-adjustable delay-line-based write clock, has been designed, fabricated and tested. The 2.1 by 6.9 mm layout, in 1.2 micron CMOS, includes over 31,000 transistors and 2048 double polysilicon capacitors. The circuit contains four parallel channels, each with a 512 deep switched-capacitor sample-and-hold system. A 512 deep edge sensitive tapped active delay line uses look-ahead and 16 way interleaving to develop the 512 sample and hold clocks, each as little as 3.2 ns wide and 200 ps apart. Measurements of the device have demonstrated 5 GHz maximum sample rate, at least 350 MHz bandwidth, an extrapolated rms aperture uncertainty per sample of 0.7 ps, and a signal to rms noise ratio of 2000:1.

  13. Integrated Circuit Implementation of a Cortical Neuron Jayawan H. B. Wijekoon and Piotr Dudek

    E-print Network

    Dudek, Piotr

    Integrated Circuit Implementation of a Cortical Neuron Jayawan H. B. Wijekoon and Piotr Dudek-mail: jayawan@ieee.org, p.dudek@manchester.ac.uk. Abstract-- This paper presents an analogue integrated circuit the results obtained from the integrated circuit implementation of the proposed neuron circuit. The circuit

  14. Chemical etching for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1981-01-01

    Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

  15. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  16. Superconducting single photon detectors integrated with diamond nanophotonic circuits

    E-print Network

    Patrik Rath; Oliver Kahl; Simone Ferrari; Fabian Sproll; Georgia Lewes-Malandrakis; Dietmar Brink; Konstantin Ilin; Michael Siegel; Christoph Nebel; Wolfram Pernice

    2015-05-16

    Photonic quantum technologies promise to repeat the success of integrated nanophotonic circuits in non-classical applications. Using linear optical elements, quantum optical computations can be performed with integrated optical circuits and thus allow for overcoming existing limitations in terms of scalability. Besides passive optical devices for realizing photonic quantum gates, active elements such as single photon sources and single photon detectors are essential ingredients for future optical quantum circuits. Material systems which allow for the monolithic integration of all components are particularly attractive, including III-V semiconductors, silicon and also diamond. Here we demonstrate nanophotonic integrated circuits made from high quality polycrystalline diamond thin films in combination with on-chip single photon detectors. Using superconducting nanowires coupled evanescently to travelling waves we achieve high detection efficiencies up to 66 % combined with low dark count rates and timing resolution of 190 ps. Our devices are fully scalable and hold promise for functional diamond photonic quantum devices.

  17. Design automation and analysis of three-dimensional integrated circuits

    E-print Network

    Das, Shamik, 1977-

    2004-01-01

    This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical ...

  18. Superconducting single photon detectors integrated with diamond nanophotonic circuits

    E-print Network

    Rath, Patrik; Ferrari, Simone; Sproll, Fabian; Lewes-Malandrakis, Georgia; Brink, Dietmar; Ilin, Konstantin; Siegel, Michael; Nebel, Christoph; Pernice, Wolfram

    2015-01-01

    Photonic quantum technologies promise to repeat the success of integrated nanophotonic circuits in non-classical applications. Using linear optical elements, quantum optical computations can be performed with integrated optical circuits and thus allow for overcoming existing limitations in terms of scalability. Besides passive optical devices for realizing photonic quantum gates, active elements such as single photon sources and single photon detectors are essential ingredients for future optical quantum circuits. Material systems which allow for the monolithic integration of all components are particularly attractive, including III-V semiconductors, silicon and also diamond. Here we demonstrate nanophotonic integrated circuits made from high quality polycrystalline diamond thin films in combination with on-chip single photon detectors. Using superconducting nanowires coupled evanescently to travelling waves we achieve high detection efficiencies up to 66 % combined with low dark count rates and timing resolu...

  19. Algorithms for design for quality of integrated circuits 

    E-print Network

    Achab, Abdenour

    1995-01-01

    The main thesis objective is to develop new, efficient algorithms for designing high quality Integrated Circuits (ICs). The following three major areas of Design for Quality are studied: 1. Quality Measures and their applications. 2.Optimum...

  20. Addressable-Matrix Integrated-Circuit Test Structure

    NASA Technical Reports Server (NTRS)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  1. Multilayer microwave integrated quantum circuits for scalable quantum computing

    E-print Network

    T. Brecht; W. Pfaff; C. Wang; Y. Chu; L. Frunzio; M. H. Devoret; R. J. Schoelkopf

    2015-09-11

    As experimental quantum information processing (QIP) rapidly advances, an emerging challenge is to design a scalable architecture that combines various quantum elements into a complex device without compromising their performance. In particular, superconducting quantum circuits have successfully demonstrated many of the requirements for quantum computing, including coherence levels that approach the thresholds for scaling. However, it remains challenging to couple a large number of circuit components through controllable channels while suppressing any other interactions. We propose a hardware platform intended to address these challenges, which combines the advantages of integrated circuit fabrication and long coherence times achievable in three-dimensional circuit quantum electrodynamics (3D cQED). This multilayer microwave integrated quantum circuit (MMIQC) platform provides a path toward the realization of increasingly complex superconducting devices in pursuit of a scalable quantum computer.

  2. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    E-print Network

    Thornton, Mitchell

    is the process of finding design errors in a model of an electronic Integrated Circuit (IC) beforeIntegrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits Lun Li, Mitchell A. Thornton, Stephen A. Szygenda Dept. of Computer Science and Engineering

  3. Microwave GaAs Integrated Circuits On Quartz Substrates

    NASA Technical Reports Server (NTRS)

    Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

    1994-01-01

    Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

  4. Integrated digital inverters based on two-dimensional anisotropic ReS2 field-effect transistors

    PubMed Central

    Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching-Hwa; Huang, Ying-Sheng; Cao, Zhengyi; Wang, Laiguo; Li, Aidong; Zeng, Junwen; Song, Fengqi; Wang, Xinran; Shi, Yi; Yuan, Hongtao; Hwang, Harold Y.; Cui, Yi; Miao, Feng; Xing, Dingyu

    2015-01-01

    Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS2) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS2 field-effect transistors, which exhibit competitive performance with large current on/off ratios (?107) and low subthreshold swings (100?mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconducting materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS2 anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications. PMID:25947630

  5. Integrated digital inverters based on two-dimensional anisotropic ReS2 field-effect transistors.

    PubMed

    Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching-Hwa; Huang, Ying-Sheng; Cao, Zhengyi; Wang, Laiguo; Li, Aidong; Zeng, Junwen; Song, Fengqi; Wang, Xinran; Shi, Yi; Yuan, Hongtao; Hwang, Harold Y; Cui, Yi; Miao, Feng; Xing, Dingyu

    2015-01-01

    Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS2) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS2 field-effect transistors, which exhibit competitive performance with large current on/off ratios (?10(7)) and low subthreshold swings (100?mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconducting materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS2 anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications. PMID:25947630

  6. Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

    PubMed

    Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

    2015-10-27

    Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%. PMID:26370537

  7. Thin-film transistor circuits on large-area spherical surfaces P. I. Hsu, R. Bhattacharya, H. Gleskova, M. Huang, Z. Xi, Z. Suo, S. Wagner, and

    E-print Network

    Suo, Zhigang

    of stiff circuit islands fabricated on deformable foil substrates is a promising approach to electronics for publication 3 July 2002 We report amorphous silicon (a-Si:H) thin-film transistors TFTs fabricated on a planar.1063/1.1502199 There is growing interest in flexible electronics, includ- ing foldable displays, sensor skins, and electronic

  8. Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

    SciTech Connect

    Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M.

    2013-11-25

    We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

  9. Integrated Circuit Failure Analysis Expert System

    Energy Science and Technology Software Center (ESTSC)

    1995-10-03

    The software assists a failure analyst performing failure anaysis on intergrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  10. Integration of silk protein in organic and light-emitting transistors.

    PubMed

    Capelli, R; Amsden, J J; Generali, G; Toffanin, S; Benfenati, V; Muccini, M; Kaplan, D L; Omenetto, F G; Zamboni, R

    2011-07-01

    We present the integration of a natural protein into electronic and optoelectronic devices by using silk fibroin as a thin film dielectric in an organic thin film field-effect transistor (OFET) ad an organic light emitting transistor device (OLET) structures. Both n- (perylene) and p-type (thiophene) silk-based OFETs are demonstrated. The measured electrical characteristics are in agreement with high-efficiency standard organic transistors, namely charge mobility of the order of 10(-2) cm(2)/Vs and on/off ratio of 10(4). The silk-based optolectronic element is an advanced unipolar n-type OLET that yields a light emission of 100nW. PMID:22899899

  11. Flexible low-voltage organic integrated circuits with megahertz switching frequencies (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Zschieschang, Ute; Takimiya, Kazuo; Zaki, Tarek; Letzkus, Florian; Richter, Harald; Burghartz, Joachim N.; Klauk, Hagen

    2015-09-01

    A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.

  12. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  13. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  14. Development of integrated thermionic circuits for high-temperature applications

    SciTech Connect

    McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.

    1981-01-01

    This report describes a class of microminiature, thin film devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500/sup 0/C. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time (greater than 11,000 hours).

  15. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  16. Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes

    NASA Astrophysics Data System (ADS)

    Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng

    2014-11-01

    In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 ?s. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr05471g

  17. 796 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 7, NO. 6, DECEMBER 2013 Integrated Circuits for Volumetric Ultrasound

    E-print Network

    Khuri-Yakub, Butrus T. "Pierre"

    capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges array, capacitive micromachined ultrasonic transducer (CMUT), flip-chip bonding, integrated circuits Circuits for Volumetric Ultrasound Imaging With 2-D CMUT Arrays Anshuman Bhuyan, Student Member, IEEE, Jung

  18. Integrated Circuit For Simulation Of Neural Network

    NASA Technical Reports Server (NTRS)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  19. III–V compound semiconductor transistors—from planar to nanowire structures

    E-print Network

    Riel, Heike

    Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics ...

  20. Test Circuits for 3-D Systems Integration Ioannis Savidis and Eby G. Friedman

    E-print Network

    Friedman, Eby G.

    Test Circuits for 3-D Systems Integration Ioannis Savidis and Eby G. Friedman Department circuit focuses on power delivery in 3-D integrated systems. The objective of this test circuit of each plane within a three plane 3- D integrated system. A microphotograph of the second test circuit

  1. A low-cost Method for Test and Speed Characterization of Digital Integrated Circuit Prototypes

    E-print Network

    Elrabaa, Muhammad E. S.

    A low-cost Method for Test and Speed Characterization of Digital Integrated Circuit Prototypes for the high-speed test and characterization of digital integrated circuit (IC) prototypes has been developed . Keywords: Circuit Intellectual Property, Integrated Circuits, Characterization and Testing. 1. INTRODUCTION

  2. Technology characteristics and concerns arising in the design and fabrication of an entire signal processor using gallium arsenide integrated circuits

    NASA Astrophysics Data System (ADS)

    Naused, Barbara A.; Samson, Mark L.; Schwab, Daniel J.; Gilbert, Barry K.

    Various GaAs transistor and gate technologies that have been developed since 1980 are analyzed. The characteristics of GaAs logic gates and ICs and the buffered FET logic, Shottky diode FET logic, direct coupled FET logic, and heterojunction integrated injection logic used to implement GaAs gate arrays of LSI complexity are described. The use of digital GaAs in a complex target signal processor, the Advanced Onboard Signal Processor (AOSP), is studied. Data from the testing of GaAs components for the AOSP at the wafer probe, package, and assembled circuit board levels are examined.

  3. A PWM transistor inverter for an ac electric vehicle drive

    NASA Technical Reports Server (NTRS)

    Slicker, J. M.

    1981-01-01

    A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

  4. Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

    NASA Astrophysics Data System (ADS)

    Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

    2015-03-01

    This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

  5. Organic thin-film transistors for circuits in a foundry: process, charge transport phenomena and device library

    NASA Astrophysics Data System (ADS)

    Pankalla, Sebastian; Ganz, Simone; Spiehl, Dieter; Dörsam, Edgar; Glesner, Manfred

    2013-09-01

    For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.

  6. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-23

    ...Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...importation of certain large scale integrated circuit semiconductor chips and products...Freescale Semiconductor Xiqing Integrated Semiconductor...

  7. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-03-17

    ...Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...importation of certain large scale integrated circuit semiconductor chips and products...Freescale Semiconductor Xiqing Integrated Semiconductor...

  8. Silica Integrated Optical Circuits Based on Glass Photosensitivity

    NASA Technical Reports Server (NTRS)

    Abushagur, Mustafa A. G.

    1999-01-01

    Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

  9. Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature.

    PubMed

    Pattanasattayavong, Pichaya; Yaacobi-Gross, Nir; Zhao, Kui; Ndjawa, Guy Olivier Ngongang; Li, Jinhua; Yan, Feng; O'Regan, Brian C; Amassian, Aram; Anthopoulos, Thomas D

    2013-03-13

    The wide bandgap and highly transparent inorganic compound copper(I) thiocyanate (CuSCN) is used for the first time to fabricate p-type thin-film transistors processed from solution at room temperature. By combining CuSCN with the high-k relaxor ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm(2) V(-1) s(-1) . By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. PMID:23280854

  10. Healing of voids in the aluminum metallization of integrated circuit chips

    NASA Technical Reports Server (NTRS)

    Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas R.

    1990-01-01

    The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.

  11. Thermally-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I. (Albuquerque, NM)

    2000-01-01

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  12. Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

    NASA Technical Reports Server (NTRS)

    Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

    2011-01-01

    Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

  13. Single Event Transients in Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed to transients. In some cases, such events produced resets by falsely triggering circuits designed to protect against over- voltage or over-current. On at least three occasions, transients caused satellites to switch into "safe mode" in which most of the systems on board the satellites were powered down for an extended period. By the time the satellites were reconfigured and returned to full operational state, much scientific data had been lost. Fortunately, no permanent damage occurred in any of the systems and they were all successfully re-activated.

  14. Radio Frequency Identification iny integrated circuits equipped with radio an-

    E-print Network

    Han, Richard Y.

    -called Radio Frequency Identification tags--better known as RFID--could help stamp out drug counterfeitingRadio Frequency Identification T iny integrated circuits equipped with radio an- tennas are fast,mostpopularpresscover- age of RFID tags has centered on the technology's po- tential for tracking consumers without

  15. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1988-04-20

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

  16. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  17. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, David R. (Albuquerque, NM)

    1989-01-01

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  18. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    DOEpatents

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  19. Reliability Without Hermeticity (RWOH) for Integrated Circuits (IC)

    NASA Astrophysics Data System (ADS)

    1994-03-01

    This effort establishes baseline performance data for an inorganic (ceramic) protective coating over integrated circuits in plastic packages. Severe and differentiating environmental stress testing demonstrated protection against humidity beginning to approach the protection offered by hermetic packaging. Advantages in size and weight are inherent in the technology.

  20. An integrated circuit/packet switched videoconferencing system

    SciTech Connect

    Kippenhan, H.A. Jr.; Lidinsky, W.P.; Roediger, G.A.; Watts, T.A.

    1995-11-01

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible videoconferencing system for use by high energy physics collaborations and others wishing to use videoconferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of videoconferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEP`s needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Videoconferencing Using PAckets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched videoconferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet videoconferencing interface. Augmentation is centered in another subsystem called MSB (Multiport multisession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system.

  1. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

  2. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  3. Focal plane infrared readout circuit

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2002-01-01

    An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

  4. Integrated optical circuits for RF spectrum analysis

    NASA Astrophysics Data System (ADS)

    Chen, B.; Joseph, T. R.; Lee, J. Y.; Ranganath, T. R.

    1980-01-01

    This paper describes the integrated-optic implementation of a Bragg spectrum analyzer that employs the interaction between a coherent optical guided wave and a surface acoustic wave to determine the power spectral density of the input. The integrated-optic spectrum analyzer consists of an injection laser diode, a thin-film optical waveguide, waveguide lenses, a surface-acoustic-wave transducer, and a linear detector array with CCD readout. Design principles are given for selecting component parameters such as optical beam width, detector cell size, lens aperture and focal length, and acoustic transducer design so as to obtain specific RF resolution, spurious level, and signal-to-noise ratio. Design parameters are presented for a 750- to 1250-MHz spectrum analyzer with a resolution of 4 MHz and a 40-dB dynamic range. Also described in the paper is the development of state-of-the-art component technology for the spectrum analyzer.

  5. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    NASA Technical Reports Server (NTRS)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the switch and the inductor configuration. In the fault condition, both the resistor and the inductor react immediately. The resistor reacts by allowing more current to flow and dropping the voltage. Initially, the inductor reacts by dropping the voltage, and then by not allowing the current to change. When the comparator detects the drop in voltage, it opens the switch, thus preventing any further current flow. The inductor alone is not sufficient protection, because after the voltage drop has settled, the inductor would then allow the current to change, in this example, the current would be 3.7 A. In the fault condition, the resistor is flowing 200 mA until the fuse blows (anywhere from 1 ms to 100 s), while the switch and inductor combination is flowing about 2 A test current while monitoring for the fault to be corrected. Finally, as an additional safety feature, the circuit can be configured to hold the switch opened until both the load and source are disconnected.

  6. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    PubMed

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ?7 kHz bandwidth, ring oscillators with <10 ?s stage delays, and NAND and NOR logic gates. PMID:26407206

  7. Waveguide single-photon detectors for integrated quantum photonic circuits

    E-print Network

    J. P. Sprengers; A. Gaggero; D. Sahin; S. Jahanmiri Nejad; F. Mattioli; R. Leoni; J. Beetz; M. Lermer; M. Kamp; S. Höfling; R. Sanjines; A. Fiore

    2011-08-25

    The generation, manipulation and detection of quantum bits (qubits) encoded on single photons is at the heart of quantum communication and optical quantum information processing. The combination of single-photon sources, passive optical circuits and single-photon detectors enables quantum repeaters and qubit amplifiers, and also forms the basis of all-optical quantum gates and of linear-optics quantum computing. However, the monolithic integration of sources, waveguides and detectors on the same chip, as needed for scaling to meaningful number of qubits, is very challenging, and previous work on quantum photonic circuits has used external sources and detectors. Here we propose an approach to a fully-integrated quantum photonic circuit on a semiconductor chip, and demonstrate a key component of such circuit, a waveguide single-photon detector. Our detectors, based on superconducting nanowires on GaAs ridge waveguides, provide high efficiency (20%) at telecom wavelengths, high timing accuracy (60 ps), response time in the ns range, and are fully compatible with the integration of single-photon sources, passive networks and modulators.

  8. InGaAs/InP heterojunction bipolar transistors for ultra-low power circuit applications

    SciTech Connect

    Chang, P.C.; Baca, A.G.; Hafich, M.J.; Ashby, C.I.

    1998-08-01

    For many modern day portable electronic applications, low power high speed devices have become very desirable. Very high values of f{sub T} and f{sub MAX} have been reported with InGaAs/InP heterojunction bipolar transistors (HBTs), but only under high bias and high current level operating conditions. An InGaAs/InP ultra-lowpower HBT with f{sub MAX} greater than 10 GHz operating at less than 20 {micro}A has been reported for the first time in this work. The results are obtained on a 2.5 x 5 {micro}m{sup 2} device, corresponding to less than 150 A/cm{sup 2} of current density. These are the lowest current levels at which f{sub MAX} {ge} 10 GHz has been reported.

  9. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-06

    ...importation of certain semiconductor integrated circuits using tungsten metallization and...Manufacturing Corporation of China; Integrated Device Technology, Inc. of San...Court of Appeals for the Federal Circuit (``Federal...

  10. 75 FR 65654 - In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-10-26

    ...No. 337-TA-709] In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including...within the United States after importation of certain integrated circuits, chipsets, and products containing same...

  11. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-12

    ...COMMISSION [Investigation No. 337-TA-851] Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting...within the United States after importation of certain integrated circuit packages provided with multiple...

  12. 75 FR 49524 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-13

    ...Investigation No. 337-TA-709] In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...within the United States after importation of certain integrated circuits, chipsets, and products containing same...

  13. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-06-10

    ...Investigation No. 337-TA-709] In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...within the United States after importation of certain integrated circuits, chipsets, and products containing same...

  14. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-29

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt of... received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products Containing Same... importation, and the sale within the United States after importation of certain semiconductor...

  15. Millimeter-wave and terahertz integrated circuit antennas

    NASA Technical Reports Server (NTRS)

    Rebeiz, Gabriel M.

    1992-01-01

    This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

  16. Transistor Basics II PHYS 309 Name

    E-print Network

    Herman, Rhett

    Transistor Basics II PHYS 309 Name: A. Introduction The two basic types of transistors have specific functions related to the transistor's ability to regulate the current that flow through so you can immediately tell the type of the transistor. A typical transistor circuit is shown

  17. Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

    SciTech Connect

    Dell'Erba, Giorgio; Natali, Dario; Luzio, Alessandro; Caironi, Mario E-mail: yynoh@dongguk.edu; Noh, Yong-Young E-mail: yynoh@dongguk.edu

    2014-04-14

    Ambipolar semiconducting polymers, characterized by both high electron (?{sub e}) and hole (?{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with ?{sub h}?=?0.29 cm{sup 2}/V s and ?{sub e}?=?0.001 cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with ?{sub e}?=?0.12 cm{sup 2}/V s and ?{sub h}?=?8 ×?10{sup ?4}?cm{sup 2}/V?s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

  18. Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors.

    PubMed

    Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; Li, Liang; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I; Alshareef, H N; Zhang, Yafei; Zhang, X X

    2014-08-01

    Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. PMID:24965261

  19. Carbon nanotubes for interconnects in integrated circuits

    NASA Astrophysics Data System (ADS)

    Dijon, Jean

    2011-03-01

    Carbon nanotubes are one of the materials that may be used for advanced interconnects beyond the 16nm node thanks to there extreme resistance to electro migration and to bottom up approach which allow to grow them in tiny holes with very high aspect ratio. The resistance of a via with area A and height h filled with CNT is expressed by Rvia =rq/+ rsh + rc Adt where rq, rs, rc are respectively the 6.5 k ? quantum resistance, the scattering resistance and the contact resistances of one tube. To be competitive with copper via resistance, a large density d t of carbon walls have to be paralleled. Following ITRS needs a density of 2 or 3 1013 cm-2 conducting CNT walls have to be obtained. This optimum wall density requests the growth of highly packed few nanometre diameter CNTs. Such density has been the main bottleneck for the development of CNT interconnects. Recently ultra high density integration scheme have been demonstrated and for the first time wall density close to the requested one have been integrated in devices. Such density comes from the development on conductive substrates of a CNT growth mode normally used to obtain forests of small tube diameter on insulating substrate like alumina. With this mode, CNTs are grown with base growth mode which is the mode requested for SWCNT or DWCNT thus by continuity it will be possible to increase the density still further by increasing the density of catalyst particles. Our bottom metal of choice is AlCu with iron as catalyst. With this system tube contact resistance between 104 to 106 Ohm have been measured on blanket AlCu substrates. This resistance must be decreased by one or two order of magnitude while increasing further CNT density. In this paper we will present our last integration developments and the role of plasma pre-treatment of the iron aluminium interface in order to decrease the contact resistance. We will show that the bottom profile of via has a major impact on the quality of CNT growing in the holes and discuss future evolutions of this technology.

  20. 6-1 Research Centers MTL Annual Research Report 2008 Center for Integrated Circuits and Systems

    E-print Network

    Reif, Rafael

    6-1 Research Centers MTL Annual Research Report 2008 Center for Integrated Circuits and Systems Professor Hae-Seung Lee, Director The Center for Integrated Circuits and Systems (CICS) at MIT, established believe that it will have a lasting impact on the field of integrated circuits and systems. Research

  1. Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube Networks for Digital, Analog, and

    E-print Network

    Javey, Ali

    Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube integrated circuits or active-matrix backplanes for display and sensor applications. Amorphous silicon and sophisticated flexible integrated circuits such as flip-flop and decoder have been demonstrated.16,17 Despite

  2. Publish date: 06/27/2011 ECE 4321: Applications of Analog Integrated Circuits

    E-print Network

    Gelfond, Michael

    Publish date: 06/27/2011 ECE 4321: Applications of Analog Integrated Circuits Credit / Contact, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000. Catalog description: Principles involved in designing analog integrated circuits. Device physics, small-signal and large-signal models. Biasing

  3. 75 FR 43553 - In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-26

    ... In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same; Notice..., and sale within the United States after importation of certain encapsulated integrated circuit devices... encapsulated integrated circuit devices and products contains same in connection with claims 1- 4, 7, 17,...

  4. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-01

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of... the sale within the United States after importation of certain semiconductor integrated circuit... semiconductor integrated circuit devices and products containing same that infringe one or more of claims 1,...

  5. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-19

    ... Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice of... certain digital televisions containing integrated circuit devices and components thereof by reason of... integrated circuit devices and components thereof that infringe one or more of claims 9, 10, 12, 31, 32,...

  6. Developing design rules to avert cracking and debonding in integrated circuit structures

    E-print Network

    Suo, Zhigang

    Developing design rules to avert cracking and debonding in integrated circuit structures X.H. Liua 26 January 2000 Abstract In an integrated circuit, stresses come from many sources (e.g., dierential based on two attributes of integrated circuits. First, high tensile sress is generated by internal mis

  7. Publish date: 06/27/2011 ECE 4310: Introduction to Very Large Scale Integrated Circuit Design

    E-print Network

    Gelfond, Michael

    Publish date: 06/27/2011 ECE 4310: Introduction to Very Large Scale Integrated Circuit Design: B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001. Catalog description: ECE introduction to very large-scale integrated design of circuits and devices. Geometrical patterns

  8. 78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-02-14

    ... COMMISSION Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of... received a complaint entitled Certain Integrated Circuit Devices and Products Containing the Same, DN 2938..., and the sale within the United States after importation of certain integrated circuit devices...

  9. 77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-23

    ... COMMISSION Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation... integrated circuit chips and products containing the same by reason of infringement of certain claims of U.S... importation of certain integrated circuit chips and products containing the same that infringe one or more...

  10. 77 FR 39735 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-05

    ... COMMISSION Certain Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products... the sale within the United States after importation of certain integrated circuit packages provided... integrated circuit packages provided with multiple heat-conducting paths and products containing same...

  11. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  12. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, Anthony F. (Berkeley, CA); Malba, Vincent (Livermore, CA)

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  13. Monolithically integrated, flexible display of polymer-dispersed liquid crystal driven by rubber-stamped organic thin-film transistors

    SciTech Connect

    Mach, P.; Rodriguez, S. J.; Nortrup, R.; Wiltzius, P.; Rogers, J. A.

    2001-06-04

    This letter describes the monolithic integration of rubber-stamped thin-film organic transistors with polymer-dispersed liquid crystals (PDLCs) to create a multipixel, flexible display with plastic substrates. We report the electro-optic switching behavior of the PDLCs as driven by the organic transistors, and we show that our displays operate robustly under flexing and have a contrast comparable to that of newsprint. {copyright} 2001 American Institute of Physics.

  14. Organic printed photonics: From microring lasers to integrated circuits

    PubMed Central

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-01-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

  15. Organic printed photonics: From microring lasers to integrated circuits.

    PubMed

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

  16. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  17. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  18. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  19. Impact of electrostatics on IC (Integrated Circuit) fabrication

    NASA Astrophysics Data System (ADS)

    Denson, W. K.; Turner, T.

    1983-09-01

    Integrated circuit fabrication processes inherently involve materials with a high propensity of triboelectric charge generation. This report details the results of a study in which the intent was: (1) to determine how electrostatic charges can catastrophically dame integrated circuits during their fabrication, and (2) to investigate the effect these charges have on individual fabrication processes. Possible reliability implications of the presence of electric charges during fabrication are also hypothesized. An experiment was also carried out to determine the susceptibility of IC's in wafer form. In these tests, devices were stressed at various levels and then electrically tested to determine their functionality. Additionally, the susceptibility modes of devices in wafer form were compared to those in packaged form.

  20. Transcap: A new integrated hybrid supercapacitor and electrolyte-gated transistor device (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Santato, Clara

    2015-10-01

    The boom in multifunctional, flexible, and portable electronics and the increasing need of low-energy cost and autonomy for applications ranging from wireless sensor networks for smart environments to biomedical applications are triggering research efforts towards the development of self-powered sustainable electronic devices. Within this context, the coupling of electronic devices (e.g. sensors, transistors) with small size energy storage systems (e.g. micro-batteries or micro-supercapacitors) is actively pursued. Micro-electrochemical supercapacitors are attracting much attention in electronics for their capability of delivering short power pulses with high stability over repeated charge/discharge cycling. For their high specific pseudocapacitance, electronically conducting polymers are well known as positive materials for hybrid supercapacitors featuring high surface carbon negative electrodes. The processability of both polymer and carbon is of great relevance for the development of flexible miniaturised devices. Electronically conducting polymers are even well known to feature an electronic conductivity that depends on their oxidation (p-doped state) and that it is modulated by the polymer potential. This property and the related pseudocapacitive response make polymer very attracting channel materials for electrolyte-gated (EG) transistors. Here, we propose a novel concept of "Trans-capacitor", an integrated device that exhibits the storage properties of a polymer/carbon hybrid supercapacitor and the low-voltage operation of an electrolyte-gated transistor.

  1. Monolithic microwave integrated circuit technology for advanced space communication

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Romanofsky, Robert R.

    1988-01-01

    Future Space Communications subsystems will utilize GaAs Monolithic Microwave Integrated Circuits (MMIC's) to reduce volume, weight, and cost and to enhance system reliability. Recent advances in GaAs MMIC technology have led to high-performance devices which show promise for insertion into these next generation systems. The status and development of a number of these devices operating from Ku through Ka band will be discussed along with anticipated potential applications.

  2. Aperture efficiency of integrated-circuit horn antennas

    NASA Technical Reports Server (NTRS)

    Guo, Yong; Lee, Karen; Stimson, Philip; Potter, Kent; Rutledge, David

    1991-01-01

    The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent at 93 GHz. This is sufficient for use in many applications which now use machined waveguide horns.

  3. Tuning the threshold voltage in electrolyte-gated organic field-effect transistors.

    PubMed

    Kergoat, Loïg; Herlogsson, Lars; Piro, Benoit; Pham, Minh Chau; Horowitz, Gilles; Crispin, Xavier; Berggren, Magnus

    2012-05-29

    Low-voltage organic field-effect transistors (OFETs) promise for low power consumption logic circuits. To enhance the efficiency of the logic circuits, the control of the threshold voltage of the transistors are based on is crucial. We report the systematic control of the threshold voltage of electrolyte-gated OFETs by using various gate metals. The influence of the work function of the metal is investigated in metal-electrolyte-organic semiconductor diodes and electrolyte-gated OFETs. A good correlation is found between the flat-band potential and the threshold voltage. The possibility to tune the threshold voltage over half the potential range applied and to obtain depletion-like (positive threshold voltage) and enhancement (negative threshold voltage) transistors is of great interest when integrating these transistors in logic circuits. The combination of a depletion-like and enhancement transistor leads to a clear improvement of the noise margins in depleted-load unipolar inverters. PMID:22586088

  4. Tuning the threshold voltage in electrolyte-gated organic field-effect transistors

    PubMed Central

    Kergoat, Loïg; Herlogsson, Lars; Piro, Benoit; Pham, Minh Chau; Horowitz, Gilles; Crispin, Xavier; Berggren, Magnus

    2012-01-01

    Low-voltage organic field-effect transistors (OFETs) promise for low power consumption logic circuits. To enhance the efficiency of the logic circuits, the control of the threshold voltage of the transistors are based on is crucial. We report the systematic control of the threshold voltage of electrolyte-gated OFETs by using various gate metals. The influence of the work function of the metal is investigated in metal-electrolyte-organic semiconductor diodes and electrolyte-gated OFETs. A good correlation is found between the flat-band potential and the threshold voltage. The possibility to tune the threshold voltage over half the potential range applied and to obtain depletion-like (positive threshold voltage) and enhancement (negative threshold voltage) transistors is of great interest when integrating these transistors in logic circuits. The combination of a depletion-like and enhancement transistor leads to a clear improvement of the noise margins in depleted-load unipolar inverters. PMID:22586088

  5. Tunable conduction type of solution-processed germanium nanoparticle based field effect transistors and their inverter integration.

    PubMed

    Meric, Zeynep; Mehringer, Christian; Karpstein, Nicolas; Jank, Michael P M; Peukert, Wolfgang; Frey, Lothar

    2015-09-14

    In this work we demonstrate the fabrication of germanium nanoparticle (NP) based electronics. The whole process chain from the nanoparticle production up to the point of inverter integration is covered. Ge NPs with a mean diameter of 33 nm and a geometric standard deviation of 1.19 are synthesized in the gas phase by thermal decomposition of GeH4 precursor in a seeded growth process. Dispersions of these particles in ethanol are employed to fabricate thin particulate films (60 to 120 nm in thickness) on substrates with a pre-patterned interdigitated aluminum electrode structure. The effect of temperature treatment, polymethyl methacrylate encapsulation and alumina coating by plasma-assisted atomic layer deposition (employing various temperatures) on the performance of these layers as thin film transistors (TFTs) is investigated. This coating combined with thermal annealing delivers ambipolar TFTs which show an Ion/Ioff ratio in the range of 10(2). We report fabrication of n-type, p-type or ambipolar Ge NP TFTs at maximum temperatures of 450 °C. For the first time, a circuit using two ambipolar TFTs is demonstrated to function as a NOT gate with an inverter gain of up to 4 which can be operated at room temperature in ambient air. PMID:26256208

  6. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    SciTech Connect

    Rath, P.; Ummethala, S.; Pernice, W. H. P.; Diewald, S.; Lewes-Malandrakis, G.; Brink, D.; Heidrich, N.; Nebel, C.

    2014-12-22

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here, we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115?MHz and observe the nanomechanical response also under ambient conditions.

  7. Integrated circuits for accurate linear analogue electric signal processing

    NASA Astrophysics Data System (ADS)

    Huijsing, J. H.

    1981-11-01

    The main lines in the design of integrated circuits for accurate analog linear electric signal processing in a frequency range including DC are investigated. A categorization of universal active electronic devices is presented on the basis of the connections of one of the terminals of the input and output ports to the common ground potential. The means for quantifying the attributes of four types of universal active electronic devices are included. The design of integrated operational voltage amplifiers (OVA) is discussed. Several important applications in the field of general instrumentation are numerically evaluated, and the design of operatinal floating amplifiers is presented.

  8. Design of self-checking N-MOS (H-MOS) integrated circuits

    NASA Astrophysics Data System (ADS)

    Nicolaidis, M.; Courtois, B.

    1984-10-01

    The design of self-checking N metal oxide semiconductor circuits is discussed. Two types of test are planned for the use of these circuits: on-line testing to detect failures during the function run of software; and off-line testing, with an emphasis on detection and localization for maintainability. The design of these circuits is based on transistor level fault hypotheses. The design of a functional part, the design of a checker, and procedures/design rules for a design for maintainability are addressed.

  9. A Graphene Quantum Dot with a Single Electron Transistor as Integrated Charge Sensor

    E-print Network

    Ling-Jun Wang; Gang Cao; Tao Tu; Hai-Ou Li; Cheng Zhou; Xiao-Jie Hao; Zhan Su; Guang-Can Guo; Guo-Ping Guo; Hong-Wen Jiang

    2010-08-28

    We have developed an etching process to fabricate a quantum dot and a nearby single electron transistor as a charge detector in a single layer graphene. The high charge sensitivity of the detector is used to probe Coulomb diamonds as well as excited spectrum in the dot, even in the regime where the current through the quantum dot is too small to be measured by conventional transport means. The graphene based quantum dot and integrated charge sensor serve as an essential building block to form a solid-state qubit in a nuclear-spin-free quantum world.

  10. Pneumatic oscillator circuits for timing and control of integrated microfluidics

    PubMed Central

    Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

    2013-01-01

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

  11. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    PubMed

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-01

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

  12. Methodology for analysis of TSV stress induced transistor variation and circuit performance

    E-print Network

    Yu, Li

    As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal ...

  13. Design and status of the RF-digitizer integrated circuit

    NASA Technical Reports Server (NTRS)

    Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

    1991-01-01

    An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

  14. Integrating anatomy and function for zebrafish circuit analysis

    PubMed Central

    Arrenberg, Aristides B.; Driever, Wolfgang

    2013-01-01

    Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties—e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

  15. Few-electron quantum dot circuit with integrated charge read out J. M. Elzerman,1

    E-print Network

    Zumbühl, Dominik

    Few-electron quantum dot circuit with integrated charge read out J. M. Elzerman,1 R. Hanson,1 J. S of these types of quan- tum dots is that they are hard to integrate into circuits with a controllable coupling. The experiments demonstrate that this quantum dot circuit can serve as a good starting point for a scalable spin

  16. Sensory integration in mouse insular cortex reflects GABA circuit maturation

    PubMed Central

    Gogolla, Nadine; Takesian, Anne E.; Feng, Guoping; Fagiolini, Michela; Hensch, Takao K.

    2014-01-01

    SUMMARY Insular cortex (IC) contributes to a variety of complex brain functions, such as communication, social behavior and self-awareness through the integration of sensory, emotional and cognitive content. How the IC acquires its integrative properties remains unexplored. We compared the emergence of multisensory integration (MSI) in the IC of behaviorally distinct mouse strains. While adult C57BL/6 mice exhibited robust MSI, this capacity was impaired in the inbred BTBR T+tf/J mouse model of idiopathic autism. The deficit reflected a compromised postnatal pruning of cross-modal input by weakened inhibition. Transient pharmacological enhancement by diazepam in BTBR mice during an early sensitive period rescued GABA circuits and integration in the adult IC. Moreover, impaired MSI was common across three other monogenic models (GAD65, Shank3, Mecp2 knockout mice) displaying behavioral phenotypes and altered parvalbumin-positive GABA circuitry. Our findings offer developmental insight into a key neural circuit relevant to neuropsychiatric conditions like schizophrenia and autism. PMID:25088363

  17. Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits

    E-print Network

    Nagarajan, Raghavan

    2008-01-01

    Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power ...

  18. Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

    NASA Astrophysics Data System (ADS)

    Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2015-04-01

    Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

  19. Single Grain Si TFTs and Circuits based on the -Czochralski Process

    E-print Network

    Technische Universiteit Delft

    Single Grain Si TFTs and Circuits based on the µ-Czochralski Process PROEFSCHRIFT ter verkrijging begeleiding van dr. R. Ishihara. Vikas Rana Single Grain Si TFTs and Circuits based on the µ-Czochralski-laser crystallization, µ-Czochralski, grain filter, thin-film transistors, integrated circuits ISBN: Copyright 2006

  20. SiGe/Si Monolithically Integrated Amplifier Circuits

    NASA Technical Reports Server (NTRS)

    Katehi, Linda P. B.; Bhattacharya, Pallab

    1998-01-01

    With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

  1. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

    1995-01-01

    An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

  2. State-Transfer Simulation in Integrated Waveguide Circuits

    E-print Network

    Ludovico Latmiral; Carlo Di Franco; Paolo L. Mennea; Myungshik Kim

    2015-08-24

    Spin-chain models have been widely studied in terms of quantum information processes, for instance for the faithful transmission of quantum states. Here, we investigate the limitations of mapping this process to an equivalent one through a bosonic chain. In particular, we keep in mind experimental implementations, which the progress in integrated waveguide circuits could make possible in the very near future. We consider the feasibility of exploiting the higher dimensionality of the Hilbert space of the chain elements for the transmission of a larger amount of information, and the effects of unwanted excitations during the process. Finally, we exploit the information-flux method to provide bounds to the transfer fidelity.

  3. Universal nondestructive mm-wave integrated circuit test fixture

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert R. (inventor); Shalkhauser, Kurt A. (inventor)

    1990-01-01

    Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

  4. State-transfer simulation in integrated waveguide circuits

    NASA Astrophysics Data System (ADS)

    Latmiral, L.; Di Franco, C.; Mennea, P. L.; Kim, M. S.

    2015-08-01

    Spin-chain models have been widely studied in terms of quantum information processes, for instance for the faithful transmission of quantum states. Here, we investigate the limitations of mapping this process to an equivalent one through a bosonic chain. In particular, we keep in mind experimental implementations, which the progress in integrated waveguide circuits could make possible in the very near future. We consider the feasibility of exploiting the higher dimensionality of the Hilbert space of the chain elements for the transmission of a larger amount of information, and the effects of unwanted excitations during the process. Finally, we exploit the information-flux method to provide bounds to the transfer fidelity.

  5. Thermal resistance of VCSEL's bonded to integrated circuits

    SciTech Connect

    Pu, R.; Wilmsen, C.W.; Geib, K.M.; Choquette, K.D.

    1999-12-01

    The thermal resistance of vertical-cavity surface-emitting lasers (VCSEL's) flip chip bonded to GaAs substrates and CMOS integrated circuits has been measured. The measurements on GaAs show that if the bonding is done properly, the bonding does not add significantly to the thermal resistance. However, the SiO{sub 2} under the CMOS bonding pad can double the thermal resistance unless measures are taken to improve the thermal conductance of these layers. Finite element simulations indicate that the thermal resistance of bonded VCSEL's increases rapidly as the solder bond size and the aperture size decrease below {approximately}10 {micro}m.

  6. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  7. Stainless Steel NaK Circuit Integration and Fill Submission

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

  8. Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20 um SiGe heterojunction bipolar transistors and circuits.

    SciTech Connect

    Fritz, Karl; Irwin, Timothy J.; Niu, Guofu; Fodness, Bryan; Carts, Martin A.; Marshall, Paul W.; Reed, Robert A.; Gilbert, Barry; Randall, Barbara; Prairie, Jason; Riggs, Pam; Pickel, James C.; LaBel, Kenneth; Cressler, John D.; Krithivasan, Ramkumar; Dodd, Paul Emerson; Vizkelethy, Gyorgy

    2003-09-01

    Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallele-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

  9. Printing microchips Lithography is used in the manufacture of integrated circuits (ICs) to transfer circuit patterns from a mask to the silicon wafer.

    E-print Network

    circuit patterns from a mask to the silicon wafer. The number of transistors that can be put on a computer; - less than 70% reflectivity; - produces a 4 or 5 reduction of the mask's image on the wafer ­ 120 mm to illuminate the reflective reticle (mask); Wafer - thin slice of silicon or other

  10. A monolithic lead sulfide-silicon MOS integrated-circuit structure

    NASA Technical Reports Server (NTRS)

    Jhabvala, M. D.; Barrett, J. R.

    1982-01-01

    A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

  11. Local and nonlocal optically induced transparency effects in graphene-silicon hybrid nanophotonic integrated circuits.

    PubMed

    Yu, Longhai; Zheng, Jiajiu; Xu, Yang; Dai, Daoxin; He, Sailing

    2014-11-25

    Graphene is well-known as a two-dimensional sheet of carbon atoms arrayed in a honeycomb structure. It has some unique and fascinating properties, which are useful for realizing many optoelectronic devices and applications, including transistors, photodetectors, solar cells, and modulators. To enhance light-graphene interactions and take advantage of its properties, a promising approach is to combine a graphene sheet with optical waveguides, such as silicon nanophotonic wires considered in this paper. Here we report local and nonlocal optically induced transparency (OIT) effects in graphene-silicon hybrid nanophotonic integrated circuits. A low-power, continuous-wave laser is used as the pump light, and the power required for producing the OIT effect is as low as ?0.1 mW. The corresponding power density is several orders lower than that needed for the previously reported saturated absorption effect in graphene, which implies a mechanism involving light absorption by the silicon and photocarrier transport through the silicon-graphene junction. The present OIT effect enables low power, all-optical, broadband control and sensing, modulation and switching locally and nonlocally. PMID:25372937

  12. Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits

    SciTech Connect

    Keast, Craig

    2007-02-28

    Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

  13. Mixed signal custom integrated circuit development for physics instrumentation

    SciTech Connect

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S.

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  14. Fabrication of Planar Gradiometers by Using Superconducting Integrated Circuit Technology

    NASA Astrophysics Data System (ADS)

    Maezawa, Masaaki; Ying, Liliang; Gorwadkar, Sucheta; Zhang, Guofeng; Wang, Hai; Kong, Xiangyan; Wang, Zhen; Xie, Xiaoming

    We present fabrication technology for planar-type superconducting quantum interference devices (SQUIDs) comprising trilayer Nb/AlOx/Nb Josephson junctions and thin-film pick-up coils integrated on a single chip. A well-established superconducting integrated circuit technology that was originally developed for digital applications has been modified for developing SQUID fabrication processes with high reliability and controllability. Combination of two photolithography techniques, a high-resolution stepper and a large-shot-area mask aligner, has been introduced to fabricate fine-scale patterns such as 2-?m-square junctions and large-scale patterns such as 10-mm-square pick-up coils with a 2.5- or 3.0-cm baseline on the same chip. We successfully fabricated planar gradiometers and confirmed the operation with typical modulation amplitude of 50 ?V, achieving gradient field resolutions as small as 3.5 fT/Hz1/2cm.

  15. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  16. INTEGRATED MEMS STRUCTURES AND CMOS CIRCUITS FOR BIOELECTRONIC INTERFACE WITH SINGLE CELLS

    E-print Network

    Maryland at College Park, University of

    INTEGRATED MEMS STRUCTURES AND CMOS CIRCUITS FOR BIOELECTRONIC INTERFACE WITH SINGLE CELLS N each vial are integrated bio-amplifiers and/or other sensing circuits to form a biolab-on-a-chip. We. INTRODUCTION The integration of living cells with electronics can be used for fast medical diagnosis [1

  17. Investigation of high sensitivity radio-frequency readout circuit based on AlGaN/GaN high electron mobility transistor

    NASA Astrophysics Data System (ADS)

    Zhang, Xiao-Yu; Tan, Ren-Bing; Sun, Jian-Dong; Li, Xin-Xing; Zhou, Yu; Lü, Li; Qin, Hua

    2015-10-01

    An AlGaN/GaN high electron mobility transistor (HEMT) device is prepared by using a semiconductor nanofabrication process. A reflective radio-frequency (RF) readout circuit is designed and the HEMT device is assembled in an RF circuit through a coplanar waveguide transmission line. A gate capacitor of the HEMT and a surface-mounted inductor on the transmission line are formed to generate LC resonance. By tuning the gate voltage Vg, the variations of gate capacitance and conductance of the HEMT are reflected sensitively from the resonance frequency and the magnitude of the RF reflection signal. The aim of the designed RF readout setup is to develop a highly sensitive HEMT-based detector. Project supported by the National Natural Science Foundation of China (Grant No. 61107093), the Suzhou Science and Technology Project, China (Grant No. ZXG2012024), and the Youth Innovation Promotion Association, Chinese Academy of Sciences (Grant No. 2012243).

  18. Integrated circuit for processing a low-frequency signal from a seismic detector

    SciTech Connect

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A. Fedorov, R. A.

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  19. Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

    E-print Network

    Tan, Michael Loong P.; Lentaris, Georgios; Amaratunga, Gehan A. J.

    2012-08-19

    AbstractThe performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well...

  20. 2-Transistor Oscillator PHYS 309 Name

    E-print Network

    Herman, Rhett

    2-Transistor Oscillator PHYS 309 Name: A. Introduction--the circuit · One-week check: Build of your oscilloscope to investigate what's going on at the base and collector of each transistor (base and collector of the transistors). Writeup: · I will email you the 5Spice file for this circuit

  1. Experiments And Simulations On A Few-Electron Quantum Dot Circuit With Integrated Charge Read-Out

    E-print Network

    Experiments And Simulations On A Few-Electron Quantum Dot Circuit With Integrated Charge Read-Out R dot circuit, integrated with two quantum point contacts that serve as charge detectors. The circuit into circuits with a controllable coupling between the elements, although integration of vertical quantum dot

  2. Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

    PubMed

    Gao, Pingqi; Zhang, Qing

    2014-02-14

    Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc. PMID:24441981

  3. 77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-11-14

    ...INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-848] Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial Determination...

  4. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-09

    ...INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-806] Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice of Commission Determination Not To Review an Initial Determination...

  5. Multi-parameter extraction from SOI photonic integrated circuits using circuit simulation and evolutionary algorithms

    NASA Astrophysics Data System (ADS)

    Ruocco, A.; Fiers, M.; Vanslembrouck, M.; Van Vaerenbergh, T.; Bogaerts, W.

    2015-02-01

    We propose a procedure to extract multiple parameters from the spectral characteristic of a single photonic integrated circuit. We applied the method on high order silicon Mach-Zehnder lattice filters:1 these filters are realized by cascading delay stages and directional couplers of different length. Because of their cascaded nature and steep roll-off properties, these devices can be used to accurately extract properties of the waveguides and the directional couplers. The spectral transmission is measured between the inputs and the outputs. This result is compared to a full CAPHE optical circuit simulation with parametric behavioral models for the waveguide and the directional couplers. An evolutionary fitting algorithm based on the covariance matrix adaptation method is used to match the circuit simulation with the measurement. This black box approach gives us fast and accurate parameter extraction with a reduced number of iteration steps. The quadratic error between measurement and simulation of each iteration is used as feedback for the evolutionary algorithm that adapts the test values for the following step. The objective of our analysis is an accurate, wavelength-dependent model for the waveguide group index and the directional couplers. The proposed method has been used for wafer scale parameter extraction. Our fast method makes it possible to extract the parameters in real time, and correlate the functional parameters of the waveguides with process statistics collected during fabrication. The obtained parameters are in substantial agreement with the results of the simulations used in the design, and can be used to further improve behavioral models that correlate the manufacturing process data with the optical performance.

  6. The Stabilized Supralinear Network: A Unifying Circuit Motif Underlying Multi-Input Integration in

    E-print Network

    Columbia University

    -Input Integration in Sensory Cortex Highlights d A simple, unified circuit model of contextual modulationArticle The Stabilized Supralinear Network: A Unifying Circuit Motif Underlying Multi to the individual stimuli, but may facilitate for weak stimuli. Rubin et al. demonstrate a ``canonical'' circuit

  7. A kind of integrated method discuss of fOG signal processing circuit

    NASA Astrophysics Data System (ADS)

    Lu, Jun; Pan, Xin; Ying, Jiaju; Liu, Jie

    2014-12-01

    In view of the circuit miniaturization need in project application of fiber optic gyroscope(FOG), a new integrated technical scheme adopting system in package(SIP) for signal processing circuit of FOG was put forward. At first, the principle on signal processing circuit of FOG was analyzed, and the technical scheme adopting SIP based on low-temperature co-fired substrate technology was presented according to circuit characteristic and actual condition. Secondly, under the prerequisite of the concept introduction of SIP and LTCC, the SIP prototype of signal processing circuit of FOG was trialed produced?and it passed through the debug test. This SIP modular is an overall circuit complete integrated the signal processing circuit of FOG, and only a potentiometer and EPROM do not case outside. The testing results indicate that SIP is a kind of feasible scheme that carries out miniaturization for signal processing circuit of FOG.

  8. Application of self-testing integrated circuits to the safety of systems operation

    NASA Astrophysics Data System (ADS)

    Noraz, Serge

    The use of self-testing circuits, and specially self-checking circuits (able to detect instantaneously their own errors) to the high dependability integrated systems design, is investigated. The general fail-safe theory is discussed. An application involving a built-in-self testing interface able to transform the outputs of self-checking circuits into safe signals adequate to drive electromechanical actuators is presented. This interface allows the implementation in MOS technologies of strongly fail-safe VLSI (Very Large Scale Integration) circuits. All the practical considerations for the design of circuits are based on the analytical faults hypotheses bounded to the CMOS technology.

  9. Integrated Circuit Design in US High-Energy Physics

    E-print Network

    G. De Geronimo; D. Christian; C. Bebek; M. Garcia-Sciveres; H. Von der Lippe; G. Haller; A. A. Grillo; M. Newcomer

    2013-07-15

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

  10. Advanced polymer systems for optoelectronic integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Stengel, Kelly M. T.; Shacklette, Lawrence W.; Norwood, Robert A.; Xu, Chengzeng; Wu, Chengjiu; Yardley, James T.

    1997-01-01

    An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness, loss, and stability against yellowing and humidity. These monomers are intermiscible, providing for precise adjustment of the refractive index from 1.30 to 1.60. Waveguides are formed photolithographically, with the liquid monomer mixture polymerizing upon illumination in the UV via either mask exposure or laser direct-writing. A wide range of rigid and flexible substrates can be used, including glass, quartz, oxidized silicon, glass-filled epoxy printed circuit board substrate, and flexible polyimide film. We discuss the use of these materials on chips and on multi-chip modules (MCMs), specifically in transceivers where we adaptively produced waveguides on vertical-cavity surface-emitting lasers (VCSELs) embedded in transmitter MCMs and on high- speed photodetector chips in receiver MCMs. Light coupling from and to chips is achieved by cutting 45 degree mirrors using excimer laser ablation. The fabrication of our polymeric structures directly on the modules provides for stability, ruggedness, and hermeticity in packaging.

  11. Wireless multichannel biopotential recording using an integrated FM telemetry circuit.

    PubMed

    Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

    2005-09-01

    This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB. PMID:16200750

  12. An investigation of defect detection using random defect excitation and deterministic defect observation in complex integrated logic circuits 

    E-print Network

    Dworak, Jennifer

    2013-02-22

    aWhenever integrated circuits are manufactured, a certain percentage of those circuits will be defective. Defective circuits present problems for both the manufacturers who wish to maintain a good reputation with their customers and the consumers...

  13. Uncertain behaviours of integrated circuits improve computational performance

    PubMed Central

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  14. Plasmonic nanopatch array for optical integrated circuit applications.

    PubMed

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  15. Monolithic microwave integrated circuit devices for active array antennas

    NASA Technical Reports Server (NTRS)

    Mittra, R.

    1984-01-01

    Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

  16. Uncertain behaviours of integrated circuits improve computational performance.

    PubMed

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-Ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  17. Apparatus and method for defect testing of integrated circuits

    DOEpatents

    Cole, Jr., Edward I. (Albuquerque, NM); Soden, Jerry M. (Placitas, NM)

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  18. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  19. Development of a plan for automating integrated circuit processing

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

  20. Optimization of the hybrid silicon photonic integrated circuit platform

    NASA Astrophysics Data System (ADS)

    Heck, Martijn J. R.; Davenport, Michael L.; Srinivasan, Sudharsanan; Hulme, Jared; Bowers, John E.

    2013-03-01

    In the hybrid silicon platform, active III/V based components are integrated on a silicon-on-insulator photonic integrated circuit by means of wafer bonding. This is done in a self-aligned back-end process at low temperatures, making it compatible with CMOS-based silicon processing. This approach allows for low cost, high volume, high quality and reproducible chip fabrication. Such features make the hybrid silicon platform an attractive technology for applications like optical interconnects, microwave photonics and sensors operating at wavelengths around 1.3 ?m and 1.55 ?m. For these applications energy efficient operation is a key parameter. In this paper we present our efforts to bring the III/V components in the hybrid silicon platform, such as lasers and optical amplifiers, on par with the far more mature monolithic InP-based integration technology. We present our development work to increase hybrid silicon laser and amplifier wall-plug efficiency. This is done by careful optimization of III/V mesa geometry and guiding silicon waveguide width. We also discuss current injection efficiency and thermal performance. Furthermore we show the characterization of the low-loss and low-reflection mode converters that couple the hybrid III/V components to silicon waveguides. Reflections below -41 dB and passive loss of 0.3 dB per converter were obtained.

  1. Integrated Conditional Teleportation and Readout Circuit Based on a Photonic Crystal Single Chip

    E-print Network

    Durdu Ö. Güney; David A. Meyer

    2006-05-06

    We demonstrate the design of an integrated conditional quantum teleportation circuit and a readout circuit using a two-dimensional photonic crystal single chip. Fabrication and testing of the proposed quantum circuit can be accomplished with current or near future semiconductor process technology and experimental techniques. The readout part of our device, which has potential for independent use as an atomic interferometer, can also be used on its own or integrated with other compatible optical circuits to achieve atomic state detection. Further improvement of the device in terms of compactness and robustness could be achieved by integrating it with sources and detectors in the optical regime.

  2. Triple-mode single-transistor graphene amplifier and its applications.

    PubMed

    Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

    2010-10-26

    We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications. PMID:20939515

  3. Towards an automated design framework for large-scale photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Mingaleev, Sergei; Richter, André; Sokolov, Eugene; Arellano, Cristina; Koltchanov, Igor

    2015-05-01

    We present our approach towards an automated design framework for integrated photonics and optoelectronics, based on the experience of developing VPIcomponentMaker Photonic Circuits. We show that design tasks imposed by large-scale integrated photonics require introducing new "functional" types of model parameters and extending the hierarchical design approach with advanced parameter scripting capabilities. We discuss the requirements imposed by the need for seamless integration between circuit-level and device-level simulators, and illustrate our approach for the combination of VPIcomponentMaker Photonic Circuits and VPImodeDesigner. We show that accurate and scalable circuit-level modeling of large-scale photonic integrated circuits requires combination of several frequency- and time-domain simulation techniques (scattering-matrix assembly, transmission-line models, FIR and IIR digital filters, etc) within the same circuit simulation. We extend the scattering-matrix assembly approach for modeling linear electronic circuits, and motivate it being a viable alternative to the traditional modified nodal analysis approach employed in SPICE-like electronic circuit simulators. Further, we present our approach to support process design kits (PDK) for generic foundries of integrated photonics. It is based on the PDAFlow API which is designed to link different photonic simulation and design automation tools. In particular, it allows design and optimization of photonic circuits for a selected foundry with VPIcomponentMaker Photonic Circuits, and their subsequent export to PhoeniX OptoDesigner for layout verification and GDSII mask generation.

  4. Materials and devices for optical switching and modulation of photonic integrated circuits

    E-print Network

    Seneviratne, Dilan Anuradha

    2007-01-01

    The drive towards photonic integrated circuits (PIC) necessitates the development of new devices and materials capable of achieving miniaturization and integration on a CMOS compatible platform. Optical switching: fast ...

  5. Characterization and requirements for Cu-Cu bonds for three-dimensional integrated circuits

    E-print Network

    Tadepalli, Rajappa, 1979-

    2007-01-01

    Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and reduces global RC delay by increasing the device density per unit chip area. ...

  6. High-Performance InP Photonic Integrated Circuits Leif A. Johansson1,2

    E-print Network

    Rodwell, Mark J. W.

    in the development of high performance Indium Phosphide photonic integrated circuits for coherent communications FOR COHERENT OPTICAL COMMUNICATIONS LINKS Future iterations of 100G transceivers will need to meet power advanced photonic integrated circuit development for coherent optical communications links. This includes

  7. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-06-10

    ... Freescale Semiconductor, Inc. of Austin Texas. 75 FR 16837 (Mar. 29, 2010). The complaint alleged violations... In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions, media players, and...

  8. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-03-17

    ... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... the sale within the United States after importation of certain large scale integrated circuit... of Japan. 75 FR 24742-43. The complaint alleges violations of section 337 of the Tariff Act of...

  9. 78 FR 35051 - Certain Encapsulated Integrated Circuit Devices and Products Containing Same; Commission...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-11

    ... COMMISSION Certain Encapsulated Integrated Circuit Devices and Products Containing Same; Commission... after importation of certain encapsulated integrated circuit devices and products containing same in... December 19, 2003, based on a complaint filed by Amkor Technology Inc. (``Amkor''). See 68 FR 70836...

  10. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-03

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not... the sale within the United States after importation of certain semiconductor integrated circuit... FR 25747-48 (May 1, 2012). The complaint alleges violations of section 337 of the Tariff Act of...

  11. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-12

    ... COMMISSION Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products... integrated circuit packages provided with multiple heat-conducting paths and products containing same by..., California (collectively, ``ITRI''). 77 FR 39735 (Jul. 5, 2012). The complaint, as amended,...

  12. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-23

    ... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... importation of certain large scale integrated circuit semiconductor chips and products containing same by..., based on a complaint filed by Panasonic Corporation (``Panasonic'') of Japan. 75 FR 24742-43....

  13. 78 FR 16533 - Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-15

    ... COMMISSION Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation... importation, or the sale within the United States after importation of certain integrated circuit devices and... sale for importation, and/or the sale within the United States after importation of certain...

  14. Active Control and Digital Rights Management of Integrated Circuit IP Cores

    E-print Network

    Active Control and Digital Rights Management of Integrated Circuit IP Cores Yousra Alkabani CS control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP and specialization of design houses. Many fabless design companies, particularly the special- ized IP core designers

  15. Photonic integrated circuits based on novel glass waveguides and devices

    NASA Astrophysics Data System (ADS)

    Zhang, Yaping; Zhang, Deng; Pan, Weijian; Rowe, Helen; Benson, Trevor; Loni, Armando; Sewell, Phillip; Furniss, David; Seddon, Angela B.

    2006-04-01

    Novel materials, micro-, nano-scale photonic devices, and 'photonic systems on a chip' have become important focuses for global photonics research and development. This interest is driven by the rapidly growing demand for broader bandwidth in optical communication networks, and higher connection density in the interconnection area, as well as a wider range of application areas in, for example, health care, environment monitoring and security. Taken together, chalcogenide, heavy metal fluoride and fluorotellurite glasses offer transmission from ultraviolet to mid-infrared, high optical non-linearity and the ability to include active dopants, offering the potential for developing optical components with a wide range of functionality. Moreover, using single-mode large cross-section glass-based waveguides as an optical integration platform is an elegant solution for the monolithic integration of optical components, in which the glass-based structures act both as waveguides and as an optical bench for integration. We have previously developed a array of techniques for making photonic integrated circuits and devices based on novel glasses. One is fibre-on-glass (FOG), in which the fibres can be doped with different active dopants and pressed onto a glass substrate with a different composition using low-temperature thermal bonding under mechanical compression. Another is hot-embossing, in which a silicon mould is placed on top of a glass sample, and hot-embossing is carried out by applying heat and pressure. In this paper the development of a fabrication technique that combines the FOG and hot-embossing procedures to good advantage is described. Simulation and experimental results are presented.

  16. Design structure for in-system redundant array repair in integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  17. Interfacial electronic effects in functional biolayers integrated into organic field-effect transistors

    PubMed Central

    Angione, Maria Daniela; Cotrone, Serafina; Magliulo, Maria; Mallardi, Antonia; Altamura, Davide; Giannini, Cinzia; Cioffi, Nicola; Sabbatini, Luigia; Fratini, Emiliano; Baglioni, Piero; Scamarcio, Gaetano; Palazzo, Gerardo; Torsi, Luisa

    2012-01-01

    Biosystems integration into an organic field-effect transistor (OFET) structure is achieved by spin coating phospholipid or protein layers between the gate dielectric and the organic semiconductor. An architecture directly interfacing supported biological layers to the OFET channel is proposed and, strikingly, both the electronic properties and the biointerlayer functionality are fully retained. The platform bench tests involved OFETs integrating phospholipids and bacteriorhodopsin exposed to 1–5% anesthetic doses that reveal drug-induced changes in the lipid membrane. This result challenges the current anesthetic action model relying on the so far provided evidence that doses much higher than clinically relevant ones (2.4%) do not alter lipid bilayers’ structure significantly. Furthermore, a streptavidin embedding OFET shows label-free biotin electronic detection at 10 parts-per-trillion concentration level, reaching state-of-the-art fluorescent assay performances. These examples show how the proposed bioelectronic platform, besides resulting in extremely performing biosensors, can open insights into biologically relevant phenomena involving membrane weak interfacial modifications. PMID:22493224

  18. 76 FR 19174 - In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated Medical Resources...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-04-06

    ...500-1 In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated Medical Resources, Inc...concerning the securities of Circuit Systems, Inc. because...concerning the securities of Integrated Medical Resources,...

  19. Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1984-01-01

    Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

  20. Effects of Ambient Air and Temperature on Ionic Gel Gated Single-Walled Carbon Nanotube Thin-Film Transistor and Circuits.

    PubMed

    Li, Huaping; Zhou, Lili

    2015-10-21

    Single-walled carbon nanotube thin-film transistor (SWCNT TFT) and circuits were fabricated by fully inkjet printing gold nanoparticles as source/drain electrodes, semiconducting SWCNT thin films as channel materials, PS-PMMA-PS/EMIM TFSI composite gel as gate dielectrics, and PEDOT/PSS as gate electrodes. The ionic gel gated SWCNT TFT shows reversible conversion from p-type transistor behavior in air to ambipolar features under vacuum due to reversible oxygen doping in semiconducting SWCNT thin films. The threshold voltages of ionic gel gated SWCNT TFT and inverters are largely shifted to the low value (0.5 V for p-region and 1.0 V for n-region) by vacuum annealing at 140 °C to exhausively remove water that is incorporated in the ionic gel as floating gates. The vacuum annealed ionic gel gated SWCNT TFT shows linear temperature dependent transconductances and threshold voltages for both p- and n-regions. The strong temperature dependent transconductances (0.08 ?S/K for p-region, 0.4 ?S/K for n-region) indicate their potential application in thermal sensors. In the other hand, the weak temperature dependent threshold voltages (-1.5 mV/K for p-region, -1.1 mV/K for n-region) reflect their excellent thermal stability. PMID:26418482

  1. High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.

    2002-01-01

    Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

  2. 406 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 4, APRIL 1999 Theory and Algorithm of Local-Refinement-

    E-print Network

    Cong, Jason "Jingsheng"

    algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact circuit board (PCB) designs. In particular, we apply the algorithm to the simultaneous transistor

  3. Integrating AlGaN/GaN high electron mobility transistor with Si: A comparative study of integration schemes

    NASA Astrophysics Data System (ADS)

    Mohan, Nagaboopathy; Singh, Manikant; Soman, Rohith; Raghavan, Srinivasan

    2015-10-01

    AlGaN/GaN high electron mobility transistor stacks deposited on a single growth platform are used to compare the most common transition, AlN to GaN, schemes used for integrating GaN with Si. The efficiency of these transitions based on linearly graded, step graded, interlayer, and superlattice schemes on dislocation density reduction, stress management, surface roughness, and eventually mobility of the 2D-gas are evaluated. In a 500 nm GaN probe layer deposited, all of these transitions result in total transmission electron microscopy measured dislocations densities of 1 to 3 × 109/cm2 and <1 nm surface roughness. The 2-D electron gas channels formed at an AlGaN-1 nm AlN/GaN interface deposited on this GaN probe layer all have mobilities of 1600-1900 cm2/V s at a carrier concentration of 0.7-0.9 × 1013/cm2. Compressive stress and changes in composition in GaN rich regions of the AlN-GaN transition are the most effective at reducing dislocation density. Amongst all the transitions studied the step graded transition is the one that helps to implement this feature of GaN integration in the simplest and most consistent manner.

  4. Cell Transformations and Physical Design Techniques for 3D Monolithic Integrated Circuits

    E-print Network

    De Micheli, Giovanni

    19 Cell Transformations and Physical Design Techniques for 3D Monolithic Integrated Circuits´ed´erale de Lausanne (EPFL) 3D Monolithic Integration (3DMI), also termed as sequential integration, Performance Additional Key Words and Phrases: 3D integration, 3D monolithic, cell transformation techniques

  5. Broad Beam and Ion Microprobe Studies of Single-Event Upsets in High Speed 0.18micron Silicon Germanium Heterojunction Bipolar Transistors and Circuits

    NASA Technical Reports Server (NTRS)

    Reed, Robert A.; Marshall, Paul W.; Pickel, Jim; Carts, Martin A.; Irwin, TIm; Niu, Guofu; Cressler, John; Krithivasan, Ramkumar; Fritz, Karl; Riggs, Pam

    2003-01-01

    SiGe based technology is widely recognized for its tremendous potential to impact the high speed microelectronic industry, and therefore the space industry, by monolithic incorporation of low power complementary logic with extremely high speed SiGe Heterojunction Bipolar Transistor (HBT) logic. A variety of studies have examined the ionizing dose, displacement damage and single event characteristics, and are reported. Accessibility to SiGe through an increasing number of manufacturers adds to the importance of understanding its intrinsic radiation characteristics, and in particular the single event effect (SEE) characteristics of the high bandwidth HBT based circuits. IBM is now manufacturing in its 3rd generation of their commercial SiGe processes, and access is currently available to the first two generations (known as and 6HP) through the MOSIS shared mask services with anticipated future release of the latest (7HP) process. The 5 HP process is described and is characterized by a emitter spacing of 0.5 micron and a cutoff frequency ff of 50 GHz, whereas the fully scaled 7HP HBT employs a 0.18 micron emitter and has an fT of 120 GHz. Previous investigations have the examined SEE response of 5 HP HBT circuits through both circuit testing and modeling. Charge collection modeling studies in the 5 H P process have also been conducted, but to date no measurements have been reported of charge collection in any SiGe HBT structures. Nor have circuit models for charge collection been developed in any version other than the 5 HP HBT structure. Our investigation reports the first indications of both charge collection and circuit response in IBM s 7HP-based SiGe process. We compare broad beam heavy ion SEU test results in a fully function Pseudo-Random Number (PRN) sequence generator up to frequencies of 12 Gbps versus effective LET, and also report proton test results in the same circuit. In addition, we examine the charge collection characteristics of individual 7HP HBT structures and map out the spatial sensitivities using the Sandia Focused Heavy Ion Microprobe Facility s Ion Beam Induced Charge Collection (IBICC) technique. Combining the two data sets offers insights into the charge collection mechanisms responsible for circuit level response and provides the first insights into the SEE characteristics of this latest version of IBM s commercial SiGe process.

  6. PAMM Proc. Appl. Math. Mech. 11, 783 784 (2011) / DOI 10.1002/pamm.201110380 Variational integrators for electric circuits

    E-print Network

    Ober-Blöbaum, Sina

    2011-01-01

    integrators for electric circuits Sina Ober-Blöbaum1, , Molei Tao2, , and Houman Owhadi2, 1 Computational of mechanical systems. In this work, we develop a variational integrator for the simulation of electric circuits for the simulation of the electric circuit. In this way, a variational integrator is constructed that gains several

  7. Analog Integrated Circuits and Signal Processing, 46, 275280, 2006 c 2006 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

    E-print Network

    Dudek, Piotr

    Analog Integrated Circuits and Signal Processing, 46, 275­280, 2006 c 2006 Springer Science + Business Media, Inc. Manufactured in The Netherlands. Integrated Circuit Implementation of a Compact, random noise generator 1. Introduction Integrated circuit implementations of non-linear deter

  8. Analog Integrated Circuits and Signal Processing, 24, 213229, 2000 # 2000 Kluwer Academic Publishers. Manufactured in The Netherlands.

    E-print Network

    Koch, Christof

    Analog Integrated Circuits and Signal Processing, 24, 213±229, 2000 # 2000 Kluwer Academic a Reichardt motion sensor with integrated photodetectors in a standard CMOS process. Our circuit operates of substrate and component variability both within and between integrated circuits; and external robustness

  9. Analog Integrated Circuits and Signal Processing, 22, 107109 (2000) # 2000 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

    E-print Network

    Serdijn, Wouter A.

    2000-01-01

    Analog Integrated Circuits and Signal Processing, 22, 107±109 (2000) # 2000 Kluwer Academic, which was treated previously in Vol. 9, No. 2 of Analog Integrated Circuits and Signal Processing and theoretical interest, this Special Issue of Analog Integrated Circuits and Signal Processing on Dynamic

  10. Low-voltage polymer/small-molecule blend organic thin-film transistors and circuits fabricated via spray deposition

    SciTech Connect

    Hunter, By Simon; Anthopoulos, Thomas D.; Ward, Jeremy W.; Jurchescu, Oana D.; Payne, Marcia M.; Anthony, John E.

    2015-06-01

    Organic thin-film electronics have long been considered an enticing candidate in achieving high-throughput manufacturing of low-power ubiquitous electronics. However, to achieve this goal, more work is required to reduce operating voltages and develop suitable mass-manufacture techniques. Here, we demonstrate low-voltage spray-cast organic thin-film transistors based on a semiconductor blend of 2,8-difluoro- 5,11-bis (triethylsilylethynyl) anthradithiophene and poly(triarylamine). Both semiconductor and dielectric films are deposited via successive spray deposition in ambient conditions (air with 40%–60% relative humidity) without any special precautions. Despite the simplicity of the deposition method, p-channel transistors with hole mobilities of >1?cm{sup 2}/Vs are realized at ?4?V operation, and unipolar inverters operating at ?6?V are demonstrated.

  11. Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

    PubMed

    Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

    2012-01-01

    The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

  12. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    NASA Technical Reports Server (NTRS)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful performance of experimental, proof-of-concept MMIC K/Ka-band arrays developed with U.S. industry in field demonstrations with ACTS indicates that high density MMIC integration at 20 and 30 GHz is indeed feasible. The successful development and demonstration of the MMIC array systems was possible only because of significant intergovernmental and Government/industry cooperation and the high level of teamwork within Lewis. The results provide a strong incentive for continuing the focused development of MMIC-array technology for satellite communications applications, with emphasis on packaging and cost issues, and for continuing the planning and conducting of other appropriate demonstrations or experiments of phased-array technology with ACTS. Given the present pressures on reducing funding for research and development in Government and industry, the extent to which this can be continued in a cooperative manner will determine whether MMIC array technology will make the transition from the proof-of-concept level to the operational system level.

  13. Laser Micromachining of Active and Passive Photonic Integrated Circuits

    E-print Network

    Cho, Seong-Ho

    2006-06-28

    This thesis describes the development of advanced laser resonators and applications of laserinduced micromachining for photonic circuit fabrication. Two major advantages of laserinduced micromachining are direct patterning ...

  14. Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

    PubMed Central

    Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

  15. Miniaturized ultrasound imaging probes enabled by CMUT arrays with integrated frontend electronic circuits.

    PubMed

    Khuri-Yakub, B T; Oralkan, Omer; Nikoozadeh, Amin; Wygant, Ira O; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O'Donnell, Matthew; Truong, Uyen; Sahn, David J

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

  16. PETRIC - A positron emission tomography readout integrated circuit

    SciTech Connect

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  17. Scheduling revisited workstations in integrated-circuit fabrication

    NASA Technical Reports Server (NTRS)

    Kline, Paul J.

    1992-01-01

    The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

  18. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  19. Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment

    NASA Technical Reports Server (NTRS)

    Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

    1998-01-01

    Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

  20. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 1775 Transforming Cyclic Circuits Into

    E-print Network

    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 1775 Transforming Cyclic Circuits Into Acyclic Equivalents Osama Neiroukh, Stephen A. Edwards tools can intro- duce unwanted cycles in digital circuits, and for certain com- binational functions

  1. 436 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 3, MARCH 2008 Quantum Circuit Simplification and

    E-print Network

    Miller, D. Michael

    436 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 3, MARCH 2008 Quantum Circuit Simplification and Level Compaction Dmitri Maslov, Gerhard W. Dueck, Member, IEEE, D. Michael Miller, Member, IEEE, and Camille Negrevergne Abstract--Quantum circuits are time

  2. Device and Circuit Modeling and Development of a Non-Volatile Random Access Memory Cell, Utilizing AN Amorphous Silicon Thin-Film Floating-Gate Transistor Based Technology.

    NASA Astrophysics Data System (ADS)

    Riggio, Salvatore Richard, Jr.

    1994-01-01

    High density storage mechanisms are generally created using either magnetic or optical implementation techniques. Both of these techniques require mechanical transport of the medium and, therefore, have low reliability factors. These devices also generate unwanted low level ambient noise, which is of particular concern when considering modern quiet office standards. Additionally, optical techniques tend to be read-only in nature. Both mechanisms exhibit random access times that are measured in milli-seconds, rather than in micro-seconds. Therefore, the creation of a non-volatile random access memory as a replacement for the above mentioned storage techniques would be of great advantage in terms of access time, reliability, and ambient noise level. Described within are the device and circuit modeling and fabrication techniques used to develop a non-volatile random access memory cell from an amorphous silicon thin -film transistor based technology. Amorphous silicon thin-film transistors are fabricated by depositing the metal, the insulator and the semiconductor materials with a sputtering mechanism in a vacuum at 220 degrees centigrade, rather than by diffusion at 2000 degrees centigrade, as is done with crystalline silicon. By depositing a metal in the insulator, which is located between the gate and the channel, and by using an insulator material with extremely high resistivity, one can store charge in the gate region for a long period of time without external power. For example, this period of time can be as little as one week or as long as over one year. With a periodic refresh, one can extend the memory time of this storage mechanism indefinitely. Thin-film transistors can be deposited on a variety of materials such as glass, quartz or plastic by means of a stationary or continuous motion fabrication system. This material can be either rigid or flexible, and can be comparatively large in size. This allows for much greater circuit density than a standard crystalline silicon chip that contains devices of a comparable channel length. Ten-thousand mega bytes, or more, of virtual storage could become common place. In summary, this approach represents a large scale, high density, high speed "non-volatile" storage device, with read-write random access capability, without moving parts.

  3. Method for producing a hybridization of detector array and integrated circuit for readout

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (inventor); Grunthaner, Frank J. (inventor)

    1993-01-01

    A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

  4. Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

    PubMed

    Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

    2013-08-21

    For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (?) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of ? ? 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. PMID:23761043

  5. 75 FR 49524 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-13

    ... Semiconductor of Austin, Texas (``Freescale''). 75 FR 16837-38. The complaint alleges violations of section 337... In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... circuits, chipsets, and products containing same including televisions, media players, and cameras...

  6. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    ERIC Educational Resources Information Center

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  7. Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics

    E-print Network

    Chung, Jinwook W. (Jinwook Will)

    2011-01-01

    In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. ...

  8. A correlated nickelate synaptic transistor

    NASA Astrophysics Data System (ADS)

    Shi, Jian; Ha, Sieu D.; Zhou, You; Schoofs, Frank; Ramanathan, Shriram

    2013-10-01

    Inspired by biological neural systems, neuromorphic devices may open up new computing paradigms to explore cognition, learning and limits of parallel computation. Here we report the demonstration of a synaptic transistor with SmNiO3, a correlated electron system with insulator-metal transition temperature at 130°C in bulk form. Non-volatile resistance and synaptic multilevel analogue states are demonstrated by control over composition in ionic liquid-gated devices on silicon platforms. The extent of the resistance modulation can be dramatically controlled by the film microstructure. By simulating the time difference between postneuron and preneuron spikes as the input parameter of a gate bias voltage pulse, synaptic spike-timing-dependent plasticity learning behaviour is realized. The extreme sensitivity of electrical properties to defects in correlated oxides may make them a particularly suitable class of materials to realize artificial biological circuits that can be operated at and above room temperature and seamlessly integrated into conventional electronic circuits.

  9. Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

    E-print Network

    Fariborzi, Hossein

    2013-01-01

    Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade ...

  10. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    ERIC Educational Resources Information Center

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  11. On-chip spectrum/vector analyzer for built-in testing of analog integrated circuits 

    E-print Network

    Mendez Rivera, Marcia Gisela

    2002-01-01

    The number of functions that can be integrated on a single chip has increased during the last years, making the functional testing of circuits a challenging task. Even though the digital testing has reached certain maturity and well...

  12. Design and testing of a sensorless switched reluctance motor drive with a custom integrated circuit controller 

    E-print Network

    Zhang, Yingxia

    1996-01-01

    section circuits of an SRM drive integratable will make a large contribution to the SRM's acceptability by relieving design and application engineers of the burden of designing controls. Ile objective of this research is to develop an integrated control...

  13. Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

    E-print Network

    Leong, Hoi Liong

    Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures ...

  14. A statistical optimization methodology for practical integrated circuit design for quality and manufacturability 

    E-print Network

    Pastor, Curtis Lemay

    1997-01-01

    .This thesis addresses some of the problems encountered in Statistical Design of Analog Integrated Circuits (ICs). The objective is to develop a methodology to optimize an industrial operational amplifier (OpAmp) for improved performance and reduced...

  15. Demonstration of Integrated Mico-Electro-Mechanical Switch Circuits for VLSI Applications

    E-print Network

    Stojanovic, Vladimir Marko

    A testchip demonstrates monolithic integration of micro-electro-mechanical (MEM) switch circuit building blocks for logic, timing, I/O and memory functions. Experimental results show functionality for an inverter, XOR, ...

  16. Methodologies for statistical behavioral modeling and simulation of complex analog integrated circuits 

    E-print Network

    Swidzinski, Jan

    1997-01-01

    The objective of this thesis is to develop efficient methodologies for statistical behavioral modeling of analog integrated circuits and apply them to practical problems. Through appropriate statistical modeling, the Design for Quality (DFQ...

  17. GeSi photodetectors and electro-absorption modulators for Si electronic-photonic integrated circuits

    E-print Network

    Liu, Jifeng, Ph. D. Massachusetts Institute of Technology

    2007-01-01

    The silicon electronic-photonic integrated circuit (EPIC) has emerged as a promising technology to break through the interconnect bottlenecks in telecommunications and on-chip interconnects. High performance photonic ...

  18. Genetically Increased Cell-Intrinsic Excitability Enhances Neuronal Integration into Adult Brain Circuits

    E-print Network

    Lin, Chia-Wei

    New neurons are added to the adult brain throughout life, but only half ultimately integrate into existing circuits. Sensory experience is an important regulator of the selection of new neurons but it remains unknown whether ...

  19. Characterization and modeling of plasma etch pattern dependencies in integrated circuits

    E-print Network

    Abrokwah, Kwaku O

    2006-01-01

    A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent ...

  20. High-speed silicon electro-optic modulator for electronic photonic integrated circuits

    E-print Network

    Gan, Fuwan

    2007-01-01

    The development of future electronic-photonic integrated circuits (EPIC) based on silicon technology critically depends on the availability of CMOS-compatible high-speed modulators that enable the interaction of electronic ...

  1. The development of an uncommitted integrated circuit for combined digital and analogue applications

    NASA Astrophysics Data System (ADS)

    Kemp, A. J.

    1982-06-01

    An uncommmited integrated circuit is a standardized integrated circuit needing only a fraction of the normal processing steps to program it for a required application. The result is a reduction in the time, money and knowledge required to develop an integrated circuit. The development and industrialization of an uncommitted circuit for combined digital and analog applications are described. Integrated Injection Logic (I2L) is used to realize digital functions, and standard analog techniques, based on a bipolar process, are used to realize analog functions. A novel architecture, as well as the use of three masks to realize a required interconnection pattern, results in a very high efficiency in terms of the number of components that was used.

  2. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    DOEpatents

    Schwank, James R. (Albuquerque, NM); Shaneyfelt, Marty R. (Albuquerque, NM); Draper, Bruce L. (Albuquerque, NM); Dodd, Paul E. (Tijeras, NM)

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  3. Design of a semi-custom integrated circuit for the SLAC SLC timing control system

    SciTech Connect

    Linstadt, E.

    1984-10-01

    A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given.

  4. Evaluation of high temperature accelerated aging tests used on integrated circuits

    NASA Astrophysics Data System (ADS)

    Gracey, J. P.

    1986-04-01

    Accelerated aging tests such as high temperature burn-in, which are in current use on Bendix Kansas City Division's (BKC) purchased small and medium scale integrated circuits, were evaluated to determine if they are effective and necessary to ensure the required reliability. A theoretical analysis, a literature search, and a study of lot acceptance results were used to assess the value of integrated circuit burn-in.

  5. Laser micromachining of active and passive photonic integrated circuits

    E-print Network

    Cho, Seong-Ho, 1966-

    2004-01-01

    This thesis describes the development of advanced laser resonators and applications of laser-induced micromachining for photonic circuit fabrication. Two major advantages of laser-induced micromachining are direct patterning ...

  6. CARBON NANOTUBE TRANSISTORS: AN EVALUATION

    E-print Network

    Pulfrey, David L.

    -effect transistors. It is shown that, by appropriate work function engineering of the source, drain and gate contacts transistors and interconnects.1 Such circuits would be of a different form from that of today's silicon by atomic force microscopy,12 but recent reports of covalent chemical functionalization could make this task

  7. Planarization techniques for vertically integrated metallic MEMS on silicon foundry circuits

    NASA Astrophysics Data System (ADS)

    Lee, J.-B.; English, J.; Ahn, C.-H.; Allen, M. G.

    1997-06-01

    Various micromachining techniques exist to realize integrated microelectromechanical systems (MEMS), which include sensors, signal processing and/or driving circuits, and/or actuators in one small die. Post-processing techniques performed on foundry-fabricated circuits (e.g., MOSIS) are attractive since such an approach eliminates the need for an in-house integrated circuit fabrication line to produce integrated MEMS. A method based on the combination of metallic (e.g., electroplating) micromachining techniques with multichip module deposited (MCM-D) processes is a possible candidate to realize vertically-stacked integrated MEMS using the post-processing of integrated circuits (post-IC) approach. In order to realize such devices, planarization of the surface of foundry-fabricated circuit chips or wafers is often required. In such planarization layers, mechanical and chemical stability, as well as adhesion between the circuit-containing substrate and the micromachined devices, should be addressed. A PI/BCB/PI sandwich interlayer system, which utilizes both advantages of DuPont polyimide PI 2611 and Dow benzocyclobutene (BCB) Cyclotene 3022 series, was developed as a planarization interlayer for vertically integrated MEMS. The PI/BCB/PI interlayer system shows an over 95% degree of planarization (DOP) as well as passes the Method 107G Thermal Shock from the military standard MIL-STD-202F. A 0960-1317/7/2/002/img7 interlayer system was also developed as an alternative to the PI/BCB/PI system.

  8. V-band low-noise integrated circuit receiver. [for space communication systems

    NASA Technical Reports Server (NTRS)

    Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

    1983-01-01

    A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

  9. Models for Examining Impact of Cosmic Rays on Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Atkinson, William; William J Atkinson Collaboration

    2015-04-01

    The Soft Error Rate (SER) produced by SEUs in microelectronic devices in near-earth orbits and in the atmosphere has been computed using a common model developed at Boeing, TSAREME. In space, TSAREME models protons, alphas, and heavy ions with atomic numbers up to 26 (iron) for GCR and peak solar flares. In the atmosphere, TSAREME computes the neutron flux fluxes produced by charged particles interacting with air molecules, accounting for magnetosphere variations with latitude. The devices include Complementary Metal on Oxide (CMOS) and Silicon on Insulator (SOI) transistors with feature sizes varying from a micron to 15 nm. Validation of model results to empirical data discussed.

  10. Advancements in bipolar VLSI circuits and technologies

    NASA Astrophysics Data System (ADS)

    Wiedmann, S. K.

    1984-06-01

    This paper gives an overview on bipolar circuit/device techniques for VLSI logic and memories. Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are still mainly applied, but also new circuit technologies such as integrated injection logic or merged transistor logic (I2L/MTL) and Schottky transistor logic (STL) or integrated Schottky logic (ISL) have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected by technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 micron dimensions or below. Some experimental data and projections indicate the strong potentials of bipolar VLSI.

  11. Solder Bonding for Power Transistors

    NASA Technical Reports Server (NTRS)

    Snytsheuvel, H. A.; Mandel, H.

    1985-01-01

    Indium solder boosts power rating and facilitates circuit changes. Efficient heat conduction from power transistor to heat sink provided by layer of indium solder. Low melting point of indium solder (141 degrees C) allows power transistor to be removed, if circuit must be reworked, without disturbing other components mounted with ordinary solder that melts at 181 degrees C. Solder allows devices operated at higher power levels than does conventional attachment by screws.

  12. Process development of beam-lead silicon-gate COS/MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Baptiste, B.; Boesenberg, W.

    1974-01-01

    Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

  13. The stabilized supralinear network: a unifying circuit motif underlying multi-input integration in sensory cortex.

    PubMed

    Rubin, Daniel B; Van Hooser, Stephen D; Miller, Kenneth D

    2015-01-21

    Neurons in sensory cortex integrate multiple influences to parse objects and support perception. Across multiple cortical areas, integration is characterized by two neuronal response properties: (1) surround suppression--modulatory contextual stimuli suppress responses to driving stimuli; and (2) "normalization"--responses to multiple driving stimuli add sublinearly. These depend on input strength: for weak driving stimuli, contextual influences facilitate or more weakly suppress and summation becomes linear or supralinear. Understanding the circuit operations underlying integration is critical to understanding cortical function and disease. We present a simple, general theory. A wealth of integrative properties, including the above, emerge robustly from four cortical circuit properties: (1) supralinear neuronal input/output functions; (2) sufficiently strong recurrent excitation; (3) feedback inhibition; and (4) simple spatial properties of intracortical connections. Integrative properties emerge dynamically as circuit properties, with excitatory and inhibitory neurons showing similar behaviors. In new recordings in visual cortex, we confirm key model predictions. PMID:25611511

  14. Self-protecting transistor oscillator for treating animal tissues

    DOEpatents

    Doss, James D. (Los Alamos, NM)

    1980-01-01

    A transistor oscillator circuit wherein the load current applied to animal tissue treatment electrodes is fed back to the transistor. Removal of load is sensed to automatically remove feedback and stop oscillations. A thermistor on one treatment electrode senses temperature, and by means of a control circuit controls oscillator transistor current.

  15. Active parallel redundancy for electronic integrator-type control circuits

    NASA Technical Reports Server (NTRS)

    Peterson, R. A.

    1971-01-01

    Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

  16. Deformable interconnects for conformal integrated circuits Stphanie Prichon Lacour1

    E-print Network

    Huang, Zhenyu

    and analyzed during tensile deformation. For a 100-nm thick gold layer evaporated on a 1-mm thick silicone with the flexibility of plastic substrates. Once circuits are fabricated onto a deformable substrate, stretchable that the Au layers remain electrically conducting up to large tensile deformation (~ 22%). THEORY Complex wave

  17. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G. (inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  18. Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

    NASA Technical Reports Server (NTRS)

    Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

    1981-01-01

    Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

  19. Integrated Printed Circuit Board Device for Cell Lysis and Nucleic Acid Extraction

    E-print Network

    Santiago, Juan G.

    Integrated Printed Circuit Board Device for Cell Lysis and Nucleic Acid Extraction Lewis A and an isotachophoresis assay for sample preparation of nucleic acids from biological samples. The device has integrated two 15 L reservoirs. We demonstrated this device by extracting pathogenic nucleic acids from 1 L

  20. A Fully Integrated Multi-channel Impedance Extraction Circuit for Biosensor Arrays

    E-print Network

    Mason, Andrew

    A Fully Integrated Multi-channel Impedance Extraction Circuit for Biosensor Arrays Xiaowen Liu biosensors that utilize a combination of electrochemical reactions and electronic instrumentation are promising candidates for the next generation of integrated biosensors. They are well suited to characterize

  1. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-02-04

    ... December 24, 2008, based on a complaint filed by Qimonda AG of Munich, Germany (``Qimonda''). 73 FR 79165... In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice of... importation, and sale within the United States after importation of certain semiconductor integrated...

  2. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-04

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain semiconductor integrated... (``Microchip''). 77 FR 25747-48 (May 1, 2012). The complaint alleges violations of section 337 of the...

  3. A Monolithic InP-based Photonic Integrated Circuit for Optical Arbitrary Waveform Generation

    E-print Network

    Yoo, S. J. Ben

    A Monolithic InP-based Photonic Integrated Circuit for Optical Arbitrary Waveform Generation W demonstrate a compact monolithically-integrated InP optical arbitrary waveform generator, consisting the feasibility of OAWG has been demonstrated in a free-space optical platform [1], monolithic chip

  4. A Pre-Search Assisted ILP Approach to Analog Integrated Circuit Routing 

    E-print Network

    Wu, Chia-Yu

    2015-07-06

    .6 Number of variables and constraints impact of the number of candi- date routes for OP2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vii 1. INTRODUCTION 1.1 Physical Layout Design in Analog Circuit Nowadays, analog integrated circuits (IC...) design is still mostly a manual process, which is typically very time consuming. A key reason is that it involves a large amount of constraints, which are hard to capture, and makes automated design tools very difficult to be competitive. Routing...

  5. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1980-01-01

    The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

  6. Development of Liquid Crystal Display Panel Integrated with Drivers Using Amorphous In-Ga-Zn-Oxide Thin Film Transistors

    NASA Astrophysics Data System (ADS)

    Osada, Takeshi; Akimoto, Kengo; Sato, Takehisa; Ikeda, Masataka; Tsubuku, Masashi; Sakata, Junichiro; Koyama, Jun; Serikawa, Tadashi; Yamazaki, Shunpei

    2010-03-01

    We designed, prototyped, and evaluated a liquid crystal panel integrated with a gate driver and a source driver using amorphous In-Ga-Zn-oxide thin film transistors (TFTs). Using bottom-gate bottom-contact (BGBC) thin film transistors, superior characteristics could be obtained. We obtained TFT characteristics with little variation even when the thickness of the gate insulator (GI) film was reduced owing to etching of source/drain (S/D) wiring, which is a typical process for the BGBC TFT. Moreover, a favorable ON-state current was obtained even when an In-Ga-Zn-oxide layer was formed over the S/D electrode. Since the upper portion of the In-Ga-Zn-oxide layer is not etched, the BGBC structure is predicted to be effective in thinning the In-Ga-Zn-oxide layer in the future. Upon evaluation, we found that the prototyped liquid crystal panel integrated with the gate and source drivers using the TFTs with improved characteristics had stable drive.

  7. Sensory integration for reaching: models of optimality in the context of behavior and the underlying neural circuits

    E-print Network

    Sabes, Philip

    and the underlying neural circuits Philip N. Sabes Department of Physiology and Keck Center for Integrative shown how optimal integration could be instantiated in neural circuits. However, strong links have yetSensory integration for reaching: models of optimality in the context of behavior

  8. Transistor analogs of emergent iono-neuronal dynamics

    PubMed Central

    Rachmuth, Guy; Poon, Chi-Sang

    2008-01-01

    Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications. PMID:19404469

  9. InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

    NASA Technical Reports Server (NTRS)

    Radisic, Vesna; Sawdai, Donald; Scott, Dennis; Deal, William; Dang, Linh; Li, Danny; Cavus, Abdullah; To, Richard; Lai, Richard

    2009-01-01

    Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

  10. A UNIVERSAL SOI-BASED HIGH TEMPERATURE GATE DRIVER INTEGRATED CIRCUIT FOR SIC POWER SWITCHES WITH ON-CHIP SHORT CIRCUIT PROTECTION

    E-print Network

    Tolbert, Leon M.

    A UNIVERSAL SOI-BASED HIGH TEMPERATURE GATE DRIVER INTEGRATED CIRCUIT FOR SIC POWER SWITCHES mechanism. This gate-driver chip can drive SiC power FETs of the DC-DC converters in a HEV, and future chip for the power electronics module. Keyword: SiC, BCD-on-SOI, high-voltage, gate-driver, short-circuit protection

  11. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2011 2095 Linear and Switch-Mode Conversion in 3-D Circuits

    E-print Network

    Friedman, Eby G.

    .5 V and 1 V with, respectively, 74% and 44% power efficiency. Index Terms--3-D integrated circuits, DC complexity circuits, an emerging three-dimensional (3-D) integrated circuit technology is under development [3]. In a 3-D technology, indi- vidual planes of 2-D integrated circuits are combined into 3-D cubes

  12. Tunnel field-effect transistors as energy-efficient electronic switches.

    PubMed

    Ionescu, Adrian M; Riel, Heike

    2011-11-17

    Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits. PMID:22094693

  13. Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

    NASA Technical Reports Server (NTRS)

    Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

    1981-01-01

    Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

  14. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  15. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

    2008-07-29

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  16. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

    2008-07-08

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  17. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A. (Croton-on-Hudson, NY); Crumley, Paul G. (Yorktown Heights, NY); Dombrowa, Marc B. (Bronx, NY); Douskey, Steven M. (Rochester, MN); Haring, Rudolf A. (Cortlandt Manor, NY); Oakland, Steven F. (Colchester, VT); Ouellette, Michael R. (Westford, VT); Strissel, Scott A. (Byron, MN)

    2007-12-18

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  18. System-Level Integrated Circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  19. Analog Integrated Circuits and Signal Processing, 43, 281296, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

    E-print Network

    Maryland at College Park, University of

    Analog Integrated Circuits and Signal Processing, 43, 281­296, 2005 c 2005 Springer Science with modern digital CMOS technologies and is readily extended to novel circuit applications. We highlight). This is the first use of this technique for adaptation in a nonlinear circuit. The AFGC computes appropriate

  20. Apoptotic self-organized electronic device using thin-film transistors for artificial neural networks with unsupervised learning functions

    NASA Astrophysics Data System (ADS)

    Kimura, Mutsumi; Miyatani, Tomoaki; Fujita, Yusuke; Kasakawa, Tomohiro

    2015-03-01

    Artificial neural networks are promising systems for information processing with many advantages, such as self-teaching and parallel distributed computing. However, conventional networks consist of extremely intricate circuits to guarantee accurate behaviors of the neurons and synapses. We demonstrate an apoptotic self-organized electronic device using thin-film transistors for artificial neural networks with unsupervised learning functions. First, we formed a “neuron” from only eight transistors and reduced a “synapse” to only one transistor by employing the characteristic degradations of the synapse transistors to adjust the synaptic connection strength. Second, we classified the synapses into two types, “concordant” and “discordant” synapses, and composed a local interconnective network optimized for integrated electronic circuits. Finally, we confirmed that the device is feasible and can learn multiple logical operations, including AND, OR, and XOR.